Multilayer ceramic capacitor

Abstract

Provided is a multilayer ceramic capacitor provided with an external electrode having a base electrode layer in which the surface is reliably covered with a plated layer.　A multilayer ceramic capacitor 1 has: a laminate 2 in which dielectric layers 4 and internal electrode layers 5 are alternately layered; and external electrodes 3 which are respectively disposed on end surfaces C of the laminate 2 on both sides in a length direction L orthogonal to the layering direction T and which are connected to the internal electrode layers 5. Each of the external electrodes 3 is provided with a region R in which a base electrode layer 30 disposed on an end surface C, a Ni plated layer 31a disposed on the base electrode layer 30, and a Sn plated layer 31b disposed on the Ni plated layer 31a are layered, and in which Sn is deposited between the base electrode layer 30 and the Ni plated layer 31a.

Description

Technical Field

[0001] The present invention relates to a multilayer ceramic capacitor.

Background Art

[0002] Conventionally, in a multilayer ceramic capacitor, in order to be mounted on a wiring board, an external electrode that conducts with the internal electrode layer is provided on the surface of a ceramic body incorporating an internal electrode layer. The external electrode usually includes a base electrode layer containing a conductive metal and glass, but in order to prevent erosion by solder used when mounting to an electric circuit, the surface of the base electrode layer is covered with a Ni plating layer and further with a Sn plating layer.

[0003] Generally, an electrolytic plating method is used for forming the plating layer. In the electrolytic plating method, a plating film is deposited and grown with the conductive metal exposed on the surface of the base electrode layer as nuclei, and thus the plating layer is formed so as to cover the base electrode layer. However, if the deposited plating film is non-uniform, a uniform plating layer cannot be formed, and when mounted on a wiring board, the laminate is damaged due to solder erosion, leading to a failure of the multilayer ceramic capacitor.

[0004] On the other hand, it is also conceivable to form a thicker plating film in order to improve the film-forming property of the plating film. However, an increase in current in electrolytic plating or an extension of the electrolytic plating treatment time tends to cause variations in the thickness of the plating layer in mass production, making it difficult to maintain a constant quality. Also, in order to keep the dimensions of the multilayer ceramic capacitor within the standard dimensions, it is necessary to further reduce the thickness of the ceramic body by the amount of the thicker plating film formed. As a result, since the ceramic body is further thinned, a decrease in the capacitance of the multilayer ceramic capacitor becomes a problem.

[0005] Therefore, there is a demand for the development of a multilayer ceramic capacitor provided with an external electrode formed by reliably covering the surface of the base electrode layer with a plating layer.

Prior Art Documents

Patent Documents

[0006] [Patent Document 1] Japanese Patent Application Publication No. 8-102425 [Overview of the project] [Problems that the invention aims to solve]

[0007] The present invention aims to provide a multilayer ceramic capacitor equipped with an external electrode formed by reliably coating the surface of a base electrode layer with a plating layer. [Means for solving the problem]

[0008] The inventors of the present invention have discovered that by providing a region where Sn is deposited on the surface of the underlying electrode layer constituting the external electrode, the deposition and growth of the plating film proceed smoothly, and have completed the present invention.

[0009] In other words, the present invention relates to a multilayer ceramic capacitor having a laminate in which dielectric layers and internal electrode layers are alternately stacked, and external electrodes arranged on both end faces in the longitudinal direction perpendicular to the stacking direction of the laminate and connected to the internal electrode layers, The external electrode comprises a base electrode layer placed on the end face, A Ni plating layer is placed on the aforementioned under electrode layer, A Sn plating layer is placed on the Ni plating layer, This is a multilayer ceramic capacitor in which layers are stacked, and a region in which Sn is deposited between the base electrode layer and the Ni plating layer. [Effects of the Invention]

[0010] According to the present invention, it is possible to provide a multilayer ceramic capacitor equipped with an external electrode formed by reliably covering the surface of the underlying electrode layer with a plating layer. [Brief explanation of the drawing]

[0011] [Figure 1] This is a schematic perspective view of the multilayer ceramic capacitor 1. [Figure 2] Figure 1 is a cross-sectional view of the multilayer ceramic capacitor 1 along the line II-II. [Figure 3] Figure 1 is a cross-sectional view of the multilayer ceramic capacitor 1 along the line III-III. [Figure 4] This is a flowchart illustrating the manufacturing method of the multilayer ceramic capacitor 1. [Figure 5] This figure shows the cross-sectional state of the external electrode 3 as observed by an electron microscope. [Modes for carrying out the invention]

[0012] The following describes a multilayer ceramic capacitor according to an embodiment of the present invention, but the present invention is not limited thereto. Furthermore, the drawings may be schematically simplified to illustrate the content of the invention, and the ratios of dimensions of the depicted components or between components may not match the ratios of those dimensions described in the specification. Also, components described in the specification may be omitted in the drawings, or their quantities may be omitted.

[0013] (Multilayer ceramic capacitor 1) Figures 1 to 3 show the shape and structure of the multilayer ceramic capacitor 1. Figure 1 is a schematic perspective view of the multilayer ceramic capacitor 1. Figure 2 is a cross-sectional view (LT cross-section) of the multilayer ceramic capacitor 1 cut along the line II-II in the center of the width direction W shown in Figure 1. Figure 3 is a cross-sectional view (WT cross-section) of the multilayer ceramic capacitor 1 along the line III-III in Figure 1. Figure 4 is a flowchart explaining the manufacturing method of the multilayer ceramic capacitor 1. Figure 5 shows the cross-sectional state of the external electrode 3 as observed by an electron microscope. The stacking direction T is defined as the direction in which the dielectric layer and the internal electrode layer are stacked, and the structure of the multilayer ceramic capacitor 1 is described using the length direction L, which is perpendicular to the stacking direction T, and the width direction W, which is perpendicular to both the stacking direction T and the length direction L. In this embodiment, the width direction W, the length direction L, and the stacking direction T are orthogonal to each other, but they are not necessarily orthogonal to each other and may intersect with each other.

[0014] The multilayer ceramic capacitor 1 has a substantially rectangular parallelepiped shape and comprises a laminate 2 and a pair of external electrodes 3 provided at both ends of the laminate 2. The laminate 2 includes an inner layer portion 6 which comprises multiple sets of dielectric layers 4 and internal electrode layers 5.

[0015] Furthermore, of the six outer surfaces of the laminate 2, the pair of outer surfaces facing the lamination direction T are designated as the first main surface A1 and the second main surface A2, the pair of outer surfaces facing the width direction W are designated as the first side surface B1 and the second side surface B2, and the pair of outer surfaces facing the length direction L are designated as the first end surface C1 and the second end surface C2.

[0016] Furthermore, when there is no need to distinguish between the first main surface A1 and the second main surface A2, they will be collectively referred to as main surface A; when there is no need to distinguish between the first side surface B1 and the second side surface B2, they will be collectively referred to as side surface B; and when there is no need to distinguish between the first end surface C1 and the second end surface C2, they will be collectively referred to as end surface C.

[0017] (Laminate 2) The laminate 2 includes an inner layer portion 6, an outer layer portion 7 disposed on the main surface A side of the inner layer portion 6, and a side gap portion 8. The laminate 2 is preferably rounded at the ridge line portion E. The ridge line portion E is a portion where two surfaces of the laminate 2, that is, the main surface A and the side surface B, the main surface A and the end surface C, or the side surface B and the end surface C intersect, and includes the corner portion where the main surface A, the side surface B, and the end surface C intersect.

[0018] (Inner layer portion 6) The inner layer portion 6 includes a plurality of sets of dielectric layers 4 and internal electrode layers 5 laminated alternately along the lamination direction T.

[0019] (Dielectric layer 4) The dielectric layer 4 is formed of a ceramic material. As the ceramic material, for example, a dielectric ceramic mainly composed of BaTiO3 is used. Further, as the ceramic material, a material obtained by adding at least one of sub-components such as Mn compounds, Fe compounds, Cr compounds, Co compounds, Ni compounds, etc. to these main components may be used.

[0020] (Internal electrode layer 5) The internal electrode layer 5 is preferably formed of a metal material typified by, for example, Ni, Cu, Ag, Pd, Ag-Pd alloy, Au, etc.

[0021] The internal electrode layer 5 includes a plurality of first internal electrode layers 5A and a plurality of second internal electrode layers 5B. The first internal electrode layer 5A and the second internal electrode layer 5B are arranged alternately. When there is no need to particularly distinguish and explain the first internal electrode layer 5A and the second internal electrode layer 5B, they are collectively described as the internal electrode layer 5.

[0022] The internal electrode layer 5 comprises opposing portions 52 that face each other between the first internal electrode layer 5A and the second internal electrode layer 5B, and leading portions 51 that do not face each other between the first internal electrode layer 5A and the second internal electrode layer 5B, but are drawn out from the opposing portions 52 toward one end face C. The ends of the leading portions 51 are exposed to the end face C and are electrically connected to the external electrode 3. The direction in which the leading portions 51 extend differs between the first internal electrode layer 5A and the second internal electrode layer 5B, and they are drawn out alternately toward the first end face C1 and the second end face C2. Charge is accumulated between the opposing portions 52 of the first internal electrode layer 5A and the second internal electrode layer 5B that are adjacent in the stacking direction T, and they function as a capacitor.

[0023] (Outer layer part 7) The outer layer 7 is positioned on both main surface A sides of the inner layer 6 and is made of the same material as the dielectric layer 4 of the inner layer 6.

[0024] (Side gap section 8) The side gap portions 8 are provided on both sides B of the inner layer portion 6 in the laminate 2. The side gap portions 8 are integrally formed from the same material as the dielectric layer 4.

[0025] (External electrode 3) The external electrodes 3 are provided on both end faces C of the laminate 2. The external electrodes 3 cover not only the end faces C, but also a portion of the main surface A and the side surface B on the end face C side. The external electrodes 3 include a base electrode layer 30 and a plating layer 31 formed on the surface of the base electrode layer 30.

[0026] (Base electrode layer 30) The base electrode layer 30 is electrically connected to the end of the lead portion 51 of the internal electrode layer 5 that is exposed on the end face C. The base electrode layer preferably contains a conductive metal and either glass or ceramic, or both glass and ceramic. In this embodiment, the base electrode layer 30 contains a conductive metal and glass. This improves the adhesion between the end face C of the laminate 2 and the base electrode layer 30, and suppresses the intrusion of moisture into the interior of the laminate 2.

[0027] The conductive metal used to form the underlying electrode layer includes, for example, at least one selected from Cu, Ni, Ag, Pd, Ag-Pd alloy, Au, etc.

[0028] Furthermore, the glass forming the base electrode layer 30 contains at least one selected from B, Si, Ba, Mg, Al, Li, etc. If a ceramic component is included, the same type of ceramic component as that used in the dielectric layer may be used, or a different type of ceramic component may be used.

[0029] (Area R) A region R is formed on the surface of the conductive metal exposed on the surface of the base electrode layer 30, where Sn is deposited. Region R is formed by the deposition of Sn or an alloy of Sn and Ni by electroless plating or the like, as described later.

[0030] Figure 5 shows the cross-sectional state of the external electrode 3 as observed by electron microscopy. Region R is formed to protrude from the surface of the underlying electrode layer 30 to a height of 0.1 to 3.0 μm. Region R serves as a nucleus for forming the Ni plating layer 31a, enabling the smooth formation of the Ni plating layer 31a.

[0031] (Plating layer 31) The plating layer 31 consists of a Ni plating layer 31a, which is positioned to cover the surface and region R of the underlying electrode layer 30, and a Sn plating layer 31b, which is positioned to cover the Ni plating layer 31a. The Ni plating layer 31a consists of plating of Ni or an alloy containing Ni. The Ni plating layer 31a prevents the underlying electrode layer 30 from being corroded by solder. The Sn plating layer 31b consists of plating of Sn or an alloy containing Sn. The formation of the Sn plating layer 31b improves the solder wettability when mounting the multilayer ceramic capacitor 1 to a wiring board, thus facilitating mounting.

[0032] The molar ratio of Sn to Ni (Sn / Ni) in region R, as measured by energy-dispersive X-ray spectroscopy (EDX), is preferably between 0.2 and 0.4. By constructing region R with such a molar ratio (Sn / Ni), region R can be stably formed in mass production, and the Ni plating layer 31a can be smoothly laminated onto the surface of the base electrode layer 30.

[0033] (Method for manufacturing a multilayer ceramic capacitor 1) Next, a method for manufacturing the multilayer ceramic capacitor 1 according to the embodiment will be described. Figure 4 is a flowchart illustrating the method for manufacturing the multilayer ceramic capacitor 1. The manufacturing process for the multilayer ceramic capacitor 1 comprises a laminate manufacturing process S1, a base electrode layer formation process S2, a region R formation process S3, a Ni plating layer formation process S4, and a Sn plating layer formation process S5.

[0034] (Laminate manufacturing process S1) First, in the laminate manufacturing process S1, a material sheet is prepared in which the pattern of the internal electrode layer 5 is printed with conductive paste on a ceramic green sheet for lamination, which is formed from a ceramic slurry into a sheet. Then, multiple material sheets are stacked so that the internal electrode patterns are offset by half a pitch in the length direction between adjacent material sheets. Furthermore, a mother block component is formed by stacking ceramic green sheets for the outer layer on both sides of multiple laminated material sheets and heat-pressing them together. Multiple laminated chips are manufactured by dividing the mother block component along cutting lines corresponding to the dimensions of the laminate. The laminated chips are then barrel polished to round the corners and edges, and then fired. This causes the ceramic and metal materials contained in the laminated chips to be fired, forming a laminate 2 that includes multiple dielectric layers 4 and multiple internal electrode layers 5.

[0035] (Base electrode layer formation step S2) Next, in the base electrode layer formation step S2, a base electrode layer 30 is formed on both ends of the laminate 2. The base electrode layer 30 is formed, for example, by applying a conductive paste containing a conductive metal and glass to both ends of the laminate 2 and baking it. The base electrode layer may be formed by simultaneously baking the laminate chip and the conductive paste applied to the laminate chip, or by baking the laminate chip to obtain the laminate 2, and then applying the conductive paste to the laminate 2 and baking it. As shown in Figure 2, the base electrode layer 30 extends not only to the end faces C on both sides of the laminate 2, but also to the main surface A side, and is formed to cover a part of the end face C side of the main surface A.

[0036] (Region R formation step S3) Region R can be formed by electroless plating by immersion. The laminate 2 on which the base electrode layer 30 is formed is immersed in a plating bath, and Sn is deposited on the surface of the conductive metal exposed on the surface of the base electrode layer 30. The metal to be deposited is not limited to Sn, but may also be an alloy of Sn and Ni, etc. These metals are supplied as cation species in the plating bath. The plating bath contains both a metal salt and a reducing agent, but the action of the reducing agent added to the aqueous solution of the metal salt causes a metal layer to be deposited, covering the surface of the conductive metal exposed on the surface of the base electrode layer. Region R can also be formed by electroplating or other plating methods.

[0037] (Ni plating layer formation process S4) In the Ni plating layer formation step S3, a Ni plating layer 31a is formed so as to cover the surface of the underlying electrode layer 30 in which region R is formed. It is preferable to use an electrolytic plating method for the Ni plating layer 31a. Barrel plating can be used as the plating method.

[0038] (Sn plating layer formation process S5) Next, a tin plating layer 31b is formed to cover the tin plating layer 31a. It is preferable to use an electrolytic plating method for the tin plating layer 31b. Barrel plating can be used as the plating method.

[0039] Through the above process, a multilayer ceramic capacitor 1 is manufactured in which the external electrodes 3 are formed on the laminate 2.

[0040] Although embodiments of the present invention have been described above, the present invention is not limited to these embodiments and can be implemented in various forms without departing from the spirit of the invention. [Explanation of symbols]

[0041] 1. Multilayer ceramic capacitor 2 Laminate 3 External electrode 4. Dielectric layer 5 Internal electrode layer 6. Inner layer 7 Outer layer 30 Base electrode layer 31 Plating layer 31a Ni plating layer 31b Sn plating layer R area A Main surface A1 First Main Surface A2 2nd main surface B side B1 1st side B2 2nd side C end face C1 1st end surface C2 2nd end face

Claims

1. A multilayer ceramic capacitor comprising a laminate in which dielectric layers and internal electrode layers are alternately stacked, and external electrodes arranged on both end faces in the longitudinal direction perpendicular to the stacking direction of the laminate and connected to the internal electrode layers, The external electrode comprises a base electrode layer placed on the end face, A Ni plating layer is placed on the aforementioned base electrode layer, A Sn plating layer is placed on the Ni plating layer, The layers are stacked, and a region in which Sn is deposited between the base electrode layer and the Ni plating layer is provided. A multilayer ceramic capacitor in which the region where Sn is deposited protrudes from the surface of the underlying electrode layer at an uneven height of 0.1 μm to 3.0 μm.

2. The multilayer ceramic capacitor according to claim 1, wherein the molar ratio of Sn to Ni (Sn / Ni) in the region where Sn is deposited, as measured by energy-dispersive X-ray spectroscopy (EDX), is 0.2 or more and 0.4 or less.

3. The multilayer ceramic capacitor according to claim 1 or claim 2, wherein the region where Sn is deposited is formed continuously on the underlying electrode layer.

4. The underlying electrode layer comprises a conductive metal and glass, The multilayer ceramic capacitor according to claim 1 or claim 2, wherein the glass comprises at least one element selected from B, Ba, Mg, Al, and Li.

Images