Multilayer ceramic electronic components

Abstract

Provided is a highly reliable layered ceramic electronic component capable of preventing cracks from occurring in a laminate of layered ceramic electronic components.　A layered ceramic condenser 1 comprises an external electrode 40 which has: a first external electrode 40A having, from the bottom, a first base electrode layer 50A, a first organic layer 70A, and a first plating layer 60A; and a second external electrode 40B having, from the bottom, a second base electrode layer 50B, a second organic layer 70B, and a second plating layer 60B, wherein the surface of the first organic layer 70A is formed as a surface in which the first base electrode layer 50A is partially exposed, the surface of the second organic layer 70B is formed as a surface in which the second base electrode layer 50B is partially exposed, the atomic percentage of main component metal in the first base electrode layer 50A on the surface of the first organic layer 70A is 4.0 atomic% or less, and the atomic percentage of main component metal in the second base electrode layer 50B on the surface of the second organic layer 70B is 4.0 atomic% or less.

Description

Technical Field

[0001] The present invention relates to a multilayer ceramic electronic component.

Background Art

[0002] Conventionally, a multilayer ceramic capacitor as a multilayer ceramic electronic component has been known. Generally, a multilayer ceramic capacitor includes a laminate in which a plurality of dielectric layers and internal electrode layers are alternately laminated, and external electrodes connected to the internal electrode layers and provided on both end faces of the laminate. For example, Patent Document 1 discloses a multilayer ceramic capacitor having the above-described structure, in which a terminal electrode as an external electrode is composed of a metal component and an inorganic binder, and a plurality of pores are formed inside.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In the multilayer ceramic capacitor of Patent Document 1, the terminal electrode has pores. Therefore, external stress is relaxed, and the generation of cracks inside the capacitor is suppressed. As a result, the reliability of the multilayer ceramic capacitor is enhanced. However, in recent years, higher reliability has been required, and further countermeasures are demanded.

[0005] An object of the present invention is to provide a highly reliable multilayer ceramic electronic component capable of suppressing cracks from occurring in a laminate of the multilayer ceramic electronic component.

Means for Solving the Problems

[0006] The multilayer ceramic electronic component according to the present invention comprises a laminate having a plurality of alternately stacked ceramic layers and a plurality of internal conductor layers, a first main surface and a second main surface facing each other in the height direction, a first side surface and a second side surface facing each other in the width direction perpendicular to the height direction, and a first end surface and a second end surface facing each other in the length direction perpendicular to the height direction and the width direction, and an external electrode connected to the internal conductor layer, wherein the external electrode has a first external electrode disposed on the first end surface and a second external electrode disposed on the second end surface, and the first external electrode has a first base electrode layer disposed on the first base electrode layer, The second external electrode comprises a first plating layer disposed on the first organic layer, a second base electrode layer disposed on the second end face, a second organic layer disposed on the second base electrode layer, and a second plating layer disposed on the second organic layer, wherein the surface of the first organic layer is formed as a surface in which a part of the first base electrode layer is exposed, the surface of the second organic layer is formed as a surface in which a part of the second base electrode layer is exposed, the atomic percentage of the main component metal of the first base electrode layer on the surface of the first organic layer is 4.0 atom% or less, and the atomic percentage of the main component metal of the second base electrode layer on the surface of the second organic layer is 4.0 atom% or less. [Effects of the Invention]

[0007] According to the present invention, it is possible to provide a highly reliable multilayer ceramic electronic component that can suppress crack formation in the laminate of the multilayer ceramic electronic component. [Brief explanation of the drawing]

[0008] [Figure 1] This is an external perspective view of a multilayer ceramic capacitor according to the first embodiment. [Figure 2] This is a cross-sectional view taken along line II-II in Figure 1. [Figure 3] This is a cross-sectional view taken along line III-III in Figure 2. [Figure 4A] Figure 2 is an IVA-IVA cross-sectional view. [Figure 4B] Figure 2 shows a cross-sectional view from IVB to IVB. [Figure 5] This is an enlarged cross-sectional view of the area indicated by R in Figure 2. [Figure 6] This diagram shows a dual-gang multilayer ceramic capacitor. [Figure 7] This diagram shows a triple-layer ceramic capacitor. [Figure 8] This diagram shows a four-gang multilayer ceramic capacitor. [Figure 9] This is a cross-sectional view corresponding to Figure 2 in the modified example. [Figure 10A] This is a cross-sectional view corresponding to Figure 4A in the modified example. [Figure 10B] This is a cross-sectional view corresponding to Figure 4B in the modified example. [Figure 11] This is an external perspective view of a multilayer ceramic capacitor according to the second embodiment. [Figure 12] This is a cross-sectional view corresponding to Figure 4A in the second embodiment. [Figure 13] This is a cross-sectional view corresponding to Figure 4B in the second embodiment. [Modes for carrying out the invention]

[0009] <First Embodiment> Hereinafter, a multilayer ceramic capacitor 1 as a multilayer ceramic electronic component according to the first embodiment of this disclosure will be described with reference to Figures 1 to 5. Figure 1 is an external perspective view of the multilayer ceramic capacitor 1 according to the first embodiment. Figure 2 is a cross-sectional view taken along line II-II of Figure 1. Figure 3 is a cross-sectional view taken along line III-III of Figure 2. Figure 4A is a cross-sectional view taken along line IVA-IVA of Figure 2. Figure 4B is a cross-sectional view taken along line IVB-IVB of Figure 2. Figure 5 is an enlarged cross-sectional view of the portion indicated by R in Figure 2.

[0010] As shown in FIG. 1, the multilayer ceramic capacitor 1 according to the first embodiment has a substantially rectangular parallelepiped shape. The multilayer ceramic capacitor 1 includes a laminate 10 having a substantially rectangular parallelepiped shape, and a pair of external electrodes 40 disposed apart from each other at both ends of the laminate 10.

[0011] In FIG. 1, an arrow T indicates the stacking direction of the multilayer ceramic capacitor 1 and the laminate 10. This stacking direction T is also the thickness direction and the height direction of the multilayer ceramic capacitor 1 and the laminate 10. In FIG. 1, an arrow L indicates the length direction of the multilayer ceramic capacitor 1 and the laminate 10 that is orthogonal to the stacking direction T. In FIG. 1, an arrow W indicates the width direction of the multilayer ceramic capacitor 1 and the laminate 10 that is orthogonal to the stacking direction T and the length direction L. The pair of external electrodes 40 are respectively disposed at one end and the other end in the length direction L of the laminate 10.

[0012] In FIGS. 1 to 4B, an XYZ orthogonal coordinate system is shown. The length direction L of the multilayer ceramic capacitor 1 and the laminate 10 corresponds to the X direction. The width direction W of the multilayer ceramic capacitor 1 and the laminate 10 corresponds to the Y direction. The stacking direction T of the multilayer ceramic capacitor 1 and the laminate 10 corresponds to the Z direction. Here, the cross section shown in FIG. 2 is also referred to as an LT cross section. The cross section shown in FIG. 3 is also referred to as a WT cross section. The cross sections shown in FIGS. 4A and 4B are also referred to as LW cross sections.

[0013] As shown in FIGS. 1 to 4B, the laminate 10 includes a first main surface TS1 and a second main surface TS2 that face each other in the stacking direction T, a first end surface LS1 and a second end surface LS2 that face each other in the length direction L orthogonal to the stacking direction T, and a first side surface WS1 and a second side surface WS2 that face each other in the width direction W orthogonal to the stacking direction T and the length direction L.

[0014] As shown in FIG. 1, the laminate 10 has a substantially rectangular parallelepiped shape. Note that the dimension in the length direction L of the laminate 10 is not necessarily longer than the dimension in the width direction W. It is preferable that the corners and ridge lines of the laminate 10 are rounded. A corner is a portion where three surfaces of the laminate intersect, and a ridge line is a portion where two surfaces of the laminate intersect. Note that irregularities or the like may be formed on part or all of the surfaces constituting the laminate 10.

[0015] The dimensions of the laminate 10 are not particularly limited. However, when the dimension in the length direction L of the laminate 10 is defined as the L dimension, the L dimension is preferably 0.2 mm or more and 10 mm or less. Also, when the dimension in the stacking direction T of the laminate 10 is defined as the T dimension, the T dimension is preferably 0.1 mm or more and 10 mm or less. Further, when the dimension in the width direction W of the laminate 10 is defined as the W dimension, the W dimension is preferably 0.1 mm or more and 10 mm or less.

[0016] As shown in FIGS. 2 and 3, the laminate 10 includes an inner layer portion 11, a first main surface side outer layer portion 12 and a second main surface side outer layer portion 13 that are arranged so as to sandwich the inner layer portion 11 in the stacking direction T.

[0017] The inner layer portion 11 includes a plurality of dielectric layers 20 as a plurality of ceramic layers stacked alternately in the stacking direction T and a plurality of internal electrode layers 30 as a plurality of internal conductor layers. The inner layer portion 11 includes from the internal electrode layer 30 located closest to the first main surface TS1 side to the internal electrode layer 30 located closest to the second main surface TS2 side in the stacking direction T. In the inner layer portion 11, the plurality of internal electrode layers 30 are arranged to face each other via the dielectric layers 20. The inner layer portion 11 is a portion that generates capacitance and functions substantially as a capacitor.

[0018] The multiple dielectric layers 20 are composed of a dielectric material. The dielectric material may be a dielectric ceramic containing components such as BaTiO3, CaTiO3, SrTiO3, or CaZrO3. Alternatively, the dielectric material may have minor components such as Mn compounds, Fe compounds, Cr compounds, Co compounds, or Ni compounds added to these main components. It is particularly preferable that the dielectric material contains BaTiO3 as its main component.

[0019] The thickness of the dielectric layer 20 is preferably 0.5 μm or more and 15 μm or less. The number of dielectric layers 20 to be stacked is preferably 10 or more and 700 or less. This number of dielectric layers 20 is the sum of the number of dielectric layers 20 in the inner layer portion 11 and the number of dielectric layers 20 in the first main surface side outer layer portion 12 and the second main surface side outer layer portion 13.

[0020] The multiple internal electrode layers 30 include multiple first internal electrode layers 31 as multiple first internal conductor layers and multiple second internal electrode layers 32 as multiple second internal conductor layers. The first internal electrode layers 31 and the second internal electrode layers 32 are alternately arranged in the stacking direction T with a dielectric layer 20 in between. The first internal electrode layers 31 are led out to the first end face LS1. The second internal electrode layers 32 are led out to the second end face LS2. In the following, when it is not necessary to distinguish between the first internal electrode layers 31 and the second internal electrode layers 32, the first internal electrode layers 31 and the second internal electrode layers 32 may be collectively referred to as the internal electrode layer 30.

[0021] As shown in Figure 4A, the first internal electrode layer 31 has a first opposing portion 31A and a first leading portion 31B. The first opposing portion 31A is a region that faces the second internal electrode layer 32 with the dielectric layer 20 in between, and is located inside the laminate 10. The first leading portion 31B is a portion that is drawn out from the first opposing portion 31A to the first end face LS1, and is exposed to the first end face LS1.

[0022] As shown in Figure 4B, the second internal electrode layer 32 has a second opposing portion 32A and a second leading portion 32B. The second opposing portion 32A is a region that faces the first internal electrode layer 31 with the dielectric layer 20 in between, and is located inside the laminate 10. The second leading portion 32B is a portion that is drawn out from the second opposing portion 32A to the second end face LS2, and is exposed to the second end face LS2.

[0023] In this embodiment, capacitance is formed when the first opposing portion 31A and the second opposing portion 32A face each other via the dielectric layer 20, and the characteristics of a capacitor are exhibited.

[0024] The shapes of the first opposing portion 31A and the second opposing portion 32A are not particularly limited, but are preferably rectangular. However, the corners of the rectangular shape may be rounded, or the corners of the rectangular shape may be formed at an angle. The shapes of the first pull-out portion 31B and the second pull-out portion 32B are not particularly limited, but are preferably rectangular. However, the corners of the rectangular shape may be rounded, or the corners of the rectangular shape may be formed at an angle.

[0025] The widthwise dimension W of the first opposing portion 31A and the widthwise dimension W of the first drawer portion 31B may be the same, or one of them may be smaller. The widthwise dimension W of the second opposing portion 32A and the widthwise dimension W of the second drawer portion 32B may be the same, or one of them may be narrower.

[0026] The first internal electrode layer 31 and the second internal electrode layer 32 are made of a suitable conductive material such as metals like Ni, Cu, Ag, Pd, and Au, or alloys containing at least one of these metals. When using an alloy, the first internal electrode layer 31 and the second internal electrode layer 32 may be made of, for example, an Ag-Pd alloy.

[0027] The thickness of the first internal electrode layer 31 and the second internal electrode layer 32 is preferably, for example, 0.2 μm or more and 2.0 μm or less. The total number of the first internal electrode layer 31 and the second internal electrode layer 32 is preferably 10 or more and 700 or less.

[0028] As shown in Figures 2 and 3, the first main surface-side outer layer 12 is located on the first main surface TS1 side of the laminate 10. The first main surface-side outer layer 12 is an assembly of multiple dielectric layers 20 located between the first main surface TS1 and the internal electrode layer 30 closest to the first main surface TS1. On the other hand, the second main surface-side outer layer 13 is located on the second main surface TS2 side of the laminate 10. The second main surface-side outer layer 13 is an assembly of multiple dielectric layers 20 located between the second main surface TS2 and the internal electrode layer 30 closest to the second main surface TS2. The dielectric layers 20 used in the first main surface-side outer layer 12 and the second main surface-side outer layer 13 may be the same as the dielectric layers 20 used in the inner layer 11.

[0029] The laminate 10 has a counter electrode portion 11E. The counter electrode portion 11E is the portion where the first counter portion 31A of the first internal electrode layer 31 and the second counter portion 32A of the second internal electrode layer 32 face each other. The counter electrode portion 11E is configured as part of the inner layer portion 11. Figures 4A and 4B show the width W and length L ranges of the counter electrode portion 11E. The counter electrode portion 11E is also called the capacitor effective portion.

[0030] The laminate 10 has a side outer layer. The side outer layer comprises a first side outer layer WG1 and a second side outer layer WG2. The first side outer layer WG1 is a portion that includes a dielectric layer 20 located between the opposing electrode portion 11E and the first side WS1. The second side outer layer WG2 is a portion that includes a dielectric layer 20 located between the opposing electrode portion 11E and the second side WS2. Figures 3, 4A, and 4B show the widthwise range W of the first side outer layer WG1 and the second side outer layer WG2. The side outer layer is also called a W gap or side gap.

[0031] The laminate 10 has an end-face side outer layer. The end-face side outer layer has a first end-face side outer layer LG1 and a second end-face side outer layer LG2. The first end-face side outer layer LG1 is a portion located between the opposing electrode portion 11E and the first end face LS1, and includes the dielectric layer 20 and the first lead portion 31B. That is, the first end-face side outer layer LG1 is an assembly of the portions of multiple dielectric layers 20 on the first end face LS1 side and multiple first lead portions 31B. The second end-face side outer layer LG2 is a portion located between the opposing electrode portion 11E and the second end face LS2, and includes the dielectric layer 20 and the second lead portion 32B. That is, the second end-face side outer layer LG2 is an assembly of the portions of multiple dielectric layers 20 on the second end face LS2 side and multiple second lead portions 32B. Figures 2, 4A, and 4B show the longitudinal range L of the first end-face outer layer LG1 and the second end-face outer layer LG2. The end-face outer layer is also called the L gap or end gap.

[0032] As shown in Figures 1 and 2, the external electrode 40 includes a first external electrode 40A positioned on the first end face LS1 side of the laminate 10 and a second external electrode 40B positioned on the second end face LS2 side of the laminate 10.

[0033] The basic configurations of the first external electrode 40A and the second external electrode 40B are the same. Furthermore, the first external electrode 40A and the second external electrode 40B have shapes that are generally symmetrical with respect to the WT cross-section at the center of the length L of the multilayer ceramic capacitor 1. Therefore, in the following, when it is not necessary to explain the first external electrode 40A and the second external electrode 40B separately, the first external electrode 40A and the second external electrode 40B may be collectively referred to as the external electrode 40.

[0034] The first external electrode 40A is positioned on the first end face LS1. The first external electrode 40A is in contact with the first lead-out portion 31B of each of the multiple first internal electrode layers 31 exposed on the first end face LS1. As a result, the first external electrode 40A is electrically connected to the multiple first internal electrode layers 31. The first external electrode 40A may also be positioned on a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as a portion of the first side surface WS1 and a portion of the second side surface WS2. In this embodiment, the first external electrode 40A is formed extending from the first end face LS1 to a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0035] The second external electrode 40B is positioned on the second end face LS2. The second external electrode 40B is in contact with the second lead-out portion 32B of each of the multiple second internal electrode layers 32 exposed on the second end face LS2. As a result, the second external electrode 40B is electrically connected to the multiple second internal electrode layers 32. The second external electrode 40B may also be positioned on a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as on a portion of the first side surface WS1 and a portion of the second side surface WS2. In this embodiment, the second external electrode 40B is formed extending from the second end face LS2 to a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as on a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0036] As described above, within the laminate 10, capacitance is formed when the first opposing portion 31A of the first internal electrode layer 31 and the second opposing portion 32A of the second internal electrode layer 32 face each other via the dielectric layer 20. Therefore, capacitor characteristics are exhibited between the first external electrode 40A to which the first internal electrode layer 31 is connected and the second external electrode 40B to which the second internal electrode layer 32 is connected.

[0037] As shown in Figures 2, 4A, and 4B, the first external electrode 40A includes a first base electrode layer 50A, a first organic layer 70A disposed on the first base electrode layer 50A, and a first plating layer 60A disposed on the first organic layer 70A. The second external electrode 40B includes a second base electrode layer 50B, a second organic layer 70B disposed on the second base electrode layer 50B, and a second plating layer 60B disposed on the second organic layer 70B.

[0038] The first base electrode layer 50A is positioned on the first end face LS1. The first base electrode layer 50A is connected to the first lead-out portion 31B of each of the multiple first internal electrode layers 31 exposed on the first end face LS1. In this embodiment, the first base electrode layer 50A is formed extending from the first end face LS1 to a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0039] The second base electrode layer 50B is positioned on the second end face LS2. The second base electrode layer 50B is in contact with the second lead-out portion 32B of each of the multiple second internal electrode layers 32 that are exposed on the second end face LS2. In this embodiment, the second base electrode layer 50B is formed extending from the second end face LS2 to a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0040] The first base electrode layer 50A and the second base electrode layer 50B in this embodiment are baked layers. The baked layers preferably contain a metal component and either a glass component or a ceramic component, or both. The metal component includes at least one selected from, for example, Cu, Ni, Ag, Pd, Ag-Pd alloy, Au, etc. The glass component includes at least one selected from, for example, B, Si, Ba, Mg, Al, Li, etc. The ceramic component may be the same type of ceramic material as the dielectric layer 20, or a different type of ceramic material. The ceramic component includes at least one selected from, for example, BaTiO3, CaTiO3, (Ba,Ca)TiO3, SrTiO3, CaZrO3, etc. The main component metal of the first base electrode layer 50A and the main component metal of the second base electrode layer 50B are preferably Cu.

[0041] The baked layer is formed, for example, by applying a conductive paste containing glass and metal to the laminate 10 and baking it. The baked layer can be formed by simultaneously baking the laminated chip, which is the material for the laminate 10 having multiple internal electrodes and dielectric layers, and the conductive paste applied to the laminated chip. Alternatively, it may be formed by baking the laminated chip to obtain the laminate 10, and then applying the conductive paste to the laminate 10 and baking it. In the above formation method, it is preferable to bake a baked layer with a ceramic material added instead of the glass component. In that case, it is particularly preferable to use the same type of ceramic material as the dielectric layer 20 as the added ceramic material. The baked layer may consist of multiple layers.

[0042] The thickness of the first base electrode layer 50A located on the first end face LS1, corresponding to the length L, is preferably, for example, 2 μm to 220 μm in the central part of the first base electrode layer 50A in the lamination direction T and width direction W.

[0043] The thickness of the second base electrode layer 50B located on the second end face LS2, corresponding to the length L, is preferably, for example, 2 μm to 220 μm in the central part of the second base electrode layer 50B in the lamination direction T and width direction W.

[0044] When the first base electrode layer 50A is provided on a portion of at least one of the first main surface TS1 or the second main surface TS2, the thickness of the first base electrode layer 50A provided in this portion, corresponding to the lamination direction T, is preferably, for example, 4 μm to 15 μm, at the center of the first base electrode layer 50A in the length direction L and width direction W.

[0045] If the first base electrode layer 50A is also provided on a portion of at least one of the first side surface WS1 or the second side surface WS2, the thickness of the first base electrode layer 50A provided in this portion, corresponding to the width direction W, is preferably, for example, 4 μm to 15 μm, at the center of the first base electrode layer 50A provided in this portion, in the length direction L and the lamination direction T.

[0046] When a second base electrode layer 50B is provided on a portion of at least one of the first main surface TS1 or the second main surface TS2, the thickness of the second base electrode layer 50B provided in this portion, corresponding to the lamination direction T, is preferably, for example, 4 μm to 15 μm, at the center of the second base electrode layer 50B in the length direction L and width direction W.

[0047] When a second base electrode layer 50B is provided on a portion of at least one of the first side surface WS1 or the second side surface WS2, the thickness of the second base electrode layer 50B provided in this portion, corresponding to the width direction W, is preferably, for example, 4 μm to 15 μm, at the center of the second base electrode layer 50B provided in this portion, in the length direction L and the lamination direction T.

[0048] The first organic layer 70A is positioned to cover the first base electrode layer 50A. Details of the first organic layer 70A will be described later.

[0049] The second organic layer 70B is positioned to cover the second base electrode layer 50B. Details of the second organic layer 70B will be described later.

[0050] The first plating layer 60A is positioned to cover the first organic layer 70A.

[0051] The second plating layer 60B is positioned to cover the second organic layer 70B.

[0052] The first plating layer 60A and the second plating layer 60B may each contain at least one selected from, for example, Cu, Ni, Sn, Ag, Pd, Ag-Pd alloy, Au, etc. The first plating layer 60A and the second plating layer 60B may each be formed by multiple layers. Preferably, the first plating layer 60A and the second plating layer 60B have a two-layer structure in which a Sn plating layer is formed on top of a Ni plating layer.

[0053] The first plating layer 60A is arranged to cover the first organic layer 70A. In this embodiment, the first plating layer 60A includes a first Ni plating layer 61A and a first Sn plating layer 62A located on the first Ni plating layer 61A.

[0054] The second plating layer 60B is arranged to cover the second organic layer 70B. In this embodiment, the second plating layer 60B includes a second Ni plating layer 61B and a second Sn plating layer 62B located on the second Ni plating layer 61B.

[0055] The Ni plating layer prevents the first and second base electrode layers 50A and 50B from being corroded by solder when mounting the multilayer ceramic capacitor 1. The Sn plating layer improves the wettability of the solder when mounting the multilayer ceramic capacitor 1. This facilitates the mounting of the multilayer ceramic capacitor 1. The thickness of each of the first Ni plating layer 61A, the first Sn plating layer 62A, the second Ni plating layer 61B and the second Sn plating layer 62B is preferably between 2 μm and 15 μm.

[0056] The external electrode 40 in this embodiment may, for example, have a conductive resin layer containing conductive particles and a thermosetting resin. The conductive resin layer may be arranged to cover the baking layer. When the conductive resin layer is arranged to cover the baking layer, the conductive resin layer is positioned between the baking layer and the organic layer 70 (first organic layer 70A, second organic layer 70B). The conductive resin layer may completely cover the baking layer or cover only a portion of the baking layer.

[0057] A conductive resin layer containing a thermosetting resin is more flexible than a conductive layer made of, for example, a plated film or a fired conductive paste. Therefore, even if the multilayer ceramic capacitor 1 is subjected to physical shock or shock caused by thermal cycling, the conductive resin layer functions as a buffer layer. Thus, the conductive resin layer suppresses the occurrence of cracks in the multilayer ceramic capacitor 1.

[0058] The metal constituting the conductive particles may be Ag, Cu, Ni, Sn, Bi, or alloys containing these. The conductive particles preferably contain Ag. For example, the conductive particles are Ag metal powder. Ag is suitable as an electrode material because it has the lowest resistivity among metals. Furthermore, since Ag is a noble metal, it is resistant to oxidation and has high weather resistance. Therefore, Ag metal powder is suitable as conductive particles.

[0059] Furthermore, the conductive particles may be metal powders with an Ag coating on their surface. When using metal powders with an Ag coating on their surface, the metal powders are preferably Cu, Ni, Sn, Bi, or alloys thereof. It is preferable to use Ag-coated metal powders in order to maintain the properties of Ag while making the base metal less expensive.

[0060] Furthermore, the conductive particles may be Cu or Ni that have been treated to prevent oxidation. Alternatively, the conductive particles may be metal powder coated with Sn, Ni, or Cu on the surface of the metal powder. When using metal powder coated with Sn, Ni, or Cu on the surface, the metal powder is preferably Ag, Cu, Ni, Sn, Bi, or an alloy of these.

[0061] The shape of the conductive particles is not particularly limited. Conductive particles can have shapes such as spherical or flattened, but it is preferable to use a mixture of spherical metal powder and flattened metal powder.

[0062] The conductive particles contained in the conductive resin layer primarily play a role in ensuring the conductivity of the conductive resin layer. Specifically, the contact between multiple conductive particles forms an electrical pathway within the conductive resin layer.

[0063] The resin constituting the conductive resin layer may include at least one selected from various known thermosetting resins such as epoxy resin, phenolic resin, urethane resin, silicone resin, and polyimide resin. Among these, epoxy resin, which has excellent heat resistance, moisture resistance, and adhesion, is one of the most suitable resins. Furthermore, it is preferable that the resin in the conductive resin layer includes a curing agent together with the thermosetting resin. When epoxy resin is used as the base resin, the curing agent for the epoxy resin may be various known compounds such as phenolic, amine, acid anhydride, imidazole, active ester, and amide-imide compounds.

[0064] The conductive resin layer may be formed from multiple layers. Preferably, the thickness of the thickest part of the conductive resin layer is 10 μm or more and 200 μm or less.

[0065] Next, the organic layer 70 according to this embodiment will be described with reference to Figures 2 to 5. The organic layer 70 according to this embodiment includes a first organic layer 70A and a second organic layer 70B.

[0066] The first organic layer 70A is disposed on the first underlay electrode layer 50A. The first plating layer 60A is disposed on the first organic layer 70A. The first organic layer 70A may also be disposed on a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as a portion of the first side surface WS1 and a portion of the second side surface WS2. In this embodiment, the first organic layer 70A is formed to extend approximately to the center of the length L of the first main surface TS1 and the second main surface TS2, and approximately to the center of the length L of the first side surface WS1 and the second side surface WS2.

[0067] The second organic layer 70B is disposed on the second under electrode layer 50B. The second plating layer 60B is disposed on the second organic layer 70B. The second organic layer 70B may also be disposed on a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as a portion of the first side surface WS1 and a portion of the second side surface WS2. In this embodiment, the second organic layer 70B is formed to extend to approximately the center of the length L of the first main surface TS1 and the second main surface TS2, and to approximately the center of the length L of the first side surface WS1 and the second side surface WS2.

[0068] Therefore, the first organic layer 70A and the second organic layer 70B are integrally formed at approximately the center of the length L of the first main surface TS1 and the second main surface TS2, and at approximately the center of the length L of the first side surface WS1 and the second side surface WS2. In this way, the first organic layer 70A and the second organic layer 70B of this embodiment are integrally formed to cover the entire portion of the surface of the laminate 10 that is exposed from the external electrode 40.

[0069] The state of the underlying electrode layer 50 covered by the organic layer 70 will be explained using Figure 5. Figure 5 is an enlarged cross-sectional view of the portion indicated by R in Figure 2. In Figure 5, the state of the first base electrode layer 50A covered by the first organic layer 70A will be described, but the state of the second base electrode layer 50A covered by the second organic layer 70B is similar, so the description will be omitted. As shown in Figure 5, the first organic layer 70A is formed between the first base electrode layer 50A formed on the dielectric layer 20 and the first Ni plating layer 61A.

[0070] The surface of the first organic layer 70A is formed as a surface in which a portion of the first underlying electrode layer 50A is exposed. That is, the first organic layer 70A has multiple voids as shown in Figure 5. On the surface of the first organic layer 70A, the atomic percentage of the main component metal of the first underlying electrode layer 50A is 4.0 atom% or less. More preferably, on the surface of the first organic layer 70A, the atomic percentage of the main component metal of the first underlying electrode layer 50A is 3.0 atom% or less.

[0071] The surface of the second organic layer 70B is formed as a surface in which a portion of the second underlying electrode layer 50B is exposed. That is, the second organic layer 70B has multiple voids as shown in Figure 5. On the surface of the second organic layer 70B, the atomic percentage of the main component metal of the second underlying electrode layer 50B is 4.0 atom% or less. More preferably, on the surface of the second organic layer 70B, the atomic percentage of the main component metal of the second underlying electrode layer 50B is 3.0 atom% or less.

[0072] On the surface of the first organic layer 70A, it is preferable that the atomic percentage of the main component metal of the first underlay electrode layer 50A is 0.6 atom% or more. On the surface of the second organic layer 70B, it is preferable that the atomic percentage of the main component metal of the second underlay electrode layer 50B is 0.6 atom% or more.

[0073] As mentioned above, the main component metal of the first base electrode layer 50A and the main component metal of the second base electrode layer 50B is preferably Cu. However, the main component metal of the first base electrode layer 50A and the main component metal of the second base electrode layer 50B are not limited to Cu. For example, Ni, Ag, Pd, Ag-Pd alloy, or Au can be used.

[0074] The first organic layer 70A and the second organic layer 70B contain organosilicon compounds. As a result, the first organic layer 70A and the second organic layer 70B are reliably formed on the surface of the laminate 10, the base electrode layer 50, etc., thereby improving reliability.

[0075] However, the compositions constituting the first organic layer 70A and the second organic layer 70B are not limited to these. Examples of the first organic layer 70A and the second organic layer 70B include fatty acid coatings. A fatty acid coating is a layer formed by scattering fatty acids on the surface of the underlying electrode layer. When a fatty acid coating is applied as the first organic layer 70A and the second organic layer 70B, fatty acids will be present on the surface of the underlying electrode layer at least. More specifically, fatty acids will be present on the surface of the first underlying electrode layer 50A and the surface of the second underlying electrode layer 50B at least. As a result, the carboxyl groups of the fatty acids are ionized and adsorbed onto the underlying electrode layer by ionic bonding force, and the deposition of the plating layer provided on the underlying electrode layer is inhibited at the adsorption site, thereby reducing the bonding area between the underlying electrode layer and the plating layer. Therefore, the adhesion force between the underlying electrode layer and the plating layer is reduced, which has the effect of promoting the separation of the underlying electrode layer from the plating layer formed thereon. Therefore, when a multilayer ceramic capacitor is subjected to impact from a fall or thermal cycling, it becomes possible to stably delaminate between the underlying electrode layer and the plating layer, thereby releasing stress. As a result, it is possible to suppress crack formation in the multilayer structure of the multilayer ceramic capacitor.

[0076] On the surface of the first organic layer 70A, it is preferable that the sum of the atomic percentages (atom%) of Si, C, N, and O is 90 atom% or more. On the surface of the second organic layer 70B, it is preferable that the sum of the atomic percentages (atom%) of Si, C, N, and O is 90 atom% or more.

[0077] The thickness of the first organic layer 70A is preferably 5 nm to 500 nm. More preferably, the thickness of the first organic layer 70A is 100 nm to 200 nm. The thickness of the second organic layer 70B is preferably 5 nm to 500 nm. More preferably, the thickness of the second organic layer 70B is 100 nm to 200 nm.

[0078] The above describes the basic configuration of the multilayer ceramic capacitor 1 according to the embodiment. If the lengthwise dimension of the multilayer ceramic capacitor 1, including the laminated body 10 and the external electrodes 40, is denoted as dimension L, then it is preferable that dimension L is between 0.2 mm and 10 mm. Furthermore, if the dimension in the stacking direction of the multilayer ceramic capacitor 1 is denoted as dimension T, then it is preferable that dimension T is between 0.1 mm and 10 mm. Also, if the widthwise dimension of the multilayer ceramic capacitor 1 is denoted as dimension W, then it is preferable that dimension W is between 0.1 mm and 10 mm.

[0079] <Atomic percentage of organic layer surface components> Next, the method for measuring the atomic percentage of the organic layer surface components in this embodiment will be described. First, one external electrode of the multilayer ceramic capacitor is mounted on the mounting substrate using solder, leaving the other external electrode suspended in mid-air. Next, the other suspended external electrode is pushed from below in the height direction to separate the base electrode layer from the plating layer on the external electrode mounted on the mounting substrate, exposing the organic layer. Then, XPS analysis is performed on the multilayer ceramic capacitor 1 from which the plating layer has been removed. First, X-rays are irradiated onto the entire surface of the exposed organic layer. The thermionic acceleration voltage at this time is set to 15kV. Next, a qualitative analysis of all elements is performed using a wide scan, and then a quantitative analysis of all elements is performed using a narrow scan to calculate the abundance ratio (atom%) of all elements on the surface of the organic layer. In this embodiment, the narrow scan spectrum is calculated for the elements detected from the wide scan spectrum, normalized so that the sum of the detected elements is 100 atom%, and then XPS analysis is performed. Note that the abundance ratio (atom%) is the atomic percentage that represents the proportion of atoms excluding hydrogen and helium.

[0080] Next, the manufacturing method of the multilayer ceramic capacitor 1 of this embodiment will be described. The manufacturing method of the multilayer ceramic capacitor 1 of this embodiment is not limited as long as the above requirements are satisfied. However, a preferred manufacturing method comprises the following steps. The details of each step are described below.

[0081] A dielectric sheet for the dielectric layer 20 and a conductive paste for the internal electrode layer 30 are prepared. Both the dielectric sheet for the dielectric layer 20 and the conductive paste for the internal electrode layer 30 contain a binder and a solvent. The binder and solvent may be known materials. The paste made of a conductive material is, for example, a metal powder to which an organic binder and an organic solvent are added.

[0082] A conductive paste for the internal electrode layer 30 is printed onto the dielectric sheet using a printing plate designed to form the shape of the internal electrode layer 30 in this embodiment, for example, by screen printing or gravure printing. This prepares a dielectric sheet with the pattern of the first internal electrode layer 31 formed on it and a dielectric sheet with the pattern of the second internal electrode layer 32 formed on it.

[0083] A predetermined number of dielectric sheets without the pattern of the internal electrode layer 30 printed on them are stacked to form the first main surface outer layer portion 12 on the first main surface TS1 side. On top of this, dielectric sheets with the pattern of the first internal electrode layer 31 printed on them and dielectric sheets with the pattern of the second internal electrode layer 32 printed on them are stacked alternately in sequence to form the inner layer portion 11. On top of this inner layer portion 11, a predetermined number of dielectric sheets without the pattern of the internal electrode layer 30 printed on them are stacked to form the second main surface outer layer portion 13 on the second main surface TS2 side. This results in a laminated sheet.

[0084] Next, the laminated sheets are pressed in the lamination direction by means of a hydrostatic press or other means to produce a laminated block.

[0085] Next, the laminated block is cut into predetermined sizes to form individual pieces, thereby obtaining multiple laminated chips. After this, the laminated chips may be polished by barrel polishing or other methods to round off the corners and edges.

[0086] Next, the laminated chips are fired to obtain the laminated body 10. The firing temperature at this time depends on the materials of the dielectric layer 20 and the internal electrode layer 30, but is preferably, for example, 900°C to 1400°C.

[0087] A conductive paste, which will serve as the base electrode layer 50, is applied to both end faces of the laminate 10. In this embodiment, the base electrode layer 50 is a baked layer. The baked layer can be formed by applying a conductive paste containing glass components and metal to the laminate 10, for example by dipping, and then performing a baking treatment. The temperature of the baking treatment at this time is preferably 700°C to 900°C.

[0088] Alternatively, the laminated chip before firing and the conductive paste applied to the laminated chip may be fired simultaneously. In this case, it is preferable to form the baked layer by baking a material with a ceramic component added instead of a glass component. In this case, it is particularly preferable to use the same type of ceramic material as the dielectric layer 20 as the added ceramic material. In this case, the conductive paste is applied to the laminated chip before firing, and the laminated chip and the conductive paste applied to the laminated chip are fired simultaneously to form a laminated body 10 with a baked layer.

[0089] Next, an organic layer is formed on the base electrode layer, loosely coating it with an organic compound. One method for forming the organic layer on the base electrode layer is to dilute the organic compound with an organic solvent and spray-apply it. Specifically, for example, a solution is prepared by diluting a silane coupling agent with IPA (2-propanol). The laminate with the base electrode layer is placed in a barrel apparatus, and the solution is spray-applied to the laminate with the base electrode layer. After that, it is removed from the barrel apparatus, spread on filter paper, and the organic layer is cured by heat treatment in an oven at 100°C to 200°C for a predetermined time (30 to 60 minutes).

[0090] Alternatively, the layer can be formed by diluting an organic compound with an organic solvent to create a solution, then applying the solution to a laminate with a base electrode layer and heat-curing it. Methods for applying the solution include dipping.

[0091] Here, the target value of the atomic percentage of the main component metal of the underlying electrode layer on the surface of the organic layer, and the thickness of the organic layer, can be controlled by controlling the solution concentration, coating method, coating time, and coating temperature.

[0092] Subsequently, a plating layer is formed on the surface of the organic layer 70. In this embodiment, a first plating layer 60A is formed on the surface of the first organic layer 70A. Also, a second plating layer 60B is formed on the surface of the second organic layer 70B. In this embodiment, a Ni plating layer and a Sn plating layer are formed as the plating layers. When performing the plating treatment, either electrolytic plating or electroless plating may be used. However, electroless plating has the disadvantage of complicating the process because it requires pretreatment with a catalyst or the like to improve the plating deposition rate. Therefore, it is generally preferable to use electrolytic plating. The Ni plating layer and the Sn plating layer are formed sequentially, for example, by barrel plating.

[0093] When a conductive resin layer is provided, it may be positioned to cover the baked layer. When a conductive resin layer is provided, a conductive resin paste containing a thermosetting resin and metal components is applied to the baked layer, and then heat-treated at a temperature of 250 to 550°C or higher. This causes the thermosetting resin to harden and form a conductive resin layer. The atmosphere during this heat treatment is preferably an N2 atmosphere. Furthermore, to prevent resin scattering and oxidation of various metal components, the oxygen concentration is preferably 100 ppm or less.

[0094] Through the above manufacturing process, a multilayer ceramic capacitor 1 is produced.

[0095] Note that the configuration of the multilayer ceramic capacitor 1 is not limited to the configurations shown in Figures 1 to 4B. For example, the multilayer ceramic capacitor 1 may be a double-gang, triple-gang, or quadruple-gang multilayer ceramic capacitor as shown in Figures 6 to 8.

[0096] The multilayer ceramic capacitor 1 shown in Figure 6 is a double-gang multilayer ceramic capacitor 1, and as an internal electrode layer 30, it includes a first internal electrode layer 33 and a second internal electrode layer 34, as well as a floating internal electrode layer 35 that is not led out to either the first end face LS1 or the second end face LS2. The multilayer ceramic capacitor 1 shown in Figure 7 is a triple-gang multilayer ceramic capacitor 1, which includes a first floating internal electrode layer 35A and a second floating internal electrode layer 35B as floating internal electrode layers 35. The multilayer ceramic capacitor 1 shown in Figure 8 is a quadruple-gang multilayer ceramic capacitor 1, which includes a first floating internal electrode layer 35A, a second floating internal electrode layer 35B, and a third floating internal electrode layer 35C as floating internal electrode layers 35. In this way, by providing floating internal electrode layers 35 as internal electrode layers 30, the multilayer ceramic capacitor 1 has a structure in which the opposing electrode portion is divided into multiple parts. As a result, multiple capacitor components are formed between the opposing internal electrode layers 30, and these capacitor components are connected in series. Therefore, the voltage applied to each capacitor component becomes lower, and the voltage rating of the multilayer ceramic capacitor 1 can be increased. It goes without saying that the multilayer ceramic capacitor 1 in this embodiment may also have a multi-gang structure of four or more units.

[0097] <Variation> In the multilayer ceramic capacitor 1 according to the above embodiment, the first organic layer 70A and the second organic layer 70B extend to approximately the center in the longitudinal direction L of the first main surface TS1 and the second main surface TS2, and to approximately the center in the longitudinal direction L of the first side surface WS1 and the second side surface WS2, and are integrally formed to cover the entire portion of the surface of the laminate 10 that is exposed from the external electrode 40. However, the configuration of the first organic layer 70A and the second organic layer 70B is not limited to this.

[0098] Below, a modified example of the multilayer ceramic capacitor 1 will be described using Figures 9 to 10B. Figure 9 is a cross-sectional view corresponding to Figure 2 in the modified example. Figure 10A is a cross-sectional view corresponding to Figure 4A in the modified example. Figure 10B is a cross-sectional view corresponding to Figure 4B in the modified example. Note that for configurations similar to those in the first embodiment, the same names may be used and detailed explanations may be omitted.

[0099] As shown in Figure 1, the modified multilayer ceramic capacitor 1 has a substantially rectangular parallelepiped shape. The multilayer ceramic capacitor 1 comprises a laminate 10 having a substantially rectangular parallelepiped shape, and a pair of external electrodes 40 arranged spaced apart from each other at both ends of the laminate 10.

[0100] As shown in Figures 1 and 9, the external electrode 40 includes a first external electrode 40A positioned on the first end face LS1 side of the laminate 10 and a second external electrode 40B positioned on the second end face LS2 side of the laminate 10.

[0101] As shown in Figures 9, 10A, and 10B, the first external electrode 40A includes a first base electrode layer 50A, a first organic layer 70bA disposed on the first base electrode layer 50A, and a first plating layer 60A disposed on the first organic layer 70bA. The second external electrode 40B includes a second base electrode layer 50B, a second organic layer 70bB disposed on the second base electrode layer 50B, and a second plating layer 60B disposed on the second organic layer 70bB.

[0102] The organic layer 70b in this modified example includes a first organic layer 70bA and a second organic layer 70bB.

[0103] The first organic layer 70bA is located on the first underlay electrode layer 50A. The first plating layer 60A is located on the first organic layer 70bA. The first organic layer 70bA may also be located on a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as on a portion of the first side surface WS1 and a portion of the second side surface WS2. In this modified example, the first organic layer 70bA is formed to extend to a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as on a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0104] The second organic layer 70bB is located on the second underlay electrode layer 50B. The second plating layer 60B is located on the second organic layer 70bB. The second organic layer 70bB may also be located on a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as on a portion of the first side surface WS1 and a portion of the second side surface WS2. In this modified example, the second organic layer 70bB extends to a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as on a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0105] In other words, in the multilayer ceramic capacitor 1 according to this modified example, there is a portion between the first external electrode 40A and the second external electrode 40B where the organic layer 70b is not present. Therefore, the first organic layer 70bA and the second organic layer 70bB in this modified example are not formed integrally, and a part of the surface of the laminate 10 is exposed. Even in this case, since the organic layer is formed at the edge of the underlying electrode layer of the external electrode which is the starting point of a crack, the effect of crack suppression can be obtained.

[0106] <Second Embodiment> In the first embodiment, the multilayer ceramic capacitor 1 was a two-terminal type with two external electrodes, but it is not limited to this, and may be a multi-terminal type with a large number of external electrodes.

[0107] The multilayer ceramic capacitor 1 according to the second embodiment will be described below with reference to Figures 11 to 13. In the following description, detailed explanations of the same configuration as in the first embodiment will be omitted. Figure 11 is an external perspective view of the multilayer ceramic capacitor according to the second embodiment. Figure 12 is a cross-sectional view corresponding to Figure 4A in the second embodiment. Figure 13 is a cross-sectional view corresponding to Figure 4B in the second embodiment.

[0108] The multilayer ceramic capacitor 1 of this embodiment differs from the first embodiment in the configuration of the internal electrode layer inside the laminate 10 and the external electrode 40.

[0109] The multiple internal electrode layers, which are multiple internal conductor layers, include a plurality of first internal electrode layers 131, which are multiple first internal conductor layers drawn out to a first end face LS1 and a second end face LS2, and a plurality of second internal electrode layers 132, which are multiple second internal conductor layers drawn out to at least one of the first side face WS1 or the second side face WS2.

[0110] In this embodiment, the plurality of internal electrode layers include a plurality of first internal electrode layers 131 drawn out to a first end face LS1 and a second end face LS2, and a plurality of second internal electrode layers 132 drawn out to a first side surface WS1 and a second side surface WS2. The plurality of first internal electrode layers 131 are arranged on a plurality of dielectric layers 20. The plurality of second internal electrode layers 132 are arranged on a plurality of dielectric layers 20. The plurality of first internal electrode layers 131 and the plurality of second internal electrode layers 132 are arranged alternately via the dielectric layers 20 in the stacking direction T of the laminate 10. The first internal electrode layers 131 and the second internal electrode layers 132 are arranged so as to sandwich the dielectric layers 20.

[0111] The first internal electrode layer 131 is positioned on the dielectric layer 20 and extends from the first end face LS1 to the second end face LS2 so as to be exposed on the first end face LS1 and the second end face LS2. More specifically, the first internal electrode layer 131 has a first opposing portion 131A facing the second internal electrode layer 132, a first lead portion 131B drawn out from the first opposing portion 131A to the first end face LS1, and a second lead portion 131C drawn out from the first opposing portion 131A to the second end face LS2. The first opposing portion 131A is located in the central part of the dielectric layer 20. The first lead portion 131B is exposed on the first end face LS1. The second lead portion 131C is exposed on the second end face LS2. The first internal electrode layer 131 is not exposed on the first side surface WS1 and the second side surface WS2. The shape of the first opposing portion 131A, the shape of the first lead portion 131B, and the shape of the second lead portion 131C of the first internal electrode layer 131 are not particularly limited.

[0112] The second internal electrode layer 132 is positioned on the dielectric layer 20 and is exposed to the first side surface WS1 and the second side surface WS2, but not to the first end surface LS1 and the second end surface LS2. Specifically, the second internal electrode layer 132 extends between the first side surface WS1 and the second side surface WS2. More specifically, the second internal electrode layer 132 has a second opposing portion 132A facing the first internal electrode layer 131, a third lead portion 132B extending from the second opposing portion 132A to the first side surface WS1, and a fourth lead portion 132C extending from the second opposing portion 132A to the second side surface WS2. The second opposing portion 132A is located in the central part of the dielectric layer 20. The second opposing portion 132A is formed in a rectangular shape so as to extend in the direction of the first end surface LS1 and the direction of the second end surface LS2. The third lead portion 132B is exposed on the first side surface WS1. The fourth lead portion 132C is exposed on the second side surface WS2. The second internal electrode layer 132 is not exposed on the first end surface LS1 and the second end surface LS2. The shape of the second opposing portion 132A, the shape of the third lead portion 132B, and the shape of the fourth lead portion 132C of the second internal electrode layer 132 are not particularly limited.

[0113] In this embodiment, capacitance is formed when the first opposing portion 131A and the second opposing portion 132A face each other via the dielectric layer 20, and the characteristics of a capacitor are exhibited.

[0114] The external electrode 40 includes at least a first external electrode 40A, a second external electrode 40B, and a third external electrode 40C. In this embodiment, the external electrode 40 includes a first external electrode 40A, a second external electrode 40B, a third external electrode 40C, and a fourth external electrode 40D.

[0115] The first external electrode 40A is positioned on the first end face LS1 and connected to the first internal electrode layer 131. In other words, the first external electrode 40A is connected to the first internal electrode layer 131 which is drawn out from the first end face LS1. More specifically, the first external electrode 40A is connected to the first lead-out portion 131B of the first internal electrode layer 131. In this embodiment, the first external electrode 40A is formed extending from the first end face LS1 to a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0116] The second external electrode 40B is positioned on the second end face LS2 and connected to the first internal electrode layer 131. In other words, the second external electrode 40B is connected to the first internal conductor layer 131 that is drawn out from the second end face LS2. More specifically, the second external electrode 40B is connected to the second lead-out portion 131C of the first internal electrode layer 131. In this embodiment, the second external electrode 40B is formed extending from the second end face LS2 to a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0117] The third external electrode 40C is positioned on the first side surface WS1 and connected to the second internal electrode layer 132. More specifically, the third external electrode 40C is connected to the third lead-out portion 132B of the second internal electrode layer 132. In this embodiment, the third external electrode 40C extends from the first side surface WS1 to a portion of the first main surface TS1 and a portion of the second main surface TS2.

[0118] The fourth external electrode 40D is positioned on the second side surface WS2 and connected to the second internal electrode layer 132. More specifically, the fourth external electrode 40D is connected to the fourth lead-out portion 132C of the second internal electrode layer 132. In this embodiment, the fourth external electrode 40D extends from the second side surface WS2 to a portion of the first main surface TS1 and a portion of the second main surface TS2.

[0119] Furthermore, as the layer configuration of the external electrode 40 in this embodiment, various layer configurations similar to those of the external electrode 40 in the first embodiment can be adopted.

[0120] For example, the first external electrode 40A comprises a first underlay electrode layer 50A, a first plating layer 60A, and a first organic layer 70A, and the first plating layer 60A may comprise a first Ni plating layer 61A and a first Sn plating layer 62A. The second external electrode 40B comprises a second underlay electrode layer 50B, a second plating layer 60B, and a second organic layer 70B, and the second plating layer 60B may comprise a second Ni plating layer 61B and a second Sn plating layer 62B. The third external electrode 40C comprises a third underlay electrode layer 50C, a third plating layer 60C, and a third organic layer 70C, and the third plating layer 60C may comprise a third Ni plating layer 61C and a third Sn plating layer 62C. The fourth external electrode 40D comprises a fourth base electrode layer 50D, a fourth plating layer 60D, and a fourth organic layer 70D, and the fourth plating layer 60D may comprise a fourth Ni plating layer 61D and a fourth Sn plating layer 62D. The first base electrode layer 50A, the second base electrode layer 50B, the third base electrode layer 50C, and the fourth base electrode layer 50D may be, for example, baked layers.

[0121] As described above, the organic layer 70 according to this embodiment, which will be explained using Figures 12 and 13, includes a first organic layer 70A, a second organic layer 70B, a third organic layer 70C, and a fourth organic layer 70D.

[0122] The first organic layer 70A is placed on the first base electrode layer 50A. The first plating layer 60A is placed on the first organic layer 70A. The first organic layer 70A may also be placed on a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as a portion of the first side surface WS1 and a portion of the second side surface WS2, between the first external electrode 40A and the second external electrode 40B, third external electrode 40C, and fourth external electrode 40D in the longitudinal direction L.

[0123] The second organic layer 70B is placed on the second base electrode layer 50B. The second plating layer 60B is placed on the second organic layer 70B. The second organic layer 70B may also be placed on a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as a portion of the first side surface WS1 and a portion of the second side surface WS2, between the second external electrode 40B in the longitudinal direction L and the first external electrode 40A, the third external electrode 40C, and the fourth external electrode 40D.

[0124] The third organic layer 70C is located on the third base electrode layer 50C. The third plating layer 60C is located on the third organic layer 70C. The third organic layer 70C may also be located on a portion of the first side surface WS1 between the third external electrode 40C and the first external electrode 40A in the length direction L, and between the third external electrode 40C and the second external electrode 40B in the length direction L. The third organic layer 70C may also be located on a portion of the first main surface TS1 and a portion of the second main surface TS2.

[0125] The fourth organic layer 70D is positioned on the fourth base electrode layer 50D. The fourth plating layer 60D is positioned on the fourth organic layer 70D. The fourth organic layer 70D may also be positioned on a portion of the second side surface WS2 between the fourth external electrode 40D and the first external electrode 40A in the length direction L, and between the fourth external electrode 40D and the second external electrode 40B in the length direction L. The fourth organic layer 70D may also be positioned on a portion of the first main surface TS1 and a portion of the second main surface TS2.

[0126] Therefore, the first organic layer 70A, the second organic layer 70B, the third organic layer 70C, and the fourth organic layer 70D are integrally formed to cover the entire portion of the surface of the laminate 10 that is exposed from the external electrode 40. In this way, even in the case of a multi-terminal type with a large number of external electrodes, the organic layer is formed at the edge of the underlying electrode layer of the external electrode that is the starting point of a crack, thus providing a crack suppression effect. In the case of such a multi-terminal type multilayer ceramic electronic component, it is preferable that the organic layer comprises at least the first organic layer 70A and the second organic layer 70B.

[0127] In the embodiments described above, a multilayer ceramic capacitor was given as an example, in which a dielectric layer 20 made of dielectric ceramic is used as the ceramic layer. However, the multilayer ceramic electronic components of this disclosure are not limited to this. For example, the ceramic electronic components of this disclosure can also be applied to various multilayer ceramic electronic components such as piezoelectric components using piezoelectric ceramic as the ceramic layer, and thermistors using semiconductor ceramic as the ceramic layer. Examples of piezoelectric ceramics include PZT (lead zirconate titanate) ceramics, and examples of semiconductor ceramics include spinel ceramics.

[0128] The multilayer ceramic capacitor 1 according to the embodiment described above provides the following effects.

[0129] The multilayer ceramic capacitor 1 according to the embodiment includes a plurality of alternately stacked dielectric layers 20 (ceramic layers 20) and a plurality of internal electrode layers 30 (internal conductor layers 30), and comprises a laminate 10 having a first main surface TS1 and a second main surface TS2 facing the height direction T, a first side surface WS1 and a second side surface WS2 facing the width direction W perpendicular to the height direction T, and a first end surface LS1 and a second end surface LS2 facing the length direction L perpendicular to the height direction T and the width direction W, and an external electrode 40 connected to the internal electrode layer 30, wherein the external electrode 40 has a first external electrode 40A disposed on the first end surface LS1 and a second external electrode 40B disposed on the second end surface LS2, and the first external electrode 40A has a first base electrode layer 50A disposed on the first end surface LS1 and a first base electrode layer 50 The first external electrode 40B has a first organic layer 70A disposed on A and a first plating layer 60A disposed on the first organic layer 70A, and the second external electrode 40B has a second base electrode layer 50B disposed on the second end face LS2, a second organic layer 70B disposed on the second base electrode layer 50B and a second plating layer 60B disposed on the second organic layer 70B, the surface of the first organic layer 70A is formed as a surface in which a part of the first base electrode layer 50A is exposed, the surface of the second organic layer 70B is formed as a surface in which a part of the second base electrode layer 50B is exposed, the atomic percentage of the main component metal of the first base electrode layer 50A on the surface of the first organic layer 70A is 4.0 atom% or less, and the atomic percentage of the main component metal of the second base electrode layer 50B on the surface of the second organic layer 70B is 4.0 atom% or less.

[0130] This makes it possible to provide a highly reliable multilayer ceramic electronic component that can suppress crack formation in the laminate 10 of the multilayer ceramic electronic component.

[0131] In the multilayer ceramic capacitor 1 according to the embodiment, the atomic percentage of the main component metal of the first base electrode layer 50A on the surface of the first organic layer 70A is 0.6 atom% or more, and the atomic percentage of the main component metal of the second base electrode layer 50B on the surface of the second organic layer 70B is 0.6 atom% or more.

[0132] This makes it possible to provide highly reliable multilayer ceramic electronic components while suppressing the occurrence of plating defects.

[0133] In the multilayer ceramic capacitor 1 according to this embodiment, the main component metal of the first base electrode layer 50A and the main component metal of the second base electrode layer 50B are Cu.

[0134] This suppresses the diffusion of hydrogen into the internal dielectric layer during manufacturing, prevents degradation of insulation resistance, and allows for the provision of highly reliable multilayer ceramic electronic components while keeping manufacturing costs down.

[0135] In the multilayer ceramic capacitor 1 according to this embodiment, the first organic layer 70A and the second organic layer 70B are organosilicon compounds.

[0136] This ensures that the organic layer is reliably formed on the surface of the laminate or the underlying electrode layer of the external electrode, thereby improving reliability.

[0137] The multilayer ceramic capacitor 1 according to this embodiment has a plurality of internal electrode layers 30, which include a plurality of first internal electrode layers 31 drawn out to a first end face LS1 and a plurality of second internal electrode layers 32 drawn out to a second end face LS2, and the first external electrode 40A is connected to the first internal electrode layer 31 and the second external electrode 40B is connected to the second internal electrode layer 32.

[0138] This makes it possible to provide a highly reliable, two-terminal multilayer ceramic electronic component with two external electrodes.

[0139] The multilayer ceramic capacitor 1 according to this embodiment has an external electrode 40 which further has a third external electrode 40C (or a fourth external electrode 40D), and a plurality of internal electrode layers 30 which have a plurality of first internal electrode layers 131 which are drawn out to a first end face LS1 and a second end face LS2, and a plurality of second internal electrode layers 132 which are drawn out to at least one of the first side face WS1 or the second side face WS2, the first external electrode 40A is connected to the first internal electrode layer 131 drawn out to the first end face LS1, the second external electrode 40B is connected to the first internal electrode layer 131 which is drawn out to the second end face LS2, and the third external electrode 40C (or a fourth external electrode 40D) is connected to the second internal electrode layer 132.

[0140] This makes it possible to provide highly reliable, multi-terminal multilayer ceramic electronic components with numerous external electrodes.

[0141] The present invention is not limited to the configuration of the above embodiments, and can be modified and applied as appropriate without altering the gist of the invention. Furthermore, a combination of two or more of the desirable configurations described in the above embodiments also constitutes the present invention. Experimental Example

[0142] The following describes experimental examples. Using the manufacturing method described in the above embodiment, multilayer ceramic capacitors with the structures shown in Figures 1 to 5 were fabricated as samples for the examples and comparative examples. Specifically, multiple lots of multilayer ceramic capacitors were fabricated so that the atomic percentage of the main component metal of the underlying electrode layer on the surface of the organic layer had different values, and these were used as samples for Examples 1 to 7 and Comparative Examples 1 to 5.

[0143] Samples from the same lot were manufactured under the same conditions, and the specifications of the external electrodes were identical. For each lot (Examples 1-7 and Comparative Examples 1-5), 110 samples were prepared. For each lot, 100 of the 110 prepared samples were checked for plating defects, and then subjected to a deflection strength test. In addition, the atomic percentage of the main component metal of the underlying electrode layer on the surface of the organic layer was measured using the remaining 10 samples prepared from the same lot. The atomic percentage of the main component metal of the underlying electrode layer on the surface of the organic layer was measured using the measurement method described above, and the average value of the 10 samples was used as the measurement result.

[0144] Using the manufacturing method according to the above embodiment, a multilayer ceramic capacitor with the following specifications and the structure shown in Figures 1 to 5 was fabricated. • Dimensions of the multilayer ceramic capacitor: L × W × T = 1.0 mm × 0.5 mm × 0.5 mm • Dielectric layer material: Main component: BaTiO3 ·Capacity: 10nF ·Internal electrode: Ni • Structure of the external electrodes • Cu base electrode layer: A base electrode layer containing Cu and glass. Thickness at the center of the height direction located at the first and second end faces in the cross-section of the laminate at the 1 / 2W position (thickness at the center of the end face): 28 μm Thickness in the longitudinal central portion located on the first and second main surfaces, the first and second side surfaces, and the second side surface of the laminate at the 1 / 2W position: 10 μm • Organic layer: A solution of silane coupling agent diluted with 2-propanol was spray-applied to the laminate with the underlying electrode layer, then the chips were spread on an aluminum tray and heat-treated in an oven at 150°C for 30 minutes to cure. Location of the layered material: the exposed surface of the laminate and the surface on the underlying electrode layer. • Plating layer: Formed in two layers, with a Ni plating layer on a base electrode layer where fatty acids are arranged, and a Sn plating layer on top of the Ni plating layer. Ni plating thickness: 4.0 μm Sn plating thickness: 4.0 μm

[0145] <Method for checking for cracks using a deflection strength test> First, multilayer ceramic capacitors were mounted onto a 1.6mm thick circuit board using solder paste. Then, the circuit board without the mounted capacitors was bent using a pressure rod with a radius of curvature of 1μm, applying mechanical stress. The deflection was set to 2mm and the board was deformed for 60 seconds. Note that this test used stricter conditions than the AEC-Q200 standard required for automotive electronic components.

[0146] After bending the substrate, the multilayer ceramic capacitor was removed from the substrate, its cross-section was polished, and the presence or absence of cracks in the laminate was observed. The cross-section was polished so that the LT surface of the multilayer ceramic capacitor was exposed up to a position that was half the width W connecting the first and second end faces of the multilayer ceramic capacitor.

[0147] For each lot, if cracks occurred in 10 or more of the 100 samples subjected to the above test, the deflection strength evaluation result was judged to be NG. If fewer than 10 samples showed cracks, the deflection strength evaluation result was judged to be OK.

[0148] <How to check for plating defects> Using a jig, the plated samples were positioned with the end face facing upwards. The external electrodes on the end faces of the samples were then observed at 50x magnification using a stereomicroscope to check for plating defects. Samples where the underlying electrode layer was visible (with an occupancy rate of 5% or more) were considered to have plating defects.

[0149] <Experimental Data> Table 1 shows the results of measuring the atomic percentage of the main component metal of the underlying electrode layer on the surface of the organic layer, the number of cracks generated by the bending strength test, and the evaluation results of the number of plating defects for the samples of Examples 1 to 7 and Comparative Examples 1 to 5.

[0150] [Table 1]

[0151] Based on the above experimental results, good results were obtained for the samples of Examples 1 to 7, in which an organic layer was present on the surface of the underlying electrode layer and the atomic percentage of the main component metal of the underlying electrode layer on the surface of the organic layer was 3.0 atom% or less. Considering these experimental data, it is thought that good results can be obtained by setting the atomic percentage of the main component metal of the underlying electrode layer on the surface of the organic layer to 4.0 atom% or less. That is, by setting the atomic percentage of the main component metal of the underlying electrode layer on the surface of the organic layer to 4.0 atom% or less, the deposition of the plating layer provided on the underlying electrode layer is inhibited, the bonding area between the underlying electrode layer and the plating layer can be reduced, and good results can be obtained. It is more preferable that the atomic percentage of the main component metal of the underlying electrode layer on the surface of the organic layer be 3.0 atom% or less.

[0152] This reduces the adhesion between the base electrode layer and the plating layer, thereby promoting delamination between the base electrode layer and the plating layer formed on top of it. Consequently, when a multilayer ceramic capacitor is subjected to impact from a fall or thermal cycling, stable delamination between the base electrode layer and the plating layer becomes possible, allowing stress to be relieved. As a result, crack formation in the base material of the multilayer ceramic capacitor can be suppressed.

[0153] In Comparative Example 1, a sample in which the surface of the organic layer was not formed as a surface where a portion of the underlying electrode layer was exposed, the atomic percentage of the main component metal of the underlying electrode layer on the surface of the organic layer was 0.0 atom%, resulting in plating defects. It is preferable that the surface of the organic layer be formed as a surface where a portion of the underlying electrode layer is exposed, and it is more preferable that the atomic percentage of the main component metal of the underlying electrode layer on the surface of the organic layer be 0.6 atom% or more. This can also suppress the occurrence of plating defects. Specifically, it is preferable that the atomic percentage of the main component metal of the underlying electrode layer on the surface of the organic layer be 0.6 atom% or more and 4.0 atom% or less. Furthermore, it is more preferable that the atomic percentage of the main component metal of the underlying electrode layer on the surface of the organic layer be 0.6 atom% or more and 3.0 atom% or less.

[0154] <1> A laminate comprising a plurality of alternately stacked ceramic layers and a plurality of internal conductor layers, having a first main surface and a second main surface facing each other in the height direction, a first side surface and a second side surface facing each other in the width direction perpendicular to the height direction, and a first end surface and a second end surface facing each other in the length direction perpendicular to the height direction and the width direction, It comprises an external electrode connected to the internal conductor layer, The external electrode comprises a first external electrode disposed on the first end face and a second external electrode disposed on the second end face. The first external electrode comprises a first base electrode layer disposed on the first end face, a first organic layer disposed on the first base electrode layer, and a first plating layer disposed on the first organic layer. The second external electrode comprises a second base electrode layer disposed on the second end face, a second organic layer disposed on the second base electrode layer, and a second plating layer disposed on the second organic layer. The surface of the first organic layer is formed as a surface in which a portion of the first underlying electrode layer is exposed. The surface of the second organic layer is formed as a surface in which a portion of the second underlying electrode layer is exposed. On the surface of the first organic layer, the atomic percentage of the main component metal of the first underlay electrode layer is 4.0 atom% or less. A multilayer ceramic electronic component in which, on the surface of the second organic layer, the atomic percentage of the main component metal of the second underlay electrode layer is 4.0 atom% or less. <2> On the surface of the first organic layer, the atomic percentage of the main component metal of the first underlay electrode layer is 0.6 atom% or more. On the surface of the second organic layer, the atomic percentage of the main component metal of the second underlying electrode layer is 0.6 atom% or more. <1> Multilayer ceramic electronic components as described above. <3> The main component metal of the first base electrode layer and the main component metal of the second base electrode layer are Cu. <1> or <2> Multilayer ceramic electronic components as described above. <4> The first organic layer and the second organic layer are organosilicon compounds. <1> ~ <3> A multilayer ceramic electronic component as described in any one of the following. <5> The plurality of internal conductor layers include a plurality of first internal conductor layers drawn out to the first end face and a plurality of second internal conductor layers drawn out to the second end face. The first external electrode is connected to the first internal conductor layer, The second external electrode is connected to the second internal conductor layer. <1> ~ <4> A multilayer ceramic electronic component as described in any one of the following. <6> The aforementioned external electrode further has a third external electrode, The plurality of internal conductor layers include a plurality of first internal conductor layers drawn out to the first end face and the second end face, and a plurality of second internal conductor layers drawn out to at least one of the first side surface or the second side surface. The first external electrode is connected to the first internal conductor layer drawn out to the first end face, The second external electrode is connected to the first internal conductor layer drawn out to the second end face, The third external electrode is connected to the second internal conductor layer. <1> ~ <4> A multilayer ceramic electronic component as described in any one of the following. [Explanation of Symbols]

[0155] 1. Multilayer ceramic capacitor (multilayer ceramic electronic component) 10 Laminate 20 Dielectric layer (ceramic layer) 30. Internal electrode layer (internal conductor layer) 40 External electrode 40A First external electrode 40B Second external electrode 50A First base electrode layer 50B Second Underlay Electrode Layer 60A First plating layer 60B Second plating layer 70A First organic layer 70B Second Organic Layer L (Length direction) LS1 First end face LS2 Second end face T (height direction) TS1 First main surface TS2 Second main surface W (width direction) WS1 First Aspect WS2 Second Aspect

Claims

1. A laminate comprising a plurality of alternately stacked ceramic layers and a plurality of internal conductor layers, having a first main surface and a second main surface facing each other in the height direction, a first side surface and a second side surface facing each other in the width direction perpendicular to the height direction, and a first end surface and a second end surface facing each other in the length direction perpendicular to the height direction and the width direction, It comprises an external electrode connected to the internal conductor layer, The external electrode comprises a first external electrode disposed on the first end face and a second external electrode disposed on the second end face. The first external electrode comprises a first base electrode layer disposed on the first end face, a first organic layer disposed on the first base electrode layer, and a first plating layer disposed on the first organic layer. The second external electrode comprises a second base electrode layer disposed on the second end face, a second organic layer disposed on the second base electrode layer, and a second plating layer disposed on the second organic layer. The surface of the first organic layer is formed as a surface in which a portion of the first underlying electrode layer is exposed. The surface of the second organic layer is formed as a surface in which a portion of the second underlying electrode layer is exposed. On the surface of the first organic layer, the atomic percentage of the main component metal of the first underlay electrode layer is 4.0 atom% or less. A multilayer ceramic electronic component in which, on the surface of the second organic layer, the atomic percentage of the main component metal of the second underlay electrode layer is 4.0 atom% or less.

2. On the surface of the first organic layer, the atomic percentage of the main component metal of the first underlay electrode layer is 0.6 atom% or more. The multilayer ceramic electronic component according to claim 1, wherein the atomic percentage of the main component metal of the second underlay electrode layer on the surface of the second organic layer is 0.6 atom% or more.

3. The multilayer ceramic electronic component according to claim 1 or claim 2, wherein the main component metal of the first base electrode layer and the main component metal of the second base electrode layer are Cu.

4. The multilayer ceramic electronic component according to claim 1 or 2, wherein the first organic layer and the second organic layer are organosilicon compounds.

5. The plurality of internal conductor layers include a plurality of first internal conductor layers drawn out to the first end face and a plurality of second internal conductor layers drawn out to the second end face. The first external electrode is connected to the first internal conductor layer, The multilayer ceramic electronic component according to claim 1 or 2, wherein the second external electrode is connected to the second internal conductor layer.

6. The aforementioned external electrode further has a third external electrode, Each of the multiple internal conductor layers comprises a plurality of first internal conductor layers drawn out to the first end face and the second end face, and a plurality of second internal conductor layers drawn out to at least one of the first side surface or the second side surface. The first external electrode is connected to the first internal conductor layer drawn out to the first end face, The second external electrode is connected to the first internal conductor layer that is drawn out to the second end face. The multilayer ceramic electronic component according to claim 1 or 2, wherein the third external electrode is connected to the second internal conductor layer.

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