Memory system and address matching method

Abstract

To provide a memory system and an address collation method that can determine the validity of an address received from a host.SOLUTION: According to embodiments, a memory system includes a non-volatile memory and a controller. The controller is capable of communicating with a host and controls the non-volatile memory. When a read command including a logical address indicating a logical location on the non-volatile memory and first information associated with the logical address is received from the host, the controller determines the validity of the first information for the logical address.SELECTED DRAWING: Figure 4

Description

Technical Field

[0001] Embodiments of the present invention relate to a memory system and an address collation method.

Background Art

[0002] In recent years, memory systems equipped with non-volatile memories, such as UFS (Universal Flash Storage) devices and SSDs (Solid State Drives) equipped with NAND flash memories (NAND memories), have been widely used. In this type of memory system, a controller that controls the non-volatile memory associates a physical address indicating a physical position on the non-volatile memory with a logical address indicating a logical position on the non-volatile memory used by the host, and performs reading and writing of data to the non-volatile memory in response to a host request.

[0003] The memory system manages an address translation table that holds the correspondence between logical addresses and physical addresses, and refers to this address translation table each time to convert the logical address specified by the host into a physical address. The conversion from a logical address to a physical address or from a physical address to a logical address is called address resolution, etc.

[0004] The data volume of the address translation table has been increasing enormously as the capacity of the non-volatile memory expands. The fact that the data volume of the address translation table becomes enormous can be a factor that deteriorates the read performance of the memory system, etc. For this reason, a standard has been established that allows the host to hold a part of the address translation table and perform address resolution by the host, thereby removing the load of address resolution from the memory system (for example, JESD220-3 "Universal Flash Storage (UFS) Host Performance Booster (HPB) Extension").

[0005] A host compliant with this standard, for example, when issuing a read command, appends to the read command the physical address associated with that logical address (strictly speaking, any information that can identify the physical address in the memory system is acceptable, and is not limited to the physical address itself) in addition to the logical address. The memory system controller uses the physical address received from the host to read data from the non-volatile memory. [Prior art documents] [Patent Documents]

[0006] [Patent Document 1] Special Publication No. 2016-506585 [Patent Document 2] Japanese Patent Publication No. 2009-211234 [Patent Document 3] U.S. Patent Application Publication No. 2013 / 0191580 [Overview of the project] [Problems that the invention aims to solve]

[0007] One embodiment of the present invention provides a memory system and an address matching method that can determine the validity of an address received from a host. [Means for solving the problem]

[0008] According to the embodiment, the memory system comprises a non-volatile memory and a controller. The controller is In response to a request from the host, A logical address that indicates a logical location on non-volatile memory, Based on an address translation table that maintains the correspondence between physical addresses, which indicate the physical location on non-volatile memory, The first piece of information associated with a logical address The system generates and sends to the host, and for logical addresses where data has been written and a physical address is associated, it generates first information including identification information indicating that data has been written and the associated physical address; for logical addresses where data has not been written and a physical address is not associated, it generates first information including identification information indicating that data has not been written and the logical address for which no physical address is associated; and the logical address and the first information When a read command containing the above is received from the host, the validity of the first piece of information for the logical address is determined. If the identification information contained in the first piece of information within the read command indicates that the data has not been written, the validity is determined by comparing the logical address contained in the read command with the logical address contained in the first piece of information within the read command. do. [Brief explanation of the drawing]

[0009] [Figure 1] A diagram showing an example configuration of the memory system of the first embodiment. [Figure 2] This figure shows an example of storing a logical address in a redundant area of ​​non-volatile memory in the memory system of the first embodiment. [Figure 3] A sequence diagram showing the operation flow when a read command is received from the host in a comparative example memory system. [Figure 4] The first sequence diagram shows the flow of operations when a read command is received from the host in the memory system of the first embodiment (in the case of address matching). [Figure 5] The second sequence diagram shows the flow of operations when a read command is received from the host in the memory system of the first embodiment (in the case of address matching (mismatch)). [Figure 6] A diagram showing an example of address information generated in the memory system of the second embodiment. [Figure 7] The first sequence diagram shows the operation flow when a read command with an unwritten logical address is received from the host in the memory system of the second embodiment (in the case of address matching). [Figure 8] Figure 1 shows an example of a read command issued by a host in the memory system of the second embodiment (in the case of address matching). [Figure 9] The first sequence diagram shows the operation flow when a read command with an unwritten logical address is received from the host in the memory system of the second embodiment (in the case of address matching (mismatch)). [Figure 10] Figure 2 shows an example of a read command issued by a host in the memory system of the second embodiment (in the case of address matching (mismatch)). [Modes for carrying out the invention]

[0010] The embodiments will be described below with reference to the drawings.

[0011] (First Embodiment) First, the first embodiment will be described.

[0012] FIG. 1 is a diagram showing a configuration example of the memory system 1 according to the first embodiment. In FIG. 1, an example of a connection between the memory system 1 and the host 2 is also shown.

[0013] The memory system 1 includes a memory controller 11 and a non-volatile memory 12.

[0014] The memory controller 11 controls the non-volatile memory 12. The memory controller 11, for example, executes writing of data to the non-volatile memory 12 and reading of data from the non-volatile memory 12 in response to commands from the host 2. The memory controller 11 may autonomously execute writing of data to the non-volatile memory 12 and reading of data from the non-volatile memory 12 without depending on commands from the host 2 for optimization of the non-volatile memory 12 or the like.

[0015] The non-volatile memory 12 is, for example, a NAND memory. Here, it is assumed that the memory system 1 is realized as a UFS device.

[0016] The host 2 is a portable device such as a smartphone or a tablet terminal that uses the memory system 1 as a storage. The host 2 includes a CPU (Central Processing Unit) 21 and a main memory 22.

[0017] The CPU 21 loads various programs from the non-volatile memory 12 of the memory system 1 into the main memory 22 of the host 2 and executes them. Among the various programs, there are application programs including an OS (Operating System) and utilities that operate under the OS. The host 2 that executes these various programs by the CPU 21 issues read commands and write commands to the memory system 1 based on the descriptions of the various programs.

[0018] Main memory 22 is, for example, DRAM (Dynamic RAM [Random Access Memory]). Various programs and data are stored in main memory 22 as the CPU 21's workspace. This data includes information (hereinafter referred to as address information) that is associated with logical addresses indicating logical locations on non-volatile memory 12. Address information is generated by the memory system 1 based on an address translation table that maintains the correspondence between logical addresses and physical addresses indicating physical locations on non-volatile memory 12. Address information includes physical addresses.

[0019] The logical location on the non-volatile memory 12 refers to a location within the logical address space provided by the memory system 1 to the host 2. The physical address space is a concept corresponding to the logical address space. Therefore, it is also possible to understand that a logical address indicates a location within the logical address space, and a physical address indicates a location within the physical address space.

[0020] Address information on main memory 22 is obtained by host 2 requesting it from memory system 1 as needed. When host 2 reads data from memory system 1, it issues a read command to memory system 1, adding the address information associated with the logical address in addition to the logical address. Upon receiving this read command, the memory controller 11 of memory system 1 reads data from non-volatile memory 12 using the physical address in the address information specified in the read command, without performing address translation from logical address to physical address which would require referring to the address translation table.

[0021] In other words, both the memory system 1 of the first embodiment and the host 2 that uses the memory system 1 as storage comply with a standard that allows the host 2 to perform address resolution on behalf of the memory system 1.

[0022] Here, it is assumed that the logical address specified by host 2 when issuing read or write commands to memory system 1 is an LBA (Logical Block Address). Logical addresses are allocated in units of, for example, 4K bytes within the logical address space. Address information is exchanged between memory system 1 and host 2 in units of, for example, 16M bytes. In other words, host 2 can store address information for 4000 consecutive logical addresses in main memory 22.

[0023] When Host 2 reads data from a logical address, it checks whether the address information associated with that logical address is stored in main memory 22. If the address information is stored in main memory 22, it adds the logical address and address information to the read command and issues the read command to memory system 1. Note that the address information received from memory system 1 is uninterpretable (unnecessary) data for Host 2. When issuing a read command, Host 2 reads the address information associated with the target logical address from main memory 22 and adds it to the read command. If the address information associated with the target logical address is not stored in main memory 22, Host 2 obtains address information for the 16 MB area containing that logical address from memory system 1 again.

[0024] Incidentally, when host 2 reads data from a certain logical address, there is a risk that, due to some malfunction, it may issue a read command with address information associated with a different logical address instead of the original address information associated with that logical address. In this case, the memory controller 11 of memory system 1 will read the wrong data from the non-volatile memory 12 and send it to host 2.

[0025] Therefore, the memory system 1 of the first embodiment includes a mechanism for determining the validity of the address information received from the host 2. This point will be described in detail below.

[0026] Figure 2 shows an example of storing a logical address in the redundant area of ​​the non-volatile memory 12 in the memory system 1 of the first embodiment.

[0027] Here, we assume that logical addresses are allocated in 4K byte units within the logical address space. This 4K byte unit is derived from the unit of use of the non-volatile memory 12. The data storage area of ​​the non-volatile memory 12 is (4K + α) bytes per partition, and a physical address is assigned to each partition. In other words, each partition has a 4K byte storage area for the data itself, plus an α-byte redundant area. Multiple pieces of control information related to the data itself can be stored in the redundant area of ​​the non-volatile memory 12. Various pieces of information related to the data itself include, for example, identification information indicating the type of data itself, and an index for referencing internal management data.

[0028] When the memory controller 11 receives a write command with a logical address attached from the host 2, it selects one unused data storage area partition and stores the host's write data in the data storage area of ​​that partition. At the same time, the memory controller 11 stores the logical address specified by the host 2 in the redundant area of ​​that partition. The redundant area has a capacity that is, for example, an integer multiple of 4 bytes, and the memory controller 11 stores various information about the data body, including the logical address, in the redundant area, each consisting of 4 bytes. In Figure 2, the hatched area within the redundant area, indicated by the symbol a1, is the area where the logical address is stored when data is written. For example, when the memory controller 11 receives a write command from the host 2 to store write data 0 at logical address 0, the memory controller 11 stores write data 0 in the storage area assigned to physical address 0. At this time, the memory controller 11 stores logical address 0 in the redundant area corresponding to the storage area assigned to physical address 0.

[0029] When the memory controller 11 receives a read command from host 2 that includes a logical address and address information associated with that logical address, it uses that address information to read data from the non-volatile memory 12. At that time, the memory controller 11 obtains the read data from the data storage area and the logical address from the redundant area. The memory controller 11 compares the logical address specified by host 2 with the logical address read from the non-volatile memory 12 based on the address information specified by host 2. If the two match, the memory controller 11 determines that the address information specified by host 2 is valid for the logical address specified by host 2. If the two do not match, the memory controller 11 determines that the address information specified by host 2 is invalid for the logical address specified by host 2.

[0030] First, referring to Figure 3, we will explain the operation flow when a read command is received from the host in a comparative example memory system.

[0031] First, the host issues an address acquisition command to the memory system to obtain address translation (1). Upon receiving this command, the memory controller of the memory system instructs the non-volatile memory to output a portion of the address translation table corresponding to the address information requested by the host (2). When the memory controller receives a portion of the address translation table from the non-volatile memory (3), it generates address information based on that portion of the address translation table and sends it to the host (4).

[0032] Subsequently, the host issues a read command to the memory system using the address information received from the memory system, adding the logical address (A), size (B), and address information (C) (5). The size (B) is, for example, 1 for 4K bytes and 2 for 8K bytes (4K bytes x 2).

[0033] Upon receiving this command, the memory controller of the memory system uses the specified address information (C) to instruct the non-volatile memory to output the data requested by the host (6). When the data is output from the non-volatile memory in response to this instruction (7), the memory controller sends the data to host 2 as read data (8).

[0034] In this comparative example memory system, even if the address information specified by the host is incorrect, the data read from the non-volatile memory using that incorrect address information will be sent to the host.

[0035] Based on the operation flow of the memory system in the comparative example described above, the operation flow when the memory system 1 of the first embodiment receives a read command from the host 2 will now be explained with reference to Figure 4. Figure 4 includes the operation flow of the memory system 1 when the address matching result is a match. When the address matching result is a match, it means that the host 2 has accurately read the address information associated with the target logical address from the main memory 22 and added it to the read command.

[0036] First, host 2 issues an address acquisition command to the memory system to obtain address information (1). Upon receiving this command, the memory controller 11 of memory system 1 instructs the non-volatile memory 12 to output a portion of the address translation table corresponding to the address information requested by host 2 (2). When the memory controller 11 receives a portion of the address translation table from the non-volatile memory 12 (3), it generates address information based on that portion of the address translation table and sends it to host 2 (4).

[0037] Subsequently, host 2 issues a read command to memory system 1, adding the logical address (A), size (B), and address information (C) using the address information received from memory system 1 (5). Up to this point, it is the same as the memory system in the comparative example described above.

[0038] Upon receiving this command, the memory controller 11 of memory system 1 instructs the non-volatile memory 12 to output the data requested by host 2 using the physical address in the specified address information (C) (6). At the same time, the memory controller 11 also instructs the output of the data (logical address) stored in the redundant area.

[0039] When data is output from the non-volatile memory 12 in response to this instruction (7), the memory controller 11 performs an address match (8) by comparing the logical address specified in the read command with the logical address read from the redundant area of ​​the non-volatile memory 12. If the two logical addresses match, the memory controller 11 sends the data output from the non-volatile memory (the data itself) to the host 2 as read data (9).

[0040] Next, referring to Figure 5, we will explain the flow of operations when the address matching result is a mismatch. An example of a case where the address matching result is a mismatch is when host 2 reads address information from main memory 22 that is associated with a logical address different from the target logical address and adds it to the read command.

[0041] Steps (1) through (7) are the same as in Figure 4, so their explanation is omitted. The memory controller 11 performs address matching, comparing the logical address specified by the read command with the logical address read from the redundant area of ​​the non-volatile memory 12. If the memory controller 11 finds that the two logical addresses do not match (8), the memory controller 11 instructs the non-volatile memory 12 to output a portion of the address translation table containing the logical address specified by the read command (9). Once a portion of the address translation table is output from the non-volatile memory 12 (10), the memory controller 11 obtains the physical address associated with the logical address specified by the read command from the address translation table, and then uses the obtained physical address to instruct the non-volatile memory 12 to output data (11). The memory controller 11 sends the data output from the non-volatile memory (the data itself) to the host 2 as read data (12).

[0042] After a portion of the address translation table has been output (10), the memory controller 11 may further perform address matching by comparing the logical address specified in the read command with the logical address written to the redundant area of ​​the data read according to the physical address. If the two logical addresses match, the memory controller 11 uses the acquired physical address to instruct the non-volatile memory 12 to output data. If the two logical addresses do not match, the memory controller 11 sends an error response to the host 2.

[0043] As described above, in the memory system 1 of the first embodiment, by storing logical addresses in the redundant area of ​​the non-volatile memory 12, the validity of the address information specified in the read command can be determined for the logical address specified in the read command without degrading the read performance of the memory system 1.

[0044] Furthermore, even if the address information specified by host 2 is incorrect, the correct data can be read from the non-volatile memory 12 using the original address information associated with the logical address specified by host 2, and provided to host 2.

[0045] (Second Embodiment) Next, a second embodiment will be described.

[0046] Similar to the memory system 1 of the first embodiment, the memory system 1 of the second embodiment is assumed to be implemented as a UFS device. The configuration of the memory system 1 of the second embodiment is the same as that of the memory system 1 of the first embodiment, and redundant explanations are omitted. The same reference numerals are used for the same components as in the first embodiment.

[0047] In the first embodiment, the memory controller 11 of the memory system 1 stores a logical address in the redundant area of ​​the non-volatile memory 12 when writing data. When reading data, the memory controller 11 uses this logical address to determine whether the address information attached to the read command by the host 2 is correct.

[0048] Incidentally, host 2 may issue read commands to read data from areas in the logical address space where no data has been written, for example, to test memory system 1. Alternatively, such read commands may be issued when host 2 performs sequential access to a contiguous area in the logical address space that contains areas where no data has been written.

[0049] In the data storage area of ​​the non-volatile memory 12, in the partitions where data is not stored in the data storage area, the logical address is not stored in the redundant area. Therefore, even if incorrect address information is attached to a read command that specifies a logical address where data has not been written, the validity of that address information cannot be determined because there is no information to compare it with against the specified logical address.

[0050] Therefore, the memory system 1 of the second embodiment is equipped with a mechanism to determine the validity of the address information received from the host 2, even for read commands that have a logical address to which no data has been written, and this point will be described in detail below.

[0051] As described in the first embodiment, the address information generated by the memory system 1 based on the address translation table is data that is uninterpretable (unnecessary) for the host 2. In other words, the address information generated by the memory system 1 based on the address translation table is data that can be arbitrarily generated by the memory system 1.

[0052] In the memory system 1 according to the second embodiment, the memory controller 11 is requested by the host 2 to provide address information corresponding to a logical address. When generating this address information, the memory controller 11 determines whether data is written at the target logical address based on the address translation table. For a logical address where data is written, the memory controller 11 generates address information including identification information (written flag) indicating that the data has been written and the physical address associated with the logical address on the address translation table. On the other hand, for a logical address where data is not written, the memory controller 11 generates address information including identification information indicating that the data has not been written and the logical address instead of the physical address.

[0053] FIG. 6 is a diagram showing an example of the address information generated by the memory controller 11 according to the second embodiment.

[0054] In the example of FIG. 6, data is written at logical address 0 (“1”), and physical address 0 is associated with it. On the other hand, data is not written at logical address 1 (“0”), and as a result, logical address 1 is included in the address information instead of the physical address. For example, if the logical address and the physical address are each composed of N bits and only M (M < N) bits of the N bits are substantially used, the memory controller 11 may utilize a part or all of the (N - M) free bits as the written flag.

[0055] Based on the configuration of the address information shown in FIG. 6, next, referring to FIG. 7, the flow of operations when the memory system 1 in the second embodiment receives a read command from the host 2 will be described. FIG. 7 includes the flow of operations of the memory system 1 when a logical address with unwritten data is added to the read command and the result of the address verification is a match.

[0056] First, host 2 issues an address acquisition command to the memory system to obtain address information (1). Upon receiving this command, the memory controller 11 of memory system 1 instructs the non-volatile memory 12 to output a portion of the address translation table corresponding to the address information requested by host 2 (2). When the memory controller 11 receives a portion of the address translation table from the non-volatile memory 12 (3), it generates address information based on that portion of the address translation table. At this time, the memory controller 11 includes identification information indicating whether or not data has been written to the address information (4). In addition, for logical addresses where data has not been written, the memory controller 11 includes the logical address in the address information instead of the physical address. Needless to say, for logical addresses where data has already been written, the memory controller 11 includes the physical address associated with it in the address translation table in the address information. The memory controller 11 then sends the address information generated as described above to host 2 (5).

[0057] Subsequently, host 2 issues a read command to memory system 1 using the address information received from memory system 1, adding the logical address (A), size (B), and address information (C) (6). As mentioned above, host 2 simply reads the address information (C) associated with the logical address (A) from main memory 22 and adds it. Figure 8 shows an example of a read command issued by host 2 in the second embodiment.

[0058] Figure 8(A) shows an example of a read command to read data from logical address 0, where data has already been written. The address information (C) includes identification information indicating that data has already been written, and physical address 0, which is associated with logical address 0. On the other hand, Figure 8(B) shows an example of a read command to read data from logical address 1, where data has not yet been written. The address information (C) includes identification information indicating that data has not yet been written, and logical address 1, which replaces the physical address.

[0059] When the memory controller 11 of the memory system 1 receives a read command from host 2, it first determines whether the identification information in the address information indicates that the data has been written or that the data has not yet been written. Here, we assume that the identification information indicates that the data has not yet been written, as in the command shown in Figure 8(B).

[0060] Returning to Figure 7, if the identification information indicates that the data is unwritten, the memory controller 11 compares the logical address specified in the read command with the logical address included in the address information (7). If the two logical addresses match, the memory controller 11 determines that the correct address information has been specified, creates data in a predetermined pattern as the data to be read from the unwritten logical address (8), and sends it to the host 2 as read data (9). The data in the predetermined pattern is, for example, data in which all bits are 0.

[0061] Furthermore, when a command is received that indicates, as shown in Figure 8(A), that the data has already been written, the data is read from the non-volatile memory 12 using the physical address included in the address information, as described in the first embodiment, and a match is performed using the logical address stored in the redundant area.

[0062] Next, referring to Figure 9, we will explain the flow of operations when a logical address with no data written to it is specified and the address matching result is a mismatch. Figure 10(A) shows an example of a read command in which the address matching is a mismatch. The read command shown in Figure 10(A) specifies logical address 1 with no data written to it as logical address (A), but specifies the address information of logical address X with no data written to it, rather than the address information of logical address 1.

[0063] Steps (1) through (6) are the same as in Figure 7, so their explanation is omitted. The memory controller 11 performs address matching, comparing the logical address specified by the read command with the logical address included in the address information. If the memory controller 11 finds that the two logical addresses do not match (7), it instructs the non-volatile memory 12 to output a portion of the address translation table containing the logical address specified by the read command (8). When data is output from the non-volatile memory 12 in response to this instruction (9), the memory controller 11 determines the original write state of the logical address specified by the read command (10). If the logical address specified by the read command is in an unwritten state, the memory controller 11 creates data in the predetermined pattern described above (11) and sends it to the host 2 as read data (12).

[0064] Furthermore, while Figure 10(A) shows an example of a read command in which address information for another logical address where data has not yet been written is incorrectly appended, it is also possible that address information for another logical address where data has already been written may be incorrectly appended. The read command shown in Figure 10(B) specifies logical address 1, where data has not yet been written, as logical address (A), and specifies address information (identification information 1, physical address Y) where data has already been written, rather than the address information for that logical address 1. In this case, the memory controller 11 first reads the data from the non-volatile memory 12 using the physical address in that address information, and performs address matching using the logical address stored in the redundant area, similar to Figures 5(6) to (12) of the first embodiment.

[0065] As described above, in the memory system 1 of the second embodiment, it is also possible to determine the validity of the address information specified in a read command, even for read commands to which logical addresses with no data written are attached.

[0066] Furthermore, even if the address information specified by host 2 is incorrect, it is possible to verify the original address information associated with the logical address specified by host 2 and then provide host 2 with data in a predetermined pattern that should be read from the logical address where data has not yet been written.

[0067] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of Symbols]

[0068] 1...Memory system, 2...Host, 11...Memory controller, 12...Non-volatile memory, 21...CPU, 22...Main memory.

Claims

1. Non-volatile memory and A controller that can communicate with the host and controls the non-volatile memory, It is equipped with, The controller, in response to a request from the host, generates first information associated with the logical address based on an address translation table that maintains the correspondence between a logical address indicating a logical location on the non-volatile memory and a physical address indicating a physical location on the non-volatile memory, and transmits it to the host. For logical addresses to which data has been written and to which a physical address is associated, the first information is generated, which includes identification information indicating that the data has been written and the associated physical address. For logical addresses to which no data has been written and which are not associated with a physical address, the first information is generated, which includes identification information indicating that the data is not written and the logical address to which the physical address is not associated. When a read command including the logical address and the first information is received from the host, the validity of the first information with respect to the logical address is determined. If the identification information contained in the first information within the read command indicates that the data has not been written, the validity determination involves comparing the logical address contained in the read command with the logical address contained in the first information within the read command. Memory system.

2. The controller is Using the physical address contained in the first information, data is read from the non-volatile memory, along with the logical address recorded in the redundant area of ​​each partition of the non-volatile memory region to which the physical address is assigned. As part of the validity determination, the logical address included in the read command is compared with the logical address recorded in the redundant area. The memory system according to claim 1.

3. The aforementioned controller, If the logical address included in the read command matches the logical address recorded in the redundant area, the data read from the non-volatile memory is sent to the host. If the logical address included in the read command does not match the logical address recorded in the redundancy area, By referring to the address translation table that maintains the correspondence between the logical address and the physical address, the physical address corresponding to the logical address included in the read command is obtained. Using the acquired physical address, read data from the non-volatile memory. The data read from the non-volatile memory is transmitted to the host. The memory system according to claim 2.

4. The aforementioned controller, If the logical address included in the read command matches the logical address included in the first information within the read command, data in a predetermined pattern is generated and sent to the host. If the logical address included in the read command does not match the logical address included in the first information within the read command, Referencing the address translation table, determine whether data has been written to the logical address included in the read command. If data has already been written and a physical address is associated with a logical address included in the read command in the address translation table, the data is read from the non-volatile memory using the associated physical address and sent to the host. If no data has been written and no physical address is associated with the logical address included in the read command in the address translation table, the predetermined pattern of data is generated and sent to the host. The memory system according to claim 1.

5. The aforementioned controller, If the identification information contained in the first information within the read command indicates that the data has already been written, the data is read from the non-volatile memory using the physical address contained in the first information and sent to the host. The memory system according to claim 1.

6. The aforementioned controller, Using the physical address contained in the first information, data is read from the non-volatile memory, along with the logical address recorded in the redundant area of ​​each partition of the non-volatile memory region to which the physical address is assigned. In order to determine the validity, the logical address included in the read command is compared with the logical address recorded in the redundancy area. The memory system according to claim 5.

7. The aforementioned controller, If the logical address included in the read command matches the logical address recorded in the redundant area, the data read from the non-volatile memory is sent to the host. If the logical address included in the read command does not match the logical address recorded in the redundancy area, By referring to the address translation table that maintains the correspondence between the logical address and the physical address, the physical address corresponding to the logical address included in the read command is obtained. Using the acquired physical address, read data from the non-volatile memory. The data read from the non-volatile memory is transmitted to the host. The memory system according to claim 6.

8. The memory system according to claim 1, wherein the controller includes the identification information in the first information using a common free bit of the logical address and the physical address.

9. A method for address matching a controller that controls non-volatile memory and can communicate with a host, In response to a request from the host, first information associated with the logical address is generated based on an address translation table that maintains the correspondence between a logical address indicating a logical location on the non-volatile memory and a physical address indicating a physical location on the non-volatile memory, and this information is sent to the host. For logical addresses to which data has been written and to which a physical address is associated, the first information is generated, which includes identification information indicating that the data has been written and the associated physical address. For logical addresses to which no data has been written and which are not associated with a physical address, the first information is generated, which includes identification information indicating that the data is not written and the logical address to which the physical address is not associated. When a read command including the logical address and the first information is received from the host, the validity of the first information with respect to the logical address is determined. If the identification information contained in the first information within the read command indicates that the data has not been written, the address matching method for determining validity involves comparing the logical address contained in the read command with the logical address contained in the first information within the read command.

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