Method and apparatus for manufacturing semiconductor substrates and template substrates

Abstract

A semiconductor substrate comprising: a template substrate including a first seed region and a growth suppression region; and a first semiconductor part having a first base portion positioned above the first seed region and a first wing portion connected to the first base portion and positioned above the growth suppression region. The template substrate has a main substrate, a metal layer positioned above the main substrate, and an aluminum-based nitride layer positioned above the metal layer and containing argon. The first semiconductor part includes a nitride semiconductor.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor substrate, a template substrate, and a method and apparatus for manufacturing the template substrate.

Background Art

[0002] Patent Document 1 describes a technique in which an aluminum nitride (AlN) layer as a buffer layer is formed using a silicon (Si) substrate on which a mask for selective growth having an opening is formed, and then a gallium nitride (GaN) layer is selectively grown. In the method described in Patent Document 1, the AlN layer and the GaN layer are formed using the metalorganic chemical vapor deposition (MOCVD) method.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

[0004] A semiconductor substrate according to one aspect of the present disclosure includes a template substrate including a first seed region and a growth suppression region, and a first semiconductor portion having a first base portion located above the first seed region and a first wing portion connected to the first base portion and located above the growth suppression region. The template substrate includes a main substrate, a metal layer located above the main substrate, and an aluminum-based nitride layer located above the metal layer and containing argon. The first semiconductor portion includes a nitride semiconductor.

[0005] A semiconductor substrate in one aspect of the present disclosure comprises a template substrate including a first seed region and a growth inhibition region, and a first semiconductor portion having a first base portion located above the first seed region and a first wing portion connected to the first base portion and located above the growth inhibition region, wherein the template substrate has a main substrate and an aluminum nitride layer containing argon, the nitrogen polar surface of which is bonded to the main substrate, and the first semiconductor portion includes a nitride semiconductor.

[0006] A template substrate in one aspect of this disclosure comprises a main substrate, a metal layer located above the main substrate, and an aluminum nitride layer containing argon located above the metal layer.

[0007] A method for manufacturing a template substrate according to one aspect of the present disclosure is a method for manufacturing a template substrate including a main substrate, comprising the steps of forming a metal layer on top of the main substrate and forming an aluminum nitride layer on top of the metal layer using a sputtering method.

[0008] A method for manufacturing a template substrate according to one aspect of the present disclosure is a method for manufacturing a template substrate including a main substrate, comprising the steps of: forming a metal layer on a temporary substrate; forming an aluminum nitride layer above the metal layer using a sputtering method; and transferring the aluminum nitride layer from the temporary substrate to the main substrate. [Brief explanation of the drawing]

[0009] [Figure 1] This is a plan view schematically showing the configuration of a semiconductor substrate in one embodiment of the present disclosure. [Figure 2] This is a schematic cross-sectional view showing the configuration of a semiconductor substrate in one embodiment of the present disclosure. [Figure 3] This flowchart shows an example of a method for manufacturing a semiconductor substrate in one embodiment of the present disclosure. [Figure 4] This is a schematic cross-sectional view showing the configuration of a semiconductor substrate in another embodiment of the present disclosure. [Figure 5]A flowchart showing an example of a method for manufacturing a semiconductor substrate in another embodiment of the present disclosure. [Figure 6] A block diagram showing an example of a manufacturing apparatus in an embodiment of the present disclosure. [Figure 7] A cross-sectional view schematically showing the configuration of a template substrate in Example 1. [Figure 8] A cross-sectional view showing a method for manufacturing a template substrate in Example 1. [Figure 9] A cross-sectional view schematically showing the configuration of a semiconductor substrate in Example 1. [Figure 10] A cross-sectional view showing an example of lateral growth of a semiconductor portion. [Figure 11] A plan view showing another configuration example of a semiconductor substrate in Example 1. [Figure 12] A cross-sectional view showing another configuration example of a semiconductor substrate in Example 1. [Figure 13] A cross-sectional view showing another configuration example of a semiconductor substrate in Example 1. [Figure 14] A cross-sectional view showing another configuration example of a semiconductor substrate in Example 1. [Figure 15] A cross-sectional view showing another configuration example of a semiconductor substrate in Example 1. [Figure 16] A plan view showing another configuration example of a semiconductor substrate in Example 1. [Figure 17] A plan view showing a method for element isolation in Example 1. [Figure 18] A cross-sectional view showing a method for element isolation in Example 1. [Figure 19] A plan view showing another configuration example of a semiconductor substrate in Example 1. [Figure 20] A plan view schematically showing the configuration of a semiconductor substrate in Example 2. [Figure 21] A cross-sectional view schematically showing the configuration of a semiconductor substrate in Example 2. [Figure 22] A cross-sectional view showing an example of a method for manufacturing a semiconductor substrate in Example 2. [Figure 23]It is a cross-sectional view showing another configuration example of the semiconductor substrate in Example 2. [Figure 24] It is a cross-sectional view showing another configuration example of the semiconductor substrate in Example 2. [Figure 25] It is a cross-sectional view showing another configuration example of the semiconductor substrate in Example 2. [Figure 26] It is a cross-sectional view showing another configuration example of the semiconductor substrate in Example 2. [Figure 27] It is a cross-sectional view showing an example of a method for manufacturing a semiconductor substrate in Example 3. [Figure 28] It is a cross-sectional view showing an example of a method for manufacturing a template substrate of another configuration example in Example 3. [Figure 29] It is a cross-sectional view showing an example of a method for manufacturing a template substrate of another configuration example in Example 3. [Figure 30] It is a cross-sectional view showing an example of a method for manufacturing a semiconductor substrate in Example 4.

Embodiments for Carrying Out the Invention

[0010] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. However, the following description is for better understanding of the gist of the present disclosure and does not limit the present disclosure unless otherwise specified. The shapes and dimensions (lengths, widths, etc.) of the configurations shown in each drawing in this application do not necessarily reflect the actual shapes and dimensions, and are appropriately changed for clarity and simplification of the drawings.

[0011] 〔Semiconductor Substrate〕 FIG. 1 is a plan view schematically showing the configuration of a semiconductor substrate 10 in an embodiment of the present disclosure. FIG. 2 is a cross-sectional view schematically showing the configuration of the semiconductor substrate 10 in an embodiment of the present disclosure. Note that, as in FIG. 1 etc. in the present disclosure, for clarity of illustration, members may be hatched in the plan view, and the same applies to other drawings described below.

[0012] As shown in Figures 1 and 2, the semiconductor substrate 10 comprises a template substrate TS including a first seed region S1 and a growth suppression region DA, and a first semiconductor portion 8A located above the template substrate TS. The first semiconductor portion 8A has a first base portion B1 located above the first seed region S1, and a first wing portion F1 connected to the first base portion B1 and located above the growth suppression region DA. The template substrate TS has a main substrate 1, a metal layer ML located above the main substrate 1, and an aluminum nitride layer (Al-based nitride layer) 2 containing argon located above the metal layer ML. The first semiconductor portion 8A contains a nitride semiconductor.

[0013] In the semiconductor substrate 10 of this embodiment, the template substrate TS may have a mask pattern 6, and the mask pattern 6 may include a mask portion 5 that functions as a growth suppression region DA and a first opening K1 corresponding to the first seed region S1. Specifically, the surface (top surface) of the mask portion 5 may be the growth suppression region DA.

[0014] The first semiconductor section 8A may contain a nitride semiconductor as its main component. Nitride semiconductors can be expressed as, for example, AlxGayInzN (0≦x≦1;0≦y≦1;0≦z≦1;x+y+z=1), and specific examples include GaN-based semiconductors, AlN, InAlN (indium aluminum nitride), and InN (indium nitride). GaN-based semiconductors are semiconductors containing gallium atoms (Ga) and nitrogen atoms (N), and typical examples include GaN, AlGaN, AlGaInN, and InGaN.

[0015] The first semiconductor section 8A may be doped (e.g., n-type including a donor) or undoped. The term "semiconductor substrate" refers to a substrate containing a nitride semiconductor. The main substrate 1, the metal layer ML, and the Al-based nitride layer 2 are sometimes collectively referred to as the base substrate.

[0016] The main substrate 1 is a different type of substrate with a different lattice constant from the first semiconductor portion 8A, and the Al-based nitride layer 2 is a seed layer including the first seed region S1 and may be in contact with the first base portion B1. The Al-based nitride layer 2 may be, for example, an AlN layer. The first semiconductor portion 8A does not contain argon. Specifically, the surface (top surface) of the Al-based nitride layer 2 may be the first seed region S1.

[0017] The first semiconductor portion 8A can be formed on a template substrate TS by the ELO (Epitaxial Lateral Overgrowth) method. In the ELO method, for example, a different substrate with a different lattice constant from the nitride semiconductor can be used as the main substrate 1, and an inorganic compound film can be used as the mask portion 5, so that the first seed region S1 exposed at the first opening K1 can be used as the starting point for crystal growth. This allows for the formation of an initial growth layer on the first seed region S1, and then the first semiconductor portion 8A containing the nitride semiconductor can be grown laterally from the initial growth layer on the mask portion 5.

[0018] Of the first semiconductor portion 8A, the first base portion B1 located above the first opening K1 becomes a dislocation inheritance portion with many through-dislocations, while the first wing portion F1 located above the mask portion 5 becomes a low-defect portion with a smaller through-dislocation density compared to the dislocation inheritance portion.

[0019] The template substrate TS may have a first seed region S1 and a second seed region S2 adjacent to the first direction X1 via a growth inhibition region DA. The mask pattern 6 may include a second opening K2 corresponding to the second seed region S2. The template substrate TS may have a shape in which the first seed region S1 and the growth inhibition region DA, both aligned in the first direction X1, have their longitudinal direction aligned with the second direction X2, which is orthogonal to the first direction X1.

[0020] The semiconductor substrate 10 in this embodiment may include a second semiconductor portion 8C containing a nitride semiconductor. The second semiconductor portion 8C is located above the second seed region S2 and above the growth suppression region DA. The second semiconductor portion 8C may have a second base portion B2 located above the second seed region and a second wing portion F2 connected to the second base portion B2 and located above the growth suppression region DA. The first wing portion F1 and the second wing portion F2 may be aligned in the first direction X1 with a gap GP between them.

[0021] The second semiconductor portion 8C grows laterally on the mask portion 5, starting from the second seed region S2 exposed at the second opening K2, and its growth may be stopped before it meets the first semiconductor portion 8A. As a result, the semiconductor substrate 10 has a gap GP between the first semiconductor portion 8A and the second semiconductor portion 8C. As with the first semiconductor portion 8A described above, the second base portion B2 of the second semiconductor portion 8C located above the second opening K2 becomes a dislocation inheritance portion, and the second wing portion F2 located above the mask portion 5 becomes a low-defect portion.

[0022] Hereinafter, the first semiconductor section 8A and the second semiconductor section 8C may be collectively referred to as semiconductor section 8, the first base section B1 and the second base section B2 may be collectively referred to as base section B, and the first wing section F1 and the second wing section F2 may be collectively referred to as wing section F. Also, the first opening K1 and the second opening K2 of the mask pattern 6 may be collectively referred to as opening K, and the first seed region S1 and the second seed region S2 may be collectively referred to as seed region S. The semiconductor section 8 may be a semiconductor layer 8, and the mask section 5 may be a mask layer 5.

[0023] Furthermore, in the following, the orientation from the main substrate 1 to the semiconductor portion 8 will be referred to as "upward," and viewing the object with a line of sight parallel to the normal direction of the semiconductor substrate 10 (including the case of transparency) will be referred to as "planar view." The seed region S and the growth suppression region DA may be aligned in the first direction X1 (the direction perpendicular to the thickness direction of the substrate) in the planar view. The seed region S (e.g., the surface of the Al-based nitride layer 2) and the growth suppression region DA (e.g., the surface of the mask portion 5) may be at different positions (heights) in the thickness direction (vertical direction) of the semiconductor substrate 10, or they may be the same or approximately the same.

[0024] The first direction X1 may be the a-axis direction (<11-20> direction) of the semiconductor part 8 (nitride semiconductor crystal such as GaN). The second direction X2, which is orthogonal to the first direction X1, may be the m-axis direction (<1-100> direction) of the semiconductor part 8. The thickness direction of the semiconductor substrate 10 is the c-axis direction of the semiconductor part 8. <0001> It can be a direction.

[0025] In this embodiment, the semiconductor substrate 10 has a metal layer ML above the main substrate 1, and an Al-based nitride layer 2 is formed on the metal layer ML, which, for example, can reduce the warping of the semiconductor substrate 10. This will be explained in general terms along with an overview of the findings of this disclosure.

[0026] A conventional template substrate (hereinafter referred to as "conventional template substrate C" for convenience of explanation) has a base substrate having, for example, a silicon substrate, an AlN layer which is a buffer layer, an AlGaN layer which is a strain relaxation layer, and a GaN underlayment in this order. The conventional template substrate C has a mask pattern formed on the base substrate. The AlN layer is provided to prevent melting (meltback) between the silicon substrate and the GaN underlayment and to improve the quality of the GaN underlayment. Generally, the AlN layer is formed by the MOCVD method from the viewpoint of improving the quality as a buffer layer.

[0027] A semiconductor substrate manufactured by loading a conventional template substrate C into an MOCVD apparatus and depositing a GaN layer using the ELO method is prone to warping when the temperature is lowered from the deposition temperature, due to the difference in thermal expansion coefficients between the silicon substrate and the GaN layer. Conventional template substrate C uses an inexpensive silicon substrate while being formed using the MOCVD method, making it difficult to reduce manufacturing costs.

[0028] Incidentally, it is also possible to form an AlN layer on a silicon substrate using sputtering (physical vapor deposition) instead of MOCVD. However, conventionally, it has been difficult to form a high-quality AlN layer on a silicon substrate using sputtering. As a result of diligent research, the inventors have found that the quality of the AlN layer can be improved by forming a relatively thick metal layer ML on top of a main substrate 1 such as a silicon substrate, and then forming an AlN layer on the metal layer ML using sputtering. Until now, there has been no template substrate that uses a metal layer ML with a thickness of about 5 nm or more as a base for forming an AlN layer by sputtering, and the significance of such a template substrate was unknown.

[0029] The reason why the quality of the AlN layer improves by using a thicker metal layer ML as a growth substrate is thought to be that the crystalline state of the metal layer ML (lattice strain, residual stress, etc.) may affect the quality of the AlN layer. Furthermore, it was found that the quality of Al-based nitrides having a structure equivalent to AlN can also be improved by using a thicker metal layer ML as a growth substrate.

[0030] The metal layer ML may include a layer whose main component is Al (Al-based metal layer). Here, the main component refers to the metal element with the largest number of moles. The metal layer ML may also include one or more metals selected from the group consisting of aluminum, platinum, palladium, silver, gold, hafnium, scandium, yttrium, titanium, and zirconium, and may include any of the metals selected from the above group as its main component. The metal layer ML includes at least one metal whose (111) plane of a face-centered cubic lattice or body-centered cubic lattice, or its (0001) plane of a hexagonal close-packed lattice, is oriented toward the main surface 1a of the main substrate 1. The metal layer ML may also be an alloy.

[0031] The metal layer ML may be formed by sputtering, in which case the metal layer ML contains argon. By continuously forming the metal layer ML and the Al-based nitride layer 2 in a sputtering apparatus, the manufacturing efficiency of the template substrate TS can be increased.

[0032] When depositing an AlN layer using the conventional MOCVD method, the deposition process is carried out at a high temperature exceeding the melting point of the Al film as a metal layer, making it difficult to manufacture a template substrate TS with a metal layer ML. In contrast, the sputtering method allows for lower deposition temperatures, making it easier to manufacture a template substrate TS with a metal layer ML.

[0033] The metal layer ML may be positioned so as to overlap the entire upper surface (main surface 1a) of the main substrate 1 in a plan view taken in the direction normal to the main substrate 1. The Al-based nitride layer 2 may be positioned so as to overlap the mask portion 5. The thickness of the metal layer ML may be 20 nm or more, and may be between 100 nm and 2000 nm.

[0034] The Al-based nitride layer 2 contains at least aluminum and nitrogen. The Al-based nitride layer 2 may contain metals other than aluminum, for example, scandium (Sc) or zirconium (Zr). The Al-based nitride layer 2 may be, for example, AlScN or AlZrN. The Al-based nitride layer 2 may contain multiple metal species, in which case aluminum may have the largest content among the multiple metal species, or the content of aluminum may be greater than the total content of the other metal species.

[0035] The Al-based nitride layer 2 may be positioned so as to overlap the entire upper surface of the main substrate 1 in a plan view taken in the direction normal to the main substrate 1. Alternatively, the Al-based nitride layer 2 may be positioned so as to overlap the entire upper surface (surface MLS) of the metal layer ML in a plan view. The thickness of the Al-based nitride layer 2 may be, for example, 30 nm or more. The thickness of the Al-based nitride layer 2 may be greater than that of the metal layer ML, for example, between 30 nm and 500 nm.

[0036] In the semiconductor substrate 10 of this embodiment, the internal stress of the Al-based nitride layer 2 can be adjusted by adjusting the processing conditions of the sputtering method. For example, the Al-based nitride layer 2 contains argon that is mixed in when it is formed by the sputtering method. Therefore, by changing the argon content, the stress state of the Al-based nitride layer 2 at room temperature can be changed. For example, in the semiconductor substrate 10, at room temperature, the Al-based nitride layer 2 may be in a compressive stress state, and the semiconductor part 8 (first semiconductor part 8A) may be in a tensile stress state. In this case, the overall warpage of the semiconductor substrate 10 can be reduced, which is effective for subsequent processes (device layer formation, delamination, etc.). Also, in the semiconductor substrate 10, at room temperature, the Al-based nitride layer 2 and the semiconductor part 8 (first semiconductor part 8A) may be in a tensile stress state. If the lattice constant of the Al-based nitride layer 2 is smaller than the lattice constant of the semiconductor part 8, the tensile stress state of the Al-based nitride layer 2 widens the lattice spacing in the plane perpendicular to the c-axis, and the effect of the difference in lattice constants between the Al-based nitride layer 2 and the semiconductor part 8 is mitigated. As a result, the crystallinity of the semiconductor portion 8 (especially the base on the seed region S) can be increased. The metal layer ML and the Al-based nitride layer 2 may be in a tensile stress state. When the Al-based nitride layer 2 is an aluminum nitride layer (AlN layer), the proportion of impurity metal elements other than aluminum in the AlN layer to the total metal elements may be less than 0.5 atm%. Room temperature is typically room temperature, for example, 20°C or 25°C. The above stress states (compressive stress state and tensile stress state) are defined based on the state of internal stress generation in a plane with the first direction X1 and the second direction X2 as in-plane directions. The stress state in the height direction of the semiconductor substrate 10 and the stress state in the above plane with the first direction X1 and the second direction X2 as in-plane directions may differ from each other.

[0037] A template substrate TS with a relatively high-quality Al-based nitride layer 2 formed using a sputtering method can be manufactured, and then a semiconductor portion 8 can be deposited on the template substrate TS to produce a semiconductor substrate 10. The semiconductor portion 8 can be of a quality comparable to that of a conventional template substrate C having an AlN layer formed using the MOCVD method. The Al-based nitride layer 2 located between the main substrate 1 and the semiconductor portion 8 of the semiconductor substrate 10 relieves internal stress. This effectively reduces warping that occurs in the semiconductor substrate 10 at room temperature.

[0038] The semiconductor substrate 10 has a nitride semiconductor included in the semiconductor section 8 that is a GaN-based semiconductor, and the main substrate 1 of the template substrate TS may be a silicon substrate, a silicon carbide substrate, or a glass substrate. The Al-based nitride layer 2 may have a thermal expansion coefficient at 1000°C that is greater than that of the main substrate 1 and smaller than that of the semiconductor section 8 (first semiconductor section 8A).

[0039] The glass substrate described above only needs to be made of a material that has heat resistance to the film deposition temperature when forming the semiconductor portion 8 by the ELO method, and the material is not specifically limited. By using an inexpensive dissimilar substrate as the main substrate 1 and forming the template substrate TS by the sputtering method, the manufacturing cost of the template substrate TS can be effectively reduced.

[0040] [Method for manufacturing semiconductor substrates] Figure 3 is a flowchart showing an example of a method for manufacturing the semiconductor substrate 10 in this embodiment. The flowchart shown in Figure 3 also includes an example of a method for manufacturing the template substrate TS.

[0041] As shown in Figure 3, in the method for manufacturing the semiconductor substrate 10, first, a template substrate TS is formed. The method for manufacturing the template substrate TS includes the steps of forming a metal layer ML on top of the main substrate 1 (S10) and forming an Al-based nitride layer 2 on top of the metal layer ML using a sputtering method (S20). Next, a step of forming a mask pattern 6 including a mask portion 5 that functions as a growth suppression region DA on top of the Al-based nitride layer 2 (S30) may be performed. After that, the semiconductor substrate 10 can be manufactured by performing a step of forming a semiconductor portion 8 (S40). For example, the metal layer ML may be an aluminum layer, and the aluminum layer may be formed using a sputtering method.

[0042] [Another embodiment] Figure 4 is a schematic cross-sectional view showing the configuration of a semiconductor substrate 10 in another embodiment of the present disclosure. Figure 5 is a flowchart showing an example of a method for manufacturing a semiconductor substrate 10 in another embodiment of the present disclosure. As shown in Figures 4 and 5, the template substrate TS does not necessarily have to have a metal layer ML. Such a template substrate TS can be formed by forming the metal layer ML and the Al-based nitride layer 2 on a substrate (temporary substrate) separate from the main substrate 1, and then transferring the Al-based nitride layer 2 onto the main substrate 1. As the temporary substrate, a substrate made of a material suitable for forming the metal layer ML and the Al-based nitride layer 2 can be used.

[0043] In the example shown in Figure 4, the semiconductor substrate 10 comprises a template substrate TS including a first seed region S1 and a growth suppression region DA, and a first semiconductor portion 8A. The template substrate TS has a main substrate 1 and an Al-based nitride layer 2. The Al-based nitride layer 2 has a nitrogen polar surface bonded to the main substrate 1 and contains argon. The first semiconductor portion 8A contains a nitride semiconductor.

[0044] In this specification, the upper surface (growth surface) of the Al-based nitride layer 2 formed on the metal layer ML is referred to as the first surface 2a, and the surface located on the opposite side of the first surface 2a, i.e., the surface on which growth from the metal layer ML began, is referred to as the second surface 2b. In the example shown in Figure 4, the Al-based nitride layer 2 formed on the temporary substrate is transferred to the main substrate 1, so that the first surface 2a is the opposing surface facing the main substrate 1, and the second surface 2b is located on the side farther from the main substrate 1. The second surface 2b of the Al-based nitride layer 2 exposed at the opening K becomes the seed region S.

[0045] The first surface (upper surface) 2a of the Al-based nitride layer 2 grown on the metal layer ML using the c-plane can be an aluminum polar surface (Al polar surface). Furthermore, if the Al-based nitride layer 2 is grown on the metal layer ML using the -c-plane, the first surface 2a may be a nitrogen polar surface (N polar surface). For example, when the Al-based nitride layer 2 is formed on a temporary substrate by sputtering, the first surface 2a may be an N polar surface, and after transfer to the main substrate 1, the N polar surface may be bonded to the main substrate 1. These points will be explained in more detail in the examples described later.

[0046] In the example shown in Figure 5, the method for manufacturing the template substrate TS includes the steps of forming a metal layer ML on top of a temporary substrate (S100), forming an Al-based nitride layer 2 on top of the metal layer ML using a sputtering method (S200), and transferring the Al-based nitride layer 2 from the temporary substrate to the main substrate 1 (S250). For example, the main substrate 1 and the Al-based nitride layer 2 can be surface activated bonding. By removing the metal layer ML, the main substrate 1 and the Al-based nitride layer 2 can be separated from the temporary substrate. Then, a step of forming a mask pattern 6 on top of the Al-based nitride layer 2 (S300) may be performed. After that, a semiconductor substrate 10 can be manufactured by performing a step of forming a semiconductor part 8 (S400). For example, the metal layer ML may be an aluminum layer, and the aluminum layer may be formed using a sputtering method. In addition, after step S250, a semiconductor device can also be formed by performing steps such as electrode formation instead of steps S300 and S400.

[0047] In the template substrate TS manufactured by the manufacturing method shown in Figure 5, the Al-based nitride layer 2 is transferred from the temporary substrate to the main substrate 1, and therefore does not inherit the crystal structure of the main substrate 1 at the interface with the main substrate 1. The semiconductor substrate 10 may have a bonding mark at the interface between the Al-based nitride layer 2 and the main substrate 1. This bonding mark can be any trace of bonding between the main substrate 1 and the Al-based nitride layer 2 that indicates the difference between the Al-based nitride layer 2 that would have been epitaxially grown on the main substrate 1 and the Al-based nitride layer 2 that was transferred to the main substrate 1. The bonding mark is not particularly limited in its specific form, but for example, if the surface orientation of the main substrate 1 and the surface orientation of the first surface 2a of the Al-based nitride layer 2 are not aligned based on XRD measurement results, it can be determined that the above-mentioned bonding mark is present.

[0048] [Semiconductor substrate manufacturing equipment] Figure 6 is a block diagram showing an example of a manufacturing apparatus 50 in one embodiment of the present disclosure. The semiconductor substrate 10 manufacturing apparatus 50 shown in Figure 6 comprises apparatus A10 that performs the process in S10, apparatus A20 that performs the process in S20, apparatus A30 that performs the process in S30, apparatus A40 that performs the process in S40, and apparatus A50 that controls apparatuses A10 to A40. Apparatus A10 may perform the process in S100, and apparatus A20 may perform the process in S200. The manufacturing apparatus 50 may also include apparatus A25 that performs the process in S250. Apparatus A50 may control apparatus A25. Apparatus A30 may perform the process in S300, and apparatus A40 may perform the process in S400.

[0049] Devices A10 and A20 may each include a sputtering apparatus. The manufacturing apparatus 50 may also have a single device A12 having the functions of devices A10 and A20, and device A12 may include a sputtering apparatus. Device A50 may control device A12. Device A50 may include a processor and memory. Device A50 may also be configured to control devices A10 and A20 by executing a program stored in, for example, internal memory, a communicable communication device, or an accessible network, and this program and the recording medium on which this program is stored are also included in this embodiment.

[0050] [Semiconductor devices] The semiconductor portion 8 in the semiconductor substrate 10 has a wing portion F, which is a low-defect portion. A semiconductor device can be formed using the wing portion F. Specific examples of semiconductor devices include light-emitting elements (LED chips, semiconductor laser chips, etc.), light-emitting elements with submounted light-emitting elements, and light-emitting modules in which light-emitting elements are packaged. The semiconductor device is not limited to light-emitting semiconductor devices; for example, it may also be a photodetector (photodiode).

[0051] [Other Embodiments] Other embodiments of this disclosure are briefly described below. More details will be provided in the embodiments described later.

[0052] (a) The metal layer ML may be a single layer or a multi-layered layer containing the types of metals described above. If the metal layer ML is a multi-layered layer, at least one layer may contain aluminum as the main component, and the layer in contact with the Al nitride layer 2 (the uppermost layer) may contain aluminum as the main component. The metal layer ML may include a first layer made of a metallic material and a second layer made of a metallic material different from the first layer. Each of the first and second layers may contain one or more metals selected from the group consisting of aluminum, platinum, palladium, silver, gold, hafnium, scandium, yttrium, titanium, and zirconium.

[0053] (b) In the template substrate TS, the seed region S is only necessary as the starting point for the growth of the semiconductor portion 8, and the template substrate TS is only necessary as it has a seed region S above the main substrate 1 and a growth suppression region DA. The template substrate TS does not have to have, for example, a mask portion 5.

[0054] (c) In one example configuration, the semiconductor substrate 10 may include a metal nitride layer located between the metal layer ML and the Al-based nitride layer 2.

[0055] (d) The semiconductor substrate 10 in the above-described embodiment had a semiconductor portion 8 formed by the ELO method, but is not limited thereto. In another aspect of the present disclosure, the semiconductor substrate 10 does not need to have a mask pattern 6. The template substrate TS can be used to manufacture semiconductor devices other than optical systems, such as transistors such as HEMTs (High Electron Mobility Transistors) and elements for MEMS (Micro Electro Mechanical Systems) such as BAW (Bulk Acoustic Wave) filters.

[0056] (e) In one aspect of the present disclosure, the semiconductor substrate 10 may have a gap between the wing portion F and the mask portion 5 which is the growth suppression region DA, for example, the seed region S may be located above the growth suppression region DA in the thickness direction of the semiconductor substrate 10.

[0057] (f) In one aspect of the present disclosure, the semiconductor substrate 10 may have semiconductor portions 8 that grow laterally in opposite directions from adjacent first openings K1 and second openings K2 in the first direction X1, and these portions may be in contact (meet) on the mask portion 5. The semiconductor substrate 10 may not have a gap GP.

[0058] [Example 1] In the following, we will first describe the template substrate TS before forming the semiconductor portion 8, and then describe the semiconductor substrate 10.

[0059] (Template board) Figure 7 is a schematic cross-sectional view showing the configuration of the template substrate TS in Example 1. As shown in Figure 7, the template substrate TS in Example 1 may have the same schematic configuration as the template substrate TS in Embodiment 1 described above. The template substrate TS has a main substrate 1, a base substrate BS including a metal layer ML and an Al-based nitride layer 2, and a mask pattern 6 may be formed on the base substrate BS.

[0060] The main substrate 1 may be a silicon substrate or various types of glass substrates. The plane orientation of the main substrate 1 is, for example, the (111) plane of the silicon substrate. However, these are examples, and the main substrate 1 in Example 1 only needs to have a material and plane orientation that satisfies the following two conditions, and the specific material and plane orientation of the main substrate 1 are not necessarily limited. That is, firstly, the main substrate 1 should be capable of manufacturing a base substrate BS by forming a metal layer ML and an Al-based nitride layer 2 on top of the main substrate 1. Secondly, the main substrate 1 should be capable of growing a semiconductor portion 8 by the ELO method using a template substrate TS manufactured by forming a mask pattern 6 on top of the base substrate BS including the main substrate 1. By using an inexpensive substrate as the main substrate 1, the manufacturing costs of the template substrate TS and the semiconductor substrate 10 can be effectively reduced.

[0061] As the main substrate 1, which is a different type of substrate, a silicon carbide (SiC) substrate can be used. In this case, the surface orientation of the main substrate 1 may be the 6H-SiC(0001) or 4H-SiC(0001) plane of the SiC substrate. The main substrate 1 may also be 3C-SiC. If the use of an inexpensive substrate is not a concern, the main substrate 1 may be a sapphire substrate or a nitride substrate (such as a GaN substrate).

[0062] The metal layer ML may be formed on the main substrate 1. Alternatively, the metal layer ML may be formed above the main substrate 1, and a different layer made of a different material may be interposed between the main substrate 1 and the metal layer ML. In Example 1, the metal layer ML may overlap the entire main surface 1a of the main substrate 1 in a plan view. By having the metal layer ML and the Al-based nitride layer 2, the template substrate TS can reduce the possibility of a problem occurring where silicon and gallium react with each other at high temperatures (so-called meltback), even when a silicon substrate or the like is used as the main substrate 1.

[0063] In Example 1, the metal layer ML may be an Al layer, and the thickness of the metal layer ML is, for example, 20 nm or more. This improves the quality of the Al-based nitride layer 2 formed on the metal layer ML. The Al layer as the metal layer ML is formed from the main surface 1a of the main substrate 1 (for example, the (111) surface of the silicon substrate) and has a face-centered cubic structure. <111> It may be formed by growth in a direction, in which case the surface MLS on the side of the metal layer ML furthest from the main substrate 1 becomes the (111) plane in the face-centered cubic structure.

[0064] The Al-based nitride layer 2 has a wurtzite structure. Since the (111) plane in the face-centered cubic structure corresponds to the atomic arrangement of a hexagonal crystal system, the Al-based nitride layer 2 can be epitaxially grown in the c-axis direction from the surface MLS of the metal layer ML. At the interface between the Al-based nitride layer 2 and the metal layer ML, the surface MLS and the second surface 2b have corresponding plane orientations. Such an Al-based nitride layer 2 can be described as inheriting the crystal structure of the metal layer ML.

[0065] The metal layer ML may contain at least one metal whose (111) plane of a face-centered cubic or body-centered cubic lattice, or its (0001) plane of a hexagonal close-packed lattice, is oriented toward the main surface 1a of the main substrate 1. Examples of such metals include aluminum, as well as platinum, palladium, silver, gold, hafnium, scandium, yttrium, titanium, and zirconium. This allows the surface MLS of the metal layer ML to have a (111) plane of a face-centered cubic or body-centered cubic lattice, or a (0001) plane of a hexagonal close-packed lattice, making it easier to grow the Al-based nitride layer 2 from the surface MLS.

[0066] In the range where the thickness of the metal layer ML is 20 nm or more, increasing the thickness of the metal layer ML can improve the quality (e.g., orientation) of the Al-based nitride layer 2. The quality of the Al-based nitride layer 2 can be evaluated, for example, by measuring the X-ray rocking curve of the Al-based nitride layer 2 after deposition. When the thickness of the metal layer ML is around 1000 nm, the influence of the thickness of the metal layer ML on the quality of the Al-based nitride layer 2 may become less pronounced. The thickness of the metal layer ML may be between 20 nm and 2000 nm, or between 100 nm and 2000 nm.

[0067] According to our investigations, for example, when an AlN layer (Al-based nitride layer 2) is formed on an Al film (metal layer ML), and the relationship between the thickness of the Al film and the full width at half maximum (FWHM) of the X-ray rocking curve measurement of the AlN layer is investigated, it was found that the larger the thickness of the Al film, the smaller the FWHM and the better the quality of the AlN layer tended to be. Since the deposition time of the Al film (i.e., the thickness of the Al film) is related to the manufacturing cost, the thickness of the Al film can be set considering the balance between manufacturing cost and the quality of the AlN layer.

[0068] In Example 1, the Al-based nitride layer 2 may be an AlN layer, and the thickness of the AlN layer may be, for example, 30 nm or more. The thickness of the AlN layer may be greater than that of the Al film as the metal layer ML, and may be, for example, 30 nm or more and 500 nm or less.

[0069] In Example 1, the metal layer ML and the Al-based nitride layer 2 can be continuously formed in a sputtering apparatus using the sputtering method. Appropriate sputtering methods such as DC sputtering, RF sputtering, AC sputtering, DC magnetron sputtering, ECR (Electron Cyclotron Resonance) sputtering, RF magnetron sputtering, PSD (Pulse Sputter Deposition) method, and laser ablation method can be selected.

[0070] The metal layer ML formed by the sputtering method may contain argon originating from the argon gas introduced into the sputtering apparatus. Depending on the metal species contained in the metal layer ML, argon may be detected by SIMS (secondary ion mass spectrometry).

[0071] For example, the vacuum level inside the sputtering apparatus before film deposition is 3 × 10 -5 Pa or less or 1 × 10⁻⁶ -5 The pressure may be Pa or less. By pre-treating the main substrate 1 before starting the film deposition process, the organic layer and irregularities on the main surface 1a of the main substrate 1 may be removed, enabling the epitaxial growth of the metal layer ML. Specific examples of pre-treatment include reverse sputtering, acid treatment, and UV treatment. Reverse sputtering is a method of cleaning the main surface 1a of the main substrate 1 by colliding plasma atoms with the main substrate 1, and has the advantage of easily preventing the re-adhesion of impurities after treatment. The substrate temperature during film deposition may be room temperature, but the film quality can be further improved by performing the film deposition process while the main substrate 1 is heated. When heating the main substrate 1, the heating temperature can be adjusted according to the material of the metal layer ML; for example, the heating temperature may be 700°C to 900°C.

[0072] The Al-based nitride layer 2 is formed on the metal layer ML using a sputtering method, resulting in higher quality than if it were formed directly on the main substrate 1 using a sputtering method. The Al-based nitride layer 2 contains argon derived from the argon gas introduced into the sputtering apparatus. The argon content of the Al-based nitride layer 2 may be, for example, 0.01 atm% to 1.0 atm%.

[0073] When forming a metal layer ML and an Al-based nitride layer 2 using the sputtering method, the internal stress of the metal layer ML and the Al-based nitride layer 2 can be controlled by the deposition conditions. For example, by controlling the amount of argon incorporated into the film, the internal stress can be changed from compressive stress to tensile stress. This allows for adjustment of the stress relationship between the semiconductor portion 8 formed on the template substrate TS and the template substrate TS in the semiconductor substrate 10. As a result, warping of the semiconductor substrate 10 can be reduced.

[0074] The mask pattern 6 is formed on the base substrate BS using a material that suppresses the longitudinal growth (growth in the c-axis direction) of the nitride semiconductor, and enables the lateral growth (for example, growth in the a-axis direction) of the nitride semiconductor.

[0075] Examples of materials for the mask portion 5 of the mask pattern 6 include silicon nitride, silicon carbide, silicon carbonitride, diamond-like carbon, silicon oxide, and silicon oxynitride. Alternatively, materials that do not contain silicon, such as titanium nitride, molybdenum nitride, tungsten nitride, tantalum carbide, and high-melting-point metals (molybdenum, tungsten, platinum, etc.), can also be used for the mask portion 5. The mask portion 5 may be a single layer made of one of these materials, or a multilayer film combining multiple of these materials. The thickness of the mask portion 5 may be, for example, about 100 nm to 4 μm. The width Wm (size in the first direction X1) of the mask portion 5 may be, for example, 10 μm to 200 μm. In Example 1, the width Wm of the mask portion 5 may be smaller than the size in the first direction X1 of the metal layer ML or the Al-based nitride layer 2.

[0076] The opening K of the mask pattern 6 (exposed portion of the seed region S) serves as the growth starting point for the semiconductor portion 8. The opening K may have a longitudinal shape with the first direction X1 as the width direction and the second direction X2 (see Figure 1) as the longitudinal direction. The mask pattern 6 may have multiple openings K aligned in the first direction X1. The opening K may also have a tapered shape (a shape that narrows in width downwards). The width WK of the opening K (size in the first direction X1) can be, for example, about 0.1 μm to 20 μm. The width WK of the opening K may be smaller than the width Wm of the mask portion 5.

[0077] (Method of manufacturing a template substrate) Figure 8 is a cross-sectional view showing the manufacturing method of the template substrate TS in Example 1. For example, a silicon substrate (Si(111) plane) is used as the main substrate 1. An Al film can be formed on the silicon substrate by sputtering an Al target while introducing Ar gas in a sputtering apparatus. For example, the thickness of the Al film can be 100 nm, the Al film deposition temperature can be 400°C, the input power can be 500 W, and the back pressure during film deposition can be 0.3 Pa.

[0078] Next, by introducing a mixed gas of argon and nitrogen (for example, a gas ratio of about 1:1) into the sputtering apparatus and sputtering an Al target, an AlN film can be formed on the Al film. In this way, Al films and AlN films can be continuously deposited in the same chamber without having to remove or insert the substrate.

[0079] Generally, when an AlN film is epitaxially grown on a sapphire substrate, for example, the AlN film grows in the

[0001] direction, and the outermost surface becomes an Al polar surface. In contrast, in the template substrate TS of Example 1, the first surface 2a of the AlN film can be an N polar surface. This is thought to be because, on the Al film as the metal layer ML, the AlN film as the Al nitride layer 2 can be epitaxially grown from the surface MLS in the [000-1] direction. Furthermore, the first surface 2a of the Al nitride layer 2 may be an N polar surface, or it may be a surface in which Al polar surfaces and N polar surfaces are mixed (mixed polarity).

[0080] Next, a 300 nm thick mask layer MF (e.g., SiN) is formed on the Al nitride layer 2 using a sputtering method. Then, a resist is applied to the entire surface of the mask layer MF, and subsequently, the resist is patterned using a photolithography method to form a resist Z having multiple stripe-shaped openings approximately 3 μm wide. Subsequently, a portion of the mask layer MF is removed using a wet etchant such as hydrofluoric acid (HF) or buffered hydrofluoric acid (BHF) to create multiple openings K, and the resist Z is removed by organic washing to form the mask pattern 6.

[0081] If the Al-based nitride layer 2 is deposited by the MOCVD method, the GaN layer may also be deposited within the MOCVD apparatus. Therefore, Ga may be present within the MOCVD apparatus, and in this case, Ga may adhere to the main substrate 1. If meltback occurs due to the adhered Ga, the yield will decrease. Consequently, maintenance of the MOCVD apparatus and cleaning of internal components (trays and covers, etc.) must be performed frequently, resulting in increased costs. In contrast, if the Al-based nitride layer 2 is deposited by the sputtering method, the surface of the main substrate 1 is covered with the metal layer ML, the Al-based nitride layer 2, and the mask pattern 6 when it is loaded into the MOCVD apparatus to form the semiconductor part 8. Therefore, the possibility of Ga adhering to the surface of the main substrate 1 can be reduced, and the possibility of reduced manufacturing yield due to meltback can be reduced. This offers significant industrial advantages.

[0082] (Semiconductor substrate) Figure 9 is a schematic cross-sectional view showing the configuration of the semiconductor substrate 10 in Example 1. Figure 10 is a cross-sectional view showing an example of lateral growth of the semiconductor portion 8. In Figure 10, the mask portion 5 in the mask pattern 6 shows an example in which a tapered opening K is present. The semiconductor substrate 10 in Example 1 has a first semiconductor portion 8A and a second semiconductor portion 8C formed by the ELO method above the template substrate TS.

[0083] In the example shown in Figure 9, the base B of the semiconductor portion 8 (first semiconductor portion 8A, second semiconductor portion 8C) is in contact with the first surface 2a of the Al-based nitride layer 2 at the openings K (first opening K1, second opening K2). The semiconductor portion 8 may have an initial growth portion SL in the portion in contact with the first surface 2a. The initial growth portion SL may be an initial growth layer SL.

[0084] The semiconductor portion 8 formed by the ELO method can be grown laterally as follows. As shown in Figure 10, an initial growth portion SL may be formed on the seed region S exposed from the opening K, and then the semiconductor portion 8 may be grown laterally from the initial growth portion SL. The initial growth portion SL serves as the starting point for the lateral growth of the semiconductor portion 8. By appropriately controlling the ELO deposition conditions, it is possible to control the growth of the semiconductor portion 8 in the c-axis direction of the nitride semiconductor or in the a-axis direction (first direction X1).

[0085] For example, the deposition of the initial growth portion SL may be stopped just before the edge of the initial growth portion SL rides up onto the upper surface of the mask portion 5 (when it is in contact with the upper side of the mask portion 5), or immediately after it rides up onto the upper surface of the mask portion 5 (i.e., at this timing, the ELO deposition conditions may be switched from c-axis deposition conditions to a-axis deposition conditions). By growing the initial growth portion SL laterally from a state where it slightly protrudes from the mask portion 5, the growth of the semiconductor portion 8 in the c-axis direction (thickness direction) is suppressed, allowing the semiconductor portion 8 to be grown laterally at high speed and with high crystallinity, while also reducing the consumption of raw materials. This makes it possible to form a thin, wide, low-defect semiconductor portion 8 (crystalline nitride semiconductor such as GaN) at low cost. The initial growth portion SL can be formed to a thickness of, for example, 30 nm to 1000 nm, 50 nm to 400 nm, or 70 nm to 350 nm.

[0086] The semiconductor portions 8, which grow laterally in opposite directions from the two adjacent first openings K1 and second opening K2, do not come into contact (meet) on the mask portion 5, and have a gap GP, thereby reducing the internal stress of the semiconductor portions 8. This reduces the occurrence of cracks and defects (dislocations) in the semiconductor portions 8. The width of the gap GP (size in the first direction X1) can be 5 μm or less, 3 μm or less, or 2 μm or less.

[0087] Of the semiconductor portion 8, the base portion B, located on the initial growth portion SL, becomes a dislocation inheritance portion with many through dislocations, while the wing portion F, located on the mask portion 5, becomes a low-defect portion with a through dislocation density of 1 / 5 or less compared to the dislocation inheritance portion. A through dislocation is a dislocation that travels through the semiconductor portion 8 in its c-axis direction ( <0001> These are dislocations (defects) that extend in the direction of (X). The threading dislocation density can be determined, for example, by measuring the surface of the semiconductor part 8 using CL (Cathode Luminescence) and counting the number of black spots in the CL measurement image. The threading dislocation density of the wing part F is, for example, 5 × 10⁻¹⁰. 6 [pcs / cm 2The following is possible. As described later, if an active part (active layer) including a light-emitting part is formed above the semiconductor part 8, the light-emitting part can be positioned above the wing part F (overlapping with the wing part F in a plan view).

[0088] For the wing portion F, the ratio of the width WF (size in the first direction X1) to the thickness d1 (WF / d1) can be, for example, 2.0 or more. WF / d1 can be 2.0 or more, 4.0 or more, 5.0 or more, 7.0 or more, or 10.0 or more. By setting WF / d1 to 2.0 or more, the semiconductor substrate 10 can easily reduce internal stress in the semiconductor portion 8. As a result, the warping of the semiconductor substrate 10 can be reduced. The width WF of the wing portion F may be, for example, 7.0 μm or more, 10.0 μm or more, 20.0 μm or more, or 40.0 μm or more. The thickness d1 may be 10.0 μm or less, 5.0 μm or less, or 2.0 μm or less.

[0089] The density of basal dislocations in base B is 5 × 10 8 / cm 2 The following is also possible: The basal plane dislocations may be dislocations extending in the in-plane direction of the c-plane of the semiconductor portion 8. The basal plane dislocation density here can be determined, for example, by dividing the semiconductor portion 8 to expose the side surface of the base B and measuring the dislocation density of this side surface using CL measurement.

[0090] The semiconductor portion 8 does not need to contain argon. The absence of argon in the semiconductor portion 8 means that the argon content in the semiconductor portion 8 is less than 0.01 atm%. Here, the base B or initial growth portion SL of the semiconductor portion 8 is connected to the Al-based nitride layer 2 and may contain trace amounts of argon diffused from the Al-based nitride layer 2. The wing portion F does not need to contain argon diffused from the Al-based nitride layer 2. If the wing portion F also contains argon, the argon concentration in the wing portion F may decrease as it moves further away from the base B. For example, even if the semiconductor portion 8 contains trace amounts of argon diffused from the Al-based nitride layer 2, the argon content of the semiconductor portion 8 is less than 0.01 atm% (the semiconductor portion 8 does not contain argon).

[0091] In Example 1, the semiconductor portion 8 was made of a GaN layer, and gallium nitride (GaN) ELO film deposition was performed on the aforementioned template substrate 7 using an MOCVD apparatus. As an example of ELO film deposition conditions, the following can be used: substrate temperature: 1120°C, growth pressure: 50kPa, TMG (trimethylgallium): 22sccm, NH3: 15slm, V / III = 6000 (ratio of the amount of Group V raw material supplied to the amount of Group III raw material supplied). To make the semiconductor portion 8 n-type, SiH4 may be flowed to dope it. Alternatively, by using a silicon-containing material (e.g., SiO2 or SiN) for the mask portion 5, Si doping can be performed using Si evaporated from the mask portion 5. The width Wm of the mask portion 5 was 50μm, the width WK of the opening K was 5μm, the width of the semiconductor portion 8 was 53μm, the width WF of the wing portion F was 24μm, and the layer thickness of the semiconductor portion 8 was 5μm. The aspect ratio of the semiconductor section 8 is 53 μm / 5 μm = 10.6, achieving a very high aspect ratio.

[0092] Regarding the film deposition temperature for the semiconductor portion 8 by the ELO method, a temperature of 1150°C or lower is preferable to a high temperature exceeding 1200°C. Formation of the semiconductor portion 8 is possible even at low temperatures below 1000°C, which is even more preferable from the viewpoint of reducing mutual reactions. In Example 1, mutual diffusion may occur between the Al film as the metal layer ML and the main substrate 1 or the Al-based nitride layer 2. In the semiconductor substrate 10, the main substrate 1 may have an alloy layer (not shown) formed by mutual reaction with the metal layer ML under ELO deposition conditions. Alternatively, the Al concentration on the main surface 1a of the main substrate 1 may be higher than the Al concentration on the back surface 1b located on the opposite side of the main surface 1a. In the semiconductor substrate 10, the Al-based nitride layer 2 may have an Al-rich composition.

[0093] It has been found that when the semiconductor portion 8 contains carbon, the reaction with the mask portion 5 is reduced, and adhesion between the mask portion 5 and the semiconductor portion 8 can be reduced. Therefore, in low-temperature film deposition of the semiconductor portion 8, for example, by reducing the supply of ammonia and depositing the film at a low V / III (<1000) temperature, carbon elements in the raw material or chamber atmosphere can be incorporated into the semiconductor portion 8, thereby reducing the reaction with the mask portion 5. In low-temperature film deposition below 1000°C, it is preferable to use triethylgallium (TEG) as the gallium raw material gas. Compared to trimethylgallium (TMG), TEG allows for more efficient decomposition of organic raw materials at low temperatures, thus increasing the lateral film deposition rate.

[0094] In Example 1, the first surface 2a of the Al nitride layer 2 may be an N polar surface, or a surface in which Al polar surfaces and N polar surfaces are mixed (mixed polarity), and the first surface 2a may also be a seed region S. In such a case, the upper surface 8S, which is the growth surface of the semiconductor portion 8, can be made into a gallium polar surface (Ga polar surface) by polarity reversal due to various factors. Alternatively, the upper surface 8S may be an aluminum polar surface (Al polar surface). The semiconductor portion 8 can be formed by adjusting the polarity of the upper surface 8S to suit the device structure to be manufactured using the semiconductor substrate 10.

[0095] Figure 11 is a plan view showing another configuration example of the semiconductor substrate 10 in Example 1. As shown in Figure 11, the semiconductor portion 8 of the semiconductor substrate 10 may be separated into a plurality of parts PA arranged in a second direction X2 perpendicular to the first direction X1. Trench TR may be formed between adjacent parts PA in the second direction X2. The mask portion 5 and the Al-based nitride layer 2 may be exposed in the trench TR.

[0096] In another example, the semiconductor substrate 10 may have a template substrate TS with periodically divided openings K in a second direction X2, in which case the semiconductor portion 8 may also be divided in the second direction X2.

[0097] Figure 12 is a cross-sectional view showing another configuration example of the semiconductor substrate 10 in Example 1. As shown in Figure 12, the template substrate TS in the semiconductor substrate 10 may have a metal nitride layer NL between the metal layer ML and the Al-based nitride layer 2. The metal nitride layer NL contains nitrides of metals other than aluminum. The metal nitride layer NL may contain a material with a crystal structure similar to that of the Al-based nitride layer 2, in which case the Al-based nitride layer 2 can be easily epitaxially grown. The metal nitride layer NL may contain, for example, titanium nitride (TiN), zirconium nitride (ZrN), scandium nitride (ScN), or hafnium nitride (HfN). The metal nitride layer NL may be formed by sputtering, in which case the metal nitride layer NL may contain argon. The argon content of the metal nitride layer NL may be, for example, 0.01 atm% or more and 1.0 atm% or less.

[0098] Figure 13 is a cross-sectional view showing another configuration example of the semiconductor substrate 10 in Example 1. As shown in Figure 13, the template substrate TS in the semiconductor substrate 10 may include a plurality of different metal layers as the metal layer ML, and the metal layer ML may be a multilayer film. The template substrate TS may include, for example, a first metal layer ML1 located on the main substrate 1 and a second metal layer ML2 located on the first metal layer ML1. For example, the first metal layer ML1 may be formed from a material with high affinity to the main substrate 1, and the second metal layer ML2 may be formed from a material with high affinity to the Al-based nitride layer 2. This makes it easier to improve the quality of the Al-based nitride layer 2.

[0099] The metal layer ML may contain three or more metal layers. Multiple metal layers can be formed continuously by appropriately switching targets within the sputtering apparatus.

[0100] Figure 14 is a cross-sectional view showing another configuration example of the semiconductor substrate 10 in Example 1. As shown in Figure 14, the template substrate TS in the semiconductor substrate 10 may have a seed portion 3 between the Al-based nitride layer 2 and the mask pattern 6, in which case the surface of the seed portion 3 exposed at the opening K may be a seed region S. The seed portion 3 may be a seed layer.

[0101] The seed portion 3 only needs to be formed in a part of the opening K (of the mask pattern 6), and may be planar or patterned (e.g., stripe-shaped). The seed portion 3 may be a GaN layer, AlN layer, AlGaN layer, AlInN layer, AlGaInN, Al, etc., formed at a low temperature (500°C or below). The seed portion 3 may be formed from a different material than the Al-based nitride layer 2. The seed portion 3 may be formed by sputtering, in which case the seed portion 3 may contain argon. The argon content of the seed portion 3 may be, for example, 0.01 atm% to 1.0 atm%. The thickness of the seed portion 3 may be about 10 nm to 500 nm.

[0102] For example, when forming the seed portion 3, which is a GaN layer, using the RF sputtering method, a gallium nitride target (oxygen content: 0.4 atom%) is used, the deposition pressure is set to 0.1 Pa, nitrogen gas is introduced at 20-40 sccm, and the discharge density is 5 W / cm². 2 The film deposition temperature can be set to room temperature. The introduced gas may also contain argon gas.

[0103] Figure 15 is a cross-sectional view showing an alternative configuration of the semiconductor substrate in Example 1. Figure 16 is a plan view showing an alternative configuration of the semiconductor substrate in Example 1. As shown in Figures 15 and 16, the semiconductor substrate 10 may be located above the semiconductor portion 8 and include an upper layer 9 containing an active layer and a p-type layer.

[0104] The semiconductor substrate 10 may be removed from the MOCVD apparatus and stored with the semiconductor portion 8 exposed after the semiconductor portion 8 has been formed in the MOCVD apparatus. In this case, the stored semiconductor substrate 10 can be loaded into the MOCVD apparatus to form the upper layer 9. Alternatively, the upper layer 9 may be formed in the MOCVD apparatus immediately after the semiconductor portion 8 has been formed. For example, the upper layer 9 may be formed on the semiconductor portion 8 after the growth of the semiconductor portion 8 has been stopped by changing the film deposition conditions (for example, by lowering the film deposition temperature by about 100°C). In addition to the active layer, the upper layer 9 may include at least one of a p-type layer, an n-type layer, and an electron blocking layer.

[0105] The semiconductor substrate 10 may have an anode EA and a cathode EC located on the upper layer 9. The anode EA may be in contact with a p-type layer in the upper layer 9, and the cathode EC may be in contact with an n-type layer in the upper layer 9. However, it is not limited to this, and the cathode EC may be in contact with the upper surface 8S of the semiconductor portion 8. In a plan view, at least a part of the anode EA may be positioned to overlap with the wing portion F, and all of the anode EA may be positioned to overlap with the wing portion F.

[0106] The device structure including the semiconductor portion 8 and the upper layer portion 9 is referred to as the laminated body LB. The semiconductor substrate 10 has a plurality of bar-shaped laminated bodies LB. By forming at least an active region (e.g., a light-emitting region) above the wing portion F in the upper layer portion 9 (device layer) formed on the semiconductor portion 8, a very high-quality device can be manufactured. In Example 1, the template substrate TS is formed without using an MOCVD apparatus, and the semiconductor portion 8 and the upper layer portion 9 can be formed continuously within the MOCVD apparatus.

[0107] Figure 17 is a plan view showing the method of element isolation in Example 1. Figure 18 is a cross-sectional view showing the method of element isolation in Example 1. As shown in Figures 17 and 18, the semiconductor substrate 10 may have a plurality of element bodies 20 separated by a plurality of trenches TR on a base substrate BS. The element body 20 may include a wing portion F, an upper layer portion 9, an anode EA, and a cathode EC.

[0108] Multiple device bodies 20 may be formed on the semiconductor substrate 10 by etching multiple trenches TR in the laminate LB. Alternatively, the semiconductor substrate 10 may be divided into multiple parts PA (see Figure 11) by forming multiple trenches TR in the semiconductor portion 8, and then an upper layer 9, anode EA, and cathode EC may be formed on the parts PA. Or, multiple device bodies 20 may be formed on the semiconductor substrate 10 by cleaving the laminate LB.

[0109] In the examples shown in Figures 17 and 18, the mask portion 5 is removed by etching using hydrofluoric acid, buffered hydrofluoric acid (BHF), etc. This makes it easier to separate the element body 20 from the base substrate BS. For example, the element body 20 may be bonded to the support substrate SK via bonding layers H1 and H2. Then, by breaking the bond between the seed region S and the semiconductor portion 8, the element body 20 can be peeled off from the base substrate BS. The support substrate SK may have conductive pads in contact with bonding layer H1 and conductive pads in contact with bonding layer H2. Bonding layers H1 and H2 may be formed of solder material.

[0110] Specific examples of the element 20 include light-emitting diodes (LEDs), semiconductor lasers, Schottky diodes, photodiodes, and transistors (including power transistors and high electron mobility transistors).

[0111] Figure 19 is a plan view showing another configuration example of the semiconductor substrate 10 in Example 1. As shown in Figure 19, the semiconductor substrate 10 may have the anode EA and cathode EC formed above the same wing portion F (for example, the first wing portion F1). A trench TR may be formed in the portion of the laminate LB located above the seed region S.

[0112] [Example 2] Figure 20 is a schematic plan view showing the configuration of the semiconductor substrate 10 in Example 2. Figure 21 is a schematic cross-sectional view showing the configuration of the semiconductor substrate 10 in Example 2. In Figure 21, the black dots indicated by the leader lines labeled J1 and J2 represent the space (gap) between the wing portion F and the template substrate TS.

[0113] As shown in Figures 20 and 21, in the semiconductor substrate 10 of Embodiment 2, the template substrate TS has a ridge portion R on its upper surface, and the first seed region S1 may be located on the upper surface of the ridge portion R. A first void J1 may exist between the first semiconductor portion 8A and the mask portion 5. The first void J1 can also be described as the space sandwiched between the growth suppression region DA and the first wing portion F1. The first wing portion F1 is spaced apart from the mask portion 5, which functions as the growth suppression region DA. The surface of the first seed region S1 is located above the growth suppression region DA, and the first semiconductor portion 8A has a first base portion B1 located on the first seed region S1 and a first wing portion F1 connected to the first base portion B1 and facing the growth suppression region DA via the first void J1.

[0114] In a plan view, the Al-based nitride layer 2 of the template substrate TS does not need to overlap with the mask portion 5. At least a portion of the metal layer ML of the template substrate TS may be included in the ridge portion R. In the template substrate TS of Example 2, the metal layer ML and the Al-based nitride layer 2 may be included in the ridge portion R.

[0115] The upper surface of the ridge portion R (first seed region S1) may be composed of an Al-based nitride layer 2, and the side surface of the ridge portion R may be covered by a mask portion 5. The template substrate TS may include a portion of the mask portion 5 on the side surface of the ridge portion R. The metal layer ML and the Al-based nitride layer 2 do not need to be exposed on the side surface of the ridge portion R. The side surface of the ridge portion R does not need to be in contact with the first wing portion F1. The entire side surface of the ridge portion R may face the first void J1. This reduces the contact area between the ridge portion R and the first wing portion F1, and as a result, the defect density of the first wing portion F1 can be reduced.

[0116] The first semiconductor portion 8A can be formed by the ELO (Epitaxial Lateral Overgrowth) method, starting from the Al-based nitride layer 2 exposed below the first opening K1. The Al-based nitride layer 2 may be a seed layer including the first seed region S1. The second semiconductor portion 8C grows laterally on the mask portion 5, starting from the Al-based nitride layer 2 exposed below the second opening K2. Growth may be stopped before the first semiconductor portion 8A and the second semiconductor portion 8C meet, in which case the edge E1 of the first wing portion F1 can be formed above the growth suppression region DA.

[0117] The aspect ratio of the first void J1 (the ratio of the width WJ in the first direction X1 to the thickness TJ) can be set to 5.0 or higher. In this case, the crystallinity is high (defect density is low), and a wide first wing portion F1 can be formed quickly. In addition, the flatness of the first wing portion F1 is improved. The width WJ of the first void J1 is the distance in the first direction X1 from the side surface of the ridge R to the edge E of the first semiconductor portion 8A. The thickness (height) TJ of the first void is the distance from the upper surface of the mask portion 5 that forms the growth suppression region DA to the lower surface (back surface) of the first semiconductor portion 8A.

[0118] The first wing portion F1 may have a width in the first direction X1 as the ratio of its thickness to its width of 2.0 or more. The first wing portion F1 may have a width in the first direction X1 of 7.0 μm or more, for example, 10.0 μm or more, 20.0 μm or more, or 40.0 μm or more. The first wing portion F1 may have a width in the first direction X1 of 80.0 μm or less. This reduces the possibility of the semiconductor portion 8 warping in the substrate direction due to gravity. The first wing portion F1 may have a thickness in the first direction X1 of 10.0 μm or less, 5.0 μm or less, or 2.0 μm or less. As shown in Figure 21, the width of the gap GP may be greater than the thickness TJ of the first void J1.

[0119] The semiconductor substrate 10 may have a second void J2 between the second semiconductor portion 8C and the mask portion 5, and the second void J2 may have the same configuration as the first void J1. Therefore, a repeated explanation of the second void J2 will be omitted.

[0120] Figure 22 is a cross-sectional view showing an example of a method for manufacturing the semiconductor substrate 10 in Example 2. The semiconductor substrate 10 of Example 2 can be manufactured, for example, as follows: A silicon substrate (Si(111) plane) is used as the main substrate 1, an Al film is formed on the silicon substrate as a metal layer ML, and then an AlN film is deposited on the Al film as an Al-based nitride layer 2. Sputtering is used to deposit the metal layer ML and the Al-based nitride layer 2.

[0121] Next, using photolithography, stripe-shaped resist Z with a width of approximately 3 μm is formed on top of the Al-based nitride layer 2, and ridges R are formed by a dry etching process. During this process, a portion of the Al-based nitride layer 2 and the metal layer ML are etched. Here, the resist Z is not removed, and a mask layer MF (for example, a SiN film with a thickness of 10 nm) which will become the mask portion 5 is formed on the main substrate 1 and on the resist Z.

[0122] As in the aforementioned Example 1, when the semiconductor portion 8 is in contact with the mask portion 5 on the growth suppression region DA, the mask portion 5 requires a thickness of at least 100 nm. When the semiconductor portion 8 is in contact with the mask portion 5, it interferes with ELO growth, which can affect the surface flatness of the semiconductor portion 8. In contrast, in Example 2, because the wing portion F is floating in the hollow, the wing portion F and the mask portion 5 do not come into contact with each other above the growth suppression region DA. Therefore, even if the mask portion 5 is made very thin, it does not hinder the growth of the wing portion F, and the internal stress of the semiconductor portion 8 can be reduced. As a result, it is easier to reduce the warping of the semiconductor substrate 10.

[0123] Furthermore, thinning the mask portion 5 improves the flatness of the back surface of the wing portion F. The thickness of the mask portion 5 may be, for example, 1 μm or less, or 50 nm or less. Setting the thickness of the mask portion 5 to 50 nm or less improves flatness, and it can also be set to 30 nm or less.

[0124] Next, the resist Z is removed to lift off the mask layer MF on the ridge portion R, forming the first opening K1 and creating the template substrate TS (selective growth substrate). By fabricating the template substrate TS without using the MOCVD method, significant cost reductions can be achieved, resulting in substantial industrial benefits.

[0125] Next, the template substrate TS is transported into the MOCVD apparatus, and the semiconductor portion 8 is formed on the template substrate TS by the ELO method. In Example 2, the semiconductor portion 8 is a GaN layer, with a growth temperature of 1000 to 1200 degrees Celsius, a V / III ratio of 500 to 20000, and a growth pressure of 50 kPa. In order to make the semiconductor portion 8 n-type, Si doping may be performed as in Example 1 described above. It is preferable to set the film deposition conditions in at least two stages. In the first stage, the film deposition temperature is set to about 1030 degrees Celsius, and the V / III ratio is set to about 2000 to form growth nuclei (vertical growth portions) of the ELO layer (semiconductor portion 8) on the opening K. The thickness (height) of the growth nuclei is about 0.2 μm to 3 μm, and its width may be about the same as the width of the ridge R or slightly exceeding the a-axis direction (<11-20> direction). In the second stage, the film deposition temperature was raised to about 100°C to grow the GaN layer laterally (in the a-axis direction) from the growth nucleus, and growth was stopped when the width of the gap GP between the semiconductor parts 8 (GaN layers) growing in the opposite direction on the void reached a specified value (10 μm or less). The semiconductor substrate 10 obtained in this way (with the semiconductor parts 8 exposed) may be removed from the MOCVD apparatus and stored, or an upper layer including an active layer may be formed in the MOCVD apparatus thereafter.

[0126] Figure 23 is a cross-sectional view showing another configuration example of the semiconductor substrate 10 in Example 2. As shown in Figure 23, in the semiconductor substrate 10, the main substrate 1 may include a convex portion Q on the main surface 1a, and at least a part of the convex portion Q may be included in the ridge portion R. The metal layer ML and the Al-based nitride layer 2 may be located on the convex portion Q. The convex portion Q can be formed by removing a part of the main substrate 1 when forming the ridge portion R by a dry etching process. In the example shown in Figure 23, the first void J1 can be formed more reliably, making it easier to reduce the warping of the semiconductor substrate 10.

[0127] Figure 24 is a cross-sectional view showing another configuration example of the semiconductor substrate 10 in Example 2. As shown in Figure 24, in the semiconductor substrate 10, the metal layer ML may include a protrusion MQ on the side facing the Al-based nitride layer 2, and the Al-based nitride layer 2 may be located on the protrusion MQ. At least a portion of the metal layer ML may be located between the main substrate 1 and the mask portion 5. When forming the ridge portion R by the dry etching process, the protrusion MQ can be formed by leaving a portion of the metal layer ML on the main substrate 1 without being removed.

[0128] Figure 25 is a cross-sectional view showing another configuration example of the semiconductor substrate 10 in Example 2. As shown in Figure 25, in the semiconductor substrate 10, the metal layer ML is located over the entire surface of the main substrate 1, and the Al-based nitride layer 2 may be located locally on the metal layer ML. In the example shown in Figure 25, the metal layer ML does not need to be included in the ridge portion R.

[0129] Figure 26 is a cross-sectional view showing another configuration example of the semiconductor substrate 10 in Example 2. As shown in Figure 26, the semiconductor substrate 10 may have the side surface of the ridge portion R (mask portion 5) in contact with the first wing portion F1. As long as the first wing portion F1 does not come into contact with the mask portion 5 of the growth suppression region DA, the first void J1 can be formed, so there is no problem.

[0130] [Example 3] In Examples 1 and 2 described above, the Al-based nitride layer 2 was formed on the main substrate 1. However, the invention is not limited to this, and the Al-based nitride layer 2 can be formed on a substrate other than the main substrate 1 (hereinafter referred to as temporary substrate 1T), and then the Al-based nitride layer 2 can be transferred to the main substrate 1.

[0131] Figure 27 is a cross-sectional view showing an example of a method for manufacturing the semiconductor substrate 10 in Example 3. As shown in Figure 27, first, a metal layer ML and an Al-based nitride layer 2 are formed on top of a temporary substrate 1T using a sputtering method. The temporary substrate 1T is not particularly limited and can be made of any material on which the metal layer ML and the Al-based nitride layer 2 can be formed. As the temporary substrate 1T can be reused as described later, the impact on manufacturing costs is small even if a relatively expensive substrate is used. For example, a 4H-SiC substrate can be used as the temporary substrate 1T. Also, a silicon substrate can be used as the main substrate 1.

[0132] A metal layer ML can be formed over the entire surface of a temporary substrate 1T, and an Al-based nitride layer 2 can be formed on the metal layer ML. Generally, an AlN film is formed on a 4H-SiC substrate by sputtering. As shown in the example in Figure 27, by forming the Al-based nitride layer 2 on the temporary substrate 1T via the metal layer ML, an Al-based nitride layer 2 of higher quality than conventional methods can be formed.

[0133] Next, for example, the first surface 2a of the Al-based nitride layer 2 and the main surface 1a of the main substrate 1 are purified by plasma treatment in a vacuum. This activates the surface (resulting in the presence of dangling bonds on the surface). Subsequently, the first surface 2a of the Al-based nitride layer 2 and the main surface 1a of the main substrate 1 are brought into contact, thereby enabling surface activation bonding between the Al-based nitride layer 2 and the main substrate 1.

[0134] Subsequently, by removing the metal layer ML and separating the temporary substrate 1T, the Al-based nitride layer 2 can be transferred to the main substrate 1. The subsequent processing may be the same as in Example 1 described above, and a mask pattern 6 can be formed on the Al-based nitride layer 2, and the semiconductor portion 8 can be formed using the ELO method.

[0135] In Example 3, even if the metal layer ML is formed relatively thickly, no problems arise because the metal layer ML is removed during the transfer process. Therefore, it is easy to improve the quality of the Al-based nitride layer 2. In addition, the temporary substrate 1T can be reused by removing the metal layer ML from the surface.

[0136] As described above, in Example 3, for example, a high-quality Al-based nitride layer 2 formed on a 4H-SiC substrate can be transferred onto a silicon substrate, which serves as the main substrate 1. As a result, a template substrate TS having a higher-quality Al-based nitride layer 2 than conventional methods can be created on a silicon substrate. A semiconductor substrate 10 can be manufactured using such a template substrate TS. Therefore, the characteristics of various devices can be improved using the semiconductor substrate 10.

[0137] Furthermore, in Example 3, since the Al-based nitride layer 2 does not necessarily have to be epitaxially growable on the main surface 1a, the main substrate 1 may be, for example, a silicon substrate, and the plane orientation of the main surface 1a may be the (100) plane. Generally, since electronic circuits and the like can be formed on the Si(100) plane, by using, for example, a silicon substrate (Si(100) plane) as the main substrate 1, it becomes possible to integrate light-emitting elements and electronic circuits in a semiconductor device formed using the semiconductor substrate 10.

[0138] The first surface 2a of the Al-based nitride layer 2 facing the main surface 1a of the main substrate 1 may be, for example, an N-polar surface, and in this case, the second surface 2b of the Al-based nitride layer 2 may be an Al-polar surface. When the plane orientation of the main surface 1a of the main substrate 1 is the (100) plane, the first surface 2a of the Al-based nitride layer 2 has a hexagonal structure, so the atomic arrangement patterns of the crystals of the main surface 1a and the first surface 2a are different in the in-plane direction.

[0139] Furthermore, if the surface orientation of the main surface 1a of the main substrate 1 is (111) plane, the x and y axis directions of the unit cell in the atomic arrangement of the main surface 1a may be different from those of the unit cell in the atomic arrangement of the first surface 2a of the Al-based nitride layer 2. The presence of a bonding mark, which is the difference between the main surface 1a and the first surface 2a, makes it possible to distinguish between the AlN film epitaxially grown on the main substrate 1 and the Al-based nitride layer 2 transferred onto the main substrate 1. The above bonding mark can be confirmed, for example, based on the results of X-ray measurement.

[0140] Figure 28 is a cross-sectional view showing an example of a method for manufacturing a template substrate TS with an alternative configuration in Example 3. As shown in Figure 28, a 4H-SiC substrate is used as a temporary substrate 1T, and an Al film (thickness: 100 nm) is formed as the metal layer ML. Then, an Al-based nitride layer 2 is formed on the Al film. The Al-based nitride layer 2 may be a ScAlN film (thickness: 1000 nm).

[0141] A silicon substrate is used as the main substrate 1, and an intermediate layer IL is formed on the main substrate 1. The intermediate layer IL may be, for example, a molybdenum film (thickness: 1000 nm) and can be formed using a sputtering method. The surface of the intermediate layer IL is cleaned to activate bonding the intermediate layer IL and the Al-based nitride layer 2. By removing the metal layer ML, the Al-based nitride layer 2 is transferred onto the intermediate layer IL of the main substrate 1.

[0142] This makes it possible to manufacture a template substrate TS comprising a main substrate 1, an intermediate layer IL on the main substrate 1, and an Al-based nitride layer 2 on the intermediate layer IL. Such a template substrate TS can be used to manufacture, for example, a BAW filter, in which the Al-based nitride layer 2 is a piezoelectric layer and the intermediate layer IL is an elastic wave reflector.

[0143] Figure 29 is a cross-sectional view showing an example of a method for manufacturing a template substrate TS with an alternative configuration in Example 3. As shown in Figure 29, a 4H-SiC substrate is used as a temporary substrate 1T, and an Al film (thickness: 100 nm) is formed as a metal layer ML. Then, an AlN film (thickness: 200 nm) is formed on the Al film as an Al-based nitride layer 2. Furthermore, a GaN film (thickness: 1000 nm) is formed as a first layer L1 on the Al-based nitride layer 2, and an AlGaN film (thickness: 10 nm) is formed as a second layer L2 on the first layer L1. The metal layer ML, Al-based nitride layer 2, first layer L1, and second layer L2 are each formed using the sputtering method.

[0144] Next, the second layer L2 is temporarily bonded to the support substrate 1S. The material of the support substrate 1S is not particularly limited, and any known method can be used for temporary bonding as appropriate. By removing the metal layer ML, the Al-based nitride layer 2, the first layer L1, and the second layer L2 are transferred onto the support substrate 1S.

[0145] Subsequently, for example, the second surface 2b of the Al-based nitride layer 2 and the main surface 1a of the main substrate 1 are plasma-treated in a vacuum, and the Al-based nitride layer 2 and the main surface 1a are brought into contact to perform surface activation bonding. Then, by removing the temporary bonding between the second layer L2 and the support substrate 1S, the Al-based nitride layer 2, the first layer L1, and the second layer L2 can be transferred to the main substrate 1.

[0146] This makes it possible to manufacture a template substrate TS comprising a main substrate 1, an Al-based nitride layer 2 on the main substrate 1, a first layer L1 on the Al-based nitride layer 2, and a second layer L2 on the first layer L1. Such a template substrate TS can be used, for example, in the manufacture of a HEMT, in which the first layer L1 is an electron-passing layer and the second layer L2 is an electron-generating layer.

[0147] [Example 4] Figure 30 is a cross-sectional view showing an example of a method for manufacturing the semiconductor substrate 10 in Example 4. As shown in Figure 30, the semiconductor substrate 10 can be made into a structure having a ridge portion R as in Example 2 (ridge structure) using the template substrate TS of Example 3 described above.

[0148] First, a striped resist Z is formed on the Al nitride layer 2 using a template substrate TS having a main substrate 1 and an Al nitride layer 2 located on the main substrate 1. A portion of the Al nitride layer 2 is etched by a dry etching process. A mask layer MF (for example, a SiN film with a thickness of 10 nm) which will become the mask portion 5 is formed on the main substrate 1 and the resist Z.

[0149] Subsequently, the template substrate TS and semiconductor substrate 10 can be manufactured by performing the same process as described above in Example 2. The template substrate TS has a ridge portion R on its upper surface where the first seed region S1 is located. In the semiconductor substrate 10, a first void J1 exists between the first semiconductor portion 8A and the growth suppression region DA.

[0150] In the template substrate TS, the growth suppression region DA is a modified region of the Al-based nitride layer 2, and the first seed region S1 may be an unmodified region of the Al-based nitride layer 2. The Al-based nitride layer 2 can be modified, for example, by applying plasma treatment to it.

[0151] In plasma treatment, for example, an argon plasma is irradiated onto a predetermined area of ​​the Al-based nitride layer 2 to modify the surface of the irradiated area and form a growth-inhibiting region DA. By introducing oxygen gas, nitrogen gas, hydrogen gas, etc., in addition to argon gas, the plasma treatment can also use oxygen plasma, nitrogen plasma, hydrogen plasma, or a mixture thereof. As a result, the growth-inhibiting region DA may contain argon, oxygen, or nitrogen as impurities. In such cases, the Al-based nitride layer 2 may be aluminum nitride, and the growth-inhibiting region DA may be aluminum oxynitride. Alternatively, the Al-based nitride layer 2 may be AlScN (aluminum scandium nitride), and the growth-inhibiting region DA may be AlScON (aluminum scandium oxynitride).

[0152] [Additional notes] The inventions described herein have been explained above based on the drawings and examples. However, the inventions described herein are not limited to the embodiments and examples described above. That is, the inventions described herein can be modified in various ways within the scope shown in this disclosure, and embodiments obtained by appropriately combining the technical means disclosed in different embodiments and examples are also included in the technical scope of the inventions described herein. In other words, it should be noted that it is easy for those skilled in the art to make various modifications or alterations based on this disclosure. Furthermore, it should be noted that these modifications or alterations are included in the scope of this disclosure. [Explanation of Symbols]

[0153] 1 Main board 2 Al-based nitride layer 5 Mask section 6 Mask Patterns 8 Semiconductor Division 8A First Semiconductor Section 8C Semiconductor Section 2 10 Semiconductor substrates B base DA growth suppression area F Wing Section GP Gap K opening ML metal layer S Seed Region TS template substrate

Claims

1. The invention comprises a template substrate including a first seed region and a growth inhibition region, and a first semiconductor portion having a first base portion located above the first seed region and a first wing portion connected to the first base portion and located above the growth inhibition region. The template substrate comprises a main substrate, a metal layer located above the main substrate, and an aluminum nitride layer containing argon located above the metal layer. The first semiconductor portion includes a nitride semiconductor, A semiconductor substrate in which, at room temperature, the aluminum nitride layer is under compressive stress and the first semiconductor portion is under tensile stress.

2. The aforementioned aluminum nitride layer is an aluminum nitride layer. The main substrate is a different type of substrate with a different lattice constant from the first semiconductor portion. The aluminum nitride layer is a seed layer including the first seed region and is in contact with the first base. The semiconductor substrate according to claim 1, wherein the first semiconductor portion does not contain argon.

3. The semiconductor substrate according to claim 1, wherein the metal layer contains at least one of argon and hydrogen.

4. The semiconductor substrate according to claim 1, wherein the metal layer comprises one or more metals selected from the group consisting of aluminum, platinum, palladium, silver, gold, hafnium, scandium, yttrium, titanium, and zirconium.

5. The semiconductor substrate according to claim 1, wherein the metal layer comprises at least one metal whose (111) plane of a face-centered cubic lattice or body-centered cubic lattice or its (0001) plane of a hexagonal close-packed lattice is oriented toward the main surface of the main substrate.

6. The semiconductor substrate according to claim 1, wherein the metal layer includes a first layer made of a metal material and a second layer made of a metal material different from the first layer.

7. The semiconductor substrate according to claim 1, wherein the metal layer overlaps the entire upper surface of the main substrate in a plan view taken in the direction normal to the main substrate.

8. The semiconductor substrate according to claim 1, comprising a metal nitride layer located between the metal layer and the aluminum nitride layer.

9. The semiconductor substrate according to claim 1, wherein the thickness of the metal layer is 20 nm or more.

10. The semiconductor substrate according to claim 1, wherein the aluminum nitride layer has a coefficient of thermal expansion at 1000°C that is greater than that of the main substrate and smaller than that of the first semiconductor portion.

11. The growth suppression region is a modified region of the aluminum nitride layer, The semiconductor substrate according to any one of claims 1 to 10, wherein the first seed region is an unmodified region of the aluminum nitride layer.

12. The semiconductor substrate according to any one of claims 1 to 10, wherein the template substrate has a mask pattern including a mask portion that functions as a growth suppression region and an opening corresponding to the first seed region.

13. The semiconductor substrate according to claim 12, wherein the aluminum nitride layer overlaps the mask portion.

14. The semiconductor substrate according to claim 12, wherein the aluminum nitride layer does not overlap with the mask portion.

15. The template substrate has a ridge portion on its upper side where the first seed region is located. The semiconductor substrate according to claim 12, wherein a gap exists between the first semiconductor portion and the mask portion.

16. The semiconductor substrate according to claim 15, wherein at least a portion of the metal layer is included in the ridge portion.

17. The main substrate has a protrusion on its upper side, The semiconductor substrate according to claim 15, wherein at least a portion of the convex portion is included in the ridge portion.

18. The semiconductor substrate according to claim 15, wherein a part of the mask portion is included on the side surface of the ridge portion.

19. The semiconductor substrate according to claim 2, wherein the aluminum nitride layer has a ratio of impurity metal elements other than aluminum to the total metal elements of less than 0.5 atm%.

20. A template substrate including a first seed region and a growth inhibition region, and a first semiconductor portion having a first base portion located above the first seed region and a first wing portion connected to the first base portion and located above the growth inhibition region, The template substrate comprises a main substrate and an aluminum nitride layer containing argon, the nitrogen polarity surface of which is bonded to the main substrate. The first semiconductor portion includes a nitride semiconductor, A semiconductor substrate in which the aluminum nitride layer does not inherit the crystal structure of the main substrate at the interface with the main substrate.

21. A template substrate including a first seed region and a growth inhibition region, and a first semiconductor portion having a first base portion located above the first seed region and a first wing portion connected to the first base portion and located above the growth inhibition region, The template substrate comprises a main substrate and an aluminum nitride layer containing argon, the nitrogen polarity surface of which is bonded to the main substrate. The first semiconductor portion includes a nitride semiconductor, A semiconductor substrate having a bonding mark at the interface between the aluminum nitride layer and the main substrate.

22. The template substrate has a ridge portion on its upper side where the first seed region is located. The semiconductor substrate according to claim 20 or 21, wherein a void exists between the first semiconductor portion and the growth suppression region.

23. The semiconductor substrate according to any one of claims 1, 20, and 21, wherein each of the first seed region and the growth inhibition region, which are aligned in the first direction, has a shape in which the second direction, which is perpendicular to the first direction, is the longitudinal direction.

24. It comprises a second semiconductor section containing a nitride semiconductor, The template substrate has a second seed region adjacent to the first seed region in the first direction via the growth inhibition region, The second semiconductor portion has a second base portion located above the second seed region and a second wing portion connected to the second base portion and located above the growth suppression region. The semiconductor substrate according to any one of claims 1, 20, and 21, wherein the first wing portion and the second wing portion are aligned in the first direction with a gap between them.

25. The nitride semiconductor is a GaN-based semiconductor, The semiconductor substrate according to any one of claims 1, 20, and 21, wherein the main substrate is a silicon substrate, a silicon carbide substrate, or a glass substrate.

26. A method for manufacturing a template substrate including a main substrate, A process of forming a metal layer on a temporary substrate, The process involves forming an aluminum nitride layer above the aforementioned metal layer using a sputtering method, A method for manufacturing a template substrate, comprising the step of transferring the aluminum nitride layer from the temporary substrate to the main substrate.

27. The method for manufacturing a template substrate according to claim 26, characterized in that the aluminum nitride layer has a nitrogen polar surface when formed by sputtering, and an Al polar surface after transfer.

28. The method for manufacturing a template substrate according to claim 26, wherein the main substrate and the aluminum nitride layer are separated from the temporary substrate by removing the metal layer.

29. A method for manufacturing a template substrate according to any one of claims 26 to 28, wherein the temporary substrate is a silicon carbide substrate and the main substrate is a silicon substrate.

30. A manufacturing apparatus for a template substrate, which performs each of the steps described in claim 26.

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