Template substrate, semiconductor substrate, semiconductor device manufacturing method

Abstract

To provide a template substrate, a semiconductor substrate and a method of manufacturing a semiconductor device.SOLUTION: There is provided a template substrate (7) that comprises a main substrate having an edge (E), a peripheral edge part (1S) including the edge, and a non-peripheral edge part (1P) located inside the peripheral edge part, and a mask pattern located above the main substrate, wherein the mask pattern has a mask part (5), a plurality of first opening parts (KF) which have widths in a first direction and lengths in a second direction, and overlap with the non-peripheral edge part (1P) in plan view, and one or more second opening parts (KB) arranged along the edge in plan view.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a template substrate and the like.

Background Art

[0002] Patent Document 1 discloses a method of forming a plurality of semiconductor portions corresponding to the openings of a plurality of masks using the ELO (Epitaxial Lateral Overgrowth) method.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

[0004] The template substrate according to the present disclosure includes a main substrate having an edge, a peripheral portion including the edge, and a non-peripheral portion located inside the peripheral portion, and a mask pattern located above the main substrate. The mask pattern has a mask portion, a plurality of first openings having a first direction as a width direction and a second direction as a longitudinal direction and overlapping the non-peripheral portion in a plan view, and one or more second openings arranged along the edge in a plan view.

Brief Description of the Drawings

[0005] [Figure 1] It is a plan view showing the configuration of the template substrate according to the present embodiment. [[ID=?]] [[ID=?]] [Figure 2] It is a cross-sectional view taken along the line a-a of FIG. 1 (non-peripheral portion). [Figure 3] It is a cross-sectional view taken along the line b-b of FIG. 1 (peripheral portion). [Figure 4] It is a plan view showing the configuration of the semiconductor substrate according to the present embodiment. [Figure 5A] It is a cross-sectional view taken along the line A-A of FIG. 4. [Figure 5B] This is a cross-sectional view taken along the arrow cc in Figure 4. [Figure 6] This is a cross-sectional view showing another configuration of the semiconductor substrate according to this embodiment. [Figure 7] This is a cross-sectional view showing another configuration of the semiconductor substrate according to this embodiment. [Figure 8] This flowchart shows an example of a method for manufacturing a template substrate according to this embodiment. [Figure 9] This is a block diagram showing an example of a manufacturing apparatus for a template substrate according to this embodiment. [Figure 10] This flowchart shows an example of a method for manufacturing a semiconductor substrate according to this embodiment. [Figure 11] This is a block diagram showing an example of a semiconductor substrate manufacturing apparatus according to this embodiment. [Figure 12] This is a flowchart showing an example of a method for manufacturing a semiconductor device according to this embodiment. [Figure 13] This is a plan view showing an example of the separation of the element section. [Figure 14] This is a cross-sectional view showing an example of the separation and separation of the element section. [Figure 15] This is a schematic diagram showing the configuration of the electronic device according to this embodiment. [Figure 16] This is a schematic diagram showing an alternative configuration of the electronic device according to this embodiment. [Figure 17] This is a plan view showing the configuration of the template substrate according to Example 1. [Figure 18] This is a cross-sectional view taken along the arrow dd in Figure 17. [Figure 19] This is a plan view showing the configuration of a semiconductor substrate according to Example 1. [Figure 20] A cross-sectional view showing an example of lateral growth in the ELO semiconductor region. [Figure 21] This is a plan view showing an alternative configuration of the template substrate according to Example 1. [Figure 22] Figure 21 is a plan view showing the configuration of a semiconductor substrate including the template substrate. [Figure 23]It is a plan view showing another configuration of the template substrate according to Example 1. [Figure 24] It is a plan view showing another configuration of the template substrate according to Example 1. [Figure 25] It is a plan view showing the configuration of the template substrate according to Example 2. [Figure 26] It is a plan view showing the configuration of the semiconductor substrate according to Example 2. [Figure 27] It is a plan view showing another configuration of the template substrate according to Example 2. [Figure 28] It is a plan view showing another configuration of the template substrate according to Example 2. [Figure 29] It is a schematic cross-sectional view showing the configuration of Example 4 [Figure 30] It is a cross-sectional view showing an application example of Example 4 to an electronic device. [Figure 31] It is a schematic cross-sectional view showing the configuration of Example 5. [Figure 32] It is a cross-sectional view showing the configuration of Example 6.

Modes for Carrying Out the Invention

[0006] 〔Template Substrate〕 FIG. 1 is a plan view showing the configuration of the template substrate according to the present embodiment. FIG. 2 is a cross-sectional view taken along the line a-a (non-peripheral portion) of FIG. 1. FIG. 3 is a cross-sectional view taken along the line b-b (peripheral portion) of FIG. 1.

[0007] As shown in Figure 1, the template substrate 7 according to this embodiment comprises a main substrate 1 having an edge E (end face, side surface), a peripheral portion 1S including the edge E, and a non-peripheral portion 1P located inside the peripheral portion 1S, and a mask pattern 6 (mask layer) located above the main substrate 1. The mask pattern 6 has a mask portion 5, a plurality of first openings KF whose first direction (X direction) is the width direction and second direction (Y direction) is the longitudinal direction, overlapping with the non-peripheral portion 1P in a plan view, and a plurality of second openings KB arranged along the edge E in a plan view. The template substrate 7 can be used for forming semiconductor parts (semiconductor layers), for example, for forming GaN-based semiconductor parts (GaN-based semiconductor crystals) by the ELO method (Epitaxial Lateral Overgrowth).

[0008] In Figure 1, the edge E (side surface, end face) of the main substrate 1 includes a curved surface Er and a flat surface Ef, but it is not limited to this, and the edge E may consist only of a curved surface or a flat surface.

[0009] Each first opening KF should overlap with the non-peripheral portion 1P in a plan view. The entire opening may be located in the non-peripheral portion 1P, or a part of it may be located in the peripheral portion 1S and the remaining part may be located in the non-peripheral portion 1P.

[0010] The multiple second openings KB only need to be aligned with edge E in a plan view. Each second opening KB may be entirely located in the non-peripheral portion 1P, entirely located in the peripheral portion 1S, or a portion of it may be located in the non-peripheral portion 1P and the remaining portion in the peripheral portion 1S.

[0011] In Figure 1, the mask pattern 6 includes multiple second openings KB, but is not limited to this; it may include only one. The shape of the second openings KB may also be rectangular with the Y or X direction as its longitudinal direction, or it may be a square or a circle, or it may be an annular or curved longitudinal shape. One of the multiple second openings KB may have a different shape from the others. For example, the mask pattern 6 may be configured to include multiple second openings KB with different lengths in at least one of the X and Y directions, or it may be configured to include an annular second opening KB and a rectangular second opening.

[0012] The template substrate 7 has a base layer 4 including a seed layer 3 above the main substrate 1, and can be configured such that the seed portion 3S of the seed layer 3 is exposed at least in the first and second openings KF and KB. The first and second openings KF and KB may also be tapered (a shape that narrows in width toward the base layer 4 side).

[0013] In the template substrate 7 shown in Figure 1, multiple layers are stacked on the main substrate 1, and the stacking direction can be "upward." Furthermore, viewing a substrate-like object such as the template substrate 7 from a line of sight parallel to the substrate normal can be referred to as a "planar view."

[0014] [Semiconductor substrates] Figure 4 is a plan view showing the configuration of a semiconductor substrate according to this embodiment. Figure 5A is a cross-sectional view taken along the arrow AA in Figure 4. Figure 5B is a cross-sectional view taken along the arrow cc in Figure 4. As shown in Figures 4, 5A, and 5B, the semiconductor substrate 10 comprises a template substrate 7 and first and second semiconductor portions 8F and 8B located above the mask pattern 6. The term "semiconductor substrate" means a substrate that includes semiconductor portions, and the main substrate 1 may be a semiconductor or a non-semiconductor. At least one of the first and second semiconductor portions 8F and 8B may be a layered semiconductor layer.

[0015] The first and second semiconductor sections 8F and 8B include, for example, a nitride semiconductor. Nitride semiconductors can be represented as, for example, AlxGayInzN (0≦x≦1;0≦y≦1;0≦z≦1;x+y+z=1), and specific examples include GaN-based semiconductors, AlN (aluminum nitride), InAlN (indium aluminum nitride), and InN (indium nitride). GaN-based semiconductors are semiconductors containing gallium atoms (Ga) and nitrogen atoms (N), and typical examples include GaN, AlGaN, AlGaInN, and InGaN. The first and second semiconductor sections 8F and 8B may be doped (e.g., n-type including a donor) or undoped.

[0016] The first and second semiconductor parts 8F and 8B containing nitride semiconductors can be formed by the ELO method. In the ELO method, for example, a GaN-based semiconductor and a different substrate with a different lattice constant are used as the main substrate 1, a GaN-based semiconductor is used for the seed part 3S, an inorganic compound film is used for the mask pattern 6, and the GaN-based first and second semiconductor parts 8F and 8B can be grown laterally on the mask part 5. In this case, the thickness direction (Z direction) of the first semiconductor part 8F is the GaN-based crystal <0001> The direction (c-axis direction), the width direction (first direction, X direction) of the longitudinally shaped first and second openings KF·KB can be the <11-20> direction (a-axis direction) of the GaN-based crystal, and the longitudinal direction (Y direction) of the first and second openings KF·KB can be the <1-100> direction (m-axis direction) of the GaN-based crystal. The first semiconductor part 8F or the first and second semiconductor parts 8F·8B formed by the ELO method are sometimes collectively referred to as the ELO semiconductor part (ELO semiconductor layer) 8.

[0017] The first semiconductor portion 8F formed by the ELO method includes multiple ridges 8U corresponding to each of the multiple first openings KF, with each ridge 8U having its longitudinal direction in the Y direction. The ridges 8U include a low-defect portion (dislocation non-inheritance portion) EK with relatively few through-dislocations, and a dislocation inheritance portion NS that overlaps with the first opening KF in a plan view and has relatively many through-dislocations. When an active layer (for example, a layer where electrons and holes bond) is formed above the first semiconductor portion 8F, the active layer can be provided so as to overlap with the low-defect portion EK in a plan view. In the low-defect portion EK, <0001> The non-penetrating dislocation density in a cross-section parallel to the direction may be greater than the penetrating dislocation density.

[0018] A penetrating dislocation is a dislocation (defect) that extends from the bottom surface or interior of the first semiconductor portion 8F to its surface or surface layer along the thickness direction (Z direction) of the first semiconductor portion 8F. Penetrating dislocations can be observed by performing a CL (Cathode luminescence) measurement on the surface (parallel to the c-plane) of the first semiconductor portion 8F. Non-penetrating dislocations are dislocations measured by CL in a cross section parallel to the thickness direction, and are mainly basal plane (c-plane) dislocations. A cross section parallel to the thickness direction is, for example, the (1-100) plane (m-plane) or the (11-20) plane (a-plane).

[0019] In Figures 4 and 5, each ridge 8U of the first semiconductor portion 8F is separated from the second semiconductor portion 8B. Because the first opening KF is separated from the second opening KB, which is positioned along the edge E (closer to the edge than the first opening KF), even if the second semiconductor portion 8B, which overlaps with the second opening KB in a plan view, becomes an unintended deformity, the first semiconductor portion 8F, which overlaps with the first opening FK in a plan view, is less likely to meet with the second semiconductor portion 8B and is less affected by it. In other words, in this embodiment, the shape of the first semiconductor portion 8F can be guaranteed by using the second semiconductor portion 8B as a sacrificial layer. As shown in Figures 4 and 5, if the second semiconductor portion 8B becomes an unintended deformity, the average thickness of the second semiconductor portion 8B may become smaller than the average thickness of the first semiconductor portion 8F due to increased raw material consumption.

[0020] For example, when forming an opening in the mask pattern that extends in the Y direction from edge to edge of the main substrate in a plan view, and depositing a semiconductor film using the ELO method, there is a risk that shape distortion of the peripheral semiconductor portion may propagate to the inner (non-peripheral) semiconductor portion. However, this risk can be reduced by providing a second opening KB separated from the first opening KF.

[0021] Figure 6 is a cross-sectional view showing an alternative configuration of the semiconductor substrate according to this embodiment. As shown in Figure 6, the semiconductor substrate 10 can also be constructed by removing the sacrificial layer, the second semiconductor portion 8B.

[0022] Figure 7 is a cross-sectional view showing an alternative configuration of the semiconductor substrate according to this embodiment. The semiconductor substrate 10 in Figure 7 has a functional layer 9 above the first and second semiconductor portions 8F and 8B. The functional layer 9 may be a compound semiconductor portion containing, for example, a nitride semiconductor, and may be a single layer or a laminate.

[0023] In the semiconductor substrate 10 shown in Figure 7, the portion including the sacrificial layer, the second semiconductor portion 8B, is an unusable portion NP, and the portion including the first semiconductor portion 8F is an usable portion DP.

[0024] [Manufacturing of template circuit boards] Figure 8 is a flowchart showing an example of a method for manufacturing a template substrate according to this embodiment. In the method for manufacturing a template substrate shown in Figure 8, after the step of preparing the main substrate 1, a step of forming a mask pattern 6 above the main substrate 1 is performed.

[0025] Figure 9 is a block diagram showing an example of a template substrate manufacturing apparatus according to this embodiment. The template substrate manufacturing apparatus 60 in Figure 9 comprises a mask pattern forming unit 62 that forms a mask pattern 6 above the main substrate 1, and a control unit 64 that controls the mask pattern forming unit 62. The mask pattern forming unit 62 forms a mask portion 5, a plurality of first openings KF that are the width direction in the X direction and the longitudinal direction in the Y direction and overlap with the non-peripheral portion 1P in a plan view, and one or more second openings KB that are arranged along the edge E in a plan view.

[0026] The mask pattern forming unit 62 may include a CVD apparatus or a PECVD apparatus, and the control unit 64 may include a processor and memory. The control unit 64 may be configured to control the mask pattern forming unit 62 by executing a program stored in, for example, an internal memory, a communication device, or an accessible network, and this program and the recording medium on which this program is stored are also included in this embodiment.

[0027] [Manufacturing of semiconductor substrates] Figure 10 is a flowchart showing an example of a semiconductor substrate manufacturing method according to this embodiment. In the semiconductor substrate manufacturing method of Figure 10, after the step of preparing a template substrate 7, the first and second semiconductor parts 8F and 8B are formed on the template substrate 7 using the ELO method. After the step of forming the first and second semiconductor parts 8F and 8B, a step of forming a functional layer 9 can be performed as needed.

[0028] Figure 11 is a block diagram showing an example of a semiconductor substrate manufacturing apparatus according to this embodiment. The semiconductor substrate manufacturing apparatus 70 in Figure 11 includes a semiconductor part forming unit 72 that forms first and second semiconductor parts 8F and 8B on a template substrate 7 by the ELO method, and a control unit 74 that controls the semiconductor part forming unit 72. The semiconductor substrate manufacturing apparatus 70 may also be configured to form a functional layer 9.

[0029] [Manufacturing of semiconductor devices] Figure 12 is a flowchart showing an example of a semiconductor device manufacturing method according to this embodiment. Figure 13 is a plan view showing an example of element separation. Figure 14 is a cross-sectional view (cross-sectional view in the direction of the arrow in Figure 13) showing an example of element separation and separation. In the semiconductor device manufacturing method of Figure 12, after the step of preparing the semiconductor substrate 10, a step of forming a functional layer 9 on the first and second semiconductor parts 8F and 8B is performed as needed. Then, as shown in Figures 13 and 14, a step of forming a plurality of trenches TR (separation grooves) in the semiconductor substrate 10 to separate the element part DS (including the low defect part EK of the ridge part 8U and the functional layer 9) is performed. The trenches TR penetrate the functional layer 9 and the first semiconductor part 8F. The underlayer 4 and the mask part 5 may be exposed in the trenches TR. At this stage, the element part DS is van der Waals coupled with the mask part 5 and is part of the semiconductor substrate 10. Subsequently, as shown in Figure 14, the element portion DS (including at least a part of the ridge portion 8U) of the usable portion DP is separated from the template substrate 7 to form a semiconductor device 20. The steps for preparing the semiconductor substrate 10 shown in Figure 12 may include each of the steps for manufacturing the semiconductor substrate shown in Figure 10.

[0030] Furthermore, the isolation of the element portion DS may be achieved by removing the portion of the first semiconductor portion 8F and the functional layer 9 that overlaps with the first opening KF in a plan view by vapor phase etching, thereby peeling the element portion DS from the template substrate 7. When peeling, for example, the first semiconductor portion 8F and the functional layer 9 can be easily peeled from the mask portion 5 using a stamp. The stamp may be a viscoelastic elastomer stamp, a PDMS (Polydimethylsiloxane) stamp, or an electrostatic adhesive stamp, etc.

[0031] [Semiconductor devices] As shown in Figure 14, a semiconductor device 20 (including, for example, a GaN-based crystal) can be formed by separating the element portion DS from the template substrate 7. Specific examples of the semiconductor device 20 include light-emitting diodes (LEDs), semiconductor lasers, Schottky diodes, photodiodes, and transistors (including power transistors and high electron-mobility transistors).

[0032] [Electronic equipment] Figure 15 is a schematic diagram showing the configuration of the electronic device according to this embodiment. The electronic device 30 in Figure 15 includes a semiconductor substrate 10 (configured to function as a semiconductor device including a template substrate 7, for example, when the template substrate 7 is translucent), a drive substrate 23 on which the semiconductor substrate 10 is mounted, and a control circuit 25 that controls the drive substrate 23.

[0033] Figure 16 is a schematic diagram showing an alternative configuration of the electronic device according to this embodiment. The electronic device 30 in Figure 16 includes a semiconductor device 20 including a first semiconductor section 8F, a drive substrate 23 on which the semiconductor device 20 is mounted, and a control circuit 25 that controls the drive substrate 23.

[0034] Examples of electronic devices 30 include display devices, laser emission devices (including Fabry-Perot type and surface-emitting type), lighting devices, communication devices, information processing devices, sensing devices, power control devices, and the like.

[0035] [Example 1] Figure 17 is a plan view showing the configuration of the template substrate according to Example 1. Figure 18 is a cross-sectional view taken along the arrow dd in Figure 17. Figure 19 is a plan view showing the configuration of the semiconductor substrate according to Example 1.

[0036] As shown in Figures 17 and 18, the mask pattern 6 of the template substrate 7 according to Embodiment 1 has a mask portion 5, a plurality of first openings KF1 and KF2 whose width direction is in the X direction and length direction is in the Y direction, overlapping with the non-peripheral portion 1P in a plan view, and a plurality of second openings KB1 to KB4 which are arranged along the edge E in a plan view. The peripheral portion 1S can be, for example, an area within 2 mm from the edge E.

[0037] (Main board) The main substrate 1 can be a heterogeneous substrate having a different lattice constant from the GaN-based semiconductor. Examples of heterogeneous substrates include single-crystal silicon (Si) substrates, sapphire (Al2O3) substrates, silicon carbide (SiC) substrates, etc. The plane orientation of the main substrate 1 is, for example, the (111) plane for a silicon substrate, the (0001) plane for a sapphire substrate, and the 6H-SiC(0001) plane for a SiC substrate. These are examples, and any main substrate and plane orientation that can grow the first and second semiconductor parts 8F and 8B by the ELO method is acceptable.

[0038] (base layer) As the base layer 4, a buffer layer 2 and a seed layer 3 can be provided in order from the main substrate side. The buffer layer 2 has the function of reducing the direct contact between the main substrate 1 and the seed layer 3 and the melting of each other. When a silicon substrate or the like is used for the main substrate 1, it melts with the GaN-based semiconductor seed layer 3, so by providing a buffer layer 2 such as an AlN layer, melting is reduced. For example, when a main substrate 1 that does not melt with the seed layer 3, which is a GaN-based semiconductor, is used, a configuration without a buffer layer 2 is also possible. An example of a buffer layer 2, an AlN layer, can be formed to a thickness of about 10 nm to 5 μm using, for example, an MOCVD apparatus. The buffer layer 2 may have at least one of the effects of increasing the crystallinity of the seed layer 3 and relaxing the internal stress of the ELO semiconductor part 8. Hexagonal or cubic silicon carbide (SiC) can also be used for the buffer layer 2.

[0039] For the seed layer 3, for example, a GaN-based semiconductor such as GaN, a nitride such as AlN, or hexagonal silicon carbide (SiC) can be used. The seed layer 3 includes a seed portion 3S (growth starting point of the ELO semiconductor portion 8) that overlaps with the first and second openings (KF1~KF2·KB1~KB4) of the mask pattern 6.

[0040] As seed layer 3, a graded layer whose Al composition approaches GaN in a graded manner may be used. The graded layer may be, for example, the first layer, Al, starting from the buffer layer side. 0.7 Ga 0.3 N layer and the second layer, Al 0.3 Ga 0.7 This is a laminate with an N layer. In this case, the composition ratio of Ga in the second layer (Al:Ga:N=0.3:0.7:1) (0.7 / 2=0.35) is greater than the composition ratio of Ga in the first layer (Al:Ga:N=0.7:0.3:1) (0.3 / 2=0.15). The graded layer can be easily formed by the MOCVD method and may consist of three or more layers. By using a graded layer as the seed layer 3, stress from the main substrate 1, which is a different type of substrate, can be relieved. The seed layer 3 may include a GaN layer. In this case, the seed layer 3 may be a single layer of GaN, or the top layer of the graded layer which is the seed layer 3 may be a GaN layer.

[0041] Furthermore, a seed layer 3 does not necessarily have to be placed on the main substrate 1. Depending on the type of main substrate 1, the ELO semiconductor portion 8 can be directly deposited on the main substrate 1 with the mask pattern 6 even without a seed layer. For example, it is possible to form a mask pattern 6 including the mask portion 5 and the first aperture KF on a SiC substrate 1 and (directly) deposit the ELO semiconductor portion 8 made of GaN onto the mask pattern.

[0042] (Mask pattern) The first opening KF of the mask pattern 6 (mask layer) has the function of a growth initiation hole that exposes the seed portion 3S and initiates the growth of the ELO semiconductor portion 8, and the mask portion 5 may have the function of a selective growth mask for growing the semiconductor portion 8 laterally. The openings of the mask pattern are areas without mask portions (unformed areas), and may or may not be surrounded by mask portions. As the mask pattern 6, for example, a single layer film containing one of the following can be used: a silicon oxide film (SiOx), a titanium nitride film (TiN, etc.), a silicon nitride film (SiNx), a silicon oxynitride film (SiON), and a metal film having a high melting point (e.g., 1000 degrees or higher) (e.g., films of platinum, rhodium, iridium, ruthenium, osmium, tungsten, molybdenum, etc.), or a multilayer film containing at least two of these.

[0043] For example, a silicon oxide film with a thickness of approximately 100 nm to 4 μm (preferably approximately 150 nm to 2 μm) is formed over the entire surface of the substrate layer 4 using a sputtering method, and a resist is applied to the entire surface of the silicon oxide film. Then, the resist is patterned using a photolithography method to form a resist with multiple stripe-shaped openings. Subsequently, a portion of the silicon oxide film is removed using a wet etchant such as hydrofluoric acid (HF) or buffered hydrofluoric acid (BHF) to create multiple openings (including KF1 to KF2 and KB1 to KB4), and the mask pattern 6 is formed by removing the resist with organic washing.

[0044] The width of the first openings KF1 and KF2 is set to approximately 0.1 μm to 20 μm. The smaller the width of the first openings KF1 and KF2, the fewer through transitions propagating from the first openings KF1 and KF2 to the ELO semiconductor section 8. Furthermore, it becomes easier to peel (separate) the ELO semiconductor section 8 from the template substrate 7 in subsequent processes. In addition, the area of ​​the low-defect section EK with fewer surface defects in the ELO semiconductor section 8 (ridge section 8U) can be increased.

[0045] While silicon oxide films may decompose and evaporate in small amounts during the deposition of the ELO semiconductor portion 8 and be incorporated into the ELO semiconductor portion 8, silicon nitride films and silicon oxynitride films have the advantage of being less prone to decomposition and evaporation at high temperatures. Therefore, the mask portion 5 may be a single layer of silicon nitride film or silicon oxynitride film, or a laminated film in which silicon oxide film and silicon nitride film are formed in that order on the base layer 4, or a laminated film in which silicon nitride film and silicon oxide film are formed in that order on the base layer 4, or a laminated film in which silicon nitride film, silicon oxide film and silicon nitride film are formed in that order on the base layer.

[0046] Any abnormalities in the mask portion 5, such as pinholes, can be eliminated by performing organic cleaning after film formation and then reintroducing the material into the film formation apparatus to form the same type of film again. A high-quality mask portion 5 can also be formed using a general silicon oxide film (single layer) and this re-formation method.

[0047] In Example 1, in a plan view, the minimum distance between the multiple first openings KF1-KF2 and edge E is greater than the distance between the multiple second openings KB1-KB4 and edge E. Also, multiple first openings (including KF1-KF2) with their longitudinal side in the Y direction are aligned in the X direction, and their lengths in the Y direction decrease as they move away from the central MC of the main substrate in the X direction. For example, the first opening KF2 is located at a greater distance in the X direction from the central MC of the main substrate and has a smaller length in the Y direction compared to the first opening KF1. Furthermore, the minimum length Yf in the Y direction of the multiple first openings (including KF1-KF2) is greater than the length Yb in the Y direction of the multiple second openings (including KB1-KB4). In addition, the number of multiple second openings (including KB1-KB4) is equal to twice the number of multiple first openings (including KF1-KF2).

[0048] Furthermore, the first opening KF1 and the second opening KB1 are adjacent to each other and overlap when viewed in the Y direction, and the first opening KF1 is located between two second openings KB1 and KB3 that are aligned in the Y direction. That is, the second opening KB1, the first opening KF1, and the second opening KB3 are aligned in the Y direction, with one end of the first opening KF1 adjacent to the second opening KB1 and the other end adjacent to the second opening KB3. The distance between the first opening KF1 and the second opening KB1, and the distance between the first opening KF1 and the second opening KB3 are greater than the distance between the second openings KB1 and KB3 and edge E. The width (length in the X direction) of the second openings KB1 and KB3 may be the same as, greater than, or less than the width of the first opening KF1. The widths of the multiple second openings KB1 to KB4 may be different.

[0049] In a plan view, the aperture pattern, which includes multiple first apertures KF1-KF2 and multiple second apertures KB1-KB4, may be symmetrical with respect to a line passing through the central MC of the main substrate and parallel to the X direction.

[0050] In Example 1, the edge E of the main substrate 1 is configured to have a curved portion Er and a flat portion Ef connected to the curved portion Er and having a normal parallel to the X direction, but the invention is not limited to this configuration. The main substrate 1 may be disc-shaped. The flat portion Ef may function as an orientation marker (orientation flat). The orientation marker can also be configured as a notch.

[0051] (Specific example of a template circuit board) The main substrate 1 is a silicon substrate having a (111) plane, and the buffer layer 2 of the underlayer 4 is an AlN layer (for example, 30 nm). The underlayer 4 is the first layer Al 0.6 Ga 0.4 Let's assume a graded layer in which an N layer (e.g., 300 nm) and a second GaN layer (e.g., 1-2 μm) are formed in this order. That is, the composition ratio of Ga in the second layer (Ga:N=1:1) (1 / 2=0.5) is greater than the composition ratio of Ga in the first layer (Al:Ga:N=0.6:0.4:1) (0.6 / 2=0.3).

[0052] The mask portion 5 used a laminate in which a silicon oxide film (SiO2) and a silicon nitride film (SiN) were formed in that order. The thickness of the silicon oxide film was, for example, 0.3 μm, and the thickness of the silicon nitride film was, for example, 70 nm. Plasma chemical vapor deposition (CVD) was used to deposit both the silicon oxide film and the silicon nitride film.

[0053] (ELO Semiconductor Division) As shown in Figure 19, the semiconductor substrate 10 of Example 1 includes a first semiconductor portion 8F that overlaps with the first apertures KF1 and KF2 in a plan view, and a second semiconductor portion 8B that overlaps with the second apertures KB1 and KB2 in a plan view. The first and second semiconductor portions 8F and 8B can be ELO semiconductor portions containing a nitride semiconductor (for example, GaN-based).

[0054] The first semiconductor portion 8F has its longitudinal direction in the Y direction and includes a plurality of ridges 8U arranged in the X direction. The ends of each ridge 8U are tapered. In Embodiment 1, a plurality of second openings KB1 and KB2 are provided along the edge E. This separates each ridge 8U of the first semiconductor portion 8F from the irregularly shaped second semiconductor portion 8B (sacrificial layer), and ensures the shape (e.g., thickness and width) of each ridge 8U.

[0055] In Example 1, the first and second semiconductor sections 8F and 8B were made of GaN layers, and ELO film deposition was performed on the template substrate 7 using the MOCVD apparatus included in the semiconductor formation section 72 in Figure 11. As an example of ELO film deposition conditions, the following conditions can be used: substrate temperature: 1120°C, growth pressure: 50kPa, TMG (trimethylgallium): 22sccm, NH3: 15slm, V / III = 6000 (ratio of the amount of Group V raw material supplied to the amount of Group III raw material supplied).

[0056] In this case, the first and second semiconductor portions 8F and 8B are selectively grown on the seed portion 3S (the uppermost GaN layer of the seed layer 3) exposed at the first and second openings KF1, KF2, KB1, and KB2, and subsequently grow laterally on the mask portion 5. Then, the lateral growth of these films (ridge portions 8U) that have grown laterally from both sides on the mask portion 5 is stopped before they meet.

[0057] The width Wm of the mask portion 5 was 50 μm, the width of the first openings KF1 and KF2 was 5 μm, the width of each ridge portion 8U of the first semiconductor portion 8F was 53 μm, the width (size in the X direction) of the low-defect portion EK was 24 μm, and the layer thickness of the ridge portion 8U was 5 μm. The aspect ratio was 53 μm / 5 μm = 10.6, achieving a very high aspect ratio.

[0058] In forming the first semiconductor portion 8F, it is preferable to reduce the interaction between the first semiconductor portion 8F and the mask portion 5, so that the first semiconductor portion 8F and the mask portion 5 are in contact due to van der Waals forces.

[0059] The method for increasing the lateral film deposition rate is as follows: First, a longitudinal growth layer is formed on the seed portion 3S, growing in the Z direction (c-axis direction), and then a lateral growth layer is formed, growing in the X direction (a-axis direction). In this process, by setting the thickness of the longitudinal growth layer to 10 μm or less, 5 μm or less, 3 μm or less, or 1 μm or less, the thickness of the lateral growth layer can be kept low, thereby increasing the lateral film deposition rate.

[0060] Figure 20 is a cross-sectional view showing an example of lateral growth of the first semiconductor portion. As shown in Figure 20, it is desirable to form an initial growth layer (vertical growth layer) SL on the seed portion 3S, and then grow the first semiconductor portion 8F (multiple ridges 8U) laterally from the initial growth layer SL. The initial growth layer SL serves as the starting point for the lateral growth of the first semiconductor portion 8F. By appropriately controlling the ELO film deposition conditions, it is possible to control the growth of the first semiconductor portion 8F in the Z direction (c-axis direction) or in the X direction (a-axis direction).

[0061] Here, a method can be used in which the deposition of the initial growth layer SL is stopped just before the edge of the initial growth layer SL rides up onto the upper surface of the mask portion 5 (when it is in contact with the upper side of the mask portion 5), or immediately after it rides up onto the upper surface of the mask portion 5 (i.e., at this timing, the ELO deposition conditions are switched from c-axis deposition conditions to a-axis deposition conditions). In this way, since the deposition in the lateral direction proceeds from a state in which the initial growth layer SL is slightly protruding from the mask portion 5, the amount of material consumed for growth in the thickness direction is reduced, and the first semiconductor portion 8F (multiple ridge portions 8U) can be grown laterally at high speed. The initial growth layer SL can be formed to a thickness of, for example, 50 nm to 5.0 μm (for example, 80 nm to 2 μm). The thickness of the mask portion 5 and the thickness of the initial growth layer SL may be 500 nm or less.

[0062] For the ridges 8U of the first semiconductor section 8F, as shown in Figure 20, by depositing an initial growth layer SL (part of the dislocation inheritance section NS) and then growing it laterally, the number of non-penetrating dislocations inside the low-defect section EK can be increased (the density of penetrating dislocations on the surface of the low-defect section EK can be reduced). Furthermore, the distribution of impurity concentrations (e.g., silicon, oxygen) inside the low-defect section EK can be controlled. Using the method in Figure 20, the aspect ratio of the ridges 8U (ratio of size in the X direction to thickness = WL / d1) can be dramatically increased to 3.5 or higher, 5.0 or higher, 6.0 or higher, 8.0 or higher, 10 or higher, 15 or higher, 20 or higher, 30 or higher, or even 50 or higher. Furthermore, by using the method shown in Figure 20, the ratio of the width (WL) of the ridge portion 8U to the opening width can be set to 3.5 or more, 5.0 or more, 6.0 or more, 8.0 or more, 10 or more, 15 or more, 20 or more, 30 or more, or 50 or more, thereby increasing the ratio of low-defect portions EK. The first semiconductor portion 8F shown in Figure 20 can be made of a nitride semiconductor crystal (for example, a GaN crystal, an AlGaN crystal, an InGaN crystal, or an InAlGaN crystal).

[0063] Regarding the deposition temperature of the ELO semiconductor portion 8 (first and second semiconductor portions 8F and 8B), temperatures of 1150°C or lower are preferred over high temperatures exceeding 1200°C. Formation of the ELO semiconductor portion 8 is possible even at low temperatures below 1000°C, and this is even more preferable from the viewpoint of reducing mutual reactions. In such low-temperature deposition, when trimethylgallium (TMG) is used as the gallium raw material, the raw material is not sufficiently decomposed, and more gallium atoms and carbon atoms are incorporated into the ELO semiconductor portion 8 than usual. This is thought to be because in the ELO method, deposition is fast in the a-axis direction and slow in the c-axis direction, so more atoms are incorporated during c-plane deposition.

[0064] The carbon incorporated into the ELO semiconductor section 8 reduces the reaction with the mask section 5 and reduces adhesion between the mask section 5 and the ELO semiconductor section 8. Therefore, in low-temperature film deposition of the ELO semiconductor section 8, by reducing the supply of ammonia and depositing the film at a low V / III (<1000) level, carbon elements in the raw materials or chamber atmosphere can be incorporated into the ELO semiconductor section 8, reducing the reaction with the mask section 5. In this case, the ELO semiconductor section 8 will have a carbon-containing structure.

[0065] For low-temperature film deposition below 1000°C, it is preferable to use triethylgallium (TEG) as the gallium raw material gas. Compared to TMG, TEG allows for more efficient decomposition of organic raw materials at low temperatures, thus increasing the lateral film deposition rate.

[0066] Figure 21 is a plan view showing another configuration example of the template substrate according to Embodiment 1. Figure 22 is a plan view showing the configuration of a semiconductor substrate including the template substrate of Figure 21. In Figure 17, the first aperture KF1 and the second aperture KB1 are adjacent to each other and overlap when viewed in the Y direction, but are not limited to this. As in Figure 21, the mask pattern 6 may include a plurality of first apertures KF1 and KF2 and second apertures KB1 to KB6 arranged along the edge E, and the first aperture KF1 and the second aperture KB1 may be adjacent to each other and overlap when viewed in the X direction. In Figure 21, one end of the first aperture KF2 is located between the second apertures KB1 and KB2 aligned in the X direction, and the other end is located between the second apertures KB3 and KB4 aligned in the X direction. Furthermore, the number of multiple second openings (including KB1 to KB6) is more than twice the number of multiple first openings (including KF1 and KF2), and in the X direction, the second openings KB5 and KB6 are located outside the two outermost first openings among all the first openings.

[0067] The semiconductor substrate 10 in Figure 22 includes a first semiconductor portion 8F that overlaps the mask portion 5 and the first openings KF1 and KF2 in a plan view, and a second semiconductor portion 8B that overlaps the mask portion 5 and the second openings KB1 and KB2 in a plan view. The first semiconductor portion 8F includes a plurality of ridges 8U that overlap the first openings KF1 and KF2 in a plan view. In Figures 11 and 22, the plurality of second openings KB1 and KB2 are arranged along the edge E of the main substrate 1 in a plan view, so that each ridge 8U of the first semiconductor portion 8F is separated from the irregularly shaped second semiconductor portion 8B (sacrificial layer), and the shape of each ridge 8U is ensured. Furthermore, for example, since the tip of the first opening KF2 is sandwiched between two second openings KB1 and KB2 aligned in the X direction, edge growth (protrusions) that occur at the tip of the ridge 8U overlapping the first opening KF2 can be reduced.

[0068] Figure 23 is a plan view showing another configuration example of the template substrate according to Embodiment 1. In Figure 23, the mask pattern is provided with a plurality of first openings KF1 and KF2, and second openings KB1 to KB6 arranged along the edge E of the main substrate 1 in a plan view. The second opening KB2, the first opening KF1, and the second opening KB5 are aligned in the Y direction, with one end of the first opening KF1 adjacent to the second opening KB2 and the other end adjacent to the second opening KB5. Furthermore, one end of the first opening KF1 is located between the second openings KB1 and KB3 aligned in the X direction, and the other end is located between the second openings KB4 and KB6 aligned in the X direction.

[0069] Figure 24 is a plan view showing another configuration example of the template substrate according to Embodiment 1. As shown in Figure 24, a main substrate 1 including a curved surface Er can be used, and a plurality of second openings KB having a curved longitudinal shape can be arranged in the mask pattern 6 so as to follow the edge E of the main substrate 1 in a plan view.

[0070] [Example 2] Figure 25 is a plan view showing another configuration example of the template substrate according to Embodiment 2. Figure 26 is a plan view showing the configuration of a semiconductor substrate including the template substrate of Figure 25. In Embodiment 1, multiple second openings are provided in the mask pattern, but the invention is not limited to this. As shown in Figure 26, a main substrate 1 including a curved surface Er can be used, and an annular second opening KBL can be arranged in the mask pattern 6 so as to follow the edge E of the main substrate 1 in a plan view.

[0071] In Example 2, in a plan view, the minimum distance between the multiple first openings KF1-KF2 and edge E is greater than the distance between the annular second opening KBL and edge E. Also, multiple first openings (including KF1-KF2) with their longitudinal direction in the Y direction are aligned in the X direction, and their lengths in the Y direction decrease as they move away from the central MC of the main substrate in the X direction.

[0072] Furthermore, the first aperture KF1 and the second aperture KBL are adjacent to each other and overlap when viewed in the Y direction. In a plan view, the aperture pattern including the multiple first apertures KF1·KF2 and the annular second aperture KBL may be symmetrical with respect to a line passing through the central MC of the main substrate and parallel to the X direction.

[0073] The semiconductor substrate 10 in Figure 26 includes a first semiconductor portion 8F that overlaps with the first apertures KF1 and KF2 in a plan view, and a second semiconductor portion 8B that overlaps with the second aperture KBL in a plan view. The first semiconductor portion 8F includes a plurality of ridges 8U that overlap with the first apertures KF1 and KF2 in a plan view.

[0074] In Example 2 as well, since the annular second opening KBL is arranged along the edge E of the main substrate 1 in a plan view, each ridge 8U of the first semiconductor portion 8F is separated from the irregularly shaped second semiconductor portion 8B (sacrificial layer), and the shape of each ridge 8U is ensured.

[0075] Figure 27 is a plan view showing another configuration example of the template substrate according to Embodiment 2. In Figure 27, the mask pattern 6 includes a plurality of first openings KF1 and KF2, an annular second opening KBL arranged along edge E, and second openings KB1 to KB4 arranged along edge E, wherein the first opening KF1 and the second opening KB1 are adjacent to each other and may overlap when viewed in the X direction. In Figure 27, one end of the first opening KF2 is located between the second openings KB1 and KB2 aligned in the X direction, and the other end is located between the second openings KB3 and KB4 aligned in the X direction. Furthermore, the number of plurality of second openings (including KB1 to KB4) is less than twice the number of plurality of first openings (including KF1 and KF2), and with respect to the X direction, there are no island-shaped second openings outside of the two outermost first openings, and only the annular second opening KBL exists.

[0076] Figure 28 is a plan view showing another configuration example of the template substrate according to Embodiment 2. In Figure 27, a mask portion 5 exists on the edge of the template substrate 7, but it is not limited to this. As shown in Figure 28, the template substrate 7 may be configured without a mask portion on its edge. That is, when patterning the mask pattern 6, a ring-shaped seed portion 3S is exposed on the edge of the template substrate 7 by penetrating a ring-shaped region with the edge E of the main substrate 1 as its outer circumference in a plan view (providing a ring-shaped edge opening KE). In the template substrate 7 of Figure 28, an annular sacrificial layer is formed on its edge, so the shape of the first semiconductor portion 8F that overlaps with the first openings KF1 and KF2 is ensured.

[0077] [Example 3] In Examples 1 and 2, the ELO semiconductor portion 8 is a GaN layer, but the invention is not limited to this. In Examples 1 and 2, an InGaN layer, which is a GaN-based semiconductor portion, can also be formed as the first and second semiconductor portions 8F and 8B (ELO semiconductor portion 8). Lateral deposition of the InGaN layer is carried out at a low temperature, for example, below 1000°C. This is because at high temperatures, the vapor pressure of indium increases, and it is not effectively incorporated into the film. Lowering the deposition temperature has the effect of reducing the interaction between the mask portion 5 and the InGaN layer. In addition, the InGaN layer has the effect of being less reactive with the mask portion 5 than the GaN layer. It is desirable that the indium is incorporated into the InGaN layer at an In composition level of 1% or more, as this further reduces the reactivity with the mask portion 5. Triethylgallium (TEG) is preferably used as the gallium source gas.

[0078] [Example 4] Figure 29 is a schematic cross-sectional view showing the configuration of Example 4. In Example 4, a functional layer 9 constituting an LED is deposited on a base semiconductor portion 8S obtained as all or part of the ridge portion 8U of the first semiconductor portion 8F. The base semiconductor portion 8S is an n-type semiconductor doped with, for example, silicon. The functional layer 9 includes, in order from the bottom layer, an active layer 34, an electron blocking layer 35, and a GaN-based p-type semiconductor portion 36. The active layer 34 is MQW (Multi-Quantum Well) and includes an InGaN layer and a GaN layer. The electron blocking layer 35 is, for example, an AlGaN layer. The GaN-based p-type semiconductor portion 36 is, for example, a GaN layer. The anode 38 is arranged to be in contact with the GaN-based p-type semiconductor portion 36, and the cathode 39 is arranged to be in contact with the base semiconductor portion 8S. A semiconductor device 20 (including a GaN-based crystal) can be obtained by separating the base semiconductor portion 8S and the functional layer 10 from the template substrate 7.

[0079] Figure 30 is a cross-sectional view showing an example of the application of Embodiment 6 to an electronic device. According to Embodiment 4, a red micro-LED 20R, a green micro-LED 20G, and a blue micro-LED 20B can be obtained, and by mounting these on a drive board (TFT board) 23, a micro-LED display 30D (electronic device) can be constructed. As an example, the red micro-LED 20R, green micro-LED 20G, and blue micro-LED 20B are mounted on multiple pixel circuits 27 of the drive board 23 via a conductive resin 24 (for example, an anisotropic conductive resin), and then a control circuit 25 and a driver circuit 29 are mounted on the drive board 23. Part of the driver circuit 29 may be included in the drive board 23.

[0080] [Example 5] Figure 31 is a schematic cross-sectional view showing the configuration of Example 5. In Example 5, a functional layer 9 constituting a semiconductor laser is deposited on the base semiconductor portion 8S. The functional layer 9 includes, in order from the bottom layer, an n-type optical cladding layer 41, an n-type optical guide layer 42, an active layer 43, an electron blocking layer 44, a p-type optical guide layer 45, a p-type optical cladding layer 46, and a GaN-based p-type semiconductor portion 47. InGaN layers can be used for each guide layer 42-45. GaN layers or AlGaN layers can be used for each cladding layer 41-46. The anode 48 is arranged to be in contact with the GaN-based p-type semiconductor portion 47, and the cathode 49 is arranged to be in contact with the base semiconductor portion 8S. A semiconductor device 20 can be obtained by separating the base semiconductor portion 8S and the functional layer 10 from the template substrate 7.

[0081] [Example 6] Figure 32 is a cross-sectional view showing the configuration of Example 6. In Example 6, a sapphire substrate with a textured surface is used as the main substrate 1. The underlayer 4 has a buffer layer 2 and a seed layer 3. In Figure 32, a GaN layer having a (20-21) plane is deposited on the main substrate 1 as the underlayer 4. In this case, the first semiconductor portion 8F becomes the (20-21) plane, which is the crystal principal plane, in the underlayer 4, and a semipolar first semiconductor portion 8F can be obtained. By providing a functional layer for lasers and LEDs on the semipolar plane, there is an advantage in that the recombination probability of electrons and holes in the active layer is increased. Note that by using a sapphire substrate with a textured surface, a GaN layer having a (11-22) plane can also be deposited on the main substrate 1 as the underlayer 4. [Explanation of Symbols]

[0082] 1 Main board 2 buffer layers 3. Seed Layer 3S Seed Section 4 Base layer 5 Mask section 6 Mask Patterns 8F, Semiconductor Division 1 8B Semiconductor Section 2 8U ridge 9 Functional Layers 10 Semiconductor substrates 20 Semiconductor Devices 30 Electronic equipment KF KF1 / KF2 1st opening KB KB1~KB6 2nd opening

Claims

1. The device comprises a main substrate having an edge, a peripheral portion including the edge, and a non-peripheral portion located inside the peripheral portion, and a mask pattern located above the main substrate and having a mask portion. The mask pattern includes a plurality of first openings that overlap with the non-peripheral portion in a plan view, and a plurality of second openings that overlap with the peripheral portion in a plan view. The plurality of first openings are arranged in a first direction and form a stripe shape. A template substrate in which the plurality of second openings include two adjacent openings, and the distance between the two openings is smaller than the distance between adjacent first openings.

2. The template substrate according to claim 1, wherein the sum of the areas of the plurality of second openings is smaller than the sum of the areas of the plurality of first openings.

3. The template substrate according to claim 1 or 2, wherein the plurality of first openings and the plurality of second openings are separated.

4. The template substrate according to any one of claims 1 to 3, wherein the plurality of second openings have a longitudinal shape with the first direction as the longitudinal direction.

5. The template substrate according to claim 4, wherein the widths of the plurality of second openings are greater than the widths of the plurality of first openings.

6. The template substrate according to any one of claims 1 to 5, wherein the mask pattern is symmetrical with respect to a line passing through the center of the main substrate and parallel to the longitudinal direction of the plurality of first openings.

7. The template substrate according to any one of claims 1 to 6, wherein the widths of the two openings are different.

8. A template substrate according to any one of claims 1 to 7, wherein at least one of the plurality of first openings is adjacent to the plurality of second openings, and when viewed in the longitudinal direction of the plurality of first openings, at least one of the plurality of first openings and at least one of the plurality of second openings overlap.

9. The template substrate according to any one of claims 1 to 8, wherein the peripheral portion has an annular shape along the edge, and the non-peripheral portion is the region surrounded by the peripheral portion.

10. A template substrate according to any one of claims 1 to 9, having a seed layer that overlaps with the plurality of first openings in a plan view.

11. The template substrate according to claim 10, wherein each of the plurality of first openings is a seed region for growing a semiconductor layer to be used, and each of the plurality of second openings is a seed region for growing a semiconductor layer that is not to be used.

12. The main substrate is a sapphire substrate or a silicon substrate. A template substrate according to any one of claims 1 to 11, used for forming an ELO in a nitride semiconductor portion.

13. A semiconductor substrate comprising a template substrate according to any one of claims 1 to 12 and a first semiconductor portion that overlaps with the mask portion.

14. A template substrate comprising: a main substrate having an edge, a peripheral portion including the edge, and a non-peripheral portion located inside the peripheral portion; and a mask pattern located above the main substrate and having a mask portion, wherein the mask pattern includes a plurality of first openings that overlap with the non-peripheral portion in a plan view, and a plurality of second openings that overlap with the peripheral portion in a plan view, and the plurality of first openings are arranged in a first direction and form a stripe shape, The mask portion comprises a first semiconductor portion that overlaps the mask portion, The first semiconductor portion includes a nitride semiconductor, The longitudinal direction of the plurality of first openings is taken as the second direction, The first direction is the a-axis direction of the nitride semiconductor, The second direction is the m-axis direction of the nitride semiconductor, and the semiconductor substrate.

15. A step of preparing a semiconductor substrate according to claim 13 or 14, A method for manufacturing a semiconductor device, comprising the step of forming a functional layer above the first semiconductor portion.

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