Memory device and method for erasing and verifying the same

Abstract

To provide a memory device capable of increasing channel discharge time for avoiding false error verification and a method for erasing and verifying the same.SOLUTION: A memory device includes a plurality of memory blocks and a control circuit. The memory block selected from among the plurality of memory blocks includes an upper selection gate, a lower selection gate, a plurality of word lines, a common source line, and a P well. The control circuit executes an erasure and verification method, and the erasure and verification method includes: a step of erasing the selected memory block during an erasing stage; and a step of performing maintenance in a manner such that the lower selection gate is turned on during a maintenance period before the upper selection gate is turned on during a verifying stage.SELECTED DRAWING: Figure 7

Description

Technical Field

[0001] The present invention relates to a memory device and a method for erasing and verifying the same, and more particularly, to a memory device capable of increasing channel discharge time to avoid false error verification and a method for erasing and verifying the same.

Background Art

[0002] Semiconductor memories are widely used in various electronic devices such as mobile phones, digital cameras, portable information terminals, medical electronic devices, mobile computing devices, and non-mobile computing devices. Non-volatile memories enable information to be stored and retained. Examples of non-volatile memories include flash memories (e.g., NAND-type and NOR-type flash memories), as well as Electrically Erasable Programmable Read-Only Memories (EEPROMs).

[0003] Recently, ultra-high density storage devices using a three-dimensional (3D) stacked memory structure, sometimes referred to as a Bit Cost Scalable (BiCS) architecture, have been proposed. For example, a 3D NAND stacked flash memory device can be formed from an array of alternating conductive and dielectric layers. Memory holes are drilled into the layers to define multiple memory layers simultaneously. Then, NAND strings are formed by filling the memory holes with an appropriate material. The control gates of the memory cells are provided by the conductive layers.

[0004] Each planar NAND memory consists of an array of memory cells connected by multiple word lines and bit lines. Data is programmed into or read from the planar NAND memory page by page, and erased from the planar NAND memory block by block; that is, a block is the unit of a conventional erase operation, and a page is the unit of a conventional programming operation.

[0005] In existing 3D NAND flash memory structures, a verification phase is required after the erase phase to confirm whether the erase was successful. However, false errors can occur during the verification phase in 3D NAND flash memory. [Overview of the project] [Problems that the invention aims to solve]

[0006] Therefore, an object of the present invention is to provide a memory device that can increase the channel discharge time in order to avoid false error verification, as well as a method for erasing and verifying the same. [Means for solving the problem]

[0007] The present invention discloses a memory device comprising a plurality of memory blocks and a control circuit. A selected memory block from the plurality of memory blocks comprises an upper selection gate, a lower selection gate, a plurality of word lines, a common source line, and a P-well. The control circuit performs an erase and verification method, which includes the steps of erasing the selected memory block during the erase phase and maintaining the lower selection gate to be turned on during the maintenance phase before the upper selection gate is turned on during the verification phase.

[0008] The present invention discloses an erasure and verification method for a memory device, wherein a selected memory block from among a plurality of memory blocks of the memory device comprises an upper selection gate, a lower selection gate, a plurality of word lines, a common source line, and a P-well. The erasure and verification method includes the steps of erasing the selected memory block during the erasure phase and maintaining the lower selection gate to be turned on during the maintenance phase before the upper selection gate is turned on during the verification phase.

[0009] These and other objectives of the present invention will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments shown in various figures and drawings. [Brief explanation of the drawing]

[0010] [Figure 1] This is a top view showing a single NAND string according to one embodiment of the present invention. [Figure 2] This figure shows the equivalent circuit of a single NAND string according to one embodiment of the present invention. [Figure 3] This figure shows an exemplary structure of a memory device according to one embodiment of the present invention. [Figure 4] This is a timing chart for the conventional erase and verification process. [Figure 5A] This is a timing chart for the erase and verification process according to one embodiment of the present invention. [Figure 5B] This is a schematic diagram of the channel potentials of a conventional erase and verification process and an erase and verification process according to one embodiment of the present invention. [Figure 6A] This is a timing chart for the erasure and verification process according to another embodiment of the present invention. [Figure 6B] This is a timing chart for the erasure and verification process according to another embodiment of the present invention. [Figure 7] This is a schematic diagram of the erasure and verification process according to one embodiment of the present invention. [Modes for carrying out the invention]

[0011] The following detailed description refers to the accompanying drawings, which illustrate specific embodiments in which the present invention may be carried out. These embodiments are described in sufficient detail so that those skilled in the art can carry out the present invention. It should be understood that the various embodiments of the present invention, while different, are not necessarily mutually exclusive. For example, a particular feature, structure, or characteristic described herein in relation to one embodiment may be implemented in other embodiments without departing from the spirit and scope of the present invention. In addition, it should be understood that the position or arrangement of individual elements within each disclosed embodiment may be modified without departing from the spirit and scope of the present invention. The following detailed description should therefore not be taken as restrictive, and the scope of the present invention is defined only by the accompanying claims, as appropriately interpreted, together with the entire scope of equivalents to be given to the claims. In the drawings, the same number refers to the same or similar function across several figures.

[0012] In the following description and in the claims, the terms “includes” and “equip” are used without limitation and should therefore be interpreted as “includes, but not limited.” The term “connects” is intended to mean indirect or direct electrical connection. Thus, when one device is electrically connected to another, that connection may be by direct electrical connection or by indirect electrical connection via other devices and connections. “Approximately” means within an acceptable error margin, within an error margin that a person skilled in the art can solve a technical problem and essentially achieve a technical effect.

[0013] Figure 1 is a top view showing a NAND string according to one embodiment of the present invention. Figure 2 is a diagram showing its equivalent circuit. In a flash memory system using a NAND structure, multiple transistors are arranged in series and sandwiched between two selection gates, and these are called a NAND string. The NAND string shown in Figures 1 and 2 includes four transistors 101-104 coupled in series and sandwiched between an upper selection gate SG_T and a lower selection gate SG_B (source side), and a substrate Sub, the substrate Sub having a P-well. The upper selection gate SG_T is positioned to connect the NAND string to the bit line via a bit line contact and can be controlled by applying an appropriate voltage to the selection gate line SGTL. The lower selection gate SG_B is positioned to connect the NAND string to a common source line CSL and can be controlled by applying an appropriate voltage to the selection gate line SGBL. The common source line CSL penetrates the stacked structure. Each of the transistors 101-104 includes a control gate and a floating gate. For example, transistor 101 includes a control gate CG1 and a floating gate FG1, transistor 102 includes a control gate CG2 and a floating gate FG2, transistor 103 includes a control gate CG3 and a floating gate FG3, and transistor 104 includes a control gate CG4 and a floating gate FG4. Control gate CG1 is connected to word line WL1, control gate CG2 is connected to word line WL2, control gate CG3 is connected to word line WL3, and control gate CG4 is connected to word line WL4.

[0014] For illustrative purposes, Figures 1 and 2 show four memory cells in a NAND string. In other embodiments, the NAND string may contain eight, sixteen, thirty-two, sixty-four, or twelve-eight memory cells. However, the number of memory cells in the NAND string does not limit the scope of the present invention.

[0015] A typical architecture of a flash memory system using a NAND structure includes several NAND strings. Each NAND string is connected to a common source line CSL by its lower selection gate SG_B, controlled by a selection line SGBL, and to its associated bit line by its upper selection gate SG_T, controlled by a selection line SGTL. Each bit line and each (one or more) NAND string connected to that bit line via bit line contacts contains a row of arrays of memory cells. Bit lines are shared among multiple NAND strings. Generally, bit lines run over the top of the NAND string, perpendicular to the word lines, and are connected to one or more sense amplifiers.

[0016] Figure 3 shows an exemplary structure of a memory device 30 according to one embodiment of the present invention. The memory device 30 includes a memory array 302 and a control circuit 304. The control circuit 304 is used to perform read, write, erase, and verification operations on the memory array 302 and may include a word line driver, a bit line driver, a column decoder, a sensing circuit, a data buffer, a program verification logic, and an erase verification circuit. The memory array 302 is divided into BLOCK1~BLOCK I The memory cell is divided into multiple memory blocks, indicated by I, where I is a positive integer and is generally equal to a large number. The blocks are located on bit lines BL1 to BL M , and word lines WL1~WL N It includes a set of NAND strings accessed via a common set, where M and N are integers greater than 1. One terminal of a NAND string is connected to the corresponding bit line via an upper selection gate (connected to the selection gate line SGTL), and the other terminal is connected to the common source line CSL via a lower selection gate (connected to the selection gate line SGBL). Each block is generally divided into several pages, indicated by dotted lines. In one embodiment, a block is the unit of a conventional erase operation, and a page is the unit of a conventional programming operation. However, other units of erase / program may also be used.

[0017] When the control circuit 304 performs an erase operation in block units, in order to avoid data remanence or metastability, which causes a shortening of the life of the 3D NAND flash memory, a corresponding verification operation must be performed to ensure that the corresponding memory cells are erased.

[0018] More specifically, during the verification stage, the corresponding memory cells are made conductive in order to examine whether the corresponding memory cells are "strong" logic 1 or "weak" logic 1 by measuring the threshold voltage of the corresponding memory cells. If the corresponding memory cells are not "strong" enough, or if the threshold voltage of the corresponding memory cells does not meet a predetermined threshold, the bit cell may change from logic 1 to logic 0 during aging, reducing the reliability of the 3D NAND flash. Therefore, after the erase stage, it is necessary to examine the bit cell to determine whether the threshold voltage of the corresponding memory cell meets a predetermined threshold. However, false errors may occur during the verification stage.

[0019] Specifically, refer to FIG. 4, which is a timing chart of a conventional erase and verification process. However, T1 is when the verification stage starts, T2 is when the voltage of the upper select gate SG_T starts to reach the turn-on voltage Von, and T3 is when the verification stage ends. As shown in FIG. 4, memory blocks BLOCK1 to BLOCK IWhen a selected memory block among them is selected to be erased, taking one NAND string as an example, the upper select gate SG_T, the lower select gate SG_B, and the common source line CSL are in a floating state, the word line is grounded, and the P-well is supplied with an erase voltage Ve in the erase stage (that is, the voltage of the P-well rises, is maintained as the erase voltage Ve for a certain time period, and then drops to zero). Therefore, the electrons trapped in the floating gate of the corresponding memory cell are attracted by the high erase voltage Ve of the P-well, leave the floating gate, and the corresponding memory cell comes to be erased.

[0020] Next, in the verification stage, the word line is supplied with a verification voltage Vv (for example, 2.2V), then the upper select gate SG_T and the lower select gate SG_B are supplied with a turn-on voltage Von, and finally the word line is supplied with the verification voltage Vv again to check whether the threshold voltage of the corresponding memory cell satisfies a predetermined threshold. If the threshold voltage of the corresponding memory cell does not satisfy the predetermined threshold, that is, if the verification during the verification stage fails, another erase stage and another verification stage are performed until the threshold voltage of the corresponding memory cell satisfies the predetermined threshold, or if the verification stage in which the verification fails is performed a predetermined number of times, an error message is generated.

[0021] However, since the upper selection gate SG_T and lower selection gate SG_B are floating during the erase phase, when the voltage in the P well drops to zero, the voltages of the upper selection gate SG_T and lower selection gate SG_B drop accordingly, then to the turn-on voltage Von, and the lower selection gate SG_B is turned off (as shown by the dotted line in Figure 5B), so that the channel stops discharging and becomes floating. Then, when the voltage of the word line rises to the verification voltage Vv during the verification phase (between T1 and T2), the potential of the channel is coupled with the voltage of the word line and remains at a higher potential. Subsequently, when the upper selection gate SG_T and lower selection gate SG_B are turned on during the verification phase (after T2), the channel is connected to the P well and therefore grounded, and the potential of the channel drops rapidly, so that the voltage of the word line is coupled with it and drops accordingly. As a result, a false error occurs in the first verification phase, which requires another erase phase and another verification phase, so that the corresponding memory cell is over-erase at a lower threshold voltage than required.

[0022] For example, if a corresponding memory cell is erased to strong logic 1 but is determined to be weak logic 1, another erasure stage is required to ensure the erasure is successful. However, since the corresponding memory cell is logically strong enough, erasing a corresponding memory cell that has strong logic 1 is a redundant step. As a result, longer erasure and verification stages lead to more false errors, reducing the reliability and programming performance of the memory device 30.

[0023] In comparison, the erasure and verification process of the present invention uses memory blocks BLOCK1~BLOCK IWhen a selected memory block is selected to be erased, the control circuit 304 keeps the lower selection gate SG_B on during the maintenance period before the upper selection gate SG_T is turned on during the verification phase. As a result, by keeping the lower selection gate SG_B on during the maintenance period before the upper selection gate SG_T is turned on during the verification phase, the present invention increases the channel discharge time to avoid word line voltage drop and subsequent false error verification.

[0024] For more details, please refer to Figures 5A and 5B. Figure 5A is a timing chart of the erase and verification process according to one embodiment of the present invention, and Figure 5B is a schematic diagram of the channel potentials of the conventional erase and verification process and the erase and verification process according to one embodiment of the present invention. As can be seen from Figure 5A, memory blocks BLOCK1~BLOCK I When a selected memory block is chosen to be erased, taking a single NAND string as an example, the lower selection gate SG_B is switched out of its floating state so that it is maintained at the turn-on voltage Von (e.g., 6.5V) for a hold period Pm before the upper selection gate SG_T changes. The hold period Pm is from when the voltage of the lower selection gate SG_B drops to the turn-on voltage Von as the voltage of the P well decreases until the upper selection gate SG_T is turned on during the verification phase.

[0025] Under such circumstances, the common source line CSL and the channel may be connected for the duration of the maintenance period Pm. Therefore, compared to conventional erase and verify processes, which have the problems of higher channel potential due to word line coupling and word line voltage drop due to channel discharge coupling as described above, the channel maintains a discharge state down to zero potential in the initial verification stage (after T1), as shown by the solid line in Figure 5B of the present invention, thereby increasing the channel discharge time and avoiding the word line voltage drop as shown in Figure 5A. Other operations of the erase and verify process can be derived by referring to the above description of conventional erase and verify processes, for example, the lower selection gate is in a floating state during the erase stage except for the maintenance period Pm, and will not be described below for brevity. As a result, the present invention improves the efficiency of the erase and verify process by increasing the channel discharge time to avoid subsequent false error verification.

[0026] In particular, the spirit of the present invention is to maintain the lower selection gate SG_B on during the maintenance period before the upper selection gate SG_T is turned on during the verification phase in order to increase the channel discharge time in order to avoid the voltage drop in the word line caused by channel discharge coupling. Those skilled in the art can make changes or modifications, which still fall within the scope of the present invention. For example, the maintenance period during which the lower selection gate SG_B is turned on is not limited to the maintenance period Pm shown in Figure 5A, but can be any other time interval as long as there is a maintenance period before the upper selection gate SG_T is turned on during the verification phase.

[0027] For example, see Figures 6A and 6B, which are timing charts of the erase and verification processes according to other embodiments of the present invention. As shown in Figure 6A, the maintenance period Pm' is within the verification phase, i.e., from near the midpoint between T1 and T2 until the upper selection gate SG_T is turned on. Under such circumstances, the channel potential may become higher due to word line coupling, as shown by the dotted line in Figure 5B as in a conventional erase and verification process, but the channel is still being discharged and can rapidly reach zero potential, even starting from the midpoint between T1 and T2 (see the solid line in Figure 5B, the channel can be discharged rapidly). As a result, even when the maintenance period Pm' is shorter than the maintenance period Pm, the embodiment in Figure 6A can also increase the channel discharge time to avoid the word line voltage drop due to channel discharge coupling.

[0028] On the other hand, as shown in Figure 6B, the maintenance period Pm'' is from the start of the erasure phase until the upper selection gate SG_T is turned on. Under such circumstances, the channel is made conductive to allow electrons to be emitted as quickly as possible.

[0029] In particular, the default value of the 3D NAND flash is logic 1 in the embodiments described above. However, in other embodiments, the default value of the 3D NAND flash may be logic 0, and the erase operation is to change the memory cell from 1 to 0. In one embodiment, a high voltage (e.g., 1.1 volts) represents logic 1, and in one embodiment, logic 1 may be represented by a low voltage (e.g., 0 volts), but is not limited thereto. Furthermore, the predetermined threshold between strong logic 1 and logic 0 may differ between process techniques; for example, the threshold may be 0.7 volts in 22nm ultra-low power (22ULP) technology. Those skilled in the art may make changes or modifications as appropriate, and are not limited herein.

[0030] Furthermore, while the present invention avoids false error verification, if the threshold voltage of the corresponding memory cell does not meet a predetermined threshold, i.e., if verification during the verification stage fails, an error message is generated if another erase stage and another verification stage are performed until the threshold voltage of the corresponding memory cell meets the predetermined threshold, or if the verification stage that failed has been performed a predetermined number of times. The criteria for determining the failure of the erase and verification process are not limited, but may be based on the threshold time, the number of thresholds, or a combination thereof for performing the erase and verification process on the 3D NAND flash. In addition, the threshold time or the number of thresholds may be predetermined or fixed by calibration, may be a number mapped in a table, or may be adjusted as appropriate to suit the actual scenario. Those skilled in the art may change the determination rules and make corresponding modifications, and are not limited herein.

[0031] In addition, the erase and verification process may be modified so that the verification stage is sequentially followed by multiple erase stages. For example, a 3D NAND flash erase and verification process may include a first erase stage, a second erase stage, and a verification stage. In one embodiment, in order to increase the channel discharge time and thus avoid the voltage drop in the word line due to channel discharge coupling, each of the erase and verification processes should include a hold period in which the lower selection gate SG_B is turned on.

[0032] In particular, the embodiments described above are used to illustrate the concept of the present invention. Those skilled in the art may make changes and modifications as appropriate, and are not limited herein. Therefore, the requirements of this application are met and the application is within the scope as long as the lower selection gate SG_B is turned on before the upper selection gate SG_T is turned on during the verification stage.

[0033] Figure 7 is a schematic diagram of an erasure and verification process 70 according to one embodiment of the present invention. As shown in Figure 7, the 3D NAND flash erasure and verification process 70 includes the following steps. Step 700: Start. Step 702: Erase the selected memory block during the erase phase. Step 704: Keep the lower selection gate SG_B turned on during the maintenance period before the upper selection gate SG_T is turned on during the verification phase. Step 706: Finished.

[0034] The detailed operation of the erase and verification process 70 can be derived by referring to the description above and will not be described below for brevity.

[0035] In summary, by keeping the lower selection gate SG_B turned on during the maintenance period before the upper selection gate SG_T is turned on during the verification phase, the present invention increases the channel discharge time to avoid word line voltage drop and false error verification caused by channel discharge coupling.

[0036] Those skilled in the art will readily realize that numerous changes and modifications of the device and method can be made while retaining the teachings of the present invention. Therefore, the above disclosure should be construed as being limited only by the boundaries and limitations of the appended claims. [Explanation of Symbols]

[0037] 30 memory devices 101 Transistors 102 transistors 103 Transistors 104 transistors 302 memory array 304 Control Circuit

Claims

1. A memory device, A memory string comprising a first selection gate, a memory cell, and a second selection gate, wherein the first selection gate is coupled to a first selection line, the memory cell is coupled to a word line, and the second selection gate is coupled to a second selection line. A control circuit coupled to the first selection line, the word line, and the second selection line Equipped with, The control circuit, In an erasure operation that includes an erasure step and a verification step following the erasure step, In the erasure step, an erasure voltage is applied to the memory string. In the first stage of the verification step, a first voltage is applied to the word line. In the verification step, in the second step following the first step, a second voltage lower than the first voltage is applied to the word line, and In the verification stage, the first turn-on voltage is applied to the second select line before the second voltage is applied to the word line. It is configured to do the following: A memory device in which the first turn-on voltage is applied to the second select line such that it is maintained from a predetermined time after the start of the erase step until at least the second voltage is applied to the word line.

2. A memory device, A memory string comprising a first selection gate, a memory cell, and a second selection gate, wherein the first selection gate is coupled to a first selection line, the memory cell is coupled to a word line, and the second selection gate is coupled to a second selection line. A control circuit coupled to the first selection line, the word line, and the second selection line Equipped with, The control circuit, In an erasure operation that includes an erasure step and a verification step following the erasure step, In the erasure step, an erasure voltage is applied to the memory string. In the first stage of the verification step, a first voltage is applied to the word line. In the verification step, in the second step following the first step, a second voltage lower than the first voltage is applied to the word line, and In the verification stage, the first turn-on voltage is applied to the second select line before the second voltage is applied to the word line. It is configured to do the following: The control circuit, After stopping the application of the erase voltage for a predetermined period, a second turn-on voltage is applied to the first select line. It is further configured to do the following: A memory device in which the application of the second voltage, the application of the first turn-on voltage, and the application of the second turn-on voltage overlap at least partially in a time series.

3. The first selection gate comprises an upper selection gate or a lower selection gate, The memory device according to claim 1 or 2, wherein the second selection gate comprises the lower selection gate or the upper selection gate.

4. The memory device according to claim 1 or 2, wherein in the first stage of the verification step, the first turn-on voltage is applied to the second select line.

5. The memory device according to claim 2, wherein the first turn-on voltage is applied to the second select line such that it is maintained from a predetermined time after the start of the erase step until at least the second voltage is applied to the word line.

6. The memory device according to claim 1 or 5, wherein the predetermined time is before the second voltage is applied to the word line.

7. The control circuit, Before applying the first turn-on voltage to the second select wire, the second select wire is made to a floating state, and From the moment the stray voltage on the second selection line drops to the first turn-on voltage, the first turn-on voltage is applied to the second selection line. A memory device according to claim 1 or 2, further configured to perform the following:

8. The memory device according to claim 1 or 2, wherein the second selection gate is turned on by the first turn-on voltage.

9. The memory string further comprises a P well, The memory device according to claim 1 or 2, wherein the control circuit is further configured to apply the first turn-on voltage to the second select line before the voltage on the P well drops from the erase voltage to a predetermined voltage.

10. The memory device according to claim 1 or 2, wherein the first turn-on voltage is higher than the first voltage.

11. The memory string further comprises a P well, The control circuit, When the erase voltage is applied to the P well, the word line is grounded. A memory device according to claim 1 or 2, further configured to perform the following:

12. The control circuit, From the moment the voltage on the word line drops to a predetermined voltage, the first turn-on voltage is applied to the second select line. The memory device according to claim 11, further configured to perform the following:

13. The control circuit, in the second step, After applying the second voltage to the word line, a third voltage higher than the second voltage is applied to the word line. A memory device according to claim 1 or 2, further configured to perform the following:

14. The memory device according to claim 1 or 2, wherein the application of the first voltage and the application of the first turn-on voltage overlap at least partially in a time series.

15. A method for operating a memory device having a memory string, The memory string comprises a first selection gate, a memory cell, and a second selection gate, wherein the first selection gate is coupled to a first selection line, the memory cell is coupled to a word line, and the second selection gate is coupled to a second selection line. The method described above is The erasure step involves applying an erase voltage to the memory string, In the first stage of the verification phase, the steps include applying a first voltage to the word line, In the verification stage, in the second stage following the first stage, a step of applying a second voltage lower than the first voltage to the word line, In the verification stage, the first turn-on voltage is applied to the second select line before the second voltage is applied to the word line. Includes, A method in which the first turn-on voltage is applied to the second select line such that it is maintained from a predetermined time after the start of the erasure step until at least the second voltage is applied to the word line.

16. A method for operating a memory device comprising a memory string, The memory string comprises a first selection gate, a memory cell, and a second selection gate, wherein the first selection gate is coupled to a first selection line, the memory cell is coupled to a word line, and the second selection gate is coupled to a second selection line. The method described above is The erasure step involves applying an erase voltage to the memory string, In the first stage of the verification phase, the steps include applying a first voltage to the word line, In the verification stage, in the second stage following the first stage, a step of applying a second voltage lower than the first voltage to the word line, In the verification stage, the first turn-on voltage is applied to the second select line before the second voltage is applied to the word line. Includes, The method further includes the step of applying a second turn-on voltage to the first select line after stopping the application of the erase voltage for a predetermined period of time. A method wherein the application of the second voltage, the application of the first turn-on voltage, and the application of the second turn-on voltage overlap at least partially in a time series.

17. The first selection gate comprises an upper selection gate or a lower selection gate, The method according to claim 15 or 16, wherein the second selection gate comprises the lower selection gate or the upper selection gate.

18. The method according to claim 15 or 16, wherein in the first step of the verification step, the first turn-on voltage is applied to the second select line.

19. The method according to claim 16, wherein the first turn-on voltage is applied to the second select line such that it is maintained from a predetermined time after the start of the erasure step until at least the second voltage is applied to the word line.

20. The method according to claim 15 or 19, wherein the predetermined time is before the second voltage is applied to the word line.

21. Before applying the first turn-on voltage to the second select wire, the second select wire is set to a floating state, The steps include applying the first turn-on voltage to the second select line from the moment the stray voltage on the second select line drops to the first turn-on voltage, and The method according to claim 15 or 16, further comprising:

22. The method according to claim 15 or 16, wherein the second selection gate is turned on by the first turn-on voltage.

23. The memory string further comprises a P well, The method according to claim 15 or 16, further comprising the step of applying the first turn-on voltage to the second select line before the voltage on the P well drops from the erase voltage to a predetermined voltage.

24. The method according to claim 15 or 16, wherein the first turn-on voltage is higher than the first voltage.

25. The memory string further comprises a P well, The method described above is The step of applying the erase voltage to the P well, and grounding the word line. The method according to claim 15 or 16, further comprising:

26. Steps include applying the first turn-on voltage to the second selection line from the moment the voltage on the word line drops to a predetermined voltage. The method according to claim 25, further comprising:

27. The method according to claim 15 or 16, further comprising the step of applying a third voltage higher than the second voltage to the word line after the second voltage has been applied to the word line in the second step.

28. The method according to claim 15 or 16, wherein the application of the first voltage and the application of the first turn-on voltage overlap at least partially in time.

29. A memory system comprising a memory device, The memory device comprises a memory string and a control circuit, The memory string comprises a first selection gate, a memory cell, and a second selection gate, wherein the first selection gate is coupled to a first selection line, the memory cell is coupled to a word line, and the second selection gate is coupled to a second selection line. The control circuit is coupled to the first selection line, the word line, and the second selection line. The control circuit, In an erasure operation that includes an erasure step and a verification step following the erasure step, In the erasure step, an erasure voltage is applied to the memory string. In the first stage of the verification step, a first voltage is applied to the word line. In the verification step, in the second step following the first step, a second voltage lower than the first voltage is applied to the word line, and In the verification stage, the first turn-on voltage is applied to the second select line before the second voltage is applied to the word line. It is configured to do the following: A memory system in which the first turn-on voltage is applied to the second select line such that it is maintained from a predetermined time after the start of the erase step until at least the second voltage is applied to the word line.

30. A memory system comprising a memory device, The memory device comprises a memory string and a control circuit, The memory string comprises a first selection gate, a memory cell, and a second selection gate, wherein the first selection gate is coupled to a first selection line, the memory cell is coupled to a word line, and the second selection gate is coupled to a second selection line. The control circuit is coupled to the first selection line, the word line, and the second selection line. The control circuit, In an erasure operation that includes an erasure step and a verification step following the erasure step, In the erasure step, an erasure voltage is applied to the memory string. In the first stage of the verification step, a first voltage is applied to the word line. In the verification step, in the second step following the first step, a second voltage lower than the first voltage is applied to the word line, and In the verification stage, the first turn-on voltage is applied to the second select line before the second voltage is applied to the word line. It is configured to do the following: The control circuit, After stopping the application of the erase voltage for a predetermined period, a second turn-on voltage is applied to the first select line. Further configured to do A memory system in which the application of the second voltage, the application of the first turn-on voltage, and the application of the second turn-on voltage overlap at least partially in a time series.

Images