A precise programming method and apparatus for analog neural memory in artificial neural networks.

Abstract

To provide a method for programming and verifying multiple physical cells as a single logical multi-bit cell.SOLUTION: There is provided a method of programming a logical multi-bit cell 5400 in which physical cells 5401 are programmed, verified, and read as a single logical n-bit cell that can store more levels than each of m-bit cells. First, j of i physical cells 5401-1,..., 5401-i (where j≤i) are programmed and verified using a coarse programming method until a coarse current target for the j physical cells is achieved. Next, k out of the j physical cells (where k≤j), are programmed and verified using a precision programming method until a precision current target is achieved for k physical cells.SELECTED DRAWING: Figure 55

Description

[Technical Field]

[0001] (Claiming priority) This application claims priority to U.S. Patent Provisional Application No. 62 / 933,809, titled "PRECISE PROGRAMMING METHOD AND APPARATUS FOR ANALOG NEURAL MEMORY IN A DEEP LEARNING ARTIFICIAL NEURAL NETWORK," filed on 11 November 2019, and to U.S. Patent Application No. 16 / 751,202, titled "PRECISE PROGRAMMING METHOD AND APPARATUS FOR ANALOG NEURAL MEMORY IN A DEEP LEARNING ARTIFICIAL NEURAL NETWORK," filed on 23 January 2020.

[0002] (Field of Invention) Numerous embodiments of precision programming algorithms and apparatus for precisely and rapidly depositing a precise amount of charge onto the floating gates of nonvolatile memory cells in a vector matrix multiplication (VMM) array within an artificial neural network are disclosed. [Background technology]

[0003] Artificial neural networks mimic biological neural networks (such as the central nervous system of animals, particularly the brain) and are used to estimate or approximate functions that may depend on numerous inputs and are generally unknown. Artificial neural networks typically consist of layers of interconnected "neurons" that exchange messages.

[0004] Figure 1 shows an artificial neural network, where circles represent layers of inputs or neurons. Connections (called synapses) are represented by arrows and have numerical weights that can be adjusted based on experience. This allows the artificial neural network to adapt to inputs and learn. Typically, an artificial neural network contains multiple layers of inputs. Typically, there are hidden layers of one or more neurons and output layers of neurons that provide the output of the neural network. At each level, neurons make decisions individually or collectively based on the data they receive from synapses.

[0005] One of the major challenges in developing artificial neural networks for high-performance information processing is the lack of suitable hardware technology. In practice, practical artificial neural networks rely on a very large number of synapses, which enables high connectivity between neurons and thus very high levels of parallel processing. In principle, such complexity can be achieved by digital supercomputers or dedicated graphics processing unit clusters. However, in addition to their high cost, these approaches also suffer from poor energy efficiency compared to biological networks, which consume far less energy because they primarily perform low-precision analog calculations. CMOS analog circuits have been used in artificial neural networks, but most CMOS-implemented synapses are too bulky given the large number of neurons and synapses required.

[0006] The applicant previously disclosed an artificial (analog) neural network utilizing one or more non-volatile memory arrays as synapses in U.S. Patent Application No. 15 / 594,439, published as U.S. Patent Publication 2017 / 0337466, incorporated by reference. The non-volatile memory arrays operate as analog neuromorphic memory. As used herein, the term neuromorphic means a circuit that implements a model of a nervous system. The analog neuromorphic memory includes a first plurality of synapses configured to receive a first plurality of inputs and therefrom produce a first plurality of outputs, and a first plurality of neurons configured to receive the first plurality of outputs. The first plurality of synapses includes a plurality of memory cells, each memory cell including spaced source and drain regions formed in a semiconductor substrate with a channel region extending between them, a floating gate disposed above a first portion of the channel region and isolated from the first portion of the channel region, and a non-floating gate disposed above a second portion of the channel region and isolated from the second portion of the channel region. Each of the multiple memory cells is configured to store a weight value corresponding to a certain number of electrons on a floating gate. The multiple memory cells are configured to generate a first set of outputs by multiplying a first set of inputs by the stored weight values. An array of memory cells arranged in this manner may be called a vector-matrix multiplication (VMM) array.

[0007] Each non-volatile memory cell used in an analog neuromorphic memory array must hold a charge, i.e., the number of electrons, in a highly specific and precise quantity within its floating gate, corresponding to erasure and programming. For example, each floating gate must hold one of N different values, where N is the number of different weights that can be represented by each cell. Examples of N include 16, 32, 64, 128, and 256. One challenge in analog neuromorphic memory systems is the ability to program selected cells to the required precision and granularity for different values ​​of N.

[0008] What is needed is an improved programming system and method suitable for use with VMM arrays in analog neuromorphic memory. [Overview of the Initiative]

[0009] Numerous embodiments of precision programming algorithms and apparatus for precisely and rapidly depositing a precise amount of charge onto the floating gates of non-volatile memory cells in a vector matrix multiplication (VMM) array within an analog neuromorphic memory are disclosed. This allows selected cells to be programmed with extremely high precision to hold one of N distinct values.

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[0070] [Brief explanation of the drawing]

[0071] [Figure 1] This is a diagram showing an example of an artificial neural network using prior art technology. [Figure 2] This shows a prior art split-gate flash memory cell. [Figure 3] This shows another prior art split-gate flash memory cell. [Figure 4] This shows another prior art split-gate flash memory cell. [Figure 5]This shows another prior art split-gate flash memory cell. [Figure 6] This shows another prior art split-gate flash memory cell. [Figure 7] This shows a stacked gate flash memory cell of prior art. [Figure 8] This figure shows various levels of exemplary artificial neural networks that utilize one or more non-volatile memory arrays. [Figure 9] Block diagram of the vector-matrix multiplication system. [Figure 10] This block diagram shows an exemplary artificial neural network that utilizes one or more vector-matrix multiplication systems. [Figure 11] Another embodiment of the vector-matrix multiplication system is shown. [Figure 12] Another embodiment of the vector-matrix multiplication system is shown. [Figure 13] Another embodiment of the vector-matrix multiplication system is shown. [Figure 14] Another embodiment of the vector-matrix multiplication system is shown. [Figure 15] Another embodiment of the vector-matrix multiplication system is shown. [Figure 16] Another embodiment of the vector-matrix multiplication system is shown. [Figure 17] Another embodiment of the vector-matrix multiplication system is shown. [Figure 18] Another embodiment of the vector-matrix multiplication system is shown. [Figure 19] Another embodiment of the vector-matrix multiplication system is shown. [Figure 20] Another embodiment of the vector-matrix multiplication system is shown. [Figure 21] Another embodiment of the vector-matrix multiplication system is shown. [Figure 22] Another embodiment of the vector-matrix multiplication system is shown. [Figure 23] Another embodiment of the vector-matrix multiplication system is shown. [Figure 24]Another embodiment of the vector-matrix multiplication system is shown. [Figure 25] This demonstrates prior art long- and short-term memory systems. [Figure 26] This shows an example cell used in long- and short-term memory systems. [Figure 27] Figure 26 shows one embodiment of an exemplary cell. [Figure 28] Another embodiment of the exemplary cell shown in Figure 26 is presented. [Figure 29] This shows a prior art gated regression unit system. [Figure 30] An exemplary cell used in a gated regression unit system is shown. [Figure 31] Figure 30 shows one embodiment of an exemplary cell. [Figure 32] Another embodiment of the exemplary cell shown in Figure 30 is presented. [Figure 33A] One embodiment of a method for programming a non-volatile memory cell is shown. [Figure 33B] Another embodiment of a method for programming non-volatile memory cells is shown. [Figure 34] One embodiment of a rough programming method is shown. [Figure 35] This shows an example pulse used for programming non-volatile memory cells. [Figure 36A] This shows an example pulse used for programming non-volatile memory cells. [Figure 36B] This shows exemplary complementary incremental and subtractive pulses used in programming non-volatile memory cells. [Figure 37] This document presents a calibration algorithm for programming non-volatile memory cells, which adjusts programming parameters based on the cell's gradient characteristics. [Figure 38] The circuit used in the calibration algorithm shown in Figure 37 is illustrated. [Figure 39] This document presents a calibration algorithm for programming non-volatile memory cells. [Figure 40]This document presents a calibration algorithm for programming non-volatile memory cells. [Figure 41] The circuit used in the calibration algorithm shown in Figure 40 is illustrated. [Figure 42] This illustrates the voltage progression applied to the control gate of a non-volatile memory cell during programming. [Figure 43] This illustrates the voltage progression applied to the control gate of a non-volatile memory cell during programming. [Figure 44] This document describes a system for applying a programming voltage during the programming of a non-volatile memory cell within a vector multiplication matrix system. [Figure 45] This shows a vector multiplication matrix system having an output block including a modulator, an analog-to-digital converter, and an adder. [Figure 46] This shows a charge adder circuit. [Figure 47] This shows a current adder circuit. [Figure 48] This shows a digital adder circuit. [Figure 49A] This document describes one embodiment of an integrating analog-to-digital converter for neuron output. [Figure 49B] Figure 49A shows a graph illustrating the voltage output over time of the integrating analog-to-digital converter. [Figure 49C] Another embodiment of an integrating analog-to-digital converter for neuron output is shown. [Figure 49D] Figure 49C shows a graph illustrating the voltage output over time of the integrating analog-to-digital converter. [Figure 49E] Another embodiment of an integrating analog-to-digital converter for neuron output is shown. [Figure 49F] Another embodiment of an integrating analog-to-digital converter for neuron output is shown. [Figure 50A] This shows a successive approximation analog-to-digital converter for neuron output. [Figure 50B] This shows a successive approximation analog-to-digital converter for neuron output. [Figure 51] One embodiment of a sigma-delta type analog-to-digital converter is shown. [Figure 52A] This document illustrates one embodiment of a lamp-type analog-to-digital converter. [Figure 52B] This document illustrates one embodiment of a lamp-type analog-to-digital converter. [Figure 52C] This document illustrates one embodiment of a lamp-type analog-to-digital converter. [Figure 53] This document describes one embodiment of an algorithmic analog-to-digital converter. [Figure 54] This shows a logical multi-bit cell. [Figure 55] Figure 54 shows how to program the logical multi-bit cell. [Modes for carrying out the invention]

[0072] The artificial neural network of the present invention utilizes a combination of CMOS technology and a non-volatile memory array. [Non-volatile memory cell]

[0073] Digital non-volatile memory is well known. For example, U.S. Patent No. 5,029,130 ​​("'130"), incorporated herein by reference, discloses an array of split-gate non-volatile memory cells, a type of flash memory cell. Such a memory cell 210 is shown in Figure 2. Each memory cell 210 includes a source region 14 and a drain region 16 formed in a semiconductor substrate 12, with a channel region 18 between the source region 14 and the drain region 16. A floating gate 20 is formed insulated above a first portion of the channel region 18 (and controlling the conductivity of the first portion of the channel region 18) and extends above a portion of the source region 14. A word line terminal 22 (typically coupled to a word line) has a first portion disposed above a second portion of the channel region 18 and insulated from the second portion of the channel region 18 (and controlling the conductivity of the second portion of the channel region 18), and a second portion extending upward above the floating gate 20. The floating gate 20 and word line terminal 22 are insulated from the substrate 12 by the gate oxide. The bit line terminal 24 is coupled to the drain region 16.

[0074] By applying a high-voltage positive voltage to the word line terminal 22, the memory cell 210 is erased (electrons are removed from the floating gate), causing the electrons in the floating gate 20 to pass through the insulator between them to the word line terminal 22 via a Fowler-Nordheim tunnel.

[0075] The memory cell 210 is programmed by applying a positive voltage to the word line terminal 22 and a positive voltage to the source region 14 (electrons are applied to the floating gate). The electron current flows from the source region 14 (source line terminal) towards the drain region 16. The electrons are accelerated and heated when they reach the gap between the word line terminal 22 and the floating gate 20. Some of the heated electrons are injected into the floating gate 20 via the gate oxide due to the electrostatic attraction from the floating gate 20.

[0076] The memory cell 210 is read by applying a positive read voltage to the drain area 16 and the word line terminal 22 (turning on the portion of the channel area 18 below the word line terminal). When the floating gate 20 is positively charged (i.e., electrons are erased), the portion of the channel area 18 below the floating gate 20 is also turned on, and current flows through the channel area 18, which is detected as the erased state, or the "1" state. When the floating gate 20 is negatively charged (i.e., programmed with electrons), the portion of the channel area below the floating gate 20 is almost or completely off, and no (or very little) current flows through the channel area 18, which is detected as the programmed state, or the "0" state.

[0077] Table 1 shows typical voltage ranges that can be applied to the terminals of the memory cell 110 for performing read, erase, and program operations. Table 1: Operation of flash memory cell 210 in Figure 2 [Table 1] "Readout 1" is a readout mode in which the cell current is output to the bit line. "Readout 2" is a readout mode in which the cell current is output to the source line terminal.

[0078] Figure 3 shows a memory cell 310 similar to the memory cell 210 in Figure 2, with the addition of a control gate (CG) terminal 28. The control gate terminal 28 is biased with a high voltage (e.g., 10V) during programming, a low or negative voltage (e.g., 0V / -8V) during erasing, and a low or medium voltage (e.g., 0V / 2.5V) during reading. The other terminals are biased in the same way as the terminals in Figure 2.

[0079] Figure 4 shows a four-gate memory cell 410, comprising a source region 14, a drain region 16, a floating gate 20 above a first portion of the channel region 18, a selection gate 22 (typically coupled to a word line, WL) above a second portion of the channel region 18, a control gate 28 above the floating gate 20, and an erase gate 30 above the source region 14. This configuration is described in U.S. Patent No. 6,747,310, which is incorporated herein by reference for all purposes. Here, all gates are non-floating gates, except for the floating gate 20; that is, they are electrically connected to or can be connected to a voltage source. Programming is performed by heated electrons injecting themselves from the channel region 18 into the floating gate 20. Erasing is performed by electrons tunneling from the floating gate 20 to the erase gate 30.

[0080] Table 2 shows typical voltage ranges that can be applied to the terminals of the memory cell 410 for performing read, erase, and program operations. Table 2: Operation of flash memory cell 410 in Figure 4 [Table 2] "Readout 1" is a readout mode in which the cell current is output to the bit line. "Readout 2" is a readout mode in which the cell current is output to the source line terminal.

[0081] Figure 5 shows a memory cell 510 similar to the memory cell 410 in Figure 4, except that the memory cell 510 does not include an erase gate (EG) terminal. Erasure is performed by biasing the substrate 18 to a high voltage and the control gate CG terminal 28 to a low voltage or negative voltage. Alternatively, erasure is performed by biasing the word line terminal 22 to a positive voltage and the control gate terminal 28 to a negative voltage. Programming and reading are the same as in Figure 4.

[0082] Figure 6 shows a different type of flash memory cell, a 3-gate memory cell 610. Memory cell 610 is identical to memory cell 410 in Figure 4, except that memory cell 610 does not have a separate control gate terminal. The erase and read operations (erasure occurs through the use of the erase gate terminal) are the same as those in Figure 4, except that no control gate bias is applied. The programming operation is also performed without a control gate bias; therefore, during the programming operation, a higher voltage must be applied to the source line terminal to compensate for the lack of control gate bias.

[0083] Table 3 shows typical voltage ranges that can be applied to the terminals of the memory cell 610 for performing read, erase, and program operations. Table 3: Operation of the flash memory cell 610 in Figure 6 [Table 3] "Readout 1" is a readout mode in which the cell current is output to the bit line. "Readout 2" is a readout mode in which the cell current is output to the source line terminal.

[0084] Figure 7 shows a different type of flash memory cell, a stacked gate memory cell 710. The memory cell 710 is similar to the memory cell 210 in Figure 2, except that the floating gate 20 extends over the entire channel region 18, and the control gate terminal 22 (coupled to the word line) is separated by an insulating layer (not shown) and extends over the floating gate 20. Erase, programming, and read operations are performed in the same manner as described above for the memory cell 210.

[0085] Table 4 shows typical voltage ranges that can be applied to the terminals of the memory cell 710 and the circuit board 12 for performing read, erase, and program operations. Table 4: Operation of flash memory cell 710 in Figure 7 [Table 4]

[0086] "Read 1" is a read mode in which the cell current is output to the bit line. "Read 2" is a read mode in which the cell current is output to the source line terminal. Optionally, in an array containing rows and columns of memory cells 210, 310, 410, 510, 610, or 710, the source line may be coupled to one row of memory cells or two adjacent rows of memory cells. That is, the source line terminal may be shared by adjacent rows of memory cells.

[0087] Two modifications are made to utilize a memory array containing one of the non-volatile memory cell types in the artificial neural network described above. First, lines are configured to allow each memory cell to be programmed, erased, and read individually without adversely affecting the memory state of other memory cells in the array, as will be further described below. Second, sequential (analog) programming of the memory cells is provided.

[0088] Specifically, the memory state of each memory cell in the array (i.e., the charge on the floating gate) can be changed independently and continuously, with minimal disturbance to other memory cells, from a completely erased state to a completely programmed state. In another embodiment, the memory state of each memory cell in the array (i.e., the charge on the floating gate) can be changed independently and continuously, with minimal disturbance to other memory cells, from a completely programmed state to a completely erased state, and vice versa. This means that the cell memory is analog or can store at least one of a number of discontinuous values ​​(such as 16 or 64 different values), making every cell in the memory array highly precise and individually tunable, and the memory array ideal for memory, allowing for fine-tuning of the synaptic weights of a neural network.

[0089] The methods and means described herein can be applied without limitation to other non-volatile memory technologies such as SONOS (silicon oxide-nitride-oxide-silicon, charge trap in nitride), MONOS (metal oxide-nitride-oxide-silicon, metal charge trap in nitride), ReRAM (resistive random-access memory), PCM (phase-change memory), MRAM (magnetoresistive random-access memory), FeRAM (ferroelectric memory), OTP (bilevel or multilevel one-time programmable), and CeRAM (strongly correlated electron memory). The methods and means described herein can also be applied without limitation to volatile memory technologies used in neural networks such as SRAM, DRAM, and other volatile synaptic cells. [Neural networks using non-volatile memory cell arrays]

[0090] Figure 8 conceptually illustrates a non-limiting example of a neural network utilizing a non-volatile memory array in this embodiment. While this example uses a non-volatile memory array neural network for a facial recognition application, it is also possible to implement other suitable applications using a non-volatile memory array-based neural network.

[0091] S0 is the input layer, which in this example is a 32x32 pixel RGB image with 5-bit precision (i.e., three 32x32 pixel arrays, one for each color R, G, and B, with each pixel having 5-bit precision). Synapse CB1, going from input layer S0 to layer C1, scans the input image with a 3x3 pixel overlapping filter (kernel), applying different sets of weights to some instances and shared weights to others, and shifts the filter by one pixel (or more than two pixels depending on the model). Specifically, the values ​​of nine pixels in the 3x3 portion of the image (i.e., called the filter or kernel) are provided to synapse CB1, where these nine input values ​​are multiplied by the appropriate weights, and after summing the outputs of the multiplications, a single output value is determined and given by the first synapse of CB1 to generate one pixel of the layer in feature map C1. The 3x3 filter is then shifted one pixel to the right within the input layer S0 (i.e., a column of 3 pixels is added to the right and a column of 3 pixels is dropped to the left), thereby providing the 9 pixel values ​​of this newly positioned filter to synapse CB1, where they are multiplied by the same weights as above, determining a second single output value by the associated synapse. This process continues until the 3x3 filter has scanned the entire 32x32 pixel image of the input layer S0 for all three colors and all bits (precision values). The process is then repeated with different sets of weights to generate different feature maps of layer C1 until all feature maps of C1 have been computed.

[0092] In this example, layer C1 contains 16 feature maps, each with 30x30 pixels. Each pixel is a new feature pixel extracted from the multiplication of the input and the kernel; therefore, each feature map is a two-dimensional array, and thus in this example, layer C1 constitutes 16 layers of two-dimensional arrays (note that the layers and arrays referred to herein are logical relationships, not necessarily physical relationships; i.e., arrays are not necessarily oriented to physical two-dimensional arrays). Each of the 16 feature maps in layer C1 is generated by one of 16 different sets of synaptic weights applied to the filter scan. All C1 feature maps can target different aspects of the same image feature, such as boundary identification. For example, a first map (generated using a first set of weights shared across all scans used to generate this first map) can identify circular edges, and a second map (generated using a second set of weights different from the first) can identify rectangular edges or the aspect ratio of a particular feature, etc.

[0093] Before moving from layer C1 to layer S1, which pools values ​​from non-overlapping, consecutive 2x2 regions within each feature map, an activation function P1 (pooling) is applied. The purpose of the pooling function is to average neighboring positions (or use the max function), reduce dependence on edge positions, and reduce the data size before moving to the next stage. In layer S1, there are 16 15x15 feature maps (i.e., 16 different arrays of 15x15 pixels each). Synapse CB2, moving from layer S1 to layer C2, scans the maps in S1 with a 4x4 filter, resulting in a 1-pixel filter shift. In layer C2, there are 22 12x12 feature maps. Before moving from layer C2 to layer S2, which pools values ​​from non-overlapping, consecutive 2x2 regions within each feature map, an activation function P2 (pooling) is applied. In layer S2, there are 22 6x6 feature maps. At synapse CB3, which goes from layer S2 to layer C3, an activation function (pooling) is applied, where all neurons in layer C3 are connected to all maps in layer S2 via each synapse of CB3. There are 64 neurons in layer C3. Synapse CB4, which goes from layer C3 to output layer S3, completely connects C3 to S3; that is, all neurons in layer C3 are connected to all neurons in layer S3. The output in S3 contains 10 neurons, where the neuron with the highest output determines the class. This output can, for example, indicate the identification or classification (classification) of the content of the original image.

[0094] Each layer of a synapse operates using an array or part of an array of non-volatile memory cells.

[0095] Figure 9 is a block diagram of a system usable for that purpose. The vector matrix multiplication (VMM) system 32 includes non-volatile memory cells and synapses between one layer and the next (Figure 9). 8These are used as CB1, CB2, CB3, and CB4, etc. Specifically, the VMM system 32 includes a VMM array 33 containing non-volatile memory cells arranged in rows and columns, an erase gate and word line gate decoder 34, a control gate decoder 35, a bit line decoder 36, and a source line decoder 37, each of which decoders decodes its respective input to the non-volatile memory cell array 33. Inputs to the VMM array 33 can be made from the erase gate and word line gate decoder 34 or from the control gate decoder 35. In this example, the source line decoder 37 also decodes the output of the VMM array 33. Alternatively, the bit line decoder 36 can decode the output of the VMM array 33.

[0096] The VMM array 33 serves two purposes. First, it stores the weights used by the VMM system 32. Second, the VMM array 33 effectively multiplies the input by the weights stored in the VMM array 33 and sums them for each output line (source line or bit line) to produce an output, which becomes the input to the next layer or the last layer. By performing multiplication and addition functions, the VMM array 33 eliminates the need for separate multiplication and addition logic circuits and is also power-efficient due to on-the-spot memory calculations.

[0097] The output of the VMM array 33 is fed to a differential adder (such as an adding operational amplifier or an adding current mirror) 38, which sums the outputs of the VMM array 33 to create a single value for its convolution. The differential adder 38 is configured to perform the summation of both positive and negative weight inputs and output a single value.

[0098] The summed output values ​​of the differential adder 38 are then fed to an activation function circuit 39, which rectifies the output. The activation function circuit 39 may provide a sigmoid function, a tanh function, a ReLU function, or any other nonlinear function. The rectified output values ​​of the activation function circuit 39 become elements of the feature map of the next layer (e.g., C1 in Figure 8), which are then applied to the next synapse to generate the next feature map layer or the final layer. Thus, in this example, the VMM array 33 constitutes multiple synapses (they receive input from the previous layer of neurons or from an input layer such as an image database), and the adder 38 and activation function circuit 39 constitute multiple neurons.

[0099] The inputs to the VMM system 32 in Figure 9 (WLx, EGx, CGx, and optionally BLx and SLx) can be analog levels, binary levels, digital pulses (in which case a pulse-to-analog converter PAC may be required to convert the pulses to appropriate input analog levels), or digital bits (in which case a DAC is provided to convert the digital bits to appropriate input analog levels), and the outputs can be analog levels, binary levels, digital pulses, or digital bits (in which case an output ADC is provided to convert the output analog levels to digital bits).

[0100] Figure 10 is a block diagram showing the use of multiple layers of the VMM system 32, labeled in the figure as VMM systems 32a, 32b, 32c, 32d, and 32e. As shown in Figure 10, the input (indicated as Inputx) is converted from digital to analog by the digital-to-analog converter 31 and provided to the input VMM system 32a. The converted analog input can be voltage or current. The input D / A conversion of the first layer can be performed by using a function or LUT (lookup table) that maps the input Inputx to the appropriate analog level of the matrix multiplier of the input VMM system 32a. Input conversion can also be performed by an analog-to-analog (A / A) converter to convert an external analog input to a mapped analog input to the input VMM system 32a. Input conversion can also be performed by a digital-to-digital pulse (D / P) converter to convert an external digital input to a mapped digital pulse(s)(one or more) to the input VMM system 32a.

[0101] The output generated by input VMM system 32a is then provided as input to the next VMM system (hidden level 1) 32b, which then generates an output provided as input to input VMM system (hidden level 2) 32c, and so on. The various layers of VMM system 32 function as the synaptic and neuron layers of a convolutional neural network (CNN). VMM systems 32a, 32b, 32c, 32d, and 32e can each be a standalone physical system containing a corresponding non-volatile memory array, or multiple VMM systems can utilize different parts of the same physical non-volatile memory array, or multiple VMM systems can utilize overlapping parts of the same physical non-volatile memory array. Each VMM system 32a, 32b, 32c, 32d, and 32e can also be time-multiplexed with respect to different parts of its array or neurons. The example shown in Figure 10 includes five layers (32a, 32b, 32c, 32d, 32e), namely one input layer (32a), two hidden layers (32b, 32c), and two fully connected layers (32d, 32e). Those skilled in the art will understand that this is merely an example and that the system may instead include more than two hidden layers and more than two fully connected layers. [VMM Array]

[0102] Figure 11 shows a neuron VMM array 1100, particularly suitable for the memory cell 310 shown in Figure 3, which is used as part of a synapse and neuron between the input layer and the next layer. The VMM array 1100 includes a memory array 1101 of non-volatile memory cells and a reference array 1102 of non-volatile reference memory cells (located at the top of the array). Alternatively, another reference array may be located at the bottom.

[0103] In the VMM array 1100, control gate lines such as control gate line 1103 extend vertically (therefore, the reference array 1102 in the row direction is orthogonal to the control gate line 1103), and erase gate lines such as erase gate line 1104 extend horizontally. Here, the input to the VMM array 1100 is provided to the control gate lines (CG0, CG1, CG2, CG3), and the output of the VMM array 1100 appears on the source lines (SL0, SL1). In one embodiment, only even rows are used, and in another embodiment, only odd rows are used. The current applied to each source line (SL0 and SL1 respectively) performs a summation function of all the currents from the memory cells connected to that particular source line.

[0104] As described herein for the neural network, the non-volatile memory cells of the VMM array 1100, i.e., the flash memory of the VMM array 1100, are preferably configured to operate in the subthreshold region.

[0105] The non-volatile reference memory cells and non-volatile memory cells described herein are biased with weak inversion as follows: Ids = Io * e (Vg-Vth) / nVt = w * Io * e (Vg) / nVt Where w = e (-Vth) / nVt and where Ids is the drain-source current, Vg is the gate voltage of the memory cell, Vth is the threshold voltage of the memory cell, Vt is the thermal voltage = k * T / q, where k is the Boltzmann constant, T is the Kelvin temperature, q is the electron charge, n is the slope factor = 1+(Cdep / Cox), Cdep is the capacitance of the depletion layer, and Cox is the capacitance of the gate oxide layer, Io is the memory cell current at a gate voltage equal to the threshold voltage, and Io is (Wt / L) * u * Cox * (n - 1) * Vt 2It is proportional to , where u is the carrier mobility, and Wt and L are the width and length of the memory cell, respectively.

[0106] When using an IV logarithmic converter that converts the input current Ids to the input voltage Vg using a memory cell (such as a reference memory cell or peripheral memory cell) or a transistor: Vg=n * Vt * log[Ids / wp * Io] In the formula, wp is the w of the reference or peripheral memory cell.

[0107] When using an IV logarithmic converter that converts the input current Ids to the input voltage Vg using a memory cell (such as a reference memory cell or peripheral memory cell) or a transistor: Vg=n * Vt * log[Ids / wp * Io]

[0108] In the formula, wp is the w of the reference or peripheral memory cell.

[0109] For a memory array used as a vector matrix multiplier VMM array, the output current is as follows: Iout=wa * Io * e (Vg) / nVt That is to say Iout=(wa / wp) * Iin=W * Iin W=e (Vthp-Vtha) / nVt Iin=wp * Io * e (Vg) / nVt In the formula, wa = w for each memory cell in the memory array.

[0110] Word lines or control gates can be used as inputs to memory cells for input voltage.

[0111] Alternatively, the non-volatile memory cells of the VMM array described herein can be configured to operate in a linear region. Ids=β * (Vgs-Vth) * Vds; β=u * Cox * Wt / L W α (Vgs-Vth) In other words, the weight W in the linear region is proportional to (Vgs - Vth).

[0112] Word lines, control gates, bit lines, or source lines can be used as inputs to memory cells operating within the linear region. Bit lines or source lines can be used as outputs to memory cells.

[0113] For IV linear converters, a memory cell (such as a reference memory cell or peripheral memory cell), a transistor, or a resistor operating in the linear domain can be used to linearly convert input / output current to input / output voltage.

[0114] Alternatively, the memory cells of the VMM array described herein can be configured to operate in the saturation region. Ids = 1 / 2 * β * (Vgs-Vth) 2 β=u * Cox * Wt / L W α (Vgs-Vth) 2 That is, the weight W is (Vgs - Vth) 2 It is proportional to.

[0115] Word lines, control gates, or erase gates can be used as inputs to memory cells operating within a saturation region. Bit lines or source lines can be used as outputs to output neurons.

[0116] Alternatively, the memory cells of the VMM array described herein can be used in all regions or combinations thereof (subthreshold, linear, or saturated).

[0117] Other embodiments for the VMM array 33 shown in Figure 9 are described in U.S. Patent Application No. 15 / 826,345, which is incorporated herein by reference. As described in the above application, source lines or bit lines can be used as neuron outputs (current sum outputs).

[0118] Figure 12 shows a neuron VMM array 1200 particularly suited to the memory cell 210 shown in Figure 2, which is used as a synapse between the input layer and the next layer. The VMM array 1200 includes a memory array 1203 of non-volatile memory cells, a reference array 1201 of first non-volatile reference memory cells, and a reference array 1202 of second non-volatile reference memory cells. The reference arrays 1201 and 1202, arranged in the column direction of the array, function to convert current inputs flowing into terminals BLR0, BLR1, BLR2, and BLR3 into voltage inputs WL0, WL1, WL2, and WL3. In practice, the first and second non-volatile reference memory cells are diode-connected through a multiplexer 1214 (partially shown) with current inputs flowing in. The reference cells are tuned (e.g., programmed) to a target reference level. The target reference level is provided by a reference miniarray matrix (not shown).

[0119] The memory array 1203 serves two purposes. First, it stores the weights used by the VMM array 1200 in each memory cell. Second, the memory array 1203 effectively multiplies the inputs (i.e., the current inputs provided to terminals BLR0, BLR1, BLR2, and BLR3, which are converted into input voltages by the reference arrays 1201 and 1202 and supplied to word lines WL0, WL1, WL2, and WL3) by the weights stored in the memory cell array 1203, then adds all the results (memory cell currents) to generate the outputs of each bit line (BL0~BLN), which become inputs to the next layer or the last layer. By having the memory array 1203 perform the multiplication and addition functions, the need for separate multiplication and addition logic circuits is eliminated, and power efficiency is also improved. Here, the voltage inputs are provided to word lines WL0, WL1, WL2, and WL3, and the outputs appear on bit lines BL0~BLN respectively during read (inference) operations. The current distributed across each bit line BL0 to BLN acts as a function of the sum of the currents from all non-volatile memory cells connected to that particular bit line.

[0120] Table 5 shows the operating voltages of the VMM array 1200. The columns in the table show the voltages applied to the word lines of selected cells, word lines of unselected cells, bit lines of selected cells, bit lines of unselected cells, source lines of selected cells, and source lines of unselected cells, with FLT indicating floating, i.e., no voltage applied. The rows show the read, erase, and program operations. Table 5: Operation of VMM Array 1200 in Figure 12 [Table 5]

[0121] Figure 13 shows a neuron VMM array 1300, particularly suitable for the memory cell 210 shown in Figure 2, and used as part of synapses and neurons between the input layer and the next layer. The VMM array 1300 includes a memory array 1303 of non-volatile memory cells, a reference array 1301 of first non-volatile reference memory cells, and a reference array 1302 of second non-volatile reference memory cells. The reference arrays 1301 and 1302 extend in the row direction of the VMM array 1300. The VMM array is similar to the VMM 1000, except that the word lines in the VMM array 1300 extend vertically. Here, inputs are provided to the word lines (WLA0, WLB0, WLA1, WLB2, WLA2, WLB2, WLA3, WLB3), and outputs appear on the source lines (SL0, SL1) during read operations. The current applied to each source line performs a function of the sum of all currents from the memory cells connected to that particular source line.

[0122] Table 6 shows the operating voltages of the VMM array 1300. The columns in the table show the voltages applied to the word lines of selected cells, word lines of unselected cells, bit lines of selected cells, bit lines of unselected cells, source lines of selected cells, and source lines of unselected cells. The rows show the read, erase, and program operations. Table 6: Operation of VMM Array 1300 in Figure 13 [Table 6]

[0123] Figure 14 shows a neuron VMM array 1400, particularly suitable for the memory cell 310 shown in Figure 3, which is used as part of a synapse and neuron between the input layer and the next layer. The VMM array 1400 includes a memory array 1403 of non-volatile memory cells, a reference array 1401 of a first non-volatile reference memory cell, and a reference array 1402 of a second non-volatile reference memory cell. The reference arrays 1401 and 1402 function to convert the current inputs flowing into terminals BLR0, BLR1, BLR2, and BLR3 into voltage inputs CG0, CG1, CG2, and CG3. In practice, the first and second non-volatile reference memory cells are diode-connected through a multiplexer 1412 (partially shown) with current inputs flowing through BLR0, BLR1, BLR2, and BLR3. The multiplexer 1412 includes a separate multiplexer 1405 and a cascoding transistor 1404 to ensure a constant voltage across the respective bit lines (such as BLR0) of the first and second non-volatile reference memory cells during read operations. The reference cells are adjusted to a target reference level.

[0124] Memory array 1403 serves two purposes. First, it stores the weights used by VMM array 1400. Second, memory array 1403 is the input (current input provided to terminals BLR0, BLR1, BLR2, and BLR3), and reference arrays 1401 and 1402 convert these current inputs into input voltages for control gates (CG0, CG1, CG2, and CG3). ) The current supplied to the memory array is multiplied by the weights stored in the memory cell array, and then all the results (cell currents) are added together to generate an output, which appears in BL0~BLN and becomes the input to the next layer or the last layer. By having the memory array perform the multiplication and addition functions, the need for separate multiplication and addition logic circuits is eliminated, and power efficiency is also improved. Here, the inputs are provided to the control gate lines (CG0, CG1, CG2, and CG3), and the outputs appear in the bit lines (BL0~BLN) during read operations. The current applied to each bit line performs a function of the sum of all the currents from the memory cells connected to that particular bit line.

[0125] The VMM array 1400 performs unidirectional adjustment of non-volatile memory cells within the memory array 1403. That is, each non-volatile memory cell is erased and then partially programmed until a desired charge is reached on the floating gate. This can be done, for example, using the precision programming technique described below. If too much charge is applied to the floating gate (e.g., an incorrect value is stored in the cell), the cell must be erased and the series of partial programming operations must be repeated. As shown, two rows sharing the same erase gate (e.g., EG0 or EG1) must be erased together (known as page erase), and then each cell is partially programmed until a desired charge is reached on the floating gate.

[0126] Table 7 shows the operating voltages of the VMM array 1400. The columns in the table show the voltages applied to the word lines of selected cells, word lines of unselected cells, bit lines of selected cells, bit lines of unselected cells, control gates of selected cells, control gates of unselected cells in the same sector as the selected cell, control gates of unselected cells in a different sector than the selected cell, erase gates of selected cells, erase gates of unselected cells, source lines of selected cells, and source lines of unselected cells. The rows show the read, erase, and program operations. Table 7: Operation of VMM Array 1400 in Figure 14 [Table 7]

[0127] Figure 15 shows a neuron VMM array 1500, which is particularly suitable for the memory cell 310 shown in Figure 3 and is used as part of the synapse and neuron between the input layer and the next layer. The VMM array 1500 is a memory array 1503 of nonvolatile memory cells, First non-volatile reference memory cell Reference array 150 1 and, and a reference array 1502 of a second non-volatile reference memory cell. The EG lines EGR0, EG1, and EGR1 extend vertically, and the CG lines CG0, CG1, CG2, and CG3, as well as the SL lines WL0, WL1, WL2, and WL3 extend horizontally. VMM array 1500 is similar to VMM array 1400 except that VMM array 1500 implements bidirectional adjustment, and each individual cell can be completely erased, partially programmed, and partially erased as needed to reach a desired amount of charge on the floating gate by using separate EG lines. As shown, reference arrays 1501 and 1502 convert the input currents in terminals BLR0, BLR1, BLR2, and BLR3 into control gate voltages CG0, CG1, CG2, and CG3 (through the action of diode-connected reference cells via multiplexer 1514), and these voltages are applied to the memory cells in the row direction. Current outputs (neurons) are located in the bit lines BL0 to BLN, and each bit line sums up all the currents from the non-volatile memory cells connected to that particular bit line.

[0128] Table 8 shows the operating voltages of the VMM array 1500. The columns in the table show the voltages applied to the word lines of selected cells, word lines of unselected cells, bit lines of selected cells, bit lines of unselected cells, control gates of selected cells, control gates of unselected cells in the same sector as the selected cell, control gates of unselected cells in a different sector than the selected cell, erase gates of selected cells, erase gates of unselected cells, source lines of selected cells, and source lines of unselected cells. The rows show the read, erase, and program operations. Table 8: Operation of VMM Array 1500 in Figure 15 [Table 8]

[0129] Figure 16 shows a neuron VMM array 1600, which is particularly suitable for the memory cell 210 shown in Figure 2 and is used as part of the synapse and neuron between the input layer and the next layer. In the VMM array 1600, inputs INPUT0, ..., INPUT NThese are bit lines BL0, ..., BL N The signals are received at each of these points, and outputs OUTPUT1, OUTPUT2, OUTPUT3, and OUTPUT4 are generated on source lines SL0, SL1, SL2, and SL3, respectively.

[0130] Figure 17 shows a neuron VMM array 1700, particularly suitable for the memory cell 210 shown in Figure 2, which is used as part of synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, INPUT1, INPUT2, and INPUT3 are received on source lines SL0, SL1, SL2, and SL3 respectively, and outputs OUTPUT0, ..., OUTPUT N These are bit lines BL0, ..., BL N It is generated in [location].

[0131] Figure 18 shows a neuron VMM array 1800, particularly suitable for the memory cell 210 shown in Figure 2, which is used as part of synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, ..., INPUT M These are word lines WL0, ..., WL M Each is received and output OUTPUT0, ..., OUTPUT N These are bit lines BL0, ..., BL N It is generated in [location].

[0132] Figure 19 shows a neuron VMM array 1900, particularly suitable for the memory cell 310 shown in Figure 3, which is used as part of synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, ..., INPUT M These are word lines WL0, ..., WL M Each is received and output OUTPUT0, ..., OUTPUT N These are bit lines BL0, ..., BL N It is generated in [location].

[0133] Figure 20 shows a neuron VMM array 2000 that is particularly suitable for the memory cell 410 shown in Figure 4 and is used as part of the synapse and neuron between the input layer and the next layer. In this example, the input is INPUT 0、 ..., INPUT n These are the vertical control gate lines CG0, ..., CG N The signal is received, and outputs OUTPUT1 and OUTPUT2 are generated on source lines SL0 and SL1.

[0134] Figure 21 shows a neuron VMM array 2100 that is particularly suitable for the memory cell 410 shown in Figure 4 and is used as part of synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, ..., INPUT N These are bit lines BL0, ..., BL N The signals are received by the bit line control gates 2901-1, 2901-2, ..., 2901-(N-1), and 2901-N, which are coupled to each other. Exemplary outputs OUTPUT1 and OUTPUT2 are generated on source lines SL0 and SL1.

[0135] Figure 22 shows a neuron VMM array 2200 that is particularly suitable for the memory cell 310 shown in Figure 3, the memory cell 510 shown in Figure 5, and the memory cell 710 shown in Figure 7, and is used as part of synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, ..., INPUT M These are word lines WL0, ..., WL M Received at, output OUTPUT0, ..., OUTPUT N These are bit lines BL0, ..., BL N They are generated in each respective location.

[0136] Figure 23 shows a neuron VMM array 2300 that is particularly suitable for the memory cell 310 shown in Figure 3, the memory cell 510 shown in Figure 5, and the memory cell 710 shown in Figure 7, and is used as part of synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, ..., INPUT MThese are control gate lines CG0, ..., CG M Received at: Output OUTPUT0, ..., OUTPUT N These are the vertical source lines SL0, ..., SL N Each is generated, and each source line SL i It is coupled to the source lines of all memory cells in column i.

[0137] Figure 24 shows a neuron VMM array 2400 that is particularly suitable for the memory cell 310 shown in Figure 3, the memory cell 510 shown in Figure 5, and the memory cell 710 shown in Figure 7, and is used as part of synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, ..., INPUT M These are control gate lines CG0, ..., CG M Received at: Output OUTPUT0, ..., OUTPUT N These are vertical bit lines BL0, ..., BL N Each bit line BL is generated in its respective place. i It is coupled to the bit lines of all memory cells in column i. [Long-term and short-term memory]

[0138] Prior art includes the concept known as long short-term memory (LSTM). LSTM is often used in artificial neural networks. LSTM allows artificial neural networks to remember information over a predetermined arbitrary period and use that information in subsequent operations. A conventional LSTM includes a cell, an input gate, an output gate, and a forget gate. The three gates regulate the flow of information into and out of the cell, and the duration for which information is remembered within the LSTM. VMM is particularly useful in LSTMs.

[0139] Figure 25 shows an exemplary LSTM2500. In this example, the LSTM2500 includes cells 2501, 2502, 2503, and 2504. Cell 2501 receives the input vector x0 and generates the output vector h0 and the cell state vector c0. Cell 2502 receives the input vector x1, the output vector (hidden state) h0 from cell 2501, and the cell state c0 from cell 2501, and generates the output vector h1 and the cell state vector c1. Cell 2503 receives the input vector x2, the output vector (hidden state) h1 from cell 2502, and the cell state c1 from cell 2502, and generates the output vector h2 and the cell state vector c2. Cell 2504 receives the input vector x3, the output vector (hidden state) h2 from cell 2503, and the cell state c2 from cell 2503, and generates the output vector h3. Additional cells can also be used, and an LSTM with four cells is just one example.

[0140] Figure 26 shows an exemplary implementation of an LSTM cell 2600 that can be used for cells 2501, 2502, 2503, and 2504 in Figure 25. The LSTM cell 2600 receives an input vector x(t), a cell state vector c(t-1) from a preceding cell, and an output vector h(t-1) from a preceding cell, and generates a cell state vector c(t) and an output vector h(t).

[0141] LSTM cell 2600 includes sigmoid function devices 2601, 2602, and 2603, each controlling the degree to which each component of the input vector contributes to the output vector by applying a number between 0 and 1. LSTM cell 2600 also includes tanh devices 2604 and 2605 for applying a hyperbolic tangent function to the input vector, multiplier devices 2606, 2607, and 2608 for multiplying two vectors, and an adder device 2609 for adding two vectors. The output vector h(t) can be provided to the next LSTM cell in the system or accessed for other purposes.

[0142] Figure 27 shows an LSTM cell 2700, which is an example of an implementation of the LSTM cell 2600. For the reader's convenience, the same numbering method used in the LSTM cell 2600 is used in the LSTM cell 2700. The sigmoid function devices 2601, 2602, and 2603, and the tanh device 2604, each contain multiple VMM arrays 2701 and activation circuit blocks 2702. Thus, it can be seen that VMM arrays are particularly useful in LSTM cells used in certain neural network systems.

[0143] Figure 28 shows an alternative example of the LSTM cell 2700 (and another example of one implementation of the LSTM cell 2600). In Figure 28, the sigmoid function devices 2601, 2602, and 2603, and the tanh device 2604 may share the same physical hardware (VMM array 2801 and activation function block 2802) in a time-division multiplexed manner. The LSTM cell 2800 also includes a multiplier device 2803 for multiplying two vectors, an adder device 2808 for adding two vectors, a tanh device 2605 (including the activation circuit block 2802), a register 2807 for storing the value i(t) output from the sigmoid function block 2802, and a multiplexer 2810 for storing the value f(t) output from the multiplier device 2803. * Register 2804 stores c(t-1), and the value i(t) is output from the multiplier device 2803 via the multiplexer 2810. * A register 2805 stores u(t), and the value o(t) is output from the multiplier device 2803 via the multiplexer 2810. * It includes register 2806 for storing c~(t) and multiplexer 2809.

[0144] While an LSTM cell 2700 includes multiple sets of VMM arrays 2701 and their respective activation function blocks 2702, an LSTM cell 2800 includes only one set of VMM arrays 2801 and activation function blocks 2802, which in embodiments of the LSTM cell 2800 are used to represent multiple layers. Compared to the LSTM cell 2700, the LSTM cell 2800 requires only one-quarter the space for the VMMs and activation function blocks, thus requiring less space than the LSTM cell 2700.

[0145] It is further understood that an LSTM unit typically includes multiple VMM arrays, each of which requires functionality provided by specific circuit blocks outside the VMM array, such as adder and activation circuit blocks and high-voltage generation blocks. Providing separate circuit blocks for each VMM array would require a considerable amount of space within the semiconductor device and would be somewhat inefficient. Therefore, the embodiments described below attempt to minimize the circuitry required outside the VMM array itself. [Gated recurrent unit]

[0146] An analog VMM implementation can be used for gated recurrent units (GRUs). A GRU is a gate mechanism within an iterative artificial neural network. GRUs are similar to LSTMs, except that GRU cells generally contain fewer components than LSTM cells.

[0147] Figure 29 shows an exemplary GRU2900. The GRU2900 in this example includes cells 2901, 2902, 2903, and 2904. Cell 2901 receives an input vector x0 and generates an output vector h0. Cell 2902 receives an input vector x1 and the output vector h0 from cell 2901, and generates an output vector h1. Cell 2903 receives an input vector x2 and the output vector (hidden state) h1 from cell 2902, and generates an output vector h2. Cell 2904 receives an input vector x3 and the output vector (hidden state) h2 from cell 2903, and generates an output vector h3. Additional cells can also be used, and the GRU with four cells is merely an example.

[0148] Figure 30 shows an exemplary implementation of a GRU cell 3000 that can be used for cells 2901, 2902, 2903, and 2904 in Figure 29. The GRU cell 3000 receives an input vector x(t) and an output vector h(t - 1) from a preceding GRU cell, and generates an output vector h(t). The GRU cell 3000 includes sigmoid function devices 3001 and 3002, each of which applies a number between 0 and 1 to components from the output vector h(t - 1) and the input vector x(t). The GRU cell 3000 also includes a tanh device 3003 for applying the hyperbolic tangent function to the input vector, a plurality of multiplier devices 3004, 3005, and 3006 for multiplying two vectors, an adder device 3007 for adding two vectors, and a complementary device 3008 for subtracting the input from 1 to generate an output.

[0149] Figure 31 shows a GRU cell 3100, which is an example of an implementation of the GRU cell 3000. For the convenience of the reader, the same numbering method from the GRU cell 3000 is used for the GRU cell 3100. As can be seen from Figure 31, the sigmoid function devices 3001 and 3002, and the tanh device 3003 each include a plurality of VMM arrays 3101 and activation function blocks 3102. Therefore, it can be understood that the VMM array is particularly used in GRU cells used in a specific neural network system.

[0150] An alternative example of GRU cell 3100 (and another example of an implementation of GRU cell 3000) is shown in FIG. 32. In FIG. 32, GRU cell 3200 uses VMM array 3201 and activation function block 3202. When configured as a sigmoid function, by applying a number between 0 and 1, it controls the degree to which each component of the input vector contributes to the output vector. In FIG. 32, sigmoid function devices 3001 and 3002, and tanh device 3003 share the same physical hardware (VMM array 3201 and activation function block 3202) in a time-division multiplexed manner. GRU cell 3200 also includes a multiplier device 3203 for multiplying two vectors, an adder device 3205 for adding two vectors, a complementary device 3209 for subtracting the input from 1 to generate an output, a multiplexer 3204, and the value h(t-1) output from multiplier device 3203 via multiplexer 3204 * A register 3206 for holding r(t), and the value h(t-1) output from multiplier device 3203 via multiplexer 3204 * A register 3207 for holding z(t), and the value h^(t) output from multiplier device 3203 via multiplexer 3204 * (1 - z((t)) and a register 3208 for holding it.

[0151] While GRU cell 3100 includes multiple sets of VMM array 3101 and activation function block 3102, GRU cell 3200 includes only one set of VMM array 3201 and activation function block 3202, which is used to represent multiple layers in an embodiment of GRU cell 3200. GRU cell 3200 requires less space than GRU cell 3100 because it requires only 1 / 3 of the space for the VMM and activation function blocks.

[0152] It is further understood that systems utilizing GRUs typically include multiple VMM arrays, each of which requires functionality provided by specific circuit blocks outside the VMM array, such as adder and activation circuit blocks and high-voltage generation blocks. Providing separate circuit blocks for each VMM array would require a considerable amount of space within the semiconductor device and would be somewhat inefficient. Therefore, the embodiments described below attempt to minimize the circuitry required outside the VMM array itself.

[0153] The input to the VMM array can be analog level, binary level, timing pulse, or digital bit, and the output can be analog level, binary level, timing pulse, or digital bit (in this case, an output ADC is required to convert the output analog level current or voltage to digital bits).

[0154] For each memory cell in the VMM array, each weight w can be implemented by a single memory cell, a differential cell, or two blended memory cells (the average of two or more cells). In the case of a differential cell, the weight w is the differential weight (w=w + -w - To implement it as such, two memory cells are required. In the case of two blended memory cells, two memory cells are required to implement the weight w as the average of the two cells. [An embodiment for precise programming of cells within VMM]

[0155] Here, we describe an embodiment for precisely programming memory cells in a VMM by increasing or decreasing the programming voltage applied to different terminals of the memory cell.

[0156] Figure 33A shows the programming method 3300. First, the method starts in response to a program (adjustment) command that is typically received (step 3301). Next, a simultaneous program operation programs all cells to the "0" state (step 3302). Then, a soft erase operation erases all cells to an intermediate weak erase level so that each cell draws a current of, for example, about 3-5 μA during a read operation (step 3303). This is in contrast to the deep erase maximum level, where each cell draws a current of about 20-30 μA during a read operation. Soft erasure is performed, for example, by applying an incremental erase voltage pulse until the intermediate cell current is reached. The incremental erase voltage pulse is applied to limit the degradation of the memory cell experienced from hard erase (i.e., maximum erase level). Next, a hard program is executed in all unselected cells (step 3304) to add electrons to the floating gates of the cells to a very deep programmed state, ensuring that those cells are truly "off," i.e., those cells, such as unused memory cells, draw only a negligible amount of current during read operations. The hard program is executed, for example, with a higher incremental program voltage pulse and / or a longer program time.

[0157] Next, a coarse programming method (bringing the cell quite close to the target, for example, 2 to 100 times the target) is performed on the selected cells (step 3305), followed by a precise programming method (step 3306) which programs the desired precise value into each selected cell.

[0158] Figure 33B shows another programming method 3310 similar to programming method 3300. However, after the method starts (step 3301), instead of a programming operation that programs all cells to the "0" state as in step 3302 of Figure 33A, a soft erase operation is used to erase all cells and set them to the "1" state (step 3312). Then, a soft programming operation (step 3313) is used to program all cells to an intermediate level so that each cell draws a current of approximately 3-5uA during a read operation. After that, the coarse programming method 3305 and the fine programming method 3306 are performed as in Figure 33A. A variation of the embodiment in Figure 33B completely eliminates the soft programming operation (step 3313). Programming can be accelerated by using multiple coarse programming methods, such as by targeting multiple gradually smaller coarse targets before performing the fine programming step 3306. The fine programming method 3306 is performed, for example, with a fine (precise) incremental programming voltage pulse or a constant programming timing pulse.

[0159] Different terminals of the memory cell can be used for the coarse programming method 3305 and the precision programming method 3306. That is, during the coarse programming method 3305, the voltage applied to one of the terminals of the memory cell (which may be called the coarse programming terminal) is changed until a desired voltage level is achieved within the floating gate 20, and during the precision programming method 3306, the voltage applied to one of the terminals of the memory cell (which may be called the precision programming terminal) is changed until a desired level is achieved. Various combinations of terminals that can be used as coarse programming terminals and precision programming terminals are shown in Table 9. Table 9: Memory cell terminals used in coarse and precision programming methods [Table 9] Other combinations of terminals are possible for the coarse programming and precise programming steps.

[0160] Figure 34 shows a first embodiment of the coarse programming method 3305, which is a search and execution method 3400. First, a lookup table search or function (IV curve) is performed to obtain the coarse target current value (I) of the selected cell. CT ) is determined based on the value intended to be stored in the selected cell (step 3401). This table is created, for example, by silicon characterization or from wafer test calibration. The selected cell can be programmed to store one of N possible values ​​(e.g., 128, 64, 32, etc.). Each of the N values ​​is a different desired current value (I) that is drawn in by the selected cell during the read operation. D ) corresponds to. In one embodiment, the lookup table corresponds to the crude target current value I for the cell selected during the search and execution method 3400. CT It may contain M possible current values ​​to be used as a coarse target, where M is an integer less than N. For example, if N is 8, then M could be 4, which means there are 8 possible values ​​that the selected cell can store, and one of the 4 coarse target current values ​​will be selected as the coarse target for the search and execution method 3400. That is, the search and execution method 3400 (again, an embodiment of the coarse programming method 3305) will find the selected cell to the desired value (I D A value somewhat close to (I CT The intention is to quickly program to the desired value (I D ) achieve or the desired value (I D The intention is to program the selected cells more precisely so that they come as close as possible to the desired result.

[0161] Examples of cell values, desired current values, and crude target current values ​​are shown in Tables 10 and 11 for a simple example with N=8 and M=4. Table 10: Examples of N desired current values ​​when N=8 [Table 10] Table 11: Example of M target current values for M = 4

Table 11

[0162] Coarse target current value I CT Once selected, in step 3402, the selected cell is programmed by applying an initial voltage v0 to the coarse programming terminal of the selected cell according to one of the sequences listed in Table 9 above. (The value of the initial voltage v0 and the appropriate coarse programming terminal can optionally be determined from a voltage look-up table that stores v0 corresponding to the coarse target current value I CT .) Table 12 Initial voltage v0 applied to the coarse programming terminal

Table 12

[0163] Next, in step 3403, the selected cell is programmed by applying a voltage v[[ID=三十二]] i = v i-1 + v increment to the coarse programming terminal, where i starts from 1 and increments each time this step is repeated, and v increment is an increment of the coarse voltage that causes programming commensurate with the desired granularity of change. Thus, the first time step 3403 is executed with i = 1, v1 is v0 + v increment . Then, a read operation is performed on the selected cell, and a verification operation is performed (step 3404) where the current (I cell ) drawn through the selected cell is measured. I cell is I CTIf it is below (which is the first threshold value here), the search and execution method 3400 is completed, and it becomes possible to start the fine programming method 3306. I cell If I CT is not below, step 3403 is repeated and i is incremented.

[0164] Therefore, when the rough programming method 3305 ends and the fine programming method 3306 starts, the voltage v i is the last voltage applied to the rough programming terminal to program the selected cell, and the selected cell has a rough target current value I CT associated value, especially I CT the value below. The goal of the fine programming method 3306 is to program the selected cell to draw in the current I D (with an acceptable margin deviation such as + / - 30% added or subtracted) during the read operation, and this current is the desired current value associated with the value intended to be stored in the selected cell.

[0165] Figure 35 shows examples of different voltage progressions that can be applied to the rough programming terminal of the selected memory cell according to Table 9 during the rough programming method 3305 and / or to the fine programming terminal of the selected memory cell during the fine programming method 3306.

[0166] Under the first approach, an increasing voltage is gradually applied to the rough programming terminal and / or the fine programming terminal to further program the selected memory cell. The starting point is v i which is the last voltage applied during the rough programming method 3305. An increment v p1 is added to v i , and then the voltage v i + v p1 is used to program the selected cell (shown by the second pulse from the left in progression 3501). v p1 is v increment(The increment is smaller than the voltage increment used during the coarse programming method 3305). After each programming voltage is applied to the programming terminal, Icell is I PT1 A verification step (similar to step 3404) is performed to determine whether it is less than or equal to (the first precise target current value, which in this case is the second threshold value), and I PT1 =I D +I PT1OFFSET And I PT1OFFSET This is an offset value added to prevent program overshoot. If the condition is negative, another increment v p1 However, this is added to the previously applied programming voltage, and the process is repeated. This is I cell I PT1 The following is repeated until a certain point in time, at which point this part of the programming sequence stops. Optionally, I PT1 I D Equal to, or with a sufficiently acceptable precision, I D If it is approximately equal to this value, the selected memory cell is successfully programmed.

[0167] I PT1 I D If it is not close enough, further programming with a finer granularity can be performed. Here, progress 3502 is used. The starting point of progress 3502 is the last voltage used in the programming under progress 3501. Increment V p2 (v p1 A voltage smaller than is applied to that voltage, and the combined voltage is applied to the precision programming terminal to program the selected memory cell. After each programming voltage is applied, cell I PT2 A verification step (similar to step 3404) is performed to determine whether it is less than or equal to (the second precise target current value, which in this case is the third threshold value), and I PT2 =ID+I PT2OFFSET And I PT2OFFSETThis is an offset value added to prevent program overshoot. If the condition is negative, another increment V p2 However, this is added to the previously applied programming voltage, and the process is repeated. This is I cell I PT2 The following is repeated until a certain point in time, at which point this part of the programming sequence stops. Here, since the target value has been achieved with a sufficiently acceptable precision, I PT2 is I D I equals or is so high that it can cause the programming to stop. D It is assumed that they are sufficiently close. Those skilled in the art will understand that the programming increments used may become progressively smaller and additional increments may be applied. For example, in Figure 36A, not just two increments, but three (3601, 3602, and 3603) are applied.

[0168] A second approach is shown in progress 3503. Here, instead of increasing the voltage applied during programming of the selected memory cell, the same voltage (V) is used. i , or V i +V p1 +V p1 , or V i +V p2 +V p2 (etc.) are applied to the duration as the period increases. p1 and v in progress 3502 p2 Instead of applying incremental voltages such as, each applied pulse is t p1 To make it longer, an additional time increment t p1 This is applied to the programming pulse. After each programming pulse is applied to the precision programming terminal, the same verification steps described above are performed for progression 3501. Optionally, an additional progression may be applied in which the additional time increment applied to the programming pulse has a shorter duration than the previously used progression.

[0169] Optionally, an additional program cycle progression can be applied, where the programming pulse has the same duration as the progression of the previous program cycle used. Although only one temporal progression is shown, those skilled in the art will understand that any number of different temporal progressions can be applied. That is, instead of changing the magnitude of the voltage used during programming, or instead of changing the period of the voltage pulse used during programming, the system can instead change the number of programming cycles used.

[0170] Figure 36B illustrates the progression of complementary pulse programming, where the voltage applied to one precision programming terminal increases and the voltage applied to another precision programming terminal decreases. For example, an increasing voltage progression may be applied to the control gate of a selected cell, and a decreasing voltage progression may be applied to the erase gate or source line of a selected cell. Alternatively, an increasing voltage progression may be applied to the erase gate or source line of a selected cell, and a decreasing voltage progression may be applied to the control gate of a selected cell. These complementary progression program pulses result in greater precision in programming. For example, in a programming pulse cycle with a CG increment of 10mV and an EG decrease of 20mV, the resulting voltage in FG after the precision programming pulse cycle is 10mV, assuming a 40% CG coupling ratio and a 10% EG coupling ratio with respect to FG. * 40%-20mV * 15% is approximately 1mV. This complementary pulse programming method can be used in the precision programming step 3306 after the coarse programming step 3305, since the coarse programming step 3305 typically uses only CG increments or EG increments during its programming operation.

[0171] Further details of second and third embodiments of the rough programming method 3305 are provided here.

[0172] Figure 37 shows a second embodiment of the coarse programming (adjustment) method 3305, which is the adaptive calibration method 3700. The method is initiated (step 3701). The cell is programmed by applying an initial voltage v0 to the coarse programming terminal according to one of the sequences shown in Table 9 (step 3702). Unlike the lookup and execution method 3400, here v0 is not obtained from a lookup table and can instead be a relatively small initial value. In a non-limiting embodiment, the control gate (or erase gate) voltage of the cell (which may be referred to as CG1 or EG1) is measured at a first current value IR1 (e.g., 100 na), and the voltage on the same gate (which may be referred to as CG2 or EG2) is measured at a second current value IR2 (e.g., 10 na), i.e., IR2 is 10% of IR1. The subthreshold IV slope is determined and stored based on these measurements (e.g., 360 mV / dec or dV / d LOG(I) of the current) (step 3703). The IV slope in the linear region is dV / dI.

[0173] New voltage V i This is determined. When this step is performed for the first time, i=1, and the program voltage v1 is determined based on the stored subthreshold slope value as well as the current target and offset value, using a subthreshold formula such as the following: vi=v i-1 +v increment , V increment It is proportional to the slope of Vg. Vg=n * Vt * log[Ids / wa * Io] Here, wa is the w of the memory cell, Ids is the cell current, and Io is the cell current when Vg=Vth, Vt is the thermal voltage, and using g from 1 to 2, V1 is determined by current IR1 and V2 is determined by current IR2. Slope=(V1-V2) / (LOG(IR1)-LOG(IR2)) In the formula, v increment =α * Slope *(LOG(IR1)-LOG(I CT )) and I CT is the target current, and α is a predetermined constant (programming offset value) < 1 to prevent overshoot, for example, 0.9.

[0174] If the stored slope value is relatively steep, a relatively small current offset value can be used. If the stored slope value is relatively flat, a relatively high current offset value can be used. Therefore, determining the slope information allows for the selection of a current offset value that is customized for the particular cell in question. This generally shortens the programming process. When step 3704 is repeated, i is incremented, and v i =v i-1 +v increment Therefore, the cell is v i It is programmed by applying it to the coarse adaptive programming terminal. increment Also, the target current value is associated with v increment It can also be determined from a lookup table that stores the value.

[0175] Next, a read operation is performed on the selected cell, and the current (I) is drawn through the selected cell. cell ) is measured, and a verification operation is performed (step 3705). cell I CT If it is less than or equal to (the crude target threshold value here), CT =I D +I CTOFFSET , I CTOFFSET This is an offset value added to prevent program overshoot, and the adaptive calibration method 3700 is completed, and the precision programming method 3306 can be initiated. cell is I CT Otherwise, steps 3704-3705 (a new slope measurement is taken using a new data point) or steps 3703-3705 (if the same slope previously used is reused) are repeated, and i is incremented.

[0176] Figure 38 shows a high-level block diagram of the circuit for the implementation of method 3703. Current source 3801 is used to apply exemplary current values ​​IR1 and IR2 to a selected cell (here, memory cell 3802), and the voltage at the coarse programming terminal of memory cell 3802 (V1 (VCGR1 or VEGR1) for IR1 and V2 (VCGR2 or VEGR2) for IR2) is then measured, and the coarse programming terminal is selected according to Table 9. The linear slope is (V1-V2) / decade of the cell current on the LOGI-V curve, i.e., equal to (V1-V2) / (LOG(IR1)-LOG(IR2)).

[0177] Figure 39 shows a third embodiment of the programming method 3305, which is the adaptive calibration method 3900. The method is initiated (step 3901). The cell is programmed with a default starting value v0 by applying v0 to the cell's coarse adaptive programming terminal (step 3902). v0 is obtained from a lookup table, such as one created from silicon characterization, and the table value is offset so as not to overshoot the programmed target. An example of v0 is shown in Table 13. Table 13: Initial voltage v0 applied to the course adaptive programming terminal during adaptive calibration method 3900 [Table 13]

[0178] Step 390 3 Next, the IV slope parameter used to predict the next programming voltage is created. A first voltage, V1, is applied to the control gate or erase gate of the selected cell, and the resulting cell current, IR1, is measured. Then, a second voltage, V2, is applied to the control gate or erase gate of the selected cell, and the resulting cell current, IR2, is measured. The slope is determined based on these measurements and stored, for example, according to the following equation in the subthreshold region (a cell operating at a subthreshold): Slope=(V1-V2) / (LOG(IR1)-LOG(IR2)) (Step 3903). Examples of V1 and V2 values ​​are shown in Table 13 above.

[0179] Determining the IV slope information is customized for the specific cell in the problem. increment It allows values ​​to be selected. This generally shortens the programming process.

[0180] Each time step 3904 is performed, i is incremented, with an initial value of 0 and a desired programming voltage, v i This is determined using the following equation, based on the stored slope value, current target, and offset value. v i =v i-1 +v increment , In the formula, v increment =α * Slope * (LOG(IR1)-LOG(I CT )), I CT is the target current, and α is a predetermined constant (programming offset value) < 1 to prevent overshoot, for example, 0.9.

[0181] Next, the selected cell is v i It is programmed using (Step 3905).

[0182] Next, a read operation is performed on the selected cell, and the current (I) is drawn through the selected cell. cell ) is measured, and a verification operation is performed (step 3906). cell I CT If it is less than or equal to (the crude target threshold value here), CT =I D +I CTOFFSET , I CTOFFSETi is an offset value added to prevent program overshoot, and the process proceeds to step 3907. Otherwise, the process returns to step 3903 (new incline measurement) or 3904 (previous incline reused), and i is incremented.

[0183] In step 3907, I cell is, I CT Smaller threshold value, I CT2 It is compared to I. cell I CT It means becoming less than I cell I CT If it is far below that value, an overshoot has occurred, and the stored value may actually correspond to an incorrect value. cell I CT2 If the following conditions are not met, no overshoot has occurred, adaptive calibration method 3900 is complete, and the process proceeds to precision programming method 3306. cell I CT2 An overshoot occurs if the following conditions are met: In this case, the selected cell is cleared (step 3908), and the programming process restarts in step 3902. Optionally, if step 3908 is executed more times than predetermined, the selected cell may be considered a bad cell that should not be used, and an error signal is output or a flag is set to identify the cell.

[0184] The precision programming method 3306 may consist of multiple verification and programming cycles, wherein, toward the next pulse, the pulse width is fixed and the programming voltage is incremented by a constant minute voltage, or the programming voltage is fixed and the programming pulse width changes.

[0185] Step 3906, optionally determining whether the current passing through the selected non-volatile memory cell is less than or equal to a first threshold current value during a read operation or verification operation, involves applying a fixed bias to the terminals of the non-volatile memory cell, measuring and digitizing the current drawn in by the selected non-volatile memory cell to generate a digital output bit, and setting the digital output bit to the first threshold current, I CT This can be done by comparing it with the digital bits that represent it.

[0186] Step 3907, optionally determining whether the current passing through the selected non-volatile memory cell is less than or equal to a second threshold current value during a read operation or verification operation, involves applying a fixed bias to the terminals of the non-volatile memory cell, measuring and digitizing the current drawn in by the selected non-volatile memory cell to generate a digital output bit, and setting the digital output bit to the second threshold current, I CT2 This can be done by comparing it with the digital bits that represent it.

[0187] The optional step 3906, 3907, which determines whether the current flowing through the selected non-volatile memory cell during a read operation or verification operation is less than or equal to a first or second threshold current value, can be performed by applying an input to the terminals of the non-volatile memory cell, modulating the current drawn in by the selected non-volatile memory cell with an output pulse to generate a modulated output, digitizing the modulated output to generate digital output bits, and comparing the digital output bits with digital bits representing the first or second threshold current, respectively.

[0188] Measuring cell current for the purpose of verifying or reading the current can be done by averaging multiple measurements, for example, 8 to 32 measurements, to reduce the influence of noise.

[0189] Figure 40 shows a fourth embodiment of the coarse programming method 3305, which is the absolute calibration method 4000. The method is initiated (step 4001). The associated terminals of the cell are programmed with a default starting value v0 (step 4002). An example of v0 is shown in Table 14. Table 14: Initial voltage v0 applied to memory cell terminals during absolute calibration method 4000 [Table 14]

[0190] The voltage vTx on the coarse programming terminal is measured and stored at the current value Itarget driven through the cell, as described above in relation to Figure 38 (step 4003). The new coarse programming voltage, v1, is determined based on the stored voltage vTx and the offset value, vToffset (corresponding to Ioffset) (step 4004). For example, the new desired voltage v1 can be calculated as follows: v1 = v0 + (VTBIAS - vTx) - vToffset, where, for example, VTBIAS = approximately 1.5V, which is the default terminal voltage at the maximum target current (meaning the maximum current level that the memory cell allows). Essentially, the new target voltage is adjusted by the amount that is the difference between the current voltage vTx at the target current and the maximum voltage and offset.

[0191] Next, the cell is v i It is programmed using (step 4005). When i=1, the voltage v1 from step 4004 is used. When i>=2, the voltage v i =v i-1 +v increment v is used. increment This corresponds to the target current value v increment The value can be determined from a lookup table that stores the value. Next, a read operation is performed on the selected cell, and the current (I) drawn through the selected cell is determined. cell ) is I CT It is compared with (step 4006). cell I CTIf the value is less than or equal to (the threshold value here), the absolute calibration method 4000 is completed and the precision programming method 3306 may be initiated. cell I CT Otherwise, steps 4005-4006 are repeated, and i is incremented.

[0192] FIG. 41 shows a circuit 4100 for measuring vTx in step 4003 of the absolute calibration method 4000. vTx is measured at each memory cell 4103 (4103-0, 4103-1, 4103-2,... 4103-n). Here, n + 1 different current sources 4101 (4101-0, 4101-1, 4101-2,... 4101-n) generate different currents IO0, IO1, IO2,... IOn with increasing magnitudes. Each current source 4101 is connected to a respective inverter 4102 (4102-0, 4102-1, 4102-2,... 4102-n) and a memory cell 4103 (4103-0, 4103-1, 4103-2,... 4103-n). The input to each inverter 4102 (4102-0, 4102-1, 4102-2,... 4102-n) is initially high, and the output of each inverter is initially low. Since IO0 < IO1 < IO2 <... < IOn, the output of inverter 4102-0 will first switch from low to high because memory cell 4103-0 draws current from current source 4101-0 and also draws current from the input node of inverter 4102-0, reducing the input voltage to inverter 4102-0 before the input voltage to the other inverters 4102. Next, the output of inverter 4102-1 switches from low to high, then the output of inverter 4102-2 switches similarly, and so on until the output of inverter 4102-n switches from low to high. Each inverter 4102 controls a respective switch 4104 (4104-0, 4104-1, 4104-2,... 4104-n). As a result, when the output of inverter 4102 is high, switch 4104 is closed, whereby vTx is sampled by capacitor 4105 (4105-0, 4105-1, 4105-2,... 4105-n). Thus, switches 4104 and capacitors 4105 form a sample-and-hold circuit. In this way, vTx is measured using a sample-and-hold circuit.

[0193] Figure 42 shows an exemplary procedure 4200 for programming a selected cell during adaptive calibration method 3700 or absolute calibration method 4000. The voltage VTP (a programming voltage applied to the CG or EG terminal, corresponding to vi in ​​step 3704 in Figure 37 and step 4005 in Figure 40) is applied to the terminal of the selected memory cell using the bit line enable signal En_blx (where x varies between 1 and n, and n is the number of bit lines).

[0194] Figure 43 shows another exemplary procedure 4300 for programming a selected cell during adaptive calibration method 3700 or absolute calibration method 4000. The voltage VTP (a programming voltage applied to the CG or EG terminal, corresponding to vi in ​​step 3704 in Figure 37 and step 4005 in Figure 40) is applied to the terminal of the selected memory cell using the bit line enable signal En_blx (where x varies between 1 and n, and n is the number of bit lines).

[0195] In another embodiment, the voltage applied to the control gate terminal is incremented, and the voltage applied to the erase gate terminal is also incremented.

[0196] In another embodiment, the voltage applied to the control gate terminal is increased, and the voltage applied to the erase gate terminal is decreased. This is shown in Table 15. Table 15: Increment in control gate terminals and decrease in erase gate terminals [Table 15]

[0197] For comparison, examples of incrementing only the control gate terminal or only the erase gate terminal are included in Table 16. Table 16: Control gate terminal increment, erase gate terminal increment [Table 16]

[0198] Figure 44 shows a system for implementing input and output methods for reading or verifying within a VMM array after precision programming. The input function circuit 4401 receives digital bit values ​​and converts those digital values ​​to analog signals for use, thereby applying a voltage to the control gate of a selected cell in array 4404, which is determined via the control gate decoder 4402. Simultaneously, the word line decoder 4403 is also used to select the row in which the selected cell is located. The output neuron circuit block 4405 receives output currents from each column of cells in array 4404. The output circuit block 4405 includes an integrating analog-to-digital converter (ADC), a successive approximation (SAR) ADC, a sigma-delta ADC, or any other ADC scheme for providing a digital output.

[0199] In one embodiment, the digital value provided to the input function circuit 4401 includes four bits (DIN3, DIN2, DIN1, and DIN0), or any number of bits, and the digital value represented by these bits corresponds to the number of input pulses applied to the control gate during programming. A larger number of pulses results in a larger value being stored in the cell, and when the cell is read out, it produces a larger output current. Examples of input bit values ​​and pulse values ​​are shown in Table 17. Table 17: Digital bit input and number of generated pulses [Table 17]

[0200] In the example above, there are up to 15 pulses for a 4-bit digital input. Each pulse is equal to one unit cell value (current), i.e., a precisely programmed current. For example, if Icell unit = 1nA, then DIN[3~0] = 0001, Icell = 1 * 1nA=1nA, and DIN[3~0]=1111, Icell=15 * 1nA = 15nA.

[0201] In another embodiment, the digital bit input uses digital bit position summing to read out the cell or neuron value (e.g., a precisely programmed value of a bit line output), as shown in Table 18. Here, only four pulses or four fixed identical bias inputs (e.g., word line or control gate inputs) are required to evaluate the four-bit digital value. For example, the first pulse or first fixed bias is used to evaluate DIN0, the second pulse or second fixed bias having the same value as the first is used to evaluate DIN1, the third pulse or third fixed bias having the same value as the first is used to evaluate DIN2, and the fourth pulse or fourth fixed bias having the same value as the first is used to evaluate DIN3. Then, as shown in Table 19, the results from the four pulses, each output result multiplied (scaled) by a multiplication coefficient of 2^n (where n is the digital bit position), are added according to the bit positions. The implemented digital bit summing formula is: Output = 2^0 * DIN0+2^1 * DIN1+2^2 * DIN2+2^3 * DIN3) * Icell is the unit of measurement; in the formula, Icell represents a precisely programmed current.

[0202] For example, if Icell unit = 1nA, then DIN[3~0] = 0001, and Icell total = 0+0+0+1 * 1nA=1nA, and DIN[3~0]=1111, Icell total=8 * 1nA+4 * 1nA+2 * 1nA+1 * 1nA = 15nA. Table 18: Digital bit input summation [Table 18] Table 19: Sum of digital input bits Dn and 2^n output multiplication coefficient [Table 19]

[0203] Another embodiment having a hybrid input with multiple digital input pulse ranges and a sum of input digital ranges is shown in Table 20 for an exemplary 4-bit digital input. In this embodiment, DINn-0 can be divided into m different groups, each group is evaluated, and the output is scaled by a multiplication factor based on the group binary position. For example, in the case of a 4-bit DIN3-0, the groups could be DIN3-2 and DIN1-0, with the output of DIN1-0 scaled by 1 (X1) and the output of DIN3-2 scaled by 4 (X4). Table 20: Sum of hybrid inputs and outputs with multiple input ranges [Table 20]

[0204] Another embodiment combines a hybrid input range with a hybrid supercell. The hybrid supercell contains multiple physical x-bit cells and implements a logical n-bit cell by scaling the x-cell output by 2^n binary positions. For example, two 4-bit cells (cell 1, cell 0) are used to implement an 8-bit logical cell. The output of cell 0 is scaled by 1 (X1), and the output of cell 1 is scaled by 4 (X, 2^2). Other combinations of physical x cells to implement an n-bit logical cell are possible, such as two 2-bit physical cells and one 4-bit physical cell to implement an 8-bit logical cell.

[0205] Figure 45 shows how a digital bit input reads the current of a cell or neuron (e.g., the value of the bit line output) modulated by modulator 4510 using digital bit position summation with an output pulse width designed according to the digital input bit position (e.g., current = output voltage (V = current)). *Another embodiment similar to the system in Figure 44 is shown, except for the conversion of pulse width / capacitance. For example, a first bias (applied to an input word line or control gate) is used to evaluate DIN0, and the current (cell or neuron) output is modulated by modulator 4510 with a unit pulse width proportional to the DIN0 bit position, which is 1 (x1) units; a second input bias is used to evaluate DIN1, and the current output is modulated by modulator 4510 with a pulse width proportional to the DIN1 bit position, which is 2 (x2) units; a third input bias is used to evaluate DIN2, and the current output is modulated by modulator 4510 with a pulse width proportional to the DIN2 bit position, which is 4 (x4) units; and a fourth input bias is used to evaluate DIN3, and the current output is modulated by modulator 4510 with a pulse width proportional to the DIN3 bit position, which is 8 (x8) units. Next, each output is converted to a digital bit by an ADC (analog-to-digital converter) 4511 for each digital input bit DIN0 to DIN3. Then, the total output is output by an adder 4512 as the sum of the four digital outputs generated from the DIN0-3 inputs.

[0206] Figure 46 shows an example of a charge adder 4600 that can be used to sum the outputs of the VMM, Icell during verification operation or analog-to-digital conversion of the output neuron to obtain a single analog value representing the output of the VMM, the single analog value can then be optionally converted to a digital bit value. The charge adder 4600 can be used, for example, as an adder 4512. The charge adder 4600 includes a current source 4601 (representing the current Icell output by the VMM), a sample-and-hold circuit including a switch 4602 and a sample-and-hold (S / H) capacitor 4603. The example shown utilizes a 4-bit digital value for the output, but other numbers of bits can be used instead. There are four S / H circuits for holding values ​​generated from four evaluation pulses, and these values ​​are summed at the end of the process. The S / H capacitor 4603 has 2^n of its S / H capacitor* The selection is based on a ratio associated with the DINn bit position. For example, switch 4602 for C_DIN3 is closed when Icell > 8 × current threshold, switch 4602 for C_DIN2 is closed when Icell > 4 × current threshold, switch 4602 for C_DIN1 is closed when Icell > 2 × current threshold, and switch 4602 for C_DIN0 is closed when Icell > current threshold. Thus, the digital value stored by sample-and-hold capacitor 4603 reflects the value of Icell 4601.

[0207] Figure 47 shows a current adder 4700 that can be used to sum the outputs of VMM, Icell during verification operation or analog-to-digital conversion of output neurons. A charge adder 4700 may be used, for example, as adder 4512. The current adder 4700 includes a current source 4701 (representing Icell output from VMM), switches 4702, 4703, and 4704, and transistor 4705. The example shown utilizes a 4-bit digital value of the output, where the bit values ​​are represented by currents I_DIN0, I_DIN1, I_DIN2, and I_DIN3. The bit position of each transistor 4705 affects the value represented by that bit. Switch 4703 on I_DIN3 closes when Icell > 8 × current threshold, switch 4703 on I_DIN2 closes when Icell > 4 × current threshold, switch 4704 on I_DIN1 closes when Icell > 2 × current threshold, and switch 4703 on I_DIN0 closes when Icell > current threshold. Therefore, the digital value output by transistor 4705 (where "1" represents a positive current and "0" represents no current, and vice versa) reflects the value of Icell 4601.

[0208] Figure 48 shows a digital adder 4800 that receives multiple digital values, sums them together, and produces an output DOUT representing the sum of the inputs. A digital adder 4600 may be used, for example, as adder 4512. The digital adder 4800 may be used during verification operation or during analog-to-digital conversion of an output neuron. There are digital output bits to hold values ​​from four evaluation pulses, as shown in the example of a 4-bit digital value, and these values ​​are summed at the end of the process. The digital output is 2^n * It is digitally scaled based on the DINn bit position, for example, DOUT3=x8 DOUT0, _DOUT2=x4 DOUT1, I_DOUT1=x2 DOUT0, I_DOUT0=DOUT0.

[0209] Figure 49A shows a double-slope-integrating ADC 4900 applied to an output neuron to convert cell current into digital output bits. An integrator consisting of an integrating operational amplifier 4901 and an integrating capacitor 4902 integrates the cell current ICELL with respect to a reference current IREF. As shown in Figure 49B, for a fixed time t1, switch S1 is closed and switch S2 is open, and the cell current is integrated up (Vout rises with waveform 4950). Switch S1 is then opened and switch S2 is closed, and as a result, the reference current IREF is applied so that it is integrated down over time t2 (Vout falls with waveform 4950). The value of the current Icell is = t2 / t1 * This is determined as IREF. For example, for t1, a 10-bit digital bit resolution uses 1024 cycles, and the number of cycles for t2 varies from 0 to 1024 cycles depending on the Icell value. When the target value is applied to comparator 4904 as VREF, the output EC4905 of comparator 4904 can be used as a trigger to determine the number of cycles to which IREF has been applied until VOUT falls below VREF.

[0210] Figure 49C shows the single gradient integrating ADC4960 applied to output neuron 4966, ICELL, to convert cell current into digital output bits. ADC4960 teeth, Integrating operational amplifier 4961, integrating capacitor 4962, operational amplifier 4964, and switches S1 and S3 including The integrating operational amplifier 4961 and integrating capacitor 4962 integrate the output neuron current, ICELL. As shown in Figure 49D, during time t1, the cell current is up-integrated (Vout rises until it reaches Vref2), and simultaneously with time t1, but for a time t2 which is greater than time t1, the cell current of the reference cell is up-integrated. The cell current ICELL is = Cint * Vref is determined as Vref2 / t. A pulse counter coupled to the output of comparator 4965 is used to count the number of pulses (digital output bits) during the respective integration times t1 and t2. For example, as shown in the figure, the number of digital output bits for t1 is less than the number of digital output bits for t2, which means that the cell current during t1 is greater than the cell current during t2. Initial calibration is performed to calibrate the integrating capacitor value with a reference current and fixed time, where Cint = Tref * Iref / Vref2.

[0211] Figure 49E shows a double-slope-integrating ADC 4980 applied to output neuron 4984, ICELL, to convert cell current into digital output bits. The double-slope-integrating ADC 4980 includes switches S1, S2, and S3, operational amplifier 4981, capacitor 4982, and reference current source 4983. The double-slope-integrating ADC 4980 does not utilize an integrating operational amplifier. The cell current or reference current is directly integrated at capacitor 4982. A pulse counter is used to count pulses (digital output bits) during the integration time. Current Icell = t2 / t1 * It is IREF.

[0212] Figure 49F shows a single gradient integrating ADC 4990 applied to output neuron 4994, ICELL, to convert the cell current into digital output bits. The single gradient integrating ADC 4990 includes switches S2 and S3, operational amplifier 4991, and capacitor 4992. The single gradient integrating ADC 4980 does not utilize an integrating operational amplifier. The cell current is directly integrated at capacitor 4992. A pulse counter is used to count pulses (digital output bits) during the integration time. Cell current Icell = Cint * Vref2 / t

[0213] Figure 50A shows a SAR (Successive Approximation) ADC applied to an output neuron to convert cell current into digital output bits. The cell current can be dropped through a resistor to convert it to a voltage VCELL. Alternatively, the cell current can be converted to a voltage VCELL by charging up an S / H capacitor. VCELL is supplied to the inverting input of comparator 5003, whose output is supplied to the selection input of SAR5001. A clock input CLK is further supplied to SAR5001. Binary search is used to compute the bits starting from the MSB bit (most significant bit). Based on the digital bits DN-D0 output from SAR5001 and received as input to DAC5002, the output of DAC5002 is used to set the appropriate analog reference voltage to the non-inverting input of comparator 5003, i.e., comparator 5003. The output of comparator 5003 is sequentially fed back to SAR5001 to select the next analog level. As shown in Figure 50B, in the example of a 4-bit digital output, there are four evaluation periods, without limitation: a first pulse for evaluating DOUT3 by setting the analog level to the middle, and then a second pulse for evaluating DOUT2 by setting the analog level to the middle of the upper half or the middle of the lower half.

[0214] Modified binary search, such as cyclic (algorithmic) ADCs, can be used for cell tuning (e.g., programming) verification or output neuron transformation. Modified binary search, such as switched-cap (SC) charge redistribution ADCs, can be used for cell tuning (e.g., programming) verification or output neuron transformation.

[0215] Figure 51 shows a sigma-delta ADC 5100 applied to an output neuron to convert cell current into digital output bits. An integrator consisting of op-amp 5101 and capacitor 5105 integrates the sum of the current ICELL from the selected cell current 5106 and the reference current IREF from the 1-bit current cDAC 5104. A comparator 5102 compares the integrated output voltage of op-amp 5101 to a reference voltage, VREF2. A clocked DFF 5103 provides a digital output stream depending on the output of comparator 5102 received at the D input of the DFF 5103. The digital output stream typically proceeds to a digital filter before being output as digital output bits.

[0216] Figure 52A shows a ramp-type analog-to-digital converter 5200, which includes a current source 5201 (representing the received neuron current ICELL), a switch 5202, a variable configurable capacitor 5203, and a comparator 5204, which takes a voltage labeled Vneu generated across the variable configurable capacitor 5203 as a non-inverting input and a configurable reference voltage Vreframp as an inverting input to generate an output Cout. Vreframp ramps up at a discrete level with each comparison clock cycle. The comparator 5204 compares Vneu with Vreframp, and as a result, the output Cout is "1" when Vneu > Vreframp, and "0" otherwise. Thus, the output Cout is a pulse whose width changes in response to Ineu. The larger Ineu is, the longer the period during which Cout is "1", and as a result, the pulse width of the output Cout becomes wider. The digital counter 5220 converts each pulse of the output Cout pulse 522 into a digital output bit, which is a count value 5221, for two different ICELL currents labeled OT1A and OT2A, as shown in Figure 52B.

[0217] Alternatively, the ramp voltage Vreframp is the continuous ramp voltage 5255 shown in graph 5250 of Figure 52B.

[0218] Alternatively, Figure 52C shows a multi-lamp embodiment for reducing conversion time by utilizing a coarse-to-fine ramp conversion algorithm. First, a coarse reference ramp voltage 5271 is ramped rapidly to determine the subrange of each ICELL. Next, the fine reference ramp voltages 5272 for each subrange, i.e., Vreframp1 and Vreframp2, are used to convert the ICELL current within each subrange. As shown in the figure, there are two subranges of the fine reference ramp voltage. Two or more coarse / fine steps or two subranges are possible.

[0219] Figure 53 shows an algorithmic analog-to-digital output converter 5300, which includes switches 5301 and 5302, a sample-and-hold (S / H) circuit 5303, a 1-bit analog-to-digital converter (ADC) 5304, a 1-bit digital-to-analog converter (DAC) 5305, an adder 5306, and gains for a 2-residual operational amplifier (2x op-amp) 5307. The algorithmic analog-to-digital output converter 5300 generates a converted digital output 5308 in response to an analog input Vin and switches 5302 and a control signal applied to 5302. The input received at analog input Vin (e.g., Vneu in Figure 52) is first sampled by the S / H circuit 5303 in response to switch 5302, and then the conversion is performed for N bits over N clock cycles. For each conversion clock cycle, the 1-bit ADC 5304 compares the S / H voltage 5309 with a reference voltage VREF / 2 and outputs a digital bit (e.g., "0" if input ≤ VREF / 2, "1" if input > VREF / 2). This digital output bit, which is the digital output signal 5308, is then converted to an analog voltage (e.g., either VREF / 2 or 0V) by the 1-bit DAC 5305 and fed to the adder 5306, which is subtracted from the S / H voltage 5309. The 2× residual op-amp 5307 then amplifies the adder difference voltage output to obtain the conversion residual voltage 5310, which is fed to the S / H circuit 5303 via switch 5301 for the next clock cycle. Instead of this 1-bit (i.e., 2-level) algorithmic ADC, a 1.5-bit (i.e., 3-level) algorithmic ADC can be used to reduce the effects of offsets from the ADC 5304 and residual op-amp 5307, etc. For use with a 1.5-bit algorithmic ADC, a 1.5-bit or 2-bit (i.e., 4-level) DAC is preferred. In another embodiment, a hybrid ADC can be used. For example, for a 9-bit ADC, the first 4 bits may be generated by a SAR ADC, and the remaining 5 bits may be generated using a slope ADC or ramp ADC. [Programming and verification of multiple physical cells as a single logical multi-bit cell]

[0220] The programming and verification devices and methods described above can operate simultaneously with multiple physical cells as logical multi-bit cells.

[0221] Figure 54 shows a logical multi-bit cell 5400 containing i physical cells labeled as physical cells 5401-1, 5401-2, ..., 5401-i. In one embodiment, the physical cells 5401 have a uniform diffusion width (transistor width). In another embodiment, the physical cells 5401 have a non-uniform diffusion width (different transistor widths; transistors with larger widths can store more levels and therefore more bits). In both embodiments, the physical cells 5401 are programmed, verified, and read out as a single logical n-bit cell, specifically capable of storing more levels than each of the m-bit cells. For example, when m=2, each physical cell 5401 can hold one of four levels (L0, L1, L2, L3). Two such cells can be treated as a single logical cell with n=3, and as a result, a single logical cell can hold one of eight levels (L0, L1, L2, L3, L4, L5, L6, L7). As another example, with m=3, each physical cell 5401 can hold one of eight levels (L0, ..., L7). Four such cells can be treated as a single logical cell with n=5, and as a result, a single logical cell can hold one of 32 levels (L0, ..., L31).

[0222] Figure 55 shows method 5500 for programming logic multibit cells 5400. First, j cells (where j ≤ i) out of i physical cells 5401-1, ..., 5401-i are programmed and verified using one of the coarse programming methods 3305 until the coarse current target of the j physical cells is achieved (step 5501). Next, k cells (where k ≤ j) out of j physical cells are programmed and verified using one of the precise programming methods 3306 until the precise current target of the k physical cells is achieved (step 5502).

[0223] Method 5500 can be performed on more than one subset of i physical cells 5401-1, ... 5401-i to achieve the desired overall level of logical multi-bit cell 5400.

[0224] For example, if i=4, there are four cells: 5401-1, 5401-2, 5401-3, and 5401-4. Assuming that each cell can hold one of eight different levels, the logical multi-bit cell 5400 can hold one of 32 different levels. If the desired programming value is L27, that level (corresponding to the desired read current) can be achieved in any number of different ways.

[0225] For example, method 5500 can be performed on cells 5401-1, 5401-2, and 5401-3 until those cells collectively hold L23 (the 24th level), and then method 5500 is performed on cell 5401-4 to program that cell to the 4th level so that the logical multibit cell 5400 achieves L27 (the 28th level).

[0226] As another example, method 5500 can be performed on cells 5401-1, 5401-2, 5401-3, and 5401-4 until those cells collectively hold L25 (the 26th level), and then method 5500 can be performed only on cell 5401-4 until the entire logical multibit cell 5400 stores a value that achieves L27 (the 28th level).

[0227] Other approaches are possible, and method 5500 can be performed on different subsets of i physical cells until the desired level is achieved.

[0228] In another embodiment, in a situation where i physical cells have non-uniform diffusion widths, the coarse programming step 3305 can be performed on j1 ​​physical cells having wider transistor widths until j1 physical cells collectively achieve the coarse current target, and then the fine programming step 3306 can be performed on j2 physical cells having the smallest transistor widths until j1+j2 physical cells collectively achieve the fine current target.

[0229] It should be noted that, as used herein, the terms “over” and “on” both encompass “directly on” (without intermediate material, element, or gap between them) and “indirectly on” (with intermediate material, element, or gap between them). Similarly, the term “adjacent” includes “directly adjacent” (without intermediate material, element, or gap between them) and “indirectly adjacent” (with intermediate material, element, or gap between them); “attached” includes “directly attached” (without intermediate material, element, or gap between them) and “indirectly attached to” (with intermediate material, element, or gap between them); and “electrically coupled” includes “directly electrically coupled” (without intermediate material or element electrically connecting the elements together between them) and “indirectly electrically coupled to” (with intermediate material or element electrically connecting the elements together between them). For example, forming an element "on top of a substrate" may include forming the element directly on the substrate without any intermediate materials / elements between them, and forming the element indirectly on the substrate with one or more intermediate materials / elements between them.

Claims

1. A method for programming a logical multibit cell comprising i physical nonvolatile memory cells, wherein each of the i physical nonvolatile memory cells is capable of storing one of n possible values, where i is an integer greater than 1, and n is an integer greater than 1, and the method is A step of performing a programming operation in j of the i physical nonvolatile memory cells until the crude current target of the logical multi-bit cell is achieved, wherein j is less than or equal to i; A method comprising the step of performing a programming operation in k of the j physical nonvolatile memory cells until a precise current target of the logical multibit cell is achieved, wherein k is less than or equal to j.

2. The method according to claim 1, wherein the i physical non-volatile memory cells have a uniform width.

3. The method according to claim 1, wherein the i physical non-volatile memory cells have non-uniform widths.

4. A method for programming a logical multibit cell comprising i physical nonvolatile memory cells of non-uniform width, wherein each of the i cells is capable of storing one of n possible values, where i is an integer greater than 1 and n is an integer greater than 1, and the method is A step of performing a programming operation until the crude current target of the logical multibit cell is achieved in j of the i physical nonvolatile memory cells, the one containing the largest width, wherein j is less than or equal to i; A method comprising the step of performing a programming operation until a precise current target of the logical multibit cell is achieved in k of the j physical nonvolatile memory cells having the smallest width, wherein k is less than or equal to j.

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