Package including wire bonds coupled to integrated devices

Abstract

A package comprising: a substrate including a cavity; a first integrated device coupled to the substrate through a first plurality of pillar interconnects and a first plurality of solder interconnects; a second integrated device coupled to the substrate through a second plurality of pillar interconnects and a second plurality of solder interconnects; and a plurality of wire bonds coupled to the first integrated device and the second integrated device, the plurality of wire bonds being located over the cavity of the substrate.

Description

Technical Field

[0001] Cross - Reference to Related Applications This application claims the priority and benefit of non - provisional application No. 17 / 213,875, filed with the United States Patent and Trademark Office on March 26, 2021, the entire content of which is incorporated herein by reference for all applicable purposes as if fully set forth below.

[0002] Various features relate to packages including integrated devices, and more particularly to packages including integrated devices and substrates.

Background Art

[0003] FIG. 1 shows a package 100 including a substrate 102, an integrated device 104, and an integrated device 106. The substrate 102 includes at least one dielectric layer 120, a plurality of interconnects 122, and a plurality of solder interconnects 124. A plurality of solder interconnects 144 are coupled to the substrate 102 and the integrated device 104. A plurality of solder interconnects 164 are coupled to the substrate 102 and the integrated device 106. There is a current need to provide packages with better performance.

Summary of the Invention

Means for Solving the Problems

[0004] Various features relate to packages including integrated devices, and more particularly to packages including integrated devices and substrates.

[0005] One example provides a package including a substrate including a cavity, a first integrated device coupled to the substrate through a first plurality of pillar interconnects and a first plurality of solder interconnects, a second integrated device coupled to the substrate through a second plurality of pillar interconnects and a second plurality of solder interconnects, and a plurality of wire bonds coupled to the first integrated device and the second integrated device, wherein the plurality of wire bonds are positioned over the cavity of the substrate.

[0006] Another example provides an apparatus comprising a substrate containing a cavity, a first integrated device bonded to the substrate through a first plurality of pillar interconnects and a first plurality of solder interconnects, a second integrated device bonded to the substrate through a second plurality of pillar interconnects and a second plurality of solder interconnects, and means for wire interconnection bonded to the first and second integrated devices, wherein the means for wire interconnection is located on the cavity in the substrate.

[0007] Another example provides a method for manufacturing a package. The method provides a substrate containing a cavity. The method bonds a first integrated device to the substrate through a first plurality of pillar interconnects and a first plurality of solder interconnects. The method bonds a second integrated device to the substrate through a second plurality of pillar interconnects and a second plurality of solder interconnects. The method forms a plurality of wire bonds between the first integrated device and the second integrated device, the plurality of wire bonds located over the cavity in the substrate.

[0008] Various features, properties, and advantages may become apparent from the detailed description below when read in conjunction with drawings, which are identified by similar reference numerals throughout. [Brief explanation of the drawing]

[0009] [Figure 1] This is a side view of a package including an integrated device and a substrate. [Figure 2] This is a side view of a package including wire bonds coupled to an integrated device. [Figure 3] This is a plan view of a package including wire bonds coupled to an integrated device. [Figure 4] This is a plan view of a wire bond connected to an integrated device. [Figure 5] This is an enlarged plan view of a wire bond connected to an integrated device. [Figure 6] This is a side view of a wire bond connected to an integrated device. [Figure 7] This is a side view of a package including wire bonds coupled to an integrated device. [Figure 8A] This figure shows an exemplary sequence for manufacturing an integrated device having pillar interconnects. [Figure 8B] This figure shows an exemplary sequence for manufacturing an integrated device having pillar interconnects. [Figure 9] This is an illustrative flowchart of a method for manufacturing an integrated device having pillar interconnects. [Figure 10A] This figure shows an exemplary sequence for manufacturing a substrate. [Figure 10B] This figure shows an exemplary sequence for manufacturing a substrate. [Figure 10C] This figure shows an exemplary sequence for manufacturing a substrate. [Figure 11] This is an illustrative flowchart of a method for manufacturing a circuit board. [Figure 12A] This figure shows an exemplary sequence for manufacturing a package including wire bonds coupled to an integrated device. [Figure 12B] This figure shows an exemplary sequence for manufacturing a package including wire bonds coupled to an integrated device. [Figure 13] This is an illustrative flowchart of a method for manufacturing a package including wire bonds coupled to an integrated device. [Figure 14] This figure shows various electronic devices that can integrate dies, electronic circuits, integrated devices, integrated passive devices (PIDs), passive components, packages, and / or device packages as described herein. [Modes for carrying out the invention]

[0010] The following description provides specific details to enable a full understanding of the various aspects of this disclosure. However, it will be understood by those skilled in the art that aspects may be practiced without these specific details. For example, circuits may be shown in block diagrams to avoid obscuring the aspect with unnecessary details. In other cases, well-known circuits, structures, and techniques may not be shown in detail to avoid obscuring the aspects of this disclosure.

[0011] This disclosure describes a package comprising a substrate including a cavity, a first integrated device bonded to the substrate through a first plurality of pillar interconnects and a first plurality of solder interconnects, a second integrated device bonded to the substrate through a second plurality of pillar interconnects and a second plurality of solder interconnects, and a plurality of wire bonds bonded to the first and second integrated devices, wherein the plurality of wire bonds are located on the cavity of the substrate. The first integrated device includes a first row of a plurality of pads and a second row of a plurality of pads. The second integrated device includes a first row of a plurality of pads and a second row of a plurality of pads. The plurality of wire bonds include a first plurality of wire bonds bonded to (i) a first row of a plurality of pads of the first integrated device and (ii) a first row of a plurality of pads of the second integrated device. The plurality of wire bonds include a second plurality of wire bonds bonded to (i) a second row of a plurality of pads of the first integrated device and (ii) a second row of a plurality of pads of the second integrated device. The use of multiple wire bonds helps provide higher density interconnections between integrated devices. Multiple wire bonds can help provide shorter and more direct electrical paths between integrated devices. The package may include an underfill and / or encapsulation layer. The underfill and / or encapsulation layer can help provide strong structural integrity to the integrated devices and substrate, which in turn helps provide a package with a reliable interconnection between two or more integrated devices.

[0012] Exemplary package including wire bonding between integrated devices Figure 2 shows a side view of a package 200 that includes a plurality of wire bonds between integrated devices. The package 200 can be coupled to a board (e.g., a printed circuit board (PCB)) through a plurality of solder interconnects 280. The package 200 provides a package having high-density interconnects between integrated devices.

[0013] As shown in FIG. 2, the package 200 includes a substrate 202, a first integrated device 204, a second integrated device 206, a plurality of wire bonds 210, an underfill 244, an underfill 264, and a encapsulation layer 208.

[0014] As further described below, the plurality of wire bonds 210 can be coupled to the integrated devices (e.g., 204, 206) such that at least one electrical signal (e.g., a first electrical signal, a second electrical signal) bypasses the substrate 202 when traveling between at least two integrated devices (e.g., 204, 206). However, at least one electrical signal can travel through at least one electrical path defined by the package interconnects, integrated devices, and / or substrate.

[0015] The substrate 202 includes a first surface (e.g., the upper surface) and a second surface (e.g., the bottom surface). The substrate 202 includes at least one dielectric layer 220, a plurality of interconnects 222, a first solder resist layer 224, and a second solder resist layer 226. The substrate 202 also includes a cavity 209 that extends through the substrate 202. The cavity 209 can extend through at least one dielectric layer 220, the first solder resist layer 224, and the second solder resist layer. The cavity 209 can have any shape (e.g., rectangular, square). The substrate 202 can include two or more cavities 209. As will be further described below, the cavity 209 can be at least partially filled (e.g., completely filled) with an encapsulation layer 208 and / or other materials. In some implementations, the cavity 209 of the substrate 202 can be an area or void where there is no dielectric layer 220 and / or the plurality of interconnects 222 of the substrate 202. The substrate 202 can be considered to have the cavity 209 even if the cavity 209 is later filled with one or more materials. As will be further described below, the cavity 209 in the substrate 202 can enable a plurality of wire bonds 210 to be formed between integrated devices (e.g., 204, 206). The plurality of wire bonds 210 can be placed on top of the cavity 209 (e.g., above or below the cavity 209 depending on how above or below is arbitrarily defined). In some implementations, the plurality of wire bonds 210 can be at least partially placed within the cavity 209 of the substrate 202.

[0016] Multiple interconnects 222 may be configured to provide at least one electrical path to and / or from the board. Multiple interconnects 222 may be configured to provide at least one electrical path to at least one integrated device (e.g., 204, 206). Multiple interconnects 222 may be configured to provide at least one electrical path (e.g., electrical connection) between two or more integrated devices (e.g., 204, 206). Multiple interconnects 222 may have a first minimum pitch and a first minimum line width and spacing (L / S). In some mounting configurations, the first minimum line width and spacing (L / S) for multiple interconnects 222 is in the range of approximately 9 / 9 to 12 / 12 micrometers (μm) (e.g., a minimum line width of approximately 9 to 12 micrometers (μm), and a minimum spacing of approximately 9 to 12 micrometers (μm)). Various mounting configurations may use different substrates. The substrate 202 may be a laminate substrate, a coreless substrate, an organic substrate, and / or a core substrate (for example, including a core layer). In some configurations, at least one dielectric layer 220 may include a core layer and / or a prepreg layer. At least one dielectric layer 220 may have a dielectric constant in the range of approximately 3.5 to 3.7. An example of manufacturing the substrate is further illustrated below in Figures 10A to 10C. As further illustrated below, in some configurations, the substrate 202 may be manufactured using a modified semi-additive process (mSAP) or a semi-additive process (SAP).

[0017] The first integrated device 204 is coupled to a first surface (e.g., the top surface) of the substrate 202. In some mounting configurations, the first integrated device 204 is coupled to the substrate 202 through a plurality of pillar interconnects 240 and / or a plurality of solder interconnects 242. The plurality of pillar interconnects 240 and / or a plurality of solder interconnects 242 may be coupled to a plurality of interconnects 222 on the substrate 202. The plurality of pillar interconnects 240 may help provide a higher density of interconnects between the first integrated device 204 and the substrate 202. The plurality of pillar interconnects 240 may be optional. Thus, the first integrated device 204 may be coupled to the substrate 202 through a plurality of solder interconnects 242. A portion of the first integrated device 204 may be located above a cavity 209. The front surface of the first integrated device 204 may face the substrate 202. The first integrated device 204 includes a plurality of pads 241. As will be further described below, the plurality of pads 241 may be arranged in a row of pads that includes a first row of pads and a second row of pads. The first row of pads may be offset from the second row of pads, and vice versa. Note that the plurality of pads 241 may include three or more rows of pads.

[0018] The second integrated device 206 is coupled to a first surface of the substrate 202. In some mounting configurations, the second integrated device 206 is coupled to the substrate 202 through a plurality of pillar interconnects 260 and / or a plurality of solder interconnects 262. The plurality of pillar interconnects 260 and / or a plurality of solder interconnects 262 may be coupled to a plurality of interconnects 222. The plurality of pillar interconnects 260 may help provide a higher density of interconnects between the second integrated device 206 and the substrate 202. The plurality of pillar interconnects 260 may be optional. Thus, the second integrated device 206 may be coupled to the substrate 202 through a plurality of solder interconnects 262. Part of the second integrated device 206 may be located above a cavity 209. The front surface of the second integrated device 206 may face the substrate 202. The second integrated device 206 includes a plurality of pads 261. As will be further explained below, multiple pads 261 can be arranged in a row of pads that includes a first row of pads and a second row of pads. The first column of a pad can be offset from the second column of a pad, and vice versa. Note that multiple pads 261 can include three or more rows of pads.

[0019] Multiple wire bonds 210 are coupled to a first integrated device 204 and a second integrated device 206. For example, multiple wire bonds 210 are coupled to (i) multiple pads 241 of the first integrated device 204 and (ii) multiple pads 261 of the second integrated device 206. In some implementations, each of the multiple wire bonds 210 may have a diameter of at least 15 micrometers. Multiple wire bonds 210 may have different heights and / or vertical offsets (e.g., different maximum heights and / or maximum vertical offsets) from the surfaces of the integrated devices (e.g., 204, 206), the multiple pads 241, and / or the multiple pads 261. The use of multiple wire bonds 210 with different heights and / or vertical offsets enables high-density interconnection between the first integrated device 204 and the second integrated device 206. In some implementation configurations, the multiple wire bonds 210 may have a density of at least 40 wire bonds per millimeter (e.g., 40 interconnections per millimeter) between the first integrated device 204 and the second integrated device 206. The number of interconnections per millimeter provided by the multiple wire bonds 210 may be better than the number of interconnections per millimeter provided within the substrate 202. This can occur despite the fact that one or more wire bonds from the multiple wire bonds 210 may have a minimum diameter of 15 micrometers, while the interconnections within the substrate 202 may have a first minimum line width and spacing (L / S) in the range of approximately 9 / 9 to 12 / 12 micrometers (μm) (e.g., a minimum line width of approximately 9 to 12 micrometers (μm), and a minimum spacing of approximately 9 to 12 micrometers (μm)). Therefore, even though the wire bond 210 has a thicker dimension, the use of wire bonds with different heights and / or offsets allows for more interconnections per millimeter than the interconnections within the substrate 202. Moreover, multiple wire bonds 210 provide a shorter and more direct electrical path between the first integrated device 204 and the second integrated device 206.Shorter and more direct electrical paths between integrated devices can result in better performance for the integrated devices and / or packages. Examples of wire bond 210 configurations and arrangements are further illustrated below in at least Figures 4 to 6.

[0020] As shown in Figure 2, underfill 244 is installed between the first integrated device 204 and the substrate 202. Similarly, underfill 264 is installed between the second integrated device 206 and the substrate 202. Underfill 244 may surround multiple pillar interconnects (e.g., 240) and / or multiple solder interconnects (e.g., 242). Underfill 264 may surround multiple pillar interconnects (e.g., 260) and / or multiple solder interconnects (e.g., 262). Underfill 244 and / or 264 may be installed in other locations, such as inside the cavity 209 and / or above the first integrated device 204 and the second integrated device 206. Underfill 244 and / or 264 may be part of the same underfill or separate underfills.

[0021] The underfill 244 and / or 264 helps to provide structural stability to the package 200. In particular, the underfill 244 and / or 264 helps to provide a strong and reliable mechanical bond between the first integrator 204, the second integrator 206, and the substrate 202. By helping to structurally hold the first integrator 204 and the second integrator 206 together with the substrate 202, the underfill 244 and / or 264 helps to ensure that a strong and reliable electrical connection (e.g., an electrical path) exists between the first integrator 204 and the second integrator 206.

[0022] Various implementations may provide underfill 244 and / or 264 having different materials and / or properties. Underfill 244 and / or 264 may comprise one or more underfills (e.g., underfill layers). For example, underfill 244 and / or 264 may be formed from a single underfill configuration. In some implementations, underfill 244 and / or 264 may correspond to several parts and / or layers of separately formed and cured underfill. In some implementations, underfill 244 and / or 264 may have a viscosity of about 10 to 30 pascal seconds (Pa·s). These viscosity values ​​may be for a temperature of about 80 degrees Celsius. In some implementations, underfill 244 and / or 264 may have a coefficient of thermal expansion (CTE) of about 10 to 15 parts per million (ppm). In some implementation configurations, underfill 244 and / or 264 may contain filler equivalent to approximately 50–90 percent of the weight of underfill 244 and / or 264. As will be further described below, underfill 244 and / or 264 may have capillary properties that allow underfill 244 and / or 264 to fill small spaces between integrated devices and / or between integrated devices and the substrate. For example, the viscosity values ​​described above for underfill 244 and / or underfill 264 allow underfill 244 and / or underfill 264 to readily fill small spaces between integrated devices and / or between integrated devices and the substrate. Underfill 244 and / or underfill 264 and / or other materials that may be installed around pillars and between integrated devices and the substrate are further described below.

[0023] The encapsulation layer 208 is formed by being placed on the substrate 202. The encapsulation layer 208 may include mold, resin, epoxy, and / or polymer. The encapsulation layer 208 may be a means for encapsulation. The encapsulation layer 208 may at least partially encapsulate the first integrated device 204 and / or the second integrated device 206. The encapsulation layer 208 may be placed in a cavity 209 of the substrate 202. The encapsulation layer 208 may at least partially fill the cavity 209 of the substrate 202. Note that even if the entire cavity 209 is filled with the encapsulation layer 208 and / or other material, the substrate 202 may still be considered to have a cavity 209. The encapsulation layer 208 may help to provide structural stability to the package 200.

[0024] An integrated device (e.g., 204, 206) may include a die (e.g., a bare semiconductor die). An integrated device may include logic dies, radio frequency (RF) devices, passive devices, filters, capacitors, inductors, antennas, transmitters, receivers, gallium arsenide (GaAs) based integrated devices, surface acoustic wave (SAW) filters, bulk acoustic wave (BAW) filters, light-emitting diode (LED) integrated devices, silicon (Si) based integrated devices, silicon carbide (SiC) based integrated devices, memory, power management processors (e.g., power management integrated circuits (PMICs)), and / or combinations thereof. An integrated device (e.g., 204, 206) may include at least one electronic circuit (e.g., a first electronic circuit, a second electronic circuit, etc.).

[0025] Figure 3 shows a plan view of a package 200 including multiple wire bonds between integrated devices. The package 200 includes a substrate 202, a cavity 209, a first integrated device 204, a second integrated device 206, and multiple wire bonds 210. The first integrated device 204 and the second integrated device 206 are bonded to the substrate 202. The multiple wire bonds 210 are bonded to the first integrated device 204 and the second integrated device 206. The multiple wire bonds 210 are located on the cavity 209 of the substrate 202. Parts of the first integrated device 204 and / or parts of the second integrated device 206 may be located on the cavity 209 of the substrate 202. As described above, the cavity 209 may be at least partially filled with an encapsulation layer and / or other material.

[0026] Figure 4 shows an enlarged plan view of multiple wire bonds coupled to a pad of an integrated device. As shown in Figure 4, the multiple wire bonds 210 are coupled to a first integrated device 204 and a second integrated device 206. The multiple wire bonds 210 include wire bonds 210a, 210b, 210c, 210d, 210e, and 210f. Wire bonds 210a, 210b, and 210c may be part of a first multiple wire bond. Wire bonds 210d, 210e, and 210f may be part of a second multiple wire bond.

[0027] The first integrated device 204 includes a plurality of pads 241 arranged in a row of pads. The plurality of pads 241 include pads 241a, pads 241b, pads 241c, pads 241d, pads 241e, and pads 241f. Pads 241a, 241b, and 241c may be part of a first row of the plurality of pads relative to the first integrated device 204. Pads 241d, 241e, and 241f may be part of a second row of the plurality of pads relative to the first integrated device 204. The second row of the plurality of pads may be offset from the first row of the plurality of pads of the first integrated device 204, and vice versa. The first row of the plurality of pads may be an internal row of pads. The second row of the plurality of pads may be an external row of pads.

[0028] The second integrated device 206 includes a plurality of pads 261 arranged in a row of pads. The plurality of pads 261 include pads 261a, pads 261b, pads 261c, pads 261d, pads 261e, and pads 261f. Pads 261a, 261b, and 261c may be part of a first row of the plurality of pads for the second integrated device 206. Pads 261d, 261e, and 261f may be part of a second row of the plurality of pads for the second integrated device 206. The second row of the plurality of pads may be offset from the first row of the plurality of pads of the second integrated device 206, and vice versa. The first row of the plurality of pads may be an internal row of pads. The second row of the plurality of pads may be an external row of pads. The internal row and the external row of pads may be arbitrarily defined. For example, the outer rows of pads may be rows of pads closer to the edge of the integrated device (e.g., the edge of an integrated device facing another integrated device) than the inner rows of pads. The inner rows of pads may be rows of pads closer to the center of the integrated device than the outer rows of pads. In some implementations, an integrated device may contain several inner rows of pads.

[0029] A first plurality of wire bonds (including wire bonds 210a, 210b, and 210c) are coupled to (i) a first row of a plurality of pads (including pads 241a, 241b, and 241c) of a first integrated device 204, and to (ii) a first row of a plurality of pads (including pads 261a, 261b, and 261c) of a second integrated device 206.

[0030] The second plurality of wire bonds (including wire bonds 210d, 210e, and 210f) are coupled to (i) a second row of plurality of pads (including pads 241d, 241e, and 241f) of the first integrated device 204, and to (ii) a second row of plurality of pads (including pads 261d, 261e, and 261f) of the second integrated device 206.

[0031] Figure 4 shows two rows of pads for each integrated device. However, various mounting configurations may have different numbers of rows of pads, each coupled to multiple wire bonds. For example, the first integrated device 204 may include a third row of pads offset from the first row of pads, and the second integrated device 206 may include a third row of pads offset from the first row of pads. The third row of pads of the first integrated device 204 and the third row of pads of the second integrated device 206 may be coupled to a third multiple wire bond. The third multiple wire bond may have a different vertical offset from the first multiple wire bond and the second multiple wire bond.

[0032] As will be shown and explained below in at least Figure 6, the first plurality of wire bonds may be offset perpendicularly from the surface of the integrated device (e.g., the maximum vertical offset), unlike the perpendicular offset of the second plurality of wire bonds from the surface of the integrated device.

[0033] The configuration of pads in staggered rows and the use of wire bonds with different vertical offsets help to provide high-density electrical connections between integrated devices. For example, the configuration shown in Figure 4 shows a configuration that can accommodate at least 40 wire bonds per millimeter. Multiple wire bonds 210 may have wire bonds with a minimum diameter of 15 micrometers. In some implementations, the illustrated configuration can accommodate at least 50 wire bonds per millimeter. In some implementations, the illustrated configuration can accommodate between 40 and 60 wire bonds per millimeter (e.g., 40, 41, ... 59, 60 wire bonds per millimeter). The high-density electrical connections provided by multiple wire bonds 210 can help to provide more than 200 channels (e.g., electrical connections) for signal, power, and ground between two integrated devices, each having a minimum length and / or width of approximately 4 millimeters.

[0034] Figure 5 shows a plan view of how wire bonds are bonded to pads of an integrated device. Figure 5 may be an enlarged view of the wire bond connection shown in Figure 4. Wire bond 210a is bonded to pads 241a and pad 261a. Wire bond 210b is bonded to pads 241b and pad 261b. Wire bond 210d is bonded to pads 241d and pad 261d. Wire bond 210a may be partially located above pads 241d and pad 261d. For example, wire bond 210a may overlap pads 241d and pad 261d at least partially vertically. Wire bond 210b may be partially located above pads 241d and pad 261d. For example, wire bond 210b may overlap pads 241d and pad 261d at least partially vertically.

[0035] In some configurations, the first and second rows of pads may have a center-to-center pitch of approximately 61 micrometers (e.g., inter-row pitch (A)). In some configurations, the first row of pads may have a center-to-center pitch (B) of approximately 40.5 micrometers between pads (e.g., between pad 241a and pad 241b). In some configurations, the second row of pads may have a center-to-center pitch (B) of approximately 40.5 micrometers between pads (e.g., between pad 241d and pad 241f). In some configurations, the staggered pitch (C) (e.g., center-to-center pitch between pad 241a and pad 241d) is approximately 20.25 micrometers. However, various configurations may use different dimensions for various pitches.

[0036] Figure 6 shows a side view of how wire bonds are bonded to the pads of the integrated device. Figure 6 shows that different wire bonds may be separately vertically offset (e.g., maximum vertical offset) from the surface of the integrated device. For example, wire bond 210a may be vertically offset (e.g., vertical distance, maximum vertical distance) by about 55 micrometers from the surface of the integrated device (e.g., 204, 206) (E). Other wire bonds from multiple wire bonds 210, such as wire bond 210b and / or wire bond 210c, may be vertically offset by a similar height. In another example, wire bond 210d may be vertically offset (e.g., vertical distance, maximum vertical distance) by about 35 micrometers from the surface of the integrated device (e.g., 204, 206) (D). Other wire bonds from multiple wire bonds 210, such as wire bond 210e and / or wire bond 210f, may be vertically offset by a similar height. The wire bond 210a may be at least partially located above the wire bond 210d. The use of different vertical offsets for different sets of wire bonds helps to provide high-density interconnects between integrated devices by fitting more interconnects per millimeter between them.

[0037] Figure 7 shows a package 700 including multiple wire bonds between integrated devices. Package 700 is similar to package 200 in Figure 2 and therefore contains the same or similar components as package 200. As shown in Figure 7, package 700 includes a substrate 202, a first integrated device 204, a second integrated device 206, multiple wire bonds 210, and an encapsulation layer 708. The encapsulation layer 708 may be the same as, similar to, or different from, the encapsulation layer 208. The encapsulation layer 708 may include mold underfill (MUF). The encapsulation layer 708 may be placed on top of the substrate 202 and in the cavity 209 of the substrate 202. The encapsulation layer 708 may encapsulate the first integrated device 204 and / or the second integrated device 206. The encapsulation layer 708 can encapsulate a plurality of pillar interconnects 240, a plurality of solder interconnects 242, a plurality of pillar interconnects 260, a plurality of solder interconnects 262, and / or a plurality of wire bonds 210.

[0038] Please note that the number of wire bonds shown in Figures 2 to 7 are examples. Various mounting configurations may have different numbers of wire bonds coupled to the integrated device.

[0039] As described above, underfill 244, underfill 264, encapsulation layer 208, and / or encapsulation layer 708 may have certain properties to ensure that the space around the pillar interconnects and the space between the integrated device and the substrate are properly filled to ensure a strong and secure bond between the integrated device and the substrate.

[0040] For example, underfill (e.g., 244, 264) may include capillary underfill having good fluidity. Capillary underfill (CUF) may include a polymer composite material of silica particles and epoxy liquid. One property of capillary underfill is its good fluidity when heated, and therefore, capillary underfill can flow into the narrow space between the integrated device and the substrate, which is driven by capillary force. Capillary underfill may have sufficient silica filler to obtain a final cured material with a low CTE. Capillary underfill is usually a liquid type that freezes below -40 degrees Celsius and can be thawed and heated before application.

[0041] The encapsulation layer 208 may contain encapsulation material and / or epoxy molding compound (EMC) used to cover the entire package after capillary underfill application, and therefore the encapsulation layer can protect the entire package. The encapsulation layer 208 may contain solid pellets that can be stored at room temperature. The encapsulation layer 208 may be heated to a liquid state and processed under a transfer molding flow to cover the integrated device.

[0042] In some implementation configurations, molded underfill (MUF) may be used instead of, or in combination with, underfill (e.g., 244, 264) and / or encapsulation layer 208. Molded underfill may be a combination of capillary underfill (e.g., underfill 244) and EMC (e.g., encapsulation layer 208). The material properties and application formats of molded underfill are the same as or similar to those of ordinary EMC, but it has a much finer filler size, and therefore molded underfill can be pressed into the gaps of the substrate within the integrated device during the transfer molding process. In this way, molded underfill can replace capillary underfill and reduce process steps.

[0043] EMC and MUF can have very high filler content of up to 90 wt, and therefore, their cured material properties are better than capillary underfills, which have lower CTE and higher elasticity. In some packaging configurations, MUF can be used to replace CUF when the package requires an encapsulation layer. For packages without an encapsulation layer, only CUF may be used. Table 1 below shows exemplary properties of various materials, underfills, and encapsulation layers. Note that the values ​​for materials are examples only. Different materials may have different properties. Furthermore, the values ​​shown in Table 1 are not limiting.

[0044] [Table 1]

[0045] Note that the encapsulation layer 708 may be applicable to package 200 in Figure 2, or any package described herein. Similarly, note that the encapsulation layer 208 may be applicable to package 700 in Figure 7, or any package described herein. Note that the encapsulation layers (e.g., 208, 708) may be formed by one or more encapsulation layers. Note that each integrated device may include additional electrical paths between itself and / or between each and the substrate 202. Note that the electrical signal paths that may be shown and / or described herein are illustrative and / or conceptual. Various implementation configurations may use different paths for electrical signals. Furthermore, electrical signals and / or electrical paths may travel through various types of interconnects (e.g., vias, traces, pads, pillars), solder interconnects, and / or components (e.g., passive devices). Therefore, for example, in some implementations, an electrical signal traveling between one integrated device and another may travel through at least one intervening component (e.g., a passive device, a capacitor) between the integrated devices. The paths shown and / or described for electrical signals may also apply to power and / or ground. It should also be noted that two or more wire bonds may be used to facilitate bypassing the substrate. Multiple wire bonds may be used to facilitate electrical coupling between three or more integrated devices. For example, a first integrated device may be configured to be electrically coupled to a second integrated device through a first set of wire bonds. A first integrated device may be configured to be electrically coupled to a third integrated device through a second set of wire bonds. The terms “first surface” and “second surface” of the substrate are arbitrary and may mean any surface of the substrate. For example, the first surface of the substrate may be the bottom surface of the substrate, and the second surface of the substrate may be the top surface of the substrate. In another example, the first surface of the substrate may be the top surface of the substrate, and the second surface of the substrate may be the bottom surface of the substrate.

[0046] Exemplary sequence for manufacturing an integrated device having pillar interconnects Figures 8A and 8B show exemplary sequences for providing or manufacturing an integrated device having pillar interconnects. In some implementations, the sequences in Figures 8A and 8B may be used to provide or manufacture the integrated device of Figure 2 (e.g., 204, 206) or any of the integrated devices described herein.

[0047] Note that, in order to simplify and / or clarify the sequence for providing or manufacturing an integrated device, the sequences in Figures 8A and 8B may be a combination of one or more stages. In some implementations, the order of the processes may be changed or modified. In some implementations, one or more of the processes may be replaced or substituted without departing from the scope of this disclosure. Various implementations may each manufacture the integrated device differently.

[0048] As shown in Figure 8A, Stage 1 represents the state after the integrated device 204 has been prepared. The integrated device 204 may include a die (e.g., a bare semiconductor die). The integrated device 204 may include a substrate (e.g., a silicon substrate) and a plurality of transistors (e.g., active devices). The integrated device 204 may include a plurality of pads 241.

[0049] Stage 2 shows the state after the seed layer 811 has been formed on the front surface of the integrated device 204. The seed layer 811 may include a metal layer. The seed layer 811 can be deposited on the integrated device 204. A plating process may be used to form the seed layer 811.

[0050] Stage 3 shows the state after the photoresist layer 800 has been formed on the seed layer 811. The photoresist layer 800 can be deposited on the seed layer 811.

[0051] Stage 4 shows the state after the photoresist layer 800 has been patterned and at least one opening 801 has been created within the photoresist layer 800 that exposes a portion of the seed layer 811.

[0052] As shown in Figure 8B, Stage 5 shows the state after multiple pillar interconnects 830 and multiple solder interconnects 832 have been formed on the seed layer 811 through openings 801 in the photoresist layer 800. Multiple pillar interconnects 830 may be formed on the seed layer 811 through a plating process. Multiple solder interconnects 832 may be formed on the multiple pillar interconnects 830 through a deposition process.

[0053] Stage 6 shows the state after the photoresist layer 800 has been removed and a portion of the seed layer 811 has been removed (e.g., etched). Removing the photoresist layer 800 may include removing the photoresist layer 800.

[0054] Stage 7 shows the state after a reflow soldering process in which multiple solder interconnects 832 are coupled (e.g., joined) to multiple pillar interconnects 830. Stage 7 may show an integrated device (e.g., 204, 206) having pillar interconnects that can be coupled to a substrate. Multiple pillar interconnects 830 may represent multiple pillar interconnects 240. Multiple solder interconnects 832 may represent multiple solder interconnects 242. The seed layer 811 may be considered part of the pillar interconnects 830.

[0055] Exemplary flowchart of a method for manufacturing an integrated device including pillar interconnects. In some implementations, manufacturing an integrated device having pillar interconnects involves several processes. Figure 9 shows an exemplary flowchart of Method 900 for providing or manufacturing an integrated device having pillar interconnects. In some implementations, Method 900 of Figure 9 may be used to provide or manufacture the integrated devices of Figure 2 described herein (e.g., 204, 206). However, Method 900 may be used to provide or manufacture any and / or one of the multiple integrated devices described herein.

[0056] It should be noted that the method in Figure 9 may combine one or more processes to simplify and / or clarify a method for providing or manufacturing an integrated device having pillar interconnects. In some implementations, the order of the processes may be changed or modified.

[0057] The method involves providing an integrated device (e.g., 204, 206) (in 905). Stage 1 in Figure 8A shows and describes the first integrated device 204 that is provided. The first integrated device 204 may include a die having an active device such as a transistor. The integrated device may include a plurality of pads.

[0058] The method involves forming a seed layer (e.g., 811) on the front surface of the integrated device (at 910). The seed layer 811 may include a metal layer. The seed layer 811 can be deposited on the integrated device 204. A plating process may be used to form the seed layer 811. Stage 2 in Figure 8A illustrates an example of forming the seed layer.

[0059] The method involves forming a photoresist layer (e.g., 800) on a seed layer (e.g., 811) (in 915). The photoresist layer 800 may be formed and patterned on the seed layer 811. The photoresist layer 800 may be deposited and patterned on the seed layer 811 to create at least one opening 801 in the photoresist layer 800 that exposes a portion of the seed layer 811. Stages 3-4 in Figure 8A illustrate an example of forming and patterning a photoresist layer on a seed layer.

[0060] The method involves forming multiple pillar interconnects (e.g., 830) and / or solder interconnects (e.g., 832) on a seed layer (e.g., 811) through an opening 801 in a photoresist layer (e.g., 800) (in 920). Multiple solder interconnects may be formed on the seed layer through a deposition process. Multiple pillar interconnects may be formed on the seed layer through a plating process. Multiple solder interconnects may be formed on the multiple pillar interconnects through a deposition process. Stage 5 in Figure 8B illustrates an example of forming multiple pillar interconnects and / or multiple solder interconnects.

[0061] The method involves removing the photoresist layer (e.g., 800) (in 925). Removing the photoresist layer may include removing the photoresist layer. Stage 6 in Figure 8B shows an example of removing the photoresist layer. In some implementation configurations, a portion of the seed layer 811 may also be removed (in 925). An etching process may be used to remove a portion of the seed layer. Stage 6 in Figure 8B shows and / or illustrates an example of a portion of the seed layer to be removed. Note that forming the photoresist layer, pillar interconnects and / or solder interconnects, and removing the photoresist layer may be repeated, as described in 915, 920 and 925.

[0062] The method involves performing a reflow soldering process (in 930) to join (e.g., bond) multiple solder interconnects (e.g., 832) to multiple pillar interconnects (e.g., 830). Stage 7 in Figure 8B illustrates an example of the reflow soldering process.

[0063] In some implementations, the integrated device is part of a wafer, and unification may be performed to cut the wafer into individual integrated devices. Method 900 may be used to manufacture any integrated device described herein.

[0064] Exemplary sequence for manufacturing a substrate In some packaging configurations, manufacturing a substrate involves several processes. Figures 10A to 10C show exemplary sequences for providing or manufacturing a substrate. In some packaging configurations, the sequences in Figures 10A to 10C may be used to provide or manufacture the substrate 202 of Figure 2. However, the processes in Figures 10A to 10C may be used to manufacture any of the substrates described in this disclosure.

[0065] Note that, in order to simplify and / or clarify the sequence for providing or manufacturing the substrate, the sequences in Figures 10A to 10C may be a combination of one or more stages. In some implementations, the order of the processes may be changed or modified. In some implementations, one or more of the processes may be replaced or substituted without departing from the scope of this disclosure.

[0066] As shown in Figure 10A, Stage 1 shows the state after the carrier 1000 has been prepared and the metal layer has been formed on the carrier 1000. The metal layer may be patterned to form interconnects 1002. Plating and etching processes may be used to form the metal layer and interconnects.

[0067] Stage 2 shows the state after the dielectric layer 1020 has been formed on the carrier 1000 and the interconnect 1002. The dielectric layer 1020 may contain polyimide. However, different packaging configurations may use different materials for the dielectric layer.

[0068] Stage 3 shows the state after multiple cavities 1010 have been formed within the dielectric layer 1020. The multiple cavities 1010 may be formed using an etching process (e.g., a photoetching process) or a laser process.

[0069] Stage 4 shows the state after the interconnect 1012 has been formed in and on the dielectric layer 1020, including in and on the multiple cavities 1010. For example, vias, pads, and / or traces may be formed. A plating process may be used to form the interconnect.

[0070] Stage 5 shows the state after another dielectric layer 1022 has been formed on dielectric layer 1020. Dielectric layer 1022 may be made of the same material as dielectric layer 1020. However, different mounting configurations may use different materials for each dielectric layer.

[0071] Stage 6 shows the state after multiple cavities 1030 have been formed within the dielectric layer 1022, as shown in Figure 10B. An etching process or a laser process may be used to form the cavities 1030.

[0072] Stage 7 shows the state after the interconnect 1014 has been formed in and on the dielectric layer 1022, including in and on a plurality of cavities 1030. For example, vias, pads and / or traces may be formed. A plating process may be used to form the interconnect.

[0073] Stage 8 shows the state after another dielectric layer 1024 has been formed on dielectric layer 1022. Dielectric layer 1024 may be made of the same material as dielectric layer 1020. However, different mounting configurations may use different materials for each dielectric layer.

[0074] Stage 9 shows the state after multiple cavities 1040 have been formed within the dielectric layer 1024. An etching process or a laser process may be used to form the cavities 1040.

[0075] As shown in Figure 10C, Stage 10 shows the state after the interconnect 1016 has been formed in and on the dielectric layer 1024, including in and on a plurality of cavities 1040. For example, vias, pads and / or traces may be formed. A plating process may be used to form the interconnect.

[0076] Some or all of the interconnection portions 1002, 1012, 1014 and / or 1016 may define a plurality of interconnection portions 222 of the substrate 202. Dielectric layers 1020, 1022, and 1024 may be represented by at least one dielectric layer 220.

[0077] Stage 11 shows the state after the carrier 1000 has been decoupled from the dielectric layer 220 (e.g., removed by polishing) and separated from the substrate 202 which includes at least one dielectric layer 220 and a plurality of interconnections 222.

[0078] Stage 12 shows the state after the first solder resist layer 224 and the second solder resist layer 226 have been formed on the substrate 202. A deposition process may be used to form the first solder resist layer 224 and the second solder resist layer 226.

[0079] Various mounting configurations may use different processes to form the metal layer. In some mounting configurations, chemical vapor deposition (CVD) and / or physical vapor deposition (PVD) processes may be used to form the metal layer. For example, sputtering, spray painting, and / or plating processes may be used to form the metal layer.

[0080] Illustrative flowchart of a method for manufacturing a circuit board In some implementations, manufacturing a substrate involves several processes. Figure 11 shows an exemplary flowchart of method 1100 for providing or manufacturing a substrate. In some implementations, method 1100 of Figure 11 may be used to provide or manufacture the substrate shown in Figure 2. For example, the method of Figure 11 may be used to manufacture substrate 202.

[0081] It should be noted that the method in Figure 11 may combine one or more processes to simplify and / or clarify the method for providing or manufacturing a substrate. In some implementation configurations, the order of the processes may be changed or modified.

[0082] The method involves preparing carrier 1000 (in 1105). Various mounting configurations may use different materials for the carrier. The carrier may include substrate, glass, quartz, and / or carrier tape. Stage 1 in Figure 10A illustrates an example of a prepared carrier.

[0083] The method involves forming a metal layer on a carrier 1000 (in 1110). The metal layer may be patterned to form interconnects. A plating process may be used to form the metal layer and interconnects. In some configurations, the carrier may include a metal layer. The metal layer on the carrier may be patterned to form interconnects (e.g., 1002). Stage 1 in Figure 10A illustrates an example of a metal layer and interconnects formed on a carrier.

[0084] The method involves forming a dielectric layer 1020 on the carrier 1000 and interconnect 1002 (in 1115). The dielectric layer 1020 may contain polyimide. Forming the dielectric layer may also involve forming a plurality of cavities (e.g., 1010) within the dielectric layer 1020. The plurality of cavities may be formed using an etching process (e.g., photoetching) or a laser process. Stages 2-3 of Figure 10A illustrate an example of forming the dielectric layer and the cavities within the dielectric layer.

[0085] The method involves forming interconnects in and on the dielectric layer (in 1120). For example, interconnect 1012 may be formed in and on the dielectric layer 1020. A plating process may be used to form the interconnects. Forming interconnects may involve providing a patterned metal layer on and / or in the dielectric layer. Forming interconnects may also involve forming interconnects in cavities within the dielectric layer. Stage 4 in Figure 10A illustrates an example of forming interconnects in and on the dielectric layer.

[0086] The method involves forming a dielectric layer 1020 and a dielectric layer 1022 on top of the interconnect (in 1125). The dielectric layer 1022 may contain polyimide. Forming the dielectric layer may also involve forming a plurality of cavities (e.g., 1030) within the dielectric layer 1022. The plurality of cavities may be formed using an etching process or a laser process. Stages 5 and 6 in Figures 10A and 10B illustrate and / or demonstrate an example of forming the dielectric layer and the cavities within the dielectric layer.

[0087] The method involves forming interconnects in and / or on the dielectric layer (in 1130). For example, interconnect 1014 may be formed. A plating process may be used to form the interconnects. Forming interconnects may include providing patterned metal layers on and within the dielectric layer. Forming interconnects may also include forming interconnects within cavities in the dielectric layer. Stage 7 in Figure 10B illustrates an example of forming interconnects in and on the dielectric layer.

[0088] The method may form additional dielectric layers and additional interconnects, as described in sections 1125 and 1130. Stages 8-10 in Figures 10B-10C show an example of forming interconnects in and on the dielectric layer.

[0089] Once all dielectric layers and additional interconnects are formed, the method may decouple the carriers (e.g., 1000) from the dielectric layer 1020, leaving the substrate (e.g., by removing them or by polishing). In some configurations, the method may form solder resist layers (e.g., 224, 226) on the substrate.

[0090] Various mounting configurations may use different processes to form the metal layer. In some mounting configurations, chemical vapor deposition (CVD) and / or physical vapor deposition (PVD) processes may be used to form the metal layer. For example, sputtering, spray painting, and / or plating processes may be used to form the metal layer.

[0091] Exemplary sequence for manufacturing a package including wire bonds coupled to an integrated device Figures 12A–12B show exemplary sequences for providing or manufacturing a package including a wire bond coupled to an integrated device. In some implementations, the sequences in Figures 12A–12B may be used to provide or manufacture a package 200 including a substrate 202 and a wire bond coupled to the integrated device of Figure 2, or any of the packages described herein.

[0092] Note that the sequences in Figures 12A–12B may be combinations of one or more stages in order to simplify and / or clarify the sequence for providing or manufacturing a package. In some implementations, the order of the processes may be changed or modified. In some implementations, one or more of the processes may be replaced or substituted without departing from the scope of this disclosure. The sequences in Figures 12A–12B may be used to manufacture one package or several packages simultaneously (as part of a wafer).

[0093] As shown in Figure 12A, Stage 1 shows the state after the substrate 202 has been prepared. The substrate 202 may be provided by a supplier or manufactured. Processes similar to those shown in Figures 10A to 10C may be used to manufacture the substrate 202. However, different mounting configurations may use different processes to manufacture the substrate 202. Examples of processes that may be used to manufacture the substrate 202 include semi-additive processes (SAP) and modified semi-additive processes (mSAP). The substrate 202 includes at least one dielectric layer 220 and a plurality of interconnection parts 222. The substrate 202 may be a laminated substrate, a coreless substrate, an organic substrate, or a substrate with a core layer. In some mounting configurations, at least one dielectric layer 220 may include a core layer and / or a prepreg layer. The substrate 202 includes cavities 209. The cavities 209 may be manufactured using a laser process (e.g., laser cutting). The cavity 209 may be formed after the substrate 202 is manufactured and / or supplied. In some mounting configurations, the substrate 202 is provided with the cavity 209.

[0094] Stage 2 shows the state after the integrated devices 204 and 206 have been bonded to a first surface (e.g., the top surface) of the substrate 202. Integrated device 204 is bonded to the substrate 202 through a plurality of pillar interconnects 240 and / or a plurality of solder interconnects 242. Integrated device 206 is bonded to the substrate 202 through a plurality of pillar interconnects 260 and / or a plurality of solder interconnects 262. Parts of integrated device 204 and parts of integrated device 206 may be located above the cavity 209. Integrated device 204 may be bonded to the substrate 202 such that its front surface (e.g., the active surface) faces the substrate 202. Similarly, integrated device 206 may be bonded to the substrate 202 such that its front surface faces the substrate 202.

[0095] Stage 3 shows the state after underfill 244 is provided (e.g., formed) between the substrate 202 and the integrated device 204, and underfill 264 is provided (e.g., formed) between the substrate 202 and the integrated device 206. The underfill (e.g., 244, 264) may be provided around pillar interconnects (e.g., 240, 260) and / or solder interconnects (e.g., 242, 262) via capillary action and / or capillary force. The capillary properties of the underfill allow it to fill small spaces and / or small gaps between the integrated device and the substrate.

[0096] As shown in Figure 12B, Stage 4 shows the state after the multiple wire bonds 210 have been coupled to the first integrated device 204 and the second integrated device 206. For example, the multiple wire bonds 210 may be formed between the first integrated device 204 and the second integrated device 206. The multiple wire bonds 210 may be coupled to multiple pads 241 (of the first integrated device 204) and multiple pads 261 (of the second integrated device 206). The multiple wire bonds 210 may be formed through cavities 209 in the substrate 202. One advantage of forming the multiple wire bonds 210 after the integrated devices have been coupled to the substrate is that, since the integrated devices are fixed relative to each other after being coupled to the substrate, the multiple wire bonds 210 are unlikely to be damaged and / or fail due to movement between the integrated devices. Examples of how the multiple wire bonds 210 are coupled to the integrated devices are shown and illustrated in at least Figures 4 to 6.

[0097] Stage 5 shows the state after the encapsulation layer 208 has been formed on the first surface of the substrate 202 so that the encapsulation layer 208 encapsulates the first integrated device 204 and the second integrated device 206. The encapsulation layer 208 may encapsulate multiple wire bonds 210. The encapsulation layer 208 may at least partially fill cavities 209 in the substrate 202. The process for forming and / or depositing the encapsulation layer 208 may include using a compression and transfer molding process, a sheet molding process, or a liquid molding process. Note that in some implementations, the encapsulation layer 208 may replace underfill (e.g., 244, 264), as shown in Figure 7. Therefore, in some implementations, the encapsulation layer 208 may be formed and placed in the area occupied by the underfill 244 and / or 264.

[0098] Stage 6 shows the state after the multiple solder interconnects 280 have been bonded to the substrate 202. A reflow soldering process may be used to bond the multiple solder interconnects. Stage 8 may show a package 200 including the substrate 202, a first integrated device 204, a second integrated device 206, underfill 244, underfill 264, and encapsulation layer 208, at least as described in Figure 2.

[0099] The packages described in this disclosure (e.g., 200, 700) may be manufactured one at a time, or they may be manufactured together as part of one or more wafers and then unified into individual packages.

[0100] Exemplary flowchart of a method for manufacturing a package containing wire-bonded integrated devices. In some implementations, manufacturing a package that includes wire bonds connecting integrated devices involves several processes. Figure 13 shows an exemplary flowchart of Method 1300 for providing or manufacturing a package that includes wire bonds coupled to integrated devices. In some implementations, Method 1300 of Figure 13 may be used to provide or manufacture the package 200 of Figure 2 described herein. However, Method 1300 may be used to provide or manufacture any of the packages described herein.

[0101] It should be noted that the method in Figure 13 may combine one or more processes to simplify and / or clarify a method for providing or manufacturing a package including wire bonds coupled to an integrated device. In some implementations, the order of the processes may be changed or modified.

[0102] The method involves preparing a substrate (for example, 202) (in 1305). The substrate 202 may be provided by a supplier or manufactured by another supplier. The substrate 202 includes a first surface and a second surface. The substrate 202 includes at least one dielectric layer 220 and a plurality of interconnection parts 222. The substrate 202 may include at least one cavity 209. Various mounting configurations may each have different substrates. Processes similar to those shown in Figures 10A to 10C may be used to manufacture the substrate 202. However, various mounting configurations may each use different processes to manufacture the substrate 202. Stage 1 in Figure 12A illustrates an example of preparing the substrate.

[0103] The method (in 1310) bonds the integrated devices to the substrate. For example, the method may bond integrated devices 204 and 206 to a first surface (e.g., the top surface) of the substrate 202. Integrated device 204 is bonded to the substrate 202 through a plurality of pillar interconnects 240 and / or a plurality of solder interconnects 242. Integrated device 206 is bonded to the substrate 202 through a plurality of pillar interconnects 260 and / or a plurality of solder interconnects 262. Parts of integrated device 204 and parts of integrated device 206 may be located above the cavity 209. Integrated device 204 may be bonded to the substrate 202 such that its front surface (e.g., the active surface) faces the substrate 202. Similarly, integrated device 206 may be bonded to the substrate 202 such that its front surface faces the substrate 202. Stage 2 of Figure 12A illustrates an example of bonding integrated devices to a substrate.

[0104] The method involves forming at least one underfill between the integrated device and the substrate (in 1315). For example, the method may provide an underfill 244 between the substrate 202 and the integrated device 204, or an underfill 264 between the substrate 202 and the integrated device 206. The underfill (e.g., 244, 264) may be provided around pillar interconnects (e.g., 240, 260) and / or solder interconnects (e.g., 242, 262) via capillary action and / or capillary force. The capillary properties of the underfill allow it to fill small spaces and / or small gaps between the integrated device and the substrate. Stage 3 in Figure 12A illustrates an example of preparing the underfill.

[0105] The method involves coupling multiple wire bonds 210 (in 1320) to a first integrated device 204 and a second integrated device 206. The multiple wire bonds 210 may be formed between the first integrated device 204 and the second integrated device 206. The multiple wire bonds 210 are coupled to multiple pads 241 (of the first integrated device 204) and multiple pads 261 (of the second integrated device 206). Examples of how the multiple wire bonds 210 are coupled to the integrated devices are shown and illustrated in at least Figures 4 to 6. Stage 4 in Figure 12B illustrates an example of coupling wire bonds to an integrated device.

[0106] The method may form an encapsulation layer on a substrate (in 1325). For example, the method may form the encapsulation layer 208 on a first surface of a substrate 202 such that the encapsulation layer 208 encapsulates a first integrated device 204 and a second integrated device 206. The encapsulation layer 208 may encapsulate a plurality of wire bonds 210. The encapsulation layer 208 may at least partially fill a cavity 209 in the substrate 202. The process for forming and / or depositing the encapsulation layer 208 may include using a compression and transfer molding process, a sheet molding process, or a liquid molding process. Note that in some packaging configurations, the encapsulation layer 208 may replace underfill (e.g., 244, 264), as shown in Figure 2. Therefore, in some packaging configurations, the encapsulation layer 208 may be formed and placed in an area occupied by underfill. Stage 5 in Figure 12B illustrates an example of forming an encapsulation layer.

[0107] The method involves joining multiple solder interconnects (e.g., 280) to a second surface of a substrate (e.g., 202) (at 1330). A reflow soldering process may be used to join multiple solder interconnects. Stage 6 in Figure 12B illustrates an example of joining solder interconnects to a substrate.

[0108] Exemplary electronic device Figure 14 shows various electronic devices that may be integrated with any of the aforementioned devices, integrated devices, integrated circuit (IC) packages, integrated circuit (IC) devices, semiconductor devices, integrated circuits, dies, interposers, packages, package-on-package (PoP), system-in-package (SiP), or system-on-chip (SoC). For example, a mobile phone device 1402, a laptop computer device 1404, a fixed-location terminal device 1406, a wearable device 1408, or an automobile 1410 may include a device 1400 as described herein. Device 1400 may be, for example, any of the devices and / or integrated circuit (IC) packages described herein. Devices 1402, 1404, 1406, and 1408 and the vehicle 1410 shown in Figure 14 are merely examples. Other electronic devices may also feature device 1400, which includes, but is not limited to, a group of devices (e.g., electronic devices) that include mobile devices, handheld personal communication system (PCS) units, portable data units such as personal digital assistants, GPS-enabled devices, navigation devices, set-top boxes, music players, video players, entertainment units, stationary data units such as meter reading devices, communication devices, smartphones, tablet computers, computers, wearable devices (e.g., watches, glasses), Internet of Things (IoT) devices, servers, routers, electronic devices implemented in automobiles (e.g., autonomous vehicles), or any other devices that store or retrieve data or computer instructions, or any combination thereof.

[0109] One or more of the components, processes, features, and / or functions shown in Figures 2-7, 8A-8B, 9, 10A-10C, 11, 12A-12B, and / or Figures 13-14 may be reconfigured and / or combined into a single component, process, feature, or function, or incorporated into several components, processes, or functions. Additional elements, components, processes, and / or functions may be added without departing from this disclosure. Note that Figures 2-7, 8A-8B, 9, 10A-10C, 11, 12A-12B, and / or Figures 13-14 and their corresponding descriptions in this disclosure are not limited to dies and / or ICs. In some implementations, Figures 2–7, 8A–8B, 9, 10A–10C, 11, 12A–12B, and / or Figures 13–14 and their corresponding descriptions may be used to manufacture, fabricate, provide, and / or produce devices and / or integrated devices. In some implementations, a device may include a die, an integrated device, an integrated passive device (IPD), a die package, an integrated circuit (IC) device, a device package, an integrated circuit (IC) package, a wafer, a semiconductor device, a package-on-package (PoP) device, a heat dissipation device, and / or an interposer.

[0110] It should be noted that the figures in this disclosure may represent actual and / or conceptual representations of various components, elements, objects, devices, packages, integrated devices, integrated circuits, and / or transistors. In some examples, the figures may not be to scale. In some examples, not all elements and / or components may be shown for the sake of simplicity. In some examples, the position, location, size, and / or shape of various components and / or elements in the figures may be illustrative. In some implementations, the various components and / or components in the figures may be arbitrary.

[0111] The term “exemplary” is used herein to mean “acting as an example, case, or illustration.” Any implementation or aspect described herein as “exemplary” should not necessarily be construed as being preferable or advantageous to other aspects of the Disclosure. Similarly, the term “aspect” does not require that all aspects of the Disclosure include the described features, advantages, or modes of operation. The term “coupled” is used herein to mean a direct or indirect coupling (e.g., mechanical coupling) between two objects. For example, if object A is in physical contact with object B, and object B is in contact with object C, objects A and C may still be considered coupled to each other, even if they are not in direct physical contact with each other. The term “electrically coupled” may mean that two objects are directly or indirectly coupled together so that an electric current (e.g., signal, power, ground) can travel between the two objects. Two electrically coupled objects may or may not have an electric current traveling between them. The use of the terms “first,” “second,” “third,” and “fourth” (and / or more than fourth) is arbitrary. Any of the described components may be the first, second, third, or fourth component. For example, a component referred to as the second component may be the first, second, third, or fourth component. The term “encapsulate” means that an object may partially or completely encapsulate another object. The terms “top” and “bottom” are arbitrary. A component placed on top may be placed on top of a component placed on the bottom. A top component may be considered a bottom component, and vice versa. As described in this disclosure, a first component placed “on top” of a second component may mean that the first component is placed above or below the second component, depending on how the bottom or top is arbitrarily defined.In another example, the first component may be positioned over (e.g., above) the first face of the second component, and the third component may be positioned over (e.g., below) the second face of the second component, with the second face facing the first face. It should be further noted that the term “over” as used in this application in the context of one component being positioned over another may be used to mean a component that is positioned on and / or within another component (e.g., on the surface of the component or embedded in the component). Thus, for example, a first component positioned over a second component may mean that (1) the first component is positioned on the second component but is not in direct contact with the second component, (2) the first component is positioned on the second component (e.g., on the surface of the second component), and / or (3) the first component is positioned within the second component (e.g., embedded in the second component). A first component that is placed "in" a second component may be placed partially or entirely within the second component. As used in this disclosure, the terms "about the value of X" or "approximately the value of X" mean within 10 percent of the "value of X". For example, about 1 or approximately 1 means a value within the range of 0.9 to 1.1.

[0112] In some implementations, an interconnect is an element or component of a device or package that enables or facilitates an electrical connection between two points, elements, and / or components. In some implementations, an interconnect may include traces, vias, pads, pillars, metallization layers, redistribution layers, and / or underbump metallization (UBM) layers / interconnectors. In some implementations, an interconnect may include conductive material that may be configured to provide electrical paths for signals (e.g., data signals), ground, and / or power. An interconnect may include two or more elements or components. An interconnect may be defined by one or more interconnects. An interconnect may include one or more metal layers. An interconnect may be part of a circuit. Various implementations may use different processes and / or sequences to form interconnects. In some implementations, chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, spray coating, and / or plating processes may be used to form interconnects.

[0113] Furthermore, note that various disclosures contained herein may be described as processes shown as flowcharts, flow diagrams, structural diagrams, or block diagrams. While flowcharts may describe operations as sequential processes, many operations can be performed in parallel or simultaneously. In addition, the order of operations may be rearranged. A process terminates when its operations are completed.

[0114] The following provides an overview of the aspects of this disclosure.

[0115] Embodiment 1: A package comprising a substrate including a cavity, a first integrated device bonded to the substrate through a first plurality of pillar interconnects and a first plurality of solder interconnects, a second integrated device bonded to the substrate through a second plurality of pillar interconnects and a second plurality of solder interconnects, and a plurality of wire bonds bonded to the first integrated device and the second integrated device, wherein the plurality of wire bonds are located above (e.g., above, below) the cavity of the substrate.

[0116] Embodiment 2: The package of Embodiment 1, wherein the plurality of wire bonds include a first plurality of wire bonds coupled to a first and a second integrated device, and a second plurality of wire bonds coupled to a first and a second integrated device. The second vertical distance between the second plurality of wire bonds and the first integrated device is different from the first vertical distance between the first plurality of wire bonds and the first integrated device. The second plurality of wire bonds may be partially located on top of the first plurality of wire bonds. The vertical distance between the wire bond and the surface of the integrated device and / or the pad of the integrated device may be the vertical perpendicular distance to the surface of the integrated device and / or the pad of the integrated device. The first vertical distance may be a first maximum vertical distance. The second vertical distance may be a second maximum vertical distance.

[0117] Embodiment 3: The package of Embodiments 1 to 2, wherein the first integrated device includes a first row of a plurality of pads and a second row of a plurality of pads, the second integrated device includes a first row of a plurality of pads and a second row of a plurality of pads, and the plurality of wire bonds include a first plurality of wire bonds coupled to (i) the first row of a plurality of pads of the first integrated device and (ii) the first row of a plurality of pads of the second integrated device, and a second plurality of wire bonds coupled to (i) the second row of a plurality of pads of the first integrated device and (ii) the second row of a plurality of pads of the second integrated device.

[0118] Embodiment 4: The package of Embodiment 3, wherein a first row of multiple pads from a first integrated device is offset from a second row of multiple pads from the first integrated device.

[0119] Embodiment 5: The package according to Embodiments 1 to 4, wherein the multiple wire bonds between the first integrated device and the second integrated device have a density of at least 40 wire bonds per millimeter.

[0120] Embodiment 6: The package according to Embodiments 1 to 5, wherein each wire bond from a plurality of wire bonds has a minimum diameter of 15 micrometers.

[0121] Embodiment 7: The package according to Embodiments 1 to 6, further comprising underfill placed between (i) a first integrated device and a substrate, and (ii) between a second integrated device and a substrate. In some packaging configurations, the underfill includes an encapsulation layer.

[0122] Embodiment 8: The package of Embodiment 7, wherein the underfill contains a viscosity of approximately 10 to 30 Pascal seconds (Pa·s).

[0123] Embodiment 9: The underfill is a package of Embodiments 7 to 8, including capillary underfill and / or molded underfill.

[0124] Embodiment 10: The package according to Embodiments 1 to 9, further comprising a substrate, a first integrated device, and an encapsulation layer placed on a second integrated device.

[0125] Embodiment 11: The package of Embodiment 10, wherein the voids in the substrate are at least partially filled with an encapsulation layer. In some mounting configurations, the voids in the substrate are completely filled with an encapsulation layer.

[0126] In some implementation configurations, embodiment 1 may be a package comprising a substrate including a cavity, a first integrated device coupled to the substrate through a first plurality of interconnects, a second integrated device coupled to the substrate through a second plurality of interconnects, and a plurality of wire bonds coupled to the first and second integrated devices, wherein the plurality of wire bonds are located above (e.g., above, below) the cavity in the substrate. The first plurality of interconnects may include a first plurality of solder interconnects. The second plurality of interconnects may include a second plurality of solder interconnects.

[0127] In some implementation configurations, embodiment 1 may be a package comprising a substrate, a first integrated device coupled to the substrate through a first plurality of pillar interconnects and a first plurality of solder interconnects, a second integrated device coupled to the substrate through a second plurality of pillar interconnects and a second plurality of solder interconnects, and a plurality of wire bonds coupled to the first integrated device and the second integrated device.

[0128] Embodiment 12: A device comprising a substrate including a cavity, a first integrated device coupled to the substrate through a first plurality of pillar interconnects and a first plurality of solder interconnects, a second integrated device coupled to the substrate through a second plurality of pillar interconnects and a second plurality of solder interconnects, and means for wire interconnection coupled to the first integrated device and the second integrated device, wherein the means for wire interconnection is located above (e.g., above, below) the cavity of the substrate.

[0129] Embodiment 13: The apparatus of Embodiment 12, wherein the means for wire interconnection includes a first plurality of wire bonds coupled to a first and a second integrated device, and a second plurality of wire bonds coupled to the first and a second integrated device, wherein a second vertical distance between the second plurality of wire bonds and the first integrated device is different from a first vertical distance between the first plurality of wire bonds and the first integrated device. The second plurality of wire bonds may be partially located above the first plurality of wire bonds. The vertical distance between the wire bonds and the surface of the integrated device and / or the pads of the integrated device may be the vertical distance relative to the surface of the integrated device and / or the pads of the integrated device. The first vertical distance may be a first maximum vertical distance. The second vertical distance may be a second maximum vertical distance.

[0130] Embodiment 14: The apparatus of Embodiments 12 to 13, wherein the first integrating device includes a first row of a plurality of pads and a second row of a plurality of pads, the second integrating device includes a first row of a plurality of pads and a second row of a plurality of pads, and the means for wire interconnection includes (i) a first plurality of wire bonds coupled to the first row of a plurality of pads of the first integrating device and (ii) the first row of a plurality of pads of the second integrating device, and (i) a second plurality of wire bonds coupled to the second row of a plurality of pads of the second integrating device.

[0131] Embodiment 15: The apparatus of Embodiment 14, wherein a first row of multiple pads from a first integrated device is offset from a second row of multiple pads from the first integrated device.

[0132] Embodiment 16: The apparatus of Embodiments 12 to 15, wherein the means for wire interconnection between a first integrated device and a second integrated device has a wire bond density of at least 40 wires per millimeter.

[0133] Embodiment 17: The apparatus of Embodiments 12 to 16, wherein each wire bond from the means for wire interconnection has a minimum diameter of 15 micrometers.

[0134] Embodiment 18: The apparatus of Embodiments 12 to 17, further comprising underfill placed between (i) a first integrated device and a substrate, and (ii) between a second integrated device and a substrate. In some mounting configurations, the underfill includes an encapsulation layer.

[0135] Embodiment 19: The apparatus of embodiments 12 to 18, further comprising a substrate, a first integrated device, and means for encapsulation mounted on a second integrated device.

[0136] Embodiment 20: The apparatus of Embodiment 19, wherein the means for encapsulation is further installed in a cavity in the substrate. The cavity in the substrate may be at least partially filled with the means for encapsulation. The cavity in the substrate may be completely filled with the means for encapsulation.

[0137] Embodiment 21: The apparatus according to Embodiments 12 to 20, wherein the apparatus includes devices selected from the group consisting of music players, video players, entertainment units, navigation devices, communication devices, mobile devices, cell phones, smartphones, personal digital assistants, stationary terminals, tablet computers, computers, wearable devices, laptop computers, servers, Internet of Things (IoT) devices, and devices in an automated vehicle.

[0138] In some implementations, embodiment 12 may be an apparatus comprising a substrate including a cavity, a first integrated device coupled to the substrate through a first plurality of interconnections, a second integrated device coupled to the substrate through a second plurality of interconnections, and means for wire interconnections coupled to the first and second integrated devices, wherein the means for wire interconnections are located above (e.g., above, below) the cavity in the substrate. The first plurality of interconnections may include a first plurality of solder interconnections. The second plurality of interconnections may include a second plurality of solder interconnections.

[0139] In some implementations, embodiment 12 may be an apparatus comprising a substrate, a first integrated device coupled to the substrate through a first plurality of pillar interconnects and a first plurality of solder interconnects, a second integrated device coupled to the substrate through a second plurality of pillar interconnects and a second plurality of solder interconnects, and means for wire interconnections coupled to the first integrated device and the second integrated device.

[0140] Embodiment 22: A method for manufacturing a package, comprising the steps of: providing a substrate including a cavity; bonding a first integrated device to the substrate through a first plurality of pillar interconnects and a first plurality of solder interconnects; bonding a second integrated device to the substrate through a second plurality of pillar interconnects and a second plurality of solder interconnects; and forming a plurality of wire bonds between the first integrated device and the second integrated device, wherein the plurality of wire bonds are located above (e.g., above, below) the cavity in the substrate.

[0141] Embodiment 23: The method of Embodiment 22, wherein the step of forming a plurality of wire bonds includes the steps of bonding the first plurality of wire bonds to a first and a second integrated device, and bonding the second plurality of wire bonds to the first and a second integrated device, wherein a second vertical distance between the second plurality of wire bonds and the first integrated device is different from the first vertical distance between the first plurality of wire bonds and the first integrated device. The second plurality of wire bonds may be partially located on top of the first plurality of wire bonds. The vertical distance between the wire bond and the surface of the integrated device and / or the pad of the integrated device may be the vertical distance to the surface of the integrated device and / or the pad of the integrated device. The first vertical distance may be a first maximum vertical distance. The second vertical distance may be a second maximum vertical distance.

[0142] Embodiment 24: The method of Embodiments 22 to 23, wherein the first integrator includes a first row of a plurality of pads and a second row of a plurality of pads, and the second integrator includes a first row of a plurality of pads and a second row of a plurality of pads, and the step of forming a plurality of wire bonds includes (i) bonding a first plurality of wire bonds to the first row of a plurality of pads of the first integrator and (ii) bonding a second plurality of wire bonds to the second row of a plurality of pads of the second integrator and (ii) bonding a second plurality of wire bonds to the second row of a plurality of pads of the second integrator.

[0143] Embodiment 25: The method of Embodiment 24, wherein a first row of multiple pads from a first integrated device is offset from a second row of multiple pads from the first integrated device.

[0144] Embodiment 26: The method according to embodiments 22 to 25, wherein a plurality of wire bonds between a first integrated device and a second integrated device are formed having a density of at least 40 wire bonds per millimeter.

[0145] Embodiment 27: The method of Embodiments 22 to 26, further comprising the step of forming underfill between (i) a first integrated device and a substrate, and (ii) between a second integrated device and a substrate.

[0146] Embodiment 28: The method of embodiments 22 to 27, further comprising the step of forming an encapsulation layer to be placed on a substrate, a first integrated device, and a second integrated device.

[0147] Embodiment 29: The method of Embodiment 28, wherein the encapsulation layer is further formed at least partially within the cavity of the substrate.

[0148] In some implementations, embodiment 22 may be a method for manufacturing a package comprising the steps of providing a substrate including a cavity, bonding a first integrated device to the substrate through a first plurality of interconnects, bonding a second integrated device to the substrate through a second plurality of interconnects, and forming a plurality of wire bonds between the first integrated device and the second integrated device, wherein the plurality of wire bonds are located above (e.g., above, below) the cavity in the substrate. The first plurality of interconnects may include a first plurality of solder interconnects. The second plurality of interconnects may include a second plurality of solder interconnects.

[0149] Various features of the Disclosure described herein can be implemented in different systems without departing from the Disclosure. It should be noted that the above-described aspects of the Disclosure are illustrative and should not be construed as limiting the Disclosure. The descriptions of the aspects of the Disclosure are intended to be illustrative and not to limit the claims. Therefore, the teachings can be readily applied to other types of devices, and many substitutions, modifications, and variations will be apparent to those skilled in the art. [Explanation of Symbols]

[0150] 100 packages 102 circuit boards 104 Integrated Devices 106 Integrated Devices 120 Dielectric layer 122 Interconnection section 124 Solder interconnection 144 Solder interconnection 164 Solder interconnection 200 packages 202 circuit boards 204 First Integrated Device 206 Second Integrated Device 208 Encapsulation layer 209 Cavity 210 Wire Bond 210a Wire Bond 210b Wire Bond 210c Wire Bond 210d Wire Bond 210e Wire Bond 210f Wire Bond 220 Dielectric layer 222 Interconnection section 224 First solder resist layer 226 Second solder resist layer 240 Pillar interconnection section 241 pads 241a pad 241b pad 241c pad 241d pad 241e pad 241f pad 242 Multiple solder interconnections 244 underfill 260 Pillar interconnection section 261 pads 261a Pad 261b Pad 261c pad 261d pad 261e pad 261f pad 262 Multiple solder interconnections 264 underfill 280 Multiple solder interconnections 700 packages 708 Encapsulation layer 800 Photoresist Layers 801 Aperture 811 Seed Layer 830 Multiple pillar interconnections 832 Multiple solder interconnections 900 ways 1000 carriers 1002 Interconnection section 1010 Cavity 1012 Interconnection section 1014 Interconnection section 1016 Interconnection section 1020 Dielectric layer 1022 Dielectric layer 1024 Dielectric layer 1030 Cavity 1040 Cavity 1100 methods 1400 devices 1402 Mobile phone devices 1404 Laptop Computer Devices 1406 Fixed-position terminal device 1408 Wearable Devices 1410 Automated Vehicles

Claims

1. A substrate containing a cavity, A first integrated device coupled to the substrate through a first plurality of pillar interconnects and / or a first plurality of solder interconnects, A second integrated device coupled to the substrate through a second plurality of pillar interconnects and / or a second plurality of solder interconnects, The present invention includes a plurality of parallel wire bonds coupled to the first integrated device and the second integrated device, wherein the plurality of parallel wire bonds are located on the cavity of the substrate. The first integrated device includes a first row of pads and a second row of pads, The second integrated device includes a first row of pads and a second row of pads, The aforementioned plurality of parallel wire bonds are (i) a first row of pads of the first integrated device, and (ii) a first number of wire bonds coupled to the first row of pads of the second integrated device, (i) the second row of pads of the first integrated device, and (ii) a second plurality of wire bonds coupled to the second row of pads of the second integrated device, The first row of pads from the first integrated device is offset from the second row of pads from the first integrated device, The second vertical distance between the second plurality of wire bonds and the first integrated device is smaller than the first vertical distance between the first plurality of wire bonds and the first integrated device. In a plan view, the plurality of parallel wire bonds, the first row and second row of pads of the first integrated device, and the first row and second row of pads of the second integrated device are located within the cavity. package.

2. The package according to claim 1, wherein the plurality of parallel wire bonds between the first integration device and the second integration device have a density of at least 40 wire bonds per millimeter.

3. The package according to claim 1, wherein each wire bond from the plurality of parallel wire bonds has a minimum diameter of 15 micrometers.

4. The package according to claim 1, further comprising (i) underfill installed between the first integrated device and the substrate, and (ii) underfill installed between the second integrated device and the substrate.

5. The package according to claim 4, wherein the underfill includes capillary underfill and / or molded underfill.

6. The package according to claim 1, further comprising the substrate, the first integrated device, and an encapsulation layer placed on the second integrated device.

7. The package according to claim 6, wherein the cavity in the substrate is at least partially filled with the encapsulation layer.

8. The package according to any one of claims 1 to 7, wherein the first row of pads has a center-to-center pitch between pads of 40.5 micrometers, and / or the second row of pads has a center-to-center pitch between pads of 40.5 micrometers, and / or the first row of pads and the second row of pads have a row-to-row pitch of 61 micrometers.

9. Apparatus comprising the package according to any one of claims 1 to 8.

10. A method for manufacturing a package, The steps include providing a substrate that includes a cavity, The steps of bonding a first integrated device to the substrate through a first plurality of pillar interconnects and / or a first plurality of solder interconnects, The steps of bonding a second integrated device to the substrate through a second plurality of pillar interconnects and / or a second plurality of solder interconnects, The process includes the step of forming a plurality of parallel wire bonds between the first integrated device and the second integrated device, wherein the plurality of parallel wire bonds are located on the cavity of the substrate. The first integrated device includes a first row of pads and a second row of pads, The second integrated device includes a first row of pads and a second row of pads, The step of forming the plurality of parallel wire bonds is: (i) bonding a first number of wire bonds to the first row of pads of the first integrated device, and (ii) bonding a first number of wire bonds to the first row of pads of the second integrated device, (i) bonding a second row of pads of the first integrated device, and (ii) bonding a second plurality of wire bonds to the second row of pads of the second integrated device, The first row of pads from the first integrated device is offset from the second row of pads from the first integrated device, The second vertical distance between the second plurality of wire bonds and the first integrated device is smaller than the first vertical distance between the first plurality of wire bonds and the first integrated device. method.

11. The method according to claim 10, wherein the plurality of parallel wire bonds between the first integrated device and the second integrated device are formed having a density of at least 40 wire bonds per millimeter.

12. The method of claim 10, further comprising the step of (i) forming an underfill between the first integrated device and the substrate, and (ii) forming an underfill between the second integrated device and the substrate.

13. The method according to claim 10, further comprising the step of forming an encapsulation layer placed on the substrate, the first integrated device, and the second integrated device.

14. The method according to claim 13, wherein the encapsulation layer is further formed at least partially within the cavity of the substrate.

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