Using different work functions to reduce gate-induced drain leakage current in multilayer nanosheet transistors

Abstract

A transistor device is provided. The transistor device includes a channel stack having stacked and spaced apart channel layers. A first source or drain (S / D) region is communicatively coupled to the channel stack. A tunnel extends through the channel stack, where the tunnel includes a central region and a first set of end regions. The first set of end regions are located closer to the first S / D region than the central region is to the first S / D region. A first type of work function metal (WFM) is formed in the first set of end regions, the first type of WFM having a first work function (WF). A second type of WFM is formed in the central region, the second type of WFM having a second WF, where the first WF is different from the second WF.

Description

Technical Field

[0001] The present invention generally relates to methods of fabricating semiconductor devices and the resulting structures. More specifically, the present invention relates to methods of fabrication and resulting structures for using different work functions to reduce gate-induced drain leakage (GIDL) current in stacked nanosheet transistors.

Background Art

[0002] In modern semiconductor device fabrication processes, a number of metal-oxide-semiconductor field-effect transistors (MOSFETs), such as n-type field-effect transistors (nFETs) and p-type field-effect transistors (pFETs), are fabricated on a single wafer. Non-planar MOSFET architectures (e.g., fin-type FETs (FinFETs) and nanosheet FETs) can increase device density and improve performance compared to planar MOSFETs. For example, in contrast to a conventional planar MOSFET, a nanosheet FET includes a gate stack that surrounds the entire circumference of a plurality of stacked and spaced nanosheet-channel regions for reducing the device footprint and improving control of the flow of channel current.

[0003] GIDL current is undesirable and can occur in MOSFETs due to a high electric field between the gate and the drain. At drain voltages much lower than the junction breakdown voltage, large GIDL currents can be detected in thin gate oxide MOSFETs. The mechanism responsible for GIDL current in MOSFETs can be band-to-band tunneling that can occur at the reversely biased channel-drain interface, as well as at the channel-drain interface located within the gate-to-drain overlap region.

Summary of the Invention

[0004] Embodiments of the present invention relate to a transistor device comprising a channel stack having stacked and spaced channel layers. A first source or drain (S / D) region is coupled to the channel stack so as to communicate with it. A tunnel extends through the channel stack, the tunnel comprising a central region and a first pair of end regions. The first pair of end regions are located closer to the first S / D region than the central region is located relative to the first S / D region. A first type of work function metal (WFM) is formed in the first pair of end regions, and the first type of WFM has a first work function (WF). A second type of WFM is formed in the central region, and the second type of WFM has a second WF, where the first WF is different from the second WF.

[0005] Embodiments of the present invention relate to a method for forming a transistor device, comprising stacking to form a channel stack having spaced channel layers. A first S / D region is formed and coupled to communicate with the channel stack. A tunnel is formed extending through the channel stack, the tunnel comprising a central region and a first pair of end regions. The first pair of end regions is located closer to the first S / D region than the central region is located relative to the first S / D region. A first type of WFM is formed in the first pair of end regions, and the first type of WFM has a first WF. A second type of WFM is formed in the central region, and the second type of WFM has a second WF, where the first WF is different from the second WF.

[0006] Further features and advantages are realized by the technology described herein. Other embodiments and aspects are described in detail herein. For a more detailed understanding, please refer to the specification and drawings.

[0007] The subject matter considered to be embodiments is specifically pointed out and expressly claimed in the concluding claims of this specification. The aforementioned and other features and advantages of these embodiments are evident from the following detailed description, which shall be interpreted in conjunction with the accompanying drawings.

[0008] Figures 1-12 show multiple cross-sectional views of nanosheet-based structures after various fabrication steps for forming a stacked nanosheet transistor having a work function difference to reduce GIDL current, according to an embodiment of the present invention. [Brief explanation of the drawing]

[0009] [Figure 1] Figure 1 is a cross-sectional view of the nanosheet-based structure after the initial fabrication process according to an embodiment of the present invention. [Figure 2] Figure 2 is a cross-sectional view of the nanosheet-based structure after an additional fabrication step according to an embodiment of the present invention. [Figure 3] Figure 3 is a cross-sectional view of the nanosheet-based structure after an additional fabrication step according to an embodiment of the present invention. [Figure 4] Figure 4 is a cross-sectional view of the nanosheet-based structure after an additional fabrication step according to an embodiment of the present invention. [Figure 5] Figure 5 is a cross-sectional view of the nanosheet-based structure after an additional fabrication step according to an embodiment of the present invention. [Figure 6] Figure 6 is a cross-sectional view of the nanosheet-based structure after an additional fabrication step according to an embodiment of the present invention. [Figure 7] Figure 7 is a cross-sectional view of the nanosheet-based structure after an additional fabrication step according to an embodiment of the present invention. [Figure 8] Figure 8 is a cross-sectional view of the nanosheet-based structure after an additional fabrication step according to an embodiment of the present invention. [Figure 9] Figure 9 is a cross-sectional view of the nanosheet-based structure after an additional fabrication step according to an embodiment of the present invention. [Figure 10]Figure 10 is a cross-sectional view of the nanosheet-based structure after an additional fabrication step according to an embodiment of the present invention. [Figure 11] Figure 11 is a cross-sectional view of the nanosheet-based structure after an additional fabrication step according to an embodiment of the present invention. [Figure 12] Figure 12 is a cross-sectional view of the nanosheet-based structure after an additional fabrication step according to an embodiment of the present invention. [Modes for carrying out the invention]

[0010] For the sake of simplicity, prior art relating to the fabrication of semiconductor devices and integrated circuits (ICs) may or may not be described in detail herein. Furthermore, various tasks and process steps described herein can be incorporated into more comprehensive procedures or processes that have additional steps or functions not described in detail herein. In particular, various steps in the fabrication of semiconductor devices and semiconductor-based ICs are well known, and therefore, for the sake of simplicity, many conventional steps are only briefly mentioned herein or are completely omitted without presenting the details of well-known processes.

[0011] Now, moving on to a more specific description of the technology relating to aspects of the present invention, a semiconductor device (e.g., a FET) is formed using an active region of a wafer. The active region is defined by an insulating region used to separate and electrically insulate adjacent semiconductor devices. For example, in an IC having multiple MOSFETs, each MOSFET has a source and a drain, which are formed in the active region of a semiconductor layer by implanting n-type or p-type impurities into a layer of semiconductor material. Between the source and the drain is a channel (or body) region. Above the body region is a gate electrode. The gate electrode and the body are separated by a gate dielectric layer.

[0012] MOSFET-based ICs are fabricated using so-called complementary metal-oxide-semiconductor (CMOS) fabrication technology. Generally, CMOS is a technology that uses complementary and symmetrical pairs of p-type and n-type MOSFETs to implement logic functions. The channel region connects the source and drain, and current flows through the channel region from source to drain. This current flow is induced in the channel region by a voltage applied to the gate electrode.

[0013] The wafer footprint of an FET is related to the electrical conductivity of the channel material. If the channel material has relatively high conductivity, the FET can be fabricated with a correspondingly smaller wafer footprint. One known method to increase channel conductivity and reduce FET size is to form the channel as a nanostructure. For example, the so-called gate-all-around (GAA) nanosheet FET is a known architecture for providing a relatively small FET footprint by forming the channel region as a series of thin nanosheets (e.g., about 3 nm to 8 nm thick). In a known GAA configuration, the nanosheet-based FET includes a source region, a drain region, and a stacked nanosheet channel between the source and drain regions. The gate surrounds the stacked nanosheet channel and regulates the flow of electrons through the nanosheet channel between the source and drain regions.

[0014] GAA nanosheet FETs are fabricated by forming alternating layers of non-sacrificial nanosheets and sacrificial nanosheets. The sacrificial nanosheets are removed from the non-sacrificial nanosheets before the FET device is finished. For n-type FETs, the non-sacrificial nanosheets are typically silicon (Si), and the sacrificial nanosheets are typically silicon-germanium (SiGe). For p-type FETs, the non-sacrificial nanosheets can be SiGe and the sacrificial nanosheets can be Si. In some implementations, the non-sacrificial nanosheets for p-type FETs can be SiGe or Si, and the sacrificial nanosheets can be Si or SiGe. Forming GAA nanosheets from alternating layers of non-sacrificial nanosheets formed from a first type of semiconductor material (e.g., Si for n-type FETs, SiGe for p-type FETs) and sacrificial nanosheets formed from a second type of semiconductor material (e.g., SiGe for n-type FETs, Si for p-type FETs) provides excellent non-sacrificial electrostatic control necessary for continuously scaling gate lengths to 7 nanometer CMOS technology or less. Using multiple layered SiGe / Si sacrificial / non-sacrificial nanosheets (or Si / SiGe sacrificial / non-sacrificial nanosheets) to form the channel region in GAA FET semiconductor devices provides desirable device properties, such as introducing strain at the interface between SiGe and Si.

[0015] While nanosheet channel FET architectures offer higher device density than planar FET architectures, challenges remain when attempting to fabricate nanosheet channel FETs that provide the performance characteristics required for specific applications. For example, as the size of MOSFETs and other devices decreases, the dimensions of the S / D region, channel region, gate electrode, and gate oxide also decrease. As the MOSFET gate oxide becomes thinner and VDD increases (i.e., a higher potential between the gate and drain), the electric field across the gate oxide increases, which in turn increases the GIDL current.

[0016] Next, looking at an overview of the embodiments of the present invention, embodiments of the present invention provide a multilayer nanosheet transistor designed and configured to provide a gate structure formed from a first work function metal (WFM) and a second work function metal (WFM). The first WFM has a first work function (WF), and the second WFM has a second WF. The nanosheet transistor is fabricated according to embodiments of the present invention to have a unique structure that allows the first WFM to be positioned closer to the source or drain (S / D) region than to the S / D region from the second WFM. According to embodiments of the present invention, the first WF is different from the second WF, thereby generating a WF gradient between the central region of the nanosheet channel and either S / D region. This WF gradient relaxes the electric field across the gate oxide, thereby reducing the GIDL current in the multilayer nanosheet transistor.

[0017] In embodiments of the present invention, the space for the first WFM and the second WFM is created by increasing the depth of the recess that houses the internal spacer of the multilayer nanosheet transistor. The increased recess depth allows the nanosheet structure to accommodate a channel trimming process, which during fabrication generates a cavity (or tunnel) defined by the trimmed portion of the channel nanosheet and the portion of the internal spacer. The cavity / tunnel includes an end cavity / tunnel region and a central cavity / tunnel region between the end cavity / tunnel regions. Each end region is located closer to one of the S / D regions than the central region. According to embodiments of the present invention, the first WFM is formed in each end cavity / tunnel region, and the second WFM is formed in the central cavity / tunnel region, thereby creating a WFM difference between the central cavity / tunnel region and either of the end cavity / tunnel regions. This WF difference relaxes the electric field across the gate oxide, thereby reducing the GIDL current in the multilayer nanosheet transistor.

[0018] In an embodiment of the present invention, the first WFM and the second WFM are formed from a combination of materials that provide an appropriate threshold voltage for a stacked nanosheet transistor. At the same time, a WF difference is brought about between either the central cavity / tunnel region and the end cavity / tunnel region, thereby relaxing the electric fields at both ends of the gate oxide, which reduces the GIDL current of the stacked nanosheet transistor. In some embodiments of the present invention, WF is a characteristic of a selected WFM, and the value of the WF of the selected WFM is modulated (increased or decreased) by forming a layer of an oxygen-gettering material on the WFM and is separated from the gate oxide. Generally, a "gettering" or "getter" material is a reactive material that exhibits the property of "acquiring" or removing another material. For example, an oxygen-getter material exhibits the property of binding to nearby oxygen molecules by chemistry or adsorption, thereby removing oxygen from either the environment or another material to which the oxygen-getter material is communicatively bonded. Al is an example of an oxygen-gettering material because it is effective in getting (i.e., reacting and removing) oxygen present in either the environment or another material to which Al is communicatively bonded. By placing an oxygen-gettering material such as aluminum on the WFM, the oxygen-gettering material extracts oxygen from the gate oxide, thereby creating oxygen vacancies in the gate oxide, which reduces the EFW of the selected WFM.

[0019] In some embodiments of the present invention, the nanosheet transistor is an nFET, the first WFM is a tri-layer including an oxygen-gettering (or WF-modulating) layer, and the second WFM is also a tri-layer including an oxygen-gettering (or WF-modulating) layer. The first WFM tri-layer is on the gate oxide and is formed from a layer of TiN with a first thickness (T1), a layer of an Al-containing alloy (e.g., TiAlC), and a layer of TiN. The second WFM tri-layer is on the gate oxide and is formed from a layer of TiN with a second thickness (T2), a layer of an Al-containing alloy (e.g., TiAlC), and a layer of TiN. According to an aspect of the present invention, T1 is relatively thin and T2 is relatively thick, which means T1 < T2. By providing a tri-layer WFM configuration for both the first WFM and the second WFM and maintaining T1 relatively thin and smaller than T2, the oxygen-gettering effect for the first WFM becomes higher than that for the second WFM, and as a result, the threshold voltage near the S / D region becomes lower compared to the central region of the channel. This helps to reduce the GIDL current.

[0020] In some embodiments of the present invention, the nanosheet transistor is a pFET, the first WFM is a WFM without an oxygen-gettering layer, and the second WFM is a tri-layer including an oxygen-gettering layer. The first WFM layer is on the gate oxide and is formed from a layer of TiN. The second WFM tri-layer is on the gate oxide and is formed from a layer of TiN with a third thickness (T3), a layer of an Al-containing alloy (e.g., TiAlC), and a layer of TiN. According to an aspect of the present invention, T3 is relatively thick. In some embodiments of the present invention, T3 > T2 > T1. By providing a tri-layer WFM configuration only for the second WFM and maintaining T3 relatively thicker than T2 and larger than T2, a lower threshold voltage can be obtained near the S / D region compared to the central region on the channel, and at the same time, the threshold voltage of the central region remains acceptable for the pFET device.

[0021] Turning now to a more detailed description of the fabrication process and the resulting structure according to an aspect of the present invention, FIGS. 1-12 illustrate a nanosheet - based structure 100 after various fabrication steps for forming a nanosheet FET having a first WFM closest to the S / D, which is different from the second WFM closest to the channel nanosheet. For ease of illustration, the fabrication steps illustrated in FIGS. 1-12 are described in the context of forming one nanosheet stack 130 (shown in FIG. 1), which is etched into three nanosheet stacks 130 (shown in FIGS. 3-13). However, the fabrication steps described herein are intended to be equally applicable to the fabrication of any number of nanosheet stacks 130.

[0022] Note that although the cross - sectional views illustrated in FIGS. 1-12 are two - dimensional, it is understood that the figures illustrated in FIGS. 1-12 represent three - dimensional structures. To assist in visualizing the three - dimensional features, the top - down reference view 101 shown in FIG. 1 provides a reference point for the various cross - sectional views (X - view, Y1 - view, and Y2 - view) shown in FIGS. 1-12. The X - view is a side view across the three gates, the Y1 - view is an end view through the active gate, and the Y2 - view is an end view through a portion of the nanosheet (NS) stack in which one of the S / D regions is formed (or will be formed).

[0023] Figure 1 shows a cross-sectional view of the nanosheet-based structure 100 after the initial fabrication process according to an embodiment of the present invention. As shown in Figure 1, the nanosheet stack 130 is formed on a substrate 102. The nanosheet stack 130 includes a series of alternating SiGe sacrificial nanosheet layers 120, 122, 124, 126, 127 and Si nanosheet layers 114, 116, 118. According to an embodiment of the present invention, the alternating nanosheet layers 120, 122, 114, 124, 116, 126, 118, 127 of the nanosheet stack 130 are formed by epitaxially growing one nanosheet layer, then the next nanosheet layer, until a desired number and desired thickness of nanosheet layers are achieved. A hard mask layer (not shown) is deposited on alternating nanosheet layers 120, 122, 114, 124, 116, 126, 118, and 127. The hard mask layer and the alternating nanosheet layers 120, 122, 114, 124, 116, 126, 118, and 127 are etched to define the hard mask (HM) 128, the nanosheet stack 130, and the sub-fins 102A of the substrate 102. The hard mask layer and the resulting HM 128 can be any suitable dielectric, including but not limited to SiN.

[0024] In embodiments of the present invention, each of the nanosheet layers 120, 122, 114, 124, 116, 126, 118, and 127 can have a vertical thickness in the range of approximately 5 nm to approximately 20 nm, approximately 10 nm to approximately 15 nm, or approximately 10 nm. Other vertical thicknesses are possible. Eight alternating layers 120, 122, 114, 124, 116, 126, 118, and 127 are shown in the figure, but any number of alternating layers can be provided.

[0025] Epitaxial materials can be grown from gaseous or liquid precursors using, for example, vapor-phase epitaxy (VPE), molecular beam epitaxy (MBE), liquid-phase epitaxy (LPE), or other suitable processes. Epitaxial silicon, silicon-germanium, or carbon-doped silicon (Si:C), or combinations thereof, can be doped in-situ during deposition by adding dopants, n-type dopants (e.g., phosphorus or arsenic), or p-type dopants (e.g., boron or gallium), depending on the type of transistor.

[0026] The terms "epitaxial growth or deposition or both" and "epitaxially formed or grown or both" refer to the growth of a semiconductor material (crystalline material) on a deposition surface of another semiconductor material (crystalline material), in which case the growing semiconductor material (crystalline overlayer) has substantially the same crystalline properties as the semiconductor material (seed material) on the deposition surface. In the epitaxial deposition process, the chemical reactants provided by the source gas are controlled and system parameters are set so that the deposited atoms reach the deposition surface of the semiconductor substrate with enough energy to move around on the surface so that the deposited atoms orient themselves into the crystalline arrangement of atoms on the deposition surface. Therefore, an epitaxially grown semiconductor material has substantially the same crystalline properties as the deposition surface on which the epitaxially grown material is formed. For example, a semiconductor material that is epitaxially grown by deposition on a {100} oriented crystal surface will have a {100} orientation. In some embodiments of the present invention, the epitaxial growth or deposition process, or both, is selective for formation on semiconductor surfaces, and generally, materials are not deposited on amorphous surfaces such as silicon dioxide or silicon nitride.

[0027] In some embodiments of the present invention, the gas source for depositing epitaxial semiconductor materials may be a silicon-containing gas source, a germanium-containing gas source, or a combination thereof. For example, an epitaxial Si layer can be deposited from a silicon gas source selected from the group consisting of silane, disilane, trisilane, tetrasilane, hexachlorodisilane, tetrachlorosilane, dichlorosilane, trichlorosilane, methylsilane, dimethylsilane, ethylsilane, methyldisilane, dimethyldisilane, hexamethyldisilane, and combinations thereof. An epitaxial germanium layer can be deposited from a germanium gas source selected from the group consisting of german, digermane, halogermane, dichlorogermane, trichlorogermane, tetrachlorogermane, and combinations thereof. On the other hand, an epitaxial silicon-germanium alloy layer can be formed using a combination of such gas sources. Carrier gases such as hydrogen, nitrogen, helium, and argon can be used.

[0028] In some embodiments of the present invention, the SiGe sacrificial nanosheet layers 122, 124, 126, and 127 can be approximately 20% SiGe. The notation "20% SiGe" is used to indicate that 20% of the SiGe material is Ge and 80% of the SiGe material is Si. In some embodiments of the present invention, the percentage of Ge in the SiGe sacrificial nanosheet layers 122, 124, 126, and 127 can be any value, including, for example, a value in the range of approximately 20% to approximately 45%.

[0029] In embodiments of the present invention, the SiGe sacrificial nanosheet layer 120 has a Ge percentage that is sufficiently larger than the Ge percentage in the SiGe sacrificial nanosheet layers 122, 124, 126, and 127, providing an etching selectivity between the sacrificial nanosheet layer 120 and the sacrificial nanosheet layers 122, 124, 126, and 127. In some embodiments of the present invention, the Ge percentage in the SiGe sacrificial nanosheet layer 120 is higher than about 55%. In some embodiments of the present invention, the sacrificial nanosheet layers 122, 124, 126, and 127 can be 25% SiGe, and the sacrificial nanosheet layer 120 can be about 55% or more SiGe.

[0030] In Figure 2, known fabrication processes have been used to deposit a thin layer of gate oxide (not shown) onto the nanosheet stack 130 prior to the formation of the dummy gate 204. In Figure 2, the dummy gate 204 represents a combination of a thin layer of gate oxide (e.g., SiO2) and the material from which the dummy gate 204 is formed (e.g., amorphous silicon (a-Si)).

[0031] Referring further to Figure 2, known fabrication processes (e.g., RIE) have been used to form the dummy gate 204. In embodiments of the present invention, the dummy gate 204 can be formed by depositing a layer of dummy gate material (not shown) on top of a gate oxide (not shown apart from the top nanosheet 127) and planarizing it. In some embodiments of the present invention, the dummy gate material can be polycrystalline Si. In some embodiments of the present invention, the dummy gate material can be amorphous Si(a-Si). After deposition, the dummy gate material is planarized to a desired level (e.g., by CMP). A patterned / etched hard mask 206 is formed on the upper surface of the planarized dummy gate material using known semiconductor fabrication processes. In embodiments of the present invention, the hard mask 206 can be formed by depositing a layer of hard mask material, patterning the deposited hard mask layer, and then etching it to form the hard mask 206. The pattern used to form the hard mask 206 defines the footprints of the dummy gate 204 and the gate oxide. In embodiments of the present invention, the hard mask 206 can be formed from an oxide material, a nitride material, or both. The dummy gate material is selectively etched so that portions of the dummy gate material not under the hard mask 206 are selectively removed, thereby forming the dummy gate 204 on the gate oxide and nanosheet stack 130.

[0032] As shown in Figure 2, a known manufacturing process was used to selectively remove the portion of the gate oxide not beneath the dummy gate 204, and DHF (diluted HF) washing was performed to confirm that all of the gate oxide not beneath the dummy gate 204 had been removed.

[0033] Referring further to Figure 2, known fabrication steps were used to selectively remove the bottommost SiGe sacrificial nanosheet layer 120 (shown in Figure 1), and subsequently deposit a dielectric material on the sidewall of the dummy gate 204 to form an offset gate spacer 208. The deposited dielectric material also fills the space occupied by the removed sacrificial nanosheet layer 120, thereby forming a bottom insulating region 202, which insulates the substrate 102 from the active region of the final nanosheet transistor 1200 (shown in Figure 12). In embodiments of the present invention, the offset gate spacer 208 can be formed by depositing a dielectric material on the nanosheet base structure 100, and then performing directional etching on the dielectric material (e.g., using RIE) to form the gate spacer 208. In embodiments of the present invention, the offset gate spacer 208 and the bottom insulating region 202 can be formed from any suitable dielectric material, including, for example, silicon oxide, silicon nitride, silicon oxynitride, SiBCN, SiOCN, SiOC, or any suitable combination of these materials. In some embodiments of the present invention, the offset gate spacer 208 or the bottom insulating region 202, or both, can be made of a low-k dielectric material.

[0034] Referring further to Figure 2, as is most clearly shown in the Y2 view, a shallow trench insulation (STI) region 204 is formed adjacent to the sub-fin 102A. In embodiments of the present invention, the STI region 204 can be formed as an oxide. An exemplary process for forming the STI region 204 includes depositing an STI dielectric material (e.g., an oxide) (not shown) adjacent to the sub-fin 102a, followed by CMP planarization and recessing of the STI dielectric material to form the STI region 204.

[0035] In Figure 3, portions of the nanosheet stack 130 not covered by the gate spacer 208 and dummy gate 204 are etched, thereby forming multiple instances of the nanosheet stack 130, in each instance of the nanosheet stack 130 forming alternating layers of SiGe sacrificial nanosheets 122, 124, 126, 127 and Si nanosheets 114, 116, 118, forming S / D trenches 302, 304, providing access to the edge regions of the SiGe sacrificial nanosheets 122, 124, 126, 127 and the Si nanosheets 114, 116, 118. The rightmost and leftmost nanosheet stacks 130 can each be part of an active or inactive transistor, depending on the requirements of the IC design into which the nanosheet base structure 100 is incorporated. If the rightmost or leftmost nanosheet stack 130, or both, is part of an active transistor, the active transistor formed from the rightmost or leftmost nanosheet stack 130 is in series with the transistor formed from the central nanosheet stack 130 and shares a source or drain region with the transistor formed from the central nanosheet stack 130. Regardless of whether the transistors formed from the rightmost and leftmost nanosheet stacks 130 are active, the rightmost and leftmost nanosheet stacks 130 define portions of the S / D trenches 302, 304, where S / D regions 602, 604 (shown in Figure 6) are formed.

[0036] In Figure 4, known semiconductor fabrication processes were used to partially remove the edge regions of the SiGe sacrificial nanosheets 122, 124, 126, and 127 to form the edge regions or internal spacer cavities 402. In embodiments of the present invention, the edge regions of the SiGe sacrificial nanosheets 122, 124, 126, and 127 can be removed using a so-called "pull-back" process, in which the SiGe sacrificial nanosheets 122, 124, 126, and 127 are pulled back by an initial pull-back distance such that the edges of the SiGe sacrificial nanosheets 122, 124, 126, and 127 terminate well past the inner edge of the gate spacer 208 according to embodiments of the present invention. The pull-back process utilizes the fact that sacrificial nanosheets 122, 124, 126, and 127 are formed from SiGe, which can be selectively etched against Si nanosheets 114, 116, and 118 using, for example, a gas-phase hydrogen chloride (HCl) gas isotropic etching process.

[0037] In Figure 5, a known semiconductor fabrication process (e.g., ALD) was used to conformally deposit a layer of internal spacer liner material 502 on the nanosheet base structure 100. The internal spacer liner layer 502 can be silicon nitride, silicon boron carbonitride, silicon carbonitride, silicon carbon oxynitride, or any other type of dielectric material (e.g., a dielectric material with a dielectric constant k less than about 5). Furthermore, to remove excess dielectric material on the exposed vertical and horizontal surfaces of the nanosheet base structure 100, the internal spacers 502 were formed by applying isotropic etch-back on the internal spacer layer 502, thus leaving a portion of the internal spacer layer 502 sandwiched in the internal spacer cavity 402 (shown in Figure 4), and a known semiconductor device fabrication process was used to form the internal spacers 502.

[0038] In Figure 6, known fabrication processes were used to form doped S / D regions 602, 604 within S / D trenches 302, 304 (shown in Figure 5). In embodiments of the present invention, doped S / D regions 602, 604 can be grown from the exposed edges of Si nanosheets 114, 116, 118 using an epitaxial growth process. In embodiments of the present invention, doped S / D regions 602, 604 can be epitaxially grown from a gaseous or liquid precursor using, for example, gas-phase epitaxy (VPE), molecular beam epitaxy (MBE), liquid-phase epitaxy (LPE), or other suitable processes. In embodiments of the present invention, doped S / D regions 602, 604 can be doped during deposition (e.g., in-situ doping) by adding a dopant such as an n-type dopant (e.g., phosphorus or arsenic) or a p-type dopant (e.g., Ga, B, BF2, or Al) during the above-described method for forming the doped S / D regions 602, 604.

[0039] As shown in Figure 6, known semiconductor device fabrication processes were used to deposit interlayer dielectric (ILD) 610 to fill the remaining open spaces of the nanosheet-based structure 100 and stabilize the nanosheet-based structure 100. The structure 100 is planarized to a predetermined level by removing the hard mask 206 and some portions of the gate spacer 208. In aspects of the present invention, the deposited ILD region 610 can be formed from a low-k dielectric (e.g., k less than about 4) or an ultra-low-k (ULK) dielectric (e.g., k less than about 2.5), or both.

[0040] In Figure 7, known semiconductor fabrication processes were used to remove the sacrificial nanosheets 122, 124, 126, 127 and the dummy gate 204. The dummy gate 204 and the gate dielectric (not shown) can be removed by a suitable known etching process, such as RIE or a wet removal process. Using known semiconductor fabrication processes, the SiGe sacrificial nanosheets 122, 124, 126, 127 can be selectively removed from the Si non-sacrificial nanosheets 114, 116, 118. In embodiments of the present invention, since the sacrificial nanosheets 122, 124, 126, 127 are formed from SiGe, they can be selectively etched from the Si nanosheets 114, 116, 118, for example, using a gas-phase hydrogen chloride (HCl) gas isotropic etching process.

[0041] In Figure 8, known fabrication processes (e.g., wet etching) were used to trim the Si nanosheets 114, 116, and 118 to form a profile that defines the cavity / tunnel 802, defined by the trimmed portions of Si nanosheets 114, 116, and 118 and the portions of the internal spacer 502, according to embodiments of the present invention. According to embodiments of the present invention, the amount of Si trimming is adjusted to have an appropriate overlap between the junction and the gate in the final structure 1200 (shown in Figure 12).

[0042] In Figure 9, a known fabrication process (e.g., ALD deposition) was used to deposit the high-k gate dielectric layer 902. According to embodiments of the present invention, the high-k gate dielectric layer 902 is aligned along the cavity / tunnel 802 and can be a layer of HfO2.

[0043] In Figure 10, known metal deposition and recess processes can be used to deposit the first WFM 1002 in the end region of the cavity 802, leaving the central region of the cavity 802 open. According to an aspect of the present invention, the first WFM 1002 is configured and arranged to provide the first WF. According to an aspect of the present invention, the end region of the cavity 802 is located closer to the S / D regions 602, 604 than the central region of the cavity 802 is located relative to the S / D regions 602, 604, thereby positioning the first WFM 1002 closer to the S / D regions 602, 604 than the central region of the cavity 802 is located relative to the S / D regions 602, 604.

[0044] In Figure 11, known metal deposition processes can be used to deposit a second WFM 1102 in the central region of cavity 802. According to an aspect of the present invention, the second WFM 1102 is arranged to provide a second WF. According to an aspect of the present invention, the central region of cavity 802 is located further away from S / D regions 602, 604 than the end regions of cavity 802 are located away from S / D regions 602, 604, thereby positioning the second WFM 1102 further away from S / D regions 602, 604 than the end regions of cavity 802 are located away from S / D regions 602, 604.

[0045] According to an embodiment of the present invention, the first WFM 1002 has a first WF, and the second WFM 1102 has a second WF. The profile of the cavity / tunnel 802 according to an embodiment of the present invention allows the cavity / tunnel 802 to be positioned closer to the S / D regions 602, 604 than the second WFM 1102 is positioned relative to the S / D regions 602, 604. According to an embodiment of the present invention, the first WF differs from the second WF, which generates a WF gradient between the central region of the cavity / tunnel 802 and the edge regions of the cavity / tunnel 802. This WF gradient relaxes the electric field at both ends of the gate oxide 902, which reduces the GIDL current in the multilayer nanosheet transistor 1200 (shown in Figure 12).

[0046] In embodiments of the present invention, the first WFM 1002 and the second WFM 1102 are formed from a combination of materials that provide an appropriate threshold voltage to the multilayer nanosheet transistor 1200 (shown in Figure 12) and simultaneously provide a WF difference between the central region and the edge region of the cavity 802, thereby mitigating the electric field across the gate oxide 902 and reducing the GIDL current in the multilayer nanosheet transistor 1200. In some embodiments of the present invention, WF is a property of the selected WFM, and the WF value of the selected WFM is modulated (increased or decreased) by layering an oxygen gettering material on the WFM and separating it from the gate oxide. Generally, a “gettering” material or “getter” material is a reactive material that exhibits the property of “acquiring” or removing another material. For example, an oxygen getter material exhibits the property of binding to nearby oxygen molecules chemically or by adsorption, thereby removing oxygen from either the environment or another material to which the oxygen getter material is communicably bound. Al is an example of an oxygen gettering material because it is effective at gettering (i.e., reacting with and removing) oxygen present in either the environment or another material to which Al is communicably bonded. By placing an oxygen gettering material such as aluminum on a WFM, the oxygen gettering material draws oxygen from the gate oxide, creating oxygen vacancies in the gate oxide and reducing the EFW of the selected WFM.

[0047] In some embodiments of the present invention, the nanosheet transistor 1200 (shown in FIG. 12) is an nFET, the first WFM 1002 is a three-layer including an oxygen-gettering (or WF modulation) layer, and the second WFM 1102 is also a three-layer including an oxygen-gettering (or WF modulation) layer. The first WFM 1002 can be a three-layer formed from a layer of TiN having a first thickness (T1), a layer of an Al-containing alloy (e.g., TiAlC), and a layer of TiN. The second WFM 1102 can be a three-layer formed from a layer of TiN having a second thickness (T2), a layer of an Al-containing alloy (e.g., TiAlC), and a layer of TiN. According to an aspect of the present invention, T1 is relatively thin and T2 is relatively thick, which means T1 < T2. By giving both the first WFM 1002 and the second WFM 1102 a three-layer WFM configuration and maintaining T1 relatively thin and less than T2, the oxygen-gettering effect on the first WFM 1002 becomes higher than the oxygen-gettering effect on the second WFM 1102. As a result, the threshold voltage near the S / D regions 602, 604 becomes lower compared to the central region on the channels 114, 116, 118. This helps to reduce the GIDL current.

[0048] In some embodiments of the present invention, the nanosheet transistor 1200 is a pFET, the first WFM 1002 is a WFM without an oxygen-gettering layer, and the second WFM 1102 is a three-layer including an oxygen-gettering layer. The first WFM layer 1002 is formed from a layer of TiN. The second WFM 1102 is a three-layer formed from a layer of TiN having a third thickness (T3), a layer of an Al-containing alloy (e.g., TiAlC), and a layer of TiN. According to an aspect of the present invention, T3 is relatively thick. In some embodiments of the present invention, T3 > T2 > T1. By giving only the second WFM 1002 a three-layer WFM configuration and maintaining T3 relatively thick and greater than T2, it is possible to achieve a lower threshold voltage near the S / D regions 602, 604 compared to the central region on the channels 114, 116, 118, while the threshold voltage of the central region remains acceptable for the pFET device.

[0049] In Figure 12, the completed nanosheet transistor 1200 is formed by depositing a metal gate (MG) 1202. The MG 1202 can be formed using any suitable known fabrication process. The MG 1202, gate dielectric 902, first WFM 1002, and second WFM 1102 form a high-k MG (HKMG) stack structure with a WF gradient according to an aspect of the present invention. The HKMG stack structure surrounds trimmed non-sacrificial nanosheets 114, 116, and 118, respectively, and regulates the flow of electrons through the non-sacrificial nanosheets 114, 116, and 118. The metal gate 1202 structure may include a metal liner. The dielectric layer 902 may include an interface layer (IL) and a high-k dielectric layer. The high-k dielectric layer can be fabricated from, for example, silicon oxide, silicon nitride, silicon oxynitride, boron nitride, a high-k material, or any combination of these materials. Examples of high-k materials, though not limited to these, include metal oxides such as hafnium oxide, hafnium-silicon oxide, hafnium-silicon oxynitride, lanthanum oxide, lanthanum-aluminum oxide, zirconium oxide, zirconium-silicon oxide, zirconium-silicon oxynitride, tantalum oxide, titanium oxide, titanium-barium-strontium oxide, titanium oxide-barium, titanium oxide-strontium, yttrium oxide, aluminum oxide, tantalum-lead-scandium oxide, and zinc-lead niobate. High-k materials may further include dopants such as lanthanum and aluminum.

[0050] The methods described herein and the resulting structures can be used to manufacture IC chips. The resulting IC chips can be shipped by the manufacturer in raw wafer form (i.e., as a single wafer with multiple unpackaged chips), as bare dies, or in packaged form. In the latter case, the chips are mounted in a single-chip package (such as a plastic carrier with lead wires attached to a motherboard or other higher carrier) or in a multi-chip package (such as a ceramic carrier with one or both surface interconnects or embedded interconnects). In either case, the chips are integrated with other chips, discrete circuit elements, or other signal processing devices, or combinations thereof, as part of either (a) an intermediate product such as a motherboard, or (b) a final product. The final product can be any product containing an IC chip, ranging from toys and other low-end applications to displays, keyboards or other input devices, and advanced computer products with a central processor.

[0051] The following definitions and abbreviations are for use in interpreting the claims and specification. Where used herein, the terms “comprises,” “comprising,” “includes,” “including,” “has,” “having,” “contains,” or “containing,” or any other variation thereof, are intended to include non-exclusive inclusion. For example, a composition, mixture, process, method, article, or apparatus including a list of elements is not necessarily limited to those elements alone and may include other elements not expressly enumerated or specific to such composition, mixture, process, method, article, or apparatus.

[0052] The term “exemplary” is used herein to mean “serving as an example, case, or illustration.” Any embodiment or design described herein as “exemplary” should not necessarily be construed as being preferable or advantageous to other embodiments or designs. The terms “at least one” and “one or more” are understood to include any integer greater than or equal to 1, i.e., 1, 2, 3, 4, etc. The term “multiple” is understood to include any integer two or more, i.e., 2, 3, 4, 5, etc. The term “connection” may include indirect “connection” and direct “connection.”

[0053] References to “one embodiment,” “embodiment,” and “exemplary embodiment” in this specification indicate that the described embodiment may include certain features, structures, or characteristics, but not all embodiments may include or may not include certain features, structures, or characteristics. Furthermore, such phrases do not necessarily refer to the same embodiment. In addition, if certain features, structures, or characteristics are described in relation to an embodiment, it is assumed that any influence on such features, structures, or characteristics in relation to other embodiments, whether explicitly stated or not, is within the knowledge of those skilled in the art.

[0054] For the purposes of the following explanation, the terms “top,” “bottom,” “right,” “left,” “vertical,” “horizontal,” “apex,” “bottom,” and their derivatives relate to the structures and methods described so as they are oriented in the drawings. The terms “overlying,” “atop,” “on top,” or “positioned on,” or “positioned atop” mean that a first element, such as a first structure, is located on a second element, such as a second structure, where an intervening element, such as an interface structure, may be located between the first and second elements. The term “direct contact” means that a first element, such as a first structure, and a second element, such as a second structure, are connected at the interface of the two elements without an intermediate conductive, insulating, or semiconductor layer.

[0055] Spatially relative terms, such as “beneath,” “below,” “lower,” “above,” and “upper,” can be used herein to facilitate descriptions of the relationship between one element or feature and another, as illustrated in the figures. It will be understood that spatially relative terms are intended to encompass different orientations of the device in use or operation, in addition to the orientation depicted in the figures. For example, if the device in the figure is turned upside down, an element described as “beneath” or “below” another element or feature will then be oriented “above” that other element or feature. That is, the term “beneath” can encompass both upward and downward orientations. The device may be oriented in other ways (rotated 90 degrees or to other orientations), and the spatially relative descriptors used herein will be interpreted accordingly.

[0056] The terms “about,” “substantially,” “approximately,” and their variations are intended to include a degree of error related to the measurement of a particular quantity, based on the equipment available at the time of filing. For example, “about” may include a range of ±8%, 5%, or 2% of a given value.

[0057] For example, the phrase "selective" in "a first element that is selective to a second element" means that the first element can be etched and the second element can act as an etching stopper.

[0058] The term "conformal" (e.g., conformal layer) means that the thickness of a layer is substantially the same on all surfaces, or that the thickness variation is less than 15% of the nominal thickness of the layer.

[0059] References to terms such as “vertical,” “horizontal,” and “lateral” in this specification are made as examples, not restrictively, to establish a reference frame. Terms such as “horizontal” and “lateral” refer to in-plane directions parallel to the top surface of the semiconductor substrate, regardless of actual three-dimensional spatial orientation. Terms such as “vertical” and “normal” refer to directions perpendicular to “horizontal” and “lateral.”

[0060] As previously stated herein, for the sake of brevity, prior art relating to semiconductor device and IC fabrication may or may not be described in detail herein. However, for background purposes, a more general description of semiconductor device fabrication processes that may be used when carrying out one or more embodiments of the present invention is provided below. While specific fabrication steps used when carrying out one or more embodiments of the present invention may be individually known, the described combinations of steps of the present invention, or the resulting structures, or both, are unique. That is, the unique combinations of steps described in relation to the fabrication of semiconductor devices according to the present invention utilize various individually known physical and chemical processes performed on a semiconductor (e.g., silicon) substrate, some of which are described in the following paragraph.

[0061] Generally, the various processes used to form microchips that are packaged into ICs are classified into four common categories: deposition, removal / etching, semiconductor doping, and patterning / lithography. Deposition is any process of growing, coating, or otherwise transferring material onto a wafer. Available technologies include physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE), and more recently, atomic layer deposition (ALD). Removal / etching is any process of removing material from a wafer. Examples include etching processes (either wet or dry), chemical mechanical planarization (CMP), and others. Reactive ion etching (RIE) is a type of dry etching that removes material, such as masked patterns on semiconductor materials, by exposing the material to ion shocks, for example, using a chemically reactive plasma to move parts of the material away from the exposed surface. Plasma is usually generated by an electromagnetic field under low pressure (vacuum). Semiconductor doping is generally the modification of electrical properties by doping, for example, the source and drain of a transistor, through diffusion, ion implantation, or both. These doping processes are followed by furnace annealing or rapid thermal annealing (RTA). Annealing works to activate the implanted dopants. Films of both conductors (e.g., polysilicon, aluminum, copper, etc.) and insulators (e.g., various forms of silicon dioxide, silicon nitride, etc.) are used to connect and insulate transistors and their components. Selective doping of different areas of a semiconductor substrate allows the conductivity of the substrate to be changed by applying a voltage. By creating the structures of these various components, millions of transistors can be built and wired to form the complex circuits of modern microelectronic devices. Semiconductor lithography is the process of forming a three-dimensional relief image or pattern on a semiconductor substrate for subsequent transfer of the pattern to the substrate. In semiconductor lithography, the pattern is formed by a photosensitive polymer called a photoresist.Multiple lithography and etching pattern transfer steps are repeated to construct the complex structure that makes up the transistor and the numerous wires that connect the millions of transistors in the circuit. Each pattern printed on the wafer is aligned with a previously formed pattern, and slowly, conductive, insulating, and selectively doped regions are built to form the final device.

[0062] The flowcharts and diagrams in the figures illustrate possible implementations of various embodiments of the present invention, including manufacturing methods, operating methods, or both. Various functions / operations of the method are represented by blocks in the flowcharts. In some alternative implementations, the functions described in the blocks may occur in a different order than shown in the diagrams. For example, two consecutively shown blocks may, depending on the functions involved, be executed substantially simultaneously, or the blocks may be executed in reverse order.

[0063] The descriptions of various embodiments of the present invention are presented for illustrative purposes only and are not intended to be exhaustive or limitful to the embodiments described. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the embodiments described. The terms used herein have been selected to best describe the principles of the embodiments, their practical applications to marketable technologies or technical improvements, or to enable those skilled in the art to understand the embodiments described herein.

Claims

1. An integrated circuit (IC) having a transistor device including a first transistor type, wherein the first transistor type is A channel stack comprising stacked and spaced channel layers, wherein a first channel layer of the channel layers comprises a trimmed channel portion, A first source or drain (S / D) region coupled to the channel stack so as to be able to communicate with the channel stack, a tunnel extending through the channel stack, The tunnel is defined by the trimmed channel portion and internal spacers and includes a central region and a first set of end regions. The end region of the first set is located closer to the first S / D region than the central region is located relative to the first S / D region, the tunnel A first type of work function metal (WFM) formed in the end region of the first set, wherein the first type of WFM has a first work function (WF), and A second type of WFM formed in the central region, the second type of WFM having a second WF, the second type of WFM includes The first WF is different from the second WF. Integrated circuit (IC).

2. The IC according to claim 1, further comprising a second S / D region coupled to the channel stack in a manner that enables communication with the channel stack.

3. The tunnel further includes a second set of end regions, The IC according to claim 2, wherein the end region of the second set is located closer to the second S / D region than the central region is located relative to the second S / D region.

4. The IC according to claim 3, wherein the first type of WFM is formed in the end region of the second set.

5. The second channel layer among the stacked and spaced channel layers includes the trimmed channel portion. The IC according to claim 1, wherein the boundary of the tunnel includes the trimmed channel portion of the first channel layer, the internal spacer, and the trimmed channel portion of the second channel layer.

6. The tunnel further includes a gate dielectric, The first type of WFM described above, A first layer of metal of a first thickness, A layer of aluminum alloy, It includes a second layer of metal, The second type of WFM described above is A third layer of metal of the second thickness, A layer of aluminum alloy, It includes a fourth layer of metal, The first thickness is smaller than the second thickness. The IC according to claim 1.

7. An integrated circuit (IC) having transistor devices, including first and second transistor types, The first transistor type described above is A first channel stack, including stacked and spaced channel layers, A first source or drain (S / D) region, coupled to the first channel stack in a manner that allows communication with the first channel stack, A first tunnel extending through the first channel stack, The first tunnel includes a first central region and a first end region, The first end region is located closer to the first S / D region than the first central region is located relative to the first S / D region, the first tunnel The first gate dielectric inside the first tunnel, A first type of work function metal (WFM) formed in the first end region, wherein the first type of WFM has a first work function (WF), and comprises a first layer of metal of first thickness, a layer of aluminum alloy, and a second layer of metal, and A second type of WFM formed in the first central region, wherein the second type of WFM has a second WF different from the first WF, and comprises a third layer of metal of a second thickness, a layer of aluminum alloy, and a fourth layer of metal, wherein the first thickness is smaller than the second thickness. Includes, The second transistor type described above is, A second channel stack, including stacked and spaced channel layers, A second S / D region, coupled to the second channel stack in a manner that allows communication with the second channel stack, A second tunnel extending through the second channel stack, The second tunnel includes a second central region and a second end region. The second end region is located closer to the second S / D region than the second central region is located relative to the second S / D region, the second tunnel The second gate dielectric inside the second tunnel, A third type of work function metal (WFM) formed in the second end region, wherein the third type of WFM has a third work function (WF), and includes a fifth layer of metal, and A fourth type of WFM formed in the second central region, the fourth type of WFM having a second WF and comprising a sixth layer of metal having a third thickness, a layer of aluminum alloy, and a seventh layer of metal, wherein the third thickness is greater than the second thickness, the fourth type of WFM includes IC.

8. A method for forming an integrated circuit (IC) having a transistor device including a first transistor type, the method comprising forming the first transistor type by performing a manufacturing step, the manufacturing step being: Forming a channel stack that includes stacked and spaced-out channel layers. To form a first source or drain (S / D) region that is coupled to the channel stack in a manner that allows communication with it, This involves forming a tunnel that extends through the channel stack, To form a set of internal spacers extending beneath the gate structure of the transistor device, and This includes trimming the first channel layer among the stacked and spaced channel layers, The tunnel is defined by the trimmed portion of the first channel layer and the internal spacer, The tunnel includes a central region and a first set of end regions. The end region of the first set is located closer to the first S / D region than the central region is located relative to the first S / D region, forming the tunnel. Forming a first type of work function metal (WFM) in the end region of the first set, wherein the first type of WFM has a first work function (WF), and The process involves forming a second type of WFM in the central region, wherein the second type of WFM has a second WF, The first WF is different from the second WF. method.

9. The method according to claim 8, further comprising forming a second S / D region coupled to the channel stack in a manner that enables communication with the channel stack.

10. The tunnel further includes a second set of end regions, The method according to claim 9, wherein the end region of the second set is located closer to the second S / D region than the central region is located relative to the second S / D region.

11. The method according to claim 10, wherein the first type of WFM is formed in the end region of the second set.

12. The method further includes trimming a second channel layer among the stacked and spaced channel layers, The method according to claim 8, wherein the boundary of the tunnel includes the trimmed portion of the first channel layer, the internal spacer, and the trimmed portion of the second channel layer.

13. The method further includes forming a gate dielectric within the tunnel, The first type of WFM described above, A first layer of metal having a first thickness, A layer of aluminum alloy, It includes a second layer of metal, The second type of WFM described above is A third layer of metal having a second thickness, A layer of aluminum alloy, It includes a fourth layer of metal, The first thickness is smaller than the second thickness. The method according to claim 8.

14. A method for forming an integrated circuit (IC) having transistor devices, including first and second transistor types, The method includes forming the first transistor type by performing a first manufacturing step, the first manufacturing step being: Forming a first channel stack, which includes stacked and spaced channel layers. To form a first source or drain (S / D) region that is coupled to the first channel stack in a manner that allows communication with it, To form a first tunnel extending through the first channel stack, The first tunnel includes a first central region and a first end region, The first end region forms the first tunnel, which is located closer to the first S / D region than the first central region is located relative to the first S / D region. Forming a first gate dielectric within the first tunnel, By forming a first type of work function metal (WFM) in the first end region, The first type of WFM has a first work function (WF), and the first type of WFM is formed by comprising a first layer of metal having a first thickness, a layer of aluminum alloy, and a second layer of metal. , and The method of forming a second type of WFM in the central region, wherein the second type of WFM has a second WF, and the first WF is different from the second WF, and the second type of WFM includes a third layer of metal having a second thickness, a layer of aluminum alloy, and a fourth layer of metal, wherein the first thickness is smaller than the second thickness. Including, and, The method includes forming the second transistor type by performing a second manufacturing step, the second manufacturing step being: Forming a second channel stack, which includes stacked and spaced-out channel layers. To form a second S / D region that is coupled to the second channel stack in a manner that allows communication with it, Forming a second tunnel that extends through the second channel stack, The second tunnel includes a second central region and a second end region. The second end region forms the second tunnel, which is located closer to the second S / D region than the second central region is located relative to the second S / D region. Forming a second dielectric inside the second tunnel, To form a third type WFM formed in the second end region, wherein the third type WFM has a third work function (WF), and the third type WFM includes a fifth layer of metal, and To form a fourth type WFM in the second central region, wherein the fourth type WFM has a fourth WF, and the fourth type WFM includes a sixth layer of metal having a third thickness, a layer of aluminum alloy, and a seventh layer of metal. The third thickness is greater than the second thickness, forming the fourth type of WFM. Methods that include...

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