Semiconductor equipment

Abstract

To provide a semiconductor device capable of optimizing a PCB layout.SOLUTION: A semiconductor device 1a includes a package 100 having a rectangular shape in plan view, the package 100 having a first side 101, a second side 102, a third side 103, and a fourth side 104, a power supply terminal PVIN1 / 2 provided on the first side 101 or the second side 102, a power ground terminal PGND1 / 2 provided on the first side 101 or the second side 102 or the fourth side 104, a switch output terminal SW1 / 2 provided on the second side 102, an upper switch 11H connected between the power supply terminal PVIN1 / 2 and the switch output terminal SW1 / 2, and a lower switch 11L connected between the switch output terminal SW1 / 2 and the power ground terminal PGND1 / 2. The upper switch 11H, the lower switch 11L, the power supply terminal PVIN1 / 2, and the power ground terminal PGND1 / 2 are provided for each of a plurality of channels.SELECTED DRAWING: Figure 12

Description

Technical Field

[0001] The invention disclosed in this specification relates to a semiconductor device.

Background Art

[0002] Conventionally, various proposals have been made regarding the pin arrangement of semiconductor devices (for example, see Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] However, in order to optimize the PCB [printed circuit board] layout, there was room for further consideration regarding the pin arrangement of the semiconductor device.

[0005] In view of the above problems found by the inventors of the present application, the invention disclosed in this specification aims to provide a semiconductor device capable of optimizing the PCB layout.

Means for Solving the Problems

[0006] A semiconductor device disclosed herein has a configuration (first configuration) comprising: a rectangular package in plan view having a first side, a second side parallel to the first side, a third side perpendicular to the first and second sides, and a fourth side parallel to the third side and perpendicular to the first and second sides; a power supply terminal provided on the first side, or the third side or the fourth side; a power ground terminal provided on the second side, or the third side or the fourth side; a switch output terminal provided on the second side; an upper switch connected between the power supply terminal and the switch output terminal; and a lower switch connected between the switch output terminal and the power ground terminal.

[0007] Furthermore, in the semiconductor device having the first configuration described above, it is preferable that the upper switch, the lower switch, and the switch output terminals are each provided for multiple channels (second configuration).

[0008] Furthermore, in the semiconductor device having the second configuration described above, the switch output terminals provided for each of the multiple channels may be arranged symmetrically between at least two channels (third configuration).

[0009] Furthermore, in a semiconductor device comprising the second or third configuration described above, the power supply terminal and the power ground terminal may be configured such that they are provided for each of the multiple channels (fourth configuration).

[0010] Furthermore, in the semiconductor device comprising the fourth configuration described above, the power supply terminals provided for each of the multiple channels may be arranged symmetrically between at least two channels (fifth configuration).

[0011] Furthermore, in a semiconductor device comprising the fourth or fifth configuration described above, the power ground terminals provided for each of the multiple channels may be arranged symmetrically between at least two channels (sixth configuration).

[0012] Alternatively, in a semiconductor device comprising the second or third configuration described above, at least one of the power supply terminal and the power ground terminal may be shared by the multiple channels (seventh configuration).

[0013] Furthermore, a semiconductor device consisting of any of the above configurations 1 to 7 may be configured to further include a heat dissipation pad exposed on the top surface of the package (configuration 8).

[0014] Furthermore, in a semiconductor device consisting of any of the above configurations 1 to 8, it is preferable to have a configuration (configuration 9) in which the thermal resistance from the semiconductor chip sealed in the package to the top surface is smaller than the thermal resistance from the semiconductor chip to the bottom surface of the package.

[0015] Furthermore, in a semiconductor device comprising any of the above configurations 1 to 9, the upper switch and the lower switch may be arranged in a configuration (10th configuration) that is biased toward the second side when viewed in plan.

[0016] Furthermore, in a semiconductor device comprising any of the above configurations 1 to 10, the upper switch and the lower switch may be arranged in a vertical column along a second direction perpendicular to the first direction in which the first and second sides extend when viewed in plan (configuration 11).

[0017] Furthermore, in a semiconductor device consisting of any of the above configurations 1 to 11, the lower switch may be configured to have a larger element size than the upper switch (configuration 12).

[0018] Furthermore, in a semiconductor device comprising any of the above configurations 1 to 12, the power supply terminal and the power ground terminal are both provided on the third or fourth side, and the power ground terminal is arranged on the second side of the power supply terminal (configuration 13).

[0019] In addition, the semiconductor device having any one of the above-described Configurations 1 to 13 may have a configuration (Configuration 14) including an output feedback control unit that drives the upper switch and the lower switch so that the output current supplied from the switch output terminal to the load matches a predetermined target value.

[0020] In addition, in the semiconductor device having the above-described Configuration 14, the output feedback control unit may have a configuration (Configuration 15) that performs output feedback control in a bottom detection on-time fixed method.

[0021] In addition, the module disclosed in this specification has a configuration (Configuration 16) including a printed circuit board, a semiconductor device having any one of the above-described Configurations 1 to 15, and a load that receives supply of an output current from the semiconductor device.

[0022] In the module having the above-described Configuration 16, the semiconductor device may be mounted on the first main surface of the printed circuit board, and a power supply line connected to the power supply terminal, a power ground line connected to the power ground terminal, and a switch output line connected to the switch output terminal may be laid on the second main surface of the printed circuit board (Configuration 17).

[0023] In the module having the above-described Configuration 17, the main trunk portions of the power supply line and the power ground line may be laid in parallel along the first direction in which the first side and the second side extend in a plan view (Configuration 18).

[0024] In addition, in the module having the above-described Configuration 18, a plurality of the semiconductor devices may be mounted on the first main surface along the first direction (Configuration 19).

[0025] Also, in the module having any one of the configurations from the 17th to the 19th, at least one of the power supply line and the power ground line may be laid so as to overlap the semiconductor device in a plan view (20th configuration).

[0026] Also, in the module having any one of the configurations from the 17th to the 20th, a bypass capacitor may be connected between the power supply line and the power ground line on the second main surface (21st configuration).

[0027] Also, in the module having the 21st configuration, the bypass capacitor may be mounted so as to overlap the semiconductor device in a plan view (22nd configuration).

[0028] Also, in the module having the 21st or 22nd configuration, the bypass capacitor may be mounted at a position where the closed loop formed with the upper switch and the lower switch is minimized (23rd configuration).

[0029] Also, in the module having any one of the configurations from the 16th to the 23rd, the power supply terminals, the switch output terminals, the power ground terminals provided for each of the plurality of channels, and the discrete components externally attached to these are symmetrically arranged between at least two channels (24th configuration).

[0030] Also, the module having any one of the configurations from the 16th to the 24th may further have a heat sink attached to the semiconductor device (25th configuration).

[0031] Also, in the module having the 16th configuration, at least a part of the semiconductor device and the discrete components externally attached thereto may be mounted on the same surface of the printed circuit board (26th configuration).

[0032] Furthermore, the module comprising the 26th configuration described above may also have a configuration (27th configuration) that further includes a heat sink attached in common to both the semiconductor device and the discrete components mounted on the same side of the printed circuit board.

[0033] Furthermore, a module consisting of any of the above configurations 16 to 27 may be configured to further include a boost circuit that generates a boosted voltage from the battery voltage and supplies it to the power supply terminal (configuration 28).

[0034] Furthermore, in a module consisting of any of the above configurations 16 to 28, the load may be configured to be a light-emitting diode (configuration 29). [Effects of the Invention]

[0035] According to the inventions disclosed herein, it is possible to provide a semiconductor device that can optimize PCB layout. [Brief explanation of the drawing]

[0036] [Figure 1] This diagram shows an example of an application for an LED driver IC (2ch). [Figure 2] This diagram shows an example of an application for an LED driver IC (3 channels). [Figure 3] Diagram showing the circuit configuration of the LED driver IC. [Figure 4] This diagram illustrates output feedback control using a bottom detection on-time fixed method. [Figure 5] Diagram for evaluating the power loss of an LED driver IC. [Figure 6] Three-view drawing showing the package of an LED driver IC. [Figure 7] Perspective view showing the package of the LED driver IC. [Figure 8] A perspective view showing an example of a heatsink that can be attached to an LED driver IC. [Figure 9] Diagram for evaluating the thermal resistance of an LED driver IC. [Figure 10A]A diagram showing the pinout (first example) of an LED driver IC (2ch). [Figure 10B] This diagram shows the pinout (second example) of an LED driver IC (2ch). [Figure 11A] This diagram shows the pinout (first example) of an LED driver IC (3 channels). [Figure 11B] This diagram shows the pinout (second example) of an LED driver IC (3ch). [Figure 12] Figure 10A shows the internal structure of the LED driver IC (2ch). [Figure 13A] Figure 11A shows the internal structure of the LED driver IC (3ch). [Figure 13B] Figure 11B shows the internal structure of the LED driver IC (3ch). [Figure 14A] This diagram shows the PCB layout of an LED driver IC (2ch) that employs a synchronous rectification method. [Figure 14B] This diagram shows the PCB layout of an LED driver IC (2ch) that employs a diode rectification method. [Figure 14C] Diagram showing other PCB layouts for an LED driver IC (2ch) employing a synchronous rectification method. [Figure 14D] Diagram showing other PCB layouts for an LED driver IC (2ch) employing a diode rectification method. [Figure 15] Diagram showing the PCB layout of an LED driver IC (3 channels). [Figure 16] Diagram showing closed-loop formation of bypass capacitors. [Figure 17] Diagram showing the vertical arrangement of LED driver ICs (3 channels). [Figure 18] This diagram shows a PCB layout (comparative example) for an LED driver IC (3 channels). [Figure 19] Diagram showing the first modified pin configuration. [Figure 20] A diagram showing a second variation of the pin configuration. [Figure 21] Diagram showing a third variation of the pin configuration. [Figure 22] Diagram showing a fourth variation of the pin configuration. [Figure 23] Diagram showing a modified PCB layout. [Figure 24] Diagram showing examples of QFP adoption. [Figure 25] This diagram shows a PCB layout with an LED driver IC (3-channel) and discrete components mounted on the same side. [Figure 26] Figure 25 shows the α-β cross-section. [Modes for carrying out the invention]

[0037] <LED[light emitting diode]ドライバIC> Figure 1 shows an example configuration of an LED lamp module to which a 2-channel LED driver IC is applied. The LED lamp module X in this example configuration includes a 2-channel LED driver IC 1a, a boost circuit 2, an MCU [micro control unit] 3, light-emitting diodes LED1 and LED2 (in this figure, an LED string in which multiple light-emitting diode elements are connected in series), and various discrete components (capacitors C1 and C2, capacitors C11 to C13, capacitors C21 to C23, inductors L1 and L2, resistors R1 and R2, and sense resistors Rs1 and Rs2).

[0038] The LED driver IC1a is a semiconductor device that supplies power to light-emitting diodes LED1 and LED2 by stepping down a boosted voltage Vbst. The LED driver IC1a has multiple external terminals (VIN pin, VREG5 pin, GND pin, TON pin, SO pin, CSB pin, SCK pin, SI pin, PVIN1 pin, BOOT1 pin, SW1 pin, PGND1 pin, SNSP1 pin, SNSN1 pin, PVIN2 pin, BOOT2 pin, SW2 pin, PGND2 pin, SNSP2 pin, and SNSN2 pin) as means of establishing an electrical connection with the outside of the IC.

[0039] The VIN pin is the input voltage supply terminal for the signal system. The VREG5 pin is the output terminal for the internal regulator. The GND pin is the ground terminal for the signal system. The TON pin is the resistor connection terminal for setting the on-time. The SO pin is the serial data output terminal for SPI (serial peripheral interface) communication. The CSB pin is the chip select input terminal for SPI communication. The SCK pin is the serial clock input terminal for SPI communication. The SI pin is the serial data input terminal for SPI communication.

[0040] PVIN1 and PVIN2 are power supply terminals (power terminals) for the power system input voltage. BOOT1 and BOOT2 are bootstrap capacitor connection terminals for driving the upper gate. SW1 and SW2 are switch output terminals. PGND1 and PGND2 are power ground terminals (power ground terminals). SNSP1 and SNSP2 are output current sense input terminals (+). SNSN1 and SNSN2 are output current sense input terminals (-).

[0041] Note that the external terminals with a "1" at the end of their designation (PVIN1, SW1, PGND1, SNSP1, and SNSN1) are all for the first channel. On the other hand, the external terminals with a "2" at the end of their designation (PVIN2, SW2, PGND2, SNSP2, and SNSN2) are all for the second channel.

[0042] The VIN pin is connected to the battery voltage +B (e.g., 13V) application terminal. The GND pin is connected to the ground terminal. Capacitor C1 (=input smoothing capacitor) is connected between the VIN pin and the GND pin. Capacitor C2 (=output smoothing capacitor of the internal regulator) is connected between the VREG5 pin and the GND pin. Resistor R1 (=on-time setting resistor) is connected between the TON pin and the ground terminal. Resistor R2 (=pull-up resistor) is connected between the SO pin and the power supply voltage Vcc (e.g., 5V) application terminal. The SO pin, CSB pin, SCK pin, and SI pin are each connected to the MCU3.

[0043] The PVIN1 pin is connected to the application terminal of the boost voltage Vbst (e.g., 65V). The SW1 pin is connected to the first terminal of inductor L1. The second terminal of inductor L1 is connected to the first terminal of sense resistor Rs1. The second terminal of sense resistor Rs1 is connected to the anode of light-emitting diode LED1. The cathode of light-emitting diode LED1 is connected to the ground terminal. A capacitor C11 (bypass capacitor) is connected between the PVIN1 pin and the PGND1 pin. A capacitor C12 (bootstrap capacitor) is connected between the BOOT1 pin and the SW1 pin. A capacitor C13 (output smoothing capacitor) is connected between the anode of light-emitting diode LED1 and the ground terminal. The ends of the sense resistor Rs1 are connected to the SNSP1 pin and SNSN1 pin, respectively.

[0044] The PVIN2 pin is connected to the application terminal of the boost voltage Vbst. The SW2 pin is connected to the first terminal of inductor L2. The second terminal of inductor L2 is connected to the first terminal of sense resistor Rs2. The second terminal of sense resistor Rs2 is connected to the anode of light-emitting diode LED2. The cathode of light-emitting diode LED2 is connected to ground. A capacitor C21 (bypass capacitor) is connected between the PVIN2 pin and the PGND2 pin. A capacitor C22 (bootstrap capacitor) is connected between the BOOT2 pin and the SW2 pin. A capacitor C23 (output smoothing capacitor) is connected between the anode of light-emitting diode LED2 and ground. The ends of the sense resistor Rs2 are connected to the SNSP2 pin and SNSN2 pin, respectively.

[0045] Boost circuit 2 is a DC / DC converter that boosts the battery voltage +B to generate a boosted voltage Vbst.

[0046] The MCU3 operates on the power supply voltage Vcc and communicates with the LED driver IC1a via SPI.

[0047] Figure 2 shows an example configuration of an LED lamp module to which a 3-channel LED driver IC is applied. The LED lamp module X in this example configuration is based on Figure 1, but has a 3-channel LED driver IC 1b instead of a 2-channel LED driver IC 1a.

[0048] Furthermore, due to its three-channel design, the LED driver IC1b is equipped with a set of external terminals for the third channel (PVIN3 pin, BOOT3 pin, SW3 pin, PGND3 pin, SNSP3 pin, and SNSN3 pin) in addition to the previously mentioned external terminals.

[0049] In addition to the aforementioned components, the LED lamp module X is also equipped with a light-emitting diode LED3 for the third channel and various discrete components (capacitors C31-C33, inductor L3, and sense resistor Rs3).

[0050] PVIN3 is the power input voltage supply terminal (=power supply terminal). BOOT3 is the bootstrap capacitor connection terminal for driving the upper gate. SW3 is the switch output terminal. PGND3 is the power ground terminal (=power ground terminal). SNSP3 is the output current sense input terminal (+). SNSN3 is the output current sense input terminal (-).

[0051] The PVIN3 pin is connected to the application terminal of the boost voltage Vbst. The SW3 pin is connected to the first terminal of inductor L3. The second terminal of inductor L3 is connected to the first terminal of sense resistor Rs3. The second terminal of sense resistor Rs3 is connected to the anode of light-emitting diode LED3. The cathode of light-emitting diode LED3 is connected to ground. A capacitor C31 (bypass capacitor) is connected between the PVIN3 pin and the PGND3 pin. A capacitor C32 (bootstrap capacitor) is connected between the BOOT3 pin and the SW3 pin. A capacitor C33 (output smoothing capacitor) is connected between the anode of light-emitting diode LED3 and ground. The ends of the sense resistor Rs3 are connected to the SNSP3 pin and SNSN3 pin, respectively.

[0052] In the following, when it is not necessary to distinguish between LED driver IC1a and 1b, they may simply be referred to as LED driver IC1.

[0053] <Circuit Configuration> Figure 3 shows the circuit configuration of the LED driver IC1 (especially around the output stage). In this example configuration, the LED driver IC1 integrates an upper switch 11H, a lower switch 11L, an upper driver 12H, a lower driver 12L, a controller 13, an on-time setting unit 14, a slope voltage generation unit 15, a sense amplifier 16, an error amplifier 17, a comparator 18, and a bootstrap diode D1 as means for driving the light-emitting diode LED* of the *th channel (where *=1, 2, or 3). Of course, the LED driver IC1 may also integrate other components (such as various protection circuits).

[0054] The upper switch 11H is connected between the PVIN pin and the SW* pin and is switched on / off according to the upper gate signal GH. An NMOSFET (N-channel type metal oxide semiconductor field effect transistor) is preferably used as the upper switch 11H. In that case, the upper switch 11H turns on when GH=H (=BOOT*) and turns off when GH=L (=SW*). It is also possible to use a PMOSFET (P-channel type MOSFET) instead of an NMOSFET as the upper switch 11H. In that case, the bootstrap diode D1, capacitor C*2, and the BOOT* pin become unnecessary.

[0055] The lower switch 11L is connected between the SW* pin and the PGND* pin and is switched on / off according to the lower gate signal GL. An NMOSFET or similar is preferably used as the lower switch 11L. In that case, the lower switch 11L turns on when GL=H (=VDRV5) and turns off when GL=L (=PGND*).

[0056] The upper switch 11H and lower switch 11L, connected in this manner, form a half-bridge output stage that outputs a rectangular wave switch voltage Vsw from the SW* pin. Note that while this diagram shows a synchronous rectification half-bridge output stage, if a diode rectification method is used, a diode can be used as the lower switch 11L.

[0057] The upper driver 12H generates the upper gate signal GH based on the upper control signal SH input from the controller 13. The high level of the upper gate signal GH corresponds to the terminal voltage of the BOOT* pin (≒Vsw+VDRV5). Conversely, the low level of the upper gate signal GH corresponds to the terminal voltage of the SW* pin (≒Vsw).

[0058] The lower driver 12L generates the lower gate signal GL based on the lower control signal SL input from the controller 13. The high level of the lower gate signal GL corresponds to the constant voltage VDRV5 (internal power supply voltage VREG or a separate external input voltage). On the other hand, the low level of the lower gate signal GL corresponds to the terminal voltage of the PGND* pin (ground voltage).

[0059] The controller 13 includes, for example, an RS flip-flop that accepts the inputs of a set signal SET and a reset signal RST, and generates an upper control signal SH and a lower control signal SL to complementaryally turn the upper switch 11H and the lower switch 11L on and off.

[0060] More specifically, the controller 13 generates an upper control signal SH and a lower control signal SL such that it turns on the upper switch 11H and turns off the lower switch 11L at the rising edge of the set signal SET, while turning off the upper switch 11H and turning on the lower switch 11L at the rising edge of the reset signal RST.

[0061] However, the term "complementary" in this specification should be understood in a broad sense, including not only cases where the on / off states of the upper switch 11H and the lower switch 11L are completely reversed, but also cases where a simultaneous off period (so-called dead time) is provided to prevent through-current.

[0062] The on-time setting unit 14 raises the reset signal RST to a high level when a predetermined on-time Ton has elapsed from the rising edge timing of the set signal SET (and consequently the on-time of the upper switch 11H). The on-time setting unit 14 also has a function to arbitrarily set the on-time Ton according to the resistance value of resistor R1 connected to the TON pin. Furthermore, the on-time setting unit 14 also has a function to vary the on-time Ton to suppress fluctuations in the switching frequency Fsw based on the terminal voltages of the PVIN pin and SNSN pin, respectively.

[0063] The slope voltage generation unit 15 detects the inductor current IL that flows during the ON period of the lower switch 11L and generates a slope voltage Vslp that includes information about the inductor current IL. The slope voltage Vslp increases as the inductor current IL that flows during the ON period of the lower switch 11L increases, and decreases as the inductor current IL decreases.

[0064] The sense amplifier 16 amplifies the terminal voltage between the SNSP* pin and the SNSN* pin (= the voltage across the sense resistor Rs*) to generate the sense voltage Vs. The sense voltage Vs increases as the output current ILED (= average inductor current IL_ave) flowing through the sense resistor Rs* increases, and decreases as the output current ILED decreases.

[0065] The error amplifier 17 outputs a current according to the difference between the reference voltage VISET (= analog dimming voltage) input to the non-inverting input terminal (+) and the sense voltage Vs input to the inverting input terminal (-) (more precisely, the sum voltage of the offset voltage Vofs and the sense voltage Vs), and generates the control voltage Vc by charging and discharging a capacitor (not shown). Note that the control voltage Vc rises when VISET > Vs and falls when VISET < Vs.

[0066] The comparator 18 generates a set signal SET by comparing the slope voltage Vslp input to the inverting input terminal (-) and the control voltage Vc input to the non-inverting input terminal (+). The set signal SET becomes low level when Vc < Vslp and high level when Vc > Vslp. Therefore, the lower the control voltage Vc, the later the rising timing of the set signal SET (and thus the on-timing of the upper switch 11H), and conversely, the higher the control voltage Vc, the earlier the rising timing of the set signal SET.

[0067] Among the above components, the upper driver 12H, the lower driver 12L, the controller 13, the on-time setting unit 14, the slope voltage generation unit 15, the sense amplifier 16, the error amplifier 17, and the comparator 18 function as an output feedback control unit of the bottom detection on-time fixed method, and the upper switch 11H and the lower switch 11L are driven complementarily so that the output current ILED supplied from the switch output terminal SW* to the light-emitting diode LED* matches a predetermined target value.

[0068] <Output Feedback Control> Figure 4 is a diagram showing the output feedback control of the bottom detection on-time fixed method, and the inductor current IL and the switch voltage Vsw are depicted in order from the top.

[0069] While the upper switch 11H is off and the lower switch 11L is on, the switch voltage Vsw is at a low level (= negative voltage VDSW generated between the drain and source of the lower switch 11L). At this time, the inductor current IL flowing from the PGND* pin through the lower switch 11L to the SW* pin decreases as the energy of the inductor L* is released.

[0070] Then, when the inductor current IL decreases to the bottom value IL_btm corresponding to the control voltage Vc, Vc > Vslp, and the set signal SET rises to a high level. As a result, the upper switch 11H turns on and the lower switch 11L turns off. At this time, the switch voltage Vsw becomes high level (≒PVIN), so the inductor current IL flowing from the PVIN pin through the upper switch 11H to the SW* pin increases.

[0071] Subsequently, after a predetermined on-time Ton has elapsed, the reset signal RST rises to a high level, the upper switch 11H turns off and the lower switch 11L turns on, causing the inductor current IL to change from increasing to decreasing again. As a result, the inductor current IL becomes a ripple waveform that repeatedly increases and decreases between a peak value IL_pk and a bottom value IL_btm.

[0072] Here, the bottom value of the inductor current IL, IL_btm, varies according to the difference between the sense voltage Vs (=equivalent to the average inductor current IL_ave) and the reference voltage VISET (=equivalent to the target value of the average inductor current IL_ave). Also, the ripple amplitude ΔIL (=IL_pk - IL_btm) of the inductor current IL is determined according to the on-time Ton.

[0073] Therefore, as the above series of operations are repeated, the LED driver IC1 performs bottom detection on-time fixed output feedback control so that the average inductor current IL_ave (and consequently the output current ILED) matches a predetermined target value.

[0074] However, the output feedback control method for the LED driver IC1 is not necessarily limited to the above. For example, instead of the bottom detection on-time fixed method, a peak detection off-time fixed method may be adopted, or a hysteresis window method may be adopted. Alternatively, a PWM (pulse width modulation) control method may also be adopted.

[0075] <Power loss> Figure 5 is a diagram for evaluating the power loss of the LED driver IC1. The upper part of the figure shows the switch current Isw and switch voltage Vsw, while the lower part shows the power loss Psw (= Isw × Vsw).

[0076] As shown in this figure, when the LED driver IC1 drives the upper switch 11H and the lower switch 11L complementaryly, a switching loss Psw_loss (=Vbst×ILED / 2+(Tsw_on+Tsw_off)×Fsw) and a conduction loss Pcon_loss (=ILED×ILED×Fsw×(RonH×Ton+RonL×Toff)) occur.

[0077] In particular, when the boost voltage Vbst is several tens of volts (e.g., 65V) and the switching frequency Fsw is several MHz (e.g., 2.2MHz), the power loss of the LED driver IC1 (=Psw_loss + Pcon_loss) becomes large, and consequently, the heat generated by the LED driver IC1 increases. Therefore, the package of the LED driver IC1 requires high heat dissipation capabilities.

[0078] <Package> Figures 6 and 7 are orthographic views (top, front, and side) and perspective views, respectively, of the package of the LED driver IC1. The package 100 illustrated here is a 48-pin HTSSOP (heat-sink thin-shrink small outline package) and is formed in a rectangular shape in plan view, with the first side 101, the second side 102, the third side 103, and the fourth side 104.

[0079] The first side 101 corresponds to the first long side (for example, 12.5 mm) and is provided with a total of 24 external terminals. In Figure 6, pins 1 to 24 are arranged sequentially from the left end to the right end of the first side 101.

[0080] The second side 102 corresponds to the second longer side parallel to the first side 101, and, like the first side 101, is provided with a total of 24 external terminals. In Figure 6, pins 25 to 48 are arranged sequentially from the right end to the left end of the second side 102.

[0081] The third side 103 corresponds to the first short side (e.g., 6.1 mm) that is perpendicular to the first side 101 and the second side 102. Note that the third side 103 does not have any external terminals.

[0082] The fourth side 104 corresponds to a second short side that runs parallel to the third side 103 and perpendicular to the first and second sides 102. Note that no external terminals are provided on the fourth side 104.

[0083] The 48 external terminals are each led outward from the long side of the package 100 (corresponding to the first side 101 and the second side 102 in a plan view). Furthermore, each external terminal has a shape that is bent midway, creating a step between the base and the tip when viewed from the side of the package 100 (a so-called gull-wing shape).

[0084] Furthermore, a heat dissipation pad 111 and a 1-pin mark 112 are formed on the top surface 110 of the package 100 (corresponding to the first main surface that does not face the printed circuit board). On the other hand, nothing is formed on the bottom surface 120 of the package 100 (corresponding to the second main surface that faces the printed circuit board).

[0085] The heat dissipation pad 111 exposes the back surface of the island on which the semiconductor chip is mounted to the top surface 110 of the package 100. The size of the heat dissipation pad 111 should be such that the length of the long side (the length of one side parallel to the long side of the package 100) is about 0.4 times the length of the first side 101 and the second side 102 (for example, 5 mm), and the length of the short side (the length of one side parallel to the short side of the package 100) is about 0.7 times the length of the third side 103 and the fourth side 104 (for example, 4.2 mm).

[0086] By providing such a heat dissipation pad 111, it is possible to improve the heat dissipation performance of the package 100. In particular, if the heat dissipation pad 111 is exposed on the top surface 110 of the package 100 rather than the bottom surface 120 of the package 100, a heat sink can be attached to the heat dissipation pad 111, which further improves the heat dissipation performance of the package 100.

[0087] Figure 8 is a perspective view showing an example of a heatsink attached to the LED driver IC1. The heatsink 200 in this example configuration has a base portion 210 (e.g., 60 mm x 50 mm) and a plurality of heat dissipation fins 220 (e.g., 50 mm x 50 mm).

[0088] Multiple heat dissipation fins 220 are provided on the top surface of the base portion 210 (corresponding to the first main surface that does not face the package 100 of the LED driver IC 1). This configuration increases the surface area of ​​the heat sink 200, thereby improving the heat dissipation of the package 100. The base portion 210 and the heat dissipation fins 220 may be formed integrally or individually and then assembled.

[0089] When attaching the heatsink 200 to the LED driver IC1, it is recommended to apply thermal grease 230 to the bottom surface of the base portion 210 (corresponding to the second main surface facing the package 100 of the LED driver IC1) and then attach it to the package 100 of the LED driver IC1 (especially the heat dissipation pad 111).

[0090] Figure 9 is a schematic longitudinal cross-sectional view for evaluating the thermal resistance of the LED driver IC 1. As shown in this figure, in the LED driver IC 1 in which a heat dissipation pad 111 is exposed on the top surface 110 of the package 100, the thermal resistance θ1 from the semiconductor chip 130 sealed in the package 100 to the top surface 110 is extremely small compared to the thermal resistance θ2 from the semiconductor chip 130 to the bottom surface 120 (θ1 << θ2, for example, θ1 = 3°C / W, θ2 = 100°C / W). Therefore, heat can be quickly dissipated from the heat dissipation pad 111 (and furthermore, the heat sink 200 attached thereto), making it possible to increase the maximum allowable power dissipation of the LED driver IC 1.

[0091] <Pin assignment> Next, we propose a novel pin configuration for the LED driver IC1 described above that can optimize the PCB layout.

[0092] Figure 10A is a plan view showing the pin configuration (first example) of the LED driver IC 1a (2ch). Note that the dashed lines in the figure are auxiliary lines to schematically illustrate the connection relationship between the power supply terminals (PVIN1, PVIN2), power ground terminals (PGND1, PGND2), and switch output terminals (SW1, SW2) and the upper switch 11H and lower switch 11L, and do not represent the actual wiring pattern or element formation pattern.

[0093] Furthermore, in the following explanation, in a plan view of package 100, the first direction in which the first side 101 and the second side 102 extend is called the x-direction (the vertical direction of the paper in this figure), and the second direction perpendicular to this (= the direction in which the third side 103 and the fourth side 104 extend) is called the y-direction (the horizontal direction of the paper in this figure).

[0094] Pins 1-3 are assigned to the power supply terminals for the first channel (PVIN1). Pins 5-7 and 9 are assigned to the external terminals for SPI communication (SI, SCK, CSB, SO). Pins 11-13 and 15 are assigned to the external terminals for the signal system (GND, TON, VIN, VREG5). Pins 22-24 are assigned to the power supply terminals for the second channel (PVIN2).

[0095] Pins 25 and 26 are assigned to the output current sense input terminals (SNSN2, SNSP2) for the second channel. Pin 28 is assigned to the bootstrap capacitor connection terminal (BOOT2) for the second channel. Pins 30-32 are assigned to the switch output terminals (SW2) for the second channel. Pins 34-36 are assigned to the power ground terminal (PGND2) for the second channel.

[0096] Pins 37-39 are assigned to the power ground terminal (PGND1) of the first channel. Pins 41-43 are assigned to the switch output terminal (SW1) of the first channel. Pin 45 is assigned to the bootstrap capacitor connection terminal (BOOT1) of the first channel. Pins 47 and 48 are assigned to the output current sense input terminals (SNSN1, SNSP1) of the first channel.

[0097] As described above, in the LED driver IC1a of this configuration example, the power supply terminals (PVIN1, PVIN2) are located on the first side 101 (left side in this figure) of the package 100. On the other hand, the power ground terminals (PGND1, PGND2) and the switch output terminals (SW1, SW2) are located on the second side 102 (right side in this figure) of the package 100.

[0098] Figure 10B is a plan view showing the pin configuration (second example) of the LED driver IC 1a (2ch). Note that the dashed lines in the figure are auxiliary lines to schematically illustrate the connection relationship between the power supply terminals (PVIN1, PVIN2), power ground terminals (PGND1, PGND2), and switch output terminals (SW1, SW2) and the upper switch 11H and lower switch 11L, and do not represent the actual wiring pattern or element formation pattern.

[0099] Pins 1 and 2 are assigned to the output current sense input terminals (SNSN1, SNSP1) of the first channel. Pins 3, 4, and 15 are assigned to the power ground terminal (PGND1) of the first channel. Pins 6 and 7 are assigned to the switch output terminal (SW1) of the first channel. Pin 8 is assigned to the bootstrap capacitor connection terminal (BOOT1) of the first channel.

[0100] Pins 16, 21, and 22 are assigned to the second channel's power ground terminal (PGND2). Pin 17 is assigned to the second channel's bootstrap capacitor connection terminal (BOOT2). Pins 18 and 19 are assigned to the second channel's switch output terminal (SW2). Pins 23 and 24 are assigned to the second channel's output current sense input terminals (SNSP2, SNSN2).

[0101] Pins 25 and 33 are assigned to the power supply terminals for the second channel (PVIN2). Pins 34 and 48 are assigned to the power supply terminals for the first channel (PVIN1).

[0102] Pins 36-39 are assigned to the external signaling terminals (VIN, TON, 5VREG, and GND). Pins 41-43 and 45 are assigned to the external terminals for SPI communication (SI, SCK, CSB, and SO).

[0103] As can be seen from Figures 10A and 10B, as long as the basic concept of providing power supply terminals (PVIN1, PVIN2) on the first side 101 (left side in this figure) of package 100 and power ground terminals (PGND1, PGND2) and switch output terminals (SW1, SW2) on the second side 102 (right side in this figure) of package 100 is not deviated from, various variations in the pin configuration of the LED driver IC 1a (2ch) can be considered.

[0104] Figure 11A is a plan view showing the pin configuration (first example) of the LED driver IC 1b (3ch). Note that the dashed lines in the figure are auxiliary lines to schematically illustrate the connection relationship between the power supply terminals (PVIN1~PVIN3), power ground terminals (PGND1~PGND3), and switch output terminals (SW1~SW3) and the upper switch 11H and lower switch 11L, and do not represent the actual wiring pattern or element formation pattern.

[0105] Pins 1 and 2 are assigned to the power supply terminals for the first channel (PVIN1). Pins 4-6 and 8 are assigned to the external terminals for SPI communication (SI, SCK, CSB, and SO). Pins 10-13 are assigned to the external terminals for the signal system (VREG5, GND, TON, VIN5). Pins 14 and 15 are assigned to the power supply terminals for the second channel (PVIN2). Pins 23 and 24 are assigned to the power supply terminals for the third channel (PVIN3).

[0106] Pins 25 and 26 are assigned to the switch output terminal (SW3) for the third channel. Pin 27 is assigned to the bootstrap capacitor connection terminal (BOOT3) for the third channel. Pins 28 and 29 are assigned to the power ground terminal (PGND3) for the third channel. Pins 30 and 31 are assigned to the output current sense input terminals (SNSP3, SNSN3) for the third channel.

[0107] Pins 34 and 35 are assigned to the switch output terminal (SW2) for the second channel. Pin 36 is assigned to the bootstrap capacitor connection terminal (BOOT2) for the second channel. Pins 37 and 38 are assigned to the power ground terminal (PGND2) for the second channel. Pins 39 and 40 are assigned to the output current sense input terminals (SNSP2, SNSN2) for the second channel.

[0108] Pins 42 and 43 are assigned to the output current sense input terminals (SNSN1, SNSP1) for the first channel. Pins 44 and 45 are assigned to the power ground terminal (PGND1) for the first channel. Pin 46 is assigned to the bootstrap capacitor connection terminal (BOOT1) for the first channel. Pins 47 and 48 are assigned to the switch output terminal (SW1) for the first channel.

[0109] As described above, in the LED driver IC1b of this configuration example, the power supply terminals (PVIN1~PVIN3) are located on the first side 101 (left side in this figure) of the package 100. On the other hand, the power ground terminals (PGND1~PGND3) and the switch output terminals (SW1~SW3) are located on the second side 102 (right side in this figure) of the package 100.

[0110] Figure 11B is a plan view showing the pin configuration (second example) of the LED driver IC 1b (3ch). Note that the dashed lines in the figure are auxiliary lines to schematically illustrate the connection relationship between the power supply terminals (PVIN1, PVIN2), power ground terminals (PGND1, PGND2), and switch output terminals (SW1~SW3) and the upper switch 11H and lower switch 11L, and do not represent the actual wiring pattern or element formation pattern.

[0111] Pins 1 and 2 are assigned to the output current sense input terminals (SNSN1, SNSP1) of the first channel. Pins 3 and 4 are assigned to the power ground terminal PGND1 of the first channel. Pins 6 and 7 are assigned to the switch output terminal (SW1) of the first channel. Pin 8 is assigned to the bootstrap capacitor connection terminal (BOOT1) of the first channel.

[0112] Pin 10 is assigned to the bootstrap capacitor connection terminal (BOOT3) for the third channel. Pins 11 and 12 are assigned to the switch output terminals (SW3) for the third channel. Pins 13 and 14 are assigned to the output current sense input terminals (SNSP3, SNSN3) for the third channel. Pins 15 and 16 are assigned to the power ground terminal (PGND3) for the third channel.

[0113] Pin 17 is assigned to the bootstrap capacitor connection terminal (BOOT2) for the second channel. Pins 18 and 19 are assigned to the switch output terminals (SW2) for the second channel. Pins 21 and 22 are assigned to the power ground terminals (PGND2) for the second channel. Pins 23 and 24 are assigned to the output current sense input terminals (SNSP2, SNSN2) for the second channel.

[0114] Pin 25 is assigned to the power supply terminal for the second channel (PVIN2). Pins 33 and 34 are assigned to the power supply terminal for the third channel (PVIN3). Pin 48 is assigned to the power supply terminal for the first channel (PVIN1).

[0115] Pins 36-39 are assigned to the external signaling terminals (VIN, TON, 5VREG, and GND). Pins 41-43 and 45 are assigned to the external terminals for SPI communication (SI, SCK, CSB, and SO).

[0116] As can be seen from Figures 11A and 11B, as long as the basic concept of providing the power supply terminals (PVIN1~PVIN3) on the first side 101 (left side in this figure) of package 100 and the power ground terminals (PGND1~PGND3) and switch output terminals (SW1~SW3) on the second side 102 (right side in this figure) of package 100 is not deviated from, various variations in the pin configuration of the LED driver IC1b (3ch) can be considered.

[0117] <Internal structure> Figure 12 is a bottom perspective view (a view of package 100 from the bottom surface 120) showing the internal structure of the LED driver IC 1a (2ch) shown in Figure 10A. Therefore, in this figure, unlike Figure 10A, the first side 101 is the right side and the second side 102 is the left side.

[0118] The semiconductor chip 130, which integrates the upper switch 11H(ch1) and lower switch 11L(ch1) of the first channel, and the upper switch 11H(ch2) and lower switch 11L(ch2) of the second channel, is die-bonded to a rectangular island 140 in plan view. The island 140 is supported inside the package 100 by a support frame 151 extending toward the third side 103 and a support frame 152 extending toward the fourth side 104. The back surface of the island 140 is exposed on the top surface 110 of the package 100 as the heat dissipation pad 111.

[0119] Wire W11 is stretched between the drain pad of the upper switch 11H (ch1) and the three PVIN1 pins. Wire W12 is stretched between the source pad of the upper switch 11H (ch1) and the drain pad of the lower switch 11L (ch1) and the three SW1 pins. Wire W13 is stretched between the source pad of the lower switch 11L (ch1) and the three PGND1 pins.

[0120] Wire W21 is stretched between the drain pad of the upper switch 11H(ch2) and the three PVIN2 pins. Wire W22 is stretched between the source pad of the upper switch 11H(ch2) and the drain pad of the lower switch 11L(ch2) and the three SW2 pins. Wire W23 is stretched between the source pad of the lower switch 11L(ch2) and the three PGND2 pins.

[0121] Note that the lower switch 11L (ch1 / ch2) has a larger element size than the upper switch 11H (ch1 / ch2). With this element design, it is possible to increase the current capacity of the lower switch 11L (ch1 / ch2) compared to that of the upper switch 11H (ch1 / ch2). For example, if you want to maintain a constant output power, the higher the output voltage VLED, the smaller the output current ILED needs to be, and conversely, the lower the output voltage VLED, the larger the output current ILED needs to be. In other words, the lower the on-duty cycle of the half-bridge output stage, the larger the output current ILED needs to be, and therefore the above element design is effective.

[0122] Furthermore, the upper switch 11H(ch1) and the lower switch 11L(ch1), as well as the upper switch 11H(ch2) and the lower switch 11L(ch2), are arranged in a vertical column in the order shown in the figure, along the y-direction perpendicular to the first side 101, in a plan view of the semiconductor chip 130.

[0123] Furthermore, the switch formation regions where the upper switch 11H (ch1 / ch2) and the lower switch 11L (ch1 / ch2) are formed are located towards the second side 102 of the package 100 in a plan view of the semiconductor chip 130.

[0124] Furthermore, the upper switch 11H(ch1) and lower switch 11L(ch1) of the first channel are positioned as close as possible to the third side 103 of the package 100 in a plan view of the semiconductor chip 130, so as close as possible to the external terminals (PVIN1, PGND1, SW1) of the first channel.

[0125] On the other hand, the upper switch 11H(ch2) and lower switch 11L(ch2) of the second channel are positioned as close as possible to the fourth side 104 of the package 100 in a plan view of the semiconductor chip 130, so as close as possible to the external terminals of the second channel (PVIN2, PGND, SW2).

[0126] By adopting this element layout, the lengths of wires W11-W13 and W21-W23 can be minimized, thereby reducing their respective resistance, capacitance, and inductance components as much as possible.

[0127] Figure 13A is a bottom perspective view showing the internal structure of the LED driver IC1b (3ch) shown in Figure 11A. Therefore, unlike Figure 11A, the first side 101 is the right side and the second side 102 is the left side.

[0128] The semiconductor chip 130 integrates the upper switch 11H(ch1) and lower switch 11L(ch1) for the first channel, the upper switch 11H(ch2) and lower switch 11L(ch2) for the second channel, and the upper switch 11H(ch3) and lower switch 11L(ch3) for the third channel.

[0129] Wire W11 is stretched between the drain pad of the upper switch 11H (ch1) and the two PVIN1 pins. Wire W12 is stretched between the source pad of the upper switch 11H (ch1) and the drain pad of the lower switch 11L (ch1) and the two SW1 pins. Wire W13 is stretched between the source pad of the lower switch 11L (ch1) and the two PGND1 pins.

[0130] Wire W21 is stretched between the drain pad of the upper switch 11H(ch2) and the two PVIN2 pins. Wire W22 is stretched between the source pad of the upper switch 11H(ch2) and the drain pad of the lower switch 11L(ch2) and the two SW2 pins. Wire W23 is stretched between the source pad of the lower switch 11L(ch2) and the two PGND2 pins.

[0131] Wire W31 is stretched between the drain pad of the upper switch 11H (ch3) and the two PVIN3 pins. Wire W32 is stretched between the source pad of the upper switch 11H (ch3) and the drain pad of the lower switch 11L (ch3) and the two SW3 pins. Wire W33 is stretched between the source pad of the lower switch 11L (ch3) and the two PGND3 pins.

[0132] Note that the lower switch 11L (ch1 / ch2 / ch3) has a larger element size than the upper switch 11H (ch1 / ch2 / ch3). With this element design, it is possible to increase the current capability of the lower switch 11L (ch1 / ch2 / ch3) compared to that of the upper switch 11H (ch1 / ch2 / ch3). For example, if you want to maintain a constant output power, the higher the output voltage VLED, the smaller the output current ILED needs to be, and conversely, the lower the output voltage VLED, the larger the output current ILED needs to be. In other words, the lower the on-duty cycle of the half-bridge output stage, the larger the output current ILED needs to be, and the above element design is effective.

[0133] Furthermore, the upper switch 11H(ch1) and the lower switch 11L(ch1), the upper switch 11H(ch2) and the lower switch 11L(ch2), and the upper switch 11H(ch3) and the lower switch 11L(ch3) are arranged in a vertical column in the order shown in the figure, along the y-direction perpendicular to the first side 101 in a plan view of the semiconductor chip 130.

[0134] Furthermore, the switch formation regions where the upper switch 11H (ch1 / ch2 / ch3) and the lower switch 11L (ch1 / ch2 / ch3) are formed are located towards the second side 102 of the package 100 in a plan view of the semiconductor chip 130.

[0135] Furthermore, the upper switch 11H(ch1) and lower switch 11L(ch1) of the first channel are positioned as close as possible to the third side 103 of the package 100 in a plan view of the semiconductor chip 130, so as close as possible to the external terminals (PVIN1, PGND1, SW1) of the first channel.

[0136] On the other hand, the upper switch 11H(ch2) and lower switch 11L(ch2) of the second channel are positioned in the center of the y-direction in a plan view of the semiconductor chip 130 so that they are as close as possible to the external terminal group (PVIN2, PGND2, SW2) of the second channel.

[0137] Furthermore, the upper switch 11H(ch3) and lower switch 11L(ch3) of the third channel are positioned as close as possible to the fourth side 104 of the package 100 in a plan view of the semiconductor chip 130, so as close as possible to the external terminals (PVIN3, PGND3, SW3) of the third channel.

[0138] By adopting this element layout, the lengths of wires W11-W13, W21-W23, and W31-W33 can be minimized, thereby reducing their respective resistance, capacitance, and inductance components as much as possible.

[0139] Figure 13B is a bottom perspective view showing the internal structure of the LED driver IC1b (3ch) shown in Figure 11B. Therefore, unlike Figure 11B, the first side 101 is the right side and the second side 102 is the left side.

[0140] The semiconductor chip 130 integrates the upper switch 11H(ch1) and lower switch 11L(ch1) for the first channel, the upper switch 11H(ch2) and lower switch 11L(ch2) for the second channel, and the upper switch 11H(ch3) and lower switch 11L(ch3) for the third channel.

[0141] Wire W11 is stretched between the drain pad of the upper switch 11H (ch1) and the PVIN1 pin. Wire W12 is stretched between the source pad of the upper switch 11H (ch1) and the drain pad of the lower switch 11L (ch1) and the two SW1 pins. Wire W13 is stretched between the source pad of the lower switch 11L (ch1) and the two PGND1 pins.

[0142] Wire W21 is stretched between the drain pad of the upper switch 11H(ch2) and the PVIN2 pin. Wire W22 is stretched between the source pad of the upper switch 11H(ch2) and the drain pad of the lower switch 11L(ch2) and the two SW2 pins, respectively. Wire W23 is stretched between the source pad of the lower switch 11L(ch2) and the two PGND2 pins, respectively.

[0143] Wire W31 is stretched between the drain pad of the upper switch 11H(ch3) and the PVIN3 pin and PVIN3(S) pin, respectively. Wire W31S is stretched between the PVIN3(S) pin and the sub-pad of the semiconductor chip 130. Wire W32 is stretched between the source pad of the upper switch 11H(ch3) and the drain pad of the lower switch 11L(ch3) and the two SW3 pins, respectively. Wire W33 is stretched between the source pad of the lower switch 11L(ch3) and the two PGND3 pins, respectively.

[0144] Note that the lower switch 11L (ch1 / ch2 / ch3) has a larger element size than the upper switch 11H (ch1 / ch2 / ch3). With this element design, it is possible to increase the current capability of the lower switch 11L (ch1 / ch2 / ch3) compared to that of the upper switch 11H (ch1 / ch2 / ch3). For example, if you want to maintain a constant output power, the higher the output voltage VLED, the smaller the output current ILED needs to be, and conversely, the lower the output voltage VLED, the larger the output current ILED needs to be. In other words, the lower the on-duty cycle of the half-bridge output stage, the larger the output current ILED needs to be, and the above element design is effective.

[0145] Furthermore, the upper switch 11H(ch1) and the lower switch 11L(ch1), the upper switch 11H(ch2) and the lower switch 11L(ch2), and the upper switch 11H(ch3) and the lower switch 11L(ch3) are arranged in a vertical column in the order shown in the figure, along the y-direction perpendicular to the first side 101 in a plan view of the semiconductor chip 130.

[0146] Furthermore, the switch formation regions where the upper switch 11H (ch1 / ch2 / ch3) and the lower switch 11L (ch1 / ch2 / ch3) are formed are located towards the first side 101 of the package 100 in a plan view of the semiconductor chip 130. In addition, the logic formation regions where the controller 13 and the like are formed are located towards the second side of the package 100 in a plan view of the semiconductor chip 130.

[0147] Furthermore, the upper switch 11H(ch1) and lower switch 11L(ch1) of the first channel are positioned as close as possible to the third side 103 of the package 100 in a plan view of the semiconductor chip 130, so as close as possible to the external terminals (PVIN1, PGND1, SW1) of the first channel.

[0148] On the other hand, the upper switch 11H(ch2) and lower switch 11L(ch2) of the second channel are positioned as close as possible to the fourth side 104 of the package 100 in a plan view of the semiconductor chip 130, so as close as possible to the external terminals (PVIN2, PGND2, SW2) of the second channel.

[0149] Furthermore, the upper switch 11H(ch3) and lower switch 11L(ch3) of the third channel are positioned in the center of the y-direction in a plan view of the semiconductor chip 130, so as close as possible to the external terminal group (PVIN3, PGND3, SW3) of the third channel.

[0150] By adopting this element layout, the lengths of wires W11-W13, W21-W23, and W31-W33 can be minimized, thereby reducing their respective resistance, capacitance, and inductance components as much as possible.

[0151] Furthermore, in this layout, compared to Figure 13A shown earlier, the upper switch 11H (ch1 / ch2 / ch3) and the lower switch 11L (ch1 / ch2 / ch3) are each formed in a vertically elongated shape (a shape in which the x-direction length is greater than the y-direction length). As a result, the PGND pin can be more easily positioned closer to the end of the first side 101 than the SW1~SW3 pins.

[0152] <PCBレイアウト> Next, we will explain in detail, with specific examples, the optimization of the PCB layout achieved by the above pin configuration.

[0153] Figure 14A is a plan view showing the layout of the printed circuit board on which the LED driver IC1a (2ch) shown in Figure 10A is mounted. The LED lamp module X in this configuration example includes a printed circuit board 300 (hereinafter referred to as PCB300), a 2-channel LED driver IC1a, various discrete components attached to it (in this figure, only the capacitors C11 and C21, capacitors C13 and C23, inductors L1 and L2, and sense resistors Rs1 and Rs2 are shown as examples), and light-emitting diodes LED1 and LED2 (not shown). Although not explicitly shown in this figure, a heatsink 200 is attached to the heat dissipation pad 111 of the LED driver IC1a.

[0154] The LED driver IC 1a is mounted on the first main surface (front side of the paper) of PCB 300, as shown by the thin solid line. More specifically, the LED driver IC 1a is mounted in a state where Figure 10 is rotated 90 degrees counterclockwise. That is, in this figure, the left-right direction of the paper corresponds to the x-direction mentioned above, and the up-down direction of the paper corresponds to the y-direction mentioned above. Therefore, the power supply terminals (PVIN1, PVIN2) provided on the first side 101 of package 100 are led downwards on the paper, and the power ground terminals (PGND1, PGND2) and switch output terminals (SW1, SW2) provided on the second side 102 of package 100 are led upwards on the paper.

[0155] On the other hand, the various wires connected to the LED driver IC1a (power supply lines 310-312, power ground lines 320-322, switch output lines 331-333 and 341-343, power line 360), and various discrete components (capacitors C11 and C21, capacitors C13 and C23, inductors L1 and L2, sense resistors Rs1 and Rs2) are laid or mounted on the second main surface (back side of the paper) of the PCB300, as shown by the dashed lines. These will be explained individually below.

[0156] The main portion of the power supply line 310 connected to the power supply terminals (PVIN1, PVIN2) of the LED driver IC 1a, and the main portion of the power ground line 320 connected to the power ground terminals (PGND1, PGND2) of the LED driver IC 1a, are laid in parallel along the x-direction (left-right direction on the paper) in a plan view of the PCB 300.

[0157] Furthermore, the main sections of the power supply line 310 and the power ground line 320 are laid out so as to overlap with the package 100 of the LED driver IC 1a in a plan view of the PCB 300.

[0158] Specifically, referring to this diagram, the main portion of the power supply line 310 is laid in a straight line, starting from the outside of the third side 103, passing near the first side 101 on the back of the package 100, and ending on the outside of the fourth side 104.

[0159] On the other hand, the main portion of the power grounding line 320 is laid in a straight line from the outside of the third side 103, passing near the second side 102 on the back of the package 100, to the outside of the fourth side 104, while maintaining a predetermined gap from the main portion of the power supply line 310.

[0160] Capacitors C11 and C21 (bypass capacitors) are connected between the main section of the power supply line 310 and the main section of the power ground line 320. In particular, capacitors C11 and C21 should be mounted so that they overlap with the LED driver IC 1a in a plan view of the PCB 300, as shown in this figure.

[0161] Furthermore, the power supply line 310 has branch sections 311 and 312 that branch off from the main section. Referring to this figure, branch sections 311 and 312 each branch off downwards from the main section of the power supply line 310, which passes through the back of the package 100, toward the power supply terminals (PVIN1, PVIN2), and are electrically connected to the power supply terminals (PVIN1, PVIN2) via vias, through-holes, etc. (not shown) that penetrate between the first main surface and the second main surface of the PCB 300.

[0162] Furthermore, the power ground line 320 has branch sections 321 and 322 that branch off from the main section. Referring to this figure, branch sections 321 and 322 each branch upward from the main section of the power ground line 320, which passes through the back of the package 100, toward the power ground terminals (PGND1, PGND2), and are electrically connected to the power ground terminals (PGND1, PGND2) via vias or through-holes (not shown) that penetrate between the first and second main surfaces of the PCB 300. Note that power ground lines 321 and 322 may be shared. If power ground lines 321 and 322 are shared, the branch section branched from the main section of the power supply line 310 becomes a single line.

[0163] Switch output lines 331-333, which conduct electricity between the first channel's switch output terminal (SW1) and the light-emitting diode LED1, are laid out from the rear area of ​​the switch output terminal (SW1) facing upwards on the paper. An inductor L1 is mounted between switch output line 331 and switch output line 332. A sense resistor Rs1 is mounted between switch output line 332 and switch output line 333. A capacitor C13 is mounted between switch output line 333 and a branch line 321 of the power ground line 320 that extends to an adjacent position.

[0164] Switch output lines 341-343, which conduct electricity between the second channel's switch output terminal (SW2) and the light-emitting diode LED2, are laid out from the rear area of ​​the switch output terminal (SW2) facing upwards on the paper. An inductor L2 is mounted between switch output line 341 and switch output line 342. A sense resistor Rs2 is mounted between switch output line 342 and switch output line 343. A capacitor C23 is mounted between switch output line 343 and the branch line 322 of the power ground line 320 that extends to an adjacent position.

[0165] Furthermore, in the LED lamp module X of this configuration example, the power supply terminals (PVIN1, PVIN2), switch output terminals (SW1, SW2), power ground terminals (PGND1, PGND2) provided for each of the multiple channels, and the discrete components (C11 and C21, C13 and C23, L1 and L2, Rs1 and Rs2) attached externally to these, as well as the branch wire portions 311 and 312 of the power supply line 310, the branch wire portions 321 and 322 of the power ground line 320, and the switch output lines 331-333 and 341-343 are arranged symmetrically between the first channel and the second channel.

[0166] A brief explanation of the external terminals and wiring other than those mentioned above will also be provided. The VIN pin, located on the first side 101 of package 100, is connected to the power line 360, which is laid from the back area facing downwards on the page. In addition, logic signals are input from the bottom of the page to the SPI communication terminals (SI, SCK, CSB, SO) located on the first side 101.

[0167] Figure 14A, mentioned above, is a plan view showing the layout of a printed circuit board on which an LED driver IC1a (2ch) having a synchronous rectification half-bridge output stage is mounted. On the other hand, Figure 14B is a plan view showing the layout of a printed circuit board on which an LED driver IC1a (2ch) employing diode rectification instead of synchronous rectification is mounted.

[0168] The differences between Figure 14B and Figure 14A will now be explained. Diodes D11 and D21 are discrete components externally connected to the LED driver IC 1a. Diodes D11 and D21 are mounted on the second main surface of PCB 300, as shown by the dashed lines. Diode D11 is used as the lower switch 11L for the first channel, and diode D21 is used as the lower switch 11L for the second channel.

[0169] Diode D11 should be implemented such that its cathode terminal is electrically connected to the switch output line 331 and its anode terminal is electrically connected to the power ground line 320. To minimize the closed loop of the first channel (see Figure 16, described later), it is preferable to place the anode terminal of diode D11 as close as possible to the capacitor C11.

[0170] Diode D21 should be mounted such that its cathode terminal is electrically connected to the switch output line 341 and its anode terminal is electrically connected to the power ground line 320. To minimize the closed loop of the second channel (see Figure 16, described later), it is preferable to position the anode terminal of diode D21 as close as possible to the capacitor C21.

[0171] In the configuration example shown in Figure 14B, one power ground terminal PGND1 and one PGND2 are provided for the first channel and the second channel, respectively. However, as shown in Figure 19 later, the power ground terminal may be shared between the first channel and the second channel.

[0172] Next, we will describe the layouts of the printed circuit board other than those shown in Figures 14A and 14B. Figure 14C is a plan view showing another layout of the printed circuit board on which the LED driver IC1a (2ch) having a synchronous rectification type half-bridge output stage is mounted. Figure 14D is a plan view showing another layout of the printed circuit board on which the LED driver IC1a (2ch) having a diode rectification type half-bridge output stage is mounted. Below, we will explain the differences between Figure 14C and Figure 14A, and the differences between Figure 14D and Figure 14B.

[0173] The layouts shown in Figures 14C and 14D enlarge the power supply line 310 and power ground line 320 compared to the layouts shown in Figures 14A and 14B. Therefore, in the layouts shown in Figures 14C and 14D, unlike the layouts shown in Figures 14A and 14B, the power supply line 360, the logic signal transmission line (not shown), the switch output line 330, and the switch output line 340 are laid on the first main surface of the PCB 300.

[0174] The switch output line 330 conducts electricity between the switch output terminal (SW1) of the first channel and the switch output line 331. The switch output line 330 is electrically connected to the switch output line 331 via vias, through-holes, etc. (not shown) that penetrate between the first main surface and the second main surface of the PCB 300. In the layouts shown in Figures 14C and 14D, unlike the layouts shown in Figures 14A and 14B, the switch output line 331 does not overlap with the switch output terminal (SW1) in a plan view of the PCB 300.

[0175] Switch output line 340 conducts electricity between the second channel's switch output terminal (SW2) and switch output line 341. Switch output line 340 is electrically connected to switch output line 341 via vias or through-holes (not shown) that penetrate between the first and second main surfaces of PCB 300. In the layouts shown in Figures 14C and 14D, unlike the layouts shown in Figures 14A and 14B, switch output line 341 does not overlap with the switch output terminal (SW2) in a plan view of PCB 300.

[0176] Figure 15 is a plan view showing the layout of the printed circuit board on which the LED driver IC1b (3ch) shown in Figure 11A is mounted. The LED lamp module X in this configuration example has a PCB 300, a 3-channel LED driver IC1b, various discrete components attached to it (in this figure, only the capacitors C11, C21 and C31, capacitors C13, C23 and C33, inductors L1 to L3, and sense resistors Rs1 to Rs3 are shown as examples), and light-emitting diodes LED1 to LED3 (not shown). Although not explicitly shown in this figure, a heatsink 200 is attached to the heat dissipation pad 111 of the LED driver IC1b.

[0177] The LED driver IC1b is mounted on the first main surface (front side of the paper) of PCB300, as shown by the thin solid line. More specifically, the LED driver IC1b is mounted in a state where Figure 11 is rotated 90 degrees counterclockwise. That is, in this figure, the left-right direction of the paper corresponds to the x-direction mentioned above, and the up-down direction of the paper corresponds to the y-direction mentioned above. Therefore, the power supply terminals (PVIN1~PVIN3) provided on the first side 101 of package 100 are led downwards on the paper, and the power ground terminals (PGND1~PGND3) and switch output terminals (SW1~SW3) provided on the second side 102 of package 100 are led upwards on the paper.

[0178] On the other hand, the various wires connected to the LED driver IC1b (power supply lines 310-312, power ground lines 320-323, switch output lines 331-333, 341-343 and 351-353, power line 360), and various discrete components (capacitors C11, C21 and C31, capacitors C13, C23 and C33, inductors L1-L3, sense resistors Rs1-Rs3) are laid or mounted on the second main surface (back side of the paper) of PCB300, as shown by the dashed lines. These will be explained individually below.

[0179] The main portion of the power supply line 310 connected to the power supply terminals (PVIN1~PVIN3) of the LED driver IC 1b, and the main portion of the power ground line 320 connected to the power ground terminals (PGND1~PGND3) of the LED driver IC 1b, are laid in parallel along the x-direction (left-right direction on the paper) in a plan view of the PCB 300.

[0180] Furthermore, the main sections of the power supply line 310 and the power ground line 320 are laid out so as to overlap with the package 100 of the LED driver IC 1b in a plan view of the PCB 300.

[0181] Specifically, referring to this diagram, the main portion of the power supply line 310 is laid in a straight line, starting from the outside of the third side 103, passing near the first side 101 on the back of the package 100, and ending on the outside of the fourth side 104.

[0182] On the other hand, the main portion of the power grounding line 320 is laid in a straight line from the outside of the third side 103, passing near the second side 102 on the back of the package 100, to the outside of the fourth side 104, while maintaining a predetermined gap from the main portion of the power supply line 310.

[0183] Capacitors C11, C21, and C31 (bypass capacitors) are connected between the main section of the power supply line 310 and the main section of the power ground line 320. In particular, capacitors C11, C21, and C31 should be mounted so that they overlap with the LED driver IC 1b in a plan view of the PCB 300, as shown in this figure.

[0184] Furthermore, the power supply line 310 has branch sections 311 to 313 that branch off from the main section. Referring to this figure, the branch sections 311 to 313 each branch off downwards from the main section of the power supply line 310, which passes through the back of the package 100, toward the power supply terminals (PVIN1 to PVIN3), and are electrically connected to the power supply terminals (PVIN1 to PVIN3) via vias, through-holes, etc. (not shown) that penetrate between the first main surface and the second main surface of the PCB 300.

[0185] Furthermore, the power ground line 320 has branch sections 321 to 323 that branch off from the main section. Referring to this figure, the branch sections 321 to 323 each branch off upward from the main section of the power ground line 320, which passes through the back of the package 100, toward the power ground terminals (PGND1 to PGND3), and are electrically connected to the power ground terminals (PGND1 to PGND3) via vias, through-holes, etc. (not shown) that penetrate between the first main surface and the second main surface of the PCB 300.

[0186] Switch output lines 331-333, which conduct electricity between the first channel's switch output terminal (SW1) and the light-emitting diode LED1, are laid out from the rear area of ​​the switch output terminal (SW1) facing upwards on the paper. An inductor L1 is mounted between switch output line 331 and switch output line 332. A sense resistor Rs1 is mounted between switch output line 332 and switch output line 333. A capacitor C13 is mounted between switch output line 333 and a branch line 321 of the power ground line 320 that extends to an adjacent position.

[0187] Switch output lines 341-343, which conduct electricity between the second channel's switch output terminal (SW2) and the light-emitting diode LED2, are laid out from the rear area of ​​the switch output terminal (SW2) facing upwards on the paper. An inductor L2 is mounted between switch output line 341 and switch output line 342. A sense resistor Rs2 is mounted between switch output line 342 and switch output line 343. A capacitor C23 is mounted between switch output line 343 and the branch line 322 of the power ground line 320 that extends to an adjacent position.

[0188] Switch output lines 351-353, which conduct electricity between the third channel's switch output terminal (SW3) and the light-emitting diode LED3, are laid out from the rear area of ​​the switch output terminal (SW3) facing upwards on the paper. An inductor L3 is mounted between switch output line 351 and switch output line 352. A sense resistor Rs3 is mounted between switch output line 352 and switch output line 353. A capacitor C33 is mounted between switch output line 353 and the branch line 323 of the power ground line 320 that extends to an adjacent position.

[0189] Furthermore, in the LED lamp module X of this configuration example, the power supply terminals (PVIN1~PVIN3), switch output terminals (SW1~SW3), power ground terminals (PGND1~PGND3) provided for each of the multiple channels, and the discrete components (C11, C21 and C31, C13, C23 and C33, L1~L3, Rs1~Rs3) attached externally to these, as well as the branch wire portions 311~313 of the power supply line 310, the branch wire portions 321~323 of the power ground line 320, and the switch output lines 331~333, 341~343 and 351~353 are arranged symmetrically between at least two channels. Specifically, the components are arranged symmetrically between the first channel and the second channel, and between the first channel and the third channel.

[0190] The external terminals and wirings other than those described above will also be briefly explained. A power line 360 laid from the back region downward in the drawing plane is connected to the VIN pin provided on the first side 101 of the package 100. Further, logic signals are input from the lower side of the drawing plane to the SPI communication terminals (SI, SCK, CSB, SO) provided on the first side 101.

[0191] Note that the same changes as those from the aforementioned FIG. 14A to the aforementioned FIGS. 14B to 14D can also be made to FIG. 15.

[0192] <Bypass capacitor> Next, the optimal layout of the capacitor C*1 (* = 1, 2, or 3) that functions as a bypass capacitor will be considered while referring to the drawings. FIG. 16 is a diagram showing the formation of a closed loop of the capacitor C*1.

[0193] As shown in this figure, the capacitor C*1 of the *-th channel forms a closed loop (11H → PVIN* → C*1 → PGND* → 11L) together with the upper switch 11H and the lower switch 11L. The smaller this closed loop is, the more the influence of the transient current accompanying the power supply fluctuation can be suppressed. Therefore, it is desirable to mount the capacitor C*1 at a position where the above closed loop is minimized.

[0194] Specifically, as shown in the aforementioned FIGS. 14A to 14D and FIG. 15, it is desirable to mount the capacitor C*1 so as to overlap with the LED driver ICs 1a to 1b in a plan view of the PCB 300. Further, it is desirable to mount it on (or in the vicinity of) the line segment connecting the PVIN* pin and the PGND* pin.

[0195] <Vertical arrangement of LED driver ICs> Figure 17 shows the vertical arrangement of the LED driver IC1b(3ch). In the LED lamp module X of this configuration example, m LED driver ICs 1b(1) to 1b(m) (where m≧2) are mounted vertically along the x direction (left-right direction of the paper) on the first main surface of the PCB300.

[0196] The LED driver ICs 1b(1) to 1b(m) each employ the pin configurations shown in Figure 11. Therefore, the power supply line 310 and the power ground line 320 can be laid in a straight line along the x-direction (left-right direction on the paper), passing behind the backs of the LED driver ICs 1b(1) to 1b(m), as shown in Figure 15.

[0197] Furthermore, since the switch output lines of each LED driver IC1b(1) to 1b(m) can be led out facing upwards on the paper, even if the number of channels increases, it becomes possible to arrange all the light-emitting diodes LED1 to LED(3m) along the x-direction (left-right direction on the paper).

[0198] By adopting the aforementioned pin configuration, it becomes possible to simplify the wiring patterns laid on the PCB300, which in turn enables optimization of the PCB layout, such as preventing short circuits between wiring patterns and reducing the wiring pattern area.

[0199] Although this diagram uses a vertical arrangement of LED driver IC1b (3ch) as an example, the same applies to a vertical arrangement of LED driver IC1a (2ch).

[0200] <Comparative Example> Next, in order to more clearly understand the effects of the pin configurations described so far (Figures 10-15), we will explain the differences in PCB layouts by giving examples of cases that employ different pin configurations.

[0201] Figure 18 is a plan view showing the layout of a printed circuit board on which the LED driver IC1c (3ch), which uses a different pin configuration than the one shown earlier, is mounted.

[0202] As shown in this figure, in the LED driver IC 1c, the external terminals for the first channel (PVIN1, PGND1, SW1) are all located on the first side 101 of the package 100. On the other hand, the external terminals for the second channel (PVIN2, PGND2, SW2) and the external terminals for the third channel (PVIN3, PGND3, SW3) are all located on the second side 102 of the package 100.

[0203] Therefore, the components of the first channel, as well as the components of the second and third channels, must be installed or positioned separately on either side of the LED driver IC 1c.

[0204] Referring to this diagram, the components of the first channel (power supply line 411, branch line portion 421 of power ground line 420, switch output lines 431-433, capacitors C11 and C13, inductor L1, and sense resistor Rs1) are all located on the first side 101 of package 100.

[0205] On the other hand, the components of the second channel (power supply line 412, branch line portion 422 of power ground line 420, switch output lines 441-443, capacitors C21 and C23, inductor L2, and sense resistor Rs2) are all located on the second side 102 of package 100.

[0206] Furthermore, the components of the third channel (power supply line 413, branch line portion 423 of power ground line 420, switch output lines 451-453, capacitors C31 and C33, inductor L3, and sense resistor Rs3) are all located on the second side 102 of package 100.

[0207] Thus, if the pin configuration of this comparative example is adopted, the wiring pattern laid on the PCB400 becomes extremely complex, and it becomes impossible to arrange all the LED1 to LED3 channels in the x-direction (left-right direction on the paper).

[0208] On the other hand, by adopting the previously proposed pin configuration (Figures 10-15), it is possible to avoid such problems and optimize the PCB layout.

[0209] <Variation> It should be noted that the pin configurations and PCB layouts described so far can be modified in various ways. A brief explanation of some of these modifications follows.

[0210] Figure 19 shows a first modified example of the pin configuration. As shown in this figure, the power ground terminal (PGND) does not necessarily need to be provided for each channel; it may be shared by multiple channels.

[0211] Figure 20 shows a second modified example of the pin configuration. As shown in this figure, the power supply terminal (PVIN) does not necessarily need to be provided for each channel; it may be shared by multiple channels.

[0212] Figure 21 shows a third modified example of the pin configuration. As shown in this figure, the power ground terminal (PGND) and the switch output terminal (SW) located on the second side 102 may be swapped in their respective positions.

[0213] Figure 22 shows a fourth modified example of the pin configuration. As shown in this figure, the power terminal (VIN) of the signal system does not necessarily have to be located on the first side 101, but may also be located on the second side 102.

[0214] Figure 23 shows a modified PCB layout. As shown in this figure, at least one of the power supply line 310 and the power ground line 320 (the power supply line 310 in this figure) may be laid in a position that does not overlap with the package 100.

[0215] Figure 24 shows an example of using a quad flat package (QFP). As shown in this figure, package 100 is not necessarily limited to SOP, and a QFP can also be used.

[0216] In that case, for example, the SW1 and SW2 pins should be placed on the second side 102, the PVIN1 and PGND1 pins of the first channel should be placed on the third side 103, and the PVIN2 and PGND2 pins of the second channel should be placed on the fourth side 104. Furthermore, the PVIN1 and PVIN2 pins should be placed closer to the first side 101, and the PGND1 and PGND2 pins should be placed closer to the second side 102. In addition, the PVIN1 and PVIN2 pins should be placed opposite each other. Similarly, the PGND1 and PGND2 pins should be placed opposite each other.

[0217] By adopting this pin configuration, the power supply line 310 and the power ground line 320 can be laid in parallel and in a straight line, just as in Figure 14A above.

[0218] <Same-sided mounting> Figure 25 is a plan view showing the layout of a printed circuit board on which the LED driver IC 1b (3ch) shown in Figure 11B and several discrete components attached to it are mounted on the same surface. The LED lamp module X in this example configuration has a PCB 300, three 3-channel LED driver ICs 1b (three in this figure) shown in Figure 11B, various discrete components attached to them (in this figure, capacitor C, inductor L, and sense resistor R are examples), and light-emitting diodes LED1 to LED9 (not shown). Although not explicitly shown in this figure, a heatsink 200 is attached to the heat dissipation pad 111 of the LED driver IC 1b.

[0219] The LED driver IC1b is mounted on the first main surface (front side of the paper) of PCB300, as shown by the thin solid line. Furthermore, at least some of the various wirings and discrete components connected to the LED driver IC1b are laid or mounted on the first main surface (front side of the paper) of PCB300, as shown by the solid line, while the remainder are laid or mounted on the second main surface (back side of the paper) of PCB300, as shown by the dashed line. These will be explained individually below.

[0220] The main portion of the power supply line 310, which is connected to the power supply terminals (PVIN1 to PVIN3) of the LED driver IC 1b, is laid out along the x-direction on the first main surface of the PCB 300, in a position that does not overlap with the package 100 of the LED driver IC 1b.

[0221] On the other hand, the main portion of the power ground line 320, which is connected to the power ground terminals (PGND1 to PGND3) of the LED driver IC 1b, is laid along the x-direction on the second main surface of the PCB 300, at a position that overlaps with the package 100 of the LED driver IC 1b.

[0222] Furthermore, the power supply line 310 has branch sections 311 to 313 that branch off from the main section. Referring to this diagram, the branch sections 311 to 313 each branch off from the main section of the power supply line 310 toward the power supply terminals (PVIN1 to PVIN3) on the first main surface of the PCB 300, and are electrically connected to the power supply terminals (PVIN1 to PVIN3).

[0223] Furthermore, the power ground line 320 has branch sections 321 to 325 that branch off from the main section. Referring to this figure, branch sections 321 to 323 each branch off from the main section of the power ground line 320 toward the power ground terminals (PGND1 to PGND3) on the second main surface of the PCB 300, and are electrically connected to the power ground terminals (PGND1 to PGND3) via vias, through-holes, etc. (not shown) that penetrate between the first and second main surfaces of the PCB 300.

[0224] Furthermore, the branch line section 324 branches off from the main section of the power ground line 320 towards the branch lines 311-313 of the power supply line 310 on the second main surface of the PCB 300. A bypass capacitor C is installed between the branch sections 311-313 of the power supply line 310 and the branch section 324 of the power ground line 320.

[0225] On the other hand, the branch line section 325 branches off from the main section of the power ground line 320 towards the later-described switch output lines 333 to 353 on the second main surface of the PCB 300.

[0226] The switch output lines 331 to 333, connected to the switch output terminal (SW1) of each LED driver IC1b, are laid out on the first main surface of PCB300 toward the corresponding light-emitting diodes (LED3, LED6, and LED9 in this figure). An inductor L is mounted between switch output line 331 and switch output line 332 on the first main surface of PCB300. A sense resistor R is mounted between switch output line 332 and switch output line 333 on the first main surface of PCB300. An output capacitor C is mounted between switch output line 333 and the branch line portion 325 of the power ground line 320 that extends to an adjacent position on the first main surface of PCB300.

[0227] The switch output lines 341 to 343, connected to the switch output terminal (SW2) of each LED driver IC1b, are laid out on the first main surface of PCB300 toward the corresponding light-emitting diodes (LED1, LED4, and LED7 in this figure). An inductor L is mounted between switch output line 341 and switch output line 342 on the first main surface of PCB300. A sense resistor R is mounted between switch output line 342 and switch output line 343 on the first main surface of PCB300. An output capacitor C is mounted between switch output line 343 and the branch line portion 325 of the power ground line 320 that extends to an adjacent position on the first main surface of PCB300.

[0228] Switch output lines 351 to 353, connected to the switch output terminal (SW3) of each LED driver IC1b, are laid out on the first main surface of PCB300 toward the corresponding light-emitting diodes (LED2, LED5, and LED8 in this figure). An inductor L is mounted between switch output line 351 and switch output line 352 on the first main surface of PCB300. A sense resistor R is mounted between switch output line 352 and switch output line 353 on the first main surface of PCB300. An output capacitor C is mounted between switch output line 353 and the branch portion 323 of the power ground line 320 that extends to an adjacent position on the first main surface of PCB300.

[0229] Although not explicitly shown in this diagram, it is recommended to mount small-signal discrete components on the second main surface of PCB300.

[0230] Furthermore, when mounting the LED driver IC and the discrete components attached to it on the same side of the printed circuit board, the number of channels and pin configuration of the LED driver IC are irrelevant. In other words, in this figure, not only the LED driver IC1b (3ch) shown in Figure 11B, but also the LED driver IC1b (3ch) shown in Figure 11A, and the LED driver IC1a (2ch) shown in Figures 10A and 10B can be mounted on the same side with the discrete components.

[0231] Figure 26 shows the α-β cross-section of Figure 25. As mentioned earlier, in the LED lamp module X of Figure 25, the three LED driver ICs 1b and at least some of the discrete components attached to them (inductors L, sense resistors R, and output capacitors C) are all mounted on the same plane (first main plane) of the PCB 300.

[0232] Therefore, by designing the shape of the heatsink 200 attached to the LED driver IC 1b, it becomes possible to attach the heatsink 200 to both the LED driver IC 1b and discrete components (such as inductors L) mounted on the same side of the PCB 300.

[0233] For example, as shown in this figure, an extension 240 can be provided that extends from the base 210 of the heatsink 200 toward the top of the inductor L, and thermal grease 250 can be applied to its bottom surface and attached to the top surface of the inductor L. With such a configuration, it is possible to improve the heat dissipation not only of the LED driver IC 1b but also of discrete components.

[0234] For example, as shown in this figure, arranging discrete components of the same height in a row simplifies the design of the heatsink 200 (especially the extension portion 240). In this figure, the LED driver IC 1b and inductor L are connected to the heatsink 200, but other discrete components can also be connected to the heatsink 200 as needed.

[0235] <Other variations> Thus, the various technical features disclosed herein can be modified in various ways, in addition to the embodiments described above, without departing from the spirit of the technical creation. In other words, the embodiments described above should be considered in all respects to be illustrative and not restrictive, and the technical scope of the present invention should be understood to include all modifications that fall within the meaning and scope equivalent to the claims, rather than being limited to the embodiments described above. [Industrial applicability]

[0236] The inventions disclosed herein can be used, for example, in a multi-channel LED driver IC mounted in an automotive LED lamp module. [Explanation of Symbols]

[0237] 1, 1a, 1b LED driver IC (semiconductor device) 2 Boost Circuit 3 MCU 11H Upper switch (NMOSFET) 11L Lower switch (NMOSFET) 12H Upper Driver 12L Lower Driver 13 Controllers 14. On-time setting section 15. Slope Voltage Generation Unit 16 SenseAmp 17 Error Amplifier 18 Comparator 100 packages 101 First side 102 Second side 103 Third side 104 Fourth side 110 Top surface 111 Heat dissipation pad 112 1 pin mark 120 Bottom surface 130 semiconductor chips 140 Islands 151, 152 Support frame 200 Heatsink 210 Base 220 heat dissipation fins 230 Thermal grease 240 Extension 250 Thermal grease 300 Printed Circuit Boards 310 Power supply lines (main circuit) 311, 312, 313 Power supply lines (branch lines) 320 Power grounding line (main section) 321, 322, 323, 324, 325 Power grounding lines (branch wire sections) Switch lines 330-333, 340-343, 351-353 360 Power Lines Capacitors C1, C2, C11-C13, C21-C23, C31-C33 D1, D11, D21 diodes L1, L2, L3 Inductors LED1, LED2, LED3 Light-emitting diodes R1, R2 resistance Rs1, Rs2, Rs3 Sense Resistors W11-W13, W21-W23, W31-W33 wires X LED lamp module

Claims

1. A rectangular package in plan view having a first side, a second side parallel to the first side, a third side perpendicular to the first and second sides, and a fourth side parallel to the third side and perpendicular to the first and second sides, A power supply terminal provided on the first or second side, A power grounding terminal provided on the first side, the second side, or the fourth side, A switch output terminal is provided on the second side, An upper switch connected between the power supply terminal and the switch output terminal, A lower switch connected between the switch output terminal and the power ground terminal, It has, The upper switch, the lower switch, the power supply terminal, and the power ground terminal are each provided for each of the multiple channels. Semiconductor equipment.

2. The aforementioned switch output terminals are provided for each of the multiple channels. The semiconductor device according to claim 1.

3. The package has a heat dissipation pad exposed on the top surface, The semiconductor device according to claim 2.

4. The upper switch and the lower switch are, in a plan view, positioned towards the second side. The semiconductor device according to claim 3.

5. The upper switch and the lower switch are arranged in a vertical column in a plan view along a second direction perpendicular to the first direction in which the first and second sides extend. The semiconductor device according to claim 4.

6. The system further includes an output feedback control unit that drives the upper switch and the lower switch so that the output current supplied to the load from the switch output terminal matches a predetermined target value. The semiconductor device according to claim 5.

7. The output feedback control unit performs output feedback control using a bottom detection on-time fixed method. The semiconductor device according to claim 6.

8. The thermal resistance from the semiconductor chip sealed in the package to the top surface of the package is smaller than the thermal resistance from the semiconductor chip to the bottom surface of the package. The semiconductor device according to claim 6 or 7.

9. A rectangular package in plan view having a first side, a second side parallel to the first side, a third side perpendicular to the first and second sides, and a fourth side parallel to the third side and perpendicular to the first and second sides, A power supply terminal provided on the first or second side, A power grounding terminal provided on the first side, the second side, or the fourth side, A switch output terminal is provided on the second side, An upper switch connected between the power supply terminal and the switch output terminal, A lower switch connected between the switch output terminal and the power ground terminal, The package has a heat dissipation pad exposed on the top surface, Semiconductor equipment.

10. A rectangular package in plan view having a first side, a second side parallel to the first side, a third side perpendicular to the first and second sides, and a fourth side parallel to the third side and perpendicular to the first and second sides, A power supply terminal provided on the first or second side, A power grounding terminal provided on the first side, the second side, or the fourth side, A switch output terminal is provided on the second side, An upper switch connected between the power supply terminal and the switch output terminal, A lower switch connected between the switch output terminal and the power ground terminal, It has, The upper switch and the lower switch are, in a plan view, positioned towards the second side. Semiconductor equipment.

11. A rectangular package in plan view having a first side, a second side parallel to the first side, a third side perpendicular to the first and second sides, and a fourth side parallel to the third side and perpendicular to the first and second sides, A power supply terminal provided on the first or second side, A power grounding terminal provided on the first side, the second side, or the fourth side, A switch output terminal is provided on the second side, An upper switch connected between the power supply terminal and the switch output terminal, A lower switch connected between the switch output terminal and the power ground terminal, It has, The upper switch and the lower switch are arranged in a vertical column in a plan view along a second direction perpendicular to the first direction in which the first and second sides extend. Semiconductor equipment.

12. A rectangular package in plan view having a first side, a second side parallel to the first side, a third side perpendicular to the first and second sides, and a fourth side parallel to the third side and perpendicular to the first and second sides, A power supply terminal provided on the first or second side, A power grounding terminal provided on the first side, the second side, or the fourth side, A switch output terminal is provided on the second side, An upper switch connected between the power supply terminal and the switch output terminal, A lower switch connected between the switch output terminal and the power ground terminal, An output feedback control unit that drives the upper switch and the lower switch so that the output current supplied to the load from the switch output terminal matches a predetermined target value, Semiconductor equipment.

13. The output feedback control unit performs output feedback control using a bottom detection on-time fixed method. The semiconductor device according to claim 12.

14. A rectangular package in plan view having a first side, a second side parallel to the first side, a third side perpendicular to the first and second sides, and a fourth side parallel to the third side and perpendicular to the first and second sides, A power supply terminal provided on the first or second side, A power grounding terminal provided on the first side, the second side, or the fourth side, A switch output terminal is provided on the second side, An upper switch connected between the power supply terminal and the switch output terminal, A lower switch connected between the switch output terminal and the power ground terminal, It has, The thermal resistance from the semiconductor chip sealed in the package to the top surface of the package is smaller than the thermal resistance from the semiconductor chip to the bottom surface of the package. Semiconductor equipment.

15. A rectangular package in plan view having a first side, a second side parallel to the first side, a third side perpendicular to the first and second sides, and a fourth side parallel to the third side and perpendicular to the first and second sides, A power supply terminal provided on the first or second side, A power grounding terminal provided on the first side, the second side, or the fourth side, A switch output terminal is provided on the second side, An upper switch connected between the power supply terminal and the switch output terminal, A lower switch connected between the switch output terminal and the power ground terminal, It has, The lower switch has a larger element size than the upper switch. Semiconductor equipment.

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