Processing system, processing method, and program

Abstract

To provide a processing system that can stably supply power to the load. [Solution] The processing system comprises a plurality of power supplies, a load circuit common to the plurality of power supplies, a plurality of ORING FETs (Field Effect Transistors) one at a time provided between each of the plurality of power supplies and the load circuit, and control means that, when the load circuit is in a low load state, controls only one of the plurality of ORING FETs to be in an ON state and controls all the remaining of the plurality of ORING FETs to be in an OFF state.

Description

Technical Field

[0001] The present disclosure relates to a processing system, a processing method, and a program.

Background Art

[0002] In various technical fields, power supply devices are used. Patent Document 1 discloses a technique related to a power supply device that improves the reliability of a system by connecting a plurality of power supplies in parallel to a load.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In the technical field related to Patent Document 1, a technique capable of stably supplying power to a load is required.

[0005] One of the objectives of each aspect of the present disclosure is to provide a processing system, a processing method, and a program that can solve the above problems.

Means for Solving the Problems

[0006] According to one aspect of the present disclosure, a processing system is A control means comprising a first power supply, a second power supply, a load circuit common to the first and second power supplies, a plurality of ORING FETs (Field Effect Transistors) one each provided between the first and second power supplies and the load circuit, and a first control means for controlling the first power supply and a second control means for controlling the second power supply, wherein when the load circuit is in a low load state, only one of the plurality of ORING FETs is controlled to be turned on, and the plurality of ORING FETs The system includes control means for controlling all remaining FETs to the OFF state, wherein the first and second control means are set to primary when the input PS setting signal, which is used to determine which system is ON in the low load state, is at a High level, and are set to secondary when the input PS setting signal is at a Low level, and when set to primary, they control the first or second power supply to be controlled so that the output voltage becomes the nominal output value, and when it is determined that the first or second power supply to be controlled is abnormal, the ORING existing between the first or second control means that determined that the first or second power supply is abnormal and the first or second power supply that was determined to be abnormal The FET and the first or second power supply determined to be abnormal are controlled to the OFF state, and the signal on the signal line between the first and second control means is controlled to a Low level. If the control means is set to secondary, the first or second power supply to be controlled is controlled so that its output voltage is the lowest nominal output value. If the first or second power supply to be controlled is determined not to be abnormal and the signal on the signal line is determined to be at a Low level, the first or second power supply to be controlled is controlled so that its output voltage is the nominal output value. .

[0007] According to another aspect of the present disclosure, a processing method is A control means comprising a first power supply, a second power supply, a load circuit common to the first and second power supplies, a plurality of ORING FETs (Field Effect Transistors) one each provided between the first and second power supplies and the load circuit, and a first control means for controlling the first power supply and a second control means for controlling the second power supply, wherein when the load circuit is in a low load state, only one of the plurality of ORING FETs is controlled to be turned on, and the plurality of ORING FETs A processing method performed by a processing system comprising control means for controlling all remaining FETs to an OFF state, wherein the first control means and the second control means are set to primary when a PS setting signal input to determine which system is ON in the low load state is at a High level, and set to secondary when the input PS setting signal is at a Low level, and when set to primary, control the first power supply or the second power supply to be controlled so that the output voltage becomes the nominal output value, and when it is determined that the first power supply or the second power supply to be controlled is abnormal, an ORING existing between the first control means or the second control means that determined that the first power supply or the second power supply is abnormal and the first power supply or the second power supply that was determined to be abnormal The FET and the first or second power supply determined to be abnormal are controlled to the OFF state, and the signal on the signal line between the first and second control means is controlled to a Low level. If the control means is set to secondary, the first or second power supply to be controlled is controlled so that its output voltage is the lowest nominal output value. If the first or second power supply to be controlled is determined not to be abnormal and the signal on the signal line is determined to be at a Low level, the first or second power supply to be controlled is controlled so that its output voltage is the nominal output value. .

[0008] According to another aspect of the present disclosure, a program is A control means comprising a first power supply, a second power supply, a load circuit common to the first and second power supplies, a plurality of ORING FETs (Field Effect Transistors) one each provided between the first and second power supplies and the load circuit, and a first control means for controlling the first power supply and a second control means for controlling the second power supply, wherein when the load circuit is in a low load state, only one of the plurality of ORING FETs is controlled to be turned on, and the plurality of ORING FETs A computer in a processing system comprising control means for controlling all remaining FETs to be in the OFF state, wherein the first control means and the second control means are set to primary when the input PS setting signal, which is used to determine which system is ON in the low load state, is at a High level, and are set to secondary when the input PS setting signal is at a Low level, and when set to primary, they control the first power supply or the second power supply to be controlled so that the output voltage becomes the nominal output value, and when it is determined that the first power supply or the second power supply to be controlled is abnormal, the ORING existing between the first control means or the second control means that determined that the first power supply or the second power supply is abnormal and the first power supply or the second power supply that was determined to be abnormal The FET and the first or second power supply determined to be abnormal are controlled to be in the OFF state, and the signal on the signal line between the first and second control means is controlled to a Low level. If the control means is set to secondary, the first or second power supply to be controlled is controlled so that its output voltage is the lowest nominal output value. If the first or second power supply to be controlled is determined not to be abnormal and the signal on the signal line is determined to be at a Low level, the first or second power supply to be controlled is controlled so that its output voltage is the nominal output value. .

Effects of the Invention

[0009] According to each aspect of this disclosure, power can be supplied stably to the load. [Brief explanation of the drawing]

[0010] [Figure 1] This figure shows an example of the configuration of a processing system according to some embodiments of the present disclosure. [Figure 2] This figure shows an example of the configuration of a control unit according to some embodiments of the present disclosure. [Figure 3] This figure shows an example of a first processing flow of a processing system according to some embodiments of the present disclosure. [Figure 4] This figure shows an example of a second processing flow of a processing system according to some embodiments of the present disclosure. [Figure 5] This figure shows an example of a third processing flow of a processing system according to some embodiments of the present disclosure. [Figure 6] This figure shows an example of a fourth processing flow of a processing system according to some embodiments of the present disclosure. [Figure 7] This figure shows an example of a fifth processing flow of a processing system according to some embodiments of the present disclosure. [Figure 8] This figure shows an example of the configuration of a processing system according to some embodiments of the present disclosure. [Figure 9] This figure shows an example of the processing flow of a processing system according to some embodiments of the present disclosure. [Figure 10] This is a schematic block diagram showing the configuration of a computer according to at least one embodiment. [Modes for carrying out the invention]

[0011] The embodiments will be described in detail below with reference to the drawings. <Embodiment> A processing system 1 according to one embodiment of this disclosure will be described with reference to the drawings. The processing system 1 is a system that can stably supply power to a load.

[0012] (Configuration of the processing system) The processing system 1 according to an embodiment of the present disclosure will be described with reference to the drawings. FIG. 1 is a diagram showing an example of the configuration of the processing system 1 according to some embodiments of the present disclosure. As shown in FIG. 1, the processing system 1 includes power supplies 10a, 10b, ORING FETs (Field Effect Transistors) 20a, 20b, control units 30a, 30b, and a load circuit 40. The power supplies 10a, 10b may be collectively referred to as the power supply 10. The ORING FETs 20a, 20b may be collectively referred to as the ORING FET 20. The control units 30a, 30b may be collectively referred to as the control unit 30. The processing system 1 is a system having a redundant configuration in which a plurality of power supplies 10 are connected to the load circuit 40.

[0013] The first terminal of the power supply 10a is connected to the first terminal of the ORING FET 20a and the first terminal of the control unit 30a via the signal line L1a. The second terminal of the power supply 10a is connected to the second terminal of the control unit 30a via the signal line L2a.

[0014] The first terminal of the power supply 10b is connected to the first terminal of the ORING FET 20b and the first terminal of the control unit 30b via the signal line L1b. The second terminal of the power supply 10b is connected to the second terminal of the control unit 30b via the signal line L2b.

[0015] The second terminal of the ORING FET 20a is connected to the second terminal of the ORING FET 20b, the third terminal of the control unit 30a, the third terminal of the control unit 30b, and the first terminal of the load circuit 40 via the signal line L3. The third terminal of the ORING FET 20a is connected to the fourth terminal of the control unit 30a via the signal line L4a.

[0016] The third terminal of ORING FET20b is connected to the fourth terminal of control unit 30b via signal line L4b. The fifth terminal of control unit 30a is connected to the fifth terminal of control unit 30b via signal line L5. The sixth terminal of control unit 30a is connected to the sixth terminal of control unit 30b and the second terminal of load circuit 40 via signal line L6.

[0017] Signal line L1a is a signal line to which the voltage of the anode of the parasitic diode of ORING FET20a is applied. Signal line L1b is a signal line to which the voltage of the anode of the parasitic diode of ORING FET20b is applied.

[0018] Signal line L2a is a signal line through which an output voltage indication signal for instructing the output voltage from control unit 30a to power supply 10a propagates. Signal line L2b is a signal line through which an output voltage indication signal for instructing the output voltage from control unit 30b to power supply 10b propagates. Signal line L3 is a signal line to which the voltage of the cathode of the parasitic diode of ORING FET20 is applied.

[0019] Signal line L4a is a signal line to which the gate voltage of ORING FET20a for controlling ORING FET20a to the ON state or the OFF state is applied. Signal line L4b is a signal line to which the gate voltage of ORING FET20b for controlling ORING FET20b to the ON state or the OFF state is applied.

[0020] Signal line L5 is a signal line through which a gate state report signal for reporting the state of the gate voltage of ORING FET20 propagates. Signal line L6 is a signal line through which a load information signal including load information indicating the state of load circuit 40 propagates.

[0021] Signal line L7a is the signal line through which the PS setting signal, input to control unit 30a to determine which system will be ON when under low load, is propagated. Signal line L7b is the signal line through which the PS setting signal, input to control unit 30b to determine which system will be ON when under low load, is propagated. For example, each of the control units 30 is set to primary when a high-level PS setting signal is input. Also, each of the control units 30 is set to secondary when a low-level PS setting signal is input.

[0022] Power supply 10a supplies power to the load circuit 40 via ORING FET 20a. Power supply 10b supplies power to the load circuit 40 via ORING FET 20b.

[0023] ORING FET 20a is turned ON or OFF in response to control by control unit 30a (specifically, the gate voltage of ORING FET 20a applied by control unit 30a). ORING FET 20b is turned ON or OFF in response to control by control unit 30b (specifically, the gate voltage of ORING FET 20b applied by control unit 30b).

[0024] Each of the ORING FETs 20 is an N (Negative) channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor). However, it is also possible to configure a processing system 1 that has the same functionality as the processing system 1 when each of the ORING FETs 20 is a P (Positive) channel MOSFET. Furthermore, each of the ORING FETs 20 may consist of multiple MOSFETs connected in parallel to reduce the ON resistance.

[0025] The control unit 30a controls the ORING FET 20a to an ON state or an OFF state by controlling the gate voltage of the ORING FET 20a. The control unit 30b controls the ORING FET 20b to an ON state or an OFF state by controlling the gate voltage of the ORING FET 20b.

[0026] Figure 2 shows an example of the configuration of a control unit 30 according to some embodiments of the present disclosure. Each of the control units 30 comprises an arithmetic unit 301, a comparison unit 302, a storage unit 303, and an output unit 304, as shown in Figure 2. When it is necessary to distinguish between the processing units of control unit 30a and control unit 30b, the code for the processing unit of control unit 30a is appended with 'a', and the code for the processing unit of control unit 30b is appended with 'b'. This distinguishes between the processing units of control unit 30a and control unit 30b.

[0027] The calculation unit 301a acquires the observed anode potential Va1 and cathode potential Vc1. The calculation unit 301a calculates the potential difference Vac1 between the anode and cathode by subtracting the cathode potential Vc1 from the anode potential Va1 (i.e., by calculating Va1-Vc1).

[0028] The comparison unit 302 compares the load information Dload included in the load information signal with the load state threshold Dloadth, which is pre-stored in the storage unit 303. The load information Dload indicates the amount of current or power actually supplied by the power supply 20 to the load circuit 40. The control unit 30 detects the load state of the power supply 20 based on this load information Dload. An example of load information Dload is the value of the potential difference Vac1 between the anode and cathode, as described above. Under high load conditions, the value of the potential difference Vac1 between the anode and cathode is large. Conversely, under low load conditions, the value of the potential difference Vac1 between the anode and cathode is small. Based on the comparison result, the comparison unit 302 determines whether the information Dload exceeds the load state threshold Dloadth. If the comparison unit 302 determines that the load information Dload exceeds the load state threshold Dloadth, it determines that it is not a low load state. Conversely, if the comparison unit 302 determines that the load information Dload is less than or equal to the load state threshold Dloadth, it determines that it is a low load state.

[0029] The memory unit 303 stores the load state threshold Dloadth. The memory unit 303 stores the output voltage setting value Vset. The memory unit 303 stores the overvoltage threshold Vovth. The memory unit 303 stores the undervoltage threshold Vuvth. The memory unit 303 stores the nominal output value Vnom. The memory unit 303 stores the ON threshold Vfetonth. The memory unit 303 stores the ON threshold Vfetonth.

[0030] The output unit 304 outputs instruction signals to the control unit 30 for adjusting the output voltage of the power supply 10 and instruction signals to turn the ORING FET 20 ON or OFF. In the following description, even if the output unit 304 is not explicitly shown, the instruction signals are output via the output unit 304.

[0031] The processing described above performed by the processing system 1 according to one embodiment of this disclosure is merely an example and is not limited to the processing described above. For example, the processing system 1 may perform the processing described below.

[0032] (Processing performed by the processing system) Next, the processing performed by the processing system 1 according to one embodiment of this disclosure will be described.

[0033] (First process) Figure 3 is a diagram showing an example of the first processing flow of a processing system 1 according to some embodiments of the present disclosure. First, the first processing performed by the processing system 1 will be described with reference to Figure 3. The first processing is a load state determination processing shown by the following steps S1 to S4.

[0034] The load circuit 40 transmits a load information signal to each of the control units 30. The load information signal includes load information Dload. Each of the control units 30 receives the load information signal (step S1). In each of the control units 30, the comparison unit 302 compares the information Dload included in the load information signal with a load state threshold Dloadth that is pre-stored in the storage unit 303. Based on the comparison result, the comparison unit 302 determines whether the load information Dload exceeds the load state threshold Dloadth (step S2).

[0035] If the comparison unit 302 determines that the load information Dload exceeds the load state threshold Dloadth (YES in step S2), it determines that the load circuit 40 is in a non-low load state (step S3). Also, if the comparison unit 302 determines that the load information Dload is less than or equal to the load state threshold Dloadth (NO in step S2), it determines that the load circuit 40 is in a low load state (step S4).

[0036] (Second process) Figure 4 is a diagram showing an example of a second processing flow of processing system 1 according to some embodiments of the present disclosure. Next, the second processing performed by processing system 1 will be described with reference to Figure 4. The second processing is an output voltage adjustment processing shown by the following steps S11 to S26.

[0037] The control unit 30a transmits an output voltage instruction signal to the power supply 10a via the signal line L2a, which specifies the output voltage. The control unit 30b also transmits an output voltage instruction signal to the power supply 10b via the signal line L2b, which specifies the output voltage.

[0038] Power supply 10a receives an output voltage instruction signal from control unit 30a via signal line L2a. Power supply 10a then adjusts the output voltage according to the instruction of the received output voltage instruction signal. Power supply 10b also receives an output voltage instruction signal from control unit 30b via signal line L2b. Power supply 10b then adjusts the output voltage according to the instruction of the received output voltage instruction signal. The output voltage instruction transmitted by each of the control units 30 may be determined as described in steps S11 to S26 below.

[0039] The control unit 30a detects a voltage value Vsense1 on either signal line L1a or signal line L3 (step S11). The comparison unit 302a compares the detected voltage value Vsense1 with an output voltage setting value Vset that is pre-stored in the storage unit 303a. The comparison unit 302a then determines whether the voltage value Vsense1 is higher than the output voltage setting value Vset (step S12).

[0040] If the comparison unit 302a determines that the voltage value Vsense1 is higher than the output voltage setting value Vset (YES in step S12), it compares the voltage value Vsense1 with the overvoltage threshold Vovth that is pre-stored in the storage unit 303. Then, the comparison unit 302a determines whether the voltage value Vsense1 is higher than the overvoltage threshold Vovth (step S13).

[0041] If the comparison unit 302a determines that the voltage value Vsense1 is higher than the overvoltage threshold Vovth (YES in step S13), it determines that the power supply 10a is in an overvoltage abnormal state (step S14). In this case, the output unit 304 outputs an instruction to the power supply 10a via the signal line L2a to stop the voltage output (step S15). At the same time, the output unit 304 sets the voltage on the signal line L4a to a low level to turn the ORING FET 20a OFF (step S16). The power supply 10a stops the voltage output in response to the instruction from the control unit 30a. The ORING FET 20a also turns OFF in response to the low voltage from the control unit 30a.

[0042] Furthermore, if the comparison unit 302a determines that the voltage value Vsense1 is less than or equal to the overvoltage threshold Vovth (NO in step S13), it determines that the output voltage of the power supply 10a is within the normal range (step S17). In this case, the output unit 304 outputs an instruction to the power supply 10a via the signal line L2a to bring the output voltage closer to the output voltage setting value Vset (step S18). The power supply 10a adjusts the output voltage lower in accordance with the instruction from the output unit 304 (step S19). Then, the power supply 10a returns to the process in step S11.

[0043] Furthermore, if the comparison unit 302a determines that the voltage value Vsense1 is less than or equal to the output voltage setting value Vset (NO in step S12), it compares the voltage value Vsense1 with the undervoltage threshold Vuvth that is pre-stored in the storage unit 303. The comparison unit 302a then determines whether the voltage value Vsense1 is lower than the undervoltage threshold Vuvth (step S20).

[0044] If the comparison unit 302a determines that the voltage value Vsense1 is lower than the undervoltage threshold Vuvth (YES in step S20), it determines that the power supply 10a is in an undervoltage abnormal state (step S21). An undervoltage abnormal state is a state in which the output voltage of the power supply 10a falls below the minimum voltage value required by the load circuit 40. For example, an abnormal state occurs when the power supply 10a experiences some kind of abnormality (e.g., component failure or damage to a signal line) and the output voltage drops, even though the control unit 30a has instructed it to output a certain output voltage. In this case, the control unit 30a outputs an instruction to the power supply 10a via the signal line L2a to stop the voltage output (step S22). At the same time, the control unit 30a sets the voltage on the signal line L4a to a low level to turn the ORING FET 20a OFF (step S23). The power supply 10a stops the voltage output in response to the instruction from the control unit 30a. The ORING FET 20a also turns OFF in response to the low voltage from the control unit 30a.

[0045] Furthermore, if the comparison unit 302a determines that the voltage value Vsense1 is greater than or equal to the undervoltage threshold Vuvth (NO in step S20), it determines that the output voltage of the power supply 10a is within the normal range (step S24). In this case, the control unit 30a outputs an instruction to the power supply 10a via the signal line L2a to bring the output voltage closer to the output voltage set value Vset (step S25). The power supply 10a adjusts the output voltage higher in response to the instruction from the control unit 30a (step S26). Then, the power supply 10a returns to the process in step S11.

[0046] In the above-described second processing steps S11 to S26 were explained as being performed by the power supply 10a, ORING FET 20a, and control unit 30a. However, the second processing steps S11 to S26 are also performed by the power supply 10b, ORING FET 20b, and control unit 30b. In this case, by replacing the "a" at the end of the symbols in the above-described steps S11 to S26 with "b", and further replacing "voltage value Vsense1" with "voltage value Vsense2", the second processing performed by the power supply 10b, ORING FET 20b, and control unit 30b can be explained in the same way.

[0047] (Third process) Figure 5 is a diagram showing an example of a third processing flow of processing system 1 according to some embodiments of the present disclosure. Next, the third processing performed by processing system 1 will be described with reference to Figure 5. The third processing is a non-low load processing shown by the following steps S31 to S34.

[0048] In the process of step S3, if the control unit 30 determines that it is in a non-low load state, the control unit 30a will detect the voltage on signal line L1a, and the control unit 30b will detect the voltage on signal line L1b. Furthermore, the output voltage instruction signal that the control unit 30a transmits to the power supply 10a, and the output voltage instruction signal that the control unit 30b transmits to the power supply 10b, will instruct the output voltage values ​​of power supply 10a and power supply 10b to be the same as the nominal output value Vnom that is pre-stored in the storage unit 303a of the control unit 30a and the storage unit 303b of the control unit 30b.

[0049] The control unit 30a observes the anode potential Va1 of the ORING FET 20a via the signal line L1a. The control unit 30a also observes the cathode potential Vc1 of the ORING FET 20a via the signal line L3.

[0050] The calculation unit 301a acquires the observed anode potential Va1 and cathode potential Vc1. The calculation unit 301a calculates the potential difference Vac1 between the anode and cathode by subtracting the cathode potential Vc1 from the anode potential Va1 (i.e., by calculating Va1-Vc1) (step S31). Subsequently, the comparison unit 302a compares the value of the potential difference Vac1 with the ON threshold Vfetonth previously stored in the storage unit 303a. The comparison unit 302a determines whether the potential difference Vac1 is greater than or equal to the ON threshold Vfetonth (step S32).

[0051] If the comparison unit 302a determines that the potential difference Vac1 is greater than or equal to the ON threshold Vfetonth (YES in step S32), the control unit 30a sets the voltage on the signal line L4a to a high level to turn on the ORING FET 20a (step S33). The ORING FET 20a turns on in response to the high-level voltage from the control unit 30a. Then, the control unit 30a returns to the process in step S31.

[0052] Furthermore, if the comparison unit 302a determines that the potential difference Vac1 is less than the ON threshold Vfetonth (NO in step S32), the control unit 30a sets the voltage on the signal line L4a to a low level to turn the ORING FET 20a OFF (step S34). The ORING FET 20a turns OFF in response to the low voltage set by the control unit 30a. Then, the control unit 30a returns to the process in step S31.

[0053] In the above-described third processing steps S31 to S34 were explained as being performed by the power supply 10a, ORING FET 20a, and control unit 30a. However, the above-described third processing steps S31 to S34 are also performed by the power supply 10b, ORING FET 20b, and control unit 30b. In this case, by replacing the "a" at the end of the symbols in the above-described explanation of steps S31 to S34 with "b", and further replacing "anode potential Va1" with "anode potential Va2", "cathode potential Vc1" with "cathode potential Vc2", and "potential difference Vac1" with "potential difference Vac2", the third processing performed by the power supply 10b, ORING FET 20b, and control unit 30b can be explained in a similar manner.

[0054] (Fourth process) Figure 6 shows an example of a fourth processing flow of processing system 1 according to some embodiments of the present disclosure. Figure 7 shows an example of a fifth processing flow of processing system 1 according to some embodiments of the present disclosure. Next, the fourth processing performed by processing system 1 will be described with reference to Figures 6 and 7. Note that the fourth processing flow shown in Figure 6 shows the processing performed by the control unit 30 which is always set as primary when under low load. Also, the fifth processing flow shown in Figure 7 shows the processing performed by the control unit 30 which is set as secondary.

[0055] (Processing performed by the control unit set as primary) First, with reference to Figure 6, the processing performed by the control unit 30, which is set as the primary control unit, will be explained.

[0056] The control unit 30 sends an output voltage instruction signal to the corresponding power supply 10 so that the output voltage becomes the nominal output value Vnom (step S41). The control unit 30 determines whether the corresponding power supply 10 is abnormal or not (step S42). If the control unit 30 determines that the corresponding power supply 10 is not abnormal (NO in step S42), it returns to the process in step S42. If the control unit 30 determines that the corresponding power supply 10 is abnormal (YES in step S42), it turns off the corresponding power supply 10 and the corresponding ORING FET 20 and sets the signal line L5 to a low level (step S43).

[0057] (Processing performed when the control unit is set as secondary) Next, we will describe the processing performed by the control unit 30, which is configured as a secondary control unit.

[0058] The control unit 30 sends an output voltage instruction signal to the corresponding power supply 10 so that the output voltage becomes the minimum nominal output value Vnommin (step S51). The control unit 30 determines whether the corresponding power supply 10 is abnormal or not (step S52).

[0059] If the control unit 30 determines that the corresponding power supply 10 is not abnormal (NO in step S52), it determines whether the signal line L5 is in a low level state (step S53). If the control unit 30 determines that the signal line L5 is not in a low level state (NO in step S53), it returns to the process in step S52.

[0060] Furthermore, if the control unit 30 determines that the signal line L5 is in a low level state (YES in step S53), it sends an output voltage instruction signal to the corresponding power supply 10 so that the output voltage becomes the nominal output value Vnom (step S54). Then, the control unit 30 turns on the corresponding ORING FET 20 (step S55).

[0061] Furthermore, if the control unit 30 determines that the corresponding power supply 10 is abnormal (YES in step S52), it turns the corresponding power supply 10 OFF (step S56).

[0062] (advantage) The processing system 1 according to one embodiment of the present disclosure has been described above. The processing system 1 comprises a plurality of power supplies 10a, 10b, a load circuit 40 common to the plurality of power supplies 10a, 10b, a plurality of ORING FETs (Field Effect Transistors) 20a, 20b, one each provided between the plurality of power supplies 10a, 10b and the load circuit 40, and control units 30a, 30b that, when the load circuit 40 is in a low load state, control only one of the plurality of ORING FETs 20a, 20b to be in an ON state and control all the remaining plurality of ORING FETs to be in an OFF state. With this processing system 1, power can be supplied stably to the load.

[0063] Next, a processing system 700 according to some embodiments of the present disclosure will be described. Figure 8 is a diagram showing an example of the configuration of a processing system 700 according to some embodiments of the present disclosure. As shown in Figure 8, the processing system 700 comprises a plurality of power supplies 701, a load circuit 702 common to the plurality of power supplies 701, a plurality of ORING FETs (Field Effect Transistors) 703, one provided between each of the plurality of power supplies 701 and the load circuit 702, and a control means 704 that controls only one of the plurality of ORING FETs 703 to be in an ON state and controls all the remaining ORING FETs 703 to be in an OFF state when the load circuit 702 is in a low load state.

[0064] The processing system 700 can be implemented, for example, using the functions of the processing system 1 illustrated in Figure 1. The multiple power supplies 701 can be implemented, for example, using the functions of the power supplies 10a and 10b illustrated in Figure 1. The load circuit 702 can be implemented, for example, using the functions of the load circuit 40 illustrated in Figure 1. The multiple ORING FETs 703 can be implemented, for example, using the functions of the ORING FETs 20a and 20b illustrated in Figure 1. The control means 704 can be implemented, for example, using the functions of the control units 30a and 30b illustrated in Figure 1.

[0065] Next, the processing performed by the processing system 700 according to some embodiments of the present disclosure will be described. Figure 9 is a diagram showing an example of the processing flow of the processing system 700 according to some embodiments of the present disclosure. Here, the processing of the processing system 700 will be described with reference to Figure 9.

[0066] In a processing system 700 comprising a plurality of power supplies 701, a load circuit 702 common to the plurality of power supplies 701, and a plurality of ORING FETs 703, one each provided between each of the plurality of power supplies 701 and the load circuit 702, the control means 704 controls only one of the plurality of ORING FETs 703 to be turned on and all the remaining ORING FETs 703 to be turned off when the load circuit 702 is in a low load state (step S101).

[0067] The processing system 700 according to several embodiments of the present disclosure has been described above. This processing system 700 can stably supply power to the load.

[0068] In addition, the order of the processes in each embodiment of this disclosure may be changed, as long as appropriate processing is performed.

[0069] Although each embodiment of this disclosure has been described, the processing system 1, power supply 10, control unit 30, load circuit 40, and other control devices described above may have a computer system inside. The processing steps described above are stored in the form of a program on a computer-readable recording medium, and the processing is performed when the computer reads and executes this program. A specific example of a computer is shown below.

[0070] Figure 10 is a schematic block diagram showing the configuration of a computer according to at least one embodiment. As shown in Figure 10, the computer 5 includes a CPU (Central Processing Unit) 6, main memory 7, storage 8, and interface 9.

[0071] For example, the processing system 1, power supply 10, control unit 30, load circuit 40, and other control devices described above are each implemented in the computer 5. The operation of each processing unit described above is stored in storage 8 in the form of a program. The CPU 6 reads the program from storage 8, loads it into main memory 7, and executes the above processing according to the program. The CPU 6 also allocates memory areas in main memory 7 corresponding to each of the storage units described above, according to the program.

[0072] Examples of storage 8 include HDDs (Hard Disk Drives), SSDs (Solid State Drives), magnetic disks, magneto-optical disks, CD-ROMs (Compact Disc Read Only Memory), DVD-ROMs (Digital Versatile Disc Read Only Memory), and semiconductor memory. Storage 8 may be an internal medium directly connected to the bus of computer 5, or an external medium connected to computer 5 via interface 9 or a communication line. Furthermore, if this program is distributed to computer 5 via a communication line, computer 5, upon receiving the program, may expand it into main memory 7 and execute the above processing. In at least one embodiment, storage 8 is a tangible storage medium that is not temporary.

[0073] Furthermore, the above program may implement some of the functions described above. Moreover, the above program may be a file that can implement the above functions in combination with a program already recorded in the computer system, a so-called differential file (differential program).

[0074] While several embodiments of this disclosure have been described, these embodiments are illustrative and do not limit the scope of the disclosure. These embodiments may be modified in various ways, without departing from the gist of the disclosure.

[0075] Furthermore, some or all of the above embodiments may also be described as follows, but are not limited to these.

[0076] (Note 1) Multiple power sources, A common load circuit is provided for the aforementioned multiple power supplies, Multiple ORING FETs (Field Effect Transistors) are provided, one at a time, between each of the aforementioned multiple power supplies and the aforementioned load circuit. A control means that, when the load circuit enters a low-load state, controls only one of the plurality of ORING FETs to be turned on and controls all the remaining ORING FETs to be turned off, A processing system equipped with the following features.

[0077] (Note 2) The control means is When the load circuit enters a low-load state, the control means controls the output voltage of the power supply connected to each of the ORING FETs that have been controlled to the OFF state to a value equal to the minimum nominal value of the load circuit plus the forward voltage drop value of the ORING FET. The processing system described in Appendix 1.

[0078] (Note 3) The control means is If it is determined that the load information is below a pre-stored load state threshold, it is determined that the load state is low. The processing system described in Appendix 1 or Appendix 2.

[0079] (Note 4) When the load circuit enters a low-load state, the control means that controls only one of the multiple ORING FETs to be turned ON is set in advance as the primary. The processing system described in any one of the appendices 1 through 3.

[0080] (Note 5) When the load circuit enters a low-load state, the control means that controls all remaining ORING FETs to be turned off is set in advance as a secondary, The processing system described in any one of the appendices 1 through 4.

[0081] (Note 6) A processing method performed by a processing system comprising: multiple power supplies; a load circuit common to the multiple power supplies; and multiple ORING FETs (Field Effect Transistors) one at a time provided between each of the multiple power supplies and the load circuit, When the load circuit enters a low-load state, control only one of the multiple ORING FETs to be turned ON, and control all the remaining multiple ORING FETs to be turned OFF. A processing method that includes this.

[0082] (Note 7) When the load circuit enters a low-load state, the output voltage of the power supply connected to each of the ORING FETs, which are controlled to be in the off state, is controlled to a value equal to the minimum nominal value of the load circuit plus the forward voltage drop of the ORING FET. The processing method described in Appendix 6, including the method described therein.

[0083] (Note 8) If it is determined that the load information is below a pre-stored load state threshold, it is determined that the load state is low. The processing method described in Appendix 6 or Appendix 7, including the above.

[0084] (Note 9) The processing system is A control means that is set to primary in advance, which controls only one of the plurality of ORING FETs to be turned on when the load circuit is in a low load state. A processing method described in any one of the appendices 6 to 8, comprising the above.

[0085] (Note 10) The processing system is A control means pre-configured as a secondary control means that controls all remaining of the plurality of ORING FETs to an off state when the load circuit enters a low-load state. A processing method described in any one of the appendices 6 to 9, which includes the following:

[0086] (Note 11) A computer in a processing system comprising multiple power supplies, a load circuit common to the multiple power supplies, and multiple ORING FETs (Field Effect Transistors) one at a time between each of the multiple power supplies and the load circuit, When the load circuit enters a low-load state, control only one of the multiple ORING FETs to be turned ON, and control all the remaining multiple ORING FETs to be turned OFF. A program that executes the command.

[0087] (Note 12) When the load circuit enters a low-load state, the output voltage of the power supply connected to each of the ORING FETs, which are controlled to be in the off state, is controlled to a value equal to the minimum nominal value of the load circuit plus the forward voltage drop of the ORING FET. The program described in Appendix 11 that causes the computer to execute.

[0088] (Note 13) If it is determined that the load information is below a pre-stored load state threshold, it is determined that the load state is low. The program described in Appendix 11 or Appendix 12 that causes the computer to execute the program.

[0089] (Note 14) The processing system is A control means that is set to primary in advance, which controls only one of the plurality of ORING FETs to be turned on when the load circuit is in a low load state. A program described in any one of the appendices 11 to 13, which includes the following:

[0090] (Note 15) The processing system is A control means pre-configured as a secondary control means that controls all remaining of the plurality of ORING FETs to an off state when the load circuit enters a low-load state. A program described in any one of the appendices 11 to 14, which includes the following: [Explanation of Symbols]

[0091] 1,700 processing system 5. Computers 6..CPU 7. Main Memory 8. Storage 9. Interface 10...Power supply 20···ORING FET 30.. Control Unit 40, 702...Load circuit 301...Arithmetic section 302...Comparison Section 303...Storage section 304...Output section 701... Multiple power supplies 703...Multiple ORING FETs 704... Control means

Claims

1. A first power supply, Second power supply and A load circuit common to the first power supply and the second power supply, A plurality of ORING FETs (Field Effect Transistors) are provided, one each between the first power supply and the second power supply and the load circuit, A control means comprising a first control means for controlling the first power supply and a second control means for controlling the second power supply, wherein when the load circuit is in a low load state, the control means controls only one of the plurality of ORING FETs to be in an ON state and controls all of the remaining ORING FETs to be in an OFF state, Equipped with, The first control means and the second control means are To determine which system will be ON under the low load conditions, the input PS setting signal is set to a High level when it is set to a Primary system, and the input PS setting signal is set to a Low level when it is set to a Secondary system. When set to primary, the first or second power supply to be controlled is controlled so that its output voltage reaches the nominal output value. If it is determined that the first or second power supply to be controlled is abnormal, the ORING FET located between the first or second control means that determined the first or second power supply to be abnormal and the first or second power supply that was determined to be abnormal is controlled to the OFF state. Furthermore, the signal on the signal line between the first and second control means is controlled to a Low level. When set as secondary, the first or second power supply to be controlled is controlled so that its output voltage is the lowest nominal output value. If it is determined that the first or second power supply to be controlled is not abnormal and that the signal on the signal line is at a low level, the first or second power supply to be controlled is controlled so that its output voltage is the nominal output value. Processing system.

2. The first control means and the second control means are When the load circuit enters a low-load state, the output voltage of the first or second power supply connected to each of the ORING FETs controlled to the OFF state is controlled to a value equal to the minimum nominal value of the load circuit plus the forward voltage drop value of the ORING FET. The processing system according to claim 1.

3. The first control means and the second control means are If it is determined that the load information is below a pre-stored load state threshold, it is determined that the load state is low. The processing system according to claim 1.

4. When the load circuit enters a low-load state, the first control means or the second control means that controls only one of the plurality of ORING FETs to be turned ON is set in advance as primary. The processing system according to claim 1.

5. When the load circuit enters a low-load state, the first or second control means that controls all remaining ORING FETs to be turned off is set in advance as a secondary. The processing system according to claim 1.

6. A processing method executed by a processing system comprising: a first power supply; a second power supply; a load circuit common to the first and second power supplies; a plurality of ORING FETs (Field Effect Transistors) one each provided between the first and second power supplies and the load circuit; and a control means having a first control means for controlling the first power supply and a second control means for controlling the second power supply, wherein when the load circuit is in a low load state, the control means controls only one of the plurality of ORING FETs to be in an ON state and controls all of the remaining plurality of ORING FETs to be in an OFF state; The first control means and the second control means are To determine which system will be ON under the low load conditions, the input PS setting signal is set to a High level when it is set to a Primary system, and the input PS setting signal is set to a Low level when it is set to a Secondary system. When set to primary, the first or second power supply to be controlled is controlled so that its output voltage reaches the nominal output value. If it is determined that the first or second power supply to be controlled is abnormal, the ORING FET located between the first or second control means that determined the first or second power supply to be abnormal and the first or second power supply that was determined to be abnormal is controlled to the OFF state. Furthermore, the signal on the signal line between the first and second control means is controlled to a Low level. When set as secondary, the first or second power supply to be controlled is controlled so that its output voltage is the lowest nominal output value. If it is determined that the first or second power supply to be controlled is not abnormal and that the signal on the signal line is at a low level, the first or second power supply to be controlled is controlled so that its output voltage is the nominal output value. Processing method.

7. A computer for a processing system comprising: a first power supply; a second power supply; a load circuit common to the first and second power supplies; a plurality of ORING FETs (Field Effect Transistors), one each provided between the first and second power supplies and the load circuit; and a control means having a first control means for controlling the first power supply and a second control means for controlling the second power supply, wherein when the load circuit is in a low load state, the control means controls only one of the plurality of ORING FETs to be in an ON state and controls all of the remaining ORING FETs to be in an OFF state; The first control means and the second control means To determine which system will be ON under the low load conditions, the input PS setting signal is set to a High level when it is set to a Primary system, and the input PS setting signal is set to a Low level when it is set to a Secondary system. When set to primary, the first or second power supply to be controlled is controlled so that its output voltage reaches the nominal output value. If it is determined that the first or second power supply to be controlled is abnormal, the ORING FET located between the first or second control means that determined the first or second power supply to be abnormal and the first or second power supply that was determined to be abnormal is controlled to the OFF state. Furthermore, the signal on the signal line between the first and second control means is controlled to a Low level. When set as secondary, the first or second power supply to be controlled is controlled so that its output voltage is the lowest nominal output value. If it is determined that the first or second power supply to be controlled is not abnormal and that the signal on the signal line is at a low level, the first or second power supply to be controlled is controlled so that its output voltage is the nominal output value. A program that executes the command.

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