Wiring board and method for manufacturing the same, light-emitting board and display device

Abstract

A wiring substrate, a method for manufacturing the same, a light-emitting substrate, and a display device. The wiring substrate (100) includes a base (101), a first conductive layer (102) located on the base and at least within a functional region (E), a second conductive layer (103) located on the first conductive layer and at least within a bonding region (B) and electrically connected to the first conductive layer, and a first insulating layer (105) located on a side of the second conductive layer away from the base and including a main body portion (1051) and an opening (1052). At least one of the first conductive layer and the second conductive layer includes a plurality of electrodes (1033) located within the bonding region and extending along a first direction (D1). The electrodes include a first end (P) adjacent to the functional region in the first direction. A projection of the main body portion of the first insulating layer onto the base at least partially overlaps a projection of the first end of each electrode onto the base.

Description

Technical Field

[0001] The present disclosure relates to the technical field of displays, and particularly to a wiring substrate, a light-emitting substrate including the wiring substrate, a display device, and a method for manufacturing the wiring substrate.

Background Art

[0002] Display devices are generally classified into two types: liquid crystal display devices and organic light-emitting diode display devices. Liquid crystal display devices are widely applied because they have advantages such as being thin, light, having excellent impact resistance, a wide viewing angle, and high contrast. A liquid crystal display device generally includes a display panel and a backlight light source, and the backlight light source is usually disposed on the non-display side of the display panel to provide a light source for the display operation of the display panel. Characteristics such as the contrast, luminance uniformity, and stability of a liquid crystal display device are related to the structure and performance of the backlight light source. In recent years, mini light-emitting diodes (Mini-LEDs) have attracted more and more attention due to their excellent performance and are increasingly applied to backlight light sources.

Summary of the Invention

Means for Solving the Problems

[0003] According to one aspect of the present disclosure, a wiring substrate is provided. The wiring substrate includes a base including a functional region and a bonding region, a first conductive layer located on the base and at least within the functional region, a second conductive layer located on a side of the first conductive layer away from the base and at least within the functional region and electrically connected to the first conductive layer, and a first insulating layer located on a side of the second conductive layer away from the base and including a main body portion and an opening. At least one of the first conductive layer and the second conductive layer includes a plurality of electrodes located within the bonding region and extending along a first direction. Each of the plurality of electrodes includes a first end adjacent to the functional region in the first direction, and a positive projection of the main body portion of the first insulating layer on the base at least partially overlaps a positive projection of the first end of each electrode on the base.

[0004] In some embodiments, the wiring board further includes a second insulating layer located between the first conductive layer and the second conductive layer, the second conductive layer in contact with the first conductive layer through via holes in the second insulating layer.

[0005] In some embodiments, the second conductive layer comprises a first portion and a second portion, the first portion located within the functional region and the second portion located within the bonding region, the second portion comprising a plurality of first electrodes extending along the first direction, each of the plurality of first electrodes comprising the first end.

[0006] In some embodiments, the second conductive layer includes a first surface that moves away from the base, the distance between the portion of the first surface located in the first part and the base is greater than the distance between the portion of the first surface located in the second part and the base, and the orthographic projection of the opening of the first insulating layer on the base at least partially overlaps with the orthographic projection of the second part on the base.

[0007] In some embodiments, the opening in the first insulating layer exposes the remaining portion of each first electrode, excluding the first end.

[0008] In some embodiments, the orthographic projection of the opening of the first insulating layer on the base in the bonding region does not overlap with the orthographic projection of the second insulating layer on the base.

[0009] In some embodiments, the first conductive layer is located only within the functional region, and the orthographic projection of the first conductive layer on the base partially overlaps with the orthographic projection of the first portion of the second conductive layer on the base.

[0010] In some embodiments, the functional region includes the first conductive layer having a second surface facing the second conductive layer and a side surface bonded to the second surface and facing the bonding region, wherein the second conductive layer is in direct contact with the side surface of the first conductive layer.

[0011] In some embodiments, the first conductive layer includes a third portion located within the bonding region, the third portion includes a plurality of second electrodes extending along the first direction, the plurality of first electrodes corresponding one-to-one with the plurality of second electrodes, and the orthographic projection of each of the plurality of first electrodes on the base at least partially overlaps with the orthographic projection of one of the plurality of second electrodes on the base. Each first electrode and the second electrode corresponding to the first electrode are electrically connected to constitute an electrode, and both the electrically connected first electrode and second electrode include the first end.

[0012] In some embodiments, the orthographic projection of the first ends of the first electrode and the second electrode on the base lies within the orthographic projection of the main body of the first insulating layer on the base.

[0013] In some embodiments, the opening in the first insulating layer exposes the remaining portion of each first electrode, excluding the first end.

[0014] In some embodiments, each second electrode includes a plurality of tooth-like structures extending along the first direction and arranged along the second direction, the second direction intersecting the first direction.

[0015] In some embodiments, each of the plurality of tooth-like structures includes a second surface facing the second conductive layer and a side surface attached to the second surface, and the first electrode is in direct contact with the side surface of the tooth-like structure.

[0016] In some embodiments, the bonding region includes a first insulating layer with a plurality of openings, the openings corresponding one-to-one to the plurality of electrodes, and the orthographic projection of each of the openings on the base lies within the orthographic projection of the first electrode of the electrode corresponding to the opening on the base. The electrode further includes a second end opposite to the first end, and the orthographic projection of the second end of the electrode on the base lies within the orthographic projection of the main body of the first insulating layer on the base.

[0017] In some embodiments, the bonding region includes a first insulating layer with a plurality of openings, the openings corresponding one-to-one to the plurality of electrodes, and the orthographic projection of each of the openings on the base partially overlaps with the orthographic projection of the electrode corresponding to the opening on the base. The electrode further includes a second end opposite to the first end, a portion of which is exposed by an opening corresponding to the electrode.

[0018] In some embodiments, the orthographic projection of the second insulating layer on the base does not overlap with the orthographic projection of the first and second electrodes on the base, and the first electrode of each electrode is in direct contact with the second electrode.

[0019] In some embodiments, the bonding region includes a first insulating layer with a plurality of openings, the openings corresponding one-to-one to the plurality of electrodes, the orthographic projection of each of the plurality of openings on the base lies within the orthographic projection of the first electrode of the electrode corresponding to the opening on the base, the electrode further includes a second end opposite to the first end, the orthographic projection of the second end of the electrode on the base lies within the orthographic projection of the main body of the first insulating layer on the base.

[0020] In some embodiments, for each electrode, the orthographic projection of the first electrode on the base lies within the orthographic projection of the second electrode on the base.

[0021] In some embodiments, the main body of the first insulating layer includes a plurality of sub-insulating portions that extend along the first direction and are spaced apart from each other in a second direction intersecting the first direction, wherein the orthographic projections of two adjacent sub-insulating portions on the base partially overlap with the orthographic projections of the electrodes on the base, and the orthographic projections of the first ends of the first and second electrodes on the base partially overlap with the orthographic projections of the two adjacent sub-insulating portions on the base.

[0022] In some embodiments, the second conductive layer is disposed only within the functional region, and the first conductive layer includes a third portion disposed within the bonding region. The third portion includes a plurality of second electrodes extending along the first direction, and each of the plurality of second electrodes includes the first end.

[0023] In some embodiments, the second insulating layer includes a plurality of via holes. The plurality of via holes correspond one-to-one to the plurality of second electrodes, and the orthographic projection of each of the plurality of via holes on the base is within the orthographic projection of the second electrode corresponding to the via hole on the base.

[0024] In some embodiments, the main body portion of the first insulating layer includes a plurality of sub-insulating portions extending along the first direction and spaced apart from each other in a second direction intersecting the first direction. The orthographic projections of two adjacent sub-insulating portions among the plurality of sub-insulating portions on the base partially overlap with the orthographic projection of the second electrode on the base, respectively. The orthographic projection of the first end of the second electrode on the base partially overlaps with the orthographic projections of the two adjacent sub-insulating portions on the base.

[0025] According to another aspect of the present disclosure, a light-emitting substrate is provided. The light-emitting substrate includes the wiring substrate according to any one of the above embodiments, a plurality of light-emitting elements provided within the functional region, and a circuit board provided within the bonding region.

[0026] According to still another aspect of the present disclosure, a display device is provided. The display device includes the wiring substrate according to any one of the above embodiments or the light-emitting substrate according to any one of the above embodiments.

[0027] According to a further aspect of the present disclosure, a method for manufacturing a wiring board is provided. The manufacturing method includes the steps of: providing a base including a functional region and a bonding region; applying a first conductive film on the base and patterning the first conductive film through a first mask to form a first conductive layer located at least within the functional region; applying a second conductive film on a side of the first conductive layer away from the base and patterning the second conductive film through a second mask to form a second conductive layer located at least within the functional region and electrically connected to the first conductive layer; applying a first insulating film on a side of the second conductive layer away from the base and patterning the first insulating film through a third mask to form a first insulating layer including a main body portion and an opening. At least one of the first conductive layer and the second conductive layer includes a plurality of electrodes located within the bonding region and extending along a first direction. Each of the plurality of electrodes includes a first end adjacent to the functional region in the first direction. A positive projection of the main body portion of the first insulating layer on the base at least partially overlaps a positive projection of the first end of each electrode on the base.

[0028] In some embodiments, after the step of forming the first conductive layer on the base, the method further includes the steps of: applying a second insulating film on a side of the first conductive layer away from the base and patterning the second insulating film through a fourth mask to form a second insulating layer; and forming the second conductive layer on a side of the second insulating layer away from the base.

[0029] To more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required for use in the embodiments are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can also obtain other drawings based on these drawings without creative labor.

Brief Description of the Drawings

[0030] [Figure 1] A structural schematic diagram of a wiring board in the related art is shown. [Figure 2A] A schematic plan view of a partial structure of a wiring board according to an embodiment of this disclosure is shown. [Figure 2B] A schematic cross-sectional view is shown, cut along line AA' in Figure 2A. [Figure 2C] A simplified schematic diagram of region II in Figure 2A is shown. [Figure 3A] This shows a magnified image of the local structure of a wiring board in a related technology. [Figure 3B] This shows a magnified image of the local structure of a wiring board in a related technology. [Figure 4] This diagram shows a schematic planar structure of a functional region of a wiring board according to an embodiment of the present disclosure. [Figure 5A] A schematic plan view of a partial structure of a wiring board according to an embodiment of this disclosure is shown. [Figure 5B] Figure 5A shows a schematic cross-sectional view taken along line BB'. [Figure 6A] A schematic plan view of a partial structure of a wiring board according to an embodiment of this disclosure is shown. [Figure 6B] Figure 6A shows a schematic cross-sectional view taken along line CC'. [Figure 7A] A schematic plan view of a partial structure of a wiring board according to an embodiment of this disclosure is shown. [Figure 7B] Figure 7A shows a schematic cross-sectional view taken along line DD'. [Figure 8A] A schematic plan view of a partial structure of a wiring board according to an embodiment of this disclosure is shown. [Figure 8B] Figure 8A shows a schematic cross-sectional view taken along line EE'. [Figure 9A] A schematic plan view of a partial structure of a wiring board according to an embodiment of this disclosure is shown. [Figure 9B] Figure 9A shows a schematic cross-sectional view taken along line FF'. [Figure 10A] A schematic plan view of a partial structure of a wiring board according to an embodiment of this disclosure is shown. [Figure 10B] Figure 10A shows a schematic cross-sectional view taken along line GG'. [Figure 11A]A schematic plan view of a partial structure of a wiring board according to an embodiment of this disclosure is shown. [Figure 11B] Figure 11A shows a schematic cross-sectional view taken along line HH'. [Figure 12] A block diagram of a light-emitting substrate according to an embodiment of this disclosure is shown. [Figure 13] A block diagram of a display device according to an embodiment of this disclosure is shown. [Figure 14] A flowchart of a method for manufacturing a wiring board according to an embodiment of this disclosure is shown. [Modes for carrying out the invention]

[0031] Hereinafter, the technical solutions in the embodiments of this disclosure will be clearly and completely described, with reference to the drawings of the embodiments. Clearly, the embodiments described are only a part of the embodiments of this disclosure, not all of them. All other embodiments obtained by a person skilled in the art without requiring any creative work based on the embodiments of this disclosure are all within the scope of this disclosure.

[0032] Figure 1 shows a wiring board 10 in the related technology, which includes a base 11, a first conductive layer 12, a first sub-insulating layer 141, a second sub-insulating layer 142, a second conductive layer 13, and an insulating layer 15. The surface of the area of ​​the second conductive layer 13 that is exposed away from the base 11 needs to be treated to prevent oxidation, for example, by treating it using the electroless nickel / immersion gold method to grow a desired nickel gold layer 17 on the surface, thereby improving the oxidation resistance and / or connection reliability of the second conductive layer 13. Specifically, in the electroless nickel / immersion gold process, the wiring board 10 is first pickled, and then the wiring board 10 is treated with Pd 2+ When placed in an activating solution containing Pd, the metal (e.g., Cu) in the region where the surface of the second conductive layer 13 is exposed becomes Pd in ​​the activating solution. 2+ It undergoes a substitution reaction with Cu 2+Palladium (Pd) is generated, and the Pd adheres to the surface of the second conductive layer 13 that separates from the base 11, forming a palladium layer. Subsequently, the wiring board 10 is placed in a solution mainly composed of nickel sulfate, sodium hypophosphite (a reducing agent that reduces nickel ions to metallic nickel), and a complexing agent to generate a phosphonic nickel alloy layer on the surface of the pads. However, since the phosphonic nickel alloy layer is still oxidized, and welding between the solder and the oxidized phosphonic nickel alloy layer is difficult and not reliable, it is necessary to finally immerse the wiring board 10 in a gold ion-containing solution to form an immersion gold layer on the surface of the phosphonic nickel alloy layer. The gold particles in the immersion gold layer fill the gaps in the electroless nickel / immersion gold layer, reducing the oxidation probability of the phosphonic nickel alloy layer, thereby reducing the degree of oxidation of the exposed area of ​​the second conductive layer 13. As a result, the surface of the exposed area of ​​the second conductive layer 13 has a nickel-gold layer 17 (including the above-mentioned phosphonic nickel alloy layer and immersion gold layer).

[0033] In the region I enclosed by the dotted rectangular frame in Figure 1, the first sub-insulating layer 141 and the second sub-insulating layer 142 can cover the surface of the first conductive layer 12 and prevent oxidation when they are continuous film layers without via holes. In order to provide a good interface for forming the nickel-gold layer 17 on the surface of the second conductive layer 13, the insulating layer 15 must be etched to form via holes 16 to expose the second conductive layer 13, and a certain degree of etching must also be performed on the surface of the second conductive layer 13 away from the base 11. Since the surface of the second conductive layer 13 away from the base 11 needs to be further etched, the etching time increases compared to etching only the insulating layer 15. The thickness of the first sub-insulating layer 141 and the second sub-insulating layer 142 is usually thin, but when the etching time increases, the first sub-insulating layer 141 and the second sub-insulating layer 142 are inevitably over-etched, thereby forming unnecessary via holes 19 in the first sub-insulating layer 141 and the second sub-insulating layer 142. Due to via holes 16 in the insulating layer 15 and unnecessary via holes 19 in the first sub-insulating layer 141 and the second sub-insulating layer 142, the surface of the first conductive layer 12 away from the base 11 is partially exposed, and the nickel-gold layer 18 grows abnormally at the exposed surface of the first conductive layer 12. This abnormally grown nickel-gold layer 18 causes problems such as short circuits between film layers and damage to the surface flatness of the insulating layer 15, thereby significantly affecting the reliability of the wiring board 10.

[0034] Some embodiments of the present disclosure provide an improved wiring board that can solve the problem of abnormal growth of the nickel-gold layer, at least within the bonding region.

[0035] Figure 2A shows a schematic plan view of a portion of the wiring board 100, and Figure 2B shows a cross-sectional view cut along line AA' of Figure 2A. As shown in Figures 2A and 2B, the wiring board 100 includes a base 101 including a functional region E and a bonding region B; a first conductive layer 102 located on the base 101 and at least within the functional region E; a second conductive layer 103 located on the side of the first conductive layer 102 away from the base 101 and at least within the functional region E, and electrically connected to the first conductive layer 102; and a first insulating layer 105 located on the side of the second conductive layer 103 away from the base 101 and including a body portion 1051 and an opening 1052. A plurality of electrodes 150 are arranged in bonding region B, each extending along a first direction D1 and spaced apart along a second direction D2 intersecting the first direction D1. At least one of the first conductive layer 102 and the second conductive layer 103 includes the plurality of electrodes 150, and each of the plurality of electrodes 150 includes a first end P adjacent to the functional region E in the first direction D1. The orthographic projection of the main body 1051 of the first insulating layer 105 on the base 101 at least partially overlaps with the orthographic projection of the first end P of each electrode 150 on the base 101. The exposed surface areas of the electrodes 150 function as bonding electrodes 107. The relative positional relationships of the first conductive layer 102, the second conductive layer 103, and the first insulating layer 105 described herein are applicable not only to the wiring board 100 but also to the wiring boards described in other embodiments of this disclosure, which will be described in detail later.

[0036] It should be noted that, in this specification, the term "body portion 1051 of the first insulating layer 105" refers to the physical portion of the first insulating layer 105, which is made of a suitable insulating material, and the term "opening 1052 of the first insulating layer 105" refers to the hollow via hole of the first insulating layer 105, which does not have any physical material in the opening 1052. The body portion 1051 and the opening 1052 constitute the first insulating layer 105. Furthermore, the term "functional region" refers to the region of the base 101 for arranging functional components (e.g., light-emitting elements), and the term "bonding region" refers to the region of the base 101 for arranging electrodes 150, which are used to bond to a circuit board, and when the circuit board has a gold finger structure, the width of each electrode in the second direction of the multiple electrodes 150 in the bonding region is basically the same, and is slightly larger than, for example, the width in the second direction of the gold finger structure.

[0037] The inventors of the present application have discovered that abnormal growth of electroless nickel / immersion gold is likely to occur at the first end P of the electrode 150 within the bonding region B. Therefore, in the embodiments of the present application, by at least partially overlapping the orthographic projection of the main body portion 1051 of the first insulating layer 105 on the base 101 with the orthographic projection of the first end P of each electrode 150 on the base 101, the main body portion 1051 of the first insulating layer 105 can cover at least a portion of the first end P of the electrode 150. In this way, even when the first insulating layer 105 is etched to form an opening 1052, the main body portion 1051 of the first insulating layer 105 has a shielding and protective effect on the first end P of the electrode 150, so that the surface of the first end P of the electrode 150 is not exposed, thereby reducing and even avoiding the occurrence of abnormal growth of electroless nickel / immersion gold at the first end P of the electrode 150.

[0038] Specifically, referring to Figures 2A and 2B, the first conductive layer 102 of the wiring board 100 is located only within the functional region E and not within the bonding region B, and the second conductive layer 103 includes a first portion 1031 located within the functional region E and a second portion 1032 located within the bonding region B. The second portion 1032 of the second conductive layer 103 includes a plurality of first electrodes 1033 extending along a first direction D1, and the exposed surface region of each first electrode 1033 functions as a bonding electrode 107. The first electrode 1033 includes a first end P. The orthogonal projection of the first conductive layer 102 on the base 101 does not overlap with the orthogonal projection of the first electrode 1033 on the base 101. In some embodiments, the length L1 of the first end P of the first electrode 1033 along the first direction D1 is 30 to 60 microns, and the length L2 of the first electrode 1033 along the first direction D1 is 1050 to 1100 microns. In some embodiments, the ratio of length L1 to length L2 is between 2% and 6%.

[0039] Figure 2C shows a simplified schematic diagram of region II in Figure 2A, showing only the relative positional relationship between the first conductive layer 102 and the second conductive layer 103. The first conductive layer 102 includes a drive voltage signal line VLED, a common voltage signal line 111 (shown in Figure 4), and several other signal lines. The drive voltage signal line VLED and / or the common voltage signal line 111 extend substantially along a first direction D1, with one end of the drive voltage signal line VLED and / or the common voltage signal line 111 extending to any point away from the bonding region B of the functional region E of the wiring board 100, and the other end connected to a plurality of first electrodes 1033 extending from the bonding region B toward the functional region E. The first conductive layer 102 shown in Figure 2C can represent a drive voltage signal line VLED or a common voltage signal line 111, and is in direct contact with the first part 1031 of the second conductive layer 103 within the functional region E. Since the line width of the drive voltage signal line VLED or common voltage signal line 111 is much larger than the line width of the first electrode 1033, the other end of the drive voltage signal line VLED or common voltage signal line 111 may be electrically connected to correspond to a plurality of first electrodes 1033.

[0040] The inventors of this application have discovered that in related art, abnormal growth of electroless nickel / immersion gold is likely to occur because the surface of the bonding electrode 107 is exposed within the bonding region B, and there is a step between the position where the signal line in the first conductive layer 102 is connected to the electrode and the bonding electrode 107. However, in the embodiments of this disclosure, since the first conductive layer 102 is located only within the functional region E and not within the bonding region B, abnormal growth of electroless nickel / immersion gold within the bonding region B is avoided for the drive voltage signal line VLED and the common voltage signal line 111 formed by the first conductive layer 102. As can be seen from Figures 2A to 2C, the orthographic projection of the first conductive layer 102 on the base 101 partially overlaps with the orthographic projection of the first part 1031 of the second conductive layer 103 on the base 101, while the orthographic projection of the first conductive layer 102 on the base 101 does not overlap with the orthographic projection of the first electrode 1033 of the second part 1032 of the second conductive layer 103 on the base 101. By placing the first conductive layer 102 only within the functional region E and not within the bonding region B, the occurrence of the abnormal growth phenomenon of electroless nickel / immersion gold can be avoided when etching the first insulating layer 105 to form an opening 1052 located within the bonding region B, regardless of whether the etching time increases or not.

[0041] In some embodiments, the wiring board 100 may further include a second insulating layer 104 located between the first conductive layer 102 and the second conductive layer 103, wherein a first portion 1031 of the second conductive layer 103 is electrically connected to the first conductive layer 102 via a via hole 1043 in the second insulating layer 104. Since the second insulating layer 104 is located only in the functional region E and not in the bonding region B, the orthographic projection of the second insulating layer 104 on the base 101 does not overlap with the orthographic projection of the first electrode 1033 on the base 101. When multiple superimposed insulating layers are located in the bonding region B, the adhesion force between the multiple insulating layers is usually low, making it easy for the insulating layer to peel off. The probability of such peeling occurring increases significantly when the superimposed thickness of the multiple insulating layers exceeds a certain threshold (e.g., 6000 Å). To avoid the problem of film layer detachment within bonding region B, as shown in Figure 2A, the main body portion 1044 of the second insulating layer 104 is not provided in the region between any two adjacent first electrodes 1033 of the plurality of first electrodes 1033 in the light-emitting substrate 100. Therefore, in the region between any two adjacent first electrodes 1033 of the plurality of first electrodes 1033, the orthographic projection of the main body portion 1051 of the first insulating layer 105 on the base 101 does not overlap with the orthographic projection of the main body portion 1044 of the second insulating layer 104 on the base 101. In this way, the overlap between the main body portion 1051 of the first insulating layer 105 and the main body portion 1044 of the second insulating layer 104 in bonding region B can be reduced, thereby mitigating and even avoiding the detachment phenomenon of the first insulating layer 105 and the second insulating layer 104 in bonding region B.

[0042] As shown in Figure 2B, the second conductive layer 103 includes a first portion 1031 located within the functional region E and a second portion 1032 located within the bonding region B. The second conductive layer 103 includes a first surface that separates from the base 101, and this first surface is stepped. Specifically, the portion of the first surface located within the first portion 1031 can be denoted as surface S11, the portion located within the second portion 1032 can be denoted as surface S13, and the portion of the first surface located between surfaces S11 and S13 and connecting surfaces S11 and S13 can be denoted as surface S12. Since surface S12 is an inclined surface, the distance d1 between the portion S11 located within the first portion 1031 of the first surface and the base 101 is greater than the distance d2 between the portion S13 located within the second portion 1032 of the first surface and the base 101. The main body portion 1051 of the first insulating layer 105 is attached to at least the portion located within the first end P of the surface S11, surface S12, and surface S13 of each first electrode 1033, thereby providing better coverage and protection to the first portion 1031 of the second conductive layer 103 and the first end P of the first electrode 1033. The orthographic projection of the opening 1052 of the first insulating layer 105 on the base 101 at least partially overlaps with the orthographic projection of the second portion 1032 on the base 101. In some embodiments, the orthographic projection of the opening 1052 of the first insulating layer 105 on the base 101 does not overlap with the orthographic projection of the second insulating layer 104 on the base 101. The flexible printed circuit board may be bonded to the region excluding the first end P of the first electrode 1033, i.e., the flexible printed circuit board is bonded and connected to the bonding electrode.

[0043] In some embodiments, the first conductive layer 102 includes a second surface S21 facing the second conductive layer 103 and a side surface S22 bonded to the second surface S21 and facing the bonding region B, the second insulating layer 104 covers a portion of the second surface S21 of the first conductive layer 102 but does not cover the side surface S22 of the first conductive layer 102, and the second conductive layer 103 is in direct contact with the side surface S22 of the first conductive layer 102 via via holes 1043 in the second insulating layer 104. The second insulating layer 104 may be a single film layer or a laminate comprising multiple film layers. In one example, the second insulating layer 104 includes a first sub-insulating layer 1041 and a second sub-insulating layer 1042. In the direction perpendicular to the base 101, the thickness of the second insulating layer 104 is usually thinner than the thickness of the first conductive layer 102 (for example, the thickness of the first conductive layer 102 in the direction perpendicular to the base 101 is 1.8 μm, the thickness of the first sub-insulating layer 1041 in the direction perpendicular to the base 101 is 0.24 μm, and the thickness of the second sub-insulating layer 1042 in the direction perpendicular to the base 101 is 0.15 μm). In related technologies, the second insulating layer 104 needs to cover the side surface S22 of the first conductive layer 102, and because there is a large step between the second surface S21 of the first conductive layer 102 and the surface of the film layer below, the second insulating layer 104 is prone to rupture from the second surface S21 of the first conductive layer 102 to the position connected to the side surface S22, and as a result, the second insulating layer 104 cannot completely cover and protect the first conductive layer 102. Furthermore, after the second insulating layer 104 is fractured, the subsequently formed second conductive layer 103 cannot achieve good contact with the film layer below at the fracture site, leading to the problem of the second conductive layer 103 falling off. Moreover, after the second insulating layer 104 is fractured, the surface of a portion of the first conductive layer 102 is exposed, which causes oxidation and the generation of irregularly shaped metal oxides. This reduces the consistency and flatness of the film layer of the first conductive layer 102, and when the second conductive layer 103 comes into direct contact with the region of the first conductive layer 102 where irregularly shaped oxides have been generated, the second conductive layer 103 is prone to bulging at that location, further increasing the likelihood of the second conductive layer 103 falling off. Therefore, when the second insulating layer 104 is positioned on the side surface S22 of the first conductive layer 102, the phenomenon of the second conductive layer 103 falling off is likely to occur.Figure 3A shows that in the related technology, the second conductive layer 103 and the second insulating layer (PVX1-2) detach to the side surface of the first conductive layer (Cu1), and the second conductive layer (Cu2) and the first conductive layer (Cu1) detach to the side surface of the first conductive layer (Cu1). Figure 3B shows that in the related technology, a step exists in the first conductive layer 12, causing the first sub-insulating layer 141 or the second sub-insulating layer 142 to crack, and further, the first conductive layer 12 is oxidized at the corresponding location to generate an oxide with an irregular shape (tip), ultimately causing the second conductive layer 13 to bulge.

[0044] In the wiring board 100 provided by the embodiment of this disclosure, the second insulating layer 104 does not cover the side surface S22 of the first conductive layer 102, and the second conductive layer 103 is in direct contact with the side surface S22 of the first conductive layer 102 via via holes 1043 within the second insulating layer 104. In this way, the second insulating layer 104 is not broken, and as a result, the first electrode 1033 of the second conductive layer 103 does not experience film layer detachment from the second insulating layer 104 due to contact with a broken second insulating layer 104. Furthermore, because the second insulating layer 104 is not broken, the side surface S22 of the first conductive layer 102 does not oxidize due to surface exposure and have an irregular surface shape, thereby preventing the second conductive layer 103 from bulging, and further preventing the film layer detachment problem between the first electrode 1033 of the second conductive layer 103 and the first conductive layer 102.

[0045] In some embodiments, the first conductive layer 102 may be a MoNb / Cu / MoNb laminate. In alternative embodiments, the first conductive layer 102 may be a Mo / Cu / Mo laminate. In some embodiments, the second conductive layer 103 may be a MoNb(300Å) / Cu(6000~9000Å) / MoNb(300Å) laminate. In alternative embodiments, the second conductive layer 103 may be a Mo(300Å) / Cu(6000~9000Å) / Mo(17~30Å) laminate. The thickness of the first conductive layer 102 is usually greater than the thickness of the second conductive layer 103.

[0046] As shown in Figure 2B, in some embodiments, the wiring board 100 may further include a buffer layer 106 located between the base 101 and the first conductive layer 102. The buffer layer 106 has a planarizing effect and can improve the adhesion between the first conductive layer 102 and the base 101.

[0047] Figures 2A to 2C mainly show the arrangement of the wiring board 100 in bonding area B. To help the reader understand the overall arrangement of the wiring board 100 more clearly, Figure 4 shows an example of the arrangement of the wiring board 100 in functional area E.

[0048] The functional region of the wiring board 100 is provided with groups of pads to be bonded and connected to tens of thousands of electronic components. Referring to Figure 4, the wiring board 100 includes, in the functional region E, a first group of pads 102 located on the base 101 and including a power supply pad Pwr and an output pad Out, which is selectively coupled to a microdriver chip 002; a power signal line 103 located on the same side of the base 101 together with the first group of pads 102 and coupled to the power supply pad Pwr; and a second group of pads 104 located on the same side of the base 101 together with the first group of pads 102, which is selectively coupled to each electronic component 003. The region of the second conductive layer 103 located in the functional region E and with its surface exposed constitutes the first group of pads 102 and the second group of pads 104. Specifically, the first insulating layer 105 includes an opening 1052 in the functional region E, which exposes a portion of the second conductive layer 103 to function as a pad. The first pad group 102 can be bonded to the microdrive chip 002 by a reflow soldering process with the assistance of solder, and the second pad group 104 can be bonded to the light-emitting element 003 by a reflow soldering process with the assistance of solder. The portion of the second conductive layer 103 exposed by the opening 1052 in the bonding region B functions as a bonding electrode (e.g., the portion of the first electrode 1033 excluding the first end P), and this bonding electrode achieves a bonding connection with the gold finger structure of the circuit board (e.g., FPC) by a hot press process with the assistance of an anisotropic conductive adhesive. In some embodiments, the base 101 includes a plurality of pad regions P, each pad region P including a plurality of cascaded first pad groups 102 and a plurality of second pad groups 104 bonded to each first pad group 102, respectively. Selectively, within a single pad region P, multiple cascaded first pad groups 102 are arranged in an array along a first direction D1 and / or a second direction D2, but this is not limited to such arrangements. Figure 4 schematically illustrates an example where multiple cascaded first pad groups 102 within a single pad region P are arranged in a single row.In some embodiments, the power signal line 103 may be coupled to the power supply pads Pwr of a plurality of first pad groups 102 arranged along a first direction D1 within the pad area P and cascaded together, thereby reducing the winding design of the power signal line 103, thereby reducing the resistance of the power signal line 103 and further reducing the loss of pulse width modulated signals in the power signal line 103. In some embodiments, the wiring board 100 may further include a first connection lead 106, and the power signal line 103 may include a plurality of subsegments 103', where two subsegments 103' adjacent to each other in the first direction D1 may be connected to each other via the first connection lead 106 so that the same power signal line 103 supplies power to the power supply pads Pwr of a plurality of first pad groups 102 arranged along a first direction D1 and cascaded together within the same pad area P. Optionally, the first connection lead 106 and the subsegments 103' are integrated into a single structure. In some embodiments, the first pad group 102 further includes an address pad Di and a ground pad Gnd, and the address pad Di and power supply pad Pwr belonging to the same first pad group 102 are spaced apart in the second direction D2 and spaced apart from the output pad Out in the first direction D1, and the ground pad Gnd and power supply pad Pwr are spaced apart in the first direction D1 and spaced apart from the output pad Out in the second direction D2. Exemplarily, the output pad Out is located in the upper left corner of the first pad group 102, the address pad Di is located in the lower left corner of the first pad group 102, the ground pad Gnd is located in the upper right corner of the first pad group 102, and the power supply pad Pwr is located in the lower right corner of the first pad group 102. Each first pad group 102 may be coupled to a microdrive chip 002, and each second pad group 104 may be coupled to a plurality of electronic components 003. In some embodiments, an address pad Di can receive an address signal to strobe a microdriver chip 002 to the corresponding address. A power supply pad Pwr can provide a first operating voltage and communication data to the microdriver chip 002, which can be used to control the luminescence brightness of the corresponding light-emitting element.The output pad Out can output a relay signal and a drive signal, respectively, within different time periods. The relay signal is an address signal provided to the address pad Di in the next stage's first pad group 102, and the drive signal is a drive current used to drive and illuminate a light-emitting element coupled to the first pad group 102 where the output pad Out is located. The ground pad Gnd receives a common voltage signal. In some embodiments, the arrangement of the power supply pad Pwr, output pad Out, ground pad Gnd, and address pad Di is the same in each first pad group 102, thereby simplifying the wiring paths between the first pad groups 102 cascaded together within the same pad region P and avoiding the generation of many windings.

[0049] In some embodiments, the wiring board 100 may further include an address signal line 108, which may be coupled to the address pad Di of the first stage of the first pad group 102 in the pad area P, thereby allowing each pad area P to receive an address signal provided by the address signal line 107 via the address pad Di of the first stage of the first pad group 102. In some embodiments, the wiring board 100 may further include a cascading connection line 109, which is arranged to connect the output pad Out of the nth stage of the first pad group 102 belonging to the same pad area P to the address pad Di of the (n+1)th stage of the first pad group 102, where n is a positive integer, and the relay signal output by the output pad Out of the nth stage of the first pad group 102 is provided to the address pad Di of the (n+1)th stage of the first pad group 102 via the cascading connection line 109. In some embodiments, the wiring board 100 may further include a feedback signal line 110, which is coupled to the output pad Out of the final stage of the first pad group 102 in the pad region P to form a circuit that transports an address signal within the pad region P. In some embodiments, the wiring board 100 may further include a common voltage signal line 111, which is coupled to the ground pad Gnd of all the first pad groups 102 in the pad region P. In some embodiments, the wiring board 100 may further include a drive voltage signal line VLED for coupling to an electronic component 003.

[0050] Using Figure 4 as an example, within the functional region E of the wiring board, the first conductive layer 102 is arranged to realize the power signal line 103, the first connection lead line 106, the second connection lead line 107, the address signal line 108, the cascade connection line 109, the feedback signal line 110, the common voltage signal line 111, the drive voltage signal line VLED, the connection line connecting the first pad group and the second pad group, and the connection line (not shown) connecting the second pad group and the second pad group. During the manufacturing process, the same mask plate is used, and the first conductive layer 102 is patterned in a single patterning process to form these signal lines.

[0051] To make it clearer, in some other embodiments, within the functional area E of the wiring board, the first conductive layer 102 is arranged only to realize the power signal line 103, the address signal line 108, the feedback signal line 110, the common voltage signal line 111, and the drive voltage signal line VLED, and the second conductive layer 103 is arranged to realize the first connection lead line 106, the second connection lead line 107, the cascade connection line 109, the connection line connecting the first pad group and the second pad group, and the connection line connecting the second pad group and the second pad group.

[0052] Figure 5A shows a schematic plan view of the substructures in bonding region B and functional region E of the wiring board 200, and Figure 5B shows a cross-sectional view cut along line BB' of Figure 5A. For brevity, the similarities between wiring board 200 and wiring board 100 will be omitted from the explanation, and only the differences between wiring board 200 and wiring board 100 will be described below.

[0053] The wiring board 200 shown in Figure 5A includes a base 101, a first conductive layer 102, a second conductive layer 103, a first insulating layer 105, and a second insulating layer 104. Unlike the wiring board 100, the first conductive layer 102 of the wiring board 200 is located within a functional region E and a bonding region B, and the first conductive layer 102 includes a third portion 1022 located within the bonding region B, the third portion 1022 includes a plurality of second electrodes 1023 that extend along a first direction D1 and are spaced apart along a second direction D2. The second conductive layer 103 includes a first portion 1031 located within the functional region E and a second portion 1032 located within the bonding region B, the second portion 1032 includes a plurality of first electrodes 1033 that extend along the first direction D1. Multiple first electrodes 1033 correspond one-to-one with multiple second electrodes 1023, and the orthographic projection of each first electrode 1033 on the base 101 lies within the orthographic projection of the corresponding second electrode 1023 on the base 101. Each first electrode 1033 and its corresponding second electrode 1023 are electrically connected to form an electrode, and the exposed surface area of ​​the electrode constitutes a bonding electrode 107. Both the first electrodes 1033 and the second electrodes 1023 include a first end P approaching the functional region E. The orthographic projections of the first ends P of the first electrodes 1033 and the second electrodes 1023 on the base 101 lies within the orthographic projection of the main body 1051 of the first insulating layer 105 on the base 101. In some embodiments, an opening 1052 in the first insulating layer 105 exposes the remaining area of ​​each first electrode 1033 excluding its first end P.

[0054] The drive voltage signal line VLED and the common voltage signal line 111, which belong to the first conductive layer 102 and are located in functional region E, are bonded to the electrode at the first end P of the electrode. As described above, in related technologies, the drive voltage signal line VLED and the common voltage signal line 111 are prone to abnormal growth of electroless nickel / immersion gold because their surfaces are exposed at the first end P. In the wiring board 200 provided by embodiments of the present disclosure, the electrode includes a second electrode 1023 and a first electrode 1033 located on the side of the second electrode 1023 away from the base 101, and the orthographic projection of the first end P of the electrode on the base 101 is within the orthographic projection of the body portion 1051 of the first insulating layer 105 on the base 101, that is, the body portion 1051 of the first insulating layer 105 and the second electrode 1023 are separated by at least the distance of the first electrode 1033. With this arrangement, when etching the first insulating layer 105, even if the etching time increases, at most the surface of the first electrode 1033 that is separated from the base 101 may be over-etched. However, the first electrode 1033, which has a thicker thickness (compared to the thickness of the second insulating layer 104), shields and protects the second electrode 1023, so the first end P of the second electrode 1023 is not etched, and as a result the surface of the first end P of the second electrode 1023 is not exposed. Correspondingly, that is, the first end of the second electrode 1023 of each signal line is not exposed, and as a result abnormal growth of electroless nickel / immersion gold does not occur.

[0055] In some embodiments, the length L1 of the first end P of the first electrode 1033 along the first direction D1 is 30 to 60 microns, the length L2 of the first electrode 1033 along the first direction D1 is 1050 to 1100 microns, and the length L3 of the second electrode 1023 along the first direction D1 is 1066 to 1116 microns. In some embodiments, the ratio of length L1 to length L2 is between 2% and 6%, and the ratio of length L1 to length L3 is between 2% and 6%.

[0056] In some embodiments, the second insulating layer 104 includes a plurality of via holes 1043 within the bonding region B, where the plurality of via holes 1043 correspond one-to-one with a plurality of electrodes, and the orthographic projection of each via hole 1043 on the base 101 lies within the orthographic projection of the first electrode 1033 on the base 101 of the corresponding electrode. As shown in Figure 5B, in one example, the second insulating layer 104 can extend along a first direction D1 to cover a portion of the surface of the second electrode 1023 located in the bonding region B of the first conductive layer 102, and can cover and protect a portion of the surface of the first end P approaching the functional region E of the second electrode 1023, for example, where W1 is approximately 22 μm.

[0057] It should be noted that Figure 5A only shows a schematic diagram of the structure of a portion of the wiring board 200, but this schematic diagram does not show the electrical connection relationship between the third part 1022 and the various signal lines located in the functional area E. In reality, in the wiring board 200, the third part 1022 is electrically connected to various signal lines located in the first conductive layer 102 (e.g., power signal line 103, address signal line 108, feedback signal line 110, common voltage signal line 111, and drive voltage signal line VLED).

[0058] Figure 6A shows a schematic plan view of the substructures in bonding region B and functional region E of the wiring board 300, and Figure 6B shows a cross-sectional view cut along line CC' of Figure 6A. For brevity, the similarities between wiring board 300 and wiring board 100 will be omitted from the explanation, and only the differences between wiring board 300 and wiring board 100 will be described below.

[0059] The wiring board 300 shown in Figure 6A includes a base 101, a first conductive layer 102, a second conductive layer 103, a first insulating layer 105, and a second insulating layer 104. Unlike the wiring board 100, the first conductive layer 102 of the wiring board 200 is located within a functional region E and a bonding region B, and the first conductive layer 102 includes a third portion 1022 located within the bonding region B, and the third portion 1022 includes a plurality of second electrodes 1023 extending along a first direction D1. The second conductive layer 103 includes a first portion 1031 located within the functional region E and a second portion 1032 located within the bonding region B, and the second portion 1032 includes a plurality of first electrodes 1033 extending along the first direction D1. Multiple first electrodes 1033 correspond one-to-one with multiple second electrodes 1023, and the orthographic projection of each second electrode 1023 on the base 101 lies within the orthographic projection of the corresponding first electrode 1033 on the base 101. Each first electrode 1033 and the second electrode 1023 corresponding to it are electrically connected to form an electrode, and the exposed surface area of ​​the electrode constitutes a bonding electrode. Both the first electrode 1033 and the second electrode 1023 include a first end P approaching the functional region E. The orthographic projection of the first end P of the first electrode 1033 on the base 101 lies within the orthographic projection of the main body 1051 of the first insulating layer 105 on the base 101. With this arrangement, when etching the first insulating layer 105, even if the etching time increases, at most the surface of the first electrode 1033 that separates from the base 101 may be over-etched. However, since the first electrode 1033 has a greater thickness than the second insulating layer 104, the first electrode 1033 can shield and protect the second electrode 1023 during the etching process. As a result, the side surface S32 of the first end P of the second electrode 1023 is not etched, and therefore the side surface S32 is not exposed. In other words, the first end of the second electrode 1023 of each signal line is not exposed, and therefore abnormal growth of electroless nickel / immersion gold does not occur.

[0060] As shown in Figure 6A, each second electrode 1023 includes a plurality of tooth-like structures 1023A that extend along a first direction D1 and are arranged along a second direction D2 that intersects the first direction D1. Each second electrode 1023 further includes a connecting structure 1023B arranged along the second direction D2, and the plurality of tooth-like structures 1023A belonging to the same signal line are connected to each other via the connecting structure 1023B, and the connecting structure 1023B may have the same line width as the portion located within the functional region E of the signal line. Assuming that the two metal layers have the same surface area, the surface roughness of the thicker layer will also be greater. When the two metal layers are in direct contact, lateral sliding shear forces are likely to occur on the contact surface, reducing the adhesion between them, which in turn leads to the problem of film layer detachment. In the wiring board 300 provided by the embodiment of this disclosure, the shape of the region in the thick second electrode 1023 that directly contacts the first electrode 1033 is designed to be comb-like, thereby increasing the contact area between the second electrode 1023 and the first electrode 1033. This reduces the sliding shear force between them, increases the adhesion force between the second electrode 1023 and the first electrode 1033, and avoids the problem of film layer detachment between the second electrode 1023 and the first electrode 1033.

[0061] Each toothed structure 1023A includes a second surface S31 facing the second conductive layer 103 and a side surface S32 connected to the second surface S31. The via holes 1043 in the second insulating layer 104 expose at least the side surface S32 of each toothed structure 1023A, and as a result, the first electrode 1033 directly contacts the side surface S32 of the toothed structure 1023A via the via holes 1043 in the second insulating layer 104. In other words, the second insulating layer 104 does not cover the side surface S32 of the toothed structure 1023A. With this arrangement, the second insulating layer 104 is not fractured at the side surface S32 of the tooth-like structure 1023A, and as a result, the first electrode 1033 does not experience film layer detachment from the second insulating layer 104 due to contact with the fractured second insulating layer 104. Furthermore, because the second insulating layer 104 is not fractured at the side surface S32 of the tooth-like structure 1023A, the side surface S32 of the tooth-like structure 1023A is not exposed and oxidized to generate oxides, and as a result, the first electrode 1033 does not bulge at that location, and furthermore, the problem of film layer detachment between the first electrode 1033 and the second electrode 1023 does not occur.

[0062] As shown in Figures 6A and 6B, within bonding region B, the first insulating layer 105 includes a plurality of openings 1052, each corresponding one-to-one to a plurality of first electrodes 1033, and the orthographic projection of each opening 1052 on the base 101 lies within the orthographic projection of the first electrode 1033 corresponding to that opening 1052 on the base 101. Each first electrode 1033 further includes a second end Q opposite to the first end P, and the orthographic projections of both the first end P and the second end Q of each first electrode 1033 on the base 101 lies within the orthographic projection of the main body 1051 of the first insulating layer 105 on the base 101. By making the area of ​​the openings 1052 smaller than the area of ​​the first electrodes 1033, both the first end P and the second end Q of the first electrodes 1033 are covered by the main body 1051 of the first insulating layer 105, thereby increasing the corrosion resistance of the bonding electrode 107.

[0063] It should be noted that Figure 6A only shows a schematic diagram of the structure of a portion of the wiring board 300, but this schematic diagram does not show the electrical connection relationship between the third part 1022 and the various signal lines located in the functional area E. In reality, on the wiring board 300, the third part 1022 is electrically connected to various signal lines located in the first conductive layer 102 (e.g., power signal line 103, address signal line 108, feedback signal line 110, common voltage signal line 111, and drive voltage signal line VLED).

[0064] Figure 7A shows a schematic plan view of the partial structure in bonding region B and functional region E of the wiring board 400, and Figure 7B shows a cross-sectional view cut along line DD' of Figure 7A. The structure of the wiring board 400 is basically the same as that of the wiring board 300, except that the opening 1052 of the first insulating layer 105 is different. For brevity, only the differences between the wiring board 400 and the wiring board 300 will be described below.

[0065] As shown in Figures 7A and 7B, within bonding region B, the first insulating layer 105 includes a plurality of openings 1052, each corresponding one-to-one to a plurality of first electrodes 1033, and the orthographic projection of each opening 1052 on the base 101 partially overlaps with the orthographic projection of the first electrode 1033 on the base 101 corresponding to the opening 1052. Each first electrode 1033 further includes a second end Q opposite to the first end P, and the orthographic projection of the first end P of each first electrode 1033 on the base 101 lies within the orthographic projection of the main body 1051 of the first insulating layer 105 on the base 101, with the second end Q of each first electrode 1033 exposed by the opening 1052. With this arrangement, the main body portion 1051 of the first insulating layer 105 does not need to be provided at the second end Q of the first electrode 1033, thereby effectively reducing the problem of film layer detachment caused by the presence of the first insulating layer 105.

[0066] It should be noted that Figure 7A only shows a schematic diagram of a partial region of the wiring board 400, and this schematic diagram does not show the electrical connection relationships between the third part 1022 and the various signal lines located in the functional region E. In reality, in the wiring board 400, the third part 1022 is electrically connected to various signal lines located in the first conductive layer 102 (e.g., power signal line 103, address signal line 108, feedback signal line 110, common voltage signal line 111, and drive voltage signal line VLED).

[0067] Figure 8A shows a schematic plan view of the substructures in bonding region B and functional region E of the wiring board 500, and Figure 8B shows a cross-sectional view cut along line EE' of Figure 8A. For brevity, the similarities between wiring board 500 and wiring board 100 will not be explained, and only the differences between wiring board 500 and wiring board 100 will be described below.

[0068] The wiring board 500 shown in Figure 8A includes a base 101, a first conductive layer 102, a second conductive layer 103, a first insulating layer 105, and a second insulating layer 104. Unlike the wiring board 100, the first conductive layer 102 of the wiring board 500 is located within a functional region E and a bonding region B, and the first conductive layer 102 includes a third portion 1022 located within the bonding region B, and the third portion 1022 includes a plurality of second electrodes 1023 extending along a first direction D1. The second conductive layer 103 includes a first portion 1031 located within the functional region E and a second portion 1032 located within the bonding region B, and the second portion 1032 includes a plurality of first electrodes 1033 extending along the first direction D1. Multiple first electrodes 1033 correspond one-to-one with multiple second electrodes 1023, and the orthographic projection of each first electrode 1033 on the base 101 lies within the orthographic projection of the corresponding second electrode 1023 on the base 101. Each first electrode 1033 and the second electrode 1023 corresponding to it constitute an electrode, and the exposed surface area of ​​the electrode constitutes a bonding electrode 107. The electrode includes a first end P approaching the functional region E. The orthographic projection of the first end P of the electrode on the base 101 lies within the orthographic projection of the main body 1051 of the first insulating layer 105 on the base 101. With this arrangement, when etching the first insulating layer 105, even if the etching time increases, at most the surface of the first electrode 1033 that separates from the base 101 may be over-etched. However, since the thickness of the first electrode 1033 is greater than the thickness of the second insulating layer 104, the first electrode 1033 has the effect of shielding and protecting the second electrode 1023, so the first end P of the second electrode 1023 is not etched, and as a result the first end P of the second electrode 1023 is not exposed. In other words, the first end of the second electrode 1023 of each signal line is not exposed, and as a result abnormal growth of electroless nickel / immersion gold does not occur.

[0069] It should be noted that Figure 8A only shows a schematic diagram of the structure of a portion of the wiring board 500, and this schematic diagram does not show the electrical connection relationship between the third part 1022 and the various signal lines located in the functional area E. In reality, in the wiring board 500, the third part 1022 is electrically connected to the various signal lines located in the first conductive layer 102 (e.g., power signal line 103, address signal line 108, feedback signal line 110, common voltage signal line 111, and drive voltage signal line VLED). Also, since the second insulating layer 104 is located only in the functional area E and not in the bonding area B, the orthographic projection of the second insulating layer 104 on the base 101 does not overlap with the orthographic projection of the first electrode 1033 and the second electrode 1023 on the base 101, and the first electrode 1033 and the second electrode 1023 that constitute each electrode are in direct contact. By not providing a second insulating layer 104 within bonding region B, the problem of film layer detachment due to the overlapping of multiple insulating layers within bonding region B can be effectively reduced.

[0070] Within bonding region B, the first insulating layer 105 includes a plurality of openings 1052, each of which corresponds one-to-one with a plurality of electrodes, and the orthographic projection of each opening 1052 on the base 101 lies within the orthographic projection of the electrode corresponding to the opening 1052 on the base 101. Each electrode, composed of a first electrode 1033 and a second electrode 1023 corresponding to the first electrode 1033, further includes a second end Q opposite to the first end P, and the orthographic projections of both the first end P and the second end Q of each electrode on the base 101 lies within the orthographic projection of the main body 1051 of the first insulating layer 105 on the base 101. As shown in Figure 8B, in one example, the overlap width W2 along the second direction D2 between the main body 1051 of the first insulating layer 105 and the first electrode 1033 is approximately 30 μm. By making the area of ​​the opening 1052 smaller than the area of ​​the first electrode 1033, both the first end P and the second end Q of the electrode are covered by the main body portion 1051 of the first insulating layer 105, thereby increasing the corrosion resistance of the electrode.

[0071] Figure 9A shows a schematic plan view of the substructures in bonding region B and functional region E of the wiring board 600, and Figure 9B shows a cross-sectional view cut along line FF' of Figure 9A. For brevity, the similarities between wiring board 600 and wiring board 100 will be omitted from the explanation, and only the differences between wiring board 600 and wiring board 100 will be described below.

[0072] The wiring board 600 shown in Figure 9A includes a base 101, a first conductive layer 102, a second conductive layer 103, a first insulating layer 105, and a second insulating layer 104. Unlike the wiring board 100, the first conductive layer 102 of the wiring board 600 is located within the functional region E and the bonding region B, and the first conductive layer 102 includes a third section 1022 located within the bonding region B, and the third section 1022 includes a plurality of second electrodes 1023 extending along the first direction D1. It should be noted that Figure 9A only shows a schematic diagram of the structure of a partial region of the wiring board 600, and this schematic diagram does not show the electrical connection relationships between the third section 1022 and the various signal lines located in the functional region E. In practice, on the wiring board 600, the third section 1022 is electrically connected to various signal lines located on the first conductive layer 102 (e.g., power signal line 103, address signal line 108, feedback signal line 110, common voltage signal line 111, and drive voltage signal line VLED).

[0073] The second conductive layer 103 includes a first portion 1031 located within the functional region E and a second portion 1032 located within the bonding region B, the second portion 1032 including a plurality of first electrodes 1033 extending along a first direction D1. The plurality of first electrodes 1033 correspond one-to-one with a plurality of second electrodes 1023, the orthographic projection of each first electrode 1033 on the base 101 is within the orthographic projection of the corresponding second electrode 1023 on the base 101, each first electrode 1033 and the second electrode 1023 corresponding to the first electrode 1033 constitute an electrode, and the region where the surface of the electrode is exposed constitutes a bonding electrode 107. The electrode includes a first end P approaching the functional region E.

[0074] As shown in Figure 9A, the main body 1051 of the first insulating layer 105 includes a plurality of sub-insulating portions 1054 that extend along the first direction D1 and are spaced apart from each other in the second direction D2. The orthographic projections of two adjacent sub-insulating portions 1054 on the base 101 partially overlap with the orthographic projections of the electrodes on the base 101. Each electrode is spaced apart from each other in the second direction D2, and each sub-insulating portion 1054 is also spaced apart from each other in the second direction D2. Since each electrode corresponds to two sub-insulating portions 1054, a portion of the space between two adjacent electrodes inevitably lacks a sub-insulating portion 1054. As shown in region W in Figure 9A, no sub-insulating portion 1054 exists in region W. By not placing the first insulating layer 105 in region W, the laminate thickness of the insulating layer in region W can be reduced, thereby mitigating the problem of film layer detachment due to an excessively large laminate thickness of the insulating layer.

[0075] As shown in Figure 9A, the orthographic projection of the first end P of the electrode, which is composed of each first electrode 1033 and the second electrode 1023 corresponding to the first electrode 1033, on the base 101 partially overlaps with the orthographic projection of the two adjacent sub-insulating portions 1054 on the base 101. Therefore, the two adjacent sub-insulating portions 1054 can protect the first end P of the electrode to some extent. When etching the first insulating layer 105, even if the etching time increases, at most the surface of the first electrode 1033 that is separated from the base 101 may be over-etched. However, since the thickness of the electrode is greater than the thickness of the second insulating layer 104, the first electrode 1033 can shield and protect the second electrode 1023 at least partially. Therefore, the first end P of the second electrode 1023 is not basically etched, and thus the surface of the first end P of the second electrode 1023 is not basically exposed. In other words, the first end P of the second electrode 1023 of each signal line is not exposed, and as a result, abnormal growth of electroless nickel / immersion gold does not basically occur.

[0076] As shown in Figure 9B, in one example, the overlap width W3 along the second direction D2 between the sub-insulating portion 1054 of the first insulating layer 105 and the first electrode 1033 is approximately 15 μm, thereby protecting the two sides of the first electrode 1033 that extend along the first direction D1. The overlap width W4 along the second direction D2 between the second insulating layer 104 and the second electrode 1023 is approximately 22 μm, thereby protecting the two sides of the second electrode 1023 that extend along the first direction D1.

[0077] Figure 10A shows a schematic plan view of the substructure within bonding region B and functional region E of the wiring board 700, and Figure 10B shows a cross-sectional view cut along line GG' of Figure 10A. For brevity, the similarities between wiring board 700 and wiring board 100 will be omitted from the explanation, and only the differences between wiring board 700 and wiring board 100 will be described below.

[0078] The wiring board 700 shown in Figure 10A includes a base 101, a first conductive layer 102, a second conductive layer 103, a first insulating layer 105, and a second insulating layer 104. Unlike the wiring board 100, the first conductive layer 102 of the wiring board 700 is located within a functional region E and a bonding region B. The first conductive layer 102 includes a third portion 1022 located within the bonding region B, which includes a plurality of second electrodes 1023 extending along a first direction D1, and the exposed surface areas of the second electrodes 1023 constitute a bonding electrode 107. The second electrodes 1023 include a first end P approaching the functional region E. In some embodiments, the second conductive layer 103 of the wiring board 700 is located only within the functional region E and not within the bonding region B. In the alternative embodiment, the second conductive layer 103 is not provided in either the functional region E or the bonding region B; that is, the wiring board 700 includes only the first conductive layer 102 and does not include the second conductive layer 103. It should be noted that Figure 10A only shows a schematic diagram of the structure of a partial region of the wiring board 700, and this schematic diagram does not show the electrical connection relationship between the third part 1022 and the various signal lines located in the functional region E. In practice, in the wiring board 700, the third part 1022 is electrically connected to the various signal lines located in the first conductive layer 102 (e.g., power signal line 103, address signal line 108, feedback signal line 110, common voltage signal line 111, and drive voltage signal line VLED).

[0079] The second insulating layer 104 includes a plurality of via holes 1043, each of which corresponds one-to-one with a plurality of second electrodes 1023, and the orthographic projection of each of the via holes 1043 on the base 101 lies within the orthographic projection of the second electrode 1023 on the base 101 corresponding to the via hole 1043.

[0080] As shown in Figure 10A, the main body 1051 of the first insulating layer 105 includes a plurality of sub-insulating portions 1054 that extend along a first direction D1 and are spaced apart from each other in a second direction D2. The orthographic projections of two adjacent sub-insulating portions 1054 on the base 101 partially overlap with the orthographic projections of the second electrode 1023 on the base 101, and the orthographic projection of the first end P of the second electrode 1023 on the base 101 partially overlaps with the orthographic projections of two adjacent sub-insulating portions 1054 on the base 101. Each second electrode 1023 is provided spaced apart from each other in the second direction D2, and each sub-insulating portion 1054 is also provided spaced apart from each other in the second direction D2. Since each second electrode 1023 corresponds to two sub-insulating portions 1054, a portion of the space between two adjacent second electrodes 1023 inevitably lacks a sub-insulating portion 1054. As shown in region W in Figure 10A, no sub-insulating portion 1054 exists in region W. By not placing the first insulating layer 105 in region W, the thickness of the insulating layer in region W can be reduced, thereby mitigating the problem of film layer detachment caused by an excessively thick insulating layer.

[0081] In one example, the overlap width of the sub-insulating portion 1054 of the first insulating layer 105 and the second electrode 1023 along the second direction D2 is approximately 22 μm, thereby protecting the two sides of the second electrode 1023 that extend along the first direction D1. The overlap width of the second insulating layer 104 and the second electrode 1023 along the second direction D2 is approximately 15 to 20 μm, thereby protecting the two sides of the second electrode 1023 that extend along the first direction D1.

[0082] Figure 11A shows a schematic plan view of the bonding region B of the wiring board 800, and Figure 11B shows a cross-sectional view cut along line HH' of Figure 11A. For brevity, the similarities between wiring board 800 and wiring board 100 will be omitted from the explanation, and only the differences between wiring board 800 and wiring board 100 will be described below.

[0083] The wiring board 800 shown in Figure 11A includes a base 101, a first conductive layer 102, a second conductive layer 103, a first insulating layer 105, and a second insulating layer 104. Unlike the wiring board 100, the first insulating layer 105 and the second insulating layer 104 of the wiring board 800 are located only in the functional region E and not in the bonding region B, while the first conductive layer 102 is located in both the functional region E and the bonding region B. The first conductive layer 102 includes a third portion 1022 located in the bonding region B, which includes a plurality of second electrodes 1023 extending along a first direction D1, and the second electrodes 1023 constitute a bonding electrode 107. In some embodiments, the second conductive layer 103 of the wiring board 800 is located only in the functional region E and not in the bonding region B. In the alternative embodiment, the second conductive layer 103 is not provided in either the functional region E or the bonding region B; that is, the wiring board 800 includes only the first conductive layer 102 and does not include the second conductive layer 103. It should be noted that Figure 11A only shows a schematic diagram of the structure of a partial region of the wiring board 800, and this schematic diagram does not show the electrical connection relationship between the third part 1022 and the various signal lines located in the functional region E. In practice, in the wiring board 800, the third part 1022 is electrically connected to the various signal lines located in the first conductive layer 102 (e.g., power signal line 103, address signal line 108, feedback signal line 110, common voltage signal line 111, and drive voltage signal line VLED).

[0084] By etching and removing all portions of the first insulating layer 105 and the second insulating layer 104 located within the bonding region B, the stacking of multiple insulating layers within the bonding region B can be avoided, thereby preventing the problem of film layer detachment caused by the stacking of multiple insulating layers.

[0085] It should be noted that for the wiring boards 200 shown in Figures 5A-5B, 300 shown in Figures 6A-6B, 400 shown in Figures 7A-7B, 500 shown in Figures 8A-8B, 600 shown in Figures 9A-9B, 700 shown in Figures 10A-10B, and 800 shown in Figures 11A-11B, the first conductive layer 102 of these wiring boards contains multiple types of signal lines located in the functional area E, such as power signal lines 103, address signal lines 108, feedback signal lines 110, common voltage signal lines 111, and drive voltage signal lines VLED. These signal lines typically have different line widths along the second direction D2. For example, the line widths along the second direction D2 of the common voltage signal line 111 and the drive voltage signal line VLED are typically greater than the line width along the second direction D2 of any of the power signal line 103, address signal line 108, and feedback signal line 110. For signal lines with different line widths, the number of second electrodes 1023 included in each third section 1022 is different. For example, if the line width along the second direction D2 of a signal line in the functional area E (e.g., power signal line 103, address signal line 108, feedback signal line 110) is equal to the line width along the second direction D2 of an electrode 150 in the bonding area, then the third part 1022 of the signal line in the bonding area B includes only one second electrode 1023. If the line width along the second direction D2 of a signal line in the functional area E (e.g., drive voltage signal line VLED and common voltage signal line 111) is much larger than the line width along the second direction D2 of an electrode 150 in the bonding area, then the third part 1022 of the signal line in the bonding area B includes multiple second electrodes 1023, and in some embodiments, multiple second electrodes 1023 belonging to the same signal line are interconnected at the first end.

[0086] According to another aspect of the present disclosure, a light-emitting substrate is provided, and Figure 12 shows a block diagram of the light-emitting substrate 900, which includes a wiring board as described in any of the above embodiments, a plurality of light-emitting elements provided in a functional area E, and a circuit board provided in a bonding area B. In some embodiments, each light-emitting element may be a light-emitting diode (LED), a sub-millimeter light-emitting diode (Mini LED), or a micro light-emitting diode (Mirco LED). By using a Mini LED as a light-emitting element, high-dynamic-range (HDR) display can be achieved. When such a light-emitting substrate is applied to a display device, the contrast of the display device can be significantly improved. The circuit board may be, for example, a flexible circuit board (FPC). One end of the FPC is connected to a printed circuit board (PCBA), and the other end of the FPC is connected to a bonding electrode 107 of the light-emitting substrate 900, for example, via a chip-on-film (COF). Control signals from the ICs on the PCBA are transmitted to the bonding electrode 107 via the FPC. One end of each of the multiple signal lines on the light-emitting substrate 900 is bonded to the bonding electrode 107, and the other end is electrically connected to the light-emitting element. Therefore, control signals are transmitted to the light-emitting element via the signal lines to control the light-emitting element and cause it to emit light.

[0087] Since the light-emitting substrate 900 provided in the embodiments of this disclosure can have essentially the same technical effects as the wiring substrates described in each of the embodiments above, for the sake of brevity, the technical effects of the light-emitting substrate 900 will not be repeatedly explained here.

[0088] According to yet another aspect of the present disclosure, a display device is provided, and Figure 13 shows a block diagram of the display device 1000, which includes a wiring board or light-emitting board as described in any of the embodiments above. In some embodiments, the display device 1000 may be a liquid crystal display device, which includes a liquid crystal panel and a backlight source provided on the non-display side of the liquid crystal panel, the backlight source including a wiring board as described in any of the embodiments above, which may be used, for example, to achieve HDR dimming for display operation. The liquid crystal display device may have a more uniform backlight brightness and a better display contrast. The display device 1000 may be any suitable display device, including, but not limited to, any product or component having a display function such as a mobile phone, tablet computer, television, display, notebook computer, digital photo frame, navigator, and e-book reader.

[0089] Since the display device 1000 can have essentially the same technical effects as the wiring boards described in each of the above embodiments, for the sake of brevity, the technical effects of the display device 1000 will not be repeatedly explained here.

[0090] A further aspect of this disclosure provides a method for manufacturing a wiring board, Figure 14 shows a flowchart of the method 1100, which can be applied to the wiring board described in any of the embodiments described above. The method 1100 may include the following steps S1101 to S1104.

[0091] S1101 provides a base 101 including a functional area E and a bonding area B.

[0092] The base 101 may be a flexible or rigid material, specifically PEN resin, silica gel resin, polyimide, glass, quartz, and plastic, and embodiments of this disclosure do not limit the material of the base 101.

[0093] S1102, a first conductive film is applied to the base 101, and the first conductive film is patterned through a first mask to form a first conductive layer 102, the first conductive layer 102 is located at least within the functional region E.

[0094] A first conductive film is applied to the base 101 by a magnetron sputtering method or an electroplating method, and a first conductive layer 102 is formed by patterning the first conductive film using a first mask. The first conductive layer 102 may include the drive voltage signal line, address selection signal line, power signal line, data drive signal line, common voltage signal line, feedback signal line, and a selectable second electrode 1023. In one example, the first conductive layer 102 may be a MoNb / Cu / MoNb laminate. In an alternative embodiment, the first conductive layer 102 may be a Mo / Cu / Mo laminate.

[0095] In S1103, a second conductive film is applied to the side of the first conductive layer 102 away from the base 101, and the second conductive film is patterned through a second mask to form a second conductive layer 103, the second conductive layer 103 is located at least within the functional region B and is electrically connected to the first conductive layer 102.

[0096] The second conductive layer 103 is formed by applying a second conductive film to the side of the first conductive layer 102 away from the base 101 by magnetron sputtering or electroplating, and then patterning the second conductive film using a second mask. The second conductive layer 103 may include the first pad group 102, the second pad group 104, and a selectable first electrode 1033, the first pad group 102 may be used to mount a microdrive chip 002, and the second pad group 104 may be used to mount an electronic component 003. In one example, the second conductive layer 103 may be formed by first forming a MoNb layer with a thickness of about 300 Å on the side of the first conductive layer 102 away from the base 101, then forming a Cu layer with a thickness of about 6000 to 9000 Å on the MoNb layer, and finally forming a MoNb layer with a thickness of about 300 Å on the Cu layer. In an alternative example, the second conductive layer 103 may be formed by first forming a Mo layer with a thickness of approximately 300 Å on the side of the first conductive layer 102 away from the base 101, then forming a Cu layer with a thickness of approximately 6000 to 9000 Å on the Mo layer, and finally forming a Mo layer with a thickness of approximately 17 to 30 Å on the Cu layer.

[0097] S1104, a first insulating film is applied to the side of the second conductive layer 103 away from the base 101, and the first insulating film is patterned through a third mask to form a first insulating layer 105 including a body portion 1051 and an opening 1052, wherein at least one of the first conductive layer 102 and the second conductive layer 103 includes a plurality of electrodes located within the bonding region B and extending along a first direction D1, each of the plurality of electrodes includes a first end P adjacent to the functional region E in the first direction D1, and the orthographic projection of the body portion 1051 of the first insulating layer 105 on the base 101 at least partially overlaps with the orthographic projection of the first end P of each electrode on the base 101.

[0098] The first insulating layer 105 can be formed on the side of the second conductive layer 103 away from the base 101 by a magnetron sputtering method. By at least partially overlapping the orthographic projection of the main body 1051 of the first insulating layer 105 on the base 101 with the orthographic projection of the first end P of each electrode on the base 101, abnormal growth of electroless nickel / immersion gold in the signal line of the first end P can be prevented. The material of the first insulating layer 105 may be an organic material, an inorganic material, or a combination of organic and inorganic materials. The first insulating layer 105 may be a single film layer or may include multiple film layers.

[0099] In some embodiments, after the step of forming the first conductive layer 102 and before the step of forming the second conductive layer 103, the step of applying a second insulating film to the side of the first conductive layer 102 away from the base 101 by a magnetron sputtering method, and patterning the second insulating film through a fourth mask to form a second insulating layer 104, may further be included. The material of the second insulating layer 104 may be an organic material, an inorganic material, or a combination of organic and inorganic materials. The second insulating layer 104 may be a single film layer or may consist of multiple film layers. In one example, the second insulating layer 104 includes a first sub-insulating layer 1041 and a second sub-insulating layer 1042.

[0100] In embodiments where the second insulating layer 104 includes a first sub-insulating layer 1041 and a second sub-insulating layer 1042, an OC (Over Coating) layer may be formed between the first sub-insulating layer 1041 and the second sub-insulating layer 1042 via a fifth mask, and the OC layer may be a negative-type photoresist made of an organic material. The thickness of the OC layer is greater than the thickness of the first insulating layer 105 and the second insulating layer 104, and is usually placed only in the functional region E. In one example, the thickness of the OC layer is 3 to 4 microns. A thick OC layer can enclose particles between the first conductive layer 102 and the second conductive layer 103, preventing the particles from piercing the first conductive layer 102 and the second conductive layer 103 and causing a short circuit between them. The OC layer can also perform a planarization effect.

[0101] In some embodiments, the process may further include forming a buffer layer 106 on the base 101 by, for example, a magnetron sputtering method, prior to forming the first conductive layer 102. The buffer layer 106 may be used to reduce the stress on the base 101 when manufacturing the subsequent first conductive layer 102 and second conductive layer 103, thereby avoiding bending deformation of the base 101. The buffer layer 106 can also avoid the adverse effect of impurities in the base 101 on the conductivity of the subsequently formed first conductive layer 102 and second conductive layer 103. The buffer layer 112 may be any suitable material, for example, SiN, SiO, or SiON.

[0102] The method 1100 allows for the manufacture of a circuit board using fewer mask plates (e.g., five mask plates), and compared to the need for at least seven mask plates to manufacture a circuit board in related technologies, the method 1100 provided by embodiments of the present disclosure reduces the number of required mask plates, simplifies the process, and lowers production costs. Other technical effects achieved by the method 1100 can be seen by referring to the technical effects of the circuit boards described in each of the embodiments above, and are therefore not described again for brevity.

[0103] To be understood, terms such as first, second, and third may be used herein to describe various elements, components, regions, layers, and / or parts, but these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely for distinguishing one element, component, region, layer, or part from another. Accordingly, the first element, component, region, layer, or part considered above may be referred to as the second element, component, region, layer, or part without departing from the teachings of this disclosure.

[0104] Spatial relative terms such as “row,” “column,” “below,” “above,” “left,” and “right” may be used herein to describe the relationship between one element or feature and another (or several) elements or features, as shown in the figures, for the sake of clarity. As can be understood, these spatial relative terms are intended to encompass different orientations of the device in use or operation, in addition to the orientation shown in the figures. For example, if the device in the figure is upside down, an element described as “below another element or feature” would be oriented as “above another element or feature.” Thus, the exemplary term “below” can encompass both orientations of “above” and “below.” The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein will be interpreted accordingly. Also, as can be understood further, when a layer is described as “between two layers,” it may be the single layer between the two layers, or there may be one or more intermediate layers.

[0105] The terms used herein are for the purpose of describing specific embodiments and are not intended to limit the disclosure. As used herein, the singular forms “one,” “one,” and “the” are intended to include the plural unless the context clearly indicates otherwise. For the purposes of this disclosure, the terms “include” and / or “incorporate,” as used herein, specify the presence of such features, wholes, steps, operations, elements, and / or components, but do not preclude the presence of one or more other features, wholes, steps, operations, elements, components, and / or groups thereof, or the addition of one or more other features, wholes, steps, operations, elements, components, and / or groups thereof. As used herein, the terms “and / or” include any and all combinations of one or more of the related enumerated items. In the description herein, the reference terms such as “one embodiment” and “another embodiment” mean that the specific features, structures, materials, or properties described in combination with the embodiments are included in at least one embodiment of the disclosure. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the specific features, structures, materials, or properties described may be combined in an appropriate manner in any one or more embodiments or examples. Also, a person skilled in the art can combine and adapt the different embodiments or examples and the features of the different embodiments or examples described herein, provided they are not inconsistent.

[0106] To be understood, when an element or layer is described as "on another element or layer," "connected to another element or layer," "coupled to another element or layer," or "adjacent to another element or layer," it may be directly on another element or layer, directly connected to another element or layer, directly coupled to another element or layer, or directly adjacent to another element or layer, or an intermediate element or layer may exist. Conversely, when an element is described as "directly on another element or layer," "directly connected to another element or layer," "directly coupled to another element or layer," or "directly adjacent to another element or layer," there is no intermediate element or layer. However, in no case should "on..." or "directly on..." be interpreted as requiring one layer to completely cover the layer below.

[0107] In this specification, embodiments of the disclosure are described with reference to schematic diagrams (and intermediate structures) of idealized embodiments of the disclosure. Therefore, deformations from the illustrated shapes should be expected, for example, as a result of manufacturing techniques and / or tolerances. Accordingly, embodiments of the disclosure should not be construed as being limited to specific shapes of the regions illustrated herein, but should include, for example, shape deviations resulting from manufacturing. Accordingly, the regions shown in the figures are essentially schematic, and their shapes are not intended to illustrate the actual shapes of the regions of the device, nor are they intended to limit the scope of the disclosure.

[0108] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by those skilled in the art of the field to which this disclosure belongs. For the sake of further understanding, such terms as those defined in commonly used dictionaries should be construed to have the meaning consistent with their meaning in the relevant art and / or context of this specification, and should not be construed in an idealized or overly formal sense unless explicitly defined herein.

[0109] The above are merely specific embodiments of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any modification or substitution that can be easily conceived by any person skilled in the art within the scope of the art disclosed herein should be included within the scope of protection of the present disclosure. Accordingly, the scope of protection of the present disclosure should be based on the scope of protection of the claims described herein.

Claims

1. A wiring board, A base including functional areas and bonding areas, A first conductive layer located on the base and at least within the functional region, A second conductive layer is located on the side of the first conductive layer away from the base and at least within the functional region, and is electrically connected to the first conductive layer, The second conductive layer includes a first insulating layer located on the side away from the base and including a main body and an opening, At least one of the first conductive layer and the second conductive layer includes a plurality of electrodes located within the bonding region and extending along a first direction (D1), each of the plurality of electrodes includes a first end adjacent to the functional region in the first direction (D1), and the orthographic projection of the main body of the first insulating layer on the base at least partially overlaps with the orthographic projection of the first end of each electrode on the base. A wiring substrate in which, along the first direction (D1) in which the plurality of electrodes extend, the first conductive layer includes a second surface facing the second conductive layer and a side surface that is connected to the second surface and toward the bonding region, and the second conductive layer is in direct contact with the side surface of the first conductive layer.

2. The wiring board according to claim 1, further comprising a second insulating layer located between the first conductive layer and the second conductive layer, wherein the second conductive layer is in contact with the first conductive layer via via holes in the second insulating layer.

3. The wiring substrate according to claim 2, wherein the second conductive layer comprises a first portion and a second portion, the first portion located within the functional region, the second portion located within the bonding region, and the second portion comprising a plurality of first electrodes extending along the first direction (D1), each of the plurality of first electrodes comprising the first end.

4. The wiring board according to claim 3, wherein the second conductive layer includes a first surface that separates from the base, the distance between the portion of the first surface located in the first part and the base is greater than the distance between the portion of the first surface located in the second part and the base, and the orthographic projection of the opening of the first insulating layer on the base at least partially overlaps with the orthographic projection of the second part on the base.

5. The wiring board according to claim 4, wherein the opening in the first insulating layer exposes the remaining portion of each first electrode, excluding the first end.

6. The wiring board according to claim 5, wherein in the bonding region, the orthographic projection of the opening of the first insulating layer on the base does not overlap with the orthographic projection of the second insulating layer on the base.

7. The wiring substrate according to claim 3, wherein the first conductive layer is located only within the functional region, and the orthographic projection of the first conductive layer on the base partially overlaps with the orthographic projection of the first part of the second conductive layer on the base.

8. The first conductive layer includes a third portion located within the bonding region, the third portion includes a plurality of second electrodes extending along the first direction (D1), the plurality of first electrodes correspond one-to-one with the plurality of second electrodes, and the orthographic projection of each of the plurality of first electrodes on the base at least partially overlaps with the orthographic projection of one of the plurality of second electrodes on the base. The wiring board according to claim 3, wherein each first electrode and the second electrode corresponding to the first electrode are electrically connected to constitute the electrode, and both the electrically connected first electrode and the second electrode include the first end.

9. The wiring board according to claim 8, wherein the orthographic projection of the first ends of the first electrode and the second electrode on the base is within the orthographic projection of the main body of the first insulating layer on the base.

10. The wiring board according to claim 9, wherein the opening in the first insulating layer exposes the remaining portion of each first electrode, excluding the first end.

11. The wiring board according to claim 9, wherein each second electrode includes a plurality of tooth-like structures that extend along the first direction (D1) and are arranged along the second direction (D2), and the second direction (D2) intersects with the first direction (D1).

12. The wiring substrate according to claim 11, wherein each of the plurality of tooth-like structures includes a second surface facing the second conductive layer and a side surface connected to the second surface, and the first electrode is in direct contact with the side surface of the tooth-like structure.

13. In the bonding region, the first insulating layer includes a plurality of openings, the plurality of openings correspond one-to-one with the plurality of electrodes, and the orthographic projection of each of the plurality of openings on the base lies within the orthographic projection of the first electrode corresponding to the opening on the base. The wiring board according to claim 11, wherein the electrode further includes a second end opposite to the first end, and the orthographic projection of the second end of the electrode on the base is within the orthographic projection of the main body of the first insulating layer on the base.

14. In the bonding region, the first insulating layer includes a plurality of openings, the plurality of openings correspond one-to-one with the plurality of electrodes, and the orthographic projection of each of the plurality of openings on the base partially overlaps with the orthographic projection of the electrode corresponding to the opening on the base. The wiring board according to claim 11, wherein the electrode further includes a second end opposite to the first end, and a portion of the second end is exposed by an opening corresponding to the electrode.

15. The wiring board according to claim 9, wherein the orthographic projection of the second insulating layer on the base does not overlap with the orthographic projection of the first electrode and the second electrode on the base, and the first electrode of each electrode is in direct contact with the second electrode.

16. In the bonding region, the first insulating layer includes a plurality of openings, the plurality of openings correspond one-to-one with the plurality of electrodes, and the orthographic projection of each of the plurality of openings on the base lies within the orthographic projection on the base of the first electrode of the electrode corresponding to the opening. The wiring board according to claim 15, wherein the electrode further includes a second end opposite to the first end, and the orthographic projection of the second end of the electrode on the base is within the orthographic projection of the main body of the first insulating layer on the base.

17. The wiring board according to claim 8, wherein, for each electrode, the orthographic projection of the first electrode on the base is within the orthographic projection of the second electrode on the base.

18. The wiring board according to claim 17, wherein the main body of the first insulating layer includes a plurality of sub-insulating portions that extend along the first direction (D1) and are spaced apart from each other in a second direction (D2) that intersects the first direction (D1), the orthographic projections of two adjacent sub-insulating portions on the base of the plurality of sub-insulating portions partially overlap with the orthographic projections of the electrodes on the base, and the orthographic projections of the first ends of the first electrode and the second electrode on the base partially overlap with the orthographic projections of the two adjacent sub-insulating portions on the base.

19. The wiring substrate according to claim 2, wherein the second conductive layer is disposed only within the functional region, the first conductive layer includes a third portion disposed within the bonding region, the third portion includes a plurality of second electrodes extending along the first direction (D1), and each of the plurality of second electrodes includes the first end.

20. The wiring board according to claim 19, wherein the second insulating layer includes a plurality of via holes, the plurality of via holes correspond one-to-one with the plurality of second electrodes, and the orthogonal projection of each of the plurality of via holes on the base lies within the orthogonal projection of the second electrode corresponding to the via hole on the base.

21. The wiring board according to claim 20, wherein the main body of the first insulating layer includes a plurality of sub-insulating portions that extend along the first direction (D1) and are spaced apart from each other in a second direction (D2) that intersects the first direction (D1), the orthographic projections of two adjacent sub-insulating portions on the base of the plurality of sub-insulating portions each partially overlap with the orthographic projection of the second electrode on the base, and the orthographic projection of the first end of the second electrode on the base partially overlaps with the orthographic projections of the two adjacent sub-insulating portions on the base.

22. A light-emitting substrate comprising a wiring board according to any one of claims 1 to 21, a plurality of light-emitting elements provided in the functional area, and a circuit board provided in the bonding area.

23. A display device comprising a wiring board according to any one of claims 1 to 21.

24. A method for manufacturing a wiring board according to any one of claims 1 to 21, A step of providing a base including a functional area and a bonding area, The steps include: applying a first conductive film onto the base, patterning the first conductive film through a first mask to form a first conductive layer located at least within the functional region; The steps include: applying a second conductive film to the side of the first conductive layer away from the base, and patterning the second conductive film through a second mask to form a second conductive layer that is located at least within the functional region and is electrically connected to the first conductive layer; The process includes the steps of: applying a first insulating film to the side of the second conductive layer away from the base; and patterning the first insulating film through a third mask to form a first insulating layer including the main body and the opening; A method for manufacturing a wiring board, wherein at least one of the first conductive layer and the second conductive layer includes a plurality of electrodes located within the bonding region and extending along a first direction (D1), each of the plurality of electrodes includes a first end adjacent to the functional region in the first direction (D1), and the orthographic projection of the main body of the first insulating layer on the base at least partially overlaps with the orthographic projection of the first end of each electrode on the base.

25. After the step of forming the first conductive layer on the base, The steps include: applying a second insulating film to the side of the first conductive layer away from the base, and patterning the second insulating film through a fourth mask to form a second insulating layer; The method according to claim 24, further comprising the step of forming the second conductive layer on the side of the second insulating layer away from the base.

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