Components for semiconductor manufacturing equipment

Abstract

Provided is a member for a semiconductor manufacturing device capable of suppressing generation of particles. This member for a semiconductor manufacturing device includes a ceramic substrate that has an upper surface having a plurality of projections for mounting a wafer, and a side wall forming an outer edge of the upper surface. An arithmetic average roughness Ra1 of a surface of the side wall is 0.4 μm or less.

Description

Technical Field

[0001] The present invention relates to a member for a semiconductor manufacturing apparatus.

Background Art

[0002] Conventionally, members for semiconductor manufacturing apparatuses used for holding, temperature control, conveyance, etc. of wafers are known. This type of member for a semiconductor manufacturing apparatus is also referred to as a wafer stage, an electrostatic chuck, a susceptor, etc., and generally has a function of applying electrostatic adsorption power to an internal electrode to adsorb a wafer by electrostatic force, and there is also known one having a function of controlling the temperature of a wafer by flowing a gas between the wafer mounting surface and the wafer which is an adsorption object.

[0003] A member for a semiconductor manufacturing apparatus generally includes a ceramic substrate having an upper surface on which a wafer can be mounted. And, a plurality of protrusions for supporting the wafer are provided on the upper surface on which the wafer can be mounted. Further, the ceramic substrate can have a side wall forming an outer edge of the upper surface on which the wafer can be mounted, and furthermore, on the outer peripheral side of the upper surface on which the wafer can be mounted and at a position lower than the upper surface, it can also have an upper surface on which a focus ring for in-plane uniform processing of the wafer can be mounted (Patent Document 1).

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] The top and sides of the ceramic substrate are exposed to the plasma, making them susceptible to plasma influence during wafer processing, which may cause the ceramic particles constituting these sidewalls to detach. Furthermore, fluorination of alumina by fluorine-based corrosive gases can also cause the ceramic particles to detach. Even when a focus ring is placed, a gap is often provided between the focus ring and the wafer to prevent interference. Because the sidewalls forming the step between the wafer-mounted top surface and the focus ring-mounted top surface are exposed to the plasma in this gap, these sidewalls are affected by plasma and corrosive gases during wafer processing. When ceramic particles detach, they adhere to the wafer as particles, potentially affecting semiconductor quality and reducing yield.

[0006] Therefore, in one embodiment of the present invention, the objective is to provide a semiconductor manufacturing apparatus component comprising a ceramic substrate having an upper surface on which a wafer can be placed and a side wall forming the outer edge of the upper surface, which can suppress the generation of particles. In another embodiment of the present invention, the objective is to provide a semiconductor manufacturing apparatus component comprising a ceramic substrate having an upper surface on which a wafer can be placed, an upper surface on which a focus ring can be placed, and a side wall forming a step between the two, which can suppress the generation of particles. [Means for solving the problem]

[0007] The inventors of this invention have diligently studied and developed the present invention as illustrated below in order to solve the above problems.

[0008] [Aspect 1] A component for semiconductor manufacturing equipment comprising a ceramic substrate having a top surface with a plurality of protrusions for placing a wafer and a side wall forming the outer edge of the top surface, wherein the arithmetic mean roughness Ra1 of the surface of the side wall is 0.4 μm or less. [Aspect 2] The semiconductor manufacturing apparatus component according to embodiment 1, wherein the surface of the side wall has a patterned uneven shape. [Aspect 3] The semiconductor manufacturing apparatus component according to embodiment 2, wherein the patterned uneven shape is formed by laser processing. [Aspect 4] The semiconductor manufacturing apparatus member according to embodiment 2 or 3, wherein the surface of the side wall has one or more patterned uneven shapes of any of the following i) to iv): i) A pattern composed of multiple ridged protrusions ii) Pattern composed of multiple point-like protrusions iii) Patterns composed of multiple dimples iv) A pattern composed of a network of intersecting linear protrusions. [Aspect 5] A semiconductor manufacturing apparatus component according to any one of embodiments 1 to 4, wherein the upper surface and the side wall are connected via a chamfered portion, and the arithmetic mean roughness Ra4 of the surface of the chamfered portion is 0.4 μm or less. [Aspect 6] The arithmetic mean height Sa1 of the surface of the side wall is 1.1 μm or less, and the volume Vvv1 of the protruding valley space on the surface of the side wall is 0.5 ml / m 2 A semiconductor manufacturing apparatus component according to any one of embodiments 1 to 5 that satisfies one or both of the following conditions. [Aspect 7] The arithmetic mean height Sa4 of the chamfered surface is 1.1 μm or less, and the volume Vvv4 of the protruding valley space on the chamfered surface is 0.5 ml / m 2 A component for semiconductor manufacturing equipment according to embodiment 5, which satisfies one or both of the following conditions. [Aspect 8] The standard deviation of the arithmetic mean height Sa1 of the side wall surface is 0.1 μm or less, and the standard deviation of the volume Vvv1 of the protruding valley space on the side wall surface is 0.1 ml / m 2 A component for semiconductor manufacturing equipment according to any one of embodiments 1 to 7 that satisfies one or both of the following conditions. [Aspect 9] The standard deviation of the arithmetic mean height Sa4 of the chamfered surface is 0.1 μm or less, and the standard deviation of the protruding valley space volume Vvv4 of the chamfered surface is 0.1 ml / m 2 A semiconductor manufacturing apparatus component according to embodiment 5 or 7, which satisfies one or both of the following conditions. [Aspect 10] The semiconductor manufacturing apparatus component according to any one of embodiments 1 to 9, wherein the arithmetic mean roughness Ra1 of the surface of the side wall is smaller when measured in the circumferential direction of the ceramic substrate than when measured in the thickness direction of the ceramic substrate. [Aspect 11] A semiconductor manufacturing apparatus component according to any one of embodiments 1 to 10, wherein at least a portion of the side wall is covered by a coating layer, and the porosity of the coating layer is 2% or less. [Aspect 12] The central upper surface has multiple protrusions for placing wafers, The outer peripheral upper surface of the central upper surface, which is located at a lower position than the central upper surface, The central side wall that constitutes the step between the upper surface of the central part and the upper surface of the outer periphery, A ceramic substrate having, A component for semiconductor manufacturing equipment, comprising a ceramic substrate in which the arithmetic mean roughness Ra1 of the surface of the central side wall is smaller than the arithmetic mean roughness Ra2 of the upper surface of the outer periphery. [Aspect 13] The semiconductor manufacturing apparatus component according to embodiment 12, wherein the arithmetic mean roughness Ra1 of the surface of the central side wall is greater than the arithmetic mean roughness Ra3 of the upper end surfaces of the plurality of protrusions. [Aspect 14] The semiconductor manufacturing apparatus component according to embodiment 12 or 13, wherein the arithmetic mean roughness Ra1 of the surface of the central side wall is 0.4 μm or less. [Aspect 15] A semiconductor manufacturing apparatus component according to any one of embodiments 12 to 14, wherein the upper surface of the central portion and the side wall of the central portion are connected via a chamfered portion. [Aspect 16] The semiconductor manufacturing apparatus component according to embodiment 15, wherein the arithmetic mean roughness Ra4 of the surface of the chamfered portion is smaller than the arithmetic mean roughness Ra2 of the upper surface of the outer periphery portion. [Aspect 17] The semiconductor manufacturing apparatus component according to embodiment 15 or 16, wherein the arithmetic mean roughness Ra4 of the surface of the chamfered portion is greater than the arithmetic mean roughness Ra3 of the upper end surfaces of the plurality of protrusions. [Aspect 18] A semiconductor manufacturing apparatus component according to any one of embodiments 15 to 17, wherein the arithmetic mean roughness Ra4 of the surface of the chamfered portion is 0.4 μm or less. [Aspect 19] A semiconductor manufacturing apparatus component according to any one of embodiments 15 to 18, wherein the absolute value of the difference between the arithmetic mean roughness Ra4 of the surface of the chamfered portion and the arithmetic mean roughness Ra1 of the surface of the central portion side wall is 0.4 μm or less. [Aspect 20] A semiconductor manufacturing apparatus component according to any one of embodiments 12 to 19, wherein the surface of the central side wall has a patterned uneven shape. [Aspect 21] The semiconductor manufacturing apparatus component according to embodiment 20, wherein the patterned uneven shape is formed by laser processing. [Aspect 22] The semiconductor manufacturing apparatus member according to embodiment 20 or 21, wherein the surface of the central side wall has one or more patterned uneven shapes as described in i) to iii) below: i) A pattern composed of multiple point-like protrusions ii) Patterns composed of multiple dimples iii) A pattern composed of a network of intersecting linear protrusions. [Aspect 23] A semiconductor manufacturing apparatus component according to any one of embodiments 20 to 22, wherein the arithmetic mean roughness Ra1 of the surface of the central side wall is 0.4 μm or less. [Aspect 24] A semiconductor manufacturing apparatus component according to any one of claims 12 to 23, wherein at least a portion of the central side wall is covered by a coating layer, and the porosity of the coating layer is 2% or less. [Aspect 25] A component for semiconductor manufacturing equipment comprising a ceramic substrate having a top surface with a plurality of protrusions for placing a wafer and a side wall forming the outer edge of the top surface, wherein the arithmetic mean height Sa1 of the surface of the side wall is 1.1 μm or less. [Aspect 26] The semiconductor manufacturing apparatus component according to embodiment 25, wherein the upper surface and the side wall are connected via a chamfered portion, and the arithmetic mean height Sa4 of the surface of the chamfered portion is 0.1 μm or less. [Aspect 27] The semiconductor manufacturing apparatus component according to embodiment 25 or 26, wherein the standard deviation of the arithmetic mean height Sa1 of the surface of the side wall is 0.1 μm or less. [Aspect 28] A semiconductor manufacturing apparatus component according to embodiment 26 or embodiment 27 which is dependent on embodiment 26, wherein the standard deviation of the arithmetic mean height Sa4 of the surface of the chamfered portion is 0.1 μm or less. [Aspect 29] A semiconductor manufacturing apparatus component according to any one of embodiments 25 to 28, wherein at least a portion of the side wall is covered by a coating layer, and the porosity of the coating layer is 2% or less. [Effects of the Invention]

[0009] A semiconductor manufacturing apparatus component according to one embodiment of the present invention includes a ceramic substrate that is less prone to generating particles even if its sidewall is affected by plasma. Another embodiment of the present invention includes a semiconductor manufacturing apparatus component that is less prone to generating particles due to the influence of plasma even if plasma enters the gap between the focus ring and the wafer. For this reason, the semiconductor manufacturing apparatus component can contribute to improving the quality stability and yield of semiconductors. [Brief explanation of the drawing]

[0010] [Figure 1-1] This is a schematic partial longitudinal cross-sectional view of a semiconductor manufacturing apparatus component according to the first embodiment of the present invention (a partial cross-sectional view when cut by a plane including the central axis of the semiconductor manufacturing apparatus component). [Figure 1-2]Figure 1-1 shows a schematic magnified view of the area enclosed by the thick border. [Figure 1-3] This is a schematic plan view of a ceramic substrate according to the first embodiment of the present invention. [Figure 2-1] This is a schematic partial longitudinal cross-sectional view of a semiconductor manufacturing apparatus component according to the second embodiment of the present invention (a partial cross-sectional view when the semiconductor manufacturing apparatus component is cut by a plane including the central axis). [Figure 2-2] Figure 2-1 shows a schematic magnified view of the area enclosed by the thick border. [Figure 2-3] This is a schematic plan view of a ceramic substrate according to a second embodiment of the present invention. [Figure 3] An example of a patterned, uneven surface on the side wall is shown. [Figure 4] This is a manufacturing process diagram for a semiconductor manufacturing apparatus component according to a second embodiment of the present invention. [Modes for carrying out the invention]

[0011] Next, embodiments of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the following embodiments, and it should be understood that appropriate design changes, improvements, etc., may be made based on the ordinary knowledge of those skilled in the art, without departing from the spirit of the invention. Furthermore, in this specification, "up" and "down" are for convenience's purposes to represent the relative positional relationship when the ceramic substrate of the semiconductor manufacturing equipment component is placed on a horizontal plane with its upper surface facing upwards, and do not represent an absolute positional relationship. Therefore, depending on the orientation of the semiconductor manufacturing equipment component, "up" and "down" may become "down" and "up," "left" and "right," or "front" and "back."

[0012] <1. Configuration of components for semiconductor manufacturing equipment> Referring to the partial vertical cross-sectional views shown in Figures 1-1 and 2-1, the semiconductor manufacturing apparatus component 10 according to the first and second embodiments of the present invention can be used when performing processes such as CVD and etching on a wafer W using plasma. The semiconductor manufacturing apparatus component 10 according to the first and second embodiments comprises a ceramic substrate 20 having an upper surface 21 on which a wafer W can be placed and a lower surface 23, and incorporating electrodes 26. Furthermore, the semiconductor manufacturing apparatus component 10 according to the first and second embodiments comprises a base plate 30 located on the lower surface 23 side of the ceramic substrate 20 and incorporating a refrigerant flow path 32. The ceramic substrate 20 and the base plate 30 can be joined via a bonding layer 40.

[0013] The ceramic substrate 20 of the semiconductor manufacturing apparatus component 10 according to the first embodiment comprises a circular top surface 21 in plan view and side walls 28a that form the outer edge of the top surface 21. The ceramic substrate 20 can have, for example, a diameter of 300 to 400 mm and a thickness of 1 to 6 mm. A wafer W can be placed on the top surface 21.

[0014] The ceramic substrate 20 of the semiconductor manufacturing apparatus component 10 according to the second embodiment comprises a central portion 20a having a circular top surface 21 in plan view, and an outer peripheral portion 20b having an annular top surface 27 in plan view on the outer periphery of the central portion 20a. The central portion 20a of the ceramic substrate 20 can be, for example, 300 to 400 mm in diameter and 1 to 6 mm in thickness. A wafer W can be placed on the top surface 21 of the central portion 20a, and a focus ring can be placed on the top surface 27 of the outer peripheral portion 20b. Hereinafter, the focus ring may be abbreviated as "FR". A step is provided between the top surface 21 of the central portion 20a and the top surface 27 of the outer peripheral portion 20b, which is formed by the side wall 28b of the central portion 20a, so that the top surface 27 of the outer peripheral portion 20b is lower than the top surface 21 of the central portion 20a. The height (step) of the side wall 28b can be, for example, 0.5 to 5 mm. The lower surfaces 23 of the central portion 20a and the outer peripheral portion 20b may be on the same plane.

[0015] In the first embodiment, the upper surface 21 of the ceramic substrate 20 and in the second embodiment, the upper surface 21 of the central portion 20a of the ceramic substrate 20 are provided with a plurality of protrusions 22 for placing a wafer W. A sealing band 25 may also be formed along the outer edge of the upper surface 21. In this case, the wafer W may be supported by the upper end surface 21c of the sealing band 25 and the upper end surfaces 21a of the plurality of protrusions 22. It is preferable that the sealing band 25 and the plurality of protrusions 22 be of the same height. As shown in Figures 1-3 and 2-3, in one embodiment, an annular sealing band 25 is formed along the outer edge of the upper surface 21 of the ceramic substrate 20, and a plurality of protrusions 22 are formed over the entire inner surface of the sealing band 25.

[0016] In the ceramic substrate 20 of the first embodiment, smoothing the surface of the side wall 28a is effective in suppressing grain detachment. This is because smoothing reduces the number of microscopic protrusions that are prone to chipping. In addition, slurry and processing residues used in the manufacturing process accumulate in the microscopic depressions, becoming a source of particles. Therefore, it is preferable to perform polishing to smooth the surface of the side wall 28a. Polishing can also be expected to suppress the formation of a fractured layer and microcracks in the ceramics. More specifically, it is desirable to smooth the surface of the side wall 28a to the extent that the fractured layer, which is the starting point for grain detachment, is removed from the surface of the side wall 28a. Since the fractured layer is a fragile surface layer consisting of irregularities and cracks that occur during machining, removing the fractured layer and smoothing the surface can further reduce the risk of grain detachment. As an indicator that the fractured layer has been removed, it is preferable that the arithmetic mean roughness Ra1 of the surface of the side wall 28a is 0.4 μm or less, more preferably 0.3 μm or less, and even more preferably 0.1 μm or less. No particular lower limit is set for the arithmetic mean roughness Ra1 of the surface of the sidewall 28a, but from the viewpoint of cost-effectiveness, it is preferable to have a roughness of 0.05 μm or more. Therefore, the arithmetic mean roughness Ra1 of the surface of the sidewall 28a is preferably, for example, 0.05 to 0.4 μm, more preferably 0.05 to 0.3 μm, and even more preferably 0.05 to 0.1 μm.

[0017] The preferable range of the arithmetic mean roughness Ra1 of the surface of the side wall 28a should be satisfied regardless of the measurement direction. However, from the viewpoint of suppressing particles, the arithmetic mean roughness Ra1 of the surface of the side wall 28a is preferably smaller when measured in the circumferential direction of the ceramic substrate 20 than when measured in the thickness direction of the ceramic substrate 20.

[0018] In addition, the smoothness of the surface of the side wall 28a can also be discussed using the arithmetic mean height Sa1 and the protrusion valley space volume Vvv1, which are surface roughness parameters, in addition to the arithmetic mean roughness Ra1, which is a line roughness parameter. In this case, as a criterion for removing the crushed layer, the arithmetic mean height Sa1 of the surface of the side wall 28a is 1.1 μm or less, and the protrusion valley space volume Vvv1 of the surface of the side wall 28a is 0.5 ml / m 2 It is preferable to satisfy one or both of the following. The arithmetic mean height Sa1 of the surface of the side wall 28a is 0.6 μm or less, and the protrusion valley space volume Vvv1 of the surface of the side wall 28a is 0.2 ml / m 2 It is more preferable to satisfy one or both of the following. The arithmetic mean height Sa1 of the surface of the side wall 28a is 0.2 μm or less, and the protrusion valley space volume Vvv1 of the surface of the side wall 28a is 0.1 ml / m 2 It is even more preferable to satisfy one or both of the following. No particular lower limit is set for the arithmetic mean height Sa1 of the surface of the side wall 28a and the protrusion valley space volume Vvv1 of the surface of the side wall 28a. However, from the viewpoint of cost effectiveness, the arithmetic mean height Sa1 of the surface of the side wall 28a is 0.05 μm or more, and the protrusion valley space volume Vvv1 of the surface of the side wall 28a is 0.01 ml / m 2 It is preferable to satisfy one or both of the following. Therefore, for example, it is preferable to satisfy one or both of the following: the arithmetic mean height Sa1 of the surface of the side wall 28a is 0.05 to 1.1 μm, and the protrusion valley space volume Vvv1 of the surface of the side wall 28a is 0.01 to 0.5 ml / m 2 It is preferable to satisfy one or both of the following. The arithmetic mean height Sa1 of the surface of the side wall 28a is 0.05 to 0.6 μm, and the volume Vvv1 of the protruding valley space on the surface of the side wall 28a is 0.01 to 0.2 ml / m 2 It is more preferable that one or both of the following conditions be met. The arithmetic mean height Sa1 of the surface of the side wall 28a is 0.05 to 0.2 μm, and the volume Vvv1 of the protruding valley space on the surface of the side wall 28a is 0.01 to 0.1 ml / m 2 It is even more preferable that one or both of the following conditions are met.

[0019] From the standpoint of quality stability, it is desirable that the surface of the side wall 28a be uniformly smooth. Therefore, for example, the standard deviation of the arithmetic mean height Sa1 of the surface of the side wall 28a should be 0.1 μm or less, and the standard deviation of the volume of the protruding valley space Vvv1 on the surface of the side wall 28a should be 0.1 ml / m 2 It is preferable that one or both of the following conditions are met: The standard deviation of the arithmetic mean height Sa1 of the surface of the side wall 28a is 0.02 μm or less, and the standard deviation of the volume Vvv1 of the protruding valley space on the surface of the side wall 28a is 0.03 ml / m 2 It is more preferable that one or both of the following conditions be met: The standard deviation of the arithmetic mean height Sa1 of the surface of the side wall 28a is 0.005 μm or less, and the standard deviation of the volume Vvv1 of the protruding valley space on the surface of the side wall 28a is 0.02 ml / m 2 It is even more preferable that one or both of the following conditions are met: While no specific lower limit is set for the standard deviation of the arithmetic mean height Sa1 of the surface of the side wall 28a, or the standard deviation of the volume of the protruding valley space Vvv1 on the surface of the side wall 28a, from a cost-effectiveness standpoint, it is desirable that the standard deviation of the arithmetic mean height Sa1 of the surface of the side wall 28a be 0.001 μm or more, and that the standard deviation of the volume of the protruding valley space Vvv1 on the surface of the side wall 28a be 0.001 ml / m 2 It is preferable that one or both of the above conditions be met. Therefore, for example, the standard deviation of the arithmetic mean height Sa1 of the surface of the side wall 28a is 0.001 to 0.1 μm, and the standard deviation of the volume Vvv1 of the protruding valley space on the surface of the side wall 28a is 0.001 to 0.1 ml / m 2 It is preferable that one or both of the following conditions be met. The standard deviation of the arithmetic mean height Sa1 of the surface of the side wall 28a is 0.001 to 0.02 μm, and the standard deviation of the volume Vvv1 of the protruding valley space on the surface of the side wall 28a is 0.001 to 0.03 ml / m 2 It is more preferable that one or both of the following conditions be met. The standard deviation of the arithmetic mean height Sa1 of the surface of the side wall 28a is 0.001 to 0.005 μm, and the standard deviation of the volume Vvv1 of the protruding valley space on the surface of the side wall 28a is 0.001 to 0.02 ml / m 2 It is even more preferable that one or both of the following conditions are met.

[0020] The same applies to the ceramic substrate 20 of the second embodiment. Typically, both the side wall 28b of the central portion 20a and the upper surface 27 of the outer peripheral portion 20b of the ceramic substrate 20 of the second embodiment are formed by machining, such as cutting. If no special polishing is performed after machining, the side wall 28b of the central portion 20a and the upper surface 27 of the outer peripheral portion 20b have similar surface roughness. It is preferable that the ceramic particles constituting the side wall 28b of the central portion 20a are less likely to fall off when affected by plasma. Smoothing the surface of the side wall 28b is effective in suppressing particle fall-off. This is because smoothing reduces the number of microscopic protrusions that are prone to chipping. On the other hand, the upper surface 27 of the outer peripheral portion 20b is the mounting surface for the focus ring, and is protected by the focus ring, so there is little need to smooth it. From the viewpoint of manufacturing costs, it is desirable not to perform unnecessary polishing on the upper surface 27 of the outer peripheral portion 20b.

[0021] Therefore, when polishing is performed to smooth the surface of the side wall 28b of the central part 20a, the arithmetic mean roughness Ra1 of the surface of the side wall 28b of the central part 20a becomes smaller than the arithmetic mean roughness Ra2 of the upper surface 27 of the outer periphery 20b. More specifically, it is desirable to smooth the surface of the side wall 28b of the central part 20a to the extent that the crushed layer, which is the starting point for detachment, is removed from the surface of the side wall 28b of the central part 20a. Since the crushed layer is a fragile surface layer such as irregularities and cracks that occur during machining, removing the crushed layer and leaving a smooth surface can further reduce the risk of detachment. As an indicator that the crushed layer has been removed, it is preferable that the arithmetic mean roughness Ra1 of the surface of the side wall 28b of the central part 20a is 0.4 μm or less, more preferably 0.3 μm or less, and even more preferably 0.1 μm or less. No particular lower limit is set for the arithmetic mean roughness Ra1 of the surface of the side wall 28b of the central portion 20a, but from the viewpoint of cost-effectiveness, it is preferable to have a roughness of 0.05 μm or more. Therefore, the arithmetic mean roughness Ra1 of the surface of the side wall 28b of the central portion 20a is preferably, for example, 0.05 to 0.4 μm, more preferably 0.05 to 0.3 μm, and even more preferably 0.05 to 0.1 μm.

[0022] The preferred range for the arithmetic mean roughness Ra1 of the surface of the side wall 28b of the central portion 20a should be satisfied regardless of the measurement direction. However, from the viewpoint of suppressing particles, it is preferable that the arithmetic mean roughness Ra1 of the surface of the side wall 28b of the central portion 20a is smaller when measured in the circumferential direction of the ceramic substrate 20 than when measured in the thickness direction of the ceramic substrate 20.

[0023] Furthermore, the smoothness of the surface of the side wall 28b of the central portion 20a can be discussed not only using the arithmetic mean roughness Ra1, which is a linear roughness parameter, but also using the arithmetic mean height Sa1 and the volume of protruding valleys Vvv1, which are surface roughness parameters. Therefore, when polishing is performed to smooth the surface of the side wall 28b of the central portion 20a, the arithmetic mean height Sa1 of the surface of the side wall 28b of the central portion 20a becomes smaller than the arithmetic mean height Sa2 of the upper surface 27 of the outer peripheral portion 20b, and the volume of protruding valleys Vvv1 of the surface of the side wall 28b of the central portion 20a becomes smaller than the volume of protruding valleys Vvv2 of the upper surface 27 of the outer peripheral portion 20b. As an indicator that the fractured layer has been removed, the arithmetic mean height Sa1 of the surface of the side wall 28b of the central portion 20a is 1.1 μm or less, and the volume of protruding valleys Vvv1 of the surface of the side wall 28b of the central portion 20a is 0.5 ml / m 2 It is preferable that one or both of the following conditions are met: The arithmetic mean height Sa1 of the surface of the side wall 28b of the central portion 20a is 0.6 μm or less, and the volume Vvv1 of the protruding valley space on the surface of the side wall 28b of the central portion 20a is 0.2 ml / m 2 It is more preferable that one or both of the following conditions be met: The arithmetic mean height Sa1 of the surface of the side wall 28b of the central portion 20a is 0.2 μm or less, and the volume Vvv1 of the protruding valley space on the surface of the side wall 28b of the central portion 20a is 0.1 ml / m 2 It is even more preferable that one or both of the following conditions are met: No specific lower limits are set for the arithmetic mean height Sa1 of the surface of the side wall 28b of the central section 20a, and for the volume Vvv1 of the protruding valley space on the surface of the side wall 28b of the central section 20a. However, from a cost-effectiveness standpoint, it is desirable that the arithmetic mean height Sa1 of the surface of the side wall 28b of the central section 20a be 0.05 μm or more, and that the volume Vvv1 of the protruding valley space on the surface of the side wall 28b of the central section 20a be 0.01 ml / m 2 It is preferable that one or both of the above conditions be met. Therefore, for example, the arithmetic mean height Sa1 of the surface of the side wall 28b of the central portion 20a is 0.05 to 1.1 μm, and the volume Vvv1 of the protruding valley space on the surface of the side wall 28b of the central portion 20a is 0.01 to 0.5 ml / m 2It is preferable that one or both of the following conditions be met. The arithmetic mean height Sa1 of the surface of the side wall 28b of the central portion 20a is 0.05~0.6 μm, and the volume Vvv1 of the protruding valley space on the surface of the side wall 28b of the central portion 20a is 0.01~0.2 ml / m 2 It is more preferable that one or both of the following conditions be met. The arithmetic mean height Sa1 of the surface of the side wall 28b of the central portion 20a is 0.05 to 0.2 μm, and the volume Vvv1 of the protruding valley space on the surface of the side wall 28b of the central portion 20a is 0.01 to 0.1 ml / m 2 It is even more preferable that one or both of the following conditions are met.

[0024] From the standpoint of quality stability, it is desirable that the surface of the side wall 28b of the central portion 20a be uniformly smooth. Therefore, for example, the standard deviation of the arithmetic mean height Sa1 of the surface of the side wall 28b of the central portion 20a should be 0.1 μm or less, and the standard deviation of the volume of the protruding valley space Vvv1 on the surface of the side wall 28b of the central portion 20a should be 0.1 ml / m 2 It is preferable that one or both of the following conditions are met: The standard deviation of the arithmetic mean height Sa1 of the surface of the side wall 28b of the central part 20a is 0.02 μm or less, and the standard deviation of the volume Vvv1 of the protruding valley space on the surface of the side wall 28b of the central part 20a is 0.003 ml / m 2 It is more preferable that one or both of the following conditions be met: The standard deviation of the arithmetic mean height Sa1 of the surface of the side wall 28b of the central part 20a is 0.005 μm or less, and the standard deviation of the volume Vvv1 of the protruding valley space on the surface of the side wall 28b of the central part 20a is 0.002 ml / m 2 It is even more preferable that one or both of the following conditions are met: While no specific lower limit is set for the standard deviation of the arithmetic mean height Sa1 of the surface of the side wall 28b of the central section 20a, and the standard deviation of the protruding valley space volume Vvv1 of the surface of the side wall 28b of the central section 20a, from a cost-effectiveness standpoint, it is desirable that the standard deviation of the arithmetic mean height Sa1 of the surface of the side wall 28b of the central section 20a be 0.001 μm or more, and that the standard deviation of the protruding valley space volume Vvv1 of the surface of the side wall 28b of the central section 20a be 0.001 ml / m 2 It is preferable that one or both of the above conditions be met. Therefore, for example, the standard deviation of the arithmetic mean height Sa1 of the surface of the side wall 28b of the central part 20a is 0.001 to 0.1 μm, and the standard deviation of the volume Vvv1 of the protruding valley space on the surface of the side wall 28b of the central part 20a is 0.001 to 0.1 ml / m 2 It is preferable that one or both of the following conditions be met. The standard deviation of the arithmetic mean height Sa1 of the surface of the side wall 28b of the central part 20a is 0.001 to 0.02 μm, and the standard deviation of the volume Vvv1 of the protruding valley space on the surface of the side wall 28b of the central part 20a is 0.001 to 0.003 ml / m 2 It is more preferable that one or both of the following conditions be met. The standard deviation of the arithmetic mean height Sa1 of the surface of the side wall 28b of the central part 20a is 0.001 to 0.005 μm, and the standard deviation of the volume Vvv1 of the protruding valley space on the surface of the side wall 28b of the central part 20a is 0.001 to 0.002 ml / m 2 It is even more preferable that one or both of the following conditions are met.

[0025] In the first embodiment, the surface of the side wall 28a of the ceramic substrate 20, and in the second embodiment, the surface of the side wall 28b of the central portion 20a of the ceramic substrate 20, preferably have a patterned uneven surface. The patterned uneven surface can be formed, for example, by laser processing after polishing. Alternatively, after forming the pattern by laser processing, the pattern may be mirror-finished by soft blasting. By-products flying from inside the chamber during wafer processing may adhere to the side walls 28a and 28b like a film. In this case, if the side walls 28a and 28b have a patterned uneven surface, the advantage is that the attached particles are less likely to fall off due to the anchoring effect. However, even if the side walls 28a and 28b have a patterned uneven surface, it is preferable that the surfaces of the side walls 28a and 28b satisfy the above-mentioned arithmetic mean roughness condition. This is to suppress particle shedding from the surfaces of the side walls 28a and 28b.

[0026] There are no particular restrictions on the patterned uneven surface structure. Figure 3 shows five specific examples of patterned uneven surfaces on the side walls 28a and 28b.

[0027] The uneven shape of No. 1 has a pattern composed of multiple striated protrusions. The line width of each striated protrusion can be, for example, 20 to 200 μm.

[0028] The uneven shape of No. 2 has a pattern composed of multiple dot-like protrusions. Each dot-like protrusion in No. 2 is relatively small. It is preferable that the multiple dot-like protrusions are arranged evenly on the surface of the side walls 28a and 28b. The area of ​​each dot-like protrusion when observed from a direction perpendicular to the surface is, for example, 200 to 25000 μm². 2 It can be done this way.

[0029] The uneven shape of No. 3 also has a pattern composed of multiple point-like protrusions. Each point-like protrusion in No. 3 is relatively large. It is preferable that the multiple point-like protrusions are arranged evenly on the surface of the side walls 28a and 28b. The area of ​​each point-like protrusion when observed from a direction perpendicular to the surface is, for example, 2000 to 250000 μm².2 This can be done. The uneven shape of No. 2 and the uneven shape of No. 3 differ in the area of ​​each point-like protrusion.

[0030] The uneven shape of No. 4 has a pattern consisting of a reference surface and multiple dimples (point-like recesses) provided on the reference surface. It is preferable that the multiple dimples are arranged evenly on the surfaces of the side walls 28a and 28b. The area of ​​each dimple when observed from a direction perpendicular to the surface is, for example, 200 to 25000 μm². 2 It can be done this way.

[0031] The uneven shape of No. 5 has a pattern composed of a mesh-like structure where multiple linear protrusions intersect. In the illustrated embodiment, each mesh of the mesh-like protrusion is hexagonal (honeycomb-like), but each mesh of the mesh-like protrusion may be a triangle, square, pentagon, octagon, or other polygonal shape, or a combination of multiple polygonal shapes such as a pentagon and a triangle. The line width of each linear protrusion when observed from a direction perpendicular to the surface can be, for example, 20 to 200 μm. The area of ​​each mesh when observed from a direction perpendicular to the surface can be, for example, 2000 to 250000 μm. 2 It can be done this way.

[0032] In the first embodiment, it is preferable that the upper surface 21 and the side wall 28a of the ceramic substrate 20 are connected via a chamfered portion 29. Similarly, in the second embodiment, it is preferable that the upper surface 21 of the central portion 20a and the side wall 28b of the central portion 20a of the ceramic substrate 20 are connected via a chamfered portion 29. Chamfering the corners of the wafer mounting surface is advantageous in terms of suppressing the fractured layer at the corners and preventing grain detachment. Examples of the shape of the chamfered portion 29 include, but are not limited to, C-chamfers and R-chamfers. Although the area of ​​the chamfered portion 29 is small, it is a part that can be affected by plasma during wafer processing, and it is desirable to keep the surface smooth. For this reason, for example, in the ceramic substrate 20 of the second embodiment, it is preferable that the arithmetic mean roughness Ra4 of the surface of the chamfered portion 29 is smaller than the arithmetic mean roughness Ra2 of the upper surface 27 of the outer peripheral portion 20b. Furthermore, in the ceramic substrate 20 of the second embodiment, it is preferable that the arithmetic mean height Sa4 of the surface of the chamfered portion 29 is smaller than the arithmetic mean height Sa2 of the upper surface 27 of the outer peripheral portion 20b. Also, in the ceramic substrate 20 of the second embodiment, it is preferable that the volume Vvv4 of the protruding valley space on the surface of the chamfered portion 29 is smaller than the volume Vvv2 of the protruding valley space on the upper surface 27 of the outer peripheral portion 20b.

[0033] In both the ceramic substrate 20 of the first embodiment and the ceramic substrate 20 of the second embodiment, the arithmetic mean roughness Ra4 of the surface of the chamfered portion 29 is preferably 0.4 μm or less, more preferably 0.3 μm or less, and even more preferably 0.1 μm or less. No particular lower limit is set for the arithmetic mean roughness Ra4 of the surface of the chamfered portion 29, but from the viewpoint of cost-effectiveness, it is preferably 0.05 μm or more. Therefore, the arithmetic mean roughness Ra4 of the surface of the chamfered portion 29 is preferably, for example, 0.05 to 0.4 μm, more preferably 0.05 to 0.3 μm, and even more preferably 0.05 to 0.1 μm.

[0034] Furthermore, in both the ceramic substrate 20 of the first embodiment and the ceramic substrate 20 of the second embodiment, the arithmetic mean height Sa4 of the surface of the chamfered portion 29 is 1.1 μm or less, and the volume of the protruding valley space Vvv4 on the surface of the chamfered portion 29 is 0.5 ml / m 2 It is preferable that one or both of the following conditions are met: The arithmetic mean height Sa4 of the surface of the chamfered portion 29 is 0.8 μm or less, and the volume Vvv4 of the protruding valley space on the surface of the chamfered portion 29 is 0.2 ml / m 2 It is more preferable that one or both of the following conditions be met: The arithmetic mean height Sa4 of the surface of the chamfered portion 29 is 0.5 μm or less, and the volume Vvv4 of the protruding valley space on the surface of the chamfered portion 29 is 0.1 ml / m 2 It is even more preferable that one or both of the following conditions are met: No specific lower limits are set for the arithmetic mean height Sa4 of the chamfered portion 29 surface, or the volume of the protruding valley space Vvv4 of the chamfered portion 29 surface. However, from a cost-effectiveness standpoint, it is desirable that the arithmetic mean height Sa4 of the chamfered portion 29 surface be 0.2 μm or more, and that the volume of the protruding valley space Vvv4 of the chamfered portion 29 surface be 0.01 ml / m 2 It is preferable that one or both of the above conditions be met. Therefore, for example, the arithmetic mean height Sa4 of the surface of the chamfered portion 29 is 0.2 to 1.1 μm, and the volume Vvv4 of the protruding valley space on the surface of the side wall 28a is 0.01 to 0.5 ml / m 2 It is preferable that one or both of the following conditions be met. The arithmetic mean height Sa4 of the surface of the chamfered portion 29 is 0.2 to 0.8 μm, and the volume Vvv4 of the protruding valley space on the surface of the chamfered portion 29 is 0.01 to 0.2 ml / m 2 It is more preferable that one or both of the following conditions be met. The arithmetic mean height Sa4 of the surface of the chamfered portion 29 is 0.2 to 0.5 μm, and the volume Vvv4 of the protruding valley space on the surface of the chamfered portion 29 is 0.01 to 0.1 ml / m 2 It is even more preferable that one or both of the following conditions are met.

[0035] From the standpoint of quality stability, it is desirable that the surface of the chamfered portion 29 be uniformly smooth. Therefore, for example, the standard deviation of the arithmetic mean height Sa4 of the surface of the chamfered portion 29 should be 0.1 μm or less, and the standard deviation of the volume of the protruding valley space Vvv4 on the surface of the chamfered portion 29 should be 0.1 ml / m 2 It is preferable that one or both of the following conditions are met: The standard deviation of the arithmetic mean height Sa4 of the chamfered portion 29 surface is 0.02 μm or less, and the standard deviation of the protruding valley space volume Vvv4 of the chamfered portion 29 surface is 0.03 ml / m 2 It is more preferable that one or both of the following conditions be met: The standard deviation of the arithmetic mean height Sa4 of the chamfered portion 29 surface is 0.005 μm or less, and the standard deviation of the protruding valley space volume Vvv4 of the chamfered portion 29 surface is 0.02 ml / m 2 It is even more preferable that one or both of the following conditions are met: While no specific lower limit is set for the standard deviation of the arithmetic mean height Sa4 of the chamfered portion 29 surface, or the standard deviation of the protruding valley space volume Vvv4 of the chamfered portion 29 surface, from a cost-effectiveness standpoint, it is desirable that the standard deviation of the arithmetic mean height Sa4 of the chamfered portion 29 surface be 0.001 μm or more, and that the standard deviation of the protruding valley space volume Vvv4 of the chamfered portion 29 surface be 0.001 ml / m 2 It is preferable that one or both of the above conditions be met. Therefore, for example, the standard deviation of the arithmetic mean height Sa4 of the surface of the chamfered portion 29 is 0.001 to 0.1 μm, and the standard deviation of the volume Vvv4 of the protruding valley space on the surface of the chamfered portion 29 is 0.001 to 0.1 ml / m 2 It is preferable that one or both of the following conditions be met. The standard deviation of the arithmetic mean height Sa4 of the chamfered portion 29 surface is 0.001 to 0.02 μm, and the standard deviation of the protruding valley space volume Vvv4 of the chamfered portion 29 surface is 0.001 to 0.03 ml / m 2 It is more preferable that one or both of the following conditions be met. The standard deviation of the arithmetic mean height Sa4 of the chamfered portion 29 surface is 0.001 to 0.005 μm, and the standard deviation of the volume Vvv4 of the protruding valley space on the chamfered portion 29 surface is 0.001 to 0.02 ml / m 2 It is even more preferable that one or both of the following conditions are met.

[0036] Thus, the required level of smoothness for the surfaces of the side walls 28a and 28b and the chamfered portion 29 is approximately the same. Therefore, it is convenient for quality control to perform the same polishing process on these surfaces and set their surface roughness to approximately the same level. Accordingly, the absolute value of the difference between the arithmetic mean roughness Ra4 of the chamfered portion 29 and the arithmetic mean roughness Ra1 of the side walls 28a and 28b is preferably 0.4 μm or less, more preferably 0.2 μm or less, and even more preferably 0.1 μm or less. The absolute value of this difference may be 0.

[0037] Furthermore, the absolute value of the difference between the arithmetic mean height Sa4 of the surface of the chamfered portion 29 and the arithmetic mean height Sa1 of the surfaces of the side walls 28a and 28b is 0.4 μm or less, and the absolute value of the difference between the volume Vvv4 of the protruding valley space on the surface of the chamfered portion 29 and the volume Vvv1 of the protruding valley space on the surfaces of the side walls 28a and 28b is 0.4 ml / m 2 It is preferable that one or both of the following conditions are met: The absolute value of the difference between the arithmetic mean height Sa4 of the surface of the chamfered portion 29 and the arithmetic mean height Sa1 of the surfaces of the side walls 28a and 28b is 0.3 μm or less, and the absolute value of the difference between the volume Vvv4 of the protruding valley space on the surface of the chamfered portion 29 and the volume Vvv1 of the protruding valley space on the surfaces of the side walls 28a and 28b is 0.3 ml / m 2 It is more preferable that one or both of the following conditions be met: The absolute value of the difference between the arithmetic mean height Sa4 of the surface of the chamfered portion 29 and the arithmetic mean height Sa1 of the surfaces of the side walls 28a and 28b is 0.2 μm or less, and the absolute value of the difference between the volume Vvv4 of the protruding valley space on the surface of the chamfered portion 29 and the volume Vvv1 of the protruding valley space on the surfaces of the side walls 28a and 28b is 0.2 ml / m 2 It is even more preferable that one or both of the following conditions are met: The absolute value of the difference between the arithmetic mean height Sa4 of the surface of the chamfered portion 29 and the arithmetic mean height Sa1 of the surfaces of the side walls 28a and 28b may be 0. The absolute value of the difference between the protruding valley space volume Vvv4 of the surface of the chamfered portion 29 and the protruding valley space volume Vvv1 of the surfaces of the side walls 28a and 28b may be 0.

[0038] Figures 1-2 and 2-2 show the schematic structure of the projections 22 provided on the upper surface 21 of the ceramic substrate 20 in the first and second embodiments, respectively. The shape of the projections 22 is not limited, but can be a columnar shape such as a cylinder or a rectangular prism. The height h of the projections 22 is, for example, 5 to 100 μm, and can typically be 10 to 30 μm. The diameter d of the projections 22 is, for example, 0.5 to 5 mm, and can typically be 0.5 to 3 mm. Here, the diameter d of the projections 22 refers to the equivalent diameter of a circle when the projections 22 are viewed from above. The portion of the upper surface 21 of the ceramic substrate 20 that does not have the seal band 25 or projections 22 is referred to as the reference surface 21b.

[0039] Each of the multiple protrusions 22 has an upper end surface 21a. The wafer W in contact with the upper end surface 21a of the protrusion 22 may slide against the upper end surface 21a of the protrusion 22 due to thermal expansion or the like. To suppress the shedding of ceramic particles constituting the protrusion 22 during sliding, it is desirable to make the upper end surface 21a of the protrusion 22 as smooth as possible. For example, it is preferable that the arithmetic mean roughness Ra3 of the upper end surfaces 21a of the multiple protrusions 22 is smaller than the arithmetic mean roughness Ra1 of the surfaces of the side walls 28a and 28b (in other words, the arithmetic mean roughness Ra1 of the surfaces of the side walls 28a and 28b is larger than the arithmetic mean roughness Ra3 of the upper end surfaces 21a of the multiple protrusions 22). Furthermore, it is preferable that the arithmetic mean height Sa3 of the upper end surfaces 21a of the multiple protrusions 22 is smaller than the arithmetic mean height Sa1 of the surfaces of the side walls 28a and 28b (in other words, the arithmetic mean height Sa1 of the surfaces of the side walls 28a and 28b is larger than the arithmetic mean height Sa3 of the upper end surfaces 21a of the multiple protrusions 22). Furthermore, it is preferable that the volume Vvv3 of the protruding valley space of the upper end surfaces 21a of the multiple protrusions 22 is smaller than the volume Vvv1 of the protruding valley space of the surfaces of the side walls 28a and 28b (in other words, the volume Vvv1 of the protruding valley space of the surfaces of the side walls 28a and 28b is larger than the volume Vvv3 of the protruding valley space of the upper end surfaces 21a of the multiple protrusions 22).

[0040] Similarly, it is preferable that the arithmetic mean roughness Ra3 of the upper end faces 21a of the multiple protrusions 22 is smaller than the arithmetic mean roughness Ra4 of the surface of the chamfered portion 29 (in other words, the arithmetic mean roughness Ra4 of the surface of the chamfered portion 29 is larger than the arithmetic mean roughness Ra3 of the upper end faces 21a of the multiple protrusions 22). Furthermore, it is preferable that the arithmetic mean height Sa3 of the upper end faces 21a of the multiple protrusions 22 is smaller than the arithmetic mean height Sa4 of the surface of the chamfered portion 29 (in other words, the arithmetic mean height Sa4 of the surface of the chamfered portion 29 is larger than the arithmetic mean height Sa3 of the upper end faces 21a of the multiple protrusions 22). Furthermore, it is preferable that the volume Vvv3 of the protruding valley space of the upper end faces 21a of the multiple protrusions 22 is smaller than the arithmetic mean height Sa4 of the surface of the chamfered portion 29 (in other words, the arithmetic mean height Sa4 of the surface of the chamfered portion 29 is larger than the arithmetic mean height Sa3 of the upper end faces 21a of the multiple protrusions 22).

[0041] Specifically, the arithmetic mean roughness Ra3 of the upper end surfaces 21a of the multiple protrusions 22 is preferably 0.4 μm or less, more preferably 0.2 μm or less, and even more preferably 0.1 μm or less. No particular lower limit is set for the arithmetic mean roughness Ra3 of the upper end surfaces 21a of the multiple protrusions 22, but from the viewpoint of cost-effectiveness, it is preferably 0.05 μm or more. Therefore, the arithmetic mean roughness Ra3 of the upper end surfaces 21a of the multiple protrusions 22 is preferably 0.05 to 0.4 μm, more preferably 0.05 to 0.2 μm, and even more preferably 0.05 to 0.1 μm.

[0042] Furthermore, the arithmetic mean height Sa3 of the upper end surfaces 21a of the multiple protrusions 22 is 0.1 μm or less, and the volume Vvv3 of the protruding valley space of the upper end surfaces 21a of the multiple protrusions 22 is 0.01 ml / m 2 It is preferable that one or both of the following conditions are met: The arithmetic mean height Sa3 of the upper end surfaces 21a of the multiple protrusions 22 is 0.05 μm or less, and the volume Vvv3 of the protruding valley space of the upper end surfaces 21a of the multiple protrusions 22 is 0.005 ml / m 2 It is more preferable that one or both of the following conditions be met: The arithmetic mean height Sa3 of the upper end surfaces 21a of the multiple protrusions 22 is 0.03 μm or less, and the volume Vvv3 of the protruding valley space of the upper end surfaces 21a of the multiple protrusions 22 is 0.003 ml / m 2 It is even more preferable that one or both of the following conditions are met: No specific lower limit is set for the arithmetic mean height Sa3 of the upper end surfaces 21a of the multiple protrusions 22, or for the volume Vvv3 of the protruding valley space of the upper end surfaces 21a of the multiple protrusions 22. However, from the viewpoint of cost-effectiveness, it is desirable that the arithmetic mean height Sa3 of the upper end surfaces 21a of the multiple protrusions 22 be 0.01 μm or more, and that the volume Vvv3 of the protruding valley space of the upper end surfaces 21a of the multiple protrusions 22 be 0.001 ml / m 2 It is preferable that one or both of the above conditions be met. Therefore, for example, the arithmetic mean height Sa3 of the upper end surfaces 21a of the multiple protrusions 22 is 0.01 to 0.1 μm, and the volume Vvv3 of the protruding valley space of the upper end surfaces 21a of the multiple protrusions 22 is 0.001 to 0.01 ml / m 2 It is preferable that one or both of the following conditions be met. The arithmetic mean height Sa3 of the upper end surfaces 21a of the multiple protrusions 22 is 0.01 to 0.05 μm, and the volume Vvv3 of the protruding valley space of the upper end surfaces 21a of the multiple protrusions 22 is 0.001 to 0.005 ml / m 2 It is more preferable that one or both of the following conditions be met. The arithmetic mean height Sa3 of the upper end surfaces 21a of the multiple protrusions 22 is 0.01 to 0.03 μm, and the volume Vvv3 of the protruding valley space of the upper end surfaces 21a of the multiple protrusions 22 is 0.001 to 0.003 ml / m 2 It is even more preferable that one or both of the following conditions are met.

[0043] For similar reasons, the arithmetic mean roughness Ra5 of the upper end surface 21c of the seal band 25 is preferably 0.4 μm or less, more preferably 0.2 μm or less, and even more preferably 0.1 μm or less. No particular lower limit is set for the arithmetic mean roughness Ra5 of the upper end surface 21c of the seal band 25, but from the viewpoint of cost-effectiveness, it is preferably 0.05 μm or more. Therefore, the arithmetic mean roughness Ra5 of the upper end surface 21c of the seal band 25 is preferably 0.05 to 0.4 μm, more preferably 0.05 to 0.2 μm, and even more preferably 0.05 to 0.1 μm.

[0044] Furthermore, the arithmetic mean height Sa5 of the upper end surface 21c of the seal band 25 is 0.1 μm or less, and the volume Vvv5 of the protruding valley space of the upper end surface 21c of the seal band 25 is 0.01 ml / m 2 It is preferable that one or both of the following conditions are met: The arithmetic mean height Sa5 of the upper end surface 21c of the seal band 25 is 0.05 μm or less, and the volume Vvv5 of the protruding valley space of the upper end surface 21c of the seal band 25 is 0.005 ml / m 2It is more preferable that one or both of the following conditions be met: The arithmetic mean height Sa5 of the upper end surface 21c of the seal band 25 is 0.03 μm or less, and the volume Vvv5 of the protruding valley space of the upper end surface 21c of the seal band 25 is 0.003 ml / m 2 It is even more preferable that one or both of the following conditions are met: No specific lower limits are set for the arithmetic mean height Sa5 of the upper end surface 21c of the seal band 25, and the volume Vvv5 of the protruding valley space of the upper end surface 21c of the seal band 25. However, from the viewpoint of cost-effectiveness, the arithmetic mean height Sa5 of the upper end surface 21c of the seal band 25 should be 0.01 μm or more, and the volume Vvv5 of the protruding valley space of the upper end surface 21c of the seal band 25 should be 0.001 ml / m 2 It is preferable that one or both of the above conditions be met. Therefore, for example, the arithmetic mean height Sa5 of the upper end surface 21c of the seal band 25 is 0.01 to 0.1 μm, and the volume Vvv5 of the protruding valley space of the upper end surface 21c of the seal band 25 is 0.001 to 0.01 ml / m 2 It is preferable that one or both of the following conditions be met. The arithmetic mean height Sa5 of the upper end surface 21c of the seal band 25 is 0.01 to 0.05 μm, and the volume Vvv5 of the protruding valley space of the upper end surface 21c of the seal band 25 is 0.001 to 0.005 ml / m 2 It is more preferable that one or both of the following conditions be met. The arithmetic mean height Sa5 of the upper end surface 21c of the seal band 25 is 0.01 to 0.03 μm, and the volume Vvv5 of the protruding valley space of the upper end surface 21c of the seal band 25 is 0.001 to 0.003 ml / m 2 It is even more preferable that one or both of the following conditions are met.

[0045] The reference surface 21b of the upper surface 21 of the ceramic substrate 20 is not intended to slide against the wafer W, but it may be affected by the plasma during wafer processing. Therefore, it is desirable to keep the reference surface 21b smooth. For this reason, for example, in the ceramic substrate 20 according to the second embodiment, it is preferable that the arithmetic mean roughness Ra6 of the reference surface 21b is smaller than the arithmetic mean roughness Ra2 of the upper surface 27 of the outer peripheral portion 20b. Also, in the ceramic substrate 20 according to the second embodiment, it is preferable that the arithmetic mean height Sa6 of the reference surface 21b is smaller than the arithmetic mean height Sa2 of the upper surface 27 of the outer peripheral portion 20b. In the ceramic substrate 20 according to the second embodiment, it is preferable that the volume Vvv6 of the protruding valley space on the reference surface 21b is smaller than the volume Vvv2 of the protruding valley space on the upper surface 27 of the outer peripheral portion 20b.

[0046] In both the ceramic substrate 20 of the first embodiment and the ceramic substrate 20 of the second embodiment, the arithmetic mean roughness Ra6 of the reference surface 21b is preferably 0.4 μm or less, more preferably 0.2 μm or less, and even more preferably 0.1 μm or less. No particular lower limit is set for the arithmetic mean roughness Ra6 of the reference surface 21b, but from the viewpoint of cost-effectiveness, it is preferably 0.05 μm or more. Therefore, the arithmetic mean roughness Ra6 of the reference surface 21b is preferably, for example, 0.05 to 0.4 μm, more preferably 0.05 to 0.2 μm, and even more preferably 0.05 to 0.1 μm.

[0047] Furthermore, in both the ceramic substrate 20 of the first embodiment and the ceramic substrate 20 of the second embodiment, the arithmetic mean height Sa6 of the reference surface 21b is 0.9 μm or less, and the volume Vvv6 of the protruding valley space of the reference surface 21b is 0.2 ml / m 2 It is preferable that one or both of the following conditions are met: The arithmetic mean height Sa6 of the reference plane 21b is 0.8 μm or less, and the volume Vvv6 of the protruding valley space of the reference plane 21b is 0.15 ml / m 2 It is more preferable that one or both of the following conditions be met: The arithmetic mean height Sa6 of the reference plane 21b is 0.7 μm or less, and the volume Vvv6 of the protruding valley space of the reference plane 21b is 0.1 ml / m 2 It is even more preferable that one or both of the following conditions are met: No specific lower limits are set for the arithmetic mean height Sa6 of the reference surface 21b and the volume Vvv6 of the protruding valley space of the reference surface 21b. However, from a cost-effectiveness standpoint, it is desirable that the arithmetic mean height Sa6 of the reference surface 21b be 0.05 μm or more, and that the volume Vvv6 of the protruding valley space of the reference surface 21b be 0.01 ml / m 2 It is preferable that one or both of the above conditions be met. Therefore, for example, the arithmetic mean height Sa6 of the reference plane 21b is 0.05~0.9 μm, and the volume Vvv6 of the protruding valley space of the reference plane 21b is 0.01~0.2 ml / m 2 It is preferable that one or both of the following conditions be met. The arithmetic mean height Sa6 of the reference plane 21b is 0.05 to 0.8 μm, and the volume Vvv6 of the protruding valley space of the reference plane 21b is 0.01 to 0.15 ml / m 2 It is more preferable that one or both of the following conditions be met. The arithmetic mean height Sa6 of the reference plane 21b is 0.05 to 0.7 μm, and the volume Vvv6 of the protruding valley space of the reference plane 21b is 0.01 to 0.1 ml / m 2 It is even more preferable that one or both of the following conditions are met.

[0048] The arithmetic mean roughness Ra1 of the side walls 28a and 28b, the arithmetic mean roughness Ra2 of the upper surface 27 of the outer periphery 20b, the arithmetic mean roughness Ra3 of the upper end surfaces 21a of the multiple protrusions 22, the arithmetic mean roughness Ra4 of the surface of the chamfered portion 29, the arithmetic mean roughness Ra5 of the upper end surface 21c of the seal band 25, and the arithmetic mean roughness Ra6 of the reference surface 21b are each measured in accordance with JIS B0601:2013. Surface roughness measurements are performed at three locations for each measurement point, and the average value is taken as the measured value.

[0049] The arithmetic mean heights Sa1 of the side walls 28a and 28b, Sa2 of the upper surface 27 of the outer periphery 20b, Sa3 of the upper end surfaces 21a of the multiple protrusions 22, Sa4 of the chamfered surface 29, Sa5 of the upper end surface 21c of the seal band 25, and Sa6 of the reference surface 21b are each measured in accordance with ISO 25178 and can be measured using, for example, a non-contact roughness meter of model VK-X3100 manufactured by Keyence Corporation. Surface roughness measurements are performed at three locations for each measurement point, and the average value is taken as the measured value. Furthermore, the standard deviations of the above-mentioned arithmetic mean heights Sa1, Sa2, Sa3, Sa4, Sa5, and Sa6 are calculated based on measurement results taken at four locations without bias.

[0050] The volume of the protruding valley space Vvv1 on the surface of the side walls 28a and 28b, the volume of the protruding valley space Vvv2 on the upper surface 27 of the outer periphery 20b, the volume of the protruding valley space Vvv3 on the upper end surface 21a of the multiple protrusions 22, the volume of the protruding valley space Vvv4 on the surface of the chamfered portion 29, the volume of the protruding valley space Vvv5 on the upper end surface 21c of the seal band 25, and the volume of the protruding valley space Vvv6 on the reference surface 21b are each measured in accordance with ISO 25178 and can be measured, for example, with a non-contact roughness meter of model VK-X3100 manufactured by Keyence Corporation. Surface roughness measurements are performed at three locations for each measurement point, and the average value is taken as the measured value. Furthermore, the standard deviations of the above-mentioned protruding valley space volumes Vvv1, Vvv2, Vvv3, Vvv4, Vvv5, and Vvv6 are calculated based on measurement results performed at four locations without bias.

[0051] The ceramic substrate 20, including the protrusions 22 and the sealing band 25, can be formed from a ceramic material such as alumina or aluminum nitride. In a preferred embodiment, the ceramic substrate 20 contains one or two selected from alumina and aluminum nitride. In a more preferred embodiment, the ceramic substrate 20 contains 80% by mass or more of one or two selected from alumina and aluminum nitride. In an even more preferred embodiment, the ceramic substrate 20 contains 95% by mass or more of one or two selected from alumina and aluminum nitride.

[0052] Electrode 26 is a planar electrode used as an electrostatic electrode and is connected to an external DC power supply via a power supply member (not shown). Electrode 26 is formed from a material containing, for example, W, Mo, WC, MoC, etc. A low-pass filter may be placed in the middle of the power supply member. The power supply member is electrically insulated from the bonding layer 40 and the base plate 30. When a DC voltage is applied to electrode 26, the wafer W is attracted and fixed to the wafer mounting surface, specifically the upper end surface 21c of the seal band 25 and the upper end surface 21a of the projection 22, by electrostatic attraction force. When the DC voltage is removed, the attraction and fixation of the wafer W to the wafer mounting surface are released.

[0053] The electrode 26 may incorporate a heater electrode (resistive heating element) in place of or in addition to the electrostatic adsorption electrode, or it may incorporate an RF electrode for plasma generation. In this case, a heater power supply is connected to the heater electrode, and an RF power supply is connected to the RF electrode. The ceramic substrate 20 may have one layer of electrode 26, or it may have two or more layers spaced apart.

[0054] The base plate 30 can be, for example, disc-shaped. The base plate 30 may have an annular flange on its lower side used to clamp the semiconductor manufacturing equipment component 10 to a jig inside the chamber. The thickness of the base plate 30 can be 10 to 30 mm, typically 15 to 30 mm. The base plate 30 can be connected to a radio frequency (RF) power supply and used as an RF electrode.

[0055] The base plate 30 can be a disc with good electrical and thermal conductivity (a disc with the same diameter as or larger than the ceramic substrate 20). A refrigerant channel 32 through which the refrigerant circulates may be formed inside the base plate 30. The refrigerant flowing through the refrigerant channel 32 is preferably a liquid and preferably electrically insulating. Examples of electrically insulating liquids include fluorine-based inert liquids. The refrigerant channel 32 can be formed, for example, in a single continuous line from one end (inlet) to the other end (outlet) across the entire base plate 30 in a plan view. A supply port and a recovery port of an external refrigerant device (not shown) are connected to one end and the other end of the refrigerant channel 32, respectively. The refrigerant supplied from the supply port of the external refrigerant device to one end of the refrigerant channel 32 passes through the refrigerant channel 32, returns to the recovery port of the external refrigerant device from the other end of the refrigerant channel 32, is temperature-adjusted, and then supplied again from the supply port to one end of the refrigerant channel 32.

[0056] The base plate 30 can be made of, for example, a metallic material or a composite material of metal and ceramics. Examples of metallic materials include Al, Ti, Mo, or alloys thereof. Examples of composite materials of metal and ceramics include metal matrix composites (MMC) and ceramic matrix composites (CMC). Specific examples of such composite materials include materials containing Si, SiC, and Ti (also called SiSiCTi), materials in which Al and / or Si are impregnated into a porous SiC body, and composite materials of Al2O3 and TiC. A material in which Al is impregnated into a porous SiC body is called AlSiC, and a material in which Si is impregnated into a porous SiC body is called SiSiC. It is preferable to select a material for the base plate 30 that has a thermal expansion coefficient close to that of the ceramic substrate 20. For example, if the ceramic substrate 20 is made of alumina, it is preferable that the base plate 30 be made of SiSiCTi or AlSiC, which have a thermal expansion coefficient close to that of alumina.

[0057] As shown in Figures 1-1 and 2-1, the upper surface 31 of the base plate 30 is bonded to the lower surface 23 of the ceramic substrate 20 via a bonding layer 40. The bonding layer 40 bonds the lower surface 23 of the ceramic substrate 20 to the upper surface 31 of the base plate 30. The bonding layer 40 may be composed of a metal layer formed from, for example, solder or metal brazing material. The bonding layer 40 is formed, for example, by TCB (Thermal Compression Bonding). TCB is a known method in which a metal bonding material is sandwiched between two members to be bonded, and the two members are pressed together while heated to a temperature below the solidus temperature of the metal bonding material. The bonding layer 40 is not limited to a metal layer. For example, a resin bonding layer may be used instead of a metal layer. The resin bonding layer can be composed of, for example, a cured product of a silicone resin adhesive, epoxy resin adhesive, acrylic resin adhesive, or urethane resin adhesive.

[0058] At least a portion of the side walls 28a and 28b of the ceramic substrate 20, the outer periphery of the bonding layer 40, the chamfered portion 29, and the side surface of the base plate 30 can be covered with a coating layer 60. Examples of coating layers 60 include thermal spray films such as alumina and yttria, aerosol deposition films, and ion-assisted deposition films. From the viewpoint of preventing plasma corrosion and reducing particle generation, the porosity of the coating layer 60 is preferably 2% or less, more preferably 1% or less, and even more preferably 0.5% or less. Among the coating layers 60, it is preferable to use ion-assisted deposition from the viewpoint that it is possible to produce a dense film with low porosity. By covering at least a portion of the side walls 28a and 28b of the ceramic substrate 20, the outer periphery of the bonding layer 40, the chamfered portion 29, and the side surface of the base plate 30 with such a dense film, corrosion of these areas by plasma can be suppressed and particle generation can be reduced. Furthermore, it is preferable that the coating layer is an insulating film.

[0059] In the first and second embodiments, the semiconductor manufacturing equipment member 10 may have a plurality of holes that penetrate the semiconductor manufacturing equipment member 10 in the vertical direction. Such holes include a plurality of gas holes 50 that open to the upper surface 21 and lift pin holes for inserting lift pins to move the wafer W up and down on the upper surface 21. Multiple gas holes 50 can be provided at appropriate positions when the upper surface 21 is viewed from above (see Figures 1-3 and 2-3). A heat-conducting gas such as He gas is supplied to the gas holes 50. Typically, the gas holes 50 can be provided to open to a portion of the upper surface 21 where the seal band 25 and the plurality of protrusions 22 are not provided (reference surface 21b). When heat-conducting gas is supplied to the gas holes 50, the space on the back side of the wafer W placed on the upper surface 21 is filled with heat-conducting gas. A plug 55 having a gas flow path may be embedded in the gas holes 50. Multiple lift pin holes can be provided at equal intervals along concentric circles on the upper surface 21 when the upper surface 21 is viewed from above.

[0060] <2. Method of using components for semiconductor manufacturing equipment> Next, a representative example of how to use the semiconductor manufacturing equipment component 10 will be described. First, with the semiconductor manufacturing equipment component 10 installed in a chamber (not shown), the wafer W is placed on the upper surface 21 of the ceramic substrate 20. Then, the pressure inside the chamber is reduced using a vacuum pump to adjust to a predetermined vacuum level, and a voltage is applied to the electrodes 26 of the ceramic substrate 20 to generate electrostatic adsorption force, thereby adsorbing and fixing the wafer W to the wafer mounting surface (specifically, the upper end surface 21c of the seal band 25 and the upper end surface 21a of the projection 22).

[0061] Next, the chamber is transformed into a reaction gas atmosphere at a predetermined pressure (e.g., several tens to several hundred Pas). In this state, a high-frequency voltage such as an RF voltage is applied between an upper electrode (not shown) located on the ceiling of the chamber and the base plate 30 of the semiconductor manufacturing equipment component 10 to generate plasma. The surface of the wafer W is then treated with the generated plasma.

[0062] <3. Examples of manufacturing components for semiconductor manufacturing equipment> Next, an example of the manufacturing of the semiconductor manufacturing equipment component 10 will be illustrated using Figure 4. Here, an example of the manufacturing of the semiconductor manufacturing equipment component 10 according to the second embodiment shown in Figure 2-1 will be described. First, a disc-shaped ceramic sintered body 120, which will be the basis for the ceramic substrate 20, is manufactured by hot-press firing a molded body of ceramic powder (Figure 4A). The molded body may be manufactured by stacking multiple tape molded bodies, by mold casting, or by compressing ceramic powder. The ceramic sintered body 120 contains electrodes 26.

[0063] Next, after polishing the upper surface of the ceramic sintered body 120, multiple protrusions 22 and sealing bands 25 are provided by blasting or laser processing (Figure 4B). This makes it possible to smooth the upper end surfaces 21a of the multiple protrusions 22. As for the polishing method, lapping is one option, but it is preferable to perform polishing in addition to lapping. Diamond slurry can be used for lapping, and colloidal silica can be used for polishing. Furthermore, multiple protrusions 22 and sealing bands 25 are formed on the upper surface of the ceramic sintered plate by laser processing or the like. The timing of forming the multiple protrusions 22 and sealing bands 25 may be after the bonding of the ceramic substrate 20 and the base plate 30.

[0064] In parallel with this, two MMC disc members 131 and 136 are manufactured (Figure 4C). Then, a groove 132, which will ultimately become the refrigerant flow path 32, is formed on the lower surface of the upper MMC disc member 131 by machining (Figure 4D). A through hole 133 for refrigerant introduction and a through hole 134 for refrigerant discharge are made in the lower MMC disc member 136. If the ceramic sintered body 120 is made of alumina, it is preferable that the MMC disc members 131 and 136 are made of SiSiCTi or AlSiC. This is because the thermal expansion coefficient of alumina is approximately the same as that of SiSiCTi or AlSiC.

[0065] A disc-shaped member made of SiSiCTi can be manufactured, for example, as follows: First, a powder mixture is prepared by mixing silicon carbide, metallic Si, and metallic Ti. Next, a disc-shaped molded body is formed from the obtained powder mixture by uniaxial pressure molding, and this molded body is hot-press sintered in an inert atmosphere to obtain a disc-shaped member made of SiSiCTi.

[0066] Next, a metal bonding material 135 is placed between the lower surface of the upper MMC disc member 131 and the upper surface of the lower MMC disc member 136, and a metal bonding material 137 is placed on the upper surface of the upper MMC disc member 131. Then, the ceramic sintered body 120 is placed on top of the metal bonding material 137 placed on the upper surface of the upper MMC disc member 131. This results in a laminate 110 in which the lower MMC disc member 136 and metal bonding material 135, the upper MMC disc member 131 and metal bonding material 137, and the ceramic sintered body 120 are stacked in this order from bottom to top (Figure 4E). By heating and pressurizing this laminate 110 (TCB), a bonded body is obtained. The bonded body is formed by bonding the ceramic sintered body 120 to the upper surface of the MMC block 130, which will become the base plate 30, via a metal bonding layer. The MMC block 130 is formed by joining an upper MMC disc member 131 and a lower MMC disc member 136 via a metal bonding layer. The MMC block 130 has a refrigerant flow path 32, a refrigerant introduction section 36, and a refrigerant discharge section 38.

[0067] TCB (Temperature-Correcting Bonding) is performed, for example, as follows: The laminate is pressed and bonded at a temperature below the solidus temperature of the metal bonding material (for example, between 20°C below the solidus temperature and the solidus temperature), and then returned to room temperature. This causes the metal bonding material to become a metal bonding layer. As the metal bonding material, Al-Mg-based bonding materials or Al-Si-Mg-based bonding materials can be used. For example, when performing TCB using an Al-Si-Mg-based bonding material, the laminate is pressed while heated in a vacuum atmosphere. It is preferable to use a metal bonding material with a thickness of around 100 μm.

[0068] The above describes the case in which the base plate 30 is made from MMC and joined to the ceramic sintered body 120 via a metal bonding material 137. Alternatively, the base plate 30 may be made of metal and joined to the ceramic sintered body 120 using a resin adhesive sheet.

[0069] Furthermore, when forming the bonding layer 40 using the metal bonding material 137, the coating layer 60 can be formed by thermal spraying onto the base plate 30 either before or after bonding with the ceramic substrate 20. When forming the bonding layer 40 using a resin adhesive sheet, the resin melts, so the coating layer 60 is formed by thermal spraying before bonding with the ceramic substrate 20.

[0070] Next, the outer circumference of the ceramic sintered body 120 is machined to form a step, thereby creating a ceramic substrate 20 having a central portion 20a and an outer peripheral portion 20b. Then, the surface of the side wall 28b of the central portion 20a, preferably the surface of the side wall 28b of the central portion 20a and the surface of the chamfered portion 29 are smoothed. As a method of smoothing, polishing by a machining center using fine grinding wheels or wet blasting can be employed. This yields a semiconductor manufacturing equipment component 10 (Figure 4F).

[0071] Although the base plate 30 in Figure 1-1 is shown as a single piece, it may also be a structure in which two members are joined by a metal bonding layer, as shown in Figure 4F, or a structure in which three or more members are joined by a metal bonding layer. [Examples]

[0072] (1-1. Manufacturing of ceramic substrates) A disc-shaped (300 mm in diameter x 4 mm thick) ceramic sintered body was fabricated by hot-press firing of alumina powder molded bodies. Next, the top surface and side walls of the ceramic sintered body were shaped by machining such as grinding and polishing, and then chamfered edges were created at the corners where the side walls and top surface connect by grinding. Subsequently, the surface of the side walls and the chamfered edges of the ceramic sintered body were smoothed. The smoothing process can be performed by grinding with a grinding wheel, wet blasting or dry blasting, or brushing with a diamond slurry. Alternatively, these methods can be combined and the grit size of the grinding wheel is increased in stages. Here, too, a staged smoothing process was performed, and the grit size of the grinding wheel was changed so that the arithmetic mean roughness Ra of the side wall surface of the ceramic substrate was the value shown in Table 1 according to the test number. The arithmetic mean roughness Ra was measured according to JIS B0601:2013 as described above. The arithmetic mean roughness Ra of the chamfered area was not measured, but it is estimated to be similar to that of the sidewall surface, given that the smoothing treatment conditions were the same. After the smoothing treatment, the processed surface was cleaned with an organic solvent and pure water.

[0073] (1-2. Evaluation of particle suppression effect) Particles are often caused by processing residues and fragmented layers (microcracks) of ceramics remaining on the surface of the sidewalls and chamfered areas of ceramic substrates. Such processing residues and fragmented layers (microcracks) tend to adhere to adhesive tape. Therefore, the particle suppression effect can be easily evaluated by applying and removing adhesive tape, without actually placing the ceramic substrate under the influence of plasma. Here, cellophane tape was applied to the surface of the sidewall under the following conditions and then removed. <Conditions for applying and removing cellophane tape> Cellophane tape type: Cellotape (registered trademark) No. 405, manufactured by Nichiban Co., Ltd. Adhesion area of ​​cellophane tape against the side wall: 100 mm² 2 Pressure applied when attaching cellophane tape to the side wall: 98066 Pa Speed ​​when peeling cellophane tape from the side wall: 1 mm / s Angle when peeling cellophane tape from the side wall: 30°

[0074] The likelihood of particle generation was evaluated by the number of Al2O3 particles adhering to the cellophane tape during peeling. To evaluate the number of Al2O3 particles, the adhesive surface of the cellophane tape was magnified 100 times using SEM, and then the white areas were treated as Al2O3 particles through binarization. The number of Al2O3 particles with an equivalent circle diameter of 1 μm or more was counted. The results are shown in Table 1. It can be seen that the number of adhering Al2O3 particles decreases significantly when the Ra value is 0.4 μm or less.

[0075] [Table 1]

[0076] (2-1. Manufacturing of ceramic substrates) A disc-shaped (300 mm in diameter x 4 mm thick) ceramic sintered body was fabricated by hot-press firing of alumina powder molded bodies. Next, the top surface and side walls of the ceramic sintered body were shaped by machining such as grinding and polishing, and then chamfered edges were created at the corners where the side walls and top surface connect by grinding. Subsequently, the surface of the side walls and the chamfered edges of the ceramic sintered body were smoothed. The smoothing process can be performed by grinding with a grinding wheel, wet blasting or dry blasting, or brushing with a diamond slurry. Alternatively, these methods can be combined and the grit size of the grinding wheel is increased in stages. Here, too, a staged smoothing process was performed, and the grit size of the grinding wheel was changed so that the arithmetic mean roughness Ra of the ceramic substrate side wall surface, the arithmetic mean height Sa of the ceramic substrate side wall surface, and the volume of the protruding valley space Vvv of the side wall surface were the values ​​shown in Table 2 according to the test number. As previously mentioned, the arithmetic mean roughness Ra was measured in accordance with JIS B0601:2013. As previously mentioned, the arithmetic mean height Sa and the volume of protruding valleys Vvv were measured in accordance with ISO 25178 using a non-contact roughness meter of model VK-X3100 manufactured by Keyence Corporation. The arithmetic mean roughness Ra, arithmetic mean height Sa, and volume of protruding valleys Vvv of the chamfered section were not measured, but since the smoothing treatment conditions were the same, it is presumed to be similar to that of the sidewall surface. After the smoothing treatment, the processed surface was cleaned with an organic solvent and pure water.

[0077] (2-2. Evaluation of particle suppression effect) Particles are often caused by processing residues and fragmented layers (microcracks) of ceramics remaining on the surface of the sidewalls and chamfered areas of ceramic substrates. Such processing residues and fragmented layers (microcracks) tend to adhere to adhesive tape. Therefore, the particle suppression effect can be easily evaluated by applying and removing adhesive tape, without actually placing the ceramic substrate under the influence of plasma. Here, cellophane tape was applied to the surface of the sidewall under the following conditions and then removed. <Conditions for applying and removing cellophane tape> Cellophane tape type: Cellotape (registered trademark) No. 405, manufactured by Nichiban Co., Ltd. Adhesion area of ​​cellophane tape against the side wall: 100 mm² 2 Pressure applied when attaching cellophane tape to the side wall: 98066 Pa Speed ​​when peeling cellophane tape from the side wall: 1 mm / s Angle when peeling cellophane tape from the side wall: 30°

[0078] The likelihood of particle generation was evaluated by the number of Al2O3 particles adhering to the cellophane tape during peeling. To evaluate the number of Al2O3 particles, the adhesive surface of the cellophane tape was magnified 100 times using SEM, and then the white areas were treated as Al2O3 particles using binarization. The number of Al2O3 particles with an equivalent circle diameter of 1 μm or more was counted. The results are shown in Table 2. A smaller Ra value tends to reduce the number of attached Al2O3 particles, but even with the same Ra value, the number of attached Al2O3 particles changed significantly when Sa, Vvv, and their standard deviations were varied.

[0079] [Table 2]

[0080] (3-1. Manufacturing of ceramic substrates) A disc-shaped (300 mm in diameter x 4 mm thick) ceramic sintered body was fabricated by hot-press firing of a molded alumina powder. Next, the top surface and side walls of the ceramic sintered body were shaped by mechanical processes such as grinding and polishing, and then chamfered edges were created at the corners where the side walls and top surface connect by grinding. Subsequently, the surface of the side walls and the chamfered edges of the ceramic sintered body were smoothed. The smoothing process can be performed by grinding with a grinding wheel, wet blasting or dry blasting, or brushing with a diamond slurry. Alternatively, these methods can be combined and the grit size of the grinding wheel is increased in stages. Here, too, a staged smoothing process was performed, and the grit size of the grinding wheel was changed so that the arithmetic mean height Sa1 of the side wall surface and the arithmetic mean height Sa4 of the chamfered edge surface of the ceramic substrate were the values ​​listed in Table 3 according to the test number. As previously mentioned, the arithmetic mean height Sa was measured using a non-contact roughness meter, model VK-X3100, manufactured by Keyence Corporation, in accordance with ISO 25178. After the smoothing treatment, the processed surface was cleaned with an organic solvent and pure water.

[0081] (3-2. Evaluation of particle suppression effect) Particles are often caused by processing residues and fragmented layers (microcracks) of ceramics remaining on the surface of the sidewalls and chamfered areas of ceramic substrates. Such processing residues and fragmented layers (microcracks) tend to adhere to adhesive tape. Therefore, the particle suppression effect can be easily evaluated by applying and removing adhesive tape, without actually placing the ceramic substrate under the influence of plasma. Here, cellophane tape was applied to the surface of the sidewall under the following conditions and then removed. <Conditions for applying and removing cellophane tape> Cellophane tape type: Cellotape (registered trademark) No. 405, manufactured by Nichiban Co., Ltd. Adhesion area of ​​cellophane tape against the side wall: 100 mm² 2 Pressure applied when attaching cellophane tape to the side wall: 98066 Pa Speed ​​when peeling cellophane tape from the side wall: 1 mm / s Angle when peeling cellophane tape from the side wall: 30°

[0082] The likelihood of particle generation was evaluated by the number of Al2O3 particles adhering to the cellophane tape during peeling. To evaluate the number of Al2O3 particles, the adhesive surface of the cellophane tape was magnified 100 times using SEM, and then the white areas were treated as Al2O3 particles by binarization. The number of Al2O3 particles with an equivalent circle diameter of 1 μm or more was counted. The results are shown in Table 3. It can be seen that the number of adhering Al2O3 particles decreases significantly when Sa1 is 1.1 μm or less. It can also be seen that even with the same Sa1, a smaller standard deviation results in a smaller number of adhering Al2O3 particles. Furthermore, it can be seen that a smoother chamfered edge is preferable. This is because a smoother chamfered edge results in fewer Al2O3 particles remaining on the chamfered edge, and even if Al2O3 particles fall from the chamfered edge, they are less likely to adhere to the sidewall.

[0083] [Table 3] [Explanation of Symbols]

[0084] 10: Components for semiconductor manufacturing equipment 20: Ceramic substrate 20a: Central part 20b: Outer periphery 21:Top surface 21a: Upper end surface 21b: Reference plane 21c: Upper end surface 22: Protrusion 23: Bottom surface 25: Seal Band 26: Electrode 27:Top surface 28a: Side wall 28b: Side wall 29: Chamfered section 30: Base plate 31:Top surface 32: Refrigerant flow path 36: Refrigerant inlet 38: Refrigerant discharge part 40: Bonding layer 50: Gas hole 55: Plug 60:Coating layer 110: Laminate 120: Ceramic sintered body 130: MMC Block 131: Disc member 132: Groove 133: Through hole 134: Through hole 135: Metal bonding material 136: Disc member 137:Metal bonding material W: wafer FR: Focus Ring

Claims

1. A ceramic substrate having a top surface with a plurality of protrusions for placing a wafer, and a side wall forming the outer edge of the top surface, wherein the arithmetic mean roughness Ra of the surface of the side wall 1 A component for semiconductor manufacturing equipment comprising a ceramic substrate having a thickness of 0.4 μm or less and a patterned uneven surface on the side wall.

2. The semiconductor manufacturing apparatus component according to claim 1, wherein the patterned uneven shape is formed by laser processing.

3. The semiconductor manufacturing apparatus member according to claim 1, wherein the surface of the side wall has one or more of the following patterned uneven shapes: i) A pattern composed of multiple striated protrusions ii) Pattern composed of multiple point-like protrusions iii) Pattern composed of multiple dimples iv) A pattern composed of a network of intersecting linear protrusions.

4. The upper surface and the side wall are connected via a chamfered portion, and the arithmetic mean roughness Ra of the surface of the chamfered portion 4 The semiconductor manufacturing apparatus component according to claim 1, wherein the diameter is 0.4 μm or less.

5. The arithmetic mean height Sa of the surface of the side wall 1 The diameter is 1.1 μm or less, and the volume of the protruding valley space on the surface of the side wall is Vvv 1 0.5 ml / m 2 A semiconductor manufacturing apparatus component according to claim 1, satisfying one or both of the following conditions.

6. The arithmetic mean height Sa of the surface of the chamfered portion 4 The diameter is 1.1 μm or less, and the volume of the protruding valley space on the surface of the chamfered portion is Vvv 4 0.5 ml / m 2 A semiconductor manufacturing apparatus component according to claim 4, satisfying one or both of the following conditions.

7. The arithmetic mean height Sa of the surface of the side wall 1 has a standard deviation of 0.1 μm or less, and the protruding valley space volume Vvv of the surface of the side wall 1 has a standard deviation of 0.1 ml / m 2 or less, and the member for a semiconductor manufacturing apparatus according to claim 5 satisfying one or both of these conditions

8. The arithmetic mean height Sa of the surface of the chamfered portion 4 The standard deviation of is 0.1 μm or less, and the volume of the protruding valley space on the surface of the chamfered portion is Vvv 4 The standard deviation is 0.1 ml / m 2 A semiconductor manufacturing apparatus component according to claim 6, satisfying one or both of the following conditions.

9. The arithmetic mean roughness Ra of the surface of the side wall 1 The semiconductor manufacturing apparatus component according to claim 1, wherein the value measured in the circumferential direction of the ceramic substrate is smaller than the value measured in the thickness direction of the ceramic substrate.

10. The semiconductor manufacturing apparatus component according to claim 1, wherein at least a portion of the side wall is covered by a coating layer, and the porosity of the coating layer is 2% or less.

11. The central upper surface has multiple protrusions for placing wafers, The outer peripheral upper surface of the central upper surface, which is located at a lower position than the central upper surface, The central side wall that constitutes the step between the upper surface of the central part and the upper surface of the outer periphery, A ceramic substrate having, The arithmetic mean roughness Ra of the surface of the central side wall 1 The arithmetic mean roughness Ra of the upper surface of the outer periphery 2 A component for semiconductor manufacturing equipment, comprising a ceramic substrate that is smaller than the above and larger than the arithmetic mean roughness Ra3 of the upper end surface of the plurality of protrusions.

12. The arithmetic mean roughness Ra of the surface of the central side wall 1 The semiconductor manufacturing apparatus component according to claim 11, wherein the thickness is 0.4 μm or less.

13. The semiconductor manufacturing apparatus component according to claim 11, wherein the upper surface of the central portion and the side wall of the central portion are connected via a chamfered portion.

14. The arithmetic mean roughness Ra of the surface of the chamfered portion 4 The arithmetic mean roughness Ra of the upper surface of the outer periphery 2 A component for semiconductor manufacturing equipment according to claim 13, which is smaller than the component described in claim 13.

15. The arithmetic mean roughness Ra of the surface of the chamfered portion 4 The semiconductor manufacturing apparatus component according to claim 13, wherein the diameter is 0.4 μm or less.

16. The arithmetic mean roughness Ra of the surface of the chamfered portion 4 and the arithmetic mean roughness Ra of the surface of the central side wall 1 The semiconductor manufacturing apparatus component according to claim 13, wherein the absolute value of the difference is 0.4 μm or less.

17. A central upper surface having a plurality of protrusions for placing a wafer, The outer peripheral upper surface of the central upper surface, which is located at a lower position than the central upper surface, The central side wall that constitutes the step between the upper surface of the central part and the upper surface of the outer periphery, A ceramic substrate having, The arithmetic mean roughness Ra 1 of the surface of the central side wall is smaller than the arithmetic mean roughness Ra 2 of the upper surface of the outer periphery. The upper surface of the central portion and the side wall of the central portion are connected via a chamfered portion. A component for semiconductor manufacturing equipment comprising a ceramic substrate in which the arithmetic mean roughness Ra 4 of the surface of the chamfered portion is greater than the arithmetic mean roughness Ra 3 of the upper end surfaces of the plurality of protrusions.

18. A central upper surface having a plurality of protrusions for placing a wafer, The outer peripheral upper surface of the central upper surface, which is located at a lower position than the central upper surface, The central side wall that constitutes the step between the upper surface of the central part and the upper surface of the outer periphery, A ceramic substrate having, The arithmetic mean roughness Ra 1 of the surface of the central side wall is smaller than the arithmetic mean roughness Ra 2 of the upper surface of the outer periphery. A component for semiconductor manufacturing equipment, comprising a ceramic substrate having a patterned, uneven surface on the central side wall.

19. The semiconductor manufacturing apparatus component according to claim 18, wherein the patterned uneven shape is formed by laser processing.

20. The semiconductor manufacturing apparatus member according to claim 18, wherein the surface of the central side wall has one or more patterned uneven shapes from i) to iii) below: i) A pattern composed of multiple point-like protrusions ii) Patterns composed of multiple dimples iii) A pattern composed of a network of intersecting linear protrusions.

21. The arithmetic mean roughness Ra of the surface of the central side wall 1 A semiconductor manufacturing apparatus component according to any one of claims 18 to 20, wherein the thickness is 0.4 μm or less.

22. The semiconductor manufacturing apparatus component according to claim 11, wherein at least a portion of the central side wall is covered by a coating layer, and the porosity of the coating layer is 2% or less.

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