Semiconductor memory device

Abstract

A semiconductor memory device includes: a conductive pad on an information storage structure; a channel structure on the conductive pad, including a vertical portion extending in a first direction; word lines extending in a second direction and on a plurality of side surfaces of the vertical portion; and bit lines on the channel structure and extending upward in a third direction intersecting the second direction.

Description

Technical Field

[0001] This disclosure relates to semiconductor memory devices. Background Technology

[0002] Semiconductor devices can be core components in electronic devices used to control or amplify electrical signals, and various types of semiconductor devices can be manufactured. For example, memory devices are used to store and retrieve data, while non-memory devices are used to control or amplify electrical signals. Semiconductor devices play an important role in various fields, including computers, communication equipment, and consumer electronics.

[0003] As technology advances, the performance and functional requirements of electronic devices are increasing. Consequently, the demand for high-performance semiconductor devices is rising, and their integration density is increasing to meet these needs. Therefore, transistors with vertical channels have been proposed to improve the integration density of semiconductor devices. Summary of the Invention

[0004] This disclosure provides a semiconductor memory device with improved electrical characteristics and reliability.

[0005] According to some embodiments of this disclosure, the area of ​​the word lines on the channel structure can be increased by arranging the word lines as multiple side surfaces surrounding a vertical portion of the channel structure. Therefore, the electrical characteristics and reliability of the semiconductor memory device can be improved.

[0006] According to some embodiments of the present disclosure, a semiconductor memory device may include: a conductive pad on an information storage structure; a channel structure on the conductive pad and including a vertical portion extending in a first direction; word lines extending in a second direction and on a plurality of side surfaces of the vertical portion, wherein the second direction is substantially perpendicular to the first direction; and bit lines on the channel structure and extending upward in a third direction intersecting the second direction, wherein the third direction is substantially perpendicular to the first direction.

[0007] According to some embodiments of this disclosure, a semiconductor memory device may include: a first conductive pad and a second conductive pad, respectively, on an information storage structure; a first channel structure, on the first conductive pad, and extending in a first direction; a second channel structure, on the second conductive pad, and extending in the first direction; a first word line, extending in a second direction, and on one side of the first channel structure, wherein the second direction is substantially perpendicular to the first direction; a second word line, extending in the second direction, spaced apart from the first word line in a third direction intersecting the first direction and substantially perpendicular to the first direction, and on one side of the second channel structure; a molded pattern, between the first word line and the second word line; a liner insulating film, between the first word line and the first channel structure, and between the second word line and the second channel structure; and a bit line, extending in a third direction, and on the surface of the first channel structure opposite to the first conductive pad and the surface of the second channel structure opposite to the second conductive pad, wherein the first word line is adjacent to at least a portion of the side surface of the first channel structure, and the second word line is adjacent to at least a portion of the side surface of the second channel structure.

[0008] According to some embodiments of this disclosure, a semiconductor memory device may include: a first conductive pad and a second conductive pad on respective information storage structures; a lower insulating film on the first conductive pad and the second conductive pad; a first channel structure including a first horizontal portion and a first vertical portion, the first horizontal portion being on the first conductive pad and extending in a first direction, and the first vertical portion extending in a second direction on the first horizontal portion, wherein the second direction is substantially perpendicular to the first direction; a second channel structure including a second horizontal portion and a second vertical portion, the second horizontal portion being disposed on the second conductive pad and extending in the first direction, and the second vertical portion extending in a second direction on the second horizontal portion; and a first word line intersecting the first direction. The first letter extends in three directions and is on one side of the first vertical portion; the second letter extends in a third direction and is on one side of the second vertical portion; a molded pattern is between the first letter and the second letter; a lining insulating film is between the first letter and the first channel structure, and between the second letter and the second channel structure; and a bit line extends in a first direction and is on the surface of the first channel structure opposite to the first conductive pad and the surface of the second channel structure opposite to the second conductive pad, wherein the first letter is on the first side surface, the second side surface and the third side surface of the first vertical portion, and the first side surface and the third side surface of the first vertical portion are opposite to each other in a third direction and are each connected to the second side surface. Attached Figure Description

[0009] The above and other embodiments and features of this disclosure will become clearer by referring to the accompanying drawings and describing in detail the exemplary embodiments of this disclosure.

[0010] Figure 1 This is a plan view illustrating a semiconductor memory device according to some embodiments.

[0011] Figure 2 It is shown Figure 1 A magnified view of region Q1.

[0012] Figure 3 It is along Figure 1 The sectional view taken by line AA.

[0013] Figure 4 It is along Figure 1 The sectional view taken by line BB.

[0014] Figure 5 It is along Figure 1 The sectional view taken by the CC line.

[0015] Figure 6 This is a diagram illustrating a semiconductor memory device according to some embodiments.

[0016] Figure 7 This is a diagram illustrating a semiconductor memory device according to some embodiments.

[0017] Figure 8 This is a diagram illustrating a semiconductor memory device according to some embodiments.

[0018] Figure 9 This is a diagram illustrating a semiconductor memory device according to some embodiments.

[0019] Figure 10 This is a diagram illustrating a semiconductor memory device according to some embodiments.

[0020] Figure 11 This is a plan view illustrating a method for manufacturing a semiconductor memory device according to some embodiments.

[0021] Figure 12 It is along Figure 11 The sectional view taken by line AA.

[0022] Figure 13 This is a plan view illustrating a method for manufacturing a semiconductor memory device according to some embodiments.

[0023] Figure 14 It is along Figure 13 The sectional view taken by line AA.

[0024] Figure 15 This is a plan view illustrating a method for manufacturing a semiconductor memory device according to some embodiments.

[0025] Figure 16 and Figure 17 It is along Figure 15 A cross-sectional view taken from lines AA and BB.

[0026] Figure 18 This is a plan view illustrating a method for manufacturing a semiconductor memory device according to some embodiments.

[0027] Figure 19 and Figure 20 It is along Figure 18 A cross-sectional view taken from lines AA and BB.

[0028] Figure 21 This is a plan view illustrating a method for manufacturing a semiconductor memory device according to some embodiments.

[0029] Figure 22 and Figure 23 It is along Figure 21 A cross-sectional view taken from lines AA and BB.

[0030] Figure 24 This is a plan view illustrating a method for manufacturing a semiconductor memory device according to some embodiments.

[0031] Figure 25 and Figure 26 It is along Figure 24 A cross-sectional view taken from lines AA and BB.

[0032] Figure 27 This is a plan view illustrating a method for manufacturing a semiconductor memory device according to some embodiments.

[0033] Figure 28 and Figure 29 It is along Figure 27 A cross-sectional view taken from lines AA and BB.

[0034] Figure 30 This is a plan view illustrating a method for manufacturing a semiconductor memory device according to some embodiments.

[0035] Figure 31 and Figure 32 It is along Figure 30 A cross-sectional view taken from lines AA and BB.

[0036] Figure 33 This is a plan view illustrating a method for manufacturing a semiconductor memory device according to some embodiments.

[0037] Figure 34 and Figure 35 It is along Figure 33 A cross-sectional view taken from lines AA and BB.

[0038] Figure 36 and Figure 37 This is a diagram illustrating a method for manufacturing a semiconductor memory device according to some embodiments.

[0039] Figure 38 This is a plan view illustrating a method for manufacturing a semiconductor memory device according to some embodiments.

[0040] Figure 39 It is along Figure 38 The sectional view taken from line BB in the middle.

[0041] Figure 40 and Figure 41 This is a diagram illustrating a method for manufacturing a semiconductor memory device according to some embodiments. Detailed Implementation

[0042] In the following, a semiconductor memory device and a method for manufacturing a semiconductor memory device according to some embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0043] The terms “first,” “second,” etc., may be used herein only to distinguish one component, layer, orientation, etc., from another component, layer, orientation, etc. The terms “comprising” and / or “including,” when used herein, specify the presence of the stated elements, but do not exclude the presence of additional elements. The term “and / or” includes any and all combinations of one or more of the associated listed items. The term “connected” may be used herein to refer to a physical and / or electrical connection. When a component or layer is referred to herein as “directly on,” “directly in contact with,” or “directly connected,” there are no intermediate components or layers. Similarly, when components are “closely adjacent” to each other, there may be no intermediate components.

[0044] The terms “around,” “cover,” or “fill,” as may be used herein, do not necessarily refer to completely surrounding, covering, or filling the described element or layer, but may refer, for example, to partially surrounding, covering, or filling the described element or layer, even where gaps, spaces, or other discontinuities are present. The term “exposed” may be used to describe the relationship between elements and / or a particular intermediate process during the manufacture of a completed semiconductor device, but in the context of a completed device, it is not necessary to require the exposure of a particular area, layer, structure, or other element.

[0045] It will be understood that, unless otherwise indicated, spatial relative terms (such as "above," "upper," "upper part," "upper surface," "below," "lower," "lower part," "lower surface," "side surface," etc.) may be indicated by reference numerals and with reference to the accompanying drawings. It will be understood that such spatial relative terms refer to different orientations of the device in use or operation, other than those depicted in the figures. For example, if the device in the figures is flipped, an element described as "below" or "below" other elements or features will be oriented "above" those elements or features. Thus, the term "below" may encompass both the orientations of above and below. The device may be otherwise oriented (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted accordingly.

[0046] Figure 1 This is a plan view illustrating a semiconductor memory device according to some embodiments. Figure 2 It is shown Figure 1 A magnified view of region Q1. Figure 3 It is along Figure 1 The sectional view taken by line AA. Figure 4 It is along Figure 1 The sectional view taken by line BB. Figure 5 It is along Figure 1 A cross-sectional view taken by line CC. For reference, in Figure 1 The diagrams of the information storage structure CAP and the interlayer insulating film 170 are omitted.

[0047] A semiconductor memory device according to some embodiments may include a memory cell comprising a vertical channel transistor (VCT). A vertical channel transistor may refer to a transistor having a channel length extending in a vertical direction.

[0048] Reference Figures 1 to 5 According to some embodiments, a semiconductor memory device may include a first lower insulating film 110, a second lower insulating film 105, a protruding insulating film 107, a conductive pad 120, an information storage structure CAP, a molded pattern 130, a first word line WL1, a second word line WL2, a liner insulating film 140, a first channel structure CH1, a second channel structure CH2, an upper insulating film 150, an isolation liner film 160, an interlayer insulating film 170, and a bit line BL.

[0049] The information storage structure CAP can be configured to be spaced apart from each other in the first direction D1 and the second direction D2. A first lower insulating film 110 can be disposed between the information storage structure CAP and adjacent information storage structures CAP. The information storage structure CAP can be disposed below the conductive pad 120. Although the information storage structure CAP is shown as a single film, the embodiment is not limited thereto. The information storage structure CAP may include, for example, a first electrode, a dielectric film, and a second electrode.

[0050] The information storage structure CAP can be electrically connected to the conductive pad 120. The information storage structure CAP can store signals received from transistors in the peripheral circuitry of the semiconductor memory device (e.g., row decoders, column decoders, and sense amplifiers). The information storage structure CAP can be used as an information storage element electrically connected to the transistor. For example, the information storage structure CAP can store charge under the control of the transistor.

[0051] The first lower insulating film 110 may surround each of the plurality of information storage structures CAP. For example, the first lower insulating film 110 may be disposed between the information storage structures CAP. The first lower insulating film 110 may be superimposed on the information storage structures CAP in a first direction D1 and a second direction D2. When viewed along a line extending in a particular direction or in a plane perpendicular to the particular direction, the components or layers described with reference to "superimposed in a particular direction" may at least partially obscure each other.

[0052] For example, the first lower insulating film 110 may include at least one of silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), and low-k materials. For example, low-k materials may include fluorinated tetraethyl orthosilicate (FTEOS), silsesquioxane (HSQ), bisbenzocyclobutene (BCB), tetramethyl orthosilicate (TMOS), octamethyl cyclotetrasiloxane (OMCTS), hexamethyl disiloxane (HMDS), trimethylsilyl borate (TMSB), diacetoxydi-tert-butylsiloxane (DADBS), trimethylsilyl phosphate (TMSP), polytetrafluoroethylene (PTFE), Tonen SilaZen (TOSZ), fluorinated silicate glass (FSG), nanofoams (such as polyimide or polypropylene oxide), carbon-doped silica (CDO), organosilicon glass (OSG), SiLK, amorphous fluorinated carbon, silica aerogel, silica dry gel, mesoporous silica, or combinations thereof. However, the embodiments are not limited to the above.

[0053] The first direction D1 can be a direction that intersects with the second direction D2. For example, the first direction D1 can be a direction perpendicular to the second direction D2. The third direction D3 can be a direction perpendicular to each of the first direction D1 and the second direction D2. In other words, the first direction D1 and the second direction D2 can be horizontal, and the third direction D3 can be vertical.

[0054] Conductive pads 120 may be disposed on the information storage structure CAP. For example, corresponding conductive pads 120 may be disposed on each of a plurality of information storage structures CAP. The plurality of conductive pads 120 may be spaced apart from each other in a first direction D1 and a second direction D2. In some embodiments, the upper surface of the conductive pad 120 may be disposed on the same plane as the upper surface of the second lower insulating film 105. However, the embodiments are not limited to the above.

[0055] Although the rectangular conductive pad 120 is shown from a planar view, the embodiment is not limited thereto. For example, the conductive pad 120 may have various shapes (such as circular, elliptical, rhomboid, and hexagonal) in the planar view.

[0056] Conductive pad 120 can be made of doped polycrystalline silicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrO x RuO x Or a combination thereof, but the embodiments are not limited thereto.

[0057] The second lower insulating film 105 may surround the conductive pad 120. The second lower insulating film 105 may be stacked with the conductive pad 120 in the first direction D1 and the second direction D2. For example, the second lower insulating film 105 may include any one of silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), and silicon carbonitride oxynitride (SiOCN). However, the embodiments are not limited to the above.

[0058] The plurality of conductive pads 120 may include a first conductive pad 121 and a second conductive pad 122. The first conductive pad 121 may be spaced apart from the second conductive pad 122 in a second direction D2. A first channel structure CH1 may be disposed on the first conductive pad 121. A second channel structure CH2 may be disposed on the second conductive pad 122.

[0059] The protruding insulating film 107 may be disposed on the first conductive pad 121, the second conductive pad 122, and the second lower insulating film 105. The protruding insulating film 107 may be disposed on the portion of the second lower insulating film 105 "located between the first conductive pad 121 and the second conductive pad 122". The protruding insulating film 107 may overlap with a portion of the upper surface of the first conductive pad 121 and a portion of the upper surface of the second conductive pad 122 on a third direction D3.

[0060] The protruding insulating film 107 may extend on the second lower insulating film 105 in the first direction D1. In some embodiments, the width of the protruding insulating film 107 in the second direction D2 may not be constant. For example, the width of the protruding insulating film 107 disposed on the first conductive pad 121 and the second conductive pad 122 in the second direction D2 may be smaller than the width of the protruding insulating film 107 not disposed on the first conductive pad 121 and the second conductive pad 122 in the second direction D2. However, the embodiments are not limited to the above. Unlike the illustration, the width of the protruding insulating film 107 in the second direction D2 may be constant.

[0061] In some embodiments, the boundary surface between the protruding insulating film 107 and the second lower insulating film 105 may not be distinguished. However, the embodiments are not limited to the above. The protruding insulating film 107 may include an insulating material. The protruding insulating film 107 may include, for example, any one of silicon nitride, silicon oxynitride, silicon carbonitride, and silicon carbonitride, but the embodiments are not limited thereto.

[0062] A molded pattern 130 may be disposed on the protruding insulating film 107. The molded pattern 130 may extend along the protruding insulating film 107 in a first direction D1. The molded pattern 130 may be disposed between the first word line WL1 and the second word line WL2, which will be described below. The first word line WL1 and the second word line WL2 may be spaced apart from each other by the molded pattern 130 in a second direction D2.

[0063] In some embodiments, the width of the molded pattern 130 in the second direction D2 may not be constant. The portion of the molded pattern 130 that is "overlapped with the channel structures CH1 and CH2 in the second direction D2" may have a width in the second direction D2 that is smaller than the width of the remaining portion of the molded pattern 130 in the second direction D2.

[0064] For example, such as Figure 2As shown, the molded pattern 130 may include a first recess 130_P1 and a second recess 130_P2. The first recess 130_P1 may be configured to be adjacent to the first channel structure CH1, and the second recess 130_P2 may be configured to be adjacent to the second channel structure CH2. In other words, the first recess 130_P1 may overlap with the first channel structure CH1 in the second direction D2, and the second recess 130_P2 may overlap with the second channel structure CH2 in the second direction D2. Due to the shapes of the first recess 130_P1 and the second recess 130_P2, the width of the molded pattern 130 between the first recess 130_P1 and the second recess 130_P2 in the second direction D2 may be smaller than the width of the remaining portion.

[0065] Each of the first recess 130_P1 and the second recess 130_P2 of the molded pattern 130 can be aligned to be spaced apart in the first direction D1. That is, as Figure 1 As shown from a planar perspective, the molded pattern 130 can be arranged such that the wide portion and the narrow portion in the second direction D2 can be alternately arranged in the first direction D1.

[0066] The width of the molded pattern 130 in the second direction D2 may be smaller than the width of the protruding insulating film 107 in the second direction D2. For example, the width of the molded pattern 130 in the second direction D2 may be smaller than the width of the protruding insulating film 107 disposed below the molded pattern 130 in the second direction D2. Specifically, as... Figure 3 As shown, the width of the portion of the molded pattern 130 "located between the first channel structure CH1 and the second channel structure CH2" in the second direction D2 may be smaller than the width of the portion of the protruding insulating film 107 "located between the first channel structure CH1 and the second channel structure CH2" in the second direction D2. Furthermore, as... Figure 4 As shown, the width of the portion of the molded pattern 130 "deposited in the interlayer insulating film 170" in the second direction D2 may be smaller than the width of the portion of the protruding insulating film 107 "deposited in the interlayer insulating film 170" in the second direction D2.

[0067] The molded pattern 130 may include an insulating material. For example, the molded pattern 130 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, and low-k insulating materials, but the embodiments are not limited thereto.

[0068] The first letter line WL1 may be disposed on the upper surface of the protruding insulating film 107. The first letter line WL1 may be disposed on the side surface of the molded pattern 130. The first letter line WL1 may extend in the first direction D1. For example, the first letter line WL1 may extend along the first side surface of the molded pattern 130 in the first direction D1. The first side surface of the molded pattern 130 may include a first recess 130_P1. That is, the first letter line WL1 may be disposed along the first recess 130_P1 of the molded pattern 130.

[0069] The second letter line WL2 may be disposed on the upper surface of the protruding insulating film 107. The second letter line WL2 may also be disposed on the side surface of the molded pattern 130. The second letter line WL2 may extend in the first direction D1. For example, the second letter line WL2 may extend along the second side surface of the molded pattern 130 in the first direction D1. The second side surface of the molded pattern 130 may include a second recess 130_P2. That is, the second letter line WL2 may be disposed along the second recess 130_P2 of the molded pattern 130.

[0070] The first character line WL1 can be positioned spaced apart from the second character line WL2 in the second direction D2. The molded pattern 130 can be positioned between the first character line WL1 and the second character line WL2. The first character line WL1 and the second character line WL2 can be symmetrical to each other, and the molded pattern 130 is positioned between the first character line WL1 and the second character line WL2.

[0071] In some embodiments, the upper surfaces of the first character line WL1, the second character line WL2, and the molded pattern 130 may be disposed on the same plane. The upper surfaces of the first character line WL1, the second character line WL2, and the molded pattern 130 may be disposed at the same vertical level. In other words, the distances from the upper surface of the conductive pad 120 to the upper surface of the first character line WL1, from the upper surface of the conductive pad 120 to the upper surface of the second character line WL2, and from the upper surface of the conductive pad 120 to the upper surface of the molded pattern 130 may all be the same. However, the embodiments are not limited to the above.

[0072] For example, each of the first word line WL1 and the second word line WL2 may include at least one of the following: doped polycrystalline silicon, metal (e.g., Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co), conductive metal nitride (e.g., TiN, TaN, WN, NbN, TiAlN, TiSiN, TaSiN, RuTiN), conductive metal silicide, or conductive metal oxide (e.g., PtO, RuO2, IrO2, SrRuO3 (SRO), (Ba,Sr)RuO3 (BSRO), CaRuO3 (CRO), LSCo), but the embodiments are not limited thereto. The word line WL may include a single layer of each of the above materials or multiple layers of the same material.

[0073] In some embodiments, each of the first word line WL1 and the second word line WL2 may include a two-dimensional semiconductor material. For example, the 2D semiconductor material may include graphene, carbon nanotubes, or combinations thereof, but the embodiments are not limited thereto.

[0074] The lining insulating film 140 may be disposed on the first letter line WL1, the second letter line WL2, and the molded pattern 130. For example, the lining insulating film 140 may be disposed between the first letter line WL1 and the first channel structure CH1. The lining insulating film 140 may be disposed between the second letter line WL2 and the second channel structure CH2. The lining insulating film 140 may be disposed between the bit line BL and the first letter line WL1, and between the bit line BL and the second letter line WL2. The lining insulating film 140 may extend along the side surfaces of the first letter line WL1 and the second letter line WL2 in a first direction D1.

[0075] In some embodiments, the thickness of the liner insulating film 140 may not be constant. For example, the thickness of the portion of the liner insulating film 140 "disposed between the first word line WL1 and the first channel structure CH1" may differ from the thickness of the portion of the liner insulating film 140 "disposed below the bit line BL". However, the embodiments are not limited to the above.

[0076] The lining insulating film 140 may include at least one of silicon oxide, silicon oxynitride, and a high-k material having a dielectric constant higher than that of silicon oxide. The high-k material may include a metal oxide or a metal oxynitride. For example, the high-k material of the lining insulating film 140 may include at least one of HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, and Al2O3, but the embodiments are not limited thereto.

[0077] A first channel structure CH1 may be disposed on the first conductive pad 121. The first channel structure CH1 may be connected to the first conductive pad 121. The first channel structure CH1 may be disposed on one side of the first word line WL1. The first channel structure CH1 may extend in the third direction D3. In some embodiments, the first channel structure CH1 may contact the side surface of the protruding insulating film 107. However, the embodiments are not limited to the above.

[0078] The first channel structure CH1 may include a first horizontal portion CH1_H and a first vertical portion CH1_V. The first horizontal portion CH1_H may be disposed on the first conductive pad 121 and the second lower insulating film 105. The first horizontal portion CH1_H may extend in the second direction D2. The first horizontal portion CH1_H may cover a portion of the upper surface of the first conductive pad 121. The first horizontal portion CH1_H may overlap with a portion of the first conductive pad 121 in the third direction D3. The first horizontal portion CH1_H may be connected to the first conductive pad 121.

[0079] The first vertical portion CH1_V may extend in a third direction D3 on the first horizontal portion CH1_H. The first vertical portion CH1_V may extend in a third direction D3 along the liner insulating film 140. In some embodiments, the surfaces of the first vertical portion CH1_V and the second vertical portion CH2_V that are "opposite to the conductive pad 120" may be coplanar with the surfaces of the first word line WL1 and the second word line WL2 that are "opposite to the conductive pad 120". From a planar viewpoint, the first vertical portion CH1_V may include a rectangular shape.

[0080] The first vertical portion CH1_V may have multiple side surfaces. The first vertical portion CH1_V may include first side surfaces to fourth side surfaces SS1, SS2, SS3, and SS4. The first side surface SS1 may face the third side surface SS3 in a first direction D1. The second side surface SS2 may face the fourth side surface SS4 in a second direction D2. Therefore, opposite or opposite sides of the first vertical portion CH1_V can be described as facing each other. The first side surface SS1 and the third side surface SS3 may be connected to the second side surface SS2 and the fourth side surface SS4, respectively.

[0081] like Figure 3 As shown, the first letter line WL1 can be disposed on the second side surface SS2, and the lining insulating film 140 is placed between the first letter line WL1 and the second side surface SS2. The second side surface SS2 can face the first letter line WL1. For example, the second side surface SS2 can overlap the first letter line WL1 in the second direction D2. Figure 5As shown, the first word line WL1 may be disposed on each of the first side surface SS1 and the third side surface SS3. Each of the first side surface SS1 and the third side surface SS3 may face the first word line WL1. For example, each of the first side surface SS1 and the third side surface SS3 may overlap with the first word line WL1 in the first direction D1.

[0082] The first character line WL1 may be disposed on multiple side surfaces of the first vertical portion CH1_V. In some embodiments, the first character line WL1 may be disposed around multiple side surfaces of the first vertical portion CH1_V. The phrase "around multiple side surfaces" may include being disposed on two or more side surfaces. Furthermore, when the first character line WL1 is disposed on a side surface of the component, it may include the first character line WL1 being disposed on all or part of the side surface or overlapping all or part of the side surface. For example, the first character line WL1 may overlap with a portion of the first side surface SS1 and the third side surface SS3 of the first vertical portion CH1_V in the first direction D1.

[0083] The first letter line WL1 may include an extension extending in the first direction D1 and a recess on the first vertical portion CH1_V of the first channel structure CH1. The recess of the first letter line WL1 may be provided on the first recess 130_P1 of the molded pattern 130. The recess of the first letter line WL1 may surround or be adjacent to multiple side surfaces of the first vertical portion CH1_V. The recess of the first letter line WL1 may be provided on the first side surface SS1, the second side surface SS2, and the third side surface SS3 of the first vertical portion CH1_V.

[0084] The second channel structure CH2 may be spaced apart from the first channel structure CH1 in the second direction D2. The lining insulating film 140, the first letter line WL1, the molded pattern 130, and the second letter line WL2 may be disposed between the first channel structure CH1 and the second channel structure CH2. Furthermore, a protruding insulating film 107 may be disposed between the first channel structure CH1 and the second channel structure CH2. However, the embodiment is not limited to the above. For example, the protruding insulating film 107 may be omitted. The first channel structure CH1 and the second channel structure CH2 may be symmetrical to each other, with the molded pattern 130 positioned between the first channel structure CH1 and the second channel structure CH2.

[0085] The second channel structure CH2 may be disposed on the second conductive pad 122. The second channel structure CH2 may be connected to the second conductive pad 122. The second channel structure CH2 may be disposed on one side of the second word line WL2. The second channel structure CH2 may extend in the third direction D3. In some embodiments, the second channel structure CH2 may contact the side surface of the protruding insulating film 107. However, the embodiments are not limited to the above.

[0086] The second channel structure CH2 may include a second horizontal portion CH2_H and a second vertical portion CH2_V. The second horizontal portion CH2_H may be disposed on the second conductive pad 122 and the second lower insulating film 105. The second horizontal portion CH2_H may extend in the second direction D2. The second horizontal portion CH2_H may cover a portion of the upper surface of the second conductive pad 122. The second horizontal portion CH2_H may overlap with a portion of the second conductive pad 122 in the third direction D3. The second horizontal portion CH2_H may be connected to the second conductive pad 122.

[0087] The second vertical portion CH2_V may extend in the third direction D3 on the second horizontal portion CH2_H. The second vertical portion CH2_V may extend in the third direction D3 along the liner insulating film 140. From a planar view, the second vertical portion CH2_V may include a rectangular shape.

[0088] The second vertical portion CH2_V may include multiple side surfaces. The second vertical portion CH2_V may include a fifth to an eighth side surface. The fifth side surface may face the seventh side surface in the first direction D1. The sixth side surface may face the eighth side surface in the second direction D2. The fifth and seventh side surfaces may be connected to each of the sixth and eighth side surfaces.

[0089] The description of each of the fifth to eighth side surfaces of the second vertical portion CH2_V can be similar to the description of the first to fourth side surfaces SS1, SS2, SS3, and SS4 of the first vertical portion CH1_V. For example, the description of the relationship between each of the fifth to eighth side surfaces of the second vertical portion CH2_V and the second word line WL2 can be similar to the description of the relationship between each of the first to fourth side surfaces SS1, SS2, SS3, and SS4 of the first vertical portion CH1_V and the first word line WL1.

[0090] For example, the fifth and seventh side surfaces of the second vertical portion CH2_V may face the second character line WL2 and overlap with the second character line WL2 in the first direction D1. The sixth side surface of the second vertical portion CH2_V may face the second character line WL2 and overlap with the second character line WL2 in the second direction D2.

[0091] The second character line WL2 may be disposed on multiple side surfaces of the second vertical portion CH2_V. In some embodiments, the second character line WL2 may be disposed around multiple side surfaces of the second vertical portion CH2_V. The phrase "around multiple side surfaces" may include being disposed on two or more side surfaces. Furthermore, when the second character line WL2 is disposed on a side surface of the component, it may include the first character line WL1 disposed on or overlapping all or part of the side surface. For example, the second character line WL2 may overlap with portions of the fifth and seventh side surfaces of the second vertical portion CH2_V in the first direction D1.

[0092] The second letter line WL2 may include an extension extending in the first direction D1 and a recess provided on the second vertical portion CH2_V of the second channel structure CH2. The recess of the second letter line WL2 may be provided on the second recess 130_P2 of the molded pattern 130. The recess of the second letter line WL2 may surround multiple side surfaces of the second vertical portion CH2_V. The recess of the second letter line WL2 may be provided on the fifth, sixth, and seventh side surfaces of the second vertical portion CH2_V.

[0093] In a semiconductor memory device according to some embodiments, when word lines WL1 and WL2 are configured as multiple side surfaces surrounding the vertical portions CH1_V and CH2_V of channel structures CH1 and CH2, the area of ​​word lines WL1 and WL2 disposed on the channel structures CH1 and CH2 can be increased. For example, compared to word lines being disposed only on one side surface of the vertical portion of the channel structure, according to some embodiments, the first word line WL1 can be disposed on the first side surface SS1, the second side surface SS2, and the third side surface SS3 of the first vertical portion CH1_V1. Therefore, the electrical characteristics of a transistor using the first word line WL1 as the gate electrode and the first channel structure CH1 as the channel region can be improved. Furthermore, the reliability of the semiconductor memory device including this transistor can be enhanced.

[0094] Each of the first channel structure CH1 and the second channel structure CH2 may include an oxide semiconductor. For example, the oxide semiconductor may include In x Ga y Zn z O、In x Ga y Si z O、In x Sn y Zn z O、In x Zn y O, Zn x O, Zn x Sn y O, Znx O y N, Zr x Zn y Sn z O、Sn x O、Hf x In y Zn z O.Ga x Zn y Sn z O, Al x Zn y Sn z O、Yb x Ga y Zn z O and In x Ga y The embodiment may include at least one of the following: Indium zinc gallium oxide (IGZO). The channel structure CH may comprise a single layer or multiple layers of oxide semiconductor. The channel structure CH may comprise amorphous, single-crystal, or polycrystalline oxide semiconductor.

[0095] In some embodiments, each of the first channel structure CH1 and the second channel structure CH2 may have a bandgap energy greater than that of silicon. For example, the channel structure CH may have a bandgap energy of about 1.5 eV to 5.6 eV. For example, the channel structure CH may have optimal channel performance when it has a bandgap energy of about 2.0 eV to 4.0 eV. For example, the channel structure CH may be polycrystalline or amorphous, but the embodiments are not limited thereto.

[0096] In some embodiments, each of the first channel structure CH1 and the second channel structure CH2 may include a 2D semiconductor material. For example, the 2D semiconductor material may include graphene, carbon nanotubes, or combinations thereof.

[0097] In some embodiments, the width W2 of the channel structures CH1 and CH2 in the first direction D1 may be smaller than the width W1 of the conductive pad 120 in the first direction D1. For example, the width W2 of the first channel structure CH1 in the first direction D1 may be smaller than the width W1 of the first conductive pad 121 in the first direction D1, and the width W2 of the second channel structure CH2 in the first direction D1 may be smaller than the width W1 of the second conductive pad 122 in the first direction D1.

[0098] The upper insulating film 150 may be disposed on the first channel structure CH1 and the second channel structure CH2. For example, the upper insulating film 150 may be disposed on the upper surface of the first horizontal portion CH1_H and the fourth side surface SS4 of the first vertical portion CH1_V. The upper insulating film 150 may be disposed between the first horizontal portion CH1_H and the bit line BL. The upper insulating film 150 may be disposed on the upper surface of the second horizontal portion CH2_H and the eighth side surface of the second vertical portion CH2_V. The upper insulating film 150 may be disposed between the second horizontal portion CH2_H and the bit line BL. Although it is shown that the upper surface of the upper insulating film 150, the upper surface of the first vertical portion CH1_V and the upper surface of the second vertical portion CH2_V are disposed at the same vertical height, the embodiment is not limited thereto.

[0099] The isolation liner 160 may be disposed on the second lower insulating film 105. The isolation liner 160 may be disposed on the upper insulating film 150. The isolation liner 160 may be disposed in the second direction D2 between the upper insulating film 150 and an adjacent upper insulating film 150. The isolation liner 160 may extend along the side surface of the upper insulating film 150. The isolation liner 160 may contact the horizontal portions CH1_H and CH2_H of the channel structures CH1 and CH2. From a cross-sectional view, the isolation liner 160 may have a "U" shape.

[0100] Interlayer insulating film 170 may be disposed within the insulating liner 160. For example, interlayer insulating film 170 may fill the space within the insulating liner 160. Interlayer insulating film 170 may be disposed on the second lower insulating film 105 and the liner insulating film 140. For example, as Figure 4 As shown, in the area where the bit line BL is not provided, the interlayer insulating film 170 may cover the second lower insulating film 105 and the liner insulating film 140.

[0101] For example, the interlayer insulating film 170 may include at least one of silicon oxide, silicon oxynitride, and a low-k material having a dielectric constant lower than that of silicon oxide, but the embodiments are not limited thereto.

[0102] Bit line BL may extend in the second direction D2. Bit line BL may intersect with word lines WL1 and WL2. Bit line BL may be disposed on channel structures CH1 and CH2. Bit line BL may be connected to channel structures CH1 and CH2. Bit line BL may be configured to be spaced apart from word lines WL1 and WL2. For example, contact between bit line BL and word lines WL1 and WL2 may be prevented due to the liner insulating film 140.

[0103] Bit lines BL may include conductive materials. For example, bit lines may include at least one of doped polycrystalline silicon, metals (e.g., Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co), conductive metal nitrides (e.g., TiN, TaN, WN, NbN, TiAlN, TiSiN, TaSiN, RuTiN), conductive metal silicides or conductive metal oxides (e.g., PtO, RuO2, IrO2, SrRuO3 (SRO), (Ba,Sr)RuO3 (BSRO), CaRuO3 (CRO), LSCo), and two-dimensional (2D) materials, but the embodiments are not limited thereto.

[0104] Figure 6 This is a diagram illustrating a semiconductor memory device according to some embodiments. For reference, Figure 6 Can correspond to along Figure 1 The cross-sectional view taken by line AA. For ease of explanation, with Figures 1 to 5 The different constructions described in the text will be mainly described.

[0105] Reference Figure 6 In a semiconductor memory device according to some embodiments, the distance W4 between the first conductive pad 121 and the second conductive pad 122 may be different from the width of the first conductive pad 121 in the second direction D2.

[0106] Each of the first conductive pad 121 and the second conductive pad 122 may have a third width W3 in the second direction D2. The distance W4 between the first conductive pad 121 and the second conductive pad 122 may be greater than the third width W3, and the second conductive pad 122 is spaced apart from the first conductive pad 121 in the second direction D2.

[0107] In some embodiments, the distance W4 between the first conductive pad 121 and the second conductive pad 122 may be the same as the width of the protruding insulating film 107 in the second direction D2, and the second conductive pad 122 is spaced apart from the first conductive pad 121 in the second direction D2. Therefore, the overlapping area between the first horizontal portion CH1_H of the first channel structure CH1 and the first conductive pad 121 in the third direction D3 can be increased. Furthermore, the overlapping area between the second horizontal portion CH2_H of the second channel structure CH2 and the second conductive pad 122 in the third direction D3 can be increased. That is, the contact resistance between the conductive pad 120 and the channel structures CH1 and CH2 can be reduced.

[0108] Figure 7 This is a diagram illustrating a semiconductor memory device according to some embodiments. For reference, Figure 7 Can correspond to along Figure 1 The cross-sectional view taken by line AA. For ease of explanation, with Figures 1 to 5The different constructions described in the text will be mainly described.

[0109] Reference Figure 7 In a semiconductor memory device according to some embodiments, the lower surface of the bit line BL may be disposed at a different vertical height than the upper surfaces of the channel structures CH1 and CH2.

[0110] A portion of the bit line BL may be disposed between the first channel structure CH1 and the insulating film 160, and between the second channel structure CH2 and the insulating film 160. For example, the lower surface of the bit line BL may be disposed between the first channel structure CH1 and the insulating film 160, and between the second channel structure CH2 and the insulating film 160. The lower surface of the bit line BL may be a surface that contacts the upper surface of the upper insulating film 150.

[0111] The lower surface of bit line BL can be positioned at a vertical height below the upper surface of the first vertical portion CH1_V. Bit line BL can be positioned on the upper surface of the first vertical portion CH1_V and a portion of the fourth side surface SS4. The lower surface of bit line BL can be positioned at a vertical height below the upper surface of the second vertical portion CH2_V. Bit line BL can be positioned on the upper surface of the second vertical portion CH2_V and a portion of the eighth side surface. When bit line BL is in partial contact with the upper and side surfaces of channel structures CH1 and CH2, the contact area between bit line BL and channel structures CH1 and CH2 can be increased, thereby reducing resistance.

[0112] Figure 8 This is a diagram illustrating a semiconductor memory device according to some embodiments. For ease of explanation, [the following is a description of the device]. Figures 1 to 5 The different constructions described in the text will be mainly described.

[0113] Reference Figure 8 In a semiconductor memory device according to some embodiments, the width of the conductive pad 120 in the first direction D1 may be different from the width of the recess of the first word line WL1 in the first direction D1.

[0114] The recessed portion of the first character line WL1 may surround multiple side surfaces of the first vertical portion CH1_V of the first channel structure CH1. The width of the recessed portion of the first character line WL1 in the first direction D1 may correspond to the distance between the outer surfaces of the first character line WL1 in the first direction D1. The width of the first conductive pad 121 in the first direction D1 may be smaller than the width of the recessed portion of the first character line WL1 in the first direction D1. Therefore, the first conductive pad 121 and the first character line WL1 may not overlap each other in the third direction D3. Similarly, the second conductive pad 122 and the second character line WL2 may not overlap each other in the third direction D3.

[0115] Figure 9 This is a diagram illustrating a semiconductor memory device according to some embodiments. For ease of description, [the following is used]... Figures 1 to 8 The different constructions described in the text will be mainly described.

[0116] Reference Figure 9 According to some embodiments, a semiconductor memory device may include a cell structure (CELL) and a peripheral circuit structure (PERI).

[0117] Cell structures may include settings in reference Figures 1 to 8 The semiconductor memory device and information storage structure CAP described includes an insulating substrate 100 and a first bonding insulating layer 101.

[0118] The information storage structure CAP may include a first electrode 222, a dielectric film 224, and a second electrode 226. The first electrode 222 may be disposed on the conductive pad 120. The first electrode 222 may be electrically connected to the conductive pad 120.

[0119] For example, the first electrode 222 may include at least one of the following: conductive metal materials (cobalt (Co), titanium (Ti), nickel (Ni), tungsten (W), molybdenum (Mo), etc.), metal nitrides (titanium nitride (TiN), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), aluminum tantalum nitride (TaAlN), tungsten nitride (WN), etc.), noble metal materials (platinum (Pt), ruthenium (Ru), iridium (Ir), etc.), conductive oxides (PtO, RuO2, IrO2, SRO (SrRuO3), BSRO ((Ba,Sr)RuO3), CRO (CaRuO3), LSCo, etc.) films, and metal silicide films. However, the embodiments are not limited to the above.

[0120] A dielectric film 224 may be disposed on the first electrode 222. The dielectric film 224 may extend along the contour of the first electrode 222. For example, the dielectric film 224 may comprise a high-k material, including silicon oxide, silicon nitride, silicon oxynitride, and metals. Although the dielectric film 224 is shown as a single film, this is for ease of description only, and the embodiments are not limited thereto. Contrary to the illustration, the dielectric film 224 may comprise multiple films.

[0121] The second electrode 226 may be disposed on the dielectric film 224. The second electrode 226 may fill the empty space between the first electrodes 222. The second electrode 226 may include at least one of, for example, elemental semiconductor material film and compound semiconductor material film. The second electrode 226 may include doped n-type impurities or p-type impurities.

[0122] An insulating substrate 100 may be disposed below the information storage structure CAP. The insulating substrate 100 may be disposed on the lower surface of the second electrode 226. The insulating substrate 100 may include an insulating material. A first bonding insulating layer 101 may be disposed on the lower surface of the insulating substrate 100.

[0123] The peripheral circuit structure PERI may include a substrate 200, a plurality of peripheral circuit transistors 210, a wiring structure 220, a peripheral circuit insulating film 250, and a second bonding insulating layer 201.

[0124] The substrate 200 may be a semiconductor substrate. For example, the substrate 200 may include silicon (Si), silicon germanium (SiGe), indium antimonide (InSb), lead telluride (PbTe), indium arsenide (InAs), indium phosphide (InP), gallium arsenide (GaAs), gallium antimonide (GaSb), etc. However, the embodiments are not limited to the above.

[0125] Multiple peripheral circuit transistors 210 may be disposed on the substrate 200. These multiple peripheral circuit transistors 210 may include sensing transistors, transmission transistors, driving transistors, etc. The multiple peripheral circuit transistors 210 may be configured, for example, as row decoders, column decoders, sense amplifiers, sub-word line drivers, etc., of dynamic random access memory (DRAM). However, the embodiments are not limited to the above.

[0126] The wiring structure 220 can be disposed on multiple peripheral circuit transistors 210. The wiring structure 220 can be configured as an electrical connection path between the multiple peripheral circuit transistors 210 and the cell structure.

[0127] The cell structure can be disposed on the peripheral circuit structure (PERI). The PERI and the cell structure can be bonded to each other. For example, the first bonding insulating layer 101 of the cell structure and the second bonding insulating layer 201 of the PERI can be bonded to each other. Chemical bonding can be formed between the constituent materials of the first bonding insulating layer 101 and the constituent materials of the second bonding insulating layer 201.

[0128] Each of the first bonding insulating layer 101 and the second bonding insulating layer 201 may include, for example, one of silicon carbonitride (SiCN), silicon nitride (SiN), silicon carbon oxynitride (SiOC), silicon oxynitride (SiON), and silicon carbonitride oxynitride (SiOCN).

[0129] Figure 10 This is a diagram illustrating a semiconductor memory device according to some embodiments. For ease of explanation, [the following is a description of the device]. Figures 1 to 9 The different constructions described in the text will be mainly described.

[0130] Reference Figure 10According to some embodiments, a semiconductor memory device may include a cell structure (CELL) and a peripheral circuit structure (PERI).

[0131] Cell structures can include from Figures 1 to 8 A semiconductor memory device with a 180-degree rotation structure, an insulating substrate 100, and a first wiring structure 190 disposed in the insulating substrate 100. The information storage structure CAP may include a first electrode 222, a dielectric film 224, and a second electrode 226. A description of the first electrode 222, the dielectric film 224, and the second electrode 226 can be found in reference [reference needed]. Figure 9 The descriptions are similar.

[0132] An insulating substrate 100 may be disposed below the bit line BL. The insulating substrate 100 may include insulating material. A first wiring structure 190 may be disposed within the insulating substrate 100.

[0133] The first wiring structure 190 may be electrically connected to the peripheral circuit structure PERI. The first wiring structure 190 may include a first bonding pad 195. The first bonding pad 195 may be the pad of the first wiring structure 190 that is "set to be closest to the peripheral circuit structure PERI". The first bonding pad 195 may be disposed on the lower surface of the insulating substrate 100.

[0134] The peripheral circuit structure PERI may include a substrate 200, a plurality of peripheral circuit transistors 210, a second wiring structure 230, and a peripheral circuit insulating film 250. A description of the substrate 200 and the plurality of peripheral circuit transistors 210 can be found in reference [reference needed]. Figure 9 The descriptions are similar.

[0135] The second wiring structure 230 can be disposed on multiple peripheral circuit transistors 210. The second wiring structure 230 can be configured as an electrical connection path between the multiple peripheral circuit transistors 210 and the cell structure.

[0136] The second wiring structure 230 may include a second bonding pad 295. The second bonding pad 295 may be a pad of the second wiring structure 230 that is "set to be closest to the cell structure". A first bonding pad 195 may be disposed on the second bonding pad 295. The first bonding pad 195 and the second bonding pad 295 may be metallically bonded to each other. For example, the first bonding pad 195 and the second bonding pad 295 may be bonded by Cu-Cu bonding. However, the embodiments are not limited to the above. For example, each of the first bonding pad 195 and the second bonding pad 295 may include one of copper (Cu), tungsten (W), aluminum (Al), cobalt (Co), and molybdenum (Mo).

[0137] Figures 11 to 41This is a diagram illustrating intermediate stages and a method for manufacturing a semiconductor memory device according to some embodiments. For ease of description, see reference ______. Figures 1 to 5 Constructs that are identical to those described will be briefly described or will not be described at all.

[0138] Figure 11 This is a plan view illustrating a method for manufacturing a semiconductor memory device according to some embodiments, and Figure 12 It is along Figure 11 The sectional view taken by line AA.

[0139] Reference Figure 11 and Figure 12 A plurality of conductive pads 120 and a second lower insulating film 105 surrounding the plurality of conductive pads 120 may be provided. The plurality of conductive pads 120 may be provided on the information storage structure CAP. The conductive pads 120 may be spaced apart from each other in a first direction D1 and a second direction D2. In some embodiments, the conductive pads 120 may be aligned in the first direction D1 and the second direction D2. The second lower insulating film 105 may be provided on the first lower insulating film 110.

[0140] Figure 13 This is a plan view illustrating a method for manufacturing a semiconductor memory device according to some embodiments, and Figure 14 It is along Figure 13 The sectional view taken by line AA.

[0141] Reference Figure 13 and Figure 14 A pre-insulating film 107_P and a pre-molded pattern 130_P can be formed on multiple conductive pads 120 and a second lower insulating film 105.

[0142] A pre-insulating film 107_P may be provided on a plurality of conductive pads 120 and a second lower insulating film 105. The pre-insulating film 107_P may cover the upper surface of the plurality of conductive pads 120 and the upper surface of the second lower insulating film 105. The pre-insulating film 107_P may include, for example, any one of silicon nitride, silicon oxynitride, silicon carbonitride, and silicon carbonitride, and the embodiments are not limited thereto.

[0143] A pre-molded pattern 130_P may be formed on the pre-insulating film 107_P. The pre-molded pattern 130_P may cover the upper surface of the pre-insulating film 107_P. The pre-molded pattern 130_P may include at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, and low-k insulating materials, and the embodiments are not limited thereto.

[0144] Figure 15 This is a plan view illustrating a method for manufacturing a semiconductor memory device according to some embodiments, and Figure 16 and Figure 17 It is along Figure 15A cross-sectional view taken from lines AA and BB.

[0145] Reference Figures 15 to 17 It can remove Figure 14 A portion of the pre-molded pattern 130_P is used to form the molded pattern 130, and a portion of the pre-insulating film 107_P can be removed to form the protruding insulating film 107.

[0146] Specifically, the pre-molded pattern 130_P can be patterned to form the molded pattern 130. The process of forming the molded pattern 130 may include an etching process using a photomask. For example, a first recess 130_P1 and a second recess 130_P2 of the molded pattern 130 can be formed by an etching process.

[0147] The molded pattern 130 may extend in a first direction D1. The molded pattern 130 may include a first recess 130_P1 and a second recess 130_P2. The first recess 130_P1 and the second recess 130_P2 may be spaced apart from each other in a second direction D2. Each of the first recess 130_P1 and the second recess 130_P2 may be recessed in opposite directions.

[0148] A portion of the pre-insulating film 107_P can be removed to form a protruding insulating film 107. The protruding insulating film 107 may be disposed on the second lower insulating film 105. In some embodiments, the boundary surface between the protruding insulating film 107 and the second lower insulating film 105 is not distinguished. However, the embodiments are not limited to the above.

[0149] Figure 18 This is a plan view illustrating a method for manufacturing a semiconductor memory device according to some embodiments, and Figure 19 and Figure 20 It is along Figure 18 A cross-sectional view taken from lines AA and BB.

[0150] Reference Figures 18 to 20 The pre-printed letter line WL_P can be formed on the second lower insulating film 105, multiple conductive pads 120, protruding insulating film 107 and molded pattern 130.

[0151] The pre-line WL_P may extend along the outline of the molded pattern 130. For example, the pre-line WL_P may cover the side and top surfaces of the molded pattern 130. For example, the pre-line WL_P may be formed by either a physical vapor deposition (PVD) method or a chemical vapor deposition (CVD) method. However, the embodiments are not limited to the above.

[0152] Figure 21 This is a plan view illustrating a method for manufacturing a semiconductor memory device according to some embodiments, and Figure 22 and Figure 23 It is along Figure 21 A cross-sectional view taken from lines AA and BB. For reference, the insulating film 107 is highlighted from... Figure 21 Omitted.

[0153] Reference Figures 21 to 23 The first letter line WL1 and the second letter line WL2 can be formed on both sides of the molded pattern 130.

[0154] Specifically, it can be removed through an etching process. Figure 19 A portion of the pre-written word line WL_P. The first word line WL1 and the second word line WL2 can be formed by an etching process. The first word line WL1 may extend along one side surface of the molded pattern 130 in a first direction D1, and the second word line WL2 may extend along the other side surface of the molded pattern 130 in the first direction D1. A portion of the pre-written word line WL_P can be removed to expose the upper surface of the molded pattern 130, the upper surfaces of the plurality of conductive pads 120, and the upper surface of the second lower insulating film 105.

[0155] The first character line WL1 may extend along the first recess 130_P1 of the molded pattern 130, and the second character line WL2 may extend along the second recess 130_P2 of the molded pattern 130. The distance between the first character line WL1 and the second character line WL2, which is "spaced apart from the first character line WL1", in the second direction D2 may not be constant. Figure 22 The distance between the first character line WL1 and the second character line WL2, which is "separated from the first character line WL1", can be less than Figure 23 The distance between the first character line WL1 and the second character line WL2, which is "separated from the first character line WL1".

[0156] Figure 24 This is a plan view illustrating a method for manufacturing a semiconductor memory device according to some embodiments, and Figure 25 and Figure 26 It is along Figure 24 A cross-sectional view taken from lines AA and BB. For reference, the insulating film 107 is highlighted from... Figure 24 Omitted.

[0157] Reference Figures 24 to 26 A first backing film 142 may be formed on the first character line WL1 and the second character line WL2. The first backing film 142 may be disposed on the side surface of the first character line WL1 and the side surface of the second character line WL2.

[0158] In some embodiments, a pre-line film may be formed to cover the second lower insulating film 105, a plurality of conductive pads 120, a first word line WL1, a second word line WL2, and a molded pattern 130. A portion of the pre-line film may be removed by an etching process to form a first liner film 142. The first liner film 142 may include at least one of, for example, silicon oxide, silicon oxynitride, and a high-k material having a dielectric constant higher than that of silicon oxide. The high-k material may include a metal oxide or a metal oxynitride. For example, the high-k material of the liner insulating film 140 may include at least one of HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, and Al2O3, but the embodiments are not limited thereto.

[0159] Figure 27 This is a plan view illustrating a method for manufacturing a semiconductor memory device according to some embodiments, and Figure 28 and Figure 29 It is along Figure 27 A cross-sectional view taken from lines AA and BB.

[0160] Reference Figures 27 to 29 A pre-channel layer CH_P can be formed on the first liner 142.

[0161] Specifically, a pre-channel layer CH_P can be formed on the side and top surfaces of the second lower insulating film 105, the plurality of conductive pads 120, the first backing film 142, the top surface of the first word line WL1, the top surface of the molded pattern 130, and the top surface of the second word line WL2. The pre-channel layer CH_P can be formed along the contour of the side surface of the first word line WL1 and along the contour of the side surface of the second word line WL2. That is, along the word lines WL1 and WL2, the width of the pre-channel layer CH_P in the second direction D2 can be as follows: Figure 28 and Figure 29 The changes shown are illustrated.

[0162] The description of the material for the pre-trench layer CH_P can be found in the reference. Figures 1 to 5 The descriptions of the materials for the first channel structure CH1 and the second channel structure CH2 are identical.

[0163] Figure 30 This is a plan view illustrating a method for manufacturing a semiconductor memory device according to some embodiments, and Figure 31 and Figure 32 It is along Figure 30 A cross-sectional view taken from lines AA and BB.

[0164] Reference Figures 30 to 32A pre-insulating film 150_P can be formed on the pre-channel layer CH_P. The pre-insulating film 150_P can cover the pre-channel layer CH_P. For example, the pre-insulating film 150_P may include at least one of silicon oxide, silicon oxynitride, and a low-k material having a dielectric constant lower than that of silicon oxide, but the embodiments are not limited thereto.

[0165] Figure 33 This is a plan view illustrating a method for manufacturing a semiconductor memory device according to some embodiments, and Figure 34 and Figure 35 It is along Figure 33 A cross-sectional view taken from lines AA and BB. For reference, the upper insulating film 150 is from... Figure 33 Omitted.

[0166] Reference Figures 33 to 35 It can remove Figure 31 A portion of the pre-insulating film 150_P and a portion of the pre-channel layer CH_P are used to form the upper insulating film 150, the pre-first channel CH1_P and the pre-second channel CH2_P.

[0167] Specifically, a first mask pattern can be formed on the pre-insulating film 150_P. The first mask pattern may include an opening that exposes a portion of the pre-insulating film 150_P. The opening of the first mask pattern may extend in a first direction D1. A portion of the pre-insulating film 150_P and the pre-channel layer CH_P can be removed by using the first mask pattern as an etching mask. Thus, a pre-first channel CH1_P, a pre-second channel CH2_P, and the upper insulating film 150 can be formed. The pre-first channel CH1_P and the pre-second channel CH2_P may extend in the first direction D1.

[0168] Figure 36 and Figure 37 This is a diagram illustrating a method for manufacturing a semiconductor memory device according to some embodiments. Figure 36 Can correspond to along Figure 33 The sectional view taken by line AA, and Figure 37 Can correspond to along Figure 33 The sectional view taken by line BB.

[0169] Reference Figure 36 and Figure 37 A second backing film 144 can be formed on the upper insulating film 150, the second lower insulating film 105, the pre-first channel CH1_P, the pre-second channel CH2_P, the first letter line WL1, the second letter line WL2 and the molded pattern 130.

[0170] The second liner 144 may be disposed on the upper surface and side surface of the upper insulating film 150. The second liner 144 may be disposed between the upper insulating film 150 and an adjacent upper insulating film 150 in the second direction D2. In some embodiments, the second liner 144 may be conformally formed.

[0171] The description of the material of the second liner 144 may be the same as the description of the material of the first liner 142. In some embodiments, the first liner 142 and the second liner 144 may comprise the same material. In this case, the boundary surface between the first liner 142 and the second liner 144 may not be distinguishable.

[0172] Figure 38 This is a plan view illustrating a method for manufacturing a semiconductor memory device according to some embodiments, and Figure 39 It is along Figure 38 The cross-sectional view is taken along line BB. For reference, along... Figure 38 The sectional view taken by line AA can be compared with Figure 36 same.

[0173] Reference Figure 38 and Figure 39 It can remove a portion of the upper insulating film 150. Figure 36 Part of the pre-first channel CH1_P and Figure 36 A portion of the pre-second channel CH2_P to form the first channel structure CH1 and the second channel structure CH2.

[0174] Specifically, a second mask pattern may be formed on the upper insulating film 150. The second mask pattern may include openings extending in the second direction D2. The openings of the second mask pattern may expose a portion of the upper insulating film 150. A portion of the upper insulating film 150, a portion of the pre-first channel CH1_P, and a portion of the pre-second channel CH2_P can be removed by using the second mask pattern as an etching mask. In this case, a portion of the second substrate 144 may also be removed. For example, a portion of the substrate 144 may be removed. Figure 39 The second liner 144 shown is disposed on the second lower insulating film 105.

[0175] Therefore, a first channel structure CH1 and a second channel structure CH2 can be formed. The first channel structure CH1 and the second channel structure CH2 can be spaced apart from each other in the second direction D2. The first channel structure CH1 can be aligned with each other in the first direction D1, and the second channel structure CH2 can be aligned with each other in the first direction D1. The first channel structure CH1 may include a first horizontal portion CH1_H and a first vertical portion CH1_V. The second channel structure CH2 may include a second horizontal portion CH2_H and a second vertical portion CH2_V.

[0176] Figure 40 and Figure 41 This is a diagram illustrating a method for manufacturing a semiconductor memory device according to some embodiments. Figure 40 Can correspond to along Figure 38 The sectional view taken by line AA, and Figure 41 Can correspond to along Figure 38 The sectional view taken by line BB.

[0177] Reference Figure 40 and Figure 41 An interlayer insulating film 170 can be formed on the second liner 144. The interlayer insulating film 170 can cover the second liner 144 and the second lower insulating film 105. The interlayer insulating film 170 can fill the space between the upper insulating films 150.

[0178] The interlayer insulating film 170 can be patterned. For example, trenches extending in the second direction D2 can be formed on the interlayer insulating film 170. The trenches can expose the upper surfaces of the first vertical portion CH1_V and the second vertical portion CH2_V. Conductive material can be deposited inside the trenches to form bit lines ( Figure 2 (BL in the text).

[0179] While specific embodiments of this disclosure have been described with reference to the accompanying drawings, those skilled in the art will understand that this disclosure can be implemented in other specific forms without altering the technical concept or essential features of this disclosure. Therefore, it should be understood that the above embodiments are illustrative in all respects and not restrictive.

Claims

1. A semiconductor memory device, comprising: Conductive pads, in information storage structures; The channel structure is on the conductive pad and includes a vertical portion extending in a first direction; The letter lines extend in a second direction and on multiple side surfaces of the vertical portion, wherein the second direction is perpendicular to the first direction; and The bit line extends upward on the channel structure and on a third direction intersecting the second direction, wherein the third direction is perpendicular to the first direction.

2. The semiconductor memory device according to claim 1, wherein, The plurality of side surfaces of the vertical portion of the channel structure include a first side surface, a second side surface connected to the first side surface, and a third side surface connected to the second side surface and opposite to the first side surface. The letter lines are on the first side surface, the second side surface, and the third side surface.

3. The semiconductor memory device according to claim 1, wherein, The channel structure also includes a horizontal portion, which is disposed on the conductive pad and extends upward in a third direction. The vertical portion of the channel structure extends in the first direction on the horizontal portion.

4. The semiconductor memory device according to claim 3, wherein, The horizontal portion of the channel structure overlaps with at least a portion of the upper surface of the conductive pad in the first direction.

5. The semiconductor memory device according to claim 1, wherein, The letter line includes an extension and a recess, the extension extending in a second direction and the recess adjacent to the plurality of side surfaces of the vertical portion of the channel structure.

6. The semiconductor memory device according to claim 1, wherein, The width of the conductive pad in the second direction is equal to or greater than the width of the channel structure in the second direction.

7. The semiconductor memory device according to claim 1, further comprising: The lining insulating film extends along the letter line in the second direction and is located between the letter line and the channel structure.

8. The semiconductor memory device according to claim 1, further comprising: An insulating film is placed between the channel structure and the bit line.

9. The semiconductor memory device according to claim 1, wherein, The bit line contacts a portion of the side surface of the vertical section and the surface of the vertical section opposite the conductive pad.

10. The semiconductor memory device according to any one of claims 1 to 9, wherein, The vertical portion of the surface opposite the conductive pad is coplanar with the surface of the letter line opposite the conductive pad.

11. A semiconductor memory device, comprising: The first conductive pad and the second conductive pad are respectively located on the information storage structure; A first channel structure is formed on a first conductive pad and extends in a first direction; The second channel structure is on the second conductive pad and extends in the first direction; The first line extends in the second direction and is on one side of the first channel structure, wherein the second direction is perpendicular to the first direction; The second letter line extends in the second direction, is spaced apart from the first letter line on a third direction that intersects the second direction and is perpendicular to the first direction, and is on one side of the second channel structure; The molded pattern is located between the first and second letter lines; A lining insulating film, between the first letter and the first channel structure, and between the second letter and the second channel structure; and Bit lines extend upwards on a third side and on the surfaces of the first channel structure opposite to the first conductive pad and the second channel structure opposite to the second conductive pad, wherein... The first letter is adjacent to at least a portion of the side surface of the first channel structure, and The second letter is adjacent to at least a portion of the side surface of the second channel structure.

12. The semiconductor memory device according to claim 11, wherein, The molded pattern extends in the second direction, and The width variation of the molded pattern in the third direction.

13. The semiconductor memory device according to claim 11, wherein, The molded pattern includes a first recess and a second recess spaced apart from the first recess in a third direction. The first recess overlaps with the first channel structure in the third direction, and The second recess is superimposed on the second channel structure in the third direction.

14. The semiconductor memory device according to claim 13, wherein, The first letter extends along the first recess of the molded pattern, and The second letter line extends along the second recess of the molded pattern.

15. The semiconductor memory device according to claim 11, wherein, The first channel structure is spaced apart from the second channel structure in the third direction, and Each of the first and second letter lines is located between the first and second channel structures.

16. The semiconductor memory device of claim 11, further comprising: The lower insulating film is placed on the first conductive pad and the second conductive pad; as well as The insulating film is highlighted between the lower insulating film and the molded pattern.

17. The semiconductor memory device of claim 16, wherein, The width of the insulating film in the third direction is greater than the width of the molded pattern in the third direction.

18. The semiconductor memory device of claim 11, wherein, The distance between the first conductive pad and the second conductive pad in the third direction is equal to or greater than the width of the first conductive pad in the third direction.

19. The semiconductor memory device of claim 11, wherein, The first channel structure includes a first horizontal portion and a first vertical portion. The first horizontal portion is on the surface of the first conductive pad, and the first vertical portion extends on the first horizontal portion in a first direction. The second channel structure includes a second horizontal portion and a second vertical portion, the second horizontal portion being on the surface of the second conductive pad, and the second vertical portion being on the second horizontal portion and extending in a first direction.

20. A semiconductor memory device, comprising: The first and second conductive pads are located on the corresponding information storage structures; The lower insulating film is placed on the first conductive pad and the second conductive pad; The first channel structure includes a first horizontal portion and a first vertical portion. The first horizontal portion is on a first conductive pad and extends in a first direction. The first vertical portion extends on the first horizontal portion in a second direction, wherein the second direction is perpendicular to the first direction. The second channel structure includes a second horizontal portion and a second vertical portion, the second horizontal portion being on the second conductive pad and extending in a first direction, and the second vertical portion extending on the second horizontal portion in a second direction. The first character line extends upward at a third point intersecting the first direction, and is on one side of the first vertical portion; The second character line extends upwards from the third position and is on one side of the second vertical section; The molded pattern is located between the first and second letter lines; A lining insulating film, between the first letter and the first channel structure, and between the second letter and the second channel structure; and Bit lines extend in a first direction and are present on the surface of the first channel structure opposite to the first conductive pad and on the surface of the second channel structure opposite to the second conductive pad, wherein, The first character line is on the first side surface, the second side surface, and the third side surface of the first vertical portion, and The first and third side surfaces of the first vertical portion are opposite to each other in the third direction and are each connected to the second side surface.

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