Resistive random access memory element with non-reactive compound electrodes and method for manufacturing the same

Abstract

The present disclosure relates to a resistive random access memory (RRAM) device. In some embodiments, the RRAM device includes a first electrode, a second electrode including a first conductive material, and an oxide switching layer positioned between the first electrode and the second electrode. The oxide switching layer includes at least one transition metal oxide. The first electrode includes a metal nitride layer including a metal nitride and a metal layer formed on the metal nitride layer. The metal layer includes a metal that is non-reactive with the at least one transition metal oxide. In some embodiments, the metal nitride in the first electrode includes titanium nitride and / or tantalum nitride. The metal layer includes a layer of a noble metal such as platinum, palladium, iridium, ruthenium, etc.

Description

[Technical Field]

[0001] Embodiments of this disclosure generally relate to resistive random-access memory (RRAM) elements, and more specifically to RRAM elements equipped with non-reactive compound electrodes. [Background technology]

[0002] Resistive random-access memory (RRAM) elements are two-terminal passive elements with adjustable, non-volatile resistance. The resistance of an RRAM element can be electrically switched between a high-resistance state (HRS) and a low-resistance state (LRS) by applying an appropriate programming signal to the RRAM element. RRAM elements can be used to form crossbar arrays used for implementing in-memory arithmetic applications, non-volatile solid-state memory, image processing applications, neural networks, and the like. [Overview of the Initiative]

[0003] A simplified overview of some aspects of this disclosure is provided below. This overview is not a comprehensive overview of the disclosure, nor is it intended to identify the main features or key elements of the disclosure, nor to define the scope of any particular embodiment or claim. Its purpose is to present some of the concepts of the disclosure in a simplified form as an introduction to the more detailed description provided later.

[0004] According to one or more aspects of the present disclosure, a resistive random-access memory (RRAM) element comprises a first electrode, a second electrode comprising a conductive material, and an oxide switching layer located between the first electrode and the second electrode. The first electrode comprises a metal nitride layer comprising a metal nitride and a metal layer formed on the metal nitride layer. The oxide switching layer comprises at least one transition metal oxide. In some embodiments, the metal layer comprises a metal that is non-reactive with the at least one transition metal oxide.

[0005] In some embodiments, the metal nitride includes at least one of titanium nitride and tantalum nitride.

[0006] In some embodiments, the metal that does not react with the at least one transition metal oxide includes at least one of platinum, palladium, iridium, or ruthenium.

[0007] In some embodiments, the metal layer is thinner than the metal nitride layer.

[0008] In some embodiments, the thickness of the metal layer is 3 nm to 10 nm.

[0009] In some embodiments, the thickness of the metal nitride layer is 20 nm to 50 nm.

[0010] In some embodiments, the at least one transition metal oxide is HfO x and TaO y It includes at least one of the following, where x ≤ 2.0 and y ≤ 2.5.

[0011] In some embodiments, the conductive material of the second electrode includes tantalum.

[0012] In some embodiments, the RRAM element further comprises an interface layer located between the oxide switching layer and the second electrode. In some embodiments, the interface layer contains aluminum oxide.

[0013] In some embodiments, the RRAM element further comprises an adhesive layer containing at least one of titanium and tantalum, and the metal nitride layer is formed on the adhesive layer.

[0014] According to one or more aspects of the present disclosure, a method for manufacturing a resistive random access memory (RRAM) device includes forming a first electrode, forming an oxide switching layer on the first electrode, and forming a second electrode including a conductive material on the oxide switching layer. The oxide switching layer includes at least one transition metal oxide. The first electrode includes a metal nitride layer including a metal nitride and a metal layer formed on the metal nitride layer. In some embodiments, the metal layer includes a metal that is non-reactive with the at least one transition metal oxide.

[0015] In some embodiments, the metal nitride includes at least one of titanium nitride and tantalum nitride.

[0016] In some embodiments, the metal that is non-reactive with the at least one transition metal oxide includes at least one of platinum, palladium, iridium, or ruthenium.

[0017] In some embodiments, the metal layer is thinner than the metal nitride layer.

[0018] In some embodiments, the thickness of the metal layer is from 3 nm to 10 nm.

[0019] In some embodiments, the thickness of the metal nitride layer is from 20 nm to 50 nm.

[0020] In some embodiments, the at least one transition metal oxide includes at least one of HfO x and TaO y where x ≤ 2.0 and y ≤ 2.5.

[0021] In some embodiments, the method further includes forming an interface layer on the oxide switching layer, the interface layer being located between the oxide switching layer and the second electrode, and the interface layer including aluminum oxide.

[0022] In some embodiments, the method further comprises forming an adhesive layer containing at least one of titanium and tantalum, wherein the metal nitride layer is formed on the adhesive layer.

[0023] According to one or more aspects of the present disclosure, a method for manufacturing a non-reactive electrode comprises forming an adhesive layer containing at least one of titanium and tantalum, forming a metal nitride layer containing at least one metal nitride on the adhesive layer, forming a metal layer containing a noble metal on the metal nitride layer, and selectively removing one or more portions of the adhesive layer, the metal nitride layer, and the metal layer to form a non-reactive electrode, wherein the metal nitride contains at least one of titanium nitride and tantalum nitride. [Brief explanation of the drawing]

[0024] The Disclosure will be better understood from the detailed descriptions of various embodiments shown below. However, the drawings are for illustrative and illustrative purposes only and do not limit the Disclosure to any particular embodiment. [Figure 1] Figure 1 is a schematic diagram showing an example of a crossbar circuit according to an embodiment of the present disclosure. [Figure 2] Figure 2 is a schematic diagram showing an example of a crosspoint element according to the present disclosure. [Figure 3A] Figure 3A shows a cross-sectional view of an example of an RRAM element according to the present disclosure. [Figure 3B] Figure 3B shows a cross-sectional view of the RRAM element shown in Figure 3A in a low-resistance state. [Figure 3C] Figure 3C shows a cross-sectional view of the RRAM element shown in Figure 3A under high resistance conditions. [Figure 4] Figure 4 shows a cross-sectional view of an example of a non-reactive compound electrode 400 according to another embodiment of the present disclosure. [Figure 5] Figure 5 shows a cross-sectional view of an example of an RRAM element according to the present disclosure. [Figure 6] Figure 6 shows a cross-sectional view of an example of an RRAM element according to the present disclosure. [Figure 7]Figure 7 shows a cross-sectional view of an example of an RRAM element according to the present disclosure. [Figure 8A] Figure 8A is a schematic diagram showing a cross-sectional view of a structure for forming a non-reactive electrode of an RRAM element according to an embodiment of this disclosure. [Figure 8B] Figure 8B is a schematic diagram showing a cross-sectional view of a structure for forming a non-reactive electrode of an RRAM element according to an embodiment of this disclosure. [Figure 8C] Figure 8C is a schematic diagram showing a cross-sectional view of a structure for forming a non-reactive electrode of an RRAM element according to an embodiment of this disclosure. [Figure 8D] Figure 8D is a schematic diagram showing a cross-sectional view of a structure for forming a non-reactive electrode of an RRAM element according to the embodiment of this disclosure. [Figure 8E] Figure 8E is a schematic diagram showing a cross-sectional view of a structure for forming a non-reactive electrode of an RRAM element according to the present disclosure. [Figure 8F] Figure 8F is a schematic diagram showing a cross-sectional view of a structure for forming a non-reactive electrode of an RRAM element according to the embodiment of this disclosure. [Figure 9A] Figure 9A shows the IV (current-voltage) characteristics of an RRAM element according to the embodiment of this disclosure. [Figure 9B] Figure 9B is an IV curve showing the analog operation of an RRAM element according to the embodiment of this disclosure. [Figure 9C] Figure 9C shows the time-dependent read current characteristics of an RRAM element according to the embodiment of this disclosure. [Figure 10] Figure 10 is a flowchart showing an example of a method for manufacturing an RRAM element according to the present disclosure. [Figure 11] Figure 11 is a flowchart illustrating an example of a method for manufacturing a non-reactive electrode according to an embodiment of this disclosure. [Modes for carrying out the invention]

[0025] Aspects of this disclosure provide resistive random access memory (RRAM) elements and methods for manufacturing the same. The RRAM element is a two-terminal passive element having a variable resistor. The RRAM element may include a first electrode, a second electrode, and an oxide switching layer located between the first electrode and the second electrode. In some embodiments, the first electrode and the second electrode may be the lower electrode and upper electrode of the RRAM element, respectively. In some embodiments, the first electrode and the second electrode may be the upper electrode and lower electrode of the RRAM element, respectively. The first electrode may include a non-reactive metal such as platinum (Pt), palladium (Pd), or ruthenium (Ru). The second electrode may include a reactive metal such as tantalum (Ta). Electrodes containing non-reactive metals are also referred to herein as "non-reactive electrodes." Electrodes containing reactive metals are also referred to herein as "reactive electrodes." The oxide switching layer is made of hafnium oxide (HfO x ) or tantalum oxide (TaO xIt may contain transition metal oxides such as etc. Before the RRAM element receives an appropriate electrical stimulus (for example, a voltage or current signal applied to the RRAM element), it is in an initial state or an unused state and may have an initial high resistance. The RRAM element may be adjusted from the unused state to the low resistance state through a formation process, or from the high resistance state (HRS) to the low resistance state (LRS) through a setting process. The formation process refers to programming the element from the unused state. The setting process refers to programming the element from the high resistance state (HRS). After the reactive metal electrode is deposited on the oxide switching layer, the reactive metal can absorb oxygen from the oxide switching layer, generate oxygen vacancies in the oxide switching layer, and oxygen ions can move within the oxide switching layer through a vacancy mechanism. During the formation process, when an appropriate programming signal (for example, a voltage or current signal) is applied to the RRAM element, oxygen ions can be moved from the oxide switching layer to the reactive electrode. As a result, a conductive channel or filament is formed through the oxide switching layer (for example, from the reactive electrode to the non-reactive electrode). Next, the RRAM element is reset to the high resistance state by applying a reset signal (for example, a voltage signal, a current signal) to the RRAM element. The application of the reset signal to the RRAM element can cause oxygen to flow back into the oxide switching layer and block the conductive filament. The RRAM element can be electrically switched between the high resistance state and the low resistance state by applying an appropriate programming signal (for example, a voltage signal, a current signal, etc.) to the RRAM element. In a crossbar array circuit, the programming signal can be supplied to a specified RRAM element through a selector such as a transistor or a diode.

[0026] An RRAM element containing platinum (Pt) in the non-reactive electrode can provide high RRAM performance such as reliability, durability, multi-valuedness, retention force, etc. The lower electrode of Pt, TaO x An oxide switching layer containing, Ta (also referred to as the Pt / TaO x / Ta system) has an upper electrode in the RRAM, TaO xThe Ta filament inside demonstrated excellent performance in terms of linearity, analogity, retention, and durability for in-memory computing (IMC) applications. Pt / HfO x In the / Ta system, Ta is HfO x Move inside and HfO x It is possible to form Ta-rich filaments within it, demonstrating excellent performance in terms of linearity, analogity, retention, and durability for IMC applications. However, the material and process costs of Pt are high, and major manufacturing plants may not be ready to incorporate Pt into their processes.

[0027] According to some embodiments of this disclosure, the non-reactive compound electrode of the RRAM element may include a metal nitride layer and a metal layer. The metal nitride layer may include one or more metal nitrides such as TiN and TaN. The metal layer may include a non-reactive metal such as Pt, Pd, Ru, and Ir. The metal layer may be substantially thinner than the metal nitride layer. For example, the metal nitride layer may be about 20 nm to 25 nm, and the metal layer may be about 3 nm to about 8 nm.

[0028] Both TiN and TaN are electrically conductive materials, compatible with CMOS (complementary metal-oxide-semiconductor) processes, mass-producible, and have significantly lower manufacturing costs than Pt. RRAM elements incorporating TiN or TaN as non-reactive electrodes may exhibit specific properties desirable for IMC applications such as multi-level switching resistance and / or analog operation. RRAM elements with non-reactive electrodes containing Pt may have superior performance compared to RRAM elements with non-reactive electrodes containing only TiN or TaN, but may be more expensive. By incorporating a metal nitride layer and a substantially thinner metal layer (e.g., a layer of Pt, Pd, Ru, Ir, etc.) than the metal nitride layer, the structures for manufacturing the non-reactive compound electrodes described herein provide a cost-effective solution for manufacturing RRAM elements with desired switching and analog resistance operation.

[0029] Compared to conventional RRAM elements using Pt-based non-reactive electrodes, the RRAM elements using the non-reactive compound electrodes described herein have lower material and process costs, are compatible with CMOS processes, and are suitable for mass production. The RRAM elements disclosed herein exhibit appropriate performance and the ability to perform multi-level switching and analog operations.

[0030] Figure 1 is a schematic diagram of an example of a crossbar circuit 100 according to an embodiment of the present disclosure. As shown, the crossbar circuit 100 may include one or more row wires 111a, 111b...111i...111n and column wires 113a, 113b...113j...113m for an n-row, m-column crossbar array. The crossbar circuit 100 may further include crosspoint elements 120a, 120b...120z, etc. Each crosspoint element may connect a row wire to a column wire. For example, crosspoint element 120ij can connect a row wire 111i to a column wire 113j. In some embodiments, the crossbar circuit 100 may further include a digital-to-analog converter (DAC, not shown), an analog-to-digital converter (ADC, not shown), a switch (not shown), and / or other suitable circuit components for implementing a crossbar-based device. The number of column wires 113a-m and row wires 111a-n may be the same or different.

[0031] The row wires 111 may include a first row wire 111a, a second row wire 111b...111i...nth row wire 111n. Each of the row wires 111a...111n is and / or contains a suitable electrically conductive material. In some embodiments, each row wire 111a-n may be a metal wire.

[0032] The row wires 113 may include a first row wire 113a, a second row wire 113b... to the mth row wire 113m. Each of the row wires 113a-m is and / or contains a suitable electrically conductive material. In some embodiments, each row wire 113a-m may be a metal wire.

[0033] Each crosspoint element 120 is and / or may include a suitable variable resistor element such as a memristor, a PCM (phase-change memory) element, a floating gate, a spintronic element, a resistive random-access memory (RRAM), or a static random-access memory (SRAM). In some embodiments, one or more crosspoint elements 120 may include an RRAM element, which is described in relation to Figures 3A to 9C.

[0034] The crossbar circuit 100 can perform parallel weighted voltage multiplication and current summation. For example, an input voltage signal can be applied to one or more rows (e.g., one or more selected rows) of the crossbar circuit 100. The input signal can flow through the crosspoint elements of the rows of the crossbar circuit 100. The conductance of the crosspoint elements can be adjusted to specific values ​​(also called "weights"). According to Ohm's law, the input voltage multiplies by the crosspoint conductance to generate a current from the crosspoint elements. According to Kirchhoff's laws, the sum of the currents passing through the elements in each column generates a current as an output signal (e.g., the output of an ADC) that can be read from the column. According to Ohm's law and Kirchhoff's current law, the input-output relationship of the crossbar array can be expressed as I=VG, where I represents the output signal matrix as current, V represents the input signal matrix as voltage, and G represents the conductance matrix of the crosspoint elements. Thus, the input signal is weighted by conductance at each crosspoint element according to Ohm's law. The weighted current is output through each column wire and can be accumulated according to Kirchhoff's current law. This enables in-memory arithmetic (IMC) by parallel multiplication and addition performed on the crossbar array.

[0035] Figure 2 is a schematic diagram of an example of a crosspoint element 200 according to an embodiment of the present disclosure. As shown, the crosspoint element 200 can connect bit lines (BL) 211, selection lines (SEL) 213, and word lines (WL) 215. The bit lines 211 and word lines 215 may be column wires and row wires, respectively, as described in relation to Figure 1.

[0036] The crosspoint element 200 may include an RRAM element 201 and a transistor 203. The transistor is a three-terminal element and may be labeled as gate (G), source (S), and drain (D). Transistor 203 may be connected in series with the RRAM element 201. As shown in Figure 2, the first electrode of the RRAM element 201 may be connected to the drain of transistor 203. The second electrode of the RRAM element 201 may be connected to the bit line 211. The source of transistor 203 may be connected to the word line 215. The gate of transistor 203 may be connected to the selection line 213. The RRAM element 201 may include one or more RRAM elements, as described in relation to Figures 3A to 9C below. The crosspoint element 200 is also called a one-transistor-one-resistor (1T1R) configuration. Transistor 203 can function as a selector and as a current controller to set current compliance to the RRAM element 201 during programming. The gate voltage of transistor 203 can set the current compliance of the crosspoint element 200 during programming, thereby controlling the conductance and analog operation of the crosspoint element 200. For example, when the crosspoint element 200 is set from a high-resistance state to a low-resistance state, a setting signal (e.g., a voltage signal, a current signal) may be supplied via the bit line (BL) 211. While the word line (WL) 215 is grounded, another voltage, also called a selection voltage or gate voltage, can be applied to the transistor gate via the selection line (SEL) 213 to open the gate and set the current compliance. When the crosspoint element 200 is reset from a low-resistance state to a high-resistance state, the gate voltage can be applied to the gate of transistor 203 via the selection line 213 to open the transistor gate. On the other hand, while the bit line 211 is set to ground, a reset signal may be sent to the RRAM element 201 via the word line 215.

[0037] Figures 3A, 3B, and 3C show cross-sectional views of RRAM elements 300a, 300b, and 300c according to some embodiments of the present disclosure. RRAM elements 300b and 300c may correspond to the low-resistance and high-resistance states of RRAM element 300a, respectively.

[0038] As shown in Figure 3A, the RRAM element 300a may include a substrate 310, a first electrode 320 formed on the substrate 310, an oxide switching layer 330, and a second electrode 340. The oxide switching layer 330 is formed between the first electrode 320 and the second electrode 340. The substrate 310 may include one or more layers of suitable materials that can function as a substrate for an RRAM element, such as silicon (Si), silicon dioxide (SiO2), silicon nitride (Si3N4), aluminum oxide (Al2O3), and aluminum nitride (AlN). In some embodiments, the substrate 310 may include diodes, transistors, interconnects, integrated circuits, etc. In some embodiments, the substrate may include a drive circuit including one or more individually controllable electrical circuits (e.g., an array of electrical circuits). In some embodiments, the drive circuit may include one or more complementary metal-oxide-semiconductor (CMOS) drivers.

[0039] The first electrode 320 is electrically conductive and may include a metal nitride that is non-reactive with the formed oxide switching layer. The metal nitride may have appropriate chemical stability so as not to react with oxygen during RRAM switching. The metal nitride may include, for example, titanium nitride (TiN) or tantalum nitride (TaN). The first electrode 320 may further include a non-reactive metal that is electrically conductive and does not react with oxygen during RRAM switching, such as platinum (Pt), palladium (Pd), iridium (Ir), or ruthenium (Ru). An RRAM element with a metal nitride and a non-reactive metal in the non-reactive electrode has multi-level resistance and analog operation desirable for IMC applications.

[0040] In some embodiments, the first electrode 320 is and / or includes a compound bottom electrode, as described in relation to Figure 4. For example, the first electrode 320 may have a metal nitride layer comprising one or more metal nitrides (e.g., TiN, TaN, etc.). The first electrode 320 may further include a metal layer comprising one or more noble metals (e.g., Pt, Pb, Ir, Ru, etc.) formed on the metal nitride layer. In some embodiments, the metal layer is thinner than the metal nitride layer.

[0041] In some embodiments, a layer of Ta and / or Ti (not shown in Figure 3C) can be formed between the first electrode and the substrate 310 to enhance adhesion between the substrate 310 and the components of the RRAM element 300a.

[0042] The oxide switching layer 330 is TaO x , HfO x , TiO x NbO x ZrO x The material may include one or more transition metal oxides, such as binary oxides, ternary oxides, and higher-order oxides. In some embodiments, the chemical stability of the non-reactive material in the first electrode 320 may be higher than that of the transition metal oxide in the oxide switching layer 330. In some embodiments, the transition metal oxide is HfO x and TaO x It includes at least one of the following, where x is used to indicate that the oxide is oxygen-deficient compared to the perfect oxide, and the value of x may vary depending on the atomic ratio of oxygen to metal in the stoichiometry of the perfect oxide. For example, HfO x For x ≤ 2.0, HfO2 is a perfect oxide, and TaO x For x ≤ 2.5, Ta2O5 is a perfect oxide.

[0043] The second electrode 340 may contain an electrically conductive metallic material that reacts with the oxide switching layer. For example, the metallic material in the second electrode 340 may include Ta, Hf, Ti, TiN, TaN, etc. The second electrode 340 may react with the oxide switching layer and may have an oxygen solubility suitable for adsorbing oxygen from the oxide switching layer 330 and creating oxygen vacancies in the oxide switching layer 330. In other words, the reactive metallic material in the second electrode 340 may have an appropriate oxygen solubility and / or oxygen mobility. In some embodiments, the second electrode 340 can not only create oxygen vacancies in the oxide switching layer 330 (for example, by capturing oxygen), but can also function as an oxygen reservoir or source to the oxide switching layer 330 during device programming.

[0044] The RRAM element 300a may have an initial resistance (also called "unused resistance") after manufacturing. The initial resistance of the RRAM element 300a can be changed, and the RRAM element 300a can be switched to a lower resistance state through the formation process. For example, an appropriate voltage or current can be applied to the RRAM element 300a. The application of voltage to the RRAM element 300a can cause the metallic material at the second electrode to absorb oxygen from the oxide switching layer 330, creating oxygen vacancies in the oxide switching layer 330. As a result, an oxygen-vacuum-rich conductive channel (e.g., a filament) can be formed within the oxide switching layer 330. For example, as shown in Figure 3B, a conductive channel 335a can be formed within the oxide switching layer 330. As shown in Figure 3B, the conductive channel 335a can be formed across the oxide switching layer 330 from the second electrode 340 to the first electrode 320. The RRAM element 300b can be reset to a high resistance state. For example, a reset signal (e.g., a voltage signal or a current signal) may be applied to the RRAM element 300b during the reset process. In some embodiments, the setting signal and the reset signal may have opposite polarities, i.e., a positive signal and a negative signal, respectively. The application of the reset signal can cause oxygen to flow back into the oxide switching layer 330 and recombine with one or more oxygen vacancies. For example, as shown in Figure 3C, a suspended conductive channel 335b may be formed in the oxide switching layer 330 during the reset process. As shown in Figure 3C, the conductive channel may be suspended with an oxide gap between the suspended conductive channel 335b and the first electrode 320. The lateral dimension of the suspended conductive channel 335b may be smaller than that of the conductive channel 335a. In some embodiments, the suspended conductive channel 335b does not continuously connect the first electrode 320 and the second electrode 340. The RRAM elements 300a-c can be electrically switched between a high-resistance state and a low-resistance state by applying an appropriate programming signal (e.g., a voltage signal, a current signal, etc.) to the RRAM element.

[0045] In one embodiment, the second electrode 340 may comprise one or more alloys. Each alloy may comprise two or more metallic elements. Each alloy may comprise a binary alloy (e.g., an alloy comprising two metallic elements), a ternary alloy (e.g., an alloy comprising three metallic elements), a quaternary alloy (e.g., an alloy comprising four metallic elements), a pentary alloy (e.g., an alloy comprising five metallic elements), a hexary alloy (e.g., an alloy comprising six metallic elements), and / or a higher-order alloy (e.g., an alloy comprising more than six metallic elements). In some embodiments, the second electrode 340 may comprise one or more alloys comprising a first metallic element and one or more second metallic elements. Each second metallic element may be less or more reactive than the first metallic element with respect to the transition metal oxide in the oxide switching layer. In some embodiments, the first metallic element may be Ta. The second metallic element may include one or more elements such as tungsten (W), hafnium (Hf), molybdenum (Mo), niobium (Nb), and zirconium (Zr). In some embodiments, the ratio of the first metallic element to the second metallic element in the alloy at the second electrode 340 may be about 50 atomic percent. In some embodiments, the appropriate ratio of the first metallic element to the second metallic element in the alloy can be optimized from the entire composition range. During the formation process, the second metallic element may generate fewer oxygen vacancies in the oxide switching layer than the first metallic element. Thus, the lateral size of the filament formed in an RRAM element having a second electrode containing the alloy may be smaller than that of the filament formed in an RRAM element having a second electrode made of only the first metal.

[0046] In some embodiments, the second electrode 340 may include multiple layers of different metallic materials. For example, the second electrode 340 may include layers of titanium (Ti) and tantalum (Ta). The Ti layer may be much thinner than the Ta layer. For example, the thickness of the Ti layer may be between approximately 0.2 nm and 5 nm. The thickness of the Ta layer may be between approximately 50 nm. In some embodiments, the thickness of the Ti layer may be between 0.3 nm and 2 nm. Both Ti and Ta can trap and release oxygen during device operation. Incorporating a thin Ti layer into the RRAM element can change the unused resistance of the RRAM element, resulting in a less abrupt formation process, reducing the formation voltage, reducing the reset current, and reducing the voltage and / or current requirements in the subsequent operation process.

[0047] Figure 4 shows a cross-sectional view of a non-reactive compound electrode 400 according to another embodiment of the present disclosure.

[0048] As shown in the figure, the non-reactive electrode 400 may include a metal nitride layer 410 and a metal layer 420. The metal layer 420 may be formed on the metal nitride layer 410. The metal nitride layer 410 may include one or more layers of one or more metal nitrides. Examples of metal nitrides include TiN and TaN. The metal layer 420 may include one or more noble metals (e.g., Pt, Pb, Ru). In some embodiments, the metal layer 420 may be thinner than the metal nitride layer 410. In some embodiments, the thickness of the metal nitride layer 410 may be between about 20 nm and about 25 nm. In some embodiments, the thickness of the metal nitride layer 410 may be between about 20 nm and about 50 nm. In some embodiments, the thickness of the metal nitride layer 410 may be between about 20 nm and about 30 nm. The thickness of the metal layer 420 may be between about 3 nm and about 10 nm. In some embodiments, the metal layer 420 may be thicker than 2-3 nm and may include a continuous film of noble metal covering the metal nitride layer 410.

[0049] Figure 5 shows a cross-sectional view of an RRAM element 500 including a compound-nonreactive electrode according to one embodiment of the present disclosure.

[0050] The RRAM element 500 may include an adhesive layer 510, a first electrode 520, an oxide switching layer 530, an interface layer A (ILA) 550, and a second electrode 540. The first electrode 520, the oxide switching layer 530, and the second electrode 540 may be the same as the first electrode 320, the oxide switching layer 330, and the second electrode 340 described in relation to Figure 3A, respectively. As shown in Figure 5, the first electrode 520 may include a metal nitride layer 410 and a metal layer 420 described in relation to Figure 4. In some embodiments, the adhesive layer 510 may be considered as part of the first electrode 520.

[0051] The adhesive layer 510 may include one or more suitable metallic materials that can enhance adhesion between the substrate and the components of the RRAM element 500. In some embodiments, the adhesive layer 510 may include one or more layers such as Ti, Ta, etc.

[0052] ILA550 (also referred to as the "first interface layer") may contain a first material that is chemically more stable than the transition metal oxide in the oxide switching layer. The first material may include, for example, Al2O3, MgO, Y2O3, La2O3, etc. ILA550 may contain discontinuous films and / or continuous films of the first material. In some embodiments, the thickness of ILA550 may be between about 0.2 nm and about 0.5 nm. In some embodiments, ILA550 may contain an Al2O3 film with a thickness of 0.5 nm or less. In some embodiments, ILA550 is and / or contains an Al2O3 film with a thickness of less than 1 nm. An RRAM element 500 having an ILA550 containing aluminum oxide may be a high-resistance, annealing-resistant RRAM element.

[0053] Figure 6 shows a cross-sectional view of an RRAM element 600 including a compound-nonreactive electrode according to a further embodiment of the present disclosure.

[0054] The RRAM element 600 may include an adhesive layer 610, a first electrode 620, an interface layer B (ILB) 660, an oxide switching layer 630, an interface layer A (ILA) 650, and a second electrode 640. The first electrode 620, the oxide switching layer 630, and the second electrode 640 may be the same as the first electrode 320, the oxide switching layer 330, and the second electrode 340 described in relation to Figure 3A, respectively. The adhesive layer 610 may be the same as the adhesive layer 510 in Figure 5. The ILA 650 may be the same as the ILA 550 in Figure 5. In some embodiments, the RRAM element 600 may further include a substrate (not shown) described in relation to Figure 3A.

[0055] ILB660 may include a second material that is chemically more stable than the transition metal oxide in the oxide switching layer 630. The second material may include, for example, Al2O3, MgO, Y2O3, La2O3, etc. ILB660 may include a discontinuous film of the second material and / or a continuous film of the second material. In some embodiments, the thickness of ILB660 may be between about 0.2 nm and about 0.5 nm. In some embodiments, ILB660 may include an Al2O3 film with a thickness of 0.5 nm or less. In some embodiments, ILB660 is and / or includes an Al2O3 film with a thickness of less than 1 nm. The RRAM element 600 comprising the first interface layer and the second interface layer may be a high-resistance, annealing-resistant RRAM element.

[0056] In some embodiments, the ILA650 may be omitted from the RRAM element 600. For example, as shown in Figure 7, the RRAM element 700 may include the adhesive layer 610, the first electrode 620, the interface layer B (ILB) 660, the oxide switching layer 630, and the second electrode 640, as described in relation to Figure 6.

[0057] Figures 8A, 8B, 8C, 8D, 8E, and 8F are schematic diagrams showing cross-sectional views of structures for forming non-reactive electrodes of an RRAM element according to the embodiments of this disclosure.

[0058] As shown in Figure 8A, a substrate 810 may be provided. The substrate 810 may include one or more layers of suitable material that can function as a substrate for manufacturing RRAM elements. For example, it may include silicon (Si), silicon dioxide (SiO2), silicon nitride (Si3N4), aluminum oxide (Al2O3), aluminum nitride (AlN), etc. In some embodiments, the substrate 810 may include diodes, transistors, interconnects, integrated circuits, etc. The substrate 810 may include a drive circuit including one or more individually controllable electrical circuits (e.g., an array of electrical circuits). In some embodiments, the drive circuit may include one or more complementary metal-oxide-semiconductor (CMOS) drivers. In some embodiments, the substrate 810 may include one or more dielectric layers, interconnect layers, transistors, and / or other suitable components (not shown) for forming a crossbar circuit. Each interconnect layer may include one or more metal pads and / or metal vias that can provide electrical connections between elements formed on the substrate 810.

[0059] As shown in Figure 8A, the substrate 810 may have an interconnection layer comprising one or more metal interconnects (e.g., metal pads and / or metal vias). For example, the first interconnection layer may have metal interconnects 811a and 811b (also referred to as the "first metal interconnect" and the "second metal interconnect"). In some embodiments, the metal interconnects 811a and 811b may be metal pads comprising tungsten (W), Al, Cu, and other suitable metals. In some embodiments, the metal interconnects 811a and 811b may be metal vias comprising aluminum (Al), copper (Cu), tungsten (W), etc. Each of the metal interconnects 811a and 811b may be connected to another element (not shown), such as a transistor or diode. In some embodiments, the metal interconnects 811a-b may comprise a tungsten (W) via and a doped polycrystalline Si (polySi) terminal, the polySi terminal may be connected to a transistor or diode terminal (not shown).

[0060] As shown in Figure 8B, the adhesive layer 821 may be formed on the metal interconnects 811a and 811b and on the substrate 810. The adhesive layer 821 may also include layers of Ta, Ti, and / or other suitable materials that can enhance adhesion between the substrate 810 and the components of the RRAM element formed on the substrate 810.

[0061] As shown in Figure 8C, the metal nitride layer 823 may be formed on the adhesive layer 821. The metal nitride layer 823 may have one or more layers of metal nitrides that are electrically conductive and non-reactive to the oxide switching of the RRAM element formed on the substrate 810. The metal nitrides may include, for example, TiN, TaN, etc.

[0062] As shown in Figure 8D, the metal layer 825 may be formed on the metal nitride layer 823. The metal layer 825 may include one or more layers of one or more suitable metals (also referred to as "non-reactive metals") that are electrically conductive and non-reactive to the oxide switching of the RRAM element formed on the substrate 810. Examples of non-reactive materials include Pt, Pd, Ir, Ru, etc.

[0063] To form one or more bottom electrodes, one or more portions of the adhesive layer 821, the metal nitride layer 823, and the metal layer 825 can be selectively removed. For example, as shown in Figure 8E, a first bottom electrode 820a and a second bottom electrode 820b can be formed on the metal interconnect 811a and metal interconnect 811b, respectively, by patterning and etching the adhesive layer 821, the metal nitride layer 823, and the metal layer 825. The first bottom electrode 820a may include a first adhesive layer 821a, a first metal nitride layer 823a, and a first metal layer 825a. The second bottom electrode 820b may include a second adhesive layer 821b, a second metal nitride layer 823b, and a second metal layer 825b. The first adhesive layer 821a and the second metal nitride layer 821b may correspond to the etched adhesive layer 821. The first metal nitride layer 823a and the second metal nitride layer 823b may correspond to an etched metal nitride layer 823. The first metal layer 825a and the second metal layer 825b may correspond to an etched metal layer 825. In some embodiments, the lateral dimensions of the bottom electrodes 820a-b may be greater than those of the metal interconnects 811a-b. The first bottom electrode 820a can directly contact the metal interconnect 811a to form an ohmic contact. The second bottom electrode 820b can directly contact the second metal interconnect 811b to form an ohmic contact. The first bottom electrode 820a and the second bottom electrode 820b may further contact one or more portions of the substrate 810, for example, one or more portions of the surface 801 of the substrate 810 (e.g., the top surface of the substrate 810).

[0064] As shown in Figure 8F, the RRAM layers 830a and 830b may be formed on the first bottom electrode 820a and the second bottom electrode 820b, respectively. Each of the RRAM layers 830a and 830b may include an oxide switching layer, a top electrode, and one or more interface layers, as described in relation to Figures 3A-7 above. In some embodiments, the RRAM layers 830a and 830b may be formed using the techniques described in U.S. Patent Applications 17 / 654,476 and 17 / 936,830, which are incorporated herein by reference.

[0065] Figure 9A is a drawing 900A showing the IV (current-voltage) characteristics of an exemplary RRAM element including a non-reactive compound electrode according to several embodiments of the present disclosure. Figure 9B shows an IV curve 900B illustrating the analog operation of the RRAM element. Figure 9C is a drawing 900C showing the element read current characteristics over time for an exemplary RRAM element.

[0066] As shown in Figure 9A, the RRAM element performs repeatable and desirable set / reset operations for multiple switches (e.g., switch 1, switch 2, and switch 3), demonstrating stability for multi-level switch operation. As shown in Figure 9B, the RRAM element performs desirable analog operation. That is, the element's resistance can be adjusted to multi-level (or analog operation) by controlling the current compliance, and in each resistance state, the current is linearly proportional to the voltage (or operates linearly). As shown in Figure 9C, Figure 900C can represent the results of an element retention force test for the RRAM element's ability to maintain its resistance level over time, and the results of a read stability test for the RRAM element's ability to maintain its resistance level over time under constant readings (at a read voltage of 0.2V). As shown in Figure 9C, the RRAM element exhibits desirable element read stability over time.

[0067] Figure 10 is a flowchart illustrating an example 1000 of a method for manufacturing an RRAM element, including the RRAM elements 500, 600, and 700 of Figures 5, 6, and 7, according to some embodiments of the present disclosure.

[0068] In block 1010, a first electrode may be formed on the substrate. Forming the first electrode may involve depositing one or more layers of a metal nitride such as TiN or TaN. For example, forming the first electrode may involve depositing one or more layers of TiN using atomic layer deposition (ALD) techniques, physical vapor deposition (PVD) techniques, reactive sputtering techniques for Ti, and / or other suitable deposition techniques. Forming the first electrode may further involve depositing one or more nonreactive metals on the metal nitride. The first electrode is and / or includes a nonreactive compound electrode as described in relation to Figure 4 above. In some embodiments, forming the first bottom electrode may involve performing one or more operations as described in relation to Figure 11 below.

[0069] In block 1020, an interface layer B (ILB) may be formed on the first electrode. The ILB is made of a material that is more chemically stable than the transition metal oxide of the oxide switching layer described later (for example, AlO2O3). x ) may include. For example, forming interface layer B may involve using atomic layer deposition (ALD) technology, physical vapor deposition (PVD) technology, reaction sputtering technology for Al, and / or other suitable deposition technology, such as AlO x This may include depositing the following. Interface layer B is and / or includes ILB660 as described in relation to Figure 6 above. In some embodiments, block 1020 may be omitted from method 1000.

[0070] In block 1030, an oxide switching layer containing one or more transition metal oxides may be formed on the interface layer B. The transition metal oxide is, for example, HfO x This may include, for example, forming an oxide switching layer using atomic layer deposition (ALD) technology, physical vapor deposition (PVD) technology, Hf reaction sputtering technology, and / or other suitable deposition technology, HfO xThis may include depositing the oxide switching layer. The oxide switching layer is and / or includes the oxide switching layer 630 described in relation to Figure 6 above.

[0071] In block 1040, interface layer A (ILA) may be formed on the oxide switching layer. The ILA is a material that is chemically more stable than the transition metal oxide of the oxide switching layer, for example, AlO2O3. x This may include, for example, forming interface layer A using atomic layer deposition (ALD) technology, physical vapor deposition (PVD) technology, reaction sputtering technology for Al, and / or other suitable deposition technology, AlO x This may include depositing the following. Interface layer A is and / or includes ILA650 as described in relation to Figure 6 above.

[0072] In block 1050, a second electrode may be formed on interface layer A. Forming the second electrode may involve forming one or more layers of one or more metallic materials that are electrically conductive and reactive to oxide switching. For example, forming the second electrode may involve depositing one or more layers of Ta using physical vapor deposition (PVD) techniques and / or other suitable deposition techniques. The second electrode is and / or includes the second electrode 640 described in relation to Figure 6 above.

[0073] Figure 11 is a flowchart illustrating an example 1100 of a method for manufacturing a non-reactive electrode, as described in relation to Figures 4 and 8A-8F, according to some embodiments of the present disclosure.

[0074] In block 1110, an adhesive layer may be formed on the substrate. Forming the adhesive layer may involve depositing a layer of metal, such as Ta or Ti, which can enhance adhesion between the substrate and the bottom electrode and / or other components of the RRAM element formed on the substrate. In some embodiments, forming the adhesive layer may involve depositing a Ti or Ta film with a thickness of about 2 nm to 5 nm. The adhesive layer may be deposited using a suitable PVD technique and / or other suitable deposition technique for depositing metal. In some embodiments, block 1110 may be omitted from method 1100.

[0075] In block 1120, a metal nitride layer may be formed on the adhesive layer. Forming the metal nitride layer may involve depositing a layer of metal nitride that is nonreactive with the transition metal oxide in the oxide switching layer formed on the bottom electrode. For example, forming the metal nitride layer may involve depositing a layer of TiN, TaN, etc., using ALD, PVD, reactive sputtering techniques, or other suitable deposition techniques.

[0076] In block 1130, a metal layer may be formed on the metal nitride layer. Forming the metal layer may involve depositing one or more non-reactive metals as described herein. In some embodiments, forming the metal layer may involve depositing Pt, Pd, Ir, Ru, etc., on the metal nitride layer using PVD technology or other suitable deposition technology. In some embodiments, forming the metal layer may involve depositing layers of Pt, Pd, Ir, Ru with a thickness of about 3 nm to about 10 nm.

[0077] In some embodiments, in block 1140, one or more portions of the adhesive layer, metal nitride layer, and metal layer can be selectively removed to form one or more bottom electrodes. For example, as described in relation to Figure 8E, the adhesive layer, metal nitride layer, and metal layer can be patterned and etched to form a first bottom electrode 820a and a second bottom electrode 820b.

[0078] For the sake of simplicity, the methods of this disclosure are described and explained as a series of actions. However, the actions according to this disclosure may be performed in various orders and / or simultaneously, and in conjunction with other actions not presented and explained herein. Furthermore, not all illustrated actions are required to implement the methods according to this disclosure. In addition, as those skilled in the art will understand and recognize, the methods may be alternatively represented as a series of interrelated states via state diagrams or events.

[0079] As used herein, “about,” “approximately,” and “substantially” may mean within the range of normal tolerances in the industry, such as within ±20% of the target dimension in some embodiments, within ±10% of the target dimension in some embodiments, within ±5% of the target dimension in some embodiments, within ±2% of the target dimension in some embodiments, within ±1% of the target dimension in some embodiments, and within ±0.1% of the target dimension in some embodiments, for example, within two standard deviations of the mean. “About” and “approximately” may include the target dimension. Unless otherwise specified or evident from the context, all numerical values ​​described herein are modified by “about.”

[0080] As used herein, a range includes all values ​​within that range. For example, the range from 1 to 10 may include any number, any combination of numbers, any subrange, and fractions thereof from the digits 1, 2, 3, 4, 5, 6, 7, 8, 9, and 10.

[0081] The above description contains numerous details. However, it is clear that this disclosure can be implemented without these specific details. In some examples, well-known structures and elements are shown in block diagram form to avoid obscuring this disclosure.

[0082] The terms "first," "second," "third," and "fourth" used herein are intended as labels to distinguish different elements and do not necessarily have an ordinal meaning according to their numerical designations.

[0083] As used herein, the terms “example” or “exemplary” are used to mean “serving as an example, case, or illustration.” Any aspect or design described herein as “example” or “exemplary” should not necessarily be construed as being preferable or advantageous to other aspects or designs. Rather, the use of the terms “example” or “exemplary” is intended to present a concept in a concrete form. As used in this application, “or” is intended to mean an inclusive “or” unless otherwise specified or it is clear from the context. That is, unless otherwise specified or it is clear from the context, “X includes A or B” is intended to be satisfied under any of the following cases: X includes A, X includes B, or X includes both A and B. In addition, as used in this application and the appended claims, the articles “a” and “an” should generally be construed as meaning “one or more” unless otherwise specified or it is clear from the context that they refer to a singular form. Throughout this specification, any reference to “embodiment” or “one embodiment” means that a particular feature, structure, or characteristic described in relation to an embodiment is included in at least one embodiment. Therefore, the appearance of the phrase “embodiment” or “one embodiment” in various places throughout this specification does not necessarily refer to the same embodiment.

[0084] As used herein, when an element or layer is referred to as being "on top of" another element or layer, that element or layer may be directly on the other element or layer, or there may be an intervening element or layer. In contrast, when an element or layer is referred to as being "directly on top of" another element or layer, there is no intervening element or layer.

[0085] Many variations and modifications of this disclosure will become apparent to those skilled in the art after reading the foregoing description. While specific embodiments are shown and described by example, it is not intended to be considered restrictive to any particular embodiment. Accordingly, references to the details of various embodiments are not intended to limit the scope of the claims to describe only those features described in the claims.

[0086] [Cross-reference of related applications] This application claims the benefits of U.S. Patent Application No. 18 / 163,272, filed on 1 February 2023, entitled “Resistive Random-Access Memory Element with Non-Reactive Compound Electrodes,” which is a continuation-in-part application of U.S. Patent Application No. 17 / 843,347, filed on 17 June 2022, entitled “Resistive Random-Access Memory Element with Metal Nitride Compound Electrodes,” both of which are incorporated herein by reference in their entirety.

Claims

1. A resistive random-access memory (RRAM) element, A first non-reactive electrode comprising a metal nitride layer containing a metal nitride and a metal layer formed on the metal nitride layer, The oxide switching layer formed on the first non-reactive electrode, A second reactive electrode comprising a metallic material that reacts with at least one transition metal oxide, Equipped with, The oxide switching layer includes the at least one transition metal oxide, The metal layer comprises a metal that is nonreactive with the at least one transition metal oxide. The second reactive electrode is configured to absorb oxygen from the oxide switching layer, generate oxygen vacancies in the oxide switching layer, and function as an oxygen reservoir for the oxide switching layer during programming of the RRAM element. RRAM element.

2. The RRAM element according to claim 1, wherein the metal nitride includes at least one of titanium nitride and tantalum nitride.

3. The RRAM element according to claim 1, wherein the metal that is nonreactive with the at least one transition metal oxide includes at least one of platinum, palladium, iridium, or ruthenium.

4. The RRAM element according to claim 3, wherein the metal layer is thinner than the metal nitride layer.

5. The RRAM element according to claim 4, wherein the thickness of the metal layer is between 3 nm and 10 nm.

6. The RRAM element according to claim 5, wherein the thickness of the metal nitride layer is between 20 nm and 50 nm.

7. The at least one transition metal oxide is HfO ｘ and TaO ｙ Including at least one of the following, The RRAM element according to claim 1, wherein x ≤ 2.0 and y ≤ 2.

5.

8. The RRAM element according to claim 1, wherein the conductive material of the second reactive electrode includes tantalum.

9. The interface layer is located between the oxide switching layer and the second reactive electrode, The interface layer comprises aluminum oxide, as described in claim 1, for the RRAM element.

10. The adhesive layer further comprises at least one of titanium and tantalum, The metal nitride layer is formed on the adhesive layer, and the RRAM element is as described in claim 1.

11. A method for manufacturing a resistive random access memory (RRAM) element, To form a first non-reactive electrode comprising a metal nitride layer containing a metal nitride and a metal layer formed on the metal nitride layer, Forming an oxide switching layer on the first non-reactive electrode, A second reactive electrode comprising a metallic material that reacts with at least one transition metal oxide is formed on the oxide switching layer, Equipped with, The oxide switching layer comprises the at least one transition metal oxide, The metal layer comprises a metal that is nonreactive with the at least one transition metal oxide. The second reactive electrode is configured to absorb oxygen from the oxide switching layer, generate oxygen vacancies in the oxide switching layer, and function as an oxygen reservoir for the oxide switching layer during programming of the RRAM element. method.

12. The method according to claim 11, wherein the metal nitride comprises at least one of titanium nitride and tantalum nitride.

13. The method according to claim 12, wherein the metal that is nonreactive with the at least one transition metal oxide includes at least one of platinum, palladium, iridium, and ruthenium.

14. The method according to claim 13, wherein the metal layer is thinner than the metal nitride layer.

15. The method according to claim 14, wherein the thickness of the metal layer is between 3 nm and 10 nm.

16. The method according to claim 15, wherein the thickness of the metal nitride layer is between 20 nm and 50 nm.

17. The at least one transition metal oxide is HfO ｘ and TaO ｙ Including at least one of the following, The method according to claim 11, wherein x ≤ 2.0 and y ≤ 2.

5.

18. The further comprising forming an interface layer on the oxide switching layer, The interface layer is located between the oxide switching layer and the second reactive electrode. The method according to claim 11, wherein the interface layer comprises aluminum oxide.

19. The method further comprises forming an adhesive layer containing at least one of titanium and tantalum. The metal nitride layer is formed on the adhesive layer, according to the method of claim 11.

20. A method for manufacturing an RRAM element, which includes forming a non-reactive electrode, wherein forming the non-reactive electrode is Forming an adhesive layer containing at least one of titanium and tantalum, Forming a metal nitride layer containing at least one metal nitride on the adhesive layer, Forming a metal layer containing a precious metal on the metal nitride layer, The non-reactive electrode is formed by selectively removing one or more portions of the adhesive layer, the metal nitride layer, and the metal layer. Forming an oxide switching layer containing at least one transition metal oxide on the non-reactive electrode, Forming a reactive electrode on the oxide switching layer, Equipped with, The metal nitride includes at least one of titanium nitride and tantalum nitride. The reactive electrode reacts with the at least one transition metal oxide. method.

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