Surface-emitting laser, method for manufacturing a surface-emitting laser

Abstract

The vertical-cavity surface-emitting laser includes an oxide substrate having a first surface and a second surface opposite to the first surface, a semiconductor portion disposed on the first surface, an AR layer disposed between the semiconductor portion and the first surface, a first DBR mirror, and a second DBR mirror disposed on the curved surface of the second surface. The first DBR mirror, the semiconductor portion, the AR layer, the oxide substrate, and the second DBR mirror are arranged in the first axial direction to form an extended resonator. The semiconductor portion is disposed between the AR layer and the first DBR mirror and includes a p-type group III nitride region, a group III nitride region, and a group III nitride active region between the p-type and n-type group III nitride regions.

Description

Technical Field

[0001] The present invention relates to a group III nitride vertical cavity surface emitting laser (VCSEL) with an extended resonator and a method for manufacturing a group III nitride VCSEL with an extended resonator.

Background Art

[0002] A surface emitting laser is known as a vertical cavity surface emitting laser (VCSEL). The VCSEL includes a semiconductor active region disposed between an n-side semiconductor region and a p-side semiconductor region, and two distributed Bragg reflectors called DBRs that function as high-reflection mirrors. The semiconductor active region, also known as the gain medium, is disposed between the two DBRs such that the two DBRs and the semiconductor active region form an optical resonator. The n-side and p-side regions inject respective carriers, i.e., electrons and holes, into the active region, and these carriers recombine within the active region to generate light. The light or electromagnetic radiation thus generated is reflected multiple times by the DBRs and travels within the optical resonator, leading to laser oscillation. One of the DBRs included in the VCSEL is a mirror with a low reflectivity and is used to emit a laser beam.

[0003] Gallium nitride (GaN) VCSELs have recently received increasing research attention due to their ability to emit light in the visible and ultraviolet (UV) regions. This opens up various new application spaces in solid-state lighting, including displays, automotive lighting, and residential lighting, as well as in transmission and communication. One particularly exciting application is when a blue-emitting GaN VCSEL can be combined with a phosphor to function simultaneously as both a natural light source and a data transmission device. This application will enable all new AR / VR uses, smartphones, and ordinary displays to be treated in a new dimension by adding a communication function to each light-emitting pixel.

[0004] This application, as shown throughout this specification, refers to numerous patent or non-patent publications by reference numbers in parentheses, i.e., []. A list of these publications, arranged according to these reference numbers, can be found below in sections titled [Non-Patent Literature] or [Patent Literature].

[0005] [List of citations] [Non-patent literature] [NPL1] Appl.Phys.Express Vol. 12, 044004 (2019) [NPL2] Sci.Rep. Vol. 8, pp. 10350 (2018) [NPL3] Applied Phys. Lett. vol. 83, p. 2121 (2003) [NPL4] Appl.Phys.Express 2008, Vol. 1, 121102 [NPL5] Appl.Phys.Express 2012, Vol. 5, 092104 [NPL6] Optics Express, Volume 27, Page 24717 (2019) [NPL7] Appl.Phys.Express, Volume 13, 041003 (2020) [NPL8] Appl.Phys.Express, Volume 14, 031002 (2021) [NPL9] Applied Phys. Lett. Vol. 119, pp. 142103 (2021) [NPL10] Crystals, Volume 11, Issue 12, 1563 (2021) [NPL11] "Dry etching for coherent refractive index microlens arrays" by MBStern and TRJay, Op.Eng. Vol. 33, pp. 3547-3551 (1994). [Overview of the project] [Problems that the invention aims to solve]

[0006] VCSEL optical resonators defined by two planar DBR mirrors suffer from excessive diffraction losses as the resonator length increases. Using curved mirrors provided for long optical resonator VCSELs, the curved lenses refocus the electromagnetic field into the gain medium, thereby reducing diffraction losses originating from the long resonator length [NPL1~NPL2]. Until 2022, Sony's long resonator design held performance records of 15.8 mW CW output, a threshold current of 0.25 mA, and a wall-plug efficiency (WPE) of 9.5%. High-efficiency VCSEL operation can be achieved by tuning the resonator modes to match the gain spectrum. Curved mirrors are necessary because they prevent diffraction and scattering losses that would otherwise occur in long GaN resonators. Since diffraction losses also increase with increasing resonator length, and the typical gain of a GaN quantum well is about 1%, excessive diffraction and scattering losses due to defects in long resonators and interfaces can rapidly degrade the device performance of GaN resonators longer than 10 micrometers. For very short resonator lengths, for example, with a thickness of one or two optical wavelengths, matching the gain spectrum and modes is extremely difficult due to large mode separation, thus reducing the device yield and laser oscillation efficiency. As the resonator length increases, the mode spacing decreases, increasing the probability of the resonator modes and gain spectrum overlapping, thus enabling a higher yield for the laser oscillation device.

[0007] However, in long resonators, achieving transparency of all VCSEL device layers except the active region to propagating electromagnetic radiation is a challenging task. While this structure of VCSELs does not impose extremely stringent requirements for substrate removal, moderate losses are introduced by the remaining host substrate. Nevertheless, in all reported literature, the curved DBR mirror is formed either on the back surface of the native group III nitride substrate or on the p-side of the device. The curved mirror techniques proposed in references [NPL1] and [NPL2] still utilize a significant portion of the native host substrate, even after employing polishing and etching lens structures on the semiconductor host substrate to create the curved n-side DBR mirror. While this is a good technique, it is designed for homoepitaxy of device layers containing Ga, N, In, and Al alloys. Furthermore, the doping level of the host substrate used in long resonators should be kept low to suppress absorption losses. Therefore, first, the thickness of the host substrate is reduced to decrease absorption losses within the resonator. Thinning the substrate can be a difficult process to control, and since the substrate must be thinned from an initial thickness of 300-400 micrometers to a target thickness of 10-30 micrometers to accommodate the resonator in the VCSEL, there is a risk of damaging the wafer. Otherwise, unintended absorption losses are added with each round trip of electromagnetic radiation, reducing the laser oscillation probability. Alternatively, researchers at [NPL3] demonstrated the operation of GaN VCSELs in an extended resonator scheme by directly growing the device structure on a low-absorption sapphire substrate. However, such methods still impose limitations on crystal quality due to a significant lattice mismatch between the device layer and the sapphire substrate. Therefore, the lifetime and yield of such devices become problematic.

[0008] It is preferable to keep the absorption source as thin as possible while maintaining stable laser operation. Ideally, the bottom mirror should be positioned so that the top and bottom mirrors are positioned close together to form a resonator, enabling the formation of an optical resonator that ultimately results in the removal of the native substrate. In the case of VCSEL device layers grown on heterosubstrates such as sapphire or Si, Group III nitride VCSEL devices can be readily removed by laser lift-off (LLO) [NPL4] or chemical etching. However, GaN heteroepitaxy on sapphire has limitations in crystal quality. Conventional LLO processes are not suitable for GaN homoepitaxy. Alternatively, the removal of Group III nitride device layers from GaN homoepitaxy has been reported [NPL5] and remains a very interesting topic [NPL6~NPL10].

[0009] The longer the resonator, the better the stability in terms of laser oscillation and thermal drift. Alternatively, VCSEL designs with extended resonators can be realized by carefully removing the VCSEL device layer from the native growth substrate or heterosubstrate and then re-depositing a lossless transparent oxide (TO) material such as Al2O3, ZnO, and Ga2O3. However, sub-nanometer surface preparation must be achieved on both the substrate to which the TO is deposited and the removed device layer. However, at the GaN / oxide interface during re-deposition, refractive index differences can lead to undesirable reflections. If these reflections result in detrimental device performance, an anti-reflective coating can be added to the interface to suppress the undesirable reflections. All of these procedures are time-consuming and present further problems in addition to the additional cost.

[0010] Taking all these drawbacks into consideration, the objective is to provide a structure for a group III nitride-based VCSEL and a method for manufacturing a group III nitride-based VCSEL having the characteristics of an extended resonator. Another objective is to provide a single-step integrated solution for achieving an extended resonator without involving complex bonding procedures that involve the removal of the TO substrate and / or the substrate from the outside. [Means for solving the problem]

[0011] One configuration of the present disclosure is a VCSEL, the VCSEL comprising: an oxide substrate having a first surface and a second surface including a curved surface opposite to the first surface; a semiconductor portion disposed on the first surface of the oxide substrate; a lossless anti-reflective (AR) layer disposed between the semiconductor portion and the first surface of the oxide substrate; a first DBR mirror disposed between the semiconductor portion and a first distributed Bragg reflector (DBR) mirror; and a second DBR mirror disposed on the curved surface of the oxide substrate, wherein the first DBR mirror, the semiconductor portion, the AR layer, the oxide substrate, and the second DBR mirror are arranged in a first axial direction to form an extended resonator, the semiconductor portion comprising a p-type group III nitride region, a group III nitride region, and a group III nitride active region between the p-type group III nitride region and the group III nitride region, the p-type group III nitride region, the group III nitride active region, and the group III nitride region are arranged in a first axial direction, and the group III nitride region includes an n-type group III nitride region.

[0012] Another configuration of the present disclosure is a method for manufacturing a VCSEL, the method comprising providing a starting base comprising an oxide base, a group III nitride template plug, and a lossless anti-reflective (AR) layer, wherein the oxide base has a first surface and a second surface opposite to the first surface of the oxide base, and the AR layer and the group III nitride template plug are located on the first surface of the oxide base, Growing a group III nitride region from a group III nitride template plug on an AR layer, growing a semiconductor laminate including an n-type group III nitride region, a group III nitride active region, and a p-type group III nitride region after growing the group III nitride region, processing an oxide-based second surface to form an oxide substrate having a curved surface disposed on the opposite side of the first surface of the oxide substrate, forming a first distributed Bragg reflector (DBR) laminate on the first surface of the oxide substrate after growing the semiconductor laminate, and forming a second DBR laminate on the curved surface of the oxide substrate.

Advantages of the Invention

[0013] The above configuration can provide a structure of a group III VCSEL having characteristics of an extended resonator and a method for manufacturing a VCSEL having characteristics of an extended resonator.

Brief Description of the Drawings

[0014] [Figure 1] FIG. 1 is a schematic cross-sectional view showing a VCSEL having a thick TO block according to an embodiment of the present disclosure. [Figure 2A] FIG. 2A is a cross-sectional view taken along line I-I shown in FIG. 2B, showing a VCSEL with an extended resonator according to the present embodiment of the present disclosure. [Figure 2B] FIG. 2B is a schematic top view showing a VCSEL according to the present embodiment of the present disclosure. [Figure 3] FIG. 3 is a cross-sectional view taken along line I-I shown in FIG. 2B, showing a VCSEL with an extended resonator according to the present embodiment of the present disclosure. [Figure 4A] FIG. 4A is a schematic view showing a template including a TO substrate. [Figure 4B] FIG. 4B is a schematic view showing an etched template plug on a TO substrate. [Figure 4C] FIG. 4C is a schematic view showing an AR layer covering the TO substrate except for the template plug. [Figure 4D]FIG. 4D is a top view showing a striped pattern of the template plug. [Figure 5A] FIG. 5A is a schematic cross-sectional view taken along line II-II shown in FIG. 5B, showing a VCSEL of an extended resonator having a tunnel junction as a current diffusion layer according to a second embodiment of the present disclosure. [Figure 5B] FIG. 5B is a schematic top view showing a VCSEL according to a second embodiment of the present disclosure. [Figure 6A] FIG. 6A is a schematic cross-sectional view taken along line III-III shown in FIG. 5B, showing a VCSEL of an extended resonator having an embedded tunnel junction as a current diffusion layer according to a third embodiment of the present disclosure. [Figure 6B] FIG. 6B is a schematic top view showing a VCSEL according to a third embodiment of the present disclosure. [Figure 7A] FIG. 7A is a schematic cross-sectional view showing a base layer grown using an ELO process on a stripe-shaped object. [Figure 7B] FIG. 7B is a schematic cross-sectional view showing a base layer grown using an ELO process on a stripe-shaped object. [Figure 8] FIG. 8 is a schematic cross-sectional view showing a semiconductor device layer on a polished pallet. [Figure 9] FIG. 9 is a schematic diagram showing main step 1 in a method for manufacturing a VCSEL according to the present embodiment. [Figure 10] FIG. 10 is a schematic diagram showing main step 2 in a method for manufacturing a VCSEL according to the present embodiment. [Figure 11] 0]FIG. 11 is a schematic diagram showing main step 3 in a method for manufacturing a VCSEL according to the present embodiment. [Figure 12] FIG. 12 is a schematic diagram showing main step 4 in a method for manufacturing a VCSEL according to the present embodiment. [Figure 13] FIG. 13 is a schematic diagram showing main step 5 in a method for manufacturing a VCSEL according to the present embodiment. [Figure 14] FIG. 14 is a schematic diagram showing main step 6 in a method for manufacturing a VCSEL according to the present embodiment. [Figure 15] Figure 15 is a schematic diagram showing the main step 7 in the method for manufacturing VCSELs according to this embodiment. [Figure 16] Figure 16 is a schematic diagram showing the main step 8 in the method for manufacturing VCSELs according to this embodiment. [Figure 17] Figure 17 is a schematic diagram showing the main step 9 in the method for manufacturing VCSELs according to this embodiment. [Figure 18] Figure 18 is a schematic diagram showing the main step 10 in the method for manufacturing VCSELs according to this embodiment. [Figure 19] Figure 19 is a schematic diagram showing the main step 11 in the method for manufacturing VCSELs according to this embodiment. [Figure 20] Figure 20 is a schematic diagram showing the main step 12 in the method for manufacturing VCSELs according to this embodiment. [Figure 21A] Figure 21A is a schematic cross-sectional view along the xy line shown in Figure 21B, showing the main step 13 in the method for manufacturing VCSELs according to this embodiment. [Figure 21B] Figure 21B is a schematic top view showing a VCSEL according to the present embodiment of this disclosure. [Figure 22A] Figure 22 is a schematic cross-sectional view along the xy line shown in Figure 22B, showing the main step 14 in the method for manufacturing VCSELs according to this embodiment. [Figure 22B] Figure 22B is a schematic top view showing a VCSEL according to the present embodiment of this disclosure. [Figure 23A] Figure 23A is a schematic cross-sectional view along the xy line shown in Figure 23B, showing the main step 15 in the method for manufacturing VCSELs according to this embodiment. [Figure 23B] Figure 23B is a schematic top view showing a VCSEL according to the present embodiment of this disclosure. [Figure 24] Figure 24 is a schematic diagram showing the main step 16 in the method for manufacturing VCSELs according to this embodiment. [Figure 25] Figure 25 is a schematic diagram showing the main step 17 in the method for manufacturing VCSELs according to this embodiment. [Figure 26] Figure 26 is a schematic diagram showing the main steps 18 in the method for manufacturing VCSELs according to this embodiment. [Figure 27] Figure 27 is a top view showing the triangular grid pattern of the template plug. [Figure 28] Figure 28 is a top view showing the triangular grid pattern of the template plug with guide marks. [Figure 29] Figure 29 is a top view showing the ELO device palette on an AR mask without guiding marks. [Figure 30A] Figure 30A is a top view showing the ELO device palette on an AR mask with guiding marks. [Figure 30B] Figure 30B is a magnified view of the guideline markers in Figure 30A. [Figure 30C] Figure 30C is a schematic diagram of the growth mechanism of a hexagonal pyramid. [Figure 30D] Figure 30D is a schematic diagram of the growth mechanism for obtaining a pallet. [Figure 31A] Figure 31A shows an HCP VCSEL on a layer derived from a single template plug. [Figure 31B] Figure 31B shows the traces of the HCP VCSEL and laser beam on a layer originating from a single template plug. [Figure 32A] Figure 32A shows the fabrication of a circular lens using a single triangular lattice group III nitride plug. [Figure 32B] Figure 32B shows the fabrication of a circular lens using a single triangular lattice group III nitride plug. [Figure 32C] Figure 32C shows the fabrication of a circular lens using a single triangular lattice group III nitride plug. [Figure 32D] Figure 32D shows the fabrication of a circular lens using a single triangular lattice group III nitride plug. [Figure 33] Figure 33 shows an HCP VCSEL on a layer derived from a single template plug. [Figure 34]Figure 34 shows the traces of the HCP VCSEL and laser beam on a layer originating from a single template plug. [Figure 35A] Figure 35A shows the fabrication of a circular lens using a single triangular lattice group III nitride plug. [Figure 35B] Figure 35B shows the fabrication of a circular lens using a single triangular lattice group III nitride plug. [Figure 35C] Figure 35C shows the fabrication of a circular lens using a single triangular lattice group III nitride plug. [Figure 35D] Figure 35D shows the fabrication of a circular lens using a single triangular lattice group III nitride plug. [Figure 36] Figure 36 is a schematic diagram of the separation method used for the manufactured VCSEL, which employs laser stealth. [Figure 37] Figure 37 is a schematic diagram of the separation method used for the fabricated VCSEL, which employs cleavage. [Figure 38A] Figure 38A is a magnified view of the guideline markers in Figure 37. [Figure 38B] Figure 38B is a schematic diagram of the separation method used for the fabricated VCSEL, which employs cleavage. [Figure 38C] Figure 38C is a schematic diagram of the separation method used for the fabricated VCSEL, which employs cleavage. [Figure 38D] Figure 38D is a schematic diagram of the separation method used for the fabricated VCSEL, which employs cleavage. [Figure 39] Figure 39 is a top view of a VCSEL (Voltage-Covered Cellular Spectroscopy) that forms a group III nitride island in a single step by epitaxial lateral overgrowth from a group III nitride template plug. [Figure 40A] Figure 40A is a schematic cross-sectional view along the line IV-IV shown in Figure 40B, showing the main step 14 in the manufacturing method of VCSEL according to the fourth embodiment. [Figure 40B] Figure 40B is a schematic top view showing the VCSEL in step 14 according to the fourth embodiment of this disclosure. [Figure 41]Figure 41 is a schematic top view showing the VCSEL in step 15 according to the fourth embodiment of this disclosure. [Figure 42A] Figure 42A is a schematic top view showing the HCP VCSEL of the block. [Figure 42B] Figure 42B is a schematic diagram showing the HCP VCSEL of the block. [Figure 43] Figure 43 is a schematic diagram illustrating the photon recycling phenomenon. [Modes for carrying out the invention]

[0015] The teachings of the present invention can be easily understood by considering the following detailed description with reference to the accompanying drawings shown as examples. A schematic of the vertical-cavity surface-emitting laser (VCSEL) and the method for manufacturing the VCSEL according to the present disclosure is described below with reference to the accompanying drawings. For ease of understanding, the same reference numerals are used to indicate the same elements common to the figures, where possible.

[0016] One embodiment of the present invention relates to the placement of a curved mirror on a TO material. An AR layer is inserted between the planar mirror and the curved mirror resonator of the VCSEL. By using a curved mirror, the refocusing of electromagnetic radiation into the gain medium (by nearly 90%) enables the use of longer resonator devices with lower diffraction losses. By using a lossless transparent oxide (TO) material containing ZnO, Ga2O3, or Al2O3 for most of the resonator, implementation with a curved mirror is possible, as absorption is almost negligible. The present invention enables the realization of VCSEL devices with very long resonators and better thermal performance.

[0017] Figure 1 is a simplified schematic diagram showing an extended resonator VCSEL according to this embodiment. The VCSEL 11 comprises a curved distributed Bragg reflector (DBR) 41 (bottom mirror) on a TO material integrated into the design in a single step, and a semiconductor section 15 having a planar DBR (top mirror) 13. The curved DBR 41 is formed on the oxide substrate 10 of the monolithically integrated extended resonator via an AR layer 17. The AR layer 17 functions as a complete propagator of electromagnetic radiation and as a mounting element for the oxide substrate 10, and also functions as a support for the formation of the group III nitride alloy layer, the semiconductor section 15. The semiconductor section VCSEL formed by the ELO layer includes a p-type group III nitride region 23, a group III nitride region 25 including an n-type group III nitride region, and a group III nitride active region 27 between the p-type group III nitride region 23 and the n-type group III nitride region of the group III nitride region 25.

[0018] Figure 2A shows an enlarged view of the device layer cross-section with a fixed submount, and Figure 2B is a top view of the device that identifies the electrode arrangement. Figure 3 also represents other possible device configurations.

[0019] The semiconductor portion 15 grows laterally from the exposed (ht) sidewall region and top surface of the group III nitride template plug 18.

[0020] The template plug 18 connects the TO substrate 10 and the semiconductor section 15. Therefore, the template plug 18 functions as a thermal path for the VCSEL device during operation. By utilizing a TO substrate material with better thermal conductivity and enabling the transfer of thermal energy to the TO material via the template plug 18, the proposed VCSEL device can have better thermal properties. The crystal orientation of the group III nitride template plug 18 is c-plane, semipolar, or nonpolar.

[0021] Preferably, the AR layer 17, made entirely of dielectric material, can be used as a support structure for the semiconductor portion 15 that grows laterally from the group III nitride template plug 18. By laminating the AR layer 17 before the growth of the semiconductor portion 15, a single-step integration of a very thin semiconductor portion 15 onto the TO substrate 10 is achieved without substrate removal and bonding. The AR layer 17 is a single structure and provides a transparent window to the resonant light wavelength. The surface roughness of the AR layer 17 is less than 1 nm. Preferably, the AR layer 17 is a single layer that allows the electromagnetic radiation of interest to be directed into the resonator and onto the TO substrate, or 17 may be a multilayer structure.

[0022] The AR layer 17 has through holes extending in the first axial direction Ax1, and the group III nitride template plug 18 is placed inside the through holes and extends from the first surface of the oxide substrate 10 to the semiconductor portion 15 within the through holes. The curved surface of the oxide substrate 10 has a center line, and the group III nitride template plug 18 and the center line of the curved surface are offset from each other.

[0023] The VCSEL11 comprises a DBR13 and a semiconductor portion 15 formed on an AR layer 17. The DBR13 includes a first dielectric layer and a second dielectric layer arranged alternately in the first axial direction AX1, wherein the material of the first layer is different from that of the second layer. The semiconductor portion 15 includes a p-type group III nitride region 23, a group III nitride region 25 including an n-type group III nitride region, and a group III nitride active region 27 between the p-type group III nitride region 23 and the n-type group III nitride region of the group III nitride region 25. The p-type group III nitride region 23, the group III nitride active region 27, and the n-type group III nitride region of the group III nitride region 25 are arranged in the first axial direction Ax1. The semiconductor portion 15 and the DBR13 are arranged in the first axial direction Ax1 to form an optical resonator 29. A group III nitride active region 27 is grown to form a quantum well structure configured to generate light having wavelengths of the first reflection spectrum of the first DBR13 and the second reflection spectrum of the second DBR41.

[0024] The VCSEL 11 further includes an anode electrode 31 and a conductive layer 35. The conductive layer 35 connects the anode electrode 31 and the p-type group III nitride region 23. The conductive layer 35 may include either a group III nitride semiconductor such as p-type GaN, or a conductive inorganic material such as indium tin oxide (ITO), or both. Modifications of the conductive layer will be described later. In one example, the DBR 13 may be in contact with the conductive layer. If necessary, the semiconductor portion 15 may further include a tunnel junction disposed between the p-type group III nitride region 23 and the conductive layer 35 having n-type conductivity. The VCSEL 11 is constructed without using a group III nitride material on the oxide substrate 10 side of the AR layer 17.

[0025] In a VCSEL 11 having a mesa 37 in the semiconductor portion 15, the mesa 37 includes a p-type group III nitride region 23, a group III nitride active region 27, and a portion of the n-type group III nitride region of the group III nitride region 25. The mesa 37 is located above the remainder of the n-type group III nitride region of the group III nitride region 25, and at the bottom of the mesa 37, the mesa 37 is surrounded by an n-type group III nitride surface 25a extending along the length of the tip of the group III nitride region 25. The cathode electrode 33 may be positioned on the n-type group III nitride surface 25a of the group III nitride region 25 along its length by opening one section. A material omnidirectional reflector 40 for reflecting the resonant wavelength toward the resonator is positioned as a passivation layer between the cathode electrode 33 and the anode electrode 31. The VCSEL 11 has a cathode electrode 33. The cathode electrode 33 is electrically connected to the n-type group III nitride region of the group III nitride region. As shown in Figure 2B, the cathode electrode 33 is in contact with the n-type group III nitride region of the group III nitride region at the longitudinal front of the ELO layer.

[0026] The total resonator length L can be defined as the distance between the curved TO substrate material 41a and the plane of the conductive layer 35 before the DBR 13 is placed. CAVThe VCSEL 11 has the following characteristics: If the semiconductor portion 15 is approximately 0.5 to 4 micrometers, the VCSEL 11 can use a TO substrate 10 of 50 to 1000 micrometers as an extended resonator 29. The length of the extended resonator 29 exceeds 50 micrometers.

[0027] The semiconductor portion 15 has a conductive opening 39a and a non-conductive portion 39b surrounding the conductive opening 39a. The conductive opening 39a provides an electrical path to the VCSEL 11 from the anode electrode 31 to the cathode electrode 33. Carriers such as electrons and holes flow through the electrical path and recombine within the group III nitride active region 27 to generate light, which is emitted from one side of the DBR 13.

[0028] The conductive aperture 39a is positioned asymmetrically away from the template plug 18 to minimize overlap between the reflected electromagnetic radiation between the resonator mirrors and the template plug 18. Furthermore, the resonator length can be increased simply by utilizing a thicker TO substrate 10, thereby adjusting the beam propagation path so that the beam contour avoids any interaction with the template plug 18. The asymmetric design also helps to accommodate both the anode electrode 31 and the cathode electrode 33 on the semiconductor surface. Moreover, such an asymmetric design avoids defect or irregular regions near the template plug 18 that may result from etching or short-range crystal defects that may occur near the template plug. Preferably, when positioning the conductive aperture region 39a, approximately 3 micrometers from the sidewall of the template plug 18 should be avoided. The VCSEL block is coated on its outer surface with an anti-reflective material to capture leaked photons.

[0029] Figure 3 illustrates a modified example in which the curved mirror axis completely avoids any overlap with the template plug 18. When the standard growth pattern of the Group III nitride layer is used, a hexagonal close-packed (HCP) design can be used to obtain maximum benefit. HCP VCSELs are a new design concept for increasing packaging density. In this case, the multiple semiconductor parts 15 are formed by utilizing the growth of an HCP close-packed hexagonal design, and the curved surfaces are multiple curved surfaces arranged corresponding to the multiple semiconductor parts 15.

[0030] An exemplary manufacturing method according to this embodiment will be schematically described with reference to Figures 4A, 4B, 4C, and 4D. First, an oxide substrate 10 containing a group III nitride template 51 is prepared as a starting base. Next, selective etching is performed to obtain template plugs 18 having a width w and a height h on the oxide material substrate 10. Depending on the design described later, the template plugs 18 may be placed close to each other on the oxide substrate 10 or separated from each other. Several designs are shown in Figures 4D and 27.

[0031] The process of preparing a starting base includes depositing a group III nitride layer on a first surface of an oxide base 10, patterning the group III nitride layer to form a group III nitride template plug 18, depositing a plurality of dielectric layers covering the first surface of the oxide base 10 and the group III nitride template plug 18, and processing the plurality of layers to form the AR layer 17 such that the group III nitride template plug 18 is located within the through-holes of the AR layer 17 and the group III nitride template plug 18 has a height greater than the thickness of the AR layer 17.

[0032] Figure 4C shows the AR layer 17 partially embedding the template plugs 18. As described, the template plugs 18 may be in the form of individual stripes as shown in Figure 4D, or they may be circular spots less than 5 microns in diameter arranged in a two-dimensional triangular grid as shown in Figure 27.

[0033] An exemplary manufacturing method for realizing the VCSEL11 having ITO as a current diffusion layer, as described in Figures 3A and 3B, includes the following steps.

[0034] 1. Prepare a template plug 18 on the TO material substrate. 2. The AR layer 17 is placed over the entire TO material substrate, partially exposing the side walls of the template plug 18 and completely exposing the top surface. 3. The unintentionally doped n-GaN layer is grown from the exposed area of ​​the template plug 18. Growth is stopped after the total width of the layer, including the template plug 18, reaches approximately 30-200 microns. 4. Flattening is performed. 5. The following device layers are sequentially grown on the planarized n-GaN layer: n-GaN for cladding and n-contacts, InGaN multiple quantum wells, AlGaN electron blocking layer, p-GaN, and p++GaN. 6. Next, the back surface of the TO substrate material is polished, and the microlens pattern is transferred by registry flow and reactive ion etching. 7. Next, an aperture is defined on the surface of the device layer using a lens function from the back side. 8. Next, ion implantation is performed to define the opening. 9. After cleaning the surface, deposit a transparent conductive oxide such as ITO (Total Carbon Oxide). 10. Define mesa 37 for separating the electrodes. 11. Passivate the contact area with ODR material. 12. A dielectric distributed Bragg reflector 13 is deposited on the flat portion of the device layer. 13. Open up the areas for anode and cathode electrode deposition. 14. Deposit the electrode metal pads. 15. A dielectric distributed Bragg reflection mirror 41 is deposited on the curved portion of the TO substrate material. 16. Place the bonding material on the back of the device. 17. Separate the VCSEL chips into individual pieces. 18. Connect to the submount. 19. Used as a light source, sensor, or both for user-defined purposes.

[0035] Figure 5A is a schematic diagram showing a VCSEL according to a second embodiment of the present disclosure. Figure 5B is a schematic top view showing a VCSEL.

[0036] An exemplary manufacturing method for realizing the VCSEL61 having a tunnel junction as a current diffusion layer, as shown in Figure 5A, includes the following steps.

[0037] 1. Prepare a template plug 18 on the TO material substrate. 2. The AR layer 17 is placed over the entire TO material substrate, partially exposing the side walls of the template plug 18 and completely exposing the top surface. 3. The unintentionally doped n-GaN layer is grown from the exposed region of the template step. Growth is stopped after achieving a total layer width of approximately 30-200 microns, including the template plug 18. 4. Flattening is performed. 5. The following device layers are sequentially grown on the planarized n-GaN layer: n-GaN for cladding and n-contacts, InGaN multiple quantum wells, AlGaN electron blocking layer, p-GaN, and p++GaN. 6. Next, the back surface of the TO substrate material is polished, and the microlens pattern is transferred by registry flow and reactive ion etching. 7. Next, an aperture is defined on the surface of the device layer using a lens function from the back side. 8. Next, ion implantation is performed to define the opening. 9. After cleaning the surface, n++GaN is regrowthed to complete the tunnel junction. 10. Deposit n-GaN for contact and current diffusion. 11. Define mesa 37 for separating the electrodes. 12. Passivate the contact area with ODR material. 13. A dielectric distributed Bragg reflector 13 is deposited on the flat portion of the device layer. 14. Open up the areas for anode and cathode electrode deposition. 15. Deposit the electrode metal pads. 16. A dielectric distributed Bragg reflection mirror 41 is deposited on the curved portion of the TO substrate material. 17. Place the bonding material on the back of the device. 18. Separate the VCSEL chips into individual pieces. 19. Connect to the submount. 20. Used as a light source, sensor, or both for user-defined purposes.

[0038] Figure 6A is a schematic diagram showing a VCSEL according to a third embodiment of the present disclosure. Figure 6B is a schematic top view showing a VCSEL.

[0039] An exemplary manufacturing method for realizing the VCSEL71 with an embedded tunnel joint as an opening, as shown in Figure 6A, includes the following steps.

[0040] 1. Prepare a template plug 18 on the TO material substrate. 2. The AR layer 17 is placed over the entire TO material substrate, partially exposing the side walls of the template plug 18 and completely exposing the top surface. 3. The unintentionally doped n-GaN layer is grown from the exposed area of ​​the template plug 18. Growth is stopped after the total width of the layer, including the template plug 18, is reached to approximately 30-50 microns. 4. Flattening is performed. 5. The following device layers are sequentially grown on the planarized n-GaN layer: n-GaN for cladding and n-contacts, InGaN multiple quantum wells, AlGaN electron blocking layer, p-GaN, and p++GaN and n++GaN. 6. Next, the back surface of the TO substrate material is polished, and the microlens pattern is transferred by registry flow and reactive ion etching. 7. Next, an aperture is defined on the surface of the device layer using a lens function from the back side. 8. Next, define the aperture mask, etch n++, and expose the underlying p-GaN in p++GaN. 9. After cleaning the surface, n-GaN is regrown for contact and current diffusion to form an embedded tunnel junction. 10. Define mesa 37 for separating the electrodes. 11. Passivate the contact area with ODR material. 12. A dielectric distributed Bragg reflector 13 is deposited on the flat portion of the device layer. 13. Open up the areas for anode and cathode electrode deposition. 14. Deposit the electrode metal pads. 15. A dielectric distributed Bragg reflection mirror 41 is deposited on the curved portion of the TO substrate material. 16. Place the bonding material on the back of the device. 17. Separate the VCSEL chips into individual pieces. 18. Connect to the submount. 19. Used as a light source, sensor, or both for user-defined purposes.

[0041] Figure 7A is a schematic diagram of a group III nitride epitaxial layer, preferably an epitaxially deposited n-type doped GaN layer 25. The group III nitride regions grow from the group III nitride template plug 18 by epitaxial lateral overgrowth, forming group III nitride islands. The group III nitride islands extend outward from the group III nitride template plug 18 along the upper surface of the AR layer 17, and the roughness of the upper surface of the AR layer 17 is less than 1 nanometer.

[0042] In the following description, the group III nitride may be deposited, for example, by metal-organic vapor deposition (MOCVD). The group III nitride n-GaN layer 25 extends outward from the template plug 18. Depending on the packing density of the growth surface, group III nitride atoms may accumulate more at the edges of the group III nitride layer compared to the central portion of the layer 25. This may be seen as edge growth 26, which can be detrimental if it continues during the growth of the VCSEL device layer. In Figure 7B, the group III nitride layer deposited in this manner is polished to obtain a flatter surface and adjust the resonator length of the VCSEL. The figure shows the base layer after polishing in the case of HCP.

[0043] After planarization of the group III nitride layer 25b, a semiconductor region 15 is grown, including a group III nitride region 25c, a group III nitride active region 27, and a p-type group III nitride region 23, as shown in Figure 8. The nitride region 25 may contain a GaN-based or AlN-based material doped with an n-type dopant to enable electron supply to the group III nitride active region 27, and the p-type group III nitride region 23 may contain a GaN-based or AlN-based material doped with a p-type dopant to enable hole supply to the group III nitride active region 27. The group III nitride active region 27 may contain a GaN-based or AlN-based material such as GaN, InGaN, AlN, or AlGaN. The group III nitride active region 27 may be given as a single layer or as a quantum well structure such as a single quantum well (SQW) or multiple quantum wells (MQW). If necessary, an embedded tunnel junction or tunnel junction layer must be grown after the deposition of the p-type group III nitride region 23.

[0044] Figure 9 shows step 1 for manufacturing the VCSEL. Figure 10 shows step 2 for manufacturing the VCSEL. Figure 11 shows step 3 for manufacturing the VCSEL. In steps 1-3, microlenses are fabricated at predetermined locations on the polished TO substrate material surface, and their positions are aligned so that the focal point of the lens helps to process the current confinement aperture of the VCSEL. The microlenses are fabricated using thermal reflow technology [NPL11]. A photoresist microdisk 45a is patterned on the TO material by standard photolithography in step 1, then formed into a lenticular shape 45b on a high-temperature hot plate in step 2, and the lens is transferred to the TO substrate material 45c by reactive ion etching of a sacrificial photoresist mask in step 3. The lens fabrication for the HCP VCSEL was similar to that for the striped VCSEL, but the lens construction was described as either a discontinuous number as shown in Figures 32A, 32B, 32C, and 32D, or a continuous ring as shown in Figures 35A, 35B, 35C, and 35D.

[0045] Figure 12 shows step 4 for manufacturing VCSELs. Figure 13 shows step 5 for manufacturing VCSELs. Figure 14 shows step 6 for manufacturing VCSELs. Figure 15 shows step 7 for manufacturing VCSELs.

[0046] Steps 4 to 7 describe the process of precisely defining the conductive aperture region using a molded lens on the TO substrate material on the back side. Step 4 shows a blanket-deposited photoresist covering the device layer. Step 5 exposes the TO substrate material through the back side, at which point the pre-formed lens focuses the light to the edge of the semiconductor portion 15 as designed. As a result, the photosensitive material affected by the photoreaction dissolves during the development stage, leaving an aperture in the resist (step 6). Step 7 shows a deposited mask within the patterned region. This patterned mask 46 may be used as a protective mask during the fabrication of the aperture region 39a and the insulating region 39b, or it may be used to etch only the p++GaN and n++GaN layers in the buried tunnel junction design. The protective mask may be Ti / Au, a dielectric, or a photoresist. Alternatively, the aperture definition process may be performed from the top surface without using a lens on the TO substrate, in which case the lens can be fabricated in the final stage of device manufacturing. After step 7, if the VCSEL design includes an embedded tunnel junction or tunnel junction as a current diffusion layer, regrowth is performed.

[0047] Figure 16 shows step 8 for manufacturing a VCSEL. In step 8, a mask 46, such as a resist or a metal protective mask, is formed on the semiconductor portion 15 to generate a semiconductor aperture region 39a from the semiconductor portion 15. The aperture structure of the semiconductor portion 15 is generated by injecting ions such as hydrogen atoms, n-type dopant atoms, and / or p-type dopant atoms into the semiconductor laminate 15 having the mask 46. The aperture structure comprises a semiconductor aperture region 39a extending in the first axial direction Ax1 and an insulating region 39b surrounding the semiconductor aperture region 39a. The first DBR mirror 13, the aperture region 39a, and the second DBR mirror 41 are arranged along the axis, and the aperture structure is at least 3 micrometers away from the group III nitride template plug 18.

[0048] Figure 17 shows step 9 for manufacturing a VCSEL. After removing the mask 46, a conductive layer 35 covering the semiconductor aperture region 39a and the insulating region 39b is deposited on the aperture structure as shown in step 9. The conductive layer 35 may include a highly doped group III nitride semiconductor layer such as GaN or AlGaN, and / or an inorganic layer such as indium tin oxide (ITO). The conductive layer is positioned so as to coincide with the minimum value (node) of electromagnetic radiation in order to avoid absorption of light generated from the group III nitride active region 27.

[0049] Figure 18 shows step 10 for manufacturing VCSELs. Figure 19 shows step 11 for manufacturing VCSELs. Figure 20 shows step 12 for manufacturing VCSELs. Figure 21A shows step 13 for manufacturing VCSELs. Figure 21B is a schematic top view showing the VCSEL in step 13.

[0050] Steps 10 to 16 describe the manufacturing of the VCSEL, where a photoresist material is deposited to define the mesa 37, as shown in step 10. The mesa 37 is a rectangular photoresist section covering the opening and approximately 50% of the chip surface, although in the case of HCP, it is a circular section. Next, step 11 selectively etches the semiconductor portion 15 to expose the n-GaN region beneath the group III nitride layer 25a. Then, in step 12, an omnidirectional reflector, ODR, 40 is placed, where the ODR 40 functions to reflect the operating wavelength of the VCSEL back into the resonator and also functions as a passivation layer between the anode electrode 31 and the cathode electrode 33 to help avoid short circuits. Subsequently, in step 13, a lift-off is performed, leaving the ODR covering the entire etched sidewall and the exposed group III nitride n-GaN 25a.

[0051] Figure 22A shows step 14 for manufacturing a VCSEL. Figure 22B is a schematic top view showing the VCSEL in step 14. As shown in step 14, a distributed Bragg reflector (DBR) 13 is formed on the conductive layer 35. Specifically, a first dielectric layer and a second dielectric layer are deposited alternately to form an arrangement of these dielectric layers.

[0052] Figure 23A shows step 15 for manufacturing a VCSEL. Figure 23B is a schematic top view showing the VCSEL in step 15. As shown in step 15, mask openings for resist applications are formed on the conductive layer 35 and on the etched group III nitride n-GaN region 25a covered with ODR. Next, as shown in Figure 23B, the ODR 40 is etched to expose the underlying n-GaN surface 25a. Then, the anode electrode 31 on the conductive layer 35 and the cathode electrode 33 on the other side of the chip length are formed for electroinjection.

[0053] Figure 24 shows step 16 for manufacturing the VCSEL. Figure 25 shows step 17 for manufacturing the VCSEL. Figure 26 shows step 18 for manufacturing the VCSEL. In step 16, a second DBR mirror 41 is formed on the curved surface of the TO substrate material. In step 17, bonding material 42 is placed in the selected area to enable the bonding of the submount. As shown in step 18, the product VCSEL is bonded to the submount on the curved DBR side using solder bumps.

[0054] Figure 27 is a schematic diagram showing a VCSEL according to a fourth embodiment of the present disclosure. Figure 27 shows an AR layer 27 partially embedding a template plug 18. As described, the template plug 18 may be circular spots less than 5 microns in diameter arranged in a two-dimensional triangular grid as shown in Figure 27. The distance between spots in the triangular grid is adjusted to a desired dimension. Alternatively, the spots may be arranged in variations of the spot design, such as adding guideline markers 52 in dielectric material without interfering with the chip dimensions, as shown in Figure 28. The guideline markers 52 can be of any shape; for example, the vertices of a triangular guide marker 52 may apply pressure along the cleavable planes of the group III nitride region to separate each chip as needed.

[0055] Figures 29 and 30A illustrate the initial Group III nitride base growth of HCP with and without guide markers. Figure 30B is a magnified view of the guide marker 52 in Figure 30A. For example, c-plane growth of a GaN layer on an oxide substrate 10 by the MOCVD process results in the formation of a hexagonal pyramidal shape under a wide variety of growth conditions, as illustrated in Figure 30C. The angle between the (0001) plane and the side face is approximately 62 degrees, and it is a semipolar {1-101} type plane. The growth rate of the (0001) plane is relatively fast compared to the {1-101} plane, and it is thought that the (0001) plane disappears as a result. However, with appropriate parameter optimization, the growth rate of the (0001) plane can be slowed down, and a suitable chip area can be obtained as illustrated in Figure 30C, or Figure 30D can be obtained by polishing the pyramidal Group III nitride layer in Figure 30C. The growth rate of the (0001) plane is relatively higher than that of the {1-101} plane, and therefore the (0001) plane disappears but exists in equilibrium. The growth rate of the planes varies under different growth conditions, and optimized growth parameters may be used to reach Figure 30B, or polishing may be used, not limited to this.

[0056] When the guideline marker 52 is positioned, the group III nitride semiconductor region is formed on top of the guide mark 52, which is a piece added to the desired position on the AR layer 17. An enlarged view of the ELO group III nitride semiconductor layer covering the guideline marker 52 is shown in Figure 30B.

[0057] Figures 31A and 31B show a preferred design of the HCP VCSEL type. The p-pad was located on the side of the template plug 18, while the n-pad was on the other side. The light-emitting aperture was positioned between the p-pad and the n-pad. After growing all the device layers necessary for VCSEL fabrication, six lens structures were fabricated on the back surface of the oxide substrate 10 using the transparency of the oxide and group III nitride regions. Precise alignment between the light injection and radiation focusing lenses is possible when the lenses are fabricated first and then the current aperture is defined using the same lenses.

[0058] Figures 32A, 32B, 32C, and 32D illustrate the process of forming six lenses in a concentric ring using PR material. Lens fabrication by photolithography and registry flow has long been used to produce lens arrays. First, photoresist, PR, is spin-coated onto a substrate, soft-baked, and exposed as usual, as shown in Figure 32B. After development, the photoresist cylinder remains. The resist cylinder is then placed on a hot plate set to a temperature higher than the glass transition temperature, thereby rapidly transitioning the polymer resist from its amorphous rubber state to a glassy state system. Surface tension minimizes the surface area by rearranging the liquid clusters inside the cylinder / droplet.

[0059] Ideally, the resist is completely melted, the mass is freely transported, and the surface tension forms a spherical microlens. The lens shape is then transferred onto the substrate by dry etching using reactive ion etching or any other method, as shown in Figure 32C. The lens transferred onto the substrate is then used in a procedure to form a current aperture by focusing lithographic light through the back surface of the lens, as shown in Figure 32D. One such example is given in Figures 32A, 32B, 32C, and 32D.

[0060] The descriptions of Figures 33, 34, 35A, 35B, 35C, and 35D are the same as those for Figures 31A, 31B, 32A, 32B, 32C, and 32D. Instead of discontinuous apertures, continuous ring-shaped emission can be achieved. The aperture structure is a continuous ring-shaped aperture structure concentrically around the triangular grid-arranged Group III nitride template plugs 18. In this design, the lens on the back of the oxide substrate resembles a donut-shaped ring. As described above, after the PR pattern was formed in a donut shape by photolithography, thermal reflow was used. The concentric donut lens structure on the oxide substrate 10 is then reused to form a ring-shaped emission aperture on the Group III nitride semiconductor device region. Where current injection is present, the emission can be as a ring as described in Figure 34. Circular ring emission can be designed by this particular design. Because this chip design utilizes the entire HCP chip, one common p-pad and a common n-pad are placed on both sides of the light-emitting region.

[0061] HCP design is superior in yield improvement, especially compared to HCP type 1, which separates them into individual chips. Guide marks 52 may be placed in the early stages of the ELO process. The resulting design pattern looks like that shown in Figure 36 (without guide marks) and Figure 37 with guide marks 52. Figure 38A is a magnified view of guide marks 52 in Figure 37.

[0062] In Figure 36, where no guide markers were used, the growth of the ELO layer was stopped before it coalesced with the adjacent layer. The gap between them is preferably about 10 micrometers. Here, a laser stealth process may be utilized to separate them into blocks of VCSELs containing HCP structures. Each HCP is a combination of at least six VCSELs. Stealth laser dicing ("stealth dicing process") allows for precise focusing of the laser to cut the VCSELs into blocks.<URL:https: / / www.disco.co.jp / eg / solution / library / laser / stealth.html> This process street width, with a minimum of 10 microns, can be used in the desired configuration to easily separate the die / block from the wafer.

[0063] Figures 38B, 38C, and 38D show designs for separating individual VCSEL chips from the HCP structure. In this case, the device layers extend their corners over guide marks 52. Due to local elevation differences around the guideline markers, the device layers show a slight bulge at the guiding marks 52. Alternatively, this height variation may be minimized during a polishing process after the growth of the base group III nitride layer. The guideline markers 52 apply pressure to the cleavage plane of the group III nitride semiconductor device. Figures 38B, 38C, and 38D schematically show the separation process. In this case, the separation of individual blocks can be performed by a laser stealth process, and the fabrication of individual VCSEL chips can be performed by cleavage.

[0064] For cleavage, after removing the guide marking material, downward pressure is applied to the device surface from above. When downward pressure is applied to a strained Group III nitride device, the Group III nitride layer cleaves along the cleavage plane. Alternatively, even if height variations are leveled during polishing, downward pressure can still cleave the Group III nitride layer along the cleavage plane. Once individual chips are separated using the downward pressure method, a laser stealth process is applied to separate the VCSEL into blocks.

[0065] Multiple aperture structures are arranged concentrically around a triangular grid-like arrangement of group III nitride template plugs 18, with each aperture structure being a single chip.

[0066] The process for manufacturing a VCSEL processed by HCP design is the same as the process for manufacturing a VCSEL in which the template plug 18 is striped. However, Figures 39, 40A, 40B, and 41 show the process for manufacturing a VCSEL processed by HCP design. Figure 39 is a top view of a VCSEL formed by growing a group III nitride island in a single step by epitaxial lateral overgrowth from a group III nitride template plug 18. Figure 40A shows step 14 for manufacturing the VCSEL. Figure 40B shows a top view of the VCSEL in step 14. Figure 41 shows a top view of the VCSEL in step 15 for manufacturing the VCSEL.

[0067] High-density VCSELs processed with HCP design can be seen in Figure 42A. Dozens or hundreds of VCSELs can be cut as thick blocks using cleavage, or cleavage plus laser stealth, or laser stealth alone. Currently, CMOS technology is very advantageous and has reached the sub-micrometer boundary. Adding CMOS technology to the highly packed VCSEL technology of the present invention, as shown in Figure 42B, would be useful for a variety of applications, including displays, automotive headlights, projection, and augmented and virtual reality. The emission from the VCSELs can be controlled by changing the reflectivity of the DBR mirror, and in this particular case shown in Figure 42B, the bottom light was emitted from the curved DBR mirror by controlling its reflectivity. Figure 43 shows an overview of a VCSEL that utilizes photon recycling. When considering photon recycling, a VCSEL block containing two or more VCSELs is cut using a laser stealth process, and the sides of the block are coated with AR or ODR material to block photon leakage from the sides. The photons circulate internally within the block and are used in one of the VCSEL's resonators.

[0068] Definition:

[0069] Transparent oxide (TO) substrate materials: The lens shape is formed within a transparent oxide (TO) substrate material. The same material is used for growing the device layer. Substrate materials such as ZnO, Ga2O3, and Al2O3 can be used. This allows the VCSEL resonator to be primarily composed of TO substrates with low absorption. TO substrate materials such as sapphire may be available in larger sizes; that is, manufacturing beyond 6 inches in this procedure yields higher yields from a single run.

[0070] Template Plug: We begin with a TO material substrate having a Group III nitride template. The template thickness can be between 1 and 10 microns. The crystal quality of the template improves with increasing thickness. Through-dislocations generated at the substrate interface due to lattice mismatch are terminated as the thickness increases. Furthermore, greater thicknesses may allow for the use of thicker AR layer structures.

[0071] Starting with a flat template on the TO material substrate, selective etching is performed in a direction on the TO substrate to promote lateral growth. For example, stripes parallel to the <11-20> axis within the group III nitride layer. By etching the (0001) polar group III nitride template film to expose the (11-22) sidewalls, lateral growth from such sidewalls can be promoted. Alternatively, the template steps can be shaped arbitrarily under conditions that promote the growth of the group III nitride layer along the filter.

[0072] Epitaxial lateral overgrowth: TO substrate material having a Group III nitride template is formed in the form of stripes or HCPs, and the template plug 18 is partially embedded in an AR filter structure made entirely of a dielectric material such as SiO2, Ta2O5, or HfO5, with the sidewalls of the template plug 18 being partially embedded in the AR filter structure, while the top surface is left open. Preferably, the thickness of the template is designed to accommodate a thicker AR layer to achieve better quality of the overgrown Group III nitride ELO layer. The stripes may be longer or cut to match the length of the device. When a polar template is used, the stripes are oriented along the <11-20> axis, and when a non-polar template is used, the stripes are <0001> The stripes are oriented along the axis. When a semipolar (20-21) or (20-2-1) template is used, the stripes are oriented parallel to [-1014] or [10-14], respectively. Other faces with stripes oriented in other directions may also be used. In HCP patterns, the pattern may be a circle or small hexagon whose sides coincide with the ELO growth of the C-face group III nitride layer.

[0073] A TO substrate material including the sidewalls of a partially exposed template step is placed in MOCVD to grow a group III nitride layer. In one embodiment, the growth pressure is in the range of 50 to 760 Torr, but to widen the island-like group III nitride semiconductor layer, the growth pressure is preferably in the range of 100 to 300 Torr. The growth temperature is 900 to 1200°C. The V / III ratio is in the range of 10 to 30000. TMG is 2 to 20 sccm. NH3 is in the range of 0.1 to 10 slm. The carrier gas is hydrogen gas only, or both hydrogen gas and nitrogen gas. To obtain a smooth surface, the growth conditions for the group III nitride layer are optimized. Finally, the group III nitride ELO GaN layer 25 is stopped when it reaches a thickness of about 1 to 10 μm and a width of about 50 μm, with each wing extending to about 15 micrometers.

[0074] TO substrate materials, including growth regions (exposed template steps) and non-growth regions (AR layers), can be characterized by their fill factor. A substrate surface without the above characteristics corresponds to a fill factor of 1 for a flat growth process. When the fill factor deviates from 1, it is likely that more group III nitride atoms accumulate at the edges of the layer due to the abundance of group III nitride atoms at the growth and non-growth interfaces, resulting in a thicker GaN layer at the edges of group III nitride islands compared to the central region, called edge growth 26.

[0075] Polishing: Edge growth increases with a very small fill factor due to excess carrier gas and metal-organic materials. Group III nitride island layers tend to approach a concave shape. Edge growth is often problematic when initially growing a Group III nitride base layer of about 5-10 micrometers thickness from the template step. Planarization of the surface is recommended before growing any further device layers, including p-GaN, n-GaN, and InGaN and AlGaN layers. Planarization of the device at this stage also helps control the thickness of the resonator. Since device layers containing n-GaN, MQW, p-GaN, and tunnel junction layers all together will not exceed about 700 nm during regrowth after polishing, edge growth will be largely negligible as a result.

[0076] Device layer growth: Group III nitride semiconductor layers, tunnel junctions, and embedded tunnel junctions The laminate of the semiconductor portion 15, which is composed of a group III nitride semiconductor device layer, may contain In, Al and / or B, as well as other impurities such as Mg, Si, Zn, O, C, and H. A Group III nitride semiconductor device layer generally comprises three or more layers, including at least one of the following: an n-type layer, an undoped layer, and a p-type layer. Specifically, a Group III nitride semiconductor device layer includes GaN layers, AlGaN layers, AlGaInN layers, InGaN layers, etc. For example, after polishing a Group III nitride GaN layer 25, epitaxial growth of the device layer is performed by MOCVD. The active region includes 2xMQW (3nm wells and 7nm barrier), a 10nm p-AlGaN electron blocking layer (EBL), a 100nm p-GaN, and a 10nm p++GaN.

[0077] When ITO is used as the current diffusion layer, device layer growth should terminate at p++GaN. Otherwise, an additional 10nm thick n++GaN layer must be deposited on top of the p++GaN for embedded tunnel junctions. For embedded tunnel junctions and tunnel junctions, a current-accelerating layer of approximately 50nm n-GaN is deposited during regrowth.

[0078] In the tunnel junction design, growth was paused at p++GaN and then continued after ion implantation, whereas in the case of the embedded tunnel junction, growth was stopped after adding a 10 nm thick layer of n++GaN on top of the p++GaN. Re-growth can be performed by either MOCVD or MBE (molecular beam epitaxy). MBE was used instead of MOCVD to eliminate hydrogen repassivation of p-GaN during tunnel junction regrowth.

[0079] Alternatively, the present design, as described in one embodiment, processes discrete or island-like group III nitride device layers. Therefore, even if the p-GaN layer is embedded in a tunnel junction layer or a current diffusion layer (n-GaN), activation of the p-GaN can be achieved by lateral diffusion. Thus, a particular discrete device layer design provides the flexibility to select MBE or MOCVD depending on manufacturability parameters such as cost and yield.

[0080] Microlens formation: The VCSEL aperture fabrication procedures described in these embodiments can utilize the curved lens effect that functions as a second DBR mirror in the VCSEL product. The TO substrate material may also be a double-sided polished substrate, and as a result, the microlens pattern on the back surface is positioned such that the resulting lens shape helps to precisely align the aperture at the edge of the semiconductor portion later. Photoresist (PR) reflow and dry etching methods are used to fabricate microlenses. For example, a 2-inch wafer with a double-sided polished sapphire substrate (0001) orientation may be used. Alternatively, a wafer with a larger diameter may be used. An array of circular PR disks is patterned on the back surface of a polished sapphire substrate using standard photolithography techniques. The PR pattern is then baked at a high temperature on a hot plate. After reaching the transition temperature, the PR pattern begins to flow, forming a convex shape with the thickest point at the center of each pattern. Subsequent pattern transfer to the sapphire substrate can be performed using an inductively coupled plasma (ICP) apparatus. Optimized etching conditions can achieve a surface roughness of less than a nanometer. Preferably, the etched surface on the sapphire should have a surface roughness of 0.1 nm to 0.5 nm to avoid wavelength scattering and associated losses.

[0081] Ion implantation: Ion implantation is used to create electrical and optical openings in the GaN-based layer by damaging the GaN-based layer outside the opening, so that the damaged GaN-based material is no longer conductive. This method can keep the surface flat and give a very slight mark indicating the boundary between the opening region and the damaged region. However, the damaged region may result in increased optical loss within the resonator and tends to have a higher absorption value than the unimplanted material in the opening region. Heavy ions such as aluminum (Al) and boron (B) may be used in the ion implantation procedure. The basic purpose of ion implantation is to form conductive openings. After ion implantation, a transparent conductive layer, as defined later, may be laminated onto the device layer, or regrowth may be performed on the device layer, whether or not implantation is performed compared to the case of a tunnel junction.

[0082] Transparent conductive layer: ITO can be used as a commonly used transparent current diffusion layer. While incorporating ITO into VCSELs may result in additional absorption, this can be reduced by lowering the electromagnetic wave intensity around the ITO layer. Alternatively, alternative methods such as tunnel junctions may be used to diffuse the current and reduce optical absorption.

[0083] Tunnel junction: Tunnel junctions enable hole injection into the p-side of a device through an n-type semiconductor. This is achieved by using a junction between a highly doped n-type region and a highly doped p-type region under reverse bias, allowing electrons to tunnel from the valence band of the p-type region to the conduction band of the n-type region. Since the tunneling probability depends exponentially on the tunneling distance, a highly doped region (approximately 10⁻¹⁰) is used to generate a thin depletion width for efficient operation. 19 (More than / cc) is preferable. If device layer growth stops after p++GaN, ion implantation is performed using the lens effect from the processed curved back surface of the TO substrate material. The sample is then reintroduced for epitaxial growth of the current diffusion layer. Preferably, an n++ / n-GaN layer with a thickness of 10 / 50 nm is epitaxially regrowthed.

[0084] Embedded tunnel junction: In embedded tunnel junction devices, the highly doped region is restricted to the aperture of the VCSEL device so that current flows through the highly doped region. If low doping is used elsewhere to embed the junction, most of the current flow is restricted to the aperture until the junction breakdown voltage is reached. This is achieved by growing a flat tunnel (p++ / n++ / 10nm / 10nm) and then etching the highly doped junction layer at the desired aperture location using a lens made of TO substrate material. Next, regrowth is performed to embed the etched highly doped layer by epitaxial growth of a thick current-diffusing n-GaN layer. Alternatively, ion implantation may also be performed before regrowing the current-diffusing material to embed the tunnel junction.

[0085] DBR mirror: A DBR mirror includes interjointed and alternating dielectric layers that form a reflective mirror on top of the VCSEL's resonator. For example, a combination of quarter-wavelength thick layers of SiO2 / Ta2O5 dielectric may be used as a dielectric DBR mirror. To promote luminescence, the number of pairs on the p-side of the device must be less than the number on the curved side (n-side).

[0086] Omnidirectional reflector (ODR): Omnidirectional reflectors are similar to dielectric mirrors, but less precise than DBR mirrors. ODRs are designed to reflect light that has leaked from the propagation path back into the resonator. ODRs may also be used to protect or passivate the anode and cathode electrodes from direct contact.

[0087] Metal pads: Metals such as gold (Au), aluminum (Al), nickel (Ni), palladium (Pd), titanium (Ti), and indium (In) are used as materials for metal pads at various stages of VCSEL manufacturing. Some combinations can be used as protective masks, and some can be used for galvanic injection. The metal layer can be formed by sputtering, vapor deposition, or plating.

[0088] Purpose

[0089] illumination: GaN-based LEDs have brought about a dramatic transformation in residential and automotive lighting. Lighting combined with communication services is highly anticipated in future smart cities and smart infrastructure. VCSELs are a better alternative to LEDs and end-face emitting laser diodes. However, the lack of suitable, profitable mass production technology has prevented GaN VCSELs from entering the market. The procedure developed in the above embodiment can be used to mass-produce VCSEL units applicable to lighting applications.

[0090] Visible light communication: Laser light with the potential for data transfer and communication applications through Light Fidelity (LiFi). With the rapid increase in IoT devices, the demand for data transmission continues to expand. The RF spectrum is becoming saturated, and new frequencies are needed to keep up with the continuously increasing demand. Incorporating GaN VCSELs into existing LED configurations is simpler than replacing them with end-emitting lasers. Therefore, the devices described in the embodiments above can serve their purpose.

[0091] Near-eye display: Near-eye displays represent the next big wave in consumer electronics. These are key components of virtual reality (VR) and augmented reality (AR) technologies. While microLEDs are currently the primary display choice, VCSELs will undoubtedly be introduced as miniature and near-eye displays, despite limited progress in VCSEL research. Relatively low light power is beneficial in maintaining eye safety. Low divergence and circular symmetry reduce the need for additional optical elements, thereby resulting in compactness. The characteristics of 2D array integration of VCSELs are simpler than those of edge-emitting lasers. Therefore, VCSEL products manufactured using this invention can be applied to these applications.

[0092] advantage

[0093] A sufficiently long resonator without excessive diffraction loss can be used in conjunction with two reflective mirrors that define the VCSEL resonator. Thermal management can be improved by placing contacts on a sufficiently long resonator and / or nitride layer. The GaN template plug included in the device connects to a TO substrate material with better thermal conductivity, thereby improving thermal performance. Inexpensive, large template substrates such as GaN on sapphire can be used. By using island-like growth of group III nitrides, waste of semiconductor layers can be minimized. This eliminates the need for additional substrate removal and bonding procedures, thus improving manufacturing limitations. High-quality, large-format GaN substrates are extremely expensive. This ELO technology can enable the use of heterogeneous substrates in the manufacturing of VCSELs. This invention is expected to result in significant performance improvements, reduced manufacturing costs, and the elimination of complex procedures. This invention proposes the use of AR layer integration in VCSELs to enable epitaxial lateral overgrowth for improving the quality of the crystalline layer.

[0094] Using a template TO material substrate such as GaN / sapphire, the high-crystal-quality layer possible in this invention generally uses a device layer on an epitaxial lateral overgrowth wing that is defect-free or has few defects. An interface is created between the semiconductor region and the TO substrate to reduce scattering, and the VCSEL chip is cut into thick blocks, enabling efficient photon recycling. The sidewalls of the thick blocks of TO substrate may be AR coated to capture phonons scattered from the TO substrate-AR layer interface. These scattered photons are used somewhere in the VCSEL block to induce laser oscillation. This advantage is schematically shown in Figure 43.

[0095] A curved mirror is formed on a transparent oxide (TO) substrate, and the semiconductor portion is provided on the AR layer of an extended resonator made of TO material. Therefore, since the curved mirror can focus light, diffraction loss can be reduced. The AR layer functions as a bonding material between the TO substrate and the semiconductor portion, and also as a mask layer for ELO growth. A curved mirror refocuses all electromagnetic radiation into the gain region of the device.

[0096] Template plugs help grow semiconductor layers on the AR layer. This feature is important for several reasons. Firstly, in extended resonator designs, light passing through the AR layer to the TO substrate should not go to the semiconductor layer (Group III nitride layer) because it increases absorption. Secondly, it is for thermal improvement and defect reduction. When growth of polar c-plane group III nitride semiconductor portions is desired, hexagonal growth yields effective results. Most c-plane substrates are available in large sizes exceeding 2 inches and are desirable due to their low cost. Furthermore, this feature increases chip density and thus improves yield.

[0097] Appearance 1 VCSEL is an oxide substrate having a first surface and a second surface including a curved surface opposite to the first surface. A semiconductor portion, arranged on the first surface of the oxide substrate. A lossless anti-reflective (AR) layer is disposed between the semiconductor portion and the first surface of the oxide substrate. The semiconductor portion is positioned between the AR layer and the first distributed Bragg reflector (DBR) mirror, and the first DBR mirror, It comprises a second DBR mirror positioned on the curved surface of an oxide substrate, The first DBR mirror, semiconductor portion, AR layer, oxide substrate, and second DBR mirror are arranged in the first axial direction to form an expanded resonator. The semiconductor region includes a p-type group III nitride region, a group III nitride region, and a group III nitride active region between the p-type group III nitride region and the group III nitride region, the p-type group III nitride region, the group III nitride active region, and the group III nitride region are arranged in the first axial direction, and the group III nitride region includes an n-type group III nitride region.

[0098] Appearance 2 In the VCSEL described in Embodiment 1, the semiconductor portion and the oxide substrate are connected via a group III nitride template plug.

[0099] Appearance 3 The VCSEL according to claim 1, wherein the VCSEL is constructed without using a group III nitride material on the oxide substrate side of the AR layer.

[0100] Pattern 4 In the VCSEL described in any one of Embodiments 1 to 3, the surface roughness of the AR layer is less than 1 nm.

[0101] Appearance 5 In the VCSEL described in Embodiment 2, the AR layer has through holes extending in the first axial direction, The Group III nitride template plug is placed within the through-hole and extends from the first surface of the oxide substrate to the semiconductor portion within the through-hole.

[0102] Appearance 6 In the VCSEL described in Embodiment 2, the Group III nitride template plug facilitates the regrowth of the high-crystal-quality semiconductor device layer on the AR layer.

[0103] Appearance 7 In the VCSEL described in Embodiment 2, the group III nitride template plug is composed of a triangular lattice or an arrangement of regular strips.

[0104] Appearance 8 In the VCSEL described in Embodiment 2, the semiconductor portion has an aperture structure, the aperture structure includes an aperture region extending in a first axial direction and an insulating region surrounding the aperture region, the first DBR mirror, the aperture region and the second DBR mirror are arranged along the axis, and the aperture structure is located at least 3 micrometers away from the group III nitride template plug.

[0105] Appearance 9 In the VCSEL described in Embodiment 2, the curved surface of the oxide substrate has a center line, and the group III nitride template plug and the center line of the curved surface do not coincide in position with each other.

[0106] Appearance 10 In the VCSEL described in any one of embodiments 1 to 9, a plurality of semiconductor parts are formed by growth according to a hexagonal close-packed (HCP) design, and the curved surface consists of a plurality of curved surfaces arranged to correspond to the plurality of semiconductor parts.

[0107] Appearance 11 In the VCSEL described in Embodiment 8, the multiple aperture structures are concentric around a triangular grid-like arrangement of Group III nitride template plugs, and each aperture structure contains a single chip.

[0108] Appearance 12 In the VCSEL described in Embodiment 8, the opening structure is a continuous ring-shaped opening structure that forms concentric circles around the triangular grid-like arrangement of Group III nitride template plugs.

[0109] Appearance 13 In the VCSEL described in any one of embodiments 1 to 12, the guide marks are included in the AR layer.

[0110] Appearance 14 In the VCSEL described in embodiment 13, the VCSEL chip is fragmented by cleavage assisted by guide marks.

[0111] Appearance 15 In the VCSEL described in any one of embodiments 1 to 14, the VCSEL is separated into blocks by a laser stealth process.

[0112] Appearance 16 In the VCSEL described in any one of embodiments 1 to 15, the length of the extended resonator exceeds 50 micrometers.

[0113] Appearance 17 In the VCSEL described in any one of Embodiments 1 to 3, the oxide substrate includes one of ZnO, SiO2, Ga2O3, Al2O3, and Ta2O5.

[0114] Appearance 18 In the VCSEL described in any one of embodiments 1 to 13, the crystal orientation of the group III nitride template plug of the VCSEL is c-plane, semipolar, or nonpolar.

[0115] Appearance 20 A method for manufacturing a VCSEL includes: preparing a starting base comprising an oxide base, a group III nitride template plug, and a lossless anti-reflective (AR) layer, wherein the oxide base has a first surface and a second surface opposite to the first surface of the oxide base, and the AR layer and the group III nitride template plug are located on the first surface of the oxide base; growing a group III nitride region from the group III nitride template plug on the AR layer; growing a semiconductor laminate after growing the group III nitride region, comprising an n-type group III nitride region, a group III nitride active region, and a p-type group III nitride region; processing the second surface of the oxide base to form an oxide substrate having a curved surface located opposite to the first surface of the oxide substrate; forming a first distributed Bragg reflector (DBR) laminate on the first surface of the oxide substrate after growing the semiconductor laminate; and forming a second DBR laminate on the curved surface of the oxide substrate.

[0116] Appearance 21 The method according to embodiment 20 further includes planarizing the group III nitride region by polishing or etching at least one of the methods before growing the semiconductor stack.

[0117] Appearance 22 The method according to embodiment 20 or embodiment 21 further includes depositing a conductive layer on a first surface of an oxide substrate and forming a first electrode on the conductive layer after growing a semiconductor laminate but before forming a first DBR laminate.

[0118] Appearance 23 The method according to any one of embodiments 20 to 22 further comprises fabricating a mesa structure containing a group III nitride active region from a semiconductor laminate by etching to form an etched surface of an n-type group III nitride region.

[0119] Pattern 24 The method according to embodiment 23 further includes forming a second electrode on the etched surface of the n-type III nitride region outside the mesa structure.

[0120] Appearance 25 In the method according to any one of embodiments 20 to 24, the semiconductor stack further includes either a tunnel junction or an embedded tunnel junction.

[0121] Appearance 26 In the method according to any one of embodiments 20 to 25, preparing a starting base includes depositing a group III nitride layer on a first surface of an oxide base, patterning the group III nitride layer to form a group III nitride template plug, depositing a plurality of dielectric layers covering the first surface of the oxide base and the group III nitride template plug, and processing the plurality of layers to form an AR layer such that the group III nitride template plug is located within through-holes in the AR layer and the group III nitride template plug has a height greater than the thickness of the AR layer.

[0122] Appearance 27 In the method according to any one of embodiments 20 to 26, the group III nitride region grows from the group III nitride template plug by epitaxial lateral overgrowth to form a group III nitride island.

[0123] Appearance 28 In the method described in Embodiment 27, the group III nitride islands extend outward from the group III nitride template plug along the upper surface of the AR layer, and the roughness of the upper surface of the AR layer is less than 1 nanometer.

[0124] Appearance 29 In the method according to any one of embodiments 20 to 28, a group III nitride active region is grown to form a quantum well structure configured to generate light having wavelengths of the first reflection spectrum of the first DBR laminate and the second reflection spectrum of the second DBR laminate.

[0125] Appearance 30 In the method according to any one of embodiments 20 to 29, forming an oxide substrate by processing a second surface of an oxide base includes forming a patterned resist layer on the second surface of the oxide base, heat-treating the patterned resist layer to form a convex resist region, and etching the convex resist region and the oxide base to transfer the shape of the convex resist region to the oxide base and form a curved surface. After forming the first DBR laminate and the second DBR laminate, etching of the convex resist region and oxide substrate is stopped so that the distance between the second DBR laminate and the first DBR laminate exceeds 50 micrometers.

[0126] Appearance 31 A method according to any one of embodiments 20 to 30 further comprises: forming a resist film on a first surface of an oxide substrate after growing a semiconductor laminate but before forming a conductive layer; illuminating the resist layer through a curved surface of the oxide substrate to generate a patterned mask from the resist film; and performing ion implantation using the patterned mask to form an opening structure including an opening region and an insulating region surrounding the opening region.

[0127] While the principles of the present invention have been described and illustrated in preferred embodiments, it will be understood by those skilled in the art that the present invention can be modified in preparation and detail without departing from such principles. Accordingly, the inventors claim all modifications and variations that fall within the spirit and scope of the following claims. [Explanation of Symbols]

[0128] 10 Oxide substrate 11 VCSEL 13,41 Distributed Bragg reflector (DBR) 15 Semiconductor Section 17 AR layer 23 p-type Group III nitride region 25 n-type III-nitride region 27 Group III nitride active region 29 Resonator 31 Anode electrode 33 Cathode electrode 35 Conductive layer 37 Mesa 39a aperture area 39b Insulation area 52 Guiding Marks Ax1 Axial direction

Claims

1. An oxide substrate having a first surface and a second surface including a curved surface opposite to the first surface, A semiconductor portion, disposed on the first surface of the oxide substrate, A lossless anti-reflective (AR) layer is disposed between the semiconductor portion and the first surface of the oxide substrate. The semiconductor portion is positioned between the AR layer and the first distributed Bragg reflector (DBR) mirror, and the first DBR mirror, The oxide substrate comprises a second DBR mirror arranged on the curved surface, The first DBR mirror, the semiconductor portion, the AR layer, the oxide substrate, and the second DBR mirror are arranged in the first axial direction to form an expanded resonator. The semiconductor portion includes a p-type Group III nitride region, a Group III nitride region, and a Group III nitride active region between the p-type Group III nitride region and the Group III nitride region, the p-type Group III nitride region, the Group III nitride active region, and the Group III nitride region are arranged in the first axial direction, and the Group III nitride region includes an n-type Group III nitride region, in a vertical-cavity surface-emitting laser (VCSEL).

2. The VCSEL according to claim 1, wherein the semiconductor portion and the oxide substrate are connected via a group III nitride template plug.

3. The VCSEL according to claim 1, wherein the VCSEL is constructed without using a group III nitride material on the oxide substrate side of the AR layer.

4. The VCSEL according to claim 1, wherein the surface roughness of the AR layer is less than 1 nm.

5. The AR layer has through holes extending in the first axial direction, The VCSEL according to claim 2, wherein the group III nitride template plug is disposed within the through-hole and extends within the through-hole from the first surface of the oxide substrate to the semiconductor portion.

6. The VCSEL according to claim 2, wherein the group III nitride template plug facilitates the regrowth of the high-crystallinity semiconductor device layer on the AR layer.

7. The VCSEL according to claim 2, wherein the group III nitride template plug is composed of a triangular grid or an arrangement of regular strips.

8. The VCSEL according to claim 2, wherein the semiconductor portion has an aperture structure, the aperture structure includes an aperture region extending in the first axial direction and an insulating region surrounding the aperture region, the first DBR mirror, the aperture region, and the second DBR mirror are arranged along the axis, and the aperture structure is positioned at least 3 micrometers away from the group III nitride template plug.

9. The VCSEL according to claim 2, wherein the curved surface of the oxide substrate has a center line, and the group III nitride template plug and the center line of the curved surface do not coincide in position with each other.

10. The VCSEL according to claim 1, wherein a plurality of semiconductor portions are formed by growth according to a hexagonal close-packed (HCP) design, and the curved surface consists of a plurality of curved surfaces arranged to correspond to the plurality of semiconductor portions.

11. The VCSEL according to claim 8, wherein the plurality of the opening structures are concentric around the group III nitride template plug arranged in a triangular grid, and each opening structure includes a single chip.

12. The VCSEL according to claim 8, wherein the opening structure is a continuous ring-shaped opening structure that forms concentric circles around the group III nitride template plugs arranged in a triangular grid.

13. The VCSEL according to claim 1, wherein the guide marks are included in the AR layer.

14. The VCSEL according to claim 13, wherein the VCSEL chip is fragmented by cleavage assisted by the guide marks.

15. The VCSEL according to claim 1, wherein the VCSEL is separated into blocks by a laser stealth process.

16. The VCSEL according to claim 1, wherein the VCSEL includes a shielding outer surface coated with an anti-reflective material that prevents photon leakage.

17. The VCSEL according to claim 1, wherein the length of the extended resonator is greater than 50 micrometers.

18. The oxide substrate is ZnO, SiO ２ Ga ２ O ３ Al ２ O ３ Ta ２ O ５ A VCSEL according to any one of claims 1 to 3, comprising any one of the above.

19. The VCSEL according to claim 2, wherein the crystal orientation of the Group III nitride template plug of the VCSEL is c-plane, semipolar, or nonpolar.

20. The starting base comprises an oxide base, a group III nitride template plug, and a lossless anti-reflective (AR) layer, wherein the oxide base has a first surface and a second surface opposite to the first surface of the oxide base, and the AR layer and the group III nitride template plug are located on the first surface of the oxide base. Growing a group III nitride region from the group III nitride template plug on the AR layer, After growing the group III nitride region, a semiconductor laminate containing an n-type group III nitride region, a group III nitride active region, and a p-type group III nitride region is grown. The second surface of the oxide base is processed to form the oxide substrate having a curved surface located on the opposite side from the first surface of the oxide substrate. After growing the semiconductor laminate, a first distributed Bragg reflector (DBR) laminate is formed on the first surface of the oxide substrate, and Forming a second DBR laminate on the curved surface of the oxide substrate, A method for manufacturing a vertical-cavity surface-emitting laser (VCSEL), including the following.

21. The method according to claim 20, further comprising planarizing the group III nitride region by polishing or etching at least one of the semiconductor stack before growing the semiconductor stack.

22. After growing the semiconductor laminate, and before forming the first DBR laminate, a conductive layer is deposited on the first surface of the oxide substrate, and Forming a first electrode on the conductive layer, The method according to claim 20, further comprising:

23. The method according to claim 20, further comprising etching the mesa structure containing the group III nitride active region to form an etched surface of the n-type group III nitride region from the semiconductor laminate.

24. The method according to claim 23, further comprising forming a second electrode on the etching surface of the n-type III nitride region outside the mesa structure.

25. The method according to claim 20, wherein the semiconductor laminate further comprises either a tunnel junction or an embedded tunnel junction.

26. Providing the aforementioned starting base is Depositing a group III nitride layer on the first surface of the oxide base, Patterning the group III nitride layer to form the group III nitride template plug, Depositing a plurality of dielectric layers covering the first surface of the oxide base and the group III nitride template plug, and The method according to claim 20, comprising processing the plurality of layers to form the AR layer such that the group III nitride template plug is located in a through-hole in the AR layer and the group III nitride template plug has a height greater than the thickness of the AR layer.

27. The method according to claim 20, wherein the group III nitride region is grown from the group III nitride template plug by epitaxial lateral overgrowth to form a group III nitride island.

28. The method according to claim 27, wherein the group III nitride island extends outward from the group III nitride template plug along the upper surface of the AR layer, and the roughness of the upper surface of the AR layer is less than 1 nanometer.

29. The method according to claim 20, wherein the group III nitride active region is grown to form a quantum well structure configured to generate light having wavelengths of the first reflection spectrum of the first DBR laminate and the second reflection spectrum of the second DBR laminate.

30. Processing the second surface of the oxide base to form an oxide substrate includes forming a patterned resist layer on the second surface of the oxide base, heat-treating the patterned resist layer to form a convex resist region, and etching the convex resist region and the oxide base to transfer the shape of the convex resist region to the oxide base and form the curved surface. After forming the first DBR laminate and the second DBR laminate, etching of the convex resist region and the oxide substrate is stopped so that the distance between the second DBR laminate and the first DBR laminate exceeds 50 micrometers. The method according to claim 22.

31. After growing the semiconductor laminate, and before forming the conductive layer, a resist film is formed on the first surface of the oxide substrate. Illuminating the resist layer through the curved surface of the oxide substrate to generate a patterned mask from the resist film, and Ion implantation is performed using the patterned mask to form an opening structure including an opening region and an insulating region surrounding the opening region. The method according to claim 30, further comprising:

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