Semiconductor equipment

Abstract

This invention provides a display device that allows for a narrow bezel and offers excellent display characteristics. [Solution] A display device having a switch section or buffer section, a logic circuit section, and a pixel section. In this configuration, the pixel section comprises a first inverse staggered thin film transistor and a first inverse staggered thin film transistor It has a pixel electrode that connects to the wiring of a transistor, and the switch unit or buffer unit is first The insulating layer, the semiconductor layer, and the first and second gate electrodes sandwiching the second insulating layer It has a second inverse staggered thin-film transistor, and the logic circuit section has a third inverse staggered thin film An inverter circuit consisting of a transistor and a fourth inverse staggered thin-film transistor The first to fourth inverse staggered thin-film transistors are the same The polarity is assumed to be the same. The inverter circuit is an EDMOS circuit.

Description

[Technical Field]

[0001] The present invention relates to a display device having an inverse staggered thin-film transistor in the drive circuit and the pixel portion. . [Background technology]

[0002] As a type of field-effect transistor, a semiconductor layer formed on a substrate having an insulating surface is used. Thin-film transistors in which a channel formation region is formed are known. Amorphous silicon, microcrystalline silicon, or polycrystalline silicon can be used as the semiconductor layer. The technology has been disclosed. A typical application of thin-film transistors is in liquid crystal television equipment. Yes, and it has been put into practical use as a switching transistor for each pixel that makes up a display screen.

[0003] Furthermore, in order to reduce the cost of the display device, the number of external components was reduced, and the gate driver was made non- There are display devices that consist of thin-film transistors made of crystalline silicon or microcrystalline silicon. (See Patent Document 1). [Prior art documents] [Patent Documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2005-049832 [Overview of the Initiative] [Problems that the invention aims to solve]

[0005] Thin-film transistors in which a channel formation region is formed in an amorphous silicon layer have a field-effect mobility. Furthermore, there are problems such as low on-current. Also, thin-film transistors deteriorate with long-term use. This causes a shift in the threshold voltage, leading to a decrease in on-current. Thin-film transistors in which a channel formation region is formed by a silicon layer, such as gate drivers. When configuring such a drive circuit, the width of the channel formation region is widened, and the area of ​​the thin-film transistor is widened. By increasing this value, even if a decrease in on-current occurs due to a threshold voltage shift, sufficient on-current can be maintained. It ensures a sufficient current.

[0006] Alternatively, increase the number of thin-film transistors that make up the drive circuit, and change the movement of each thin-film transistor. By shortening the operating time, degradation of thin-film transistors is reduced, and sufficient on-current is ensured. It is.

[0007] Therefore, in thin-film transistors where the channel formation region is formed in an amorphous silicon layer, the drive cycle In a display device that forms a path, the drive circuit occupies a large area, hindering the narrowing of the display device's bezel. As a result, the area of ​​the pixel portion, which is the display area, becomes smaller.

[0008] On the other hand, thin-film transistors in which the channel formation region is formed in a microcrystalline silicon layer are amorphous silicon Compared to thin-film transistors using Recon technology, the field-effect mobility is improved, but the off-current is The price becomes too high, and there are problems such as not being able to obtain sufficient switching characteristics.

[0009] Thin-film transistors in which a channel formation region is formed in a polycrystalline silicon layer are of the two types described above. It has a significantly higher field-effect mobility than film transistors, and can achieve high on-currents, among other advantages. It has the characteristic. Due to the aforementioned characteristics, this thin-film transistor is a switch provided in the pixel. It is possible to construct not only transistors for the guiding process, but also driver circuits that require high-speed operation. can.

[0010] However, thin-film transistors in which the channel formation region is formed in a polycrystalline silicon layer are amorphous Compared to forming thin-film transistors with silicon layers, a semiconductor layer crystallization process is required. The problem is that manufacturing costs are increasing. For example, the manufacturing of polycrystalline silicon layers The laser annealing technology required for this purpose is for large-screen LCD panels with a small laser beam irradiation area. There are problems such as the inability to produce them efficiently.

[0011] Therefore, one embodiment of the present invention allows for reduced manufacturing costs and excellent image display characteristics. The objective is to provide a display device. Furthermore, one embodiment of the present invention reduces manufacturing costs. The objective is to provide a display device that is both functional and capable of narrow bezels. [Means for solving the problem]

[0012] The present invention has a drive circuit section and a pixel section, the drive circuit section having a logic circuit section and a switch section and This is a display device having a buffer section, and the TFTs constituting the drive circuit section and the pixel section are polar However, since they are both inverse staggered TFTs, the switch or buffer section is designed to allow a large amount of on-current to flow. It is constructed using inverse staggered TFTs that allow for this, and the logic circuit section uses depletion-type TFTs. and an inverter circuit composed of enhancement-type TFTs (hereinafter referred to as EDMOS circuit and It is characterized by being composed of ( ).

[0013] As a TFT capable of handling a large on-current, a dual-gate inverse staggered TFT is an example. Alternatively, a depletion-type inverse staggered TFT can be used.

[0014] EDMOS circuits consist of two or more inverse staggered TFTs with different threshold voltages, typically used in depth-segmented EDMOS circuits. It has a depression-type TFT and an enhancement-type TFT. The FT is formed on the first gate electrode, the first gate insulating layer, and the first gate insulating layer. A semiconductor layer, a second gate insulating layer formed on the semiconductor layer, and on the second gate insulating layer The second gate electrode is formed in a dual-gate type inverse staggered thin-film transistor. By doing so, the threshold voltage can be controlled, and an EDMOS circuit can be constructed.

[0015] Alternatively, as a depletion-type TFT, an impurity element acts as a donor in the channel formation region. An inverse staggered TFT having a semiconductor layer doped with [a specific substance] is used, and an enhancement type TFT is used. Therefore, a semiconductor layer is used in which no donor impurity elements are added to the channel formation region. This allows us to construct an EDMOS circuit.

[0016] Alternatively, as a depletion-type TFT, impurities act as acceptors in the channel formation region. An inverse staggered TFT having a semiconductor layer without added material elements is used, and an enhancement type As a TFT, a semiconductor layer in which impurity elements that act as acceptors are added to the channel formation region. By using this, an EDMOS circuit can be constructed.

[0017] Furthermore, the inverse staggered TFT fabricated in the display device of the present invention comprises a gate electrode and a gate A gate insulating layer formed on the electrode, a semiconductor layer formed on the gate insulating layer, and a semiconductor layer An impurity semiconductor layer that functions as a source region and a drain region formed on top, and wiring The semiconductor layer formed on the gate insulating layer has a microcrystalline semiconductor layer formed on the gate insulating layer side. Furthermore, it has an amorphous semiconductor layer on the source region and drain region side. Or, a gate insulating layer. A microcrystalline semiconductor layer is formed on one side, and amorphous semiconductor layers are formed on the source and drain regions. Between the microcrystalline semiconductor layer and the amorphous semiconductor layer, there is a cone-shaped microcrystalline semiconductor region, and filling the region It has a filled amorphous semiconductor region. Therefore, it increases the on-current of the inverse staggered TFT. This allows for suppression of the off-current.

[0018] On-current refers to the current between the source and drain electrodes when a transistor is in the ON state. This refers to the current flowing through the transistor. For example, in the case of an n-type transistor, the gate voltage is the current flowing through the transistor. This is the current that flows between the source electrode and the drain electrode when the voltage is higher than the threshold voltage.

[0019] Furthermore, off-current refers to the current between the source and drain electrodes when a transistor is in the off state. This refers to the current flowing through the transistor. For example, in the case of an n-type transistor, the gate voltage is the current flowing through the transistor. This is the current that flows between the source electrode and the drain electrode when the voltage is lower than the threshold voltage.

[0020] In this specification, a display device refers to an image display device, a light-emitting device, or a light display device. This refers to the power source (including lighting equipment). It also refers to connectors, such as FPC (Flexible Printed Circuit). (inted circuit) or TAB (Tape Automated Bon) (ding) tape or TCP (Tape Carrier Package) Modules that have a printed circuit board attached to the end of the TAB tape or TCP. The display element or IC (integrated circuit board) is integrated using the COG (Chip On Glass) method. All modules in which the road is directly implemented are also included in the display device. [Effects of the Invention]

[0021] The present invention makes it possible to reduce the cost of a display device while improving the display characteristics of images. Yes, it is possible. Furthermore, it enables narrower bezels on display devices, expanding the display area on those devices. It is possible. [Brief explanation of the drawing]

[0022] [Figure 1] A block diagram illustrating the overall structure of a display device according to one embodiment of the present invention. [Figure 2] A diagram illustrating the arrangement of wiring, input terminals, etc., in a display device according to one embodiment of the present invention. [Figure 3] A block diagram illustrating the configuration of a shift register circuit. [Figure 4] A diagram showing an example of a flip-flop circuit. [Figure 5] This diagram shows the layout (top view) of a flip-flop circuit. [Figure 6] A diagram showing a timing chart to explain the operation of a shift register circuit. [Figure 7] A cross-sectional view illustrating a display device according to one embodiment of the present invention. [Figure 8] A cross-sectional view and a top view illustrating a display device according to one embodiment of the present invention. [Figure 9] A cross-sectional view illustrating a thin-film transistor in a display device according to one embodiment of the present invention. [Figure 10] A cross-sectional view illustrating a display device according to one embodiment of the present invention. [Figure 11] A cross-sectional view and a top view illustrating a display device according to one embodiment of the present invention. [Figure 12] A cross-sectional view illustrating a display device according to one embodiment of the present invention. [Figure 13] A cross-sectional view and a top view illustrating a display device according to one embodiment of the present invention. [Figure 14] A cross-sectional view and a top view illustrating a drive circuit in a display device according to one embodiment of the present invention. [Figure 15]A cross-sectional view illustrating a method for manufacturing a display device according to one embodiment of the present invention. [Figure 16] A cross-sectional view illustrating a method for manufacturing a display device according to one embodiment of the present invention. [Figure 17] A cross-sectional view illustrating a method for manufacturing a display device according to one embodiment of the present invention. [Figure 18] A cross-sectional view illustrating a method for manufacturing a display device according to one embodiment of the present invention. [Figure 19] A diagram illustrating a multi-level mask applicable to a method for manufacturing a display device according to one embodiment of the present invention. [Figure 20] A plan view illustrating a method for manufacturing a display device according to one embodiment of the present invention. [Figure 21] A cross-sectional view illustrating a method for manufacturing a display device according to one embodiment of the present invention. [Figure 22] A cross-sectional view illustrating a method for manufacturing a display device according to one embodiment of the present invention. [Figure 23] A cross-sectional view illustrating a method for manufacturing a display device according to one embodiment of the present invention. [Figure 24] An equivalent circuit diagram illustrating a protection circuit applied to a display device according to one embodiment of the present invention. [Figure 25] A diagram illustrating the terminal portion of a display device according to one embodiment of the present invention. [Figure 26] A diagram illustrating the terminal portion of a display device according to one embodiment of the present invention. [Figure 27] A diagram illustrating an example of a liquid crystal display device according to one embodiment of the present invention. [Figure 28] A diagram illustrating an example of a light-emitting display device according to one embodiment of the present invention. [Figure 29] A diagram illustrating an example of an electronic device to which one embodiment of the present invention is applied. [Modes for carrying out the invention]

[0023] Embodiments of the present invention will be described below with reference to the drawings. However, the present invention is as follows This invention is not limited to descriptions. Without departing from the spirit and scope of the present invention, the form may be modified. It is easily understood by those skilled in the art that the state and details can be changed in various ways. Therefore, the present invention shall be interpreted as being limited only to the embodiments and examples described below. It is not the case that the same thing is referred to when describing the configuration of the present invention using drawings. The symbols used are consistent across different drawings.

[0024] (Embodiment 1) In this embodiment, a display device, which is one embodiment of the present invention, will be described with reference to a block diagram, etc. I will reveal it.

[0025] Figure 1(A) shows an example of a block diagram of an active-matrix liquid crystal display device. The liquid crystal display device shown in A) has a pixel section 1 having multiple pixels equipped with display elements on a substrate 100. 01, and a scan line driving circuit 102 that controls the scan line connected to the gate electrode of each pixel, It includes a signal line driving circuit 103 that controls the input of a video signal to a selected pixel.

[0026] Figure 1(B) is a block diagram of an active-matrix light-emitting display device to which the present invention is applied. An example is shown. The light-emitting display device shown in Figure 1(B) has multiple pixels equipped with display elements on a substrate 110. The pixel section 111 has several pixels, and the first scanning control line is connected to the gate electrode of each pixel. The line drive circuit 112 and the second scan line drive circuit 113, and the video signal to the selected pixel. It has a signal line driving circuit 114 that controls the input, and a switching TFT for one pixel. (Thin Film Transistor. Hereinafter referred to as TFT.) and current control T When two FTs are arranged, the light-emitting display device shown in Figure 1(B) uses a switching TFT. The signal input to the first scan line connected to the gate electrode of the first scan line drive circuit 112 The signal generated is input to a second scan line connected to the gate electrode of the current-control TFT. It is generated by the second scan line drive circuit 113. However, the signal input to the first scan line and the second The signal input to the second scan line may be generated by the first scan line drive circuit. For example, the operation of a switching element can be controlled by the number of TFTs it possesses. Multiple first scan lines used for control may be provided for each pixel. Alternatively, the signals input to multiple first scan lines may all be generated by a single scan line drive circuit. Alternatively, multiple scan line driving circuits may be provided and each of them may generate the signal.

[0027] Note that here, the scan line drive circuit 102, the first scan line drive circuit 112, and the second scan line drive The diagram shows how the drive circuit 113 and the signal line drive circuits 103 and 114 are manufactured in a display device. , scan line drive circuit 102, first scan line drive circuit 112, or second scan line drive circuit 1 Part of 13 may be implemented using semiconductor devices such as ICs. Also, signal line drive circuits 103, 11 Part of 4 may be implemented using semiconductor devices such as ICs.

[0028] Figure 2 shows the display device, including signal input terminals, scan lines, signal lines, and a protection circuit including nonlinear elements. This diagram illustrates the positional relationship between the path and the pixel area. Scan lines are located on the substrate 120 which has an insulating surface. 123 and signal line 124 are arranged to intersect, forming the pixel section 127. Section 127 corresponds to the pixel section 101 and pixel section 111 shown in Figure 1.

[0029] The pixel section 127 is composed of multiple pixels 128 arranged in a matrix. This includes a pixel TFT 129 connected to the scan line 123 and the signal line 124, a holding capacitance unit 130, and a pixel It is composed of an electrode 131.

[0030] In the pixel configuration shown here, in the holding capacitance section 130, one electrode and the pixel TFT 129 are This shows the case where the electrodes are connected and the capacitance line 132 is connected to the other electrode. Also, pixel electrode 1 31 drives the display elements (liquid crystal elements, light-emitting elements, contrast media (electronic ink), etc.) This constitutes one electrode. The other electrode of these display elements is connected to the common terminal 133. Yes, they are.

[0031] The protection circuit is located between the pixel unit 127 and the signal line input terminal 122. It is disposed between the line drive circuit and the pixel section 127. In this embodiment, multiple protective circuits By laying out the circuit, the scan line 123, signal line 124 and capacitance wiring 137 are protected from surges caused by static electricity, etc. The system is configured so that voltage is applied and the pixel TFT129, etc., are not damaged. Therefore, The protection circuit is configured to discharge charge to the common wiring when a surge voltage is applied. It is.

[0032] In this embodiment, the scan line 123 protection circuit 134, the signal line 124 protection circuit 135, This shows an example of installing a protective circuit 136 for the wiring 137. However, the installation position of the protective circuit is shown. This is not limited to this. Also, if the scan line drive circuit is not implemented using a semiconductor device such as an IC, Therefore, it is not necessary to provide a protection circuit 134 on the scan line 123 side.

[0033] Using the TFT of the present invention in each of these circuits offers the following advantages.

[0034] Pixel TFTs are preferably high switching characteristics. Switching characteristics of pixel TFTs By increasing the switching characteristics, the contrast ratio of the display device can be increased. To improve performance, it is effective to increase the on-current and decrease the off-current. (This invention) Pixel TFTs to which this technology is applied have a large on-current and a small off-current, resulting in a high switching characteristic. This allows for high contrast ratios and enables the realization of thin-film transistors with high contrast ratios. can.

[0035] The drive circuit is broadly divided into a logic circuit section and a switch section or buffer section. The TFT to be installed should be configured to allow control of the threshold voltage. On the other hand, the switch section Alternatively, it is preferable that the TFT provided in the buffer section has a high on-current. With this configuration, This enables control of the threshold voltage of the TFT in the logic circuit section, and the switch section or buffer section This makes it possible to increase the on-current of the TFT installed there. Furthermore, the drive circuit occupies It reduces the area and contributes to narrower bezels.

[0036] Because the protection circuit is located at the periphery of the pixel area, it was one of the factors that hindered the narrowing of the bezel. However While the display device shown herein can reduce the area of ​​the protection circuit, This can help prevent the framing process from being hindered.

[0037] (Embodiment 2) In this embodiment, the circuit diagram of the drive circuit of the display device described in Embodiment 1 is shown in Figure 1. This will be explained with reference to Figures 3 through 6.

[0038] First, we will describe the shift register circuit that constitutes the scan line drive circuit shown in Embodiment 1. ru.

[0039] The shift register circuit shown in Figure 3 has multiple flip-flop circuits 201 and control signal lines 202, control signal line 203, control signal line 204, control signal line 205, control signal line 206, It also has a reset line 207.

[0040] As shown in the shift register circuit in Figure 3, the flip-flop circuit 201 has the first stage input The start pulse SSP is input to terminal IN via control signal line 202, and the following stages... The output signal terminal S of the preceding flip-flop circuit 201 is connected to the input terminal IN. OUT It is connected It is. Also, the reset terminal RES of the Nth row (where N is a natural number) is the (N+3)th row Flip-flop circuit output signal terminal S out It is connected via reset line 207. The clock terminal CLK of the Nth stage flip-flop circuit 201 is connected to the control signal line 203. Assuming that the first clock signal CLK1 is input via this, the (N+1)th stage The clock terminal CLK of the lip-flop circuit 201 is connected to the second signal via the control signal line 204. The clock signal CLK2 is input. Also, the (N+2)th stage flip-flop circuit 2 The clock terminal CLK of 01 receives the third clock signal CLK via the control signal line 205. The input is 3. Also, the clock terminal C of the (N+3) stage flip-flop circuit 201. The fourth clock signal CLK4 is input to LK via the control signal line 206. Then, the clock terminal CLK of the (N+4) stage flip-flop circuit 201 receives a control signal. The first clock signal CLK1 is input via line 203. Also, the Nth stage flip The flop circuit 201 has a gate output terminal G out Therefore, the Nth stage flip-flop circuit Outputs SRoutN.

[0041] Note that the connection between the flip-flop circuit 201 and the power supply and power lines is not shown in the diagram, but each The flip-flop circuit 201 is supplied with power supply potential Vdd and power supply potential GND via the power supply line. It is being provided.

[0042] Note that the power supply potential described herein corresponds to the potential difference when the reference potential is set to 0V. Therefore, the power supply potential is sometimes called the power supply voltage.

[0043] In this specification, "A and B are connected" means that A and B are not directly connected. This includes not only those that are present but also those that are electrically connected. Here, A and B are electrically connected. Being "connected" means that there is an object between A and B that has some kind of electrical interaction with it. This refers to the case where A and B are approximately the same node via the object. Specifically A and B are connected via a switching element such as a TFT, and the switching element When conduction causes A and B to be at approximately the same potential, or when A and B are connected via a resistive element Therefore, the potential difference generated across the resistor element is such that it does not affect the operation of the circuit including A and B. When considering the circuit operation, such as when it is a certain degree, A and B are treated as the same node and inserted This describes a situation where there is no support.

[0044] Next, Figure 4 shows the flip-flop circuit 201 of the shift register circuit shown in Figure 3. One form is shown. The flip-flop circuit 201 shown in Figure 4 consists of a logic circuit section 211 and a switch The logic circuit section 211 has a TFT 213 to TFT 218. Furthermore, the switch section 212 has TFTs 219 to 222. The path section 211 is a circuit that responds to signals input from the outside to the subsequent switch section 212. This is a circuit for switching the output signal. Furthermore, the switch section 212 is connected to the external and theoretical components. The TFT, which acts as a switch, is turned on or off according to the signal input from the control circuit unit 211. This is a circuit for replacing and outputting a current appropriate to the size and structure of the TFT in question.

[0045] In the flip-flop circuit 201, the input terminal IN is the gate terminal of the TFT214, and The reset terminal is connected to the gate terminal of TFT217. It is connected to the child. The clock terminal CLK is connected to the first terminal of TFT219 and TFT22 It is connected to the first terminal of 1. The power line that supplies the power supply potential Vdd is the TFT214 It is connected to the first terminal and the second terminal of the TFT216. Power potential GND is supplied. The power lines are connected to the second terminal of TFT213, the second terminal of TFT215, and the second terminal of TFT217. The child, the second terminal of TFT218, the second terminal of TFT220, and the second terminal of TFT222 They are connected. Also, the first terminal of TFT213, the second terminal of TFT214, and TFT21 The first terminal of 5, the gate terminal of TFT218, the gate terminal of TFT219, and TFT22 The gate terminals of 1 are connected to each other. Also, the first terminal and gate terminal of TFT216 This refers to the gate terminal of TFT215, the first terminal of TFT217, the first terminal of TFT218, and T It is connected to the gate terminal of the FT220 and the gate terminal of the TFT222. Output terminal G out It is connected to the second terminal of TFT219 and the first terminal of TFT220. It is being output. Output signal terminal Sout This refers to the second terminal of TFT221 and the first terminal of TFT222. It is connected to the terminal.

[0046] Note that here, we assume that TFT213 through TFT222 are all N-type TFTs. An explanation will be given. However, TFT213 to TFT222 may be P-type TFTs. .

[0047] Furthermore, a TFT has at least three terminals, including a gate, a drain, and a source. It is an element that has a channel formation region between the drain region and the source region, and the drain region And current can be passed through the channel formation region and the source region. Here, the source and The drain may be swapped depending on the structure and operating conditions of the TFT, so which one is the sole It is a drain and difficult to determine which is the drain. Therefore, the source and The regions that function as both source and drain are not called source or drain, for example, respectively. These will be referred to as the first terminal and the second terminal. In this case, the terminal that functions as a gate will be referred to as This is referred to as a gate terminal.

[0048] Next, Figure 5 shows an example of a layout diagram of the flip-flop circuit 201 shown in Figure 4.

[0049] The flip-flop circuit in Figure 5 has a power line 231 to which the power supply potential Vdd is supplied, and a reset line 232, control signal line 203, control signal line 204, control signal line 205, control signal line 206, Control signal line 233, power line 234 to which the power potential GND is supplied, logic circuit section 211, and It has a switch section 212. The logic circuit section 211 has TFTs 213 to 218. Furthermore, the switch section 212 has TFTs 219 to 222. In 5, the gate output terminal G out Wiring connected to output signal terminal S out Connected The wiring diagram is also shown.

[0050] In Figure 5, the semiconductor layer 235, the first wiring layer 236, the second wiring layer 237, and the third wiring layer 238 and the contact hole 239 are shown. Note that the first wiring layer 236 is The first wiring layer is formed by a layer that forms the source electrode, and the second wiring layer 237 is the source electrode of the TFT or The third wiring layer 238 is formed by a layer that forms the drain electrode, and the pixel electrode in the pixel portion It can be formed by a layer that forms the pole. However, it is not limited to this, for example, a third wiring layer Layer 238 may be formed as a wiring layer separate from the layer forming the pixel electrodes.

[0051] The connection relationships between each circuit element in Figure 5 are as explained in Figure 4. This shows a flip-flop circuit to which the first clock signal is input, so control The connections to signal line 204 to control signal line 206 are not shown in the diagram.

[0052] In this embodiment, in the flip-flop circuit layout diagram of Figure 5, the logic circuit section 21 By controlling the threshold voltage of TFT216 or TFT217 in 1, EDMO An S-circuit 223 can be constructed. Typically, a TFT216 can be used as a depletion type. The EDMOS circuit 223 uses an enhancement type TFT217, and the switch The TFTs 219 to 222 in section 212 are dual-gate type TFTs, or One of its features is that it uses a compression-type TFT.

[0053] The channel formation region of depletion-type TFT216 contains donor impurity elements. The semiconductor layer is configured such that the channel formation region of the enhancement-type TFT217 is a donor. By creating a semiconductor layer without added impurity elements, the EDMOS circuit 223 can be formed. It is possible.

[0054] Alternatively, the channel formation region of the depletion-type TFT216 can act as an acceptor for impurities. A semiconductor layer without added physical elements is used for channel formation of an enhancement-type TFT217. By making the region a semiconductor layer containing impurity elements that act as acceptors, the EDMOS circuit 2 23 can be formed.

[0055] Alternatively, use a depression-type TFT216 or an enhancement-type TFT217. By forming a dual-gate type TFT and controlling the potential of the back gate electrode, depression can be achieved. It is possible to form a TFT216 of the enhancement type or an TFT217 of the enhancement type. Therefore, the EDMOS circuit 223 can be formed.

[0056] Therefore, the TFT of the display device is an n-channel TFT or a p-channel TFT, It can be formed using only TFTs of one polarity.

[0057] Furthermore, the TFT216 in the logic circuit section 211 supplies current according to the power supply potential Vdd. This is a TFT, and it is a dual-gate type TFT or a depletion type TFT216. As T, by increasing the current flowing, the TFT can be made smaller without degrading performance. It is possible to standardize the process.

[0058] In addition, in the TFT that constitutes the switch unit 212, by increasing the amount of current flowing through the TFT and being able to perform the switching between on and off at high speed, it is possible to reduce the area occupied by the TFT without degrading the performance. Therefore, it is also possible to reduce the area occupied by the circuit constituted by the TFT. Note that the TFTs 219 to TFT 222 in the switch unit 212 may be laid out so as to sandwich the semiconductor layer 235 between the first wiring [[ID=]]layer 236 and the third wiring layer 2 38 to form a dual-gate type TFT.

[0059] Also, in FIG. 5, an example is shown in which the dual-gate type TFT is formed by sandwiching the semiconductor layer 235 between the first wiring layer 236 and the third wiring layer 2 38 that is connected to the first wiring layer 236 through the contact hole 239 and has the same potential. However, the present invention is not limited to this configuration. For example, a separate control signal line may be provided for the third wiring layer 238, and the potential of the third wiring layer 238 may be controlled independently of the first wiring layer 236. By controlling the threshold voltage of the TFT by the third wiring layer 23 8 and increasing the amount of current flowing through the TFT, it is possible to reduce the area occupied by the TFT and further the area occupied by the circuit constituted by the TFT without degrading the performance.

[0060] In the layout diagram of the flip-flop circuit shown in FIG. 5, the shape of the channel formation regions of the TFTs 213 to TFT 222 may be U-shaped (C-shaped or horseshoe-shaped). Also, in FIG. 5, the sizes of the respective TFTs are made equal, but depending on the magnitude of the load in the subsequent stage, the output signal terminal S out or the gate output terminal G out The sizes of the respective TFTs connected to may be appropriately You may change it.

[0061] Next, using the timing chart shown in Figure 6, we can determine the operation of the shift register circuit shown in Figure 3. Let me explain. Figure 6 shows the control signals 202 to 206 shown in Figure 3. The start pulse SSP, the first clock signal CLK1 to the fourth clock signal are supplied. CLK4 and the output signal terminal S of the 1st to 5th stage flip-flop circuits. out from This shows the output Sout1 through Sout5. Note that the explanation of Figure 6 refers to Figure 4. The reference numerals assigned to each element in Figure 5 are used.

[0062] Figure 6 shows the case where each of the TFTs in the flip-flop circuit is an N-type TFT. This is a timing chart. It also shows the first clock signal CLK1 and the fourth clock signal C LK4 has a configuration that is shifted by 1 / 4 wavelength (one section divided by the dotted line) as shown in the diagram. It is.

[0063] First, during period T1, the first stage flip-flop circuit receives a start pulse SSP. When input at H level, the logic circuit section 211 controls the TFTs 219 and 221 of the switch section. Turn it on, and turn off TFT220 and TFT222. At this time, the first clock signal C Since LK1 is at L level, Sout1 is also at L level.

[0064] During period T1, a signal is input to the IN terminal of the second and subsequent flip-flop circuits. Because it is not powered, it outputs an L level without operating. Note that in the initial state, Shift Each flip-flop circuit in the resistor circuit will be described assuming it outputs a low level. .

[0065] Next, during period T2, the first-stage flip-flop circuit performs logic similarly to period T1. The circuit section 211 controls the switch section 212. During period T2, the first clock signal CL Since K1 is at level H, Sout1 will also be at level H. Also, in period T2, the second stage In the flip-flop circuit, Sout1 is input to the IN terminal at a high level, and the logic circuit section 211 turns on TFT219 and TFT221 in the switch section, and TFT220 and TFT Turn off 222. At this time, the second clock signal CLK2 is at a low level, so ut2 is at the L level.

[0066] During period T2, a signal is input to the IN terminal of the flip-flop circuit from the third stage onward. Because it is not powered, it outputs an L level without operating.

[0067] Next, during period T3, the first-stage flip-flop circuit maintains the state from period T2. The logic circuit section 211 controls the switch section 212 in this manner. Therefore, during period T3, The first clock signal CLK1 is at a high level, and Sout1 is at a high level. During period T3, the second stage flip-flop circuit operates similarly to period T2, with logic circuit section 2 11 controls the switch unit 212. During period T3, the second clock signal CLK2 is H Since it is a level, Sout2 is an H level. Also, the third flip of period T3 In the ROP circuit, Sout2 is input to the IN terminal at a high level, and the logic circuit section 211 switches Turn on TFTs 219 and 221 in the switch section, and turn off TFTs 220 and 222. At this time, since the third clock signal CLK3 is at a low level, Sout3 is also at a low level. .

[0068] During period T3, a signal is input to the IN terminal of the flip-flop circuit from the 4th stage onward. Because it is not powered, it outputs an L level without operating.

[0069] Next, during period T4, the first clock signal CLK1 is at a low level, and Sout1 is It becomes L level. Also, in period T4, the second stage flip-flop circuit, period T The logic circuit section 211 controls the switch section 212 to maintain state 3. During period T4, the second clock signal CLK2 is at a high level, and Sout2 is at a high level. It becomes a bell. Also, in period T4, the third stage flip-flop circuit is in period T3 and Similarly, the logic circuit section 211 controls the switch section 212. During period T4, the third cross Since the CLK3 signal is at a high level, Sout3 is also at a high level. Also, during period T4 In the fourth stage of the flip-flop circuit, Sout3 is input to the IN terminal at a high level, and the theory The control circuit unit 211 turns on the TFTs 219 and 221 of the switch unit 212, and TFT2 Turn off 20 and TFT222. At this time, the fourth clock signal CLK4 is at the L level. Therefore, Sout4 is at an L level.

[0070] During period T4, a signal is input to the IN terminal of the flip-flop circuit from the 5th stage onward. Because it is not powered, it outputs an L level without operating.

[0071] Next, during period T5, the first-stage flip-flop circuit maintains the state from period T4. Therefore, the logic circuit section 211 controls the switch section 212. Therefore, the first clock signal CLK1 is at a low level, and Sout1 is at a low level. During period T5, the second-stage flip-flop circuit operates similarly to period T4, in the logic circuit section. 211 controls the switch unit 212. During period T5, the second clock signal CLK2 is Since it is L level, Sout2 is L level. Also, in period T5, the third stage In the flip-flop circuit, the logic circuit section 211 switches to maintain the state during period T4. Control of the control unit 212. Therefore, during period T5, the third clock signal CLK3 is It is at level H, and Sout3 is at level H. Also, in period T5, the 4th stage flip In the pop-flop circuit, similar to the period T4, the logic circuit section 211 controls the switch section 212. Perform the following. During period T5, the fourth clock signal CLK4 is at a high level, therefore Sout4 is It is at the H level. Also, the flip-flop circuits from the 5th stage onward are the same as the flip-flops of the 1st to 4th stages. The wiring is similar to that of a pop-flop circuit, and the timing of the input signal is also the same. I will omit the explanation.

[0072] As shown in the shift register circuit in Figure 3, Sout4 is the first stage flip-flop circuit. It also serves as the reset signal. During period T5, Sout4 becomes high level, and this signal is used for one stage. The reset signal is input to the reset terminal RES of the flip-flop circuit. By doing so, the TFT219 and TFT221 of the switch unit 212 are turned off, and TFT22 Turn on 0 and TFT222. Then, Sout1 of the first stage flip-flop circuit is The system will output an L level until the next start pulse SSP is input.

[0073] Based on the operation described above, even in the second and subsequent flip-flop circuits, the subsequent flip-flops Based on the reset signal output from the jump circuit, the logic circuit section is reset, Sou As shown in t1 to Sout5, the signal is a waveform shifted by 1 / 4 wavelength from the clock signal. It can be used as an output shift register circuit.

[0074] Furthermore, as a flip-flop circuit, the logic circuit section 211 includes enhancement type and depress type The EDMOS circuit combines two types of TFTs, and the switch section 212 uses a dual-gate type. By providing a configuration that includes TFTs, the flow through the TFTs constituting the logic circuit section 211 The current can be increased, and without degrading performance, the area occupied by the TFT can be increased, and furthermore This allows for a reduction in the area occupied by the circuit composed of the TFT. Also, the switch In the TFT constituting section 212, the amount of current flowing through the TFT is increased, and the on and off states Because switching can be done at high speed, the area occupied by the TFT can be reduced without degrading performance. Furthermore, the area occupied by the circuit composed of the TFT can be reduced. Therefore, This allows for narrower bezels, smaller size, and higher performance of display devices.

[0075] Furthermore, the signal line drive circuit shown in Embodiment 1 may be provided with a latch circuit, a level shifter circuit, etc. This is possible. A buffer section is provided in the final stage where the signal is sent from the signal line drive circuit to the pixel section, and current The amplified signal is sent from the signal line drive circuit to the pixel unit. For this reason, the buffer unit is ON-power TFTs with high current flow, typically dual-gate TFTs or depletion-type TFTs. By providing T, it is possible to reduce the area of ​​the TFT, and the signal line driving circuit occupies a smaller area. The area can be reduced. Therefore, it is possible to make the display device narrower, smaller, and more high-performance. This is possible. Furthermore, the shift register, which is part of the signal line drive circuit, requires high-speed operation. Therefore, it is preferable to implement it in a display device using an IC or the like.

[0076] (Embodiment 3) In this embodiment, in the display device shown in Embodiment 1 and Embodiment 2, logical The structure of the thin-film transistors in the circuit section, switch section, and pixel section is shown. Used in a display device. In thin-film transistors, the n-type has higher carrier mobility than the p-type. By unifying the polarity of all thin-film transistors formed on the substrate, the number of manufacturing steps can be reduced. This is preferable. Therefore, in this embodiment, an n-type thin-film transistor will be described. do.

[0077] Figures 7 and 8(A) show the logic circuit section 391 and switch section of the display device according to this embodiment. A cross-sectional view of one form (structure 1) of 393 and the pixel section 395 is shown.

[0078] The logic circuit section 391 of the display device shown in Figure 7 shows an EDMOS circuit. Either a depletion-type TFT or an enhancement-type TFT is located at the gate electrode 3 It is formed with a dual-gate type TFT300a having O3 and a back gate electrode 373. Furthermore, the other of a depletion-type TFT or an enhancement-type TFT is TF It is formed from T300b. Note that the cross-sectional view CD of the logic circuit section 391 shown in Figure 7, and Figure 8... The cross-sectional view CE of the logic circuit section 391 shown in (A) corresponds to CD and CE in the top view of Figure 8(B). Each corresponds to the other.

[0079] In the switch section 393 of the display device shown in Figure 7, the gate electrode 305 and the back gate electrode A dual-gate type TFT300c with pole 374 is formed.

[0080] The switching element in the pixel of the pixel section 395 of the display device shown in Figure 7 is TFT300d It is formed by the second gate insulating layer 379 and the capacitive wiring 353 and wiring 375. A capacitive element 300e is formed.

[0081] The TFT300a has a gate electrode 303 and a first semiconductor layer 333a on a substrate 301. The second semiconductor layer 333b, the third semiconductor layer 363, the gate electrode 303 and the first semiconductor The first gate insulating layer 309 provided between the body layers 333a and the third semiconductor layer 363 are in contact Impurity semiconductor layers 355, 356 function as source and drain regions, and It has wirings 346 and 347 in contact with the semiconductor layer. It also has a first semiconductor layer 333a, The second semiconductor layer 333b, the third semiconductor layer 363, the first gate insulating layer 309, and impurities. The second layer covers the monocrystalline semiconductor layers 355 and 356 and the wiring 346 and 347 that are in contact with the impurity semiconductor layer. A gate insulating layer 379 is formed, and the gate electrode 30 is connected via the second gate insulating layer 379. A back gate electrode 373 is located in the region opposite to 3.

[0082] The TFT300b has a gate electrode 304 and a first semiconductor layer 333a on a substrate 301. The second semiconductor layer 333b, the third semiconductor layer 363, the gate electrode 304 and the first semiconductor The first gate insulating layer 309 provided between the body layers 333a and the third semiconductor layer 363 are in contact Impurity semiconductor layers 356 and 357 function as source and drain regions, and It has wirings 347 and 348 in contact with the semiconductor layer.

[0083] Furthermore, as shown in Figure 8(A), the gate electrode 303 of TFT300a and TFT300a The wiring 347 of the TFT300b is formed on the insulating layer 381 simultaneously with the pixel electrode 383. It is connected by wiring 384.

[0084] The TFT300c has a gate electrode 305 and a first semiconductor layer 334a on a substrate 301. The second semiconductor layer 334b, the third semiconductor layer 364, the gate electrode 305 and the first semiconductor The first gate insulating layer 309 is provided between the body layers 334a and the third semiconductor layer 364 is in contact with Impurity semiconductor layers 358 and 359 function as source and drain regions, and It has wirings 349 and 350 in contact with the semiconductor layer. It also has a first semiconductor layer 334a, The second semiconductor layer 334b, the third semiconductor layer 364, the first gate insulating layer 309, and A second gate insulating layer 379 covers the pure semiconductor layers 358 and 359 and the wiring 349 and 350. A second gate insulating layer 379 is formed, and in the region facing the gate electrode 305, It has a back gate electrode 374.

[0085] The TFT300d has a gate electrode 306 and a first semiconductor layer 335a on a substrate 301. The second semiconductor layer 335b, the third semiconductor layer 365, the gate electrode 306 and the first semiconductor The first gate insulating layer 309 is provided between the body layers 335a and the third semiconductor layer 365 is in contact with Impurity semiconductor layers 360, 361 function as source and drain regions, and It has wirings 351 and 352 in contact with the semiconductor layer.

[0086] Furthermore, the capacitive element 300e has a second gate insulating layer 379 and capacitive wiring 353 and wiring 375 It is composed of and .

[0087] The substrate 301 can be a glass substrate, a ceramic substrate, or any other substrate that can withstand the processing temperature of this manufacturing process. A plastic substrate with a certain degree of heat resistance can be used. In addition, the substrate may have light-transmitting properties. If this is not required, an insulating layer can be provided on the surface of a metal substrate such as a stainless steel alloy. This may also be done. Examples of glass substrates include barium borosilicate glass and aluminobosilicate glass. It is preferable to use an alkali-free glass substrate such as acidic glass or aluminosilicate glass. As board 301, the 3rd generation (550mm x 650mm), 3.5th generation (600mm) ×720mm, or 620mm×750mm), 4th generation (680mm×880mm, (or 730mm x 920mm), 5th generation (1100mm x 1300mm), 6th generation (1500mm x 1850mm), 7th generation (1870mm x 2200mm), 8th generation (2200mm×2400mm), 9th generation (2400mm×2800mm, 2450m Using glass substrates such as m x 3050 mm, 10th generation (2950 mm x 3400 mm), etc. It is possible.

[0088] The gate electrodes 303-306 and capacitive wiring 307 are made of molybdenum, titanium, chromium, and tantalum. , metallic materials such as tungsten, aluminum, copper, neodymium, scandium or these It can be formed using an alloy material with as its main component, either as a single layer or in layers. Semiconductor layers such as polycrystalline silicon doped with impurity elements like phosphorus, and AgPdC U-alloy may also be used.

[0089] For example, as a two-layer laminated structure of gate electrodes 303-306 and capacitive wiring 307, aluminum A two-layered structure in which a molybdenum layer is stacked on top of a nium layer, or a molybdenum layer on top of a copper layer A stacked two-layer structure, or a two-layer structure in which a titanium nitride layer or tantalum nitride layer is stacked on a copper layer. The structure is preferably a two-layer structure consisting of a titanium nitride layer and a molybdenum layer. The laminated structure consists of a tungsten layer or tungsten nitride layer, and aluminum and silicon A laminate of an aluminum alloy or an aluminum-titanium alloy with a titanium nitride layer or a titanium layer. It is preferable to have a laminated structure. A metal layer that functions as a barrier layer is placed on top of a layer with low electrical resistance. The layered structure results in low electrical resistance and prevents the diffusion of metal elements from the metal layer to the semiconductor layer. It can be stopped.

[0090] The first gate insulating layer 309 is formed using CVD or sputtering, etc. A single layer, silicon nitride layer, silicon oxide nitride layer, or silicon nitride oxide layer, either individually or in multiple layers. It can be formed in layers. In addition, the first gate insulating layer 309 can be made of silicon oxide or acid By forming with silicon nitride, the first semiconductor layers 333a to 335a are made of microcrystalline semiconductor material. When used as a body layer, it is possible to reduce fluctuations in the threshold voltage of the thin-film transistor.

[0091] In this specification, silicon oxidnitride refers to a silicon oxide with a composition that contains more oxygen than nitrogen. It has a high content, and preferably, Rutherford backscattering (RBS: Rutherford (Fford Backscattering Spectrometry) and hydrogen forward Using the scattering method (HFS: Hydrogen Forward Scattering) When measured, the composition range is 50-70 atomic percent oxygen and 0.5-15 atomic percent nitrogen. This refers to materials containing 25-35 atomic percent silicon and 0.1-10 atomic percent hydrogen. Furthermore, silicon nitride has a composition in which nitrogen content is higher than oxygen content. Preferably, when measured using RBS and HFS, the composition range is such that oxygen is 5 ~30 atomic percent, nitrogen 20~55 atomic percent, silicon 25~35 atomic percent, hydrogen 10~3 This refers to substances included in the range of 0 atomic percent. However, this does not apply to silicon oxide nitride or silicon oxide nitride. When the total amount of atoms constituting the element is set to 100 atomic%, the content of nitrogen, oxygen, silicon, and hydrogen The ratio is assumed to fall within the above range.

[0092] The first semiconductor layers 333a to 336a are formed from microcrystalline semiconductor layers. It is a semiconductor with a structure intermediate between amorphous and crystalline (including single crystals and polycrystalline) materials. The conductor is a semiconductor having a third state that is free energy stable and possesses short-range order. A crystalline semiconductor having lattice strain, preferably with a grain size of 2 nm to 200 nm. More preferably, columnar nodes with a wavelength of 10 nm to 80 nm, and more preferably 20 nm to 50 nm. Crystals or needle-shaped crystals are growing in the direction normal to the substrate surface. Therefore, columnar crystals or In some cases, grain boundaries may be formed at the interface of needle-shaped crystals.

[0093] Microcrystalline silicon, a typical example of a microcrystalline semiconductor, has a Raman spectrum that is different from that of single-crystal silicon. 520cm -1 It is shifted to a lower wavenumber side. In other words, it exhibits single-crystal silicon. 520cm -1 And 480 cm² showing amorphous silicon -1 Between the microcrystalline silicon There is a peak in the Mann spectrum. Also, to terminate unbonded bonds (dangling bonds) It contains at least 1 atomic percent or more of hydrogen or halogen. By including noble gas elements such as helium, argon, krypton, or neon to further induce lattice strain, the stability is enhanced and a good microcrystalline semiconductor can be obtained. A description of such a microcrystalline semiconductor is disclosed, for example, in U.S. Patent No. 4,409,134.

[0094] Also, the concentration measured by secondary ion mass spectrometry of oxygen and nitrogen contained in the first semiconductor layers 333a to 336a is less than 1×10 18 atoms / cm 3 which is preferable because it can enhance the crystallinity of the first semiconductor layers 333a to 336a.

[0095] The third semiconductor layers 363 to 366 are formed of an amorphous semiconductor layer, or an amorphous semiconductor layer having a halogen, or an amorphous semiconductor layer having nitrogen. The nitrogen contained in the amorphous semiconductor layer having nitrogen may exist, for example, as an NH group or an NH2 group. The amorphous semiconductor layer is formed using amorphous silicon.

[0096] When the third semiconductor layers 363 to 365 are formed of an amorphous semiconductor layer having nitrogen, the slope becomes steeper compared to the band tail of the bandgap of the amorphous semiconductor layer, the bandgap becomes wider, and the tunnel current becomes less likely to flow. As a result, the off-current of the thin film transistor can be reduced.

[0097] FIG. 9 shows an enlarged view between the first gate insulating layer 309 of FIG. 7 and the impurity semiconductor layers 355 to 361 functioning as source and drain regions.

[0098] As shown in FIG. 9(A), the second semiconductor layers 333b to 335b are the first semiconductor layers 333 It is provided between a to 335a and the third semiconductor layer 363 to 365. Also, the second semiconductor Layers 333b to 335b are microcrystalline semiconductor regions 367 and the microcrystalline semiconductor region 367 It has an amorphous semiconductor region 368 that fills the space between them. Specifically, the first semiconductor layer 333a A microcrystalline semiconductor region 367 extending convexly from ~335a, and a third semiconductor layer 363~365 It is formed with an amorphous semiconductor region 368 similar to the above. Furthermore, it is formed in amorphous semiconductor regions containing halogens or amorphous semiconductor regions containing nitrogen. It may also be used.

[0099] The third semiconductor layer 363-365 is an amorphous semiconductor layer with low electrical conductivity and high resistivity. Amorphous semiconductor layer having halogens, amorphous semiconductor layer having nitrogen, or having NH groups By forming it with an amorphous semiconductor layer, the off-current of the thin-film transistor can be reduced. Furthermore, in the second semiconductor layer 333b to 335b, a cone-shaped microcrystalline semiconductor region 367 Because it has the characteristics of a thin-film transistor, when a voltage is applied to the wiring while the transistor is ON, the vertical direction (film thickness) The resistance in the direction, that is, the resistance between the semiconductor layer and the source region or drain region. It is possible to lower the current and increase the on-current of the thin-film transistor.

[0100] Furthermore, as shown in Figure 9(B), the second semiconductor layer 333b to 335b is the first semiconductor layer It may also be a structure provided between 333a to 335a and the impurity semiconductor layers 355 to 361. i. That is, between the second semiconductor layer 333b~335b and the impurity semiconductor layer 355~361 This structure does not form a third semiconductor layer. The second semiconductor layers 333b to 335b are microcrystalline. Crystalline semiconductor region 367, and amorphous semiconductor region filling the space between the microcrystalline semiconductor region 367 It has region 368. Specifically, it has a micro convex shape extending from the first semiconductor layer 333a to 335a. It is formed by a crystalline semiconductor region 367 and an amorphous semiconductor region 368. The structure shown in Figure 9(B) In the manufacturing process, the ratio of the microcrystalline semiconductor region 367 to the amorphous semiconductor region 368 is low. This is preferable. Furthermore, between the pair of impurity semiconductor layers 355-361, that is, the carrier In the flowing region, it is preferable that the proportion of the microcrystalline semiconductor region 367 is low. This can reduce the off-current of the thin-film transistor. Also, the second semiconductor layer 333b In ~335b, when a voltage is applied to the wiring while the thin-film transistor is ON, the vertical direction Resistance in the (film thickness direction), i.e., between the semiconductor layer and the source region or drain region. It is possible to lower the resistance and increase the on-current of the thin-film transistor. .

[0101] The microcrystalline semiconductor region 367 is located from the first gate insulating layer 309 to the third semiconductor layer 363-36 The crystal grains are convex, narrowing towards the tip towards 5. Furthermore, the first gate insulating layer 309 is connected to the The crystal grains may be convex, widening towards the semiconductor layer 363 of the third layer.

[0102] In the second semiconductor layer 333b-335b, the microcrystalline semiconductor region 367 is the first G From the insulating layer 309 toward the third semiconductor layer 363-365, convex crystal grains with narrowing tips. In this case, the first semiconductor layer 333a~335a side is better than the third semiconductor layer 363~36 Compared to side 5, the proportion of microcrystalline semiconductor regions is higher. This is because the first semiconductor layer 333a~3 From the surface of 35a, a microcrystalline semiconductor region 367 grows in the film thickness direction, but in the source gas If the flow rate of hydrogen with respect to silane is low or the concentration of the raw material gas containing nitrogen is high, the growth of crystal grains in the microcrystalline semiconductor region 367 is suppressed, resulting in conical crystal grains, and eventually only the amorphous semiconductor region is deposited.

[0103] Also, the second semiconductor layers 333b to 335b preferably contain nitrogen. This is because at the interfaces of the crystal grains contained in the microcrystalline semiconductor region 367 and at the interfaces between the microcrystalline semiconductor region 367 and the amorphous semiconductor region 368, nitrogen, typically an NH group or an NH2 group, binds to the dangling bonds of silicon atoms to reduce defects. Therefore, the nitrogen concentration of the second semiconductor layers 333b to 335b is set to 1×10 19 atoms / cm 3 or more and 1×10 21 atoms / cm 3 or less, preferably 1×10 20 atoms / cm 3 to 1×10 21 atoms / cm 3 so that the dangling bonds of silicon atoms can be easily crosslinked by nitrogen, preferably an NH group, making it easier for carriers to flow. Or, the dangling bonds of semiconductor atoms at the above-mentioned interfaces are terminated by an NH2 group, causing the defect levels to disappear. As a result, when a voltage is applied between the source electrode and the drain electrode in the on state, the resistance in the longitudinal direction (thickness direction) is reduced. That is, the field-effect mobility and the on-current of the thin-film transistor increase .

[0104] Also, by reducing the oxygen concentration of the second semiconductor layers 333b to 335b, the carriers at the interfaces between the microcrystalline semiconductor region 367 and the amorphous semiconductor region 368 and at the interfaces between the crystal grains This can reduce the number of bonds that inhibit the movement of A.

[0105] In this context, the first semiconductor layers 333a to 335a refer to regions with approximately equal thickness. Also, the interface between the first semiconductor layer 333a-335a and the second semiconductor layer 333b-335b In the flat portion at the interface between the microcrystalline semiconductor region 367 and the amorphous semiconductor region 368, This refers to the region that is an extension of the region closest to the first gate insulating layer 309.

[0106] The sum of the thicknesses of the first semiconductor layer 333a-335a and the second semiconductor layer 333b-335b That is, from the interface of the first gate insulating layer 309, the convexity of the second semiconductor layer 333b to 335b The distance to the tip of the part shall be 3 nm to 80 nm, preferably 5 nm to 30 nm. This reduces the off-current of the TFT.

[0107] The impurity semiconductor layers 355-362 are amorphous silicon with phosphorus added. It is formed from microcrystalline silicon, etc. Furthermore, as a thin-film transistor, a p-channel thin film is used. When forming a transistor, the impurity semiconductor layers 355-362 are doped with boron. It is formed from microcrystalline silicon, amorphous silicon with boron added, etc. Semiconductor layers 333b to 336b or a third semiconductor layer 363 to 366, and wiring 346 to 35 2. When the capacitive wiring 353 makes ohmic contact, the impurity semiconductor layer 355~3 It is not necessary to form 62.

[0108] Furthermore, the impurity semiconductor layers 355-362 are made of phosphorus-doped microcrystalline silicon, or boro. When formed with microcrystalline silicon with added ions, the second semiconductor layer 333b to 336b Alternatively, between the third semiconductor layer 363-366 and the impurity semiconductor layer 355-362, microcrystals By forming a semiconductor layer, typically a microcrystalline silicon layer, the properties of the interface are improved. This results in the formation of impurity semiconductor layers 355-362 and a second semiconductor layer 333b-33 The resistance at the interface with 6b or the third semiconductor layer 363-366 can be reduced. As a result, the current flowing through the source region, semiconductor layer, and drain region of the thin-film transistor Increasing the quantity allows for an increase in on-current and field-effect mobility.

[0109] Wiring 346-352 and capacitive wiring 353 are made of aluminum, copper, titanium, neodymium, and stainless steel. Candium, molybdenum, chromium, tantalum, or tungsten, etc., in a single layer, It can be formed by lamination. Alternatively, aluminum with added hillock-preventing elements. Alloy (Al-Nd alloy that can be used for gate electrodes 303-306 and capacitive wiring 307) It may also be formed by (etc.) using crystalline silicon to which donor impurity elements have been added. Alternatively, the layer in contact with the crystalline silicon to which the donor impurity element is added can be made of titanium. , formed from tantalum, molybdenum, tungsten or nitrides of these elements, A laminated structure with aluminum or an aluminum alloy formed on top may also be used. The top and bottom surfaces of the aluminum or aluminum alloy are made of titanium, tantalum, molybdenum, A laminated structure may be formed by sandwiching tungsten or nitrides of these elements.

[0110] The second gate insulating layer 379 can be formed in the same manner as the first gate insulating layer 309. .

[0111] Back gate electrodes 373, 374, wiring 375, wirings 346-352, capacitive wiring 353 It can be formed in the same way as [this].

[0112] The insulating layer 381 can be formed using an inorganic insulating layer or an organic resin layer. The layers consist of silicon oxide, silicon oxide nitride, silicon oxide nitride, and DLC (Diamond-Like Carbon). Carbon, such as ammonium nitrile, can be used. For organic resin layers, for example, acrylic Epoxy, polyimide, polyamide, polyvinylphenol, benzocyclobutene, etc. It can be used. Additionally, siloxane polymers can be used.

[0113] The pixel electrode 383 and wiring 384 are made of indium oxide containing tungsten oxide, tungsten oxide, and tungsten oxide. Indium zinc oxide containing gusten, indium oxide containing titanium oxide, titanium oxide indium tin oxide, indium tin oxide, indium zinc oxide, or zinc oxide containing It can be formed using indium tin oxide with added lycon, etc.

[0114] Furthermore, the pixel electrode 383 and wiring 384 are made of a light-transmitting conductive polymer. It can be formed using a conductive composition containing (also known as ). Wiring 384 and pixel electricity Pole 383 has a sheet resistance of 10000 Ω / □ or less, and at a wavelength of 550 nm. It is preferable that the light transmittance is 70% or higher. Furthermore, the conductive polymer contained in the conductive composition is also preferable. It is preferable that the resistivity is 0.1 Ω·cm or less.

[0115] As the conductive polymer, so-called π-electron conjugated conductive polymers can be used. For example For example, polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene Examples include 1, its derivatives, or copolymers of two or more of these.

[0116] A dual-gate TFT has a gate electrode 303 and a back gate electrode 373, each with its own electrical components. By changing the position, it is possible to control the threshold voltage, so the logic circuit section 391 In this setup, either a depletion-type TFT or an enhancement-type TFT is used in a dual configuration. A gate-type TFT300a is used, and a depletion-type TFT or an enhancement-type TFT is used. By using the TFT300b shown in Figure 7 as the other TFT, an EDMOS circuit is formed. It is possible.

[0117] Furthermore, in a dual-gate TFT, the channel through which the carrier flows is the first gate isolation This occurs at two locations: near the interface on the edge layer 309 side and near the interface on the second gate insulating layer 379 side. This increases the amount of carrier movement, which can increase the on-current of the thin-film transistor. Therefore, the TFT formed in the switch section 393 is equipped with a dual TFT capable of increasing the on-current. By forming a gate-type TFT300c, it is possible to reduce the area of ​​the TFT. This allows for a reduction in the area of ​​the drive circuit of the display device.

[0118] Next, the logic circuit section 391, the switch section 393, and the pixel section of the display device according to this embodiment. A cross-sectional view of one form (structure 2) of 395 is shown in Figures 10 and 11.

[0119] Figure 10 shows the EDMOS circuit of the logic circuit section 391 of the display device shown in Figure 10, and the EDMOS circuit As a compression-type TFT401a, impurities that impart a single conductivity to the channel formation region. A TFT is formed having a first semiconductor layer to which elements are added. A TFT401b of the specified type is formed. Note that Figure 10 shows a cross-sectional view CD of the logic circuit section 391. , and the cross-sectional view CE of the logic circuit section 391 shown in Figure 11(A) is the same as the top view in Figure 11(B) Compatible with both CD and CE formats.

[0120] In the switch section 393 of the display device shown in Figure 10, a single conductivity type is applied to the channel formation region. In a TFT, a first semiconductor layer is formed in which impurity elements are added, and in this case, the donor element A depletion-type TFT401c having a first semiconductor layer doped with impurity elements is formed It will be accomplished.

[0121] TFT401a has a gate electrode 303 and an impurity source that imparts a single conductivity type on the substrate 301. A first semiconductor layer 427a with added elements, a second semiconductor layer 427b, and a third semiconductor layer 469 and a first semiconductor having a gate electrode 303 and impurity elements that impart a single conductivity type. The first gate insulating layer 309 provided between the body layers 427a and the third semiconductor layer 469 are in contact Impurity semiconductor layers 459 and 460 function as source and drain regions, and It has wirings 451 and 452 in contact with the material semiconductor layers 459 and 460.

[0122] The TFT401b has a gate electrode 304 and a first semiconductor layer 454a on the substrate 301. The second semiconductor layer 454b, the third semiconductor layer 470, the gate electrode 304 and the first semiconductor A first gate insulating layer 309 is provided between layers 454a and is in contact with the third semiconductor layer 470 Impurity semiconductor layers 461 and 462 that function as source and drain regions, and It has wirings 452 and 453 in contact with semiconductor layers 461 and 462.

[0123] Furthermore, as shown in Figure 11(A), the gate electrode 303 of TFT401a and TFT401 The wiring 452 of a and TFT401b are formed on the insulating layer 381 simultaneously with the pixel electrode 383. It is connected by wiring 384.

[0124] The TFT401c has a gate electrode 305 and an impurity source that imparts a single conductivity type on the substrate 301. A first semiconductor layer 428a, a second semiconductor layer 428b, and a third semiconductor layer 4 71 and the first gate insulating layer provided between the gate electrode 305 and the first semiconductor layer 428a The edge layer 309 functions as a source region and drain region in contact with the third semiconductor layer 471. The impurity semiconductor layers 463 and 464, and the wiring 454 in contact with the impurity semiconductor layers 463 and 464. It has 455.

[0125] The TFT401d has a gate electrode 306 and a first semiconductor layer 455a on the substrate 301. The second semiconductor layer 455b, the third semiconductor layer 472, the gate electrode 306 and the first semiconductor A first gate insulating layer 309 is provided between layers 455a and is in contact with the third semiconductor layer 472 Impurity semiconductor layers 465, 466 that function as source and drain regions, and It has wirings 456 and 457 that are in contact with semiconductor layers 463 and 464.

[0126] The first semiconductor layers 427a and 428a, to which impurity elements that impart a single conductivity type are added, Then, donor impurity elements are added. The donor impurity elements are, These are elements belonging to Group 15 of the solar calendar, and representative examples include phosphorus, arsenic, and antimony. So, as the first semiconductor layer 427a to which impurity elements that impart a single conductivity type are added, A microcrystalline semiconductor layer is formed by adding phosphorus, which is an impurity element.

[0127] The first semiconductor layers 454a to 456a are the first semiconductor layers 333a to shown in "Structure 1" above. It can be formed in the same way as 336a.

[0128] The second semiconductor layers 427b, 428b, and 454b-456b are the second semiconductor layers shown in "Structure 1" above. It can be formed in the same manner as the semiconductor layers 333b to 336b.

[0129] The third semiconductor layer 469-473 is the same as the third semiconductor layer 363-366 shown in "Structure 1" above. It can be formed in the same way as [this].

[0130] Here, as shown in Figure 9(A), the second semiconductor layers 427b, 428b, Between 454b~456b and the impurity semiconductor layers 459~467, there is a third semiconductor layer 469 Although a structure with ~473 was shown, the third semiconductor layer 469 is similar to that shown in Figure 9(B). It is not necessary to include ~473.

[0131] The impurity semiconductor layers 459-467 are the same as the impurity semiconductor layers 355-362 shown in "Structure 1" above. It can be formed in the same way as [this].

[0132] Wirings 451-458 shall be formed in the same manner as wirings 346-353 shown in "Structure 1" above. It is possible.

[0133] In Figure 10, the depletion-type TFT401a of the EDMOS circuit is shown as follows: A first semiconductor layer is formed in which an impurity element that imparts a single conductivity type is added to the channel formation region. Although a TFT is used, the channel formation region of the depletion-type TFT401a is The first semiconductor layer 454a of TFT401b is formed in the same way as the enhancement-type TFT In the channel-forming region of 401b, impurity elements that impart a single conductivity type, typically acceptors, are added. A first semiconductor layer may be formed by adding an impurity element that acts as an acceptor. Impurity elements are those belonging to Group 13 of the periodic table, and a typical example is boron. .

[0134] Here, in the logic circuit section 391, a depletion-type TFT or enhancement... An impurity element that imparts a monoconductivity was added to one channel-forming region of a TFT. By using a semiconductor layer, an EDMOS circuit can be formed.

[0135] Furthermore, in depletion-type TFTs, the threshold voltage shifts to the negative, so the ON state Because it is possible to increase the current in the state, TF is formed in the switch section 393 By forming a depletion-type TFT that can increase the on-current in T, TF It is possible to reduce the area of ​​T, and thus reduce the area of ​​the drive circuit of the display device. Cut.

[0136] Next, the logic circuit section 391, the switch section 393, and the pixels of the display device according to this embodiment. A cross-sectional view of one form (structure 3) of part 395 is shown using Figures 12 and 13.

[0137] Figure 12 shows the EDMOS circuit of the logic circuit section 391 of the display device shown in Figure 12, and the EDMOS circuit As a compression-type TFT401a, the channel formation region shown in "Configuration 2" above A TFT401a having a first semiconductor layer to which an impurity element that imparts a single conductivity type is added. It is formed. Also, as an enhancement type TFT401b, as shown in "Configuration 2" above A TFT401b is formed. Note that Figure 12 shows a cross-sectional view CD of the logic circuit section 391. , and the cross-sectional view CE of the logic circuit section 391 shown in Figure 13(A) is the same as the top view in Figure 13(B). Compatible with both CD and CE formats.

[0138] In the switch section 393 of the display device shown in Figure 12, the gate electrode 305 and the back gate A dual-gate type TFT403c having electrode 482 is formed.

[0139] The switching element in the pixel of the pixel section 395 of the display device shown in Figure 12 is TFT401 It is formed by d. Also, there is a pixel electrode 481 that connects to the wiring of TFT401d and wiring 458 Then, the capacitive element 403e is formed by the second gate insulating layer 379.

[0140] The TFT401a shown in Figure 12 is different from the TFT401a shown in Figure 10, as shown in Figure 13(A). As shown, the gate electrode 303 and the wiring 4 connecting TFT401a and TFT401b 52 and wiring 483 formed on the second gate insulating layer 379 simultaneously with the pixel electrode 481. The difference lies in how they are connected.

[0141] The TFT403c has a gate electrode 305 and an impurity source that imparts a single conductivity type on the substrate 301. A first semiconductor layer 428a with added elements, a second semiconductor layer 428b, and a third semiconductor layer 471 and the first gate provided between the gate electrode 305 and the first semiconductor layer 428a The insulating layer 309 functions as a source region and a drain region in contact with the third semiconductor layer 471. The impurity semiconductor layers 463 and 464, and the wiring 45 in contact with the impurity semiconductor layers 463 and 464 It has 4 and 455. Also, the gate electrode 305 and The opposing region has a back gate electrode 482. The back gate electrode 482 is a pixel electrode It can be formed simultaneously with pole 481.

[0142] Note that instead of TFT403c, the dual-gate type TFT30 shown in "Structure 1" above can be used. 0c may be formed.

[0143] The pixel electrode 481 connected to the TFT401d is formed on the second gate insulating layer 379. .

[0144] Furthermore, the capacitive element 403e includes wiring 458, a second gate insulating layer 379, and a pixel electrode 48. It is formed by 1.

[0145] The display device shown in Figure 12 has a pixel electrode 481 and a back gate electrode 482, and a gate electrode Since it is possible to form wiring 483 that connects pole 303 and wiring 452, photo It is possible to reduce the number of masks.

[0146] Next, a cross-sectional view of one form of EDMOS circuit applicable to the above "structure 1" to "structure 3" (structure The details of construction 4) are shown in Figure 14.

[0147] Figure 14(A) shows the EDMOS circuit of the logic circuit section 391 of the display device, and the EDMOS circuit As a depletion-type TFT480a, the following are shown in "Structure 2" and "Structure 3" above. A first semiconductor layer in which an impurity element that imparts a single conductivity type to the channel-forming region is added. A TFT having the following is formed. Also, as an enhancement type TFT480b, the structure It is formed with the same structure as TFT300b shown in "Structure 1". Note that the logic shown in Figure 14(A) The cross-sectional view CD of circuit section 391 corresponds to CD in the top view of Figure 14(B).

[0148] The EDMOS circuit shown in Figure 14 is a depletion-type TFT480a with gate electrode 486 However, connecting the depletion-type TFT480a and the enhancement-type TFT480b The wiring 485 and the opening formed in the first gate insulating layer 309 are directly connected. ru.

[0149] Therefore, since the gate electrode 486 and wiring 485 are directly connected, as shown in Figures 7 to 12. Compared to the EDMOS circuit shown, the contact resistance of the gate electrode 486 and wiring 485 is reduced. It is possible.

[0150] Note that the field-effect mobility of the TFT is 5 cm. 2 If it is lower than / V·sec, it is typically 0 0.5~3cm 2 In the case of / V·sec, as shown in "Structure 1" to "Structure 3", the dep A reduction-type TFT and an enhancement-type TFT are connected, and a depletion-type The wiring that connects to the gate electrode of the TFT is formed simultaneously with the back gate electrode or pixel electrode. This makes it possible to reduce the number of masks. On the other hand, the field-effect mobility of the TFT is 5cm 2 If the value is above / V·sec, a depletion-type TFT will be used, as shown in Figure 14. And wiring for connecting the enhancement-type TFTs is formed in the first gate insulating layer 309. By directly connecting the gate electrode of a depletion-type TFT at the opening, This reduces the increase in contact resistance, allowing the TFT to maintain high-speed operation.

[0151] Note that the TFTs shown in the EDMOS circuits of "Structure 1" to "Structure 4" are appropriately controlled by inverters and other components. It can also be applied to resistors, buffer circuits, protection circuits, diodes, and the like.

[0152] Furthermore, in the TFTs shown in "Structure 1" to "Structure 4", the first gate insulating layer and impurities A structure in which only the first semiconductor layer and the third semiconductor layer are stacked between the semiconductor layers is also possible. .

[0153] The display device described above has a drive circuit and a TFT formed in the pixel section that has an inverse staggered structure. Furthermore, the polarity of each TFT is set to either the n-channel type or the p-channel type polarity. It is possible to form it in this way, and furthermore, since a part of the drive circuit is formed on the substrate, display It is possible to reduce the cost of the equipment. Also, for TFTs that require a large amount of current, dual By installing algate-type or depletion-type TFTs, the area of ​​the TFT can be increased. Because it can be reduced in size, it is possible to narrow the bezel of the display device and expand the display area. This is possible. In addition, in the pixel section, a TFT with a high on-current and a low off-current is used for each pixel. Because it is used as a switching element, it results in a display device with high contrast and good image quality. .

[0154] (Embodiment 4) Here, the method for manufacturing the display device shown in Figure 7 is illustrated with reference to Figures 15 to 18. This embodiment describes a method for fabricating an n-type thin-film transistor (Method 1).

[0155] As shown in Figure 15(A), gate electrodes 303-306 and capacitive wiring 307 are placed on the substrate 301. Next, the gate electrodes 303-306 and capacitance wiring 307 are covered with the first gate insulator. A marginal layer 309 and a first semiconductor layer 311 are formed.

[0156] As the substrate 301, the substrate 301 shown in Embodiment 3 can be used as appropriate.

[0157] The gate electrodes 303-306 and capacitive wiring 307 are as shown in Embodiment 3. The gate electrodes 303-306 are formed using the materials shown in 306 and 307 as appropriate. Capacitive wiring 307 is formed on substrate 301 using sputtering or vacuum deposition. A conductive layer is formed using the specified material, and then photolithography or inkjet printing is performed on the conductive layer. A mask can be formed by the law, and the conductive layer can be formed by etching using the mask. It can also be done by applying a conductive nanopaste such as silver, gold, or copper onto a substrate using an inkjet method. It can also be formed by extrusion and firing. Note that gate electrodes 303-306, capacity To improve the adhesion between the wiring 307 and the substrate 301, a nitride layer of the above-mentioned metal material is applied to the substrate 3 01 may be provided between gate electrodes 303-306 and capacitance wiring 307. Here, A conductive layer is formed on the substrate 301, and a resist mask formed using a photomask is used. To check.

[0158] Furthermore, the sides of the gate electrodes 303-306 and the capacitive wiring 307 are tapered. Preferably, in a later step, an insulating layer, a semiconductor layer, and a wiring layer are formed on the gate electrode 303. Therefore, this is to prevent breakage at the stepped sections. Token 303~ To make the sides of capacitive wiring 306 and 307 tapered, the resist mask is moved back. You can then proceed with etching.

[0159] Furthermore, the process of forming gate electrodes 303-306 creates gate wiring (scanning lines) and capacitance distribution. Lines can also be formed simultaneously. Note that scan lines refer to wiring that selects pixels, and capacitance distribution A line refers to a wire connected to one of the electrodes of a pixel's capacitance. However, it is not limited to this. In addition to the gate wiring and capacitive wiring, one or both are provided separately from the gate electrodes 303-306. That's fine.

[0160] The first gate insulating layer 309 is made of the same material as the first gate insulating layer 309 shown in Embodiment 3. The first gate insulating layer 309 can be formed by CVD or sputtering. It can be formed using the ring method or the like. In addition, the first gate insulating layer 309 is high frequency It may also be formed using a microwave plasma CVD apparatus with a frequency of several GHz or higher. When the first gate insulating layer 309 is formed using a wave plasma CVD apparatus, the gate electrode and, This improves the breakdown voltage between the drain electrode and the source electrode, resulting in a highly reliable system. Thin-film transistors can be obtained. Also, as the first gate insulating layer 309, an organic sil By forming a silicon oxide layer using a CVD method with Lan gas, the first gate insulating layer is formed. It is possible to reduce the hydrogen content, thereby reducing the fluctuation of the threshold voltage of thin-film transistors. It can be reduced. Examples of organic silane gases include ethyl silicate (TEOS: chemical formula Si(O)). C2H5)4), tetramethylsilane (TMS: chemical formula Si(CH3)4), tetramethyl Lucyclotetrasiloxane (TMCTS), Octamethylcyclotetrasiloxane (OM CTS), hexamethyldisilazane (HMDS), triethoxysilane (SiH(OC2) Silicones such as H5)3), trisdimethylaminosilane (SiH(N(CH3)2)3), etc. The contained compounds can be used.

[0161] The first semiconductor layer 311 consists of microcrystalline silicon, microcrystalline silicon germanium, and microcrystalline It is formed using germanium, etc. The first semiconductor layer 311 is 1 nm to 20 nm in size. Preferably, it is formed with a thickness of 3 nm to 10 nm.

[0162] The first semiconductor layer 311 is made of silicon or gel in the reaction chamber of a plasma CVD apparatus. A depositing gas containing manium is mixed with hydrogen and formed by glow discharge plasma. Alternatively, a depositing gas containing silicon or germanium, hydrogen, helium, neon, It is formed by mixing it with a noble gas such as krypton and using a glow discharge plasma. The hydrogen flow rate is preferably 10 to 2000 times higher than the flow rate of the germanium-containing sedimentary gas. Dilute 10 to 200 times, then microcrystalline silicon, microcrystalline silicon germanium, microcrystalline It forms germanium, etc.

[0163] Typical examples of sedimentary gases containing silicon or germanium include SiH4 and Si2H6. Examples include GeH4 and Ge2H6.

[0164] Furthermore, before forming the first semiconductor layer 311, the processing chamber of the CVD apparatus is evacuated while... A sedimenting gas containing licone or germanium is introduced to remove impurity elements from the treatment chamber. By doing so, the first gate insulating layer 309 and the first semiconductor of the thin-film transistor that are later formed... It is possible to reduce impurity elements at the interface of the body layers, and the electrical characteristics of thin-film transistors It can improve sexual performance.

[0165] Next, as shown in Figure 15(B), a second semiconductor layer 313 and Next, a third semiconductor layer 315 is formed. Here, the first semiconductor layer 311 is partially crystallized. Under growing conditions, the second semiconductor layer 313 and the third semiconductor layer 315 are formed. In the reaction chamber of the Zuma CVD apparatus, a depositing gas containing silicon or germanium is used, It is mixed with hydrogen and formed by glow discharge plasma. At this time, the first semiconductor layer 311 The hydrogen flow rate to the depositing gas containing silicon or germanium is different from the film deposition conditions. By reducing, that is, by forming the film under conditions that reduce crystal growth, the second semiconductor layer 313 Crystal growth is suppressed, and as the film is deposited, a third semiconductor region that does not contain microcrystalline semiconductor regions is formed. A body layer 315 can be formed.

[0166] Alternatively, in the reaction chamber of a plasma CVD apparatus, a pile containing silicon or germanium A gas containing a condensing gas, hydrogen, and nitrogen is mixed, and a second semiconductor is generated by glow discharge plasma. Body layer 313 and third semiconductor layer 315 are formed. At this time, the formation of the first semiconductor layer 311 Reduce the hydrogen flow rate to the depositing gas containing silicon or germanium, rather than under membrane conditions. In addition, by mixing in a gas containing nitrogen, crystal growth in the second semiconductor layer 313 is achieved. A third semiconductor layer 315 can be formed that is suppressed and does not contain microcrystalline semiconductor regions.

[0167] Furthermore, in this embodiment, in the initial stages of deposition of the second semiconductor layer 313, the first semiconductor layer Using 311 as a seed crystal, a film is deposited throughout. After this, crystal growth is partially suppressed. Then, cone-shaped microcrystalline semiconductor regions grow (mid-deposition stage). Furthermore, cone-shaped microcrystalline semiconductor regions Crystal growth is suppressed, resulting in a third semiconductor layer 315 (late deposition stage) that does not contain microcrystalline semiconductor regions. This is formed. Thus, the first semiconductor layer shown in Embodiment 3 is shown in this embodiment. This corresponds to the film formed in the initial stages of deposition of the first semiconductor layer 311 and the second semiconductor layer 313. Furthermore, the second semiconductor layer shown in Embodiment 3 is the second semiconductor layer 31 shown in this embodiment. This corresponds to the conical microcrystalline semiconductor region and amorphous semiconductor region formed during the middle stage of deposition in 3. Furthermore, the third semiconductor layer shown in Embodiment 3 is formed in the later stages of deposition as shown in this embodiment. This corresponds to semiconductor layer 315 of 3.

[0168] Next, as shown in Figure 15(C), an impurity is impurity that impures a single conductivity type onto the third semiconductor layer 315. A semiconductor layer with added material (hereinafter referred to as impurity semiconductor layer 317) is formed, and the impurity semiconductor A conductive layer 319 is formed on the body layer 317.

[0169] The impurity semiconductor layer 317 is made of silicon or gel in the reaction chamber of the plasma CVD apparatus. A sedimentary gas containing manium, hydrogen, and phosphine (hydrogen-diluted or silane-diluted) Mixed and formed by glow discharge plasma. Depositable material containing silicon or germanium. Diluting the gas with hydrogen yields amorphous silicon with phosphorus added, and phosphorus added to microcrystalline silicon. Crystalline silicon, phosphorus-added amorphous silicon germanium, phosphorus-added microcrystalline silicon Crystalline silicon germanium, phosphorus-added amorphous germanium, phosphorus-added It forms microcrystalline germanium and other materials.

[0170] The conductive layer 319 is made of the same material as the wiring 346-352 and capacitive wiring 353 shown in Embodiment 3. A layered structure can be used as appropriate. The conductive layer 319 can be manufactured by CVD, sputtering, or It is formed using a vacuum deposition method. Furthermore, the conductive layer 319 is made of conductive nanoparticles such as silver, gold, or copper. Using a starter, the material is extruded using a screen printing method or inkjet method, and then fired. It may be formed by and .

[0171] Next, as shown in Figure 16(A), a second resist mask 321-32 is placed on the conductive layer 319. Form 4.

[0172] The resist masks 321-323 have regions of different thicknesses. Such resist masks This can be formed using a multi-gradation mask. By using a multi-gradation mask, the This is preferable because it reduces the number of photomasks and thus the number of manufacturing steps. In this process, the steps include forming a semiconductor layer pattern and separating the source region and the drain region. In this case, a multi-tone mask can be used.

[0173] A multi-gradation mask is a mask that allows exposure at multiple levels of light intensity. Typical examples include: Exposure is performed using three levels of light intensity: exposed area, partially exposed area, and unexposed area. A multi-gradation mask is used. By doing so, multiple (typically two) thicknesses can be obtained through a single exposure and development process. A resist mask can be formed. Therefore, by using a multi-level mask, The number of masks required can be reduced.

[0174] Figures 19(A-1) and 19(B-1) show cross-sectional views of typical multi-level masks. Figure 1 Figure 9(A-1) shows the gray tone mask 490, and Figure 19(B-1) shows the halftone. Shows mask 495.

[0175] The gray tone mask 490 shown in Figure 19(A-1) is placed on a light-transmitting substrate 491. Light-shielding portion 492 formed by a light-shielding film, and diffraction grating portion provided by the pattern of the light-shielding film It consists of 493.

[0176] The diffraction grating section 493 has slits and dots spaced at intervals less than or equal to the resolution limit of the light used for exposure. The light transmittance is controlled by having a grating or mesh. The slits, dots, or mesh provided may be periodic or aperiodic. It could be something like that.

[0177] As the light-transmitting substrate 491, quartz or the like can be used. The light-shielding film constituting the folded lattice section 493 may be formed using metal, preferably chromium. Alternatively, it may be provided by chromium oxide or the like.

[0178] When light is shone onto the gray tone mask 490 for exposure, the result is shown in Figure 19(A-2). Thus, the light transmittance in the region superimposed on the light-shielding portion 492 becomes 0%, and the light-shielding portion 492 or In the region where the diffraction grating 493 is not provided, the light transmittance is 100%. The light transmittance in the lattice portion 493 is generally in the range of 10-70%, and the slit of the diffraction grating, It can be adjusted by changing the spacing of dots or meshes, etc.

[0179] The halftone mask 495 shown in Figure 19(B-1) is applied to a translucent substrate 496. The structure consists of a semi-transparent portion 497 formed by a light-transmitting film and a light-shielding portion 498 formed by a light-shielding film. It has been done.

[0180] The semi-transparent portion 497 is a film made of MoSiN, MoSi, MoSiO, MoSiON, CrSi, etc. It can be formed using the same method. The light-shielding portion 498 is similar to the light-shielding film of the gray tone mask. It can be formed using a metal, preferably chromium or chromium oxide, etc.

[0181] When light is shone onto the halftone mask 495 for exposure, the result is shown in Figure 19(B-2). Thus, the light transmittance in the region superimposed on the light-shielding portion 498 becomes 0%, and the light-shielding portion 498 or In the region where the semi-transparent portion 497 is not provided, the light transmittance is 100%. The light transmittance in section 497 is generally in the range of 10-70%, depending on the type of material being formed or The thickness can be adjusted depending on the amount of film to be formed.

[0182] By exposing and developing using a multi-gradation mask, a resist mask with regions of different film thicknesses can be developed. It can form a sclera.

[0183] Next, using the resist masks 321-324, the first semiconductor layer 311 and the second semiconductor layer 313, the third semiconductor layer 315, the impurity semiconductor layer 317, and the conductive layer 319 are etched. This process creates the first semiconductor layer 311, the second semiconductor layer 313, and the third semiconductor layer. 315, the impurity semiconductor layer 317 and the conductive layer 319 are separated for each element, and the first semiconductor layer 33 3a~336a, second semiconductor layer 333b~336b, third semiconductor layer 333c~336 c. Forming impurity semiconductor layers 329-332 and conductive layers 325-328 (Figure 16(B) (See reference).

[0184] Next, the resist masks 321-324 are moved back, separating the resist masks 337- 344 and a recessed resist mask 345 are formed. Oxygen is used to recess the resist mask. Plasma ashing can be used. Here, the gate electrode is used to separate the electrodes. By ashing the dist masks 321-323, the resist masks 337-344 It can be formed (see Figure 16(C)).

[0185] Next, the conductive layers 325 to 328 are etched using the resist masks 337 to 345, and Lines 346-352 and capacitive wiring 353 are formed (see Figure 17(A)). Conductive layer 325- For etching of 328, wet etching is preferable. The conductive layers 325-328 are isotropically etched by the process. As a result, wiring 346- 352, Capacitive wiring 353 is set back inward from the resist mask 337-345. Wiring 3 Lines 46-352 function not only as source and drain electrodes but also as signal lines. However, it is not limited to this, and the signal line may be provided separately from the source electrode and drain electrode.

[0186] Next, using the resist masks 337-345, the third semiconductor layer 333c-336c, A portion of each of the pure semiconductor layers 329-332 is etched. Here, dry etching is performed. A buffer layer is used. Up to this step, the third semiconductor layer 363-366, which functions as a buffer layer, is formed. Then, impurity semiconductor layers 355-362 are formed. After this, resist masks 337-345 Remove (see Figure 17(A)). Note that the cross-sectional view of pixel 395 in Figure 17(A) is shown in Figure 2. This corresponds to the cross-sectional view of AB in the plan view of the pixel area indicated by 0(A).

[0187] Here, after wet etching the conductive layers 325-328, the resist mask 3 Leaving layers 37-345 intact, the third semiconductor layer 333c-336c and the impurity semiconductor layer 329 ~332 was dry-etched, so conductive layer 325~3 28 is etched isotropically, along with the sides of wiring 346-352 and capacitance wiring 353, and impurities The sides of semiconductor layers 355-362 do not coincide, and the sides of wiring 346-352 and capacitive wiring 353 do not coincide. The sides of the impurity semiconductor layers 355-362 are formed on the outside of this structure.

[0188] Next, after removing the resist masks 337-345, it is recommended to perform dry etching. The conditions for dry etching are that damage is inflicted on the exposed third semiconductor layer 363-366. Furthermore, conditions are used that do not result in a low etching rate for the third semiconductor layer 363-366. In other words, it causes almost no damage to the exposed third semiconductor layer 363-366 surface. Furthermore, the conditions are used such that the thickness of the exposed third semiconductor layer 363-366 is hardly reduced. Yes. As etching gas, Cl2, CF4, or N2 are used. There are no particular limitations on the coupling method; inductively coupled plasma (ICP) ly Coupled Plasma) method, capacitively coupled plasma (CCP: Capac (Ideally Coupled Plasma) method, electron cycloton resonance plasma (ECR:Electron Cyclotron Resonance) method, reactivity Using methods such as ion etching (RIE: Reactive Ion Etching) It is possible.

[0189] Next, water plasma, ammonia plasma, and nitrogen plasma are applied to the surface of the third semiconductor layer 363-366. You may irradiate it with a rasma or similar device.

[0190] Water plasma treatment involves a reaction space into which water-based gases, primarily composed of water (H2O vapor), are used. This can be done by introducing a plasma and generating it.

[0191] As described above, after forming the impurity semiconductor layers 355-362, the third semiconductor layer 363 By performing further dry etching under conditions that do not damage ~366, a third semiconductor can be created. It can remove impurities such as residue present on layers 363-366. By performing water plasma treatment following etching, residue from the resist mask can be removed. This can be achieved. By performing water plasma treatment, insulation between the source region and the drain region is ensured. It can be made into a real product, reducing the off-current of the finished thin-film transistor and improving its electrical characteristics. This can reduce the variability.

[0192] Thin-film transistors can be fabricated through the above process.

[0193] Next, a second gate insulating layer 371 is formed. Next, on the first gate insulating layer 309... The logic circuit section 391 has a dual-gate type TFT 300a, and the switch section 393 has a dual In the region where the capacitive elements of the double-gate type TFT300c and pixel section 395 are formed, The gate electrodes 373-374 and capacitive wiring 375 are formed (see Figure 17(B)).

[0194] The second gate insulating layer 371 can be formed in the same manner as the first gate insulating layer 309. .

[0195] Back gate electrodes 373-374, capacitive wiring 375, wiring 346-352, capacitive wiring 3 The materials and manufacturing methods shown in 53 can be used as appropriate.

[0196] Next, as shown in Figure 18(A), an insulating layer 372 is formed. The insulating layer 372 is formed in the embodiment The insulating layer 381 shown in state 3 can be formed using an appropriate method.

[0197] Next, the insulating layer 372 and a portion of the second gate insulating layer 371 are etched to form the logic circuit section. Wiring 347 for connecting dual-gate type TFT300a and TFT300b, An opening is formed that exposes the gate electrode 303 and the wiring 352 of the pixel portion 395. The opening can be formed by photolithography. Subsequently, through the opening Dual-gate type TFT300a and TFT are connected on the insulating layer 372. Wiring 347 connecting 300b, Wiring 384 connecting gate electrode 303, Pixel section 3 95 forms a pixel electrode 383 connected to wiring 352 (wiring 347 and gate electrode 30 See Figure 8(A) for connection 3. See Figure 18(B). Note that pixel section 39 in Figure 18(A) The cross-sectional view of 5 corresponds to the cross-sectional view of AB in the plan view of the pixel area shown in Figure 20(B).

[0198] The wiring 384 and pixel electrode 383 are made of the material shown in Embodiment 3 by sputtering. After forming the thin film used, a resist mask formed by a photolithography process is used. It can be formed by etching the above thin film. Furthermore, a transparent conductive polymer... A conductive composition containing the material can be applied or printed, and then fired to form the material. The cross-sectional view of pixel portion 395 in 17(A) is shown in the plan view of the pixel portion shown in Figure 20(A) as A- This corresponds to a cross-sectional view of B.

[0199] Wiring 384 connects to the dual-gate type TFT300a and TFT300 of the logic circuit section 391. By connecting the wiring 347 that connects b and the gate electrode 303, TFT300a and T An EDMOS circuit can be formed using FT300b.

[0200] By following the above steps, a display device like the one shown in Figure 8 can be manufactured.

[0201] Next, regarding the method for manufacturing the display device shown in Figure 10 (Method 2), using Figures 21 to 23... show.

[0202] As shown in Figure 21(A), gate electrodes 303-306 and capacitive wiring 307 are placed on the substrate 301. Next, the gate electrodes 303-306 and capacitance wiring 307 are covered with the first gate insulator. A first semiconductor layer 411 is formed by adding an impurity element that imparts a single conductivity type to the edge layer 309. ru.

[0203] As the substrate 301, the substrate 301 shown in Embodiment 3 can be used as appropriate.

[0204] The gate electrodes 303-306, the capacitive wiring 307, and the first gate insulating layer 309 are the same as described above. It can be formed in the same manner as in "Law 1".

[0205] The first semiconductor layer 411, to which impurity elements that impart a single conductivity type are added, is the first semiconductor layer 3 Formed by adding a donor or acceptor impurity element to 11. The donor impurity elements are those belonging to Group 15 of the periodic table, and typically, Examples include phosphorus, arsenic, and antimony. Additionally, the periodic list includes impurity elements that act as acceptors. These are elements belonging to Group 13 of the table, and a representative example is boron. Here, one conductivity type is assigned. As the first semiconductor layer 411 to which the donor impurity element is added, the donor impurity element This document describes a method for fabricating a microcrystalline semiconductor layer with a certain phosphorus doped into it.

[0206] The raw material gas of the first semiconductor layer 411 to which impurity elements that impart monoconductivity are added contains monoconductivity A semiconductor layer is formed by mixing a gas containing impurity elements that impart properties. Typically, plasma In the reaction chamber of the CVD apparatus, a depositing gas containing silicon or germanium and water It is formed by mixing silicon and phosphine and using glow discharge plasma. Alternatively, silicon Or a sedimentary gas containing germanium, hydrogen, phosphine, helium, neon, It is formed by mixing it with a noble gas such as krypton and using glow discharge plasma. A single conductivity type is imparted. As the first semiconductor layer 411 to which impurity elements are added, a phosphorus-containing microcrystalline silicon is used. It forms phosphorus-containing microcrystalline silicon germanium, phosphorus-containing microcrystalline germanium, etc.

[0207] Alternatively, a gas containing impurity elements that impart a single conductivity type to the surface of the first gate insulating layer 309 is used. After exposure, a microcrystalline semiconductor layer is formed, incorporating impurity elements that impart a single conductivity type. A microcrystalline semiconductor layer is formed. Typically, the surface of the first gate insulating layer 309 is... By exposing it to osphing, phosphorus is adsorbed onto the surface of the first gate insulating layer 309. Subsequently, a microcrystalline semiconductor layer is formed using the same method as the first semiconductor layer 311 shown in "Method 1" above. By forming it, phosphorus-containing microcrystalline silicon, phosphorus-containing microcrystalline silicon germanium, It is possible to form microcrystalline germanium containing phosphorus, etc.

[0208] Alternatively, a microcrystalline semiconductor layer is formed on the first gate insulating layer 309, and then a single conductivity type is imparted. Plasma is generated in a gas atmosphere containing impurity elements, and a single conductivity type is applied to the microcrystalline semiconductor layer. By exposing the material to a plasma containing impurity elements, impurity elements that impart a specific conductivity type are added. A first semiconductor layer 411 can be formed. Typically, as shown in "Method 1" above. After forming a microcrystalline semiconductor layer in the same manner as the first semiconductor layer 311, a phosphorus plasma is formed. By exposing the microcrystalline semiconductor layer, phosphorus-containing microcrystalline silicon and phosphorus-containing microcrystalline silicon gel are produced. It is possible to form microcrystalline germanium containing rumanium and phosphorus.

[0209] Next, a second semiconductor layer 413, a third semiconductor layer 415, and After forming the impurity semiconductor layer 417, a resist mask 419 is placed on the impurity semiconductor layer 417. Forms 420 (see Figure 21(B)).

[0210] Here, the second semiconductor layer 313, the third semiconductor layer 315, and impurities shown in "Method 1" above are used. The second semiconductor layer 413 and the third semiconductor layer 415 are formed in the same manner as the semiconductor layer 317. An impurity semiconductor layer 417 is formed.

[0211] Furthermore, the impurity semiconductor layer 417 is later used for the fourth semiconductor layer 431, the fifth semiconductor layer 433, and the The etching process of semiconductor layer 435 and impurity semiconductor layer 437 reduces the film thickness. Therefore, it is preferable to increase the film thickness, typically to a thickness of about 30 to 150 nm. .

[0212] The resist masks 419 and 420 are used for the TFT 401a and switches of the later logic circuit section 391. It is formed in the region that will become TFT401c of part 393.

[0213] Next, using the resist masks 419 and 420, the first semiconductor layer 411 and the second semiconductor layer 413, the third semiconductor layer 415, and the impurity semiconductor layer 417 are etched. As a result, the first semiconductor layer 411, the second semiconductor layer 413, the third semiconductor layer 415, and The pure semiconductor layer 417 is separated for each element, and the first semiconductor layer 427a, 428a and the second semiconductor layer Body layers 427b, 428b, third semiconductor layers 425, 426, and impurity semiconductor layer 423, Form 424. After this, remove the resist masks 419 and 420 (see Figure 21(C)). reference).

[0214] Next, as shown in Figure 22(A), the fourth semiconductor layer 431, the fifth semiconductor layer 433, and the sixth A semiconductor layer 435 and an impurity semiconductor layer 437 are formed, and a resin is placed on the impurity semiconductor layer 437. Forms stomach masks 439 and 440.

[0215] The fourth semiconductor layer 431, the fifth semiconductor layer 433, the sixth semiconductor layer 435, and the impurity semiconductor Body layer 437 is the first semiconductor layer 311 and the second semiconductor layer as described in "Method 1" above. 313, the third semiconductor layer 315, and the impurity semiconductor layer 317 can be formed in the same manner. ru.

[0216] The resist masks 439 and 440 are used for the TFT 401b and pixel section 3 of the later logic circuit section 391. It is formed in the region that will become TFT401d of 95.

[0217] Next, using the resist masks 439 and 440, the fourth semiconductor layer 431 and the fifth semiconductor layer 433, the sixth semiconductor layer 435, and the impurity semiconductor layer 437 are etched. As a result, the fourth semiconductor layer 431, the fifth semiconductor layer 433, the sixth semiconductor layer 435, and The pure semiconductor layer 437 is separated for each element, and the fourth semiconductor layer 454a~456a and the fifth semiconductor layer Body layers 454b-456b, sixth semiconductor layer 454c-456c, and impurity semiconductor layer 44 Forms 4, 446, and 447. Note that in this etching process, the impurity semiconductor layer 423 , 424 is also etched, so the impurity semiconductor layers 443 and 445, which have become thinner, take shape This is achieved by the fourth semiconductor layer 431, the fifth semiconductor layer 433, and the sixth semiconductor layer 43 5. To thoroughly etch the impurity semiconductor layer 437 and leave no etching residue. Furthermore, even after etching of the fourth semiconductor layer 431 is complete, over-etching is performed. As a result, in the over-etching process, the impurity semiconductor layers 423 and 424 were also etched. (See Figure 22(B)). After this, remove resist masks 439 and 440.

[0218] Next, a conductive layer 319 is formed as shown in Figure 22(C).

[0219] Next, a resist mask is formed on the conductive layer 319. Then, the resist mask is used as described above. Similar to "Method 1," the conductive layer 319 is etched to form wirings 451-458.

[0220] Next, using the resist mask, the third semiconductor layer 469~ is created in the same manner as in "Method 1" above. 473, and a portion of each of the impurity semiconductor layers 443-447 are etched. , a third semiconductor layer 469-473 that functions as a buffer layer, and an impurity semiconductor layer 459-4 67 is formed. After this, the resist mask is removed.

[0221] After removing the resist mask, it is advisable to perform dry etching. Also, the third semiconductor layer 4 You can irradiate surfaces 69-473 with water plasma, ammonia plasma, nitrogen plasma, etc. stomach.

[0222] Next, a second gate insulating layer 371 and insulating layer 372 are formed in the same manner as in "Method 1" described above. (See Figure 23(A)).

[0223] Thin-film transistors can be fabricated through the above process.

[0224] Next, a portion of the second gate insulating layer 371 and insulating layer 372 is etched to form the logic circuit section 3 The wiring 452 of TFT401a and the gate electrode 303, and the wiring 457 of the pixel section 395 are An exposed opening is formed. This opening can be formed by photolithography. Yes, it is possible. Afterwards, the logic circuit section is placed on the insulating layer 372 so that it is connected through the opening. Wiring 384 connects wiring 452 and gate electrode 303 of TFT401a 391, pixel A pixel electrode 383 is formed to connect to the wiring 457 of part 395 (wiring 384 and gate electrode). See Figure 11(A) and Figure 23(B) for the connection of unit 303.

[0225] Wiring 384 connects wiring 452 of TFT 401a in logic circuit section 391 to gate electrode 303. By connecting them, an EDMOS circuit consisting of TFT401a and TFT401b is formed. It is possible.

[0226] (Embodiment 5) In this embodiment, the drawings show a protection circuit provided in a display device, which is one embodiment of the present invention. Refer to the explanation. The protection circuits 134-136 used in Figure 2 of Embodiment 1 A specific example of the circuit configuration of the protection circuit will be explained with reference to Figure 24. In the following explanation, n This explanation will only cover the case where a transistor of a certain type is provided, but the present invention is not limited thereto.

[0227] The protection circuit shown in Figure 24(A) uses a protection diode 501 with multiple thin-film transistors. It has ~504. The protection diode 501 is connected in series with an n-type thin-film transistor 5 It has 01a and n-type thin-film transistor 501b. n-type thin-film transistor 501a One of the source electrode and drain electrode is an n-type thin-film transistor 501a and an n-type thin-film transistor It is connected to the gate electrode of the transistor 501b, and at potential V ss It is maintained in n-type thin film. The source electrode and the other drain electrode of transistor 501a are connected to n-type thin-film transistor 5 It is connected to either the source electrode or the drain electrode of 01b. n-type thin-film transistor 5 The source electrode and the other drain electrode of 01b are connected to the protection diode 502. And the other protection diodes 502 to 504 are the same as protection diode 501, respectively It has multiple thin-film transistors connected in series, and multiple thin-film transistors connected in series. One end of the transistor is connected to the gate electrodes of multiple thin-film transistors.

[0228] Furthermore, in the present invention, each of the protection diodes 501 to 504 has a thin film transient The number and polarity of the diodes are not limited to the configuration shown in Figure 24(A). For example, protection diodes 501 may consist of three thin-film transistors connected in series.

[0229] Furthermore, the protection diodes 501 to 504 are connected in series in order, and the protection diodes The connection between diode 502 and protection diode 503 is made to wiring 505. Note that wiring 50 5 is electrically connected to the semiconductor element to be protected. Note that wiring 50 The wiring connected to 5 is limited to the wiring between protection diode 502 and protection diode 503. It is not done. That is, the wiring 505 is between the protection diode 501 and the protection diode 502. They may be connected, or connected between protection diode 503 and protection diode 504. It's okay if it's not allowed.

[0230] One end of the protection diode 504 is at the power supply potential V dd It is maintained in this state. Also, protection diode 5 Each of the 01-504 pins is connected so that a reverse bias voltage is applied.

[0231] Furthermore, the protection circuit shown in Figure 24(A) includes a protection diode 50 as shown in Figure 24(B). 1. Replace 502 with protection diode 506, and replace protection diodes 503 and 504 with protection diode 506. It can also be replaced with Odor 507.

[0232] The protection circuit shown in Figure 24(C) consists of a protection diode 510, a protection diode 511, and a capacitance element. It has a sub-element 512, a capacitive element 513, and a resistive element 514. The resistive element 514 is a two-terminal resistor. And at one end of it, there is a potential V from wiring 515. in A current is supplied, and the other end has a potential V ss supplied The resistor element 514 is at a potential V in When the power supply is cut off, the potential of wiring 515 V ss It is provided for this purpose, and its resistance value is sufficiently larger than the wiring resistance of wiring 515. Set it so that it works. Protection diodes 510 and 511 are diodes It uses D-connected n-type thin-film transistors.

[0233] Furthermore, the protection diode shown in Figure 24(C) has multiple thin-film transistors connected in series. It may be done in that way.

[0234] The protection circuit shown in Figure 24(D) uses protection diodes 510 and 511, Each of these was replaced with two n-type thin-film transistors.

[0235] Note that the protection circuits shown in Figures 24(C) and 24(D) use a diode as the protection diode. Although this embodiment uses connected n-type thin-film transistors, it is not limited to this configuration. do not have.

[0236] Furthermore, the protection circuit shown in Figure 24(E) consists of protection diodes 520-527 and resistor element 52 It has 8 and . Resistor element 528 is connected in series between wiring 529A and wiring 529B Each of the protection diodes 520-527 is connected to a diode-connected n-type thin-film transistor. It uses a generator.

[0237] Protection diodes 520 and 521 are connected in series, with one end at a potential V s s It is held at the other end, and the other end is at potential V in It is connected to wiring 529A. Protection diode 52 2 and the protection diode 523 are connected in series, with one end at potential V dd It is held at the other end The potential is V in It is connected to wiring 529A. Protection diode 524 and protection diode The 525s are connected in series, with one end at potential V. ss It is held at the other end, and the other end is at potential V out distribution It is connected to line 529B. Protection diodes 526 and 527 are connected in series. They are connected, and one end is at potential V dd It is held at the other end, and the other end is at potential V out Connect to wiring 529B It is being done.

[0238] Furthermore, the protection circuit shown in Figure 24(F) includes a resistor element 530, a resistor element 531, and a protection die. It has an diode 532. In Figure 24(F), the protection diode 532 is a diode. Although this embodiment uses connected n-type thin-film transistors, it is not limited to this configuration. i. Multiple thin-film transistors connected by diodes may be used. Resistor element 530 and The resistor 531 and the protection diode 532 are connected in series with the wiring 533.

[0239] Resistor elements 530 and 531 mitigate rapid fluctuations in the potential of the wiring 533. This can prevent the degradation or destruction of semiconductor elements. Also, the protection diode 532 This prevents reverse bias current from flowing through wiring 533 due to potential fluctuations. It is possible.

[0240] Furthermore, when connecting only resistive elements in series with the wiring, the rapid fluctuations in the wiring's potential are mitigated. This prevents semiconductor elements from degrading or being destroyed. Also, only the protection diode When connecting it in series with the wiring, it prevents reverse current from flowing through the wiring due to potential fluctuations. It is possible.

[0241] Now, let's consider the case where the protection circuit shown in Figure 24 is activated. In this case, the protection diode Source electrodes for D501, 502, 506, 511, 520, 521, 524, 525 and At the drain electrode, the potential V ss The side held by is the drain electrode. The other side is the so - These become electrodes. Protection diodes 503, 504, 507, 510, 522, 523, 5 At source and drain electrodes 26 and 527, the potential V dd The side held by the saw One electrode serves as the drain electrode, and the other as the other electrode. Furthermore, the thin film transient that constitutes the protection diode... The threshold voltage of the sta is V th This indicates.

[0242] Also, protection diodes 501, 502, 506, 511, 520, 521, 524, 52 5 is the potential V in The potential is V ss When the voltage is higher, a reverse bias voltage is applied, making it difficult for current to flow. On the other hand, protection diodes 503, 504, 507, 510, 522, 523, 526, 527 is the potential V in The potential is V dd When the voltage is lower, a reverse bias voltage is applied, and current It doesn't flow easily.

[0243] Here, the potential V out The potential is approximately V ss and potential V dd Protection provided to be between Let's explain how the circuit works.

[0244] First, the potential V in The potential is V dd Let's consider the case where the potential is higher than V. in The potential is V dd Rather If the value is high, use protection diodes 503, 504, 507, 510, 522, 523, 526. The potential difference V between the gate electrode and source electrode of the 527 gs =V in -V dd >V th At that time, The n-type thin-film transistor is turned on. Here, V in This assumes a case where the value is abnormally high. Therefore, the n-type thin-film transistor turns on. At this time, protection diodes 501 and 50 The n-type thin-film transistors that are present in 2, 506, 511, 520, 521, 524, and 525 are Turn it off. Then the protection diodes 503, 504, 507, 510, 522, 5 The electrical wiring 505, 508, 515, 529A, and 529B is connected via 23, 526, and 527. V dd Therefore, the potential V will be affected by noise, etc. in The potential is V dd It is abnormally high compared to Even if that were the case, the potential of wiring 505, 508, 515, 529A, and 529B would be potential V. dd It will never go higher than that.

[0245] On the other hand, potential V in The potential is V ss If the value is lower than that, protection diodes 501, 502, Potential difference between the gate electrode and source electrode of 506, 511, 520, 521, 524, and 525 V gs =V ss -V in >V th At this point, the n-type thin-film transistor turns on. So, V in Since we are assuming an abnormally low value, the n-type thin-film transistor turns on. At this time, protection diodes 503, 504, 507, 510, 522, 523, 526, The n-type thin-film transistor in 527 is turned off. Then the protection diode 501, Wiring 505, 505 via 502, 506, 511, 520, 521, 524, 525 The potentials of 8, 515, 529A, and 529B are V ss Therefore, due to noise, etc., V in The potential is V ss Even if it becomes abnormally low, wiring 505, 508, 515, 52 The potentials of 9A and 529B are, ss It will never be lower than that. Furthermore, the capacitive element 51 2. 513 is the input potential V inIt blunts the pulse-like noise it possesses, and the potential caused by the noise It helps to mitigate abrupt changes.

[0246] Note that potential V in However, V ss -V th From V dd +V th In the case of all protection The n-type thin-film transistor in the diode turns off, and the potential V in The potential is V out year It will be output.

[0247] As explained above, by placing the protection circuit, wiring 505, 508, 515, 529A The potential of 529B is approximately the potential V ss and potential V dd It will be maintained between these two points. Therefore, Wirings 505, 508, 515, 529A, and 529B are at a potential that falls significantly outside this range. This can prevent the following: wiring 505, 508, 515, 529A, 52 To prevent 9B from becoming abnormally high or abnormally low in potential, and to prevent the downstream stage of the protection circuit This prevents the circuit from being damaged or degraded, and protects the subsequent circuitry.

[0248] Furthermore, as shown in Figure 24(C), a protection circuit having a resistive element 514 is provided at the input terminal. By doing so, when no signal is input, the potential of all wiring to which a signal is supplied remains constant. (Here, the potential V ss ) can be set to: In other words, when no signal is input, It also functions as a shorting ring, which can short-circuit wires. Therefore, This prevents electrostatic discharge damage caused by potential differences between wires. Also, the resistive element 51 Since the resistance value of 4 is sufficiently large with respect to the wiring resistance, when a signal is input, it is possible to prevent the signal applied to the wiring from dropping to the potential V. signal from dropping to the potential V ss up to.

[0249] Here, as an example, the case of using the protection diodes 510 and 511 in FIG. 24(C) will be described. threshold voltage V th =0 n-type thin film transistor will be described.

[0250] First, when V in >V dd , the protection diode 510 is V gs =V in -V dd >0 and turns on. The protection diode 511 turns off. Therefore, the potential of the wiring 515 is V d d and V out =V dd results.

[0251] On the other hand, when V in <V ss , the protection diode 510 turns off. The protection diode 511 is V gs =V ss -V in >0 and turns on. Therefore, the potential of the wiring 515 is V ss and V out =V ss results.

[0252] Thus, even when V in <V ss or V dd <V in , it can operate within the range of V ss <V o ut <V dd . Therefore, even when V in is excessive or too small in the case, even when Vout This can prevent the value from becoming excessive or insufficient. Therefore, for example, due to noise, the potential V in The potential is V ss Even if it becomes lower The potential of wiring 515 is potential V ss It will never be any lower than that. Furthermore, capacitive elements 512 and the capacitive element 513 are connected to the input potential V in It blunts the pulsed noise it possesses, and the potential It works to mitigate the abrupt changes.

[0253] As explained above, by placing the protection circuit, the potential of wiring 515 becomes potential V ss and electric potential V dd This will generally be maintained within this range. Therefore, if wiring 515 deviates significantly from this range... This prevents the potential from becoming V, and the circuit after the protection circuit (input section is V out It can protect the electrically connected circuit from damage or degradation. Furthermore, the input By providing a protection circuit at the terminal, when no signal is input, all of the applied signal will be blocked. The potential of the wiring is kept constant (here, potential V). ss ) can be kept. In other words, the signal is input When not in use, it functions as a shorting ring that can short-circuit wires together. It also has the ability to prevent electrostatic discharge caused by potential differences between wires. Also, since the resistance value of resistor element 514 is sufficiently large, when a signal is input, wiring 515 This prevents a decrease in the potential of the signal applied to it.

[0254] Furthermore, the protection circuit used in the present invention is not limited to the configuration shown in Figure 24, and similar If the circuit configuration performs this function, the design can be modified as needed.

[0255] Furthermore, the protection diode in the protection circuit of the present invention is a diode-connected thin film diode. A transistor can be used. By using the thin-film transistor of the present invention in the protection circuit... This reduces the area occupied by the protection circuit, enabling narrower bezels, smaller size, and higher performance of the display device. It is possible to measure this.

[0256] (Embodiment 6) In this embodiment, the terminal portion of the display device of the present invention will be described with reference to Figure 25.

[0257] Figures 25(A) and 25(B) show a cross-sectional view and a top view of the gate wiring terminal section, respectively. Figure 25(A) corresponds to the cross-sectional view along the line X1-X2 in Figure 25(B). Figure 2 In 5(A), the transparent conductive layer 545 on the laminated protective insulating layer 544 is This is a terminal electrode that functions as a force terminal. Also, in Figure 25(A), the terminal part is a gauge A first terminal 540 formed from the same material as the source wiring, and a first terminal 540 formed from the same material as the source wiring The connecting electrode 543 and the gate insulating layer 542 overlap, and these are connected via the transparent conductive layer 545. They are connected (at least electrically). Also, the gate insulating layer 542 and the connecting electrode 54 Between 3 and 546 is a semiconductor layer 546 (an intrinsic semiconductor layer and a semiconductor layer containing a single-conductivity impurity element). It is provided.

[0258] Figures 25(C) and 25(D) show a cross-sectional view and a top view of the source wiring terminal section, respectively. Figure 25(C) corresponds to the cross-sectional view along the Y1-Y2 line in Figure 25(D). In 5(C), the transparent conductive layer 545 on the laminated protective insulating layer 544 is This is a terminal electrode that functions as a force terminal. Also, in Figure 25(C), the terminal part is a gauge Electrode 547, formed from the same material as the source wiring, is connected (at least electrically) to the source wiring. The second terminal 541 is superimposed below the gate insulating layer 542. Electrode 547 is second The electrode 547 is not directly or electrically connected to terminal 541, and the electrode 547 is not connected to the second terminal 541. Setting to different potentials, such as floating, GND, 0V, etc., can help with noise suppression. Capacitance or capacitance for electrostatic discharge protection can be formed. Also, the second terminal 541 , is connected (at least electrically) to the transparent conductive layer 545. Also, the gate insulating layer 54 Between terminal 2 and the second terminal 541 is a semiconductor layer 546 (an intrinsic semiconductor layer and a single conductive impurity element). A semiconductor layer (including a semiconductor layer) is provided.

[0259] Gate wiring, source wiring, and capacitive wiring are provided in multiples depending on the pixel density. Furthermore, at the terminal section, the first terminal is at the same potential as the gate wiring, and the source wiring is at the same potential as the first terminal. Multiple terminals are arranged in a row, including a second terminal and a third terminal at the same potential as the capacitance wiring. The number of these terminals may be any number, and the implementer may decide as appropriate.

[0260] The terminal section and the FPC terminal section described in this embodiment are connected via anisotropic conductive paste or the like. This allows for the supply of signals and power from external sources.

[0261] Note that Figure 25 shows the terminal section when manufactured using a halftone mask, The invention is not limited to the embodiments described above. Figure 26 shows a diagram of the terminal section when manufactured using Izu.

[0262] Figures 26(A) and 26(B) show the gate when fabricated without using a halftone mask. Figure 26(A) shows a cross-sectional view and a top view of the wiring terminal section, respectively. This corresponds to a cross-sectional view along the X3-X4 line. In Figure 26(A), on the protective insulating layer 544 The transparent conductive layer 545 is a terminal electrode that functions as an input terminal. Also, as shown in Figure 26(A) In the terminal section, there is a first terminal 540 formed of the same material as the gate wiring, and a source wiring The connecting electrode 543, which is made of the same material, overlaps with the gate insulating layer 542, and these They are connected (at least electrically) via the transparent conductive layer 545. Also, gate insulation A connecting electrode 543 is provided in contact with layer 542, as shown in Figures 26(A) and 26(B). The configuration does not include a semiconductor layer.

[0263] Figures 26(C) and 26(D) show the source when created without using a halftone mask. Figure 26(C) shows a cross-sectional view and a top view of the wiring terminal section, respectively. This corresponds to the cross-sectional view along the Y3-Y4 line. In Figure 26(C), on the protective insulating layer 544 The transparent conductive layer 545 is a terminal electrode that functions as an input terminal. Also, in Figure 26(C) In the terminal section, the electrode 547, which is made of the same material as the gate wiring, is connected to the source wiring. Below the second terminal 541, which is connected (at least electrically), via the gate insulating layer 542 They overlap. Electrode 547 is not connected to the second terminal 541, and electrode 547 is connected to the second terminal 5 Setting it to a different potential than 41, such as floating, GND, 0V, etc., will reduce noise. It can form a capacitance for static electricity protection or a capacitance for static electricity protection. Also, the second terminal 5 41 is connected to the transparent conductive layer 545. Also, a second is in contact with the gate insulating layer 542. A terminal 541 is provided, and Figures 26(C) and 26(D) show that a semiconductor layer is provided. The configuration does not include a semiconductor layer. In other words, the terminal section shown in Figure 26 does not have a semiconductor layer. That's how it is.

[0264] (Embodiment 7) Next, the display panel mounted on the liquid crystal display device and light-emitting display device described in the above embodiment Alternatively, one form of the light-emitting panel will be described with reference to the drawings (cross-sectional view).

[0265] For an appearance of a liquid crystal display device and a light-emitting device according to one aspect of the present invention, please refer to Figures 27 and 28. Let me explain. Figure 27(A) shows a microcrystalline semiconductor layer formed on the first substrate 601. A thin-film transistor 610 and liquid crystal element 613 are placed between the second substrate 606 and a sealing material. Figure 27(B) shows a top view of a liquid crystal display panel sealed with 605. This corresponds to a cross-sectional view in KL.

[0266] A liquid crystal display device has a liquid crystal element in each pixel. A liquid crystal element is formed by the optical modulation effect of liquid crystals. It is an element that controls the transmission or non-transmission of light, and is composed of a pair of electrodes and liquid crystal. Furthermore, the optical modulation effect of liquid crystals is due to the electric field applied to the liquid crystal (horizontal electric field, vertical electric field, etc.). It is controlled by an electric field (including an electric field in an oblique direction). Furthermore, the liquid crystal element and its driving mode are For example, nematic liquid crystal, cholesteric liquid crystal, smectic liquid crystal, discotic liquid crystal, Thermotropic liquid crystals, lyotropic liquid crystals (also called lyotropic liquid crystals), low molecular weight Liquid crystal, polymer liquid crystal, ferroelectric liquid crystal, antiferroelectric liquid crystal, main chain liquid crystal, side chain polymer liquid crystal, plasma MA-Dress LCD (PALC), banana-shaped LCD, TN (Twisted Nematic) Mode, STN (Super Twisted Nematic) mode, IPS (In -Plane-Switching) mode, FFS (Fringe Field Switch) itching) mode, MVA (Multi-domain Vertical Al ignition) mode, PVA (Patterned Vertical Align ment), ASV (Advanced Super View) mode, ASM (Ax ally Symmetric aligned Micro-cell) mode, O CB (Optical Compensated Birefringence) mode ,ECB(Electrically Controlled Birefringen) ce) mode, FLC (Ferroelectric Liquid Crystal) Mode, AFLC (AntiFerroelectric Liquid Crysta) l) Mode, PDLC (Polymer Dispersed Liquid Crystals) You can use modes such as TAL mode, guest host mode, etc. However, you are not limited to these. Furthermore, various materials can be used as liquid crystal elements.

[0267] The liquid crystal layer may be formed using a liquid crystal that exhibits a blue phase without using an alignment film. It is one of the crystal phases, and as cholesteric liquid crystal is heated, it changes from the cholesteric phase to the isotropic phase. This is the phase that appears just before the transition to the next phase. The blue phase is only expressed within a narrow temperature range. To improve the temperature range, a liquid crystal composition containing 5% by weight or more of a chiral agent is used. Applied to a liquid crystal layer. A liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent has a response speed of With a short exposure time of 10 μs to 100 μs and optically isotropic, orientation processing is unnecessary, and the field of view is It has low addictive potential.

[0268] Surrounding the pixel section 602 and the scanning line driving circuit 604 provided on the first substrate 601, A material 605 is provided. In addition, a second A substrate 606 is provided. Therefore, the pixel unit 602 and the scan line driving circuit 604 are The first substrate 601, the sealing material 605, and the second substrate 606 seal together with the liquid crystal layer 608. It is stopped. Also, within the area surrounded by the sealing material 605 on the first substrate 601 A signal line drive circuit 603 is also provided. Note that the signal line drive circuit 603 is prepared separately. It is provided by a thin-film transistor having a polycrystalline semiconductor layer on a substrate. Alternatively, a signal line driving circuit can be formed using a transistor made of a single crystal semiconductor and bonded together. You may do so.

[0269] The pixel section 602 provided on the first substrate 601 has a plurality of thin-film transistors. Figure 27(B) illustrates a thin-film transistor 610 included in the pixel section 602. Furthermore, the scan line drive circuit 604 also has multiple thin-film transistors, as shown in Figure 27(B). This illustrates the thin-film transistor 609 included in the signal line driving circuit 603. The 610 transistor is equivalent to a thin-film transistor using a microcrystalline semiconductor layer.

[0270] Furthermore, the pixel electrode 612 of the liquid crystal element 613 is connected to the thin-film transistor 610 and the wiring 618 They are electrically connected via. Furthermore, wiring 618 is electrically connected to routing wiring 614. They are connected. The counter electrode 617 of the liquid crystal element 613 is provided on the second substrate 606. The portion where the pixel electrode 612, the counter electrode 617, and the liquid crystal layer 608 overlap is liquid. This corresponds to the crystal element 613.

[0271] The materials for the first substrate 601 and the second substrate 606 include glass, metal (typically) Stainless steel, ceramics, or plastic can be used. As for the term, FRP (Fiberglass-Reinforced Plastics) ) board, PVF (polyvinyl fluoride) film, polyester film, or acrylic A voll resin film or the like can be used. In addition, aluminum foil can be used with a PVF film. Alternatively, a sheet with a structure sandwiched between polyester films may be used.

[0272] Furthermore, the spacer 611 is a bead spacer, and is located between the pixel electrode 612 and the counter electrode 617. It is provided to keep the distance (cell gap) constant. Note that spacer 611 Instead of the bead spacer, a spacer obtained by selectively etching the insulating layer ( Post-spacers may be used.

[0273] Furthermore, the signal line drive circuit 603 and the scan line drive circuit 604 and the pixel unit 602 each provide The signal (potential) of the FPC607 (Flexible Printed Circuit) is It is supplied via the wiring 614 from t).

[0274] In this embodiment, the connection terminal 616 has the same lead as the pixel electrode 612 of the liquid crystal element 613. It is formed from an electrical layer. Also, the routing wiring 614 is formed from the same conductive layer as the wiring 618. It is being done.

[0275] The connection terminal 616 and the terminals of the FPC 607 are electrically connected via the anisotropic conductive layer 619. It continues.

[0276] Although not shown in the figures, the liquid crystal display device shown in this embodiment includes an alignment film and a polarizing plate. Furthermore, it may have a color filter, a light-shielding layer, or the like.

[0277] Furthermore, polarizing plates, circular polarizing plates (including elliptical polarizing plates), and phase difference plates (λ / 4 plates) are used on the emission surface of the light-emitting element. A polarizing plate (λ / 2 plate) or an optical film such as a color filter may be provided as appropriate. Alternatively, an anti-reflective layer may be provided on the circular polarizing plate.

[0278] Figure 28 shows an example of a light-emitting device according to one aspect of the present invention. Figure 28 differs from Figure 27 in some respects. Only the relevant part is labeled with a symbol. Electroluminescence is used as the light-emitting device. A light-emitting element is used. A light-emitting element that utilizes electroluminescence uses an organic light-emitting material. They are distinguished by whether they are chemical compounds or inorganic compounds; generally, the former are organic EL elements. The latter is called an inorganic EL element.

[0279] Organic EL elements work by applying a voltage to the light-emitting element, which causes carriers (electrons and holes) to... A pair of electrodes injects a luminescent organic compound into a layer containing it, and an electric current flows through it. Then, The recombination of these carriers (electrons and holes) excites the luminescent organic compound. It forms a state, and emits light when its carriers return from the excited state to the ground state. Based on its mechanism, optical elements are called current-excited light-emitting devices.

[0280] Inorganic electroluminescent (EL) elements are classified into dispersed inorganic EL elements and thin-film inorganic EL elements based on their element configuration. They are classified as such. Dispersive inorganic EL elements have a light-emitting layer in which particles of light-emitting material are dispersed in a binder. The luminescence mechanism utilizes donor and acceptor levels in a donor-acceptor regeneration process. It is a coupled light emission. Thin-film inorganic EL elements sandwich the light-emitting layer between dielectric layers, and further... It has a structure sandwiched between a pair of electrodes, and the light emission mechanism utilizes the inner-shell electron transitions of metal ions. It is localized luminescence.

[0281] In this explanation, we will use an organic EL element as the light-emitting element. Furthermore, the driving of the light-emitting element will be explained. The fabrication method described in the above embodiment was applied to the thin-film transistor that controls the above. This will be explained using thin-film transistors.

[0282] First, thin-film transistors 621 and 622 are formed on the substrate. Thin-film transistor 621, An insulating layer, which functions as a protective layer, is formed on 622. This insulating layer is formed of an inorganic material. It is often formed by laminating an insulating layer 623 made of organic material and an insulating layer 624 made of organic material. The upper surface is flattened by an insulating layer formed of organic material. Here, inorganic material and For example, silicon oxide, silicon nitride, silicon oxide-nitride, etc., can be used. The materials include organic resins such as acrylic, polyimide, or polyamide, or siloxane. It is recommended to use this.

[0283] A conductive layer is provided on the insulating layer 624 formed of an organic material. This conductive layer is the first conductive layer Let the electrode layer be 625. The first conductive layer functions as a pixel electrode. Pixel thin-film transistor In the case of an n-type thin-film transistor, it is preferable to form a cathode as the pixel electrode, In the case of a p-type thin-film transistor, it is preferable to form an anode. The cathode is used as the pixel electrode. When forming it, use materials with a small work function, such as Ca, Al, MgAg, AlLi You can use the following:

[0284] Next, the side (edge) of the first conductive layer 625 and the insulating layer 624 formed by the organic material A partition wall 626 is formed therein. The partition wall 626 has an opening, and the first conductive layer 6 25 is exposed. The partition wall 626 is made of an organic resin layer, an inorganic insulating layer or an organic polysilicone. Formed using sun. Particularly preferably, a partition is formed using a photosensitive material, and the first guide By exposing the partition wall 626 on the electrolytic layer 625 to form an opening, the side walls of the opening become continuous. It is preferable to form the inclined surface with a curvature.

[0285] Next, the light-emitting layer 627 is placed in contact with the first conductive layer 625 at the opening of the partition wall 626. To form. The light-emitting layer 627 may be composed of a single layer, or it may be composed of multiple layers stacked together. It's okay if it's not allowed.

[0286] Then, a second conductive layer 628 is formed so as to cover the light-emitting layer 627. 8 is called the common electrode. When the first conductive layer 625 is formed by the cathode material, the anode A second conductive layer 628 is formed using a material. The second conductive layer 628 is a transparent conductive material. It can be formed with a translucent conductive layer using a suitable material. As the second conductive layer 628, nitride A titanium layer or a titanium layer may be used. Here, as the second conductive layer 628, indigo ITO is used. At the opening of the partition wall, the first conductive layer 625 and the light-emitting layer 6 The light-emitting element 630 is formed when 27 and the second conductive layer 628 overlap. After this, To prevent oxygen, hydrogen, moisture, or carbon dioxide from entering the light-emitting element 630, a partition wall 626 It is preferable to form a protective layer on the second conductive layer 627. The protective layer may be made of nitride A silicon dioxide layer, silicon nitride layer, and DLC layer can be used. More preferably, A protective film with high airtightness and minimal degassing to prevent exposure to the outside air (UV-curing resin film) Further packaging (sealing) is performed using film or other covering material.

[0287] The light-emitting element 630 has at least one of its electrodes, either the anode or the cathode, that is transparent in order to extract light. Then, thin-film transistors 621, 622 and light-emitting element 630 are formed on the substrate. Furthermore, it has a top-surface emission structure that extracts light from the side opposite to the substrate, and a structure that extracts light from the side facing the substrate. Bottom injection structure, and double-sided injection structure that extracts light from both the substrate side and the side opposite the substrate. There is a light-emitting element. In a light-emitting device according to one aspect of the present invention, any of the above injection structures is suitable It can be used.

[0288] In the light-emitting element 630 with an upper surface injection structure, the light-emitting layer and the anode are stacked sequentially on the cathode. The cathode is made of a conductive material with a small work function and that reflects light (e.g., Ca, Al, Mg). It can be formed using materials such as Ag or AlLi. The light-emitting layer is composed of multiple layers. In some cases, for example, an electron injection layer, electron transport layer, light emission layer, hole transport layer, or hole layer may be placed on the cathode. The layers are formed by stacking them in the order of injection-treated layers. Note that it is not necessary to provide all of these layers. The anode is Formed using a light-transmitting conductive material, for example, an in which tungsten oxide is included. Indium zinc oxide containing zinc oxide, tungsten oxide, and titanium oxide Indium oxide, titanium oxide-containing indium tin oxide, indium tin oxide (ITO), Translucent indium tin oxide, such as indium zinc oxide or silicon oxide. A conductive layer may also be used. The light generated from the light-emitting layer is emitted towards the anode.

[0289] In the bottom-extrusion-type light-emitting element 630, the light-emitting layer and the anode are stacked sequentially on the cathode. Oh, if the anode is translucent, a light-shielding layer is used to reflect or block light so as to cover the anode. It is preferable that such a feature be provided. The cathode should be made of a material with a small work function, similar to the case of the top-surface injection structure. Any conductive layer formed by [the specified method] will suffice, and known materials may be used. However, its thickness is The light transmittance should be approximately 5 nm to 30 nm. For example, 20 nm. Aluminum with a thickness of m can be used as the cathode. And the light-emitting layer is Similar to the case of top-surface injection molding, even if it consists of a single layer, it is constructed by stacking multiple layers. It may be done. The anode does not need to transmit light, but as in the case of a top-surface injection structure, It can also be formed using a photosensitive conductive material. The light-shielding layer, for example, reflects light. A metal layer or a resin with black pigment added may be used. Light emitted from the light-emitting layer It is emitted towards the cathode.

[0290] Furthermore, the pixel electrodes of the light-emitting element 630 are the source electrodes of the thin-film transistor 622 or The drain electrode is electrically connected via wiring. And in this embodiment, The common electrode of the optical element 630 is electrically connected to a transparent, conductive material layer.

[0291] Furthermore, the configuration of the light-emitting element 630 is not limited to the configuration shown in this embodiment. The configuration of 30 includes the direction of light extracted from the light-emitting element 630 and the polarity of the thin-film transistor 622. It can be modified as needed to suit various circumstances.

[0292] Furthermore, if the light-emitting element 630 has an upper surface emission structure, the direction of light extraction from the light-emitting element 630 The second substrate, which is the substrate to which it is located, must be a translucent substrate. In that case, glass Light-transmitting materials such as steel plates, plastic plates, polyester films, or acrylic films. A substrate made of the specified material is used.

[0293] Furthermore, the filler material 631 placed between the two substrates may be an inert gas such as nitrogen or argon. UV-curing resins or thermosetting resins can be used, and PVC (polyvinyl chloride) can be used. ), acrylic, polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral ) or EVA (ethylene vinyl acetate), etc. can be used. Here, for example Nitrogen is a good choice.

[0294] In this embodiment, the thin-film transistor 622 (driver) controls the driving of the light-emitting element 630. An example was shown in which the dynamic transistor and the light-emitting element are directly connected, but the driving thin film A thin-film transistor for current control may be connected between the transistor and the light-emitting element.

[0295] Furthermore, the light-emitting device described in this embodiment is not limited to the illustrated configuration, and technical aspects may be considered. Various modifications are possible based on the underlying principles.

[0296] This embodiment can be implemented in combination with the configurations described in other embodiments.

[0297] (Embodiment 8) The semiconductor device having a thin-film transistor according to the present invention can be used in various electronic devices (including amusement machines). It can be applied to (m). Examples of electronic devices include television equipment (television, (Also called a television receiver), computer monitor, electronic paper, digital Cameras, digital video cameras, digital photo frames, mobile phones (mobile phones, portable cameras) (Also known as mobile phone equipment), portable game consoles, personal digital assistants, sound playback devices, pachinko machines, etc. Examples include large game consoles.

[0298] The semiconductor device having a thin-film transistor according to the present invention can be applied to electronic paper. Electronic paper can be used in electronic devices in any field that displays information. This is possible. For example, using e-paper, ebooks, posters, This applies to advertisements inside trains and other vehicles, displays on various cards such as credit cards, etc. This is possible. An example of an electronic device is shown in Figure 29.

[0299] Figure 29(A) shows an example of an e-book. The e-book shown in Figure 29(A) has a housing 7 It consists of two housings, housing 00 and housing 701. Housings 700 and 701 are connected by hinges. 704 integrates them, allowing for opening and closing operations. This configuration allows for... It will be possible to perform actions similar to those of a physical book.

[0300] The display unit 702 is incorporated into the housing 700, and the display unit 703 is incorporated into the housing 701. The display units 702 and 703 may be configured to display a continuation screen, or they may be configured differently. It is also possible to configure the system to display a different screen. By configuring the system to display different screens, for example, the right Text is displayed on the side display unit (display unit 702 in Figure 29(A)), and the display unit on the left side (Figure 29( In A), an image can be displayed on the display unit 703).

[0301] Furthermore, Figure 29(A) shows an example in which the housing 700 is equipped with an operating section, etc. The 700 is equipped with a power input terminal 705, operation keys 706, speaker 707, etc. Pages can be turned using key 706. Note that the keyboard and other components are located on the same surface as the display unit of the casing. The configuration may include a pointing device, etc. Furthermore, the back or sides of the casing may have external Terminals for connecting various cables (earphone jack, USB terminal, and USB cable). The configuration may include terminals, recording media insertion section, etc. Furthermore, Figure 29(A) The e-book shown may also be configured to function as an electronic dictionary.

[0302] Furthermore, the e-book shown in Figure 29(A) may also have a configuration that allows information to be sent and received wirelessly. By wireless communication, you can purchase and download desired book data, etc., from an e-book server. It can also be configured in this way.

[0303] Figure 29(B) shows an example of a digital photo frame. For example, Figure 29(B) The digital photo frame shown has a display unit 712 integrated into the housing 711. The unit 712 is capable of displaying various images, for example, images taken with a digital camera. By displaying the image data, it can function just like a regular photo frame.

[0304] The digital photo frame shown in Figure 29(B) includes an operating unit and an external connection terminal (USB). It is equipped with terminals, terminals that can connect to various cables such as USB cables, a recording medium insertion section, etc. The configuration shall be such that these components may be incorporated on the same surface as the display unit, but may also be on the sides or back. Placing it on the surface is preferable because it improves the design. For example, the markings on a digital photo frame. Insert a memory device containing image data taken with a digital camera into the recording medium insertion slot and the image will be displayed. The system can capture data and display the captured image data on the display unit 712.

[0305] Furthermore, the digital photo frame shown in Figure 29(B) has a configuration that allows it to send and receive information wirelessly. It is also possible to configure the system to acquire and display desired image data wirelessly. Cut.

[0306] Figure 29(C) shows an example of a television setup. The device has a display unit 722 incorporated into the housing 721. The display unit 722 displays the video. It is possible to display this. Also, here the stand 723 supports the housing 721. The configuration is shown. The display unit 722 is configured to use the display device shown in Embodiment 7. can.

[0307] The television equipment shown in Figure 29(C) is operated using the operation switches provided on the housing 721, and separate It can be done using a remote control device on the body. The operation keys on the remote control device allow you to... It is possible to control the channel and volume, and to control the image displayed on the display unit 722. This is possible. Furthermore, the remote control unit can display the information output from the remote control unit. A display unit may also be included in the configuration.

[0308] The television system shown in Figure 29(C) is configured to include a receiver, modem, and other components. The receiver can receive regular television broadcasts, and furthermore, it can receive them via a modem via wired connection. By connecting to a wireless communication network, it enables one-way communication (from sender to receiver) and It is also possible to communicate information in both directions (between a sender and receiver, or between receivers, etc.). be.

[0309] Figure 29(D) shows an example of a mobile phone. The mobile phone shown in Figure 29(D) has a casing. In addition to the display unit 732 incorporated into the body 731, there are operation buttons 733 and 737, and external It is equipped with connection ports 734, a speaker 735, and a microphone 736, etc.

[0310] The mobile phone shown in Figure 29(D) has a touch panel display unit 732, which allows for contact with fingers, etc. The display content of the display unit 732 can be operated by touch. In addition, telephone calls can be made, or Emails and other similar actions can be performed by touching the display unit 732 with a finger or the like.

[0311] The display unit 732 has three main modes. The first is a display that primarily displays images. The first mode is an input mode, and the second is an input mode primarily for entering information such as characters. The third is a display mode. This is a display + input mode, which is a combination of two modes: display and input mode.

[0312] For example, when making a phone call or composing an email, the display unit 732 is primarily used for text input. In this text input mode, you can simply input the characters displayed on the screen. This involves using most of the screen of the display unit 732 to display a keyboard or number buttons. This is preferable.

[0313] Furthermore, the mobile phone shown in Figure 29(D) has a gyroscope, accelerometer, and other sensors inside that detect tilt. By installing a detection device equipped with a sensor, the orientation (vertical or horizontal) of the mobile phone can be determined. Furthermore, the display unit 732 can be configured to automatically switch the displayed information.

[0314] Furthermore, the screen mode can be switched by touching the display unit 732 or by pressing the operation button on the housing 731. This is done by operating 737. Also, depending on the type of image displayed on the display unit 732, the cut It is also possible to change the configuration. For example, if the image signal displayed on the display unit is video data If it's text data, you can switch to display mode; if it's text data, you can switch to input mode.

[0315] Furthermore, in input mode, the signal detected by the optical sensor of the display unit 732 is detected, and the display unit If there is no touch input on the 732 for a certain period of time, the screen mode will switch from input mode. You may also control the system to switch to display mode.

[0316] The display unit 732 can also function as an image sensor. For example, the display unit 732 By touching the device with the palm or fingers, the palm print and fingerprints are captured by an image sensor to perform identity verification. This is possible. In addition, the display unit has a backlight that emits near-infrared light or a backlight that emits near-infrared light. By using a sensing light source, it is also possible to image finger veins, palmar veins, etc.

[0317] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. That is the case.

Claims

1. It has first to sixth transistors, The source electrode or drain electrode of the first transistor is always in electrical contact with the gate wiring. The source electrode or the other drain electrode of the first transistor is always in contact with the clock signal line. The source electrode or drain electrode of the second transistor is always in electrical contact with the gate wiring. The source electrode or the other drain electrode of the second transistor is always in electrical contact with the first power line. Either the source electrode or the drain electrode of the third transistor is always in electrical contact with the gate electrode of the second transistor. The source electrode or the other drain electrode of the third transistor is always in electrical contact with the first power line. The gate electrode of the third transistor is always in electrical contact with the gate electrode of the first transistor. The source electrode or drain electrode of the fourth transistor is always in electrical contact with the gate electrode of the first transistor. The source electrode or the other drain electrode of the fourth transistor is always in electrical contact with the first power line. The gate electrode of the fourth transistor is always in electrical contact with the gate electrode of the second transistor. The source electrode or drain electrode of the fifth transistor is always in electrical contact with the gate electrode of the first transistor. The source electrode or the other drain electrode of the fifth transistor is always in electrical contact with the second power line. The gate electrode of the fifth transistor is always in conductivity with the first signal line. The source electrode or drain electrode of the sixth transistor is always in electrical contact with the gate electrode of the first transistor. The source electrode or the other drain electrode of the sixth transistor is always in electrical contact with the first power line. The gate electrode of the sixth transistor is always in conductivity with the second signal line. The first conductive layer, which functions as the gate electrode of the second transistor, is always electrically connected to the third conductive layer, which functions as the gate electrode of the fourth transistor, via the second conductive layer, which functions as either the source electrode or the drain electrode of the third transistor. A semiconductor device having a region in which the second conductive layer intersects with a fourth conductive layer that functions as the gate electrode of the third transistor.

2. It has first to sixth transistors, The source electrode or drain electrode of the first transistor is always in electrical contact with the gate wiring. The source electrode or the other drain electrode of the first transistor is always in contact with the clock signal line. The source electrode or drain electrode of the second transistor is always in electrical contact with the gate wiring. The source electrode or the other drain electrode of the second transistor is always in electrical contact with the first power line. Either the source electrode or the drain electrode of the third transistor is always in electrical contact with the gate electrode of the second transistor. The source electrode or the other drain electrode of the third transistor is always in electrical contact with the first power line. The gate electrode of the third transistor is always in electrical contact with the gate electrode of the first transistor. The source electrode or drain electrode of the fourth transistor is always in electrical contact with the gate electrode of the first transistor. The source electrode or the other drain electrode of the fourth transistor is always in electrical contact with the first power line. The gate electrode of the fourth transistor is always in electrical contact with the gate electrode of the second transistor. The source electrode or drain electrode of the fifth transistor is always in electrical contact with the gate electrode of the first transistor. The source electrode or the other drain electrode of the fifth transistor is always in electrical contact with the second power line. The gate electrode of the fifth transistor is always in conductivity with the first signal line. The source electrode or drain electrode of the sixth transistor is always in electrical contact with the gate electrode of the first transistor. The source electrode or the other drain electrode of the sixth transistor is always in electrical contact with the first power line. The gate electrode of the sixth transistor is always in conductivity with the second signal line. The first conductive layer, which functions as the gate electrode of the second transistor, is always electrically connected to the third conductive layer, which functions as the gate electrode of the fourth transistor, via the second conductive layer, which functions as either the source electrode or the drain electrode of the third transistor. The second conductive layer has a region that intersects with the fourth conductive layer which functions as the gate electrode of the third transistor. A semiconductor device having a fifth conductive layer that functions as the other source electrode or drain electrode of the second transistor, and which functions as the other source electrode or drain electrode of the third transistor, the other source electrode or drain electrode of the fourth transistor, and the other source electrode or drain electrode of the sixth transistor.

3. It has first to sixth transistors, The source electrode or drain electrode of the first transistor is always in electrical contact with the gate wiring. The source electrode or the other drain electrode of the first transistor is always in contact with the clock signal line. The source electrode or drain electrode of the second transistor is always in electrical contact with the gate wiring. The source electrode or the other drain electrode of the second transistor is always in electrical contact with the first power line. Either the source electrode or the drain electrode of the third transistor is always in electrical contact with the gate electrode of the second transistor. The source electrode or the other drain electrode of the third transistor is always in electrical contact with the first power line. The gate electrode of the third transistor is always in electrical contact with the gate electrode of the first transistor. The source electrode or drain electrode of the fourth transistor is always in electrical contact with the gate electrode of the first transistor. The source electrode or the other drain electrode of the fourth transistor is always in electrical contact with the first power line. The gate electrode of the fourth transistor is always in electrical contact with the gate electrode of the second transistor. The source electrode or drain electrode of the fifth transistor is always in electrical contact with the gate electrode of the first transistor. The source electrode or the other drain electrode of the fifth transistor is always in electrical contact with the second power line. The gate electrode of the fifth transistor is always in conductivity with the first signal line. The source electrode or drain electrode of the sixth transistor is always in electrical contact with the gate electrode of the first transistor. The source electrode or the other drain electrode of the sixth transistor is always in electrical contact with the first power line. The gate electrode of the sixth transistor is always in conductivity with the second signal line. The first conductive layer, which functions as the gate electrode of the second transistor, is always electrically connected to the third conductive layer, which functions as the gate electrode of the fourth transistor, via the second conductive layer, which functions as either the source electrode or the drain electrode of the third transistor. The second conductive layer has a region that intersects with the fourth conductive layer which functions as the gate electrode of the third transistor. A semiconductor device having a fifth conductive layer that functions as either the source electrode or the drain electrode of the fourth transistor, and a fifth conductive layer that functions as either the source electrode or the drain electrode of the fifth transistor, and a sixth conductive layer that functions as either the source electrode or the drain electrode of the sixth transistor.

4. It has first to sixth transistors, The source electrode or drain electrode of the first transistor is always in electrical contact with the gate wiring. The source electrode or the other drain electrode of the first transistor is always in contact with the clock signal line. The source electrode or drain electrode of the second transistor is always in electrical contact with the gate wiring. The source electrode or the other drain electrode of the second transistor is always in electrical contact with the first power line. Either the source electrode or the drain electrode of the third transistor is always in electrical contact with the gate electrode of the second transistor. The source electrode or the other drain electrode of the third transistor is always in electrical contact with the first power line. The gate electrode of the third transistor is always in electrical contact with the gate electrode of the first transistor. The source electrode or drain electrode of the fourth transistor is always in electrical contact with the gate electrode of the first transistor. The source electrode or the other drain electrode of the fourth transistor is always in electrical contact with the first power line. The gate electrode of the fourth transistor is always in electrical contact with the gate electrode of the second transistor. The source electrode or drain electrode of the fifth transistor is always in electrical contact with the gate electrode of the first transistor. The source electrode or the other drain electrode of the fifth transistor is always in electrical contact with the second power line. The gate electrode of the fifth transistor is always in conductivity with the first signal line. The source electrode or drain electrode of the sixth transistor is always in electrical contact with the gate electrode of the first transistor. The source electrode or the other drain electrode of the sixth transistor is always in electrical contact with the first power line. The gate electrode of the sixth transistor is always in conductivity with the second signal line. The first conductive layer, which functions as the gate electrode of the second transistor, is always electrically connected to the third conductive layer, which functions as the gate electrode of the fourth transistor, via the second conductive layer, which functions as either the source electrode or the drain electrode of the third transistor. The second conductive layer has a region that intersects with the fourth conductive layer which functions as the gate electrode of the third transistor. The fifth conductive layer, which functions as the source electrode or drain electrode of the fifth transistor, is always in electrical contact with the sixth conductive layer, which functions as the second power line. The fifth conductive layer has a region in contact with the semiconductor layer having the channel formation region of the fifth transistor. A semiconductor device having, in a plan view, a region located between the sixth conductive layer and the semiconductor layer, comprising a seventh conductive layer provided in the same layer as the sixth conductive layer, an eighth conductive layer provided in the same layer as the sixth conductive layer, and a ninth conductive layer provided in the same layer as the sixth conductive layer.

5. It has first to sixth transistors, The source electrode or drain electrode of the first transistor is always in electrical contact with the gate wiring. The source electrode or the other drain electrode of the first transistor is always in contact with the clock signal line. The source electrode or drain electrode of the second transistor is always in electrical contact with the gate wiring. The source electrode or the other drain electrode of the second transistor is always in electrical contact with the first power line. Either the source electrode or the drain electrode of the third transistor is always in electrical contact with the gate electrode of the second transistor. The source electrode or the other drain electrode of the third transistor is always in electrical contact with the first power line. The gate electrode of the third transistor is always in electrical contact with the gate electrode of the first transistor. The source electrode or drain electrode of the fourth transistor is always in electrical contact with the gate electrode of the first transistor. The source electrode or the other drain electrode of the fourth transistor is always in electrical contact with the first power line. The gate electrode of the fourth transistor is always in electrical contact with the gate electrode of the second transistor. The source electrode or drain electrode of the fifth transistor is always in electrical contact with the gate electrode of the first transistor. The source electrode or the other drain electrode of the fifth transistor is always in electrical contact with the second power line. The gate electrode of the fifth transistor is always in conductivity with the first signal line. The source electrode or drain electrode of the sixth transistor is always in electrical contact with the gate electrode of the first transistor. The source electrode or the other drain electrode of the sixth transistor is always in electrical contact with the first power line. The gate electrode of the sixth transistor is always in conductivity with the second signal line. The first conductive layer, which functions as the gate electrode of the second transistor, is always electrically connected to the third conductive layer, which functions as the gate electrode of the fourth transistor, via the second conductive layer, which functions as either the source electrode or the drain electrode of the third transistor. The second conductive layer has a region that intersects with the fourth conductive layer which functions as the gate electrode of the third transistor. A semiconductor device in which, in a plan view, the channel lengths of the first to sixth transistors are aligned with one another.

6. It has first to sixth transistors, The source electrode or drain electrode of the first transistor is always in electrical contact with the gate wiring. The source electrode or the other drain electrode of the first transistor is always in contact with the clock signal line. The source electrode or drain electrode of the second transistor is always in electrical contact with the gate wiring. The source electrode or the other drain electrode of the second transistor is always in electrical contact with the first power line. Either the source electrode or the drain electrode of the third transistor is always in electrical contact with the gate electrode of the second transistor. The source electrode or the other drain electrode of the third transistor is always in electrical contact with the first power line. The gate electrode of the third transistor is always in electrical contact with the gate electrode of the first transistor. The source electrode or drain electrode of the fourth transistor is always in electrical contact with the gate electrode of the first transistor. The source electrode or the other drain electrode of the fourth transistor is always in electrical contact with the first power line. The gate electrode of the fourth transistor is always in electrical contact with the gate electrode of the second transistor. The source electrode or drain electrode of the fifth transistor is always in electrical contact with the gate electrode of the first transistor. The source electrode or the other drain electrode of the fifth transistor is always in electrical contact with the second power line. The gate electrode of the fifth transistor is always in conductivity with the first signal line. The source electrode or drain electrode of the sixth transistor is always in electrical contact with the gate electrode of the first transistor. The source electrode or the other drain electrode of the sixth transistor is always in electrical contact with the first power line. The gate electrode of the sixth transistor is always in conductivity with the second signal line. The first conductive layer, which functions as the gate electrode of the second transistor, is always electrically connected to the third conductive layer, which functions as the gate electrode of the fourth transistor, via the second conductive layer, which functions as either the source electrode or the drain electrode of the third transistor. The second conductive layer has a region that intersects with the fourth conductive layer which functions as the gate electrode of the third transistor. The fifth conductive layer, which functions as the other source electrode or drain electrode of the second transistor, has the function of the other source electrode or drain electrode of the third transistor, the function of the other source electrode or drain electrode of the fourth transistor, and the function of the other source electrode or drain electrode of the sixth transistor. A semiconductor device having a sixth conductive layer that functions as either the source electrode or the drain electrode of the fourth transistor, and also having the function of either the source electrode or the drain electrode of the fifth transistor, and the function of either the source electrode or the drain electrode of the sixth transistor.

7. It has first to sixth transistors, The source electrode or drain electrode of the first transistor is always in electrical contact with the gate wiring. The source electrode or the other drain electrode of the first transistor is always in contact with the clock signal line. The source electrode or drain electrode of the second transistor is always in electrical contact with the gate wiring. The source electrode or the other drain electrode of the second transistor is always in electrical contact with the first power line. Either the source electrode or the drain electrode of the third transistor is always in electrical contact with the gate electrode of the second transistor. The source electrode or the other drain electrode of the third transistor is always in electrical contact with the first power line. The gate electrode of the third transistor is always in electrical contact with the gate electrode of the first transistor. The source electrode or drain electrode of the fourth transistor is always in electrical contact with the gate electrode of the first transistor. The source electrode or the other drain electrode of the fourth transistor is always in electrical contact with the first power line. The gate electrode of the fourth transistor is always in electrical contact with the gate electrode of the second transistor. The source electrode or drain electrode of the fifth transistor is always in electrical contact with the gate electrode of the first transistor. The source electrode or the other drain electrode of the fifth transistor is always in electrical contact with the second power line. The gate electrode of the fifth transistor is always in conductivity with the first signal line. The source electrode or drain electrode of the sixth transistor is always in electrical contact with the gate electrode of the first transistor. The source electrode or the other drain electrode of the sixth transistor is always in electrical contact with the first power line. The gate electrode of the sixth transistor is always in conductivity with the second signal line. The first conductive layer, which functions as the gate electrode of the second transistor, is always electrically connected to the third conductive layer, which functions as the gate electrode of the fourth transistor, via the second conductive layer, which functions as either the source electrode or the drain electrode of the third transistor. The second conductive layer has a region that intersects with the fourth conductive layer which functions as the gate electrode of the third transistor. The fifth conductive layer, which functions as the other source electrode or drain electrode of the second transistor, has the function of the other source electrode or drain electrode of the third transistor, the function of the other source electrode or drain electrode of the fourth transistor, and the function of the other source electrode or drain electrode of the sixth transistor. The sixth conductive layer, which functions as the source electrode or drain electrode of the fifth transistor, is always in electrical contact with the seventh conductive layer, which functions as the second power line. The sixth conductive layer has a region in contact with the semiconductor layer having the channel formation region of the fifth transistor. A semiconductor device having, in a plan view, a region located between the seventh conductive layer and the semiconductor layer, comprising an eighth conductive layer provided in the same layer as the seventh conductive layer, a ninth conductive layer provided in the same layer as the seventh conductive layer, and a tenth conductive layer provided in the same layer as the seventh conductive layer.

8. It has first to sixth transistors, The source electrode or drain electrode of the first transistor is always in electrical contact with the gate wiring. The source electrode or the other drain electrode of the first transistor is always in contact with the clock signal line. The source electrode or drain electrode of the second transistor is always in electrical contact with the gate wiring. The source electrode or the other drain electrode of the second transistor is always in electrical contact with the first power line. Either the source electrode or the drain electrode of the third transistor is always in electrical contact with the gate electrode of the second transistor. The source electrode or the other drain electrode of the third transistor is always in electrical contact with the first power line. The gate electrode of the third transistor is always in electrical contact with the gate electrode of the first transistor. The source electrode or drain electrode of the fourth transistor is always in electrical contact with the gate electrode of the first transistor. The source electrode or the other drain electrode of the fourth transistor is always in electrical contact with the first power line. The gate electrode of the fourth transistor is always in electrical contact with the gate electrode of the second transistor. The source electrode or drain electrode of the fifth transistor is always in electrical contact with the gate electrode of the first transistor. The source electrode or the other drain electrode of the fifth transistor is always in electrical contact with the second power line. The gate electrode of the fifth transistor is always in conductivity with the first signal line. The source electrode or drain electrode of the sixth transistor is always in electrical contact with the gate electrode of the first transistor. The source electrode or the other drain electrode of the sixth transistor is always in electrical contact with the first power line. The gate electrode of the sixth transistor is always in conductivity with the second signal line. The first conductive layer, which functions as the gate electrode of the second transistor, is always electrically connected to the third conductive layer, which functions as the gate electrode of the fourth transistor, via the second conductive layer, which functions as either the source electrode or the drain electrode of the third transistor. The second conductive layer has a region that intersects with the fourth conductive layer which functions as the gate electrode of the third transistor. The fifth conductive layer, which functions as the other source electrode or drain electrode of the second transistor, has the function of the other source electrode or drain electrode of the third transistor, the function of the other source electrode or drain electrode of the fourth transistor, and the function of the other source electrode or drain electrode of the sixth transistor. A semiconductor device in which, in a plan view, the channel lengths of the first to sixth transistors are aligned with one another.

9. It has first to sixth transistors, The source electrode or drain electrode of the first transistor is always in electrical contact with the gate wiring. The source electrode or the other drain electrode of the first transistor is always in contact with the clock signal line. The source electrode or drain electrode of the second transistor is always in electrical contact with the gate wiring. The source electrode or the other drain electrode of the second transistor is always in electrical contact with the first power line. Either the source electrode or the drain electrode of the third transistor is always in electrical contact with the gate electrode of the second transistor. The source electrode or the other drain electrode of the third transistor is always in electrical contact with the first power line. The gate electrode of the third transistor is always in electrical contact with the gate electrode of the first transistor. The source electrode or drain electrode of the fourth transistor is always in electrical contact with the gate electrode of the first transistor. The source electrode or the other drain electrode of the fourth transistor is always in electrical contact with the first power line. The gate electrode of the fourth transistor is always in electrical contact with the gate electrode of the second transistor. The source electrode or drain electrode of the fifth transistor is always in electrical contact with the gate electrode of the first transistor. The source electrode or the other drain electrode of the fifth transistor is always in electrical contact with the second power line. The gate electrode of the fifth transistor is always in conductivity with the first signal line. The source electrode or drain electrode of the sixth transistor is always in electrical contact with the gate electrode of the first transistor. The source electrode or the other drain electrode of the sixth transistor is always in electrical contact with the first power line. The gate electrode of the sixth transistor is always in conductivity with the second signal line. The first conductive layer, which functions as the gate electrode of the second transistor, is always electrically connected to the third conductive layer, which functions as the gate electrode of the fourth transistor, via the second conductive layer, which functions as either the source electrode or the drain electrode of the third transistor. The second conductive layer has a region that intersects with the fourth conductive layer which functions as the gate electrode of the third transistor. The fifth conductive layer, which functions as either the source electrode or the drain electrode of the fourth transistor, has the function of either the source electrode or the drain electrode of the fifth transistor and the function of either the source electrode or the drain electrode of the sixth transistor. The sixth conductive layer, which functions as the source electrode or drain electrode of the fifth transistor, is always in electrical contact with the seventh conductive layer, which functions as the second power line. The sixth conductive layer has a region in contact with the semiconductor layer having the channel formation region of the fifth transistor. A semiconductor device having, in a plan view, a region located between the seventh conductive layer and the semiconductor layer, comprising an eighth conductive layer provided in the same layer as the seventh conductive layer, a ninth conductive layer provided in the same layer as the seventh conductive layer, and a tenth conductive layer provided in the same layer as the seventh conductive layer.

10. It has first to sixth transistors, The source electrode or drain electrode of the first transistor is always in electrical contact with the gate wiring. The source electrode or the other drain electrode of the first transistor is always in contact with the clock signal line. The source electrode or drain electrode of the second transistor is always in electrical contact with the gate wiring. The source electrode or the other drain electrode of the second transistor is always in electrical contact with the first power line. Either the source electrode or the drain electrode of the third transistor is always in electrical contact with the gate electrode of the second transistor. The source electrode or the other drain electrode of the third transistor is always in electrical contact with the first power line. The gate electrode of the third transistor is always in electrical contact with the gate electrode of the first transistor. The source electrode or drain electrode of the fourth transistor is always in electrical contact with the gate electrode of the first transistor. The source electrode or the other drain electrode of the fourth transistor is always in electrical contact with the first power line. The gate electrode of the fourth transistor is always in electrical contact with the gate electrode of the second transistor. The source electrode or drain electrode of the fifth transistor is always in electrical contact with the gate electrode of the first transistor. The source electrode or the other drain electrode of the fifth transistor is always in electrical contact with the second power line. The gate electrode of the fifth transistor is always in conductivity with the first signal line. The source electrode or drain electrode of the sixth transistor is always in electrical contact with the gate electrode of the first transistor. The source electrode or the other drain electrode of the sixth transistor is always in electrical contact with the first power line. The gate electrode of the sixth transistor is always in conductivity with the second signal line. The first conductive layer, which functions as the gate electrode of the second transistor, is always electrically connected to the third conductive layer, which functions as the gate electrode of the fourth transistor, via the second conductive layer, which functions as either the source electrode or the drain electrode of the third transistor. The second conductive layer has a region that intersects with the fourth conductive layer which functions as the gate electrode of the third transistor. The fifth conductive layer, which functions as either the source electrode or the drain electrode of the fourth transistor, has the function of either the source electrode or the drain electrode of the fifth transistor and the function of either the source electrode or the drain electrode of the sixth transistor. A semiconductor device in which, in a plan view, the channel lengths of the first to sixth transistors are aligned with one another.

11. It has first to sixth transistors, The source electrode or drain electrode of the first transistor is always in electrical contact with the gate wiring. The source electrode or the other drain electrode of the first transistor is always in contact with the clock signal line. The source electrode or drain electrode of the second transistor is always in electrical contact with the gate wiring. The source electrode or the other drain electrode of the second transistor is always in electrical contact with the first power line. Either the source electrode or the drain electrode of the third transistor is always in electrical contact with the gate electrode of the second transistor. The source electrode or the other drain electrode of the third transistor is always in electrical contact with the first power line. The gate electrode of the third transistor is always in electrical contact with the gate electrode of the first transistor. The source electrode or drain electrode of the fourth transistor is always in electrical contact with the gate electrode of the first transistor. The source electrode or the other drain electrode of the fourth transistor is always in electrical contact with the first power line. The gate electrode of the fourth transistor is always in electrical contact with the gate electrode of the second transistor. The source electrode or drain electrode of the fifth transistor is always in electrical contact with the gate electrode of the first transistor. The source electrode or the other drain electrode of the fifth transistor is always in electrical contact with the second power line. The gate electrode of the fifth transistor is always in conductivity with the first signal line. The source electrode or drain electrode of the sixth transistor is always in electrical contact with the gate electrode of the first transistor. The source electrode or the other drain electrode of the sixth transistor is always in electrical contact with the first power line. The gate electrode of the sixth transistor is always in conductivity with the second signal line. The first conductive layer, which functions as the gate electrode of the second transistor, is always electrically connected to the third conductive layer, which functions as the gate electrode of the fourth transistor, via the second conductive layer, which functions as either the source electrode or the drain electrode of the third transistor. The second conductive layer has a region that intersects with the fourth conductive layer which functions as the gate electrode of the third transistor. The fifth conductive layer, which functions as the source electrode or drain electrode of the fifth transistor, is always in electrical contact with the sixth conductive layer, which functions as the second power line. The fifth conductive layer has a region in contact with the semiconductor layer having the channel formation region of the fifth transistor. In a plan view, the region located between the sixth conductive layer and the semiconductor layer includes a seventh conductive layer provided in the same layer as the sixth conductive layer, an eighth conductive layer provided in the same layer as the sixth conductive layer, and a ninth conductive layer provided in the same layer as the sixth conductive layer. A semiconductor device in which, in a plan view, the channel lengths of the first to sixth transistors are aligned with one another.

12. It has first to sixth transistors, The source electrode or drain electrode of the first transistor is always in electrical contact with the gate wiring. The source electrode or the other drain electrode of the first transistor is always in contact with the clock signal line. The source electrode or drain electrode of the second transistor is always in electrical contact with the gate wiring. The source electrode or the other drain electrode of the second transistor is always in electrical contact with the first power line. Either the source electrode or the drain electrode of the third transistor is always in electrical contact with the gate electrode of the second transistor. The source electrode or the other drain electrode of the third transistor is always in electrical contact with the first power line. The gate electrode of the third transistor is always in electrical contact with the gate electrode of the first transistor. The source electrode or drain electrode of the fourth transistor is always in electrical contact with the gate electrode of the first transistor. The source electrode or the other drain electrode of the fourth transistor is always in electrical contact with the first power line. The gate electrode of the fourth transistor is always in electrical contact with the gate electrode of the second transistor. The source electrode or drain electrode of the fifth transistor is always in electrical contact with the gate electrode of the first transistor. The source electrode or the other drain electrode of the fifth transistor is always in electrical contact with the second power line. The gate electrode of the fifth transistor is always in conductivity with the first signal line. The source electrode or drain electrode of the sixth transistor is always in electrical contact with the gate electrode of the first transistor. The source electrode or the other drain electrode of the sixth transistor is always in electrical contact with the first power line. The gate electrode of the sixth transistor is always in conductivity with the second signal line. The first conductive layer, which functions as the gate electrode of the second transistor, is always electrically connected to the third conductive layer, which functions as the gate electrode of the fourth transistor, via the second conductive layer, which functions as either the source electrode or the drain electrode of the third transistor. The second conductive layer has a region that intersects with the fourth conductive layer which functions as the gate electrode of the third transistor. The fifth conductive layer, which functions as the other source electrode or drain electrode of the second transistor, has the function of the other source electrode or drain electrode of the third transistor, the function of the other source electrode or drain electrode of the fourth transistor, and the function of the other source electrode or drain electrode of the sixth transistor. The sixth conductive layer, which functions as either the source electrode or the drain electrode of the fourth transistor, has the function of either the source electrode or the drain electrode of the fifth transistor and the function of either the source electrode or the drain electrode of the sixth transistor. The seventh conductive layer, which functions as the source electrode or drain electrode of the fifth transistor, is always in electrical contact with the eighth conductive layer, which functions as the second power line. The seventh conductive layer has a region in contact with the semiconductor layer having the channel formation region of the fifth transistor. A semiconductor device having, in a plan view, a region located between the eighth conductive layer and the semiconductor layer, comprising a ninth conductive layer provided in the same layer as the eighth conductive layer, a tenth conductive layer provided in the same layer as the eighth conductive layer, and an eleventh conductive layer provided in the same layer as the eighth conductive layer.

13. It has first to sixth transistors, The source electrode or drain electrode of the first transistor is always in electrical contact with the gate wiring. The source electrode or the other drain electrode of the first transistor is always in contact with the clock signal line. The source electrode or drain electrode of the second transistor is always in electrical contact with the gate wiring. The source electrode or the other drain electrode of the second transistor is always in electrical contact with the first power line. Either the source electrode or the drain electrode of the third transistor is always in electrical contact with the gate electrode of the second transistor. The source electrode or the other drain electrode of the third transistor is always in electrical contact with the first power line. The gate electrode of the third transistor is always in electrical contact with the gate electrode of the first transistor. The source electrode or drain electrode of the fourth transistor is always in electrical contact with the gate electrode of the first transistor. The source electrode or the other drain electrode of the fourth transistor is always in electrical contact with the first power line. The gate electrode of the fourth transistor is always in electrical contact with the gate electrode of the second transistor. The source electrode or drain electrode of the fifth transistor is always in electrical contact with the gate electrode of the first transistor. The source electrode or the other drain electrode of the fifth transistor is always in electrical contact with the second power line. The gate electrode of the fifth transistor is always in conductivity with the first signal line. The source electrode or drain electrode of the sixth transistor is always in electrical contact with the gate electrode of the first transistor. The source electrode or the other drain electrode of the sixth transistor is always in electrical contact with the first power line. The gate electrode of the sixth transistor is always in conductivity with the second signal line. The first conductive layer, which functions as the gate electrode of the second transistor, is always electrically connected to the third conductive layer, which functions as the gate electrode of the fourth transistor, via the second conductive layer, which functions as either the source electrode or the drain electrode of the third transistor. The second conductive layer has a region that intersects with the fourth conductive layer which functions as the gate electrode of the third transistor. The fifth conductive layer, which functions as the other source electrode or drain electrode of the second transistor, has the function of the other source electrode or drain electrode of the third transistor, the function of the other source electrode or drain electrode of the fourth transistor, and the function of the other source electrode or drain electrode of the sixth transistor. The sixth conductive layer, which functions as either the source electrode or the drain electrode of the fourth transistor, has the function of either the source electrode or the drain electrode of the fifth transistor and the function of either the source electrode or the drain electrode of the sixth transistor. A semiconductor device in which, in a plan view, the channel lengths of the first to sixth transistors are aligned with one another.

14. It has first to sixth transistors, The source electrode or drain electrode of the first transistor is always in electrical contact with the gate wiring. The source electrode or the other drain electrode of the first transistor is always in contact with the clock signal line. The source electrode or drain electrode of the second transistor is always in electrical contact with the gate wiring. The source electrode or the other drain electrode of the second transistor is always in electrical contact with the first power line. Either the source electrode or the drain electrode of the third transistor is always in electrical contact with the gate electrode of the second transistor. The source electrode or the other drain electrode of the third transistor is always in electrical contact with the first power line. The gate electrode of the third transistor is always in electrical contact with the gate electrode of the first transistor. The source electrode or drain electrode of the fourth transistor is always in electrical contact with the gate electrode of the first transistor. The source electrode or the other drain electrode of the fourth transistor is always in electrical contact with the first power line. The gate electrode of the fourth transistor is always in electrical contact with the gate electrode of the second transistor. The source electrode or drain electrode of the fifth transistor is always in electrical contact with the gate electrode of the first transistor. The source electrode or the other drain electrode of the fifth transistor is always in electrical contact with the second power line. The gate electrode of the fifth transistor is always in conductivity with the first signal line. The source electrode or drain electrode of the sixth transistor is always in electrical contact with the gate electrode of the first transistor. The source electrode or the other drain electrode of the sixth transistor is always in electrical contact with the first power line. The gate electrode of the sixth transistor is always in conductivity with the second signal line. The first conductive layer, which functions as the gate electrode of the second transistor, is always electrically connected to the third conductive layer, which functions as the gate electrode of the fourth transistor, via the second conductive layer, which functions as either the source electrode or the drain electrode of the third transistor. The second conductive layer has a region that intersects with the fourth conductive layer which functions as the gate electrode of the third transistor. The fifth conductive layer, which functions as the other source electrode or drain electrode of the second transistor, has the function of the other source electrode or drain electrode of the third transistor, the function of the other source electrode or drain electrode of the fourth transistor, and the function of the other source electrode or drain electrode of the sixth transistor. The sixth conductive layer, which functions as the source electrode or drain electrode of the fifth transistor, is always in electrical contact with the seventh conductive layer, which functions as the second power line. The sixth conductive layer has a region in contact with the semiconductor layer having the channel formation region of the fifth transistor. In a plan view, the region located between the seventh conductive layer and the semiconductor layer includes an eighth conductive layer provided in the same layer as the seventh conductive layer, a ninth conductive layer provided in the same layer as the seventh conductive layer, and a tenth conductive layer provided in the same layer as the seventh conductive layer. A semiconductor device in which, in a plan view, the channel lengths of the first to sixth transistors are aligned with one another.

15. It has first to sixth transistors, The source electrode or drain electrode of the first transistor is always in electrical contact with the gate wiring. The source electrode or the other drain electrode of the first transistor is always in contact with the clock signal line. The source electrode or drain electrode of the second transistor is always in electrical contact with the gate wiring. The source electrode or the other drain electrode of the second transistor is always in electrical contact with the first power line. Either the source electrode or the drain electrode of the third transistor is always in electrical contact with the gate electrode of the second transistor. The source electrode or the other drain electrode of the third transistor is always in electrical contact with the first power line. The gate electrode of the third transistor is always in electrical contact with the gate electrode of the first transistor. The source electrode or drain electrode of the fourth transistor is always in electrical contact with the gate electrode of the first transistor. The source electrode or the other drain electrode of the fourth transistor is always in electrical contact with the first power line. The gate electrode of the fourth transistor is always in electrical contact with the gate electrode of the second transistor. The source electrode or drain electrode of the fifth transistor is always in electrical contact with the gate electrode of the first transistor. The source electrode or the other drain electrode of the fifth transistor is always in electrical contact with the second power line. The gate electrode of the fifth transistor is always in conductivity with the first signal line. The source electrode or drain electrode of the sixth transistor is always in electrical contact with the gate electrode of the first transistor. The source electrode or the other drain electrode of the sixth transistor is always in electrical contact with the first power line. The gate electrode of the sixth transistor is always in conductivity with the second signal line. The first conductive layer, which functions as the gate electrode of the second transistor, is always electrically connected to the third conductive layer, which functions as the gate electrode of the fourth transistor, via the second conductive layer, which functions as either the source electrode or the drain electrode of the third transistor. The second conductive layer has a region that intersects with the fourth conductive layer which functions as the gate electrode of the third transistor. The fifth conductive layer, which functions as either the source electrode or the drain electrode of the fourth transistor, has the function of either the source electrode or the drain electrode of the fifth transistor and the function of either the source electrode or the drain electrode of the sixth transistor. The sixth conductive layer, which functions as the source electrode or drain electrode of the fifth transistor, is always in electrical contact with the seventh conductive layer, which functions as the second power line. The sixth conductive layer has a region in contact with the semiconductor layer having the channel formation region of the fifth transistor. In a plan view, the region located between the seventh conductive layer and the semiconductor layer includes an eighth conductive layer provided in the same layer as the seventh conductive layer, a ninth conductive layer provided in the same layer as the seventh conductive layer, and a tenth conductive layer provided in the same layer as the seventh conductive layer. A semiconductor device in which, in a plan view, the channel lengths of the first to sixth transistors are aligned with one another.

16. It has first to sixth transistors, The source electrode or drain electrode of the first transistor is always in electrical contact with the gate wiring. The source electrode or the other drain electrode of the first transistor is always in contact with the clock signal line. The source electrode or drain electrode of the second transistor is always in electrical contact with the gate wiring. The source electrode or the other drain electrode of the second transistor is always in electrical contact with the first power line. Either the source electrode or the drain electrode of the third transistor is always in electrical contact with the gate electrode of the second transistor. The source electrode or the other drain electrode of the third transistor is always in electrical contact with the first power line. The gate electrode of the third transistor is always in electrical contact with the gate electrode of the first transistor. The source electrode or drain electrode of the fourth transistor is always in electrical contact with the gate electrode of the first transistor. The source electrode or the other drain electrode of the fourth transistor is always in electrical contact with the first power line. The gate electrode of the fourth transistor is always in electrical contact with the gate electrode of the second transistor. The source electrode or drain electrode of the fifth transistor is always in electrical contact with the gate electrode of the first transistor. The source electrode or the other drain electrode of the fifth transistor is always in electrical contact with the second power line. The gate electrode of the fifth transistor is always in conductivity with the first signal line. The source electrode or drain electrode of the sixth transistor is always in electrical contact with the gate electrode of the first transistor. The source electrode or the other drain electrode of the sixth transistor is always in electrical contact with the first power line. The gate electrode of the sixth transistor is always in conductivity with the second signal line. The first conductive layer, which functions as the gate electrode of the second transistor, is always electrically connected to the third conductive layer, which functions as the gate electrode of the fourth transistor, via the second conductive layer, which functions as either the source electrode or the drain electrode of the third transistor. The second conductive layer has a region that intersects with the fourth conductive layer which functions as the gate electrode of the third transistor. The fifth conductive layer, which functions as the other source electrode or drain electrode of the second transistor, has the function of the other source electrode or drain electrode of the third transistor, the function of the other source electrode or drain electrode of the fourth transistor, and the function of the other source electrode or drain electrode of the sixth transistor. The sixth conductive layer, which functions as either the source electrode or the drain electrode of the fourth transistor, has the function of either the source electrode or the drain electrode of the fifth transistor and the function of either the source electrode or the drain electrode of the sixth transistor. The seventh conductive layer, which functions as the source electrode or drain electrode of the fifth transistor, is always in electrical contact with the eighth conductive layer, which functions as the second power line. The seventh conductive layer has a region in contact with the semiconductor layer having the channel formation region of the fifth transistor. In a plan view, the region located between the eighth conductive layer and the semiconductor layer includes a ninth conductive layer provided in the same layer as the eighth conductive layer, a tenth conductive layer provided in the same layer as the eighth conductive layer, and an eleventh conductive layer provided in the same layer as the eighth conductive layer. A semiconductor device in which, in a plan view, the channel lengths of the first to sixth transistors are aligned with one another.

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