Double data rate circuit and data generation method for implementing precise duty cycle control

Abstract

To provide a double data rate circuit that implements precise duty cycle control, and a data generation method.SOLUTION: A data generation method is performed by a double data rate circuit including a clock generator, a clock divider, and a multiplexer. The clock generator receives a source clock signal for generating a pair of complementary clock signals, and the clock divider is coupled to the clock generator and generates four multi-phase clock signals that are sequentially out of phase by 90° using only single edge transitions of the pair of complementary clock signals. The multiplexer is coupled to the clock divider and multiplexes multiple data bits into an output data stream by sequentially selecting each data bit of the multiple data bits at each of first and second edge transitions of two of the four multi-phase clock signals, cancelling the selection, and making each selected data bit into the output data stream.SELECTED DRAWING: Figure 8

Description

Technical Field

[0001] The present invention relates to high-speed data processing, and more particularly, to a double data rate circuit and a data generation method that implement accurate duty cycle control.

Background Art

[0002] A double data rate (DDR) system transfers data on both the rising and falling edges of a clock signal. Therefore, the output data from a DDR circuit is aligned with the rising and falling edges of the clock signal, and thus the duty cycle of the clock signal directly affects the data window of the output data. In order to optimize the timing operation of the output signal, a low-jitter clock with a 50% duty cycle is essential.

[0003] In the prior art, conventional DDR circuits often have the drawback of a low duty cycle of the output data due to the imbalance between the pull-up and pull-down drive strengths for selecting the output data.

Summary of the Invention

Problems to be Solved by the Invention

[0004] Therefore, there is a need for a double data rate circuit and a data generation method that implement accurate duty cycle control in order to meet timing requirements, reduce data skew, lower the error rate, and enhance system performance.

Means for Solving the Problems

[0005] One embodiment of the present invention provides a double data rate circuit including a clock generator, a clock divider, and a multiplexer. The clock generator is used to receive a source clock signal to generate a pair of complementary clock signals. The clock divider is coupled to the clock generator and used to generate four polyphase clock signals using only the single-edge transitions of the pair of complementary clock signals. The four polyphase clock signals are phased by 90° in sequence. The multiplexer is coupled to the clock divider and uses the first edge transitions and second edge transitions of two of the four polyphase clock signals. In It is used to multiplex multiple data bits into an output data stream by sequentially selecting and deselecting each data bit of a group of data bits, and outputting each selected data bit as an output data stream.

[0006] In another embodiment of the present invention, a data generation method employed by a double data rate circuit comprising a clock generator, a clock divider, and a multiplexer is disclosed. The data generation method is a method of generating data by: a clock generator receiving a source clock signal to generate a pair of complementary clock signals; a clock divider generating four polyphase clock signals using only the single-edge transitions of the pair of complementary clock signals, wherein the four polyphase clock signals are out of phase by 90° from each other; and two first edge transitions and second edge transitions of the four polyphase clock signals. In The process includes the steps of the multiplexer multiplexing multiple data bits into an output data stream by sequentially selecting and deselecting each data bit of a plurality of data bits, and outputting each selected data bit as an output data stream.

[0007] These and other objectives of the present invention will become apparent to those skilled in the art after reading the following detailed description of preferred embodiments shown in various figures and drawings.

[0008] The accompanying drawings incorporated herein and forming part thereof illustrate embodiments of the present disclosure, illustrate the principles of the present disclosure together with the description, and further assist those skilled in the art in preparing and using the present disclosure. [Brief explanation of the drawing]

[0009] [Figure 1] This is a block diagram of a double data rate circuit according to one embodiment of the present invention. [Figure 2] Figure 1 is a timing diagram of the DDR circuit. [Figure 3] Figure 1 is a block diagram of the clock generator. [Figure 4] Figure 1 is a block diagram of the clock frequency divider. [Figure 5] Figure 1 is a block diagram of the multiplexer. [Figure 6] Figure 5 is a schematic diagram of a matched 3-input NAND gate in a multiplexer. [Figure 7] Figure 5 is a schematic diagram of a matched 4-input NAND gate in a multiplexer. [Figure 8] Figure 1 is a flowchart illustrating the data generation method employed by the double data rate circuit. [Figure 9] This figure shows a simulation of the DDR circuit shown in Figure 1. [Figure 10] This figure shows a simulation of a conventional memory controller. [Modes for carrying out the invention]

[0010] Figure 1 is a block diagram of a double data rate (DDR) circuit 1 according to one embodiment of the present invention, comprising a clock generator 10, a clock divider 12, and a multiplexer 14. The clock generator 10 is coupled to the clock divider 12 and then to the multiplexer 14. The double data rate circuit 1 receives four data bits Dr0, Df0, Dr1, and Df1 from a baseband circuit, receives source clock signals CKs from an external clock source, and can multiplex the data bits Dr0, Df0, Dr1, and Df1 into a single data stream DQ at twice the clock rate of the source clock signals CKs. In detail, the start and end of each multiplexing of the data bits Dr0, Df0, Dr1, and Df1 are controlled by an equal number of signal edges, thereby reducing or eliminating timing mismatches between the start and end of multiplexing due to unbalanced pull-up and pull-down drive strengths and / or process variations. The double data rate circuit 1 may be a DDR memory controller that transmits the output data stream DQ to the DDR memory. The external clock source refers to an external clock generator of the double data rate circuit 1, and may be a crystal oscillator.

[0011] More specifically, the clock generator 10 may receive source clock signals CKs to generate a pair of complementary clock signals CK, CKc. The pair of complementary clock signals CK, CKc have a phase difference of approximately 180° relative to each other and substantially equal timing delays relative to the source clock signals CKs. In detail, the clock generator 10 may employ an even number of inverters coupled in series to generate the complementary clock signal CK and an odd number of inverters coupled in series to generate the complementary clock signal CKc. The sum of the fan-outs of the even number of inverters and the sum of the fan-outs of the odd number of inverters are configured to be substantially the same in order to ensure substantially equal timing delays for the pair of complementary clock signals CK, CKc.

[0012] The clock divider 12 can generate four polyphase clock signals CKsel_L0, CKsel_L1, CKsel_U0, and CKsel_U1 using only single-edge transitions of a pair of complementary clock signals CK and CKc. The four polyphase clock signals CKsel_L0, CKsel_L1, CKsel_U0, and CKsel_U1 are sequentially out of phase by 90°. The single-edge transition may be the rising edge or the falling edge of the pair of complementary clock signals CK and CKc.

[0013] The multiplexer 14 controls two first edge transitions and two second edge transitions from among the four polyphase clock signals CKsel_L0, CKsel_L1, CKsel_U0, and CKsel_U1. In The data bits Dr0, Df0, Dr1, and Df1 may be multiplexed into the output data stream DQ by sequentially selecting and deselecting each of the data bits Dr0, Df0, Dr1, and Df1, and outputting each selected data bit as an output data stream DQ. For example, the multiplexer 14 processes the first edge transition of the first polyphase clock signal CKsel_L0, one of the four polyphase clock signals CKsel_L0, CKsel_L1, CKsel_U0, and CKsel_U1. In The first data bit Dr0 out of the data bits Dr0, Df0, Dr1, and Df1 is selected as the output data stream DQ, and the second edge transition of the second polyphase clock signal CKsel_L1 out of the four polyphase clock signals CKsel_L0, CKsel_L1, CKsel_U0, and CKsel_U1 is performed. InThe first data bit Dr0 among the data bits Dr0, Df0, Dr1, and Df1 may be deselected as the output data stream DQ. The first polyphase clock signal CKsel_L0 and the second polyphase clock signal CKsel_L1 are out of phase by 90°. The first edge transition and the second edge transition may be opposite clock edges. For example, the first edge transition may be a rising edge and the second edge transition may be a falling edge. The other three data bits Df0, Dr1, and Df1 may be selected and / or deselected on the same principle using other combinations of the two polyphase clock signals CKsel_L0, CKsel_L1, CKsel_U0, and CKsel_U1, which are also out of phase by 90°.

[0014] Figure 2 is a timing diagram of DDR circuit 1, which includes source clock signals CKs, complementary clock signals CK and CKc, polyphase clock signals CKsel_L0, CKsel_L1, CKsel_U0, and CKsel_U1, and output data stream DQ. The source clock signals CKs are used to generate a pair of complementary clock signals CK and CKc, which have substantially identical delays. Next, the complementary clock signal CK is used to generate the polyphase clock signals CKsel_L1 and CKsel_U1 using the rising edge of the complementary clock signal CK, and similarly, the complementary clock signal CKc is used to generate the polyphase clock signals CKsel_L0 and CKsel_U0 using the rising edge of the complementary clock signal CKc. Since only rising edges are used, the timing skew between any two of the polyphase clock signals CKsel_L0, CKsel_L1, CKsel_U0, and CKsel_U1 is reduced or minimized. The polyphase clock signals CKsel_L0, CKsel_L1, CKsel_U0, and CKsel_U1 are then used to multiplex the data bits Dr0, Df0, Dr1, and Df1. Specifically, four pairs of polyphase clock signals may be selected from the four polyphase clock signals CKsel_L0, CKsel_L1, CKsel_U0, and CKsel_U1, respectively, to combine the data bits Dr0, Df0, Dr1, and Df1 into the output data stream DQ, with each pair of polyphase clock signals being 90° out of phase. For example, when both of the pair of polyphase clock signals CKsel_L0 and CKsel_L1 are in the logic state "HIGH", the data bit Dr0 may be selected as the output data bit Q0 of the output data stream DQ; otherwise, the data bit Dr0 may be deselected. To this end, the selection of data bit Dr0 is triggered by the rising edge of the polyphase clock signal CKsel_L1, and the deselection of data bit Dr0 is triggered by the falling edge of the polyphase clock signal CKsel_L0. Similarly, data bits Df0, Dr1, and Df1 can be sequentially selected as output data bits Q1, Q2, and Q3 of the output data stream DQ.

[0015] Therefore, the start of the output data bits in the output data stream DQ depends on the rising edge of one of the first polyphase clock signals among the four polyphase clock signals CKsel_L0, CKsel_L1, CKsel_U0, CKsel_U1, and the end of the output data bits in the output data stream DQ depends on the falling edge of one of the second polyphase clock signals among the four polyphase clock signals CKsel_L0, CKsel_L1, CKsel_U0, CKsel_U1. Therefore, the start and end of the output data bits are driven with substantially equal driving strengths, and mismatches due to timing variations and process variations between the start delay and the end delay can be reduced or eliminated, thereby generating an output data stream DQ with enhanced duty cycle control.

[0016] The double data rate circuit 1 uses matched circuit components to further control the duty cycle of the output data stream DQ to approximately 50%. More specifically, the clock generator 10, the clock divider 12, and the multiplexer 14 all adopt a matched structure, which will be described in detail as follows.

[0017] FIG. 3 is a block diagram of the clock generator 10 of FIG. 1. The clock generator 10 includes inverters 300, 302, 320, 322, 324. The inverters 300, 302 are connected in series to form a first clock path and receive a source clock CKs to generate complementary clock signals CK. Similarly, the inverters 320, 322, 324 are connected in series to form a second clock path and receive a source clock CKs to generate complementary clock signals CKc. The fan-out of the inverter 300 is equal to the sum of the fan-outs of the inverters 320 and 322 and can be expressed by Equation Eq(1). FO(inverter 300) = FO(inverter 320) + FO(inverter 322) Eq(1) Here, FO() is the fan-out of the inverter.

[0018] Since the sum of the fan-outs of the inverters on the first clock path and the second clock path is matched, the timing delays of the complementary clock signals CK and CKc are substantially equal. The circuit configuration ensures that there is low or no timing skew while introducing a 180° phase difference between the complementary clock signals CK and CKc.

[0019] FIG. 4 is a block diagram of the clock divider 12 of FIG. 1. The clock divider 12 includes first and second pairs of cross-coupled flip-flops. The first pair of cross-coupled flip-flops are cross-coupled to each other and receive the complementary clock signal CK to generate the polyphase clock signals CKsel_L1 and CKsel_U1 by switching the polyphase clock signals CKsel_L1 and CKsel_U1 at all rising edges of the complementary clock signal CK, and includes flip-flops 40a and 40b. Similarly, the second pair of cross-coupled flip-flops are cross-coupled to each other and receive the complementary clock signal CKc to generate the polyphase clock signals CKsel_L0 and CKsel_U0 by switching the polyphase clock signals CKsel_L0 and CKsel_U0 at all rising edges of the complementary clock signal CKc, and includes flip-flops 40c and 40d. The polyphase clock signals CKsel_L1 and CKsel_U1 have opposite phases, and the polyphase clock signals CKsel_L0 and CKsel_U0 have opposite phases.

[0020] FIG. 5 is a block diagram of the multiplexer 14 of FIG. 1. The multiplexer 14 includes four 3-input NAND gates 50a to 50d and a 4-input NAND gate 52 coupled thereto. Each of the four 3-input NAND gates 50a to 50d receives one of the data bits Dr0, Df0, Dr1, Df1 and two of the four polyphase clock signals CKsel_L0, CKsel_L1, CKsel_U0, CKsel_U1, and the first edge transition of one of the two received polyphase clock signals In...to initiate the output of the received data bits and the second edge transition of the other one of the two received polyphase clock signals. In The gates are configured to stop outputting the received data bits. The two received polyphase clock signals are out of phase by 90°. For example, a 3-input NAND gate 50b may receive data bit Df0 and polyphase clock signals CKsel_L1 and CKsel_U0. On the rising edge of the polyphase clock signal CKsel_U0, the 3-input NAND gate 50b may start outputting data bit Df0, and on the falling edge of the polyphase clock signal CKsel_L1, the 3-input NAND gate 50b may stop outputting data bit Df0. The same operating principle applies to the other 3-input NAND gates 50a, 50c, and 50d. Because the received polyphase clock signals are out of phase by 90°, each data bit may be valid for a period of about a quarter clock cycle and can be coupled to the output data stream DQ by the 4-input NAND gate 52. When no data bits are output, the 3-input NAND gates 50a to 50d may output a logic state "HIGH". The 4-input NAND gate 52 may receive the respective output signals from the four 3-input NAND gates 50a to 50d to generate the output data stream DQ. Thus, the 3-input NAND gates 50a to 50d may output the valid data bits Dr0, Df0, Dr1, and Df1 for a quarter-clock period and the logic state "HIGH" for the remainder of the time, after which the 4-input NAND gate 52 may receive only one valid data bit and three logic states "HIGH" in any quarter-clock cycle, and combine the data bits Dr0, Df0, Dr1, and Df1 to form the output data stream DQ. The multiplexer 14 may further include a keeper circuit configured to maintain the output data stream DQ in a steady state during standby mode.

[0021] Furthermore, the 3-input NAND gates 50a-50d and the 4-input NAND gate 52 may be implemented in a matched structure, as shown in Figures 6 and 7, to compensate for differences in output response speed due to input connections. In Figure 6, the input signals A, B, and C of the 3-input NAND gate 50 are matched with pull-up and pull-down paths. The 3-input NAND gate 50 comprises three P-type metal-oxide-semiconductor field-effect transistors (MOSFETs) Q600-Q604 and nine N-type MOSFETs Q606-Q622. The three P-type MOSFETs Q600-Q604 are coupled in parallel, each receiving its respective input signal A, B, or C. The nine N-type MOSFETs Q606-Q622 are grouped into three parallel-coupled groups. Each group of N-type MOSFETs contains three N-type MOSFETs coupled in series, referred to as the upper N-type MOSFET, middle N-type MOSFET, and lower N-type MOSFET, respectively. The three groups of N-type MOSFETs may receive input signals A, B, and C in a matched manner, or each of input signals A, B, and C may be input to the upper, middle, and lower N-type MOSFETs of different groups of N-type MOSFETs. Using a matched structure, the output signal Sout3 can respond to input signals A, B, and C at approximately the same speed. Similarly, in Figure 7, the 4-input NAND gate 52 comprises four P-type MOSFETs Q700-Q706 and sixteen N-type MOSFETs Q710-Q740. The inputs of the 4-input NAND gate are matched with pull-up and pull-down paths so that the output signal Sout4 can respond to input signals A, B, C, and D at approximately the same speed.

[0022] Figure 8 is a flowchart of the data generation method 8 employed by the DDR circuit 1 in Figure 1. The data generation method 8 includes steps S800 to S804 and is used to implement precise duty cycle control for the output data stream DQ. Any reasonable technical changes or step adjustments are within the scope of this disclosure. Steps S800 to S804 are described in detail below. Step S800: The clock generator 10 receives source clock signals CKs to generate a pair of complementary clock signals CK and CKc. Step S802: The clock divider 12 generates four polyphase clock signals CKsel_L0, CKsel_L1, CKsel_U0, and CKsel_U1 using only single-edge transitions of a pair of complementary clock signals CK and CKc. Step S804: The multiplexer 14 performs the first edge transitions and the second edge transitions of two of the four polyphase clock signals. In Multiple data bits are multiplexed into an output data stream by sequentially selecting and deselecting each data bit of a set of data bits, and outputting each selected data bit as an output data stream.

[0023] Steps S800 to S804 have been explained in detail in the previous paragraph, and for the sake of brevity, that explanation will be omitted here.

[0024] Figures 9 and 10 show simulations of the DDR circuit 1 and a conventional memory controller from Figure 1, respectively. It can be seen that while the conventional memory controller generates a duty cycle of 36.4%, the DDR circuit 1 of the present invention can generate a duty cycle of 47.5%.

[0025] To this end, the DDR circuit 1 and data generation method 8 can provide enhanced duty cycle control, thereby meeting timing requirements, reducing data skew, lowering the error rate, and improving system performance.

[0026] Those skilled in the art will readily realize that numerous changes and modifications of the device and method can be made while retaining the teachings of the present invention. Therefore, the above disclosure should be construed as being limited only by the metes and bounds of the appended claims. [Explanation of Symbols]

[0027] 1. Double Data Rate (DDR) Circuit 8. Data Generation Method 10 Clock generators 12 Clock divider 14 Multiplexer 40 flip-flops 50a~50d 3-input NAND gate 52 4-input NAND gate 300 Inverter 302 Inverter 320 Inverter 322 Inverter 324 Inverter Q600~Q604 P-type metal-oxide-semiconductor field-effect transistor (MOSFET) Q606~Q622 N-type MOSFET Q700~Q706 P-type MOSFET Q710~Q740 N-type MOSFET

Claims

1. It is a double data rate circuit, It is a clock generator, A first clock path that receives a source clock signal and generates a first complementary clock signal based on the source clock signal, A clock generator comprising: a second clock path that receives the source clock signal and generates a second complementary clock signal based on the source clock signal, wherein the second complementary clock signal and the first complementary clock signal have a phase difference of 180°; A clock divider coupled to the clock generator and configured to generate four polyphase clock signals that are sequentially shifted in phase by 90° based on the first complementary clock signal and the second complementary clock signal, A multiplexer coupled to the clock divider and configured to multiplex multiple data bits into an output data stream based on at least two of the four polyphase clock signals which are out of phase, Equipped with, A double data rate circuit in which the first clock path and the second clock path each comprise one or more inverters, and the sum of the fan-outs of the one or more inverters in the first clock path matches the sum of the fan-outs of the one or more inverters in the second clock path.

2. The double data rate circuit according to claim 1, wherein one or more inverters of the first clock path are coupled in series.

3. The double data rate circuit according to claim 1, wherein one or more inverters of the second clock path are coupled in series.

4. The double data rate circuit according to claim 1, wherein the first clock path comprises a first inverter and a second inverter coupled in series, the second clock path comprises a third inverter, a fourth inverter and a fifth inverter, and the fan-out of the first inverter is the sum of the fan-outs of the third inverter and the fourth inverter.

5. The double data rate circuit according to claim 1, wherein the first complementary clock signal and the second complementary clock signal have equal timing delays.

6. The aforementioned clock frequency divider, A first pair of cross-coupled flip-flops configured to receive one of the first complementary clock signal and the second complementary clock signal, and to generate two of the four polyphase clock signals with opposite phases, The double data rate circuit according to claim 1, further comprising: a second pair of cross-coupled flip-flops configured to receive the other of the first complementary clock signal and the second complementary clock signal, and to generate two other opposite-phase signals from the four polyphase clock signals.

7. The double data rate circuit according to claim 1, wherein the multiplexer is further configured to multiplex the plurality of data bits into the output data stream by sequentially selecting and deselecting each of the plurality of data bits at two first edge transitions and a second edge transition of the at least two polyphase clock signals.

8. The double data rate circuit according to claim 7, wherein the multiplexer is configured to select the first data bit of the plurality of data bits as the output data stream at the first edge transition of the first polyphase clock signal among the four polyphase clock signals, and to deselect the first data bit of the plurality of data bits as the output data stream at the second edge transition of the second polyphase clock signal among the four polyphase clock signals.

9. The double data rate circuit according to claim 1, further comprising a keeper circuit configured to maintain the output data stream in a steady state during standby mode.

10. A data generation method performed by a double data rate (DDR) circuit, The steps include receiving a source clock signal and generating a first complementary clock signal, A step of receiving the source clock signal and generating a second complementary clock signal, wherein the second complementary clock signal and the first complementary clock signal have a phase difference of 180°. The steps include generating four polyphase clock signals that are sequentially shifted in phase by 90° based on the first complementary clock signal and the second complementary clock signal, The steps include multiplexing multiple data bits into an output data stream based on at least two of the four polyphase clock signals whose phases are shifted, Equipped with, The first complementary clock signal is generated via a first clock path, and the second complementary clock signal is generated via a second clock path, and the first clock path and the second clock path each comprise one or more inverters, and the sum of the fanouts of the one or more inverters in the first clock path matches the sum of the fanouts of the one or more inverters in the second clock path. Data generation method.

11. The data generation method according to claim 10, wherein one or more inverters of the first clock path are coupled in series.

12. The data generation method according to claim 10, wherein one or more inverters of the second clock path are coupled in series.

13. The data generation method according to claim 10, wherein the first complementary clock signal and the second complementary clock signal have equal timing delays.

14. The steps include receiving one of the first complementary clock signal and the second complementary clock signal, and generating two of the four polyphase clock signals with opposite phases, The data generation method according to claim 10, further comprising the steps of receiving the other of the first complementary clock signal and the second complementary clock signal, and generating two other opposite-phase signals from the four polyphase clock signals.

15. The step of multiplexing multiple data bits into an output data stream using at least two of the four phase-shifted polyphase clock signals is: The data generation method according to claim 10, comprising the step of sequentially selecting and deselecting each of the plurality of data bits in two first edge transitions and second edge transitions of at least two of the polyphase clock signals, and outputting each selected data bit as the output data stream.

16. The steps include: selecting the first data bit of the plurality of data bits as the output data stream in the first edge transition of the first polyphase clock signal of the four polyphase clock signals; The data generation method according to claim 15, further comprising the step of deselecting the first data bit of the plurality of data bits as the output data stream in the second edge transition of the second polyphase clock signal of the four polyphase clock signals.

17. A step of receiving one of four data bits and two of the four polyphase clock signals, starting the output of the received data bit at the first edge transition of one of the two received polyphase clock signals, and stopping the output of the received data bit at the second edge transition of the other one of the two received polyphase clock signals, wherein the two received polyphase clock signals are out of phase by 90°. The data generation method according to claim 15, further comprising the step of receiving each output signal and generating the output data stream.

18. The data generation method according to claim 10, further comprising the step of maintaining the output data stream in a steady state during standby mode.

19. A memory device, A memory array equipped with memory cells, If the double data rate circuit is coupled to the memory array, It is a clock generator, A first clock path that receives a source clock signal and generates a first complementary clock signal based on the source clock signal, A second clock path that receives the source clock signal and generates a second complementary clock signal based on the source clock signal, wherein the second complementary clock signal and the first complementary clock signal have a phase difference of 180°. A clock generator equipped with, A clock divider coupled to the clock generator and configured to generate four polyphase clock signals sequentially shifted by 90° in phase based on the first complementary clock signal and the second complementary clock signal, A multiplexer coupled to the clock divider and configured to multiplex multiple data bits into an output data stream based on at least two of the four phase-shifted polyphase clock signals, A double data rate circuit, Equipped with, The first clock path and the second clock path each include one or more inverters, and the sum of the fan-outs of the one or more inverters in the first clock path matches the sum of the fan-outs of the one or more inverters in the second clock path. Memory device.

20. The memory device according to claim 19, wherein the memory device comprises a double data rate memory.

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