A system for high-speed transactions using non-volatile memory on a double data-rate memory bus.

Abstract

To provide a memory device and a system that provide high speed access to a memory in higher temperature applications.SOLUTION: A method can include: receiving a plurality of consecutive commands on a unidirectional command-address (CA) bus input of a nonvolatile memory (NVM) device, the commands being synchronous with a timing clock; and for each received command, determining if the command is an express read (NVR) command, determining if a next consecutive command is a NVR command, in which consecutive NVR commands form a NVR command sequence; in response to the no more than the NVR command sequence, accessing read data stored in NVM cells; and driving the read data on parallel data input / outputs (I / Os) of the NVM device in a burst of data values, the data values of the burst being output in synchronism with rising and falling edges of the timing clock.SELECTED DRAWING: Figure 16

Description

Technical Field

[0001] Related Applications This application is an international application of U.S. Non-Provisional Application No. 17 / 125,927, filed on December 17, 2020, which claims the benefit of priority under 35 U.S.C. 119(e) to U.S. Provisional Patent Application No. 6,308,572, filed on October 7, 2020, the content of which is incorporated herein by reference.

[0002] The present disclosure generally relates to systems that require fast access to memory devices, and more particularly to systems that access non-volatile memory devices through a double data rate interface.

Background Art

[0003] A system-on-chip (SoC) can enable high-performance control of a device in a very compact package. SoCs enjoy wide use from very compact devices (e.g., mobile phones) to very large devices (e.g., automobiles). An SoC typically includes processor circuitry and on-board memory for storing data including instructions executable by the processor. SoC performance often depends heavily on memory access speed. For ambient temperature and sub-ambient temperature applications, an SoC can include a combination of non-volatile memory (NVM) and volatile memory, such as dynamic random access memory (DRAM). NVM can store data when there is no power. DRAM can provide an acceptable access speed and can consume relatively little power. In this type of system, it is common to load data from NVM into DRAM for access by the processor and / or to back up DRAM data by NVM.

[0004] For higher temperature applications, such as in automobiles, DRAM is undesirable as a memory choice because its performance can degrade as the temperature rises. Consequently, static RAM (SRAM) can be used as volatile memory for higher temperature applications. While SRAM can offer even faster speeds than DRAM, it can have higher component costs and draw more power than DRAM.

[0005] Figure 19 is a block diagram of a conventional DRAM read operation compatible with the LPDDR4 standard published by JEDEC. At time t0, a first read command sequence may be received. The read command sequence may include two activate instructions (Activate1, Activate2), a read instruction, and a CAS instruction. The read command sequence may be received over eight clock cycles (CK_t) (i.e., from time t0 to t2).

[0006] At time t2, a second read sequence can be initiated, having the same type of instructions as the first read sequence.

[0007] The DRAM may have a read latency (RL) of 14 clocks and a skew delay (tDQSCK) of approximately 2 clocks (at a clock speed of 800 MHz). After this type of delay, at time t4, the read data may be output. The read data may be output in minimum bursts of 16 (or 32, depending on the burst length setting). For the illustrated bursts of 16, the total time to receive the bursts may be 31 clocks, or 38.75 ns at 800 MHz.

[0008] In an x32 configuration, 64 bytes can be transferred over eight clock cycles (between times t4 and t5). For a system with 32 bytes of cache memory, 32 bytes may be discarded as a result of this type of read transfer.

[0009] While DRAM (including LPPDR4-compatible DRAM as shown in Figure 19) can provide high access speeds to systems like SoCs, as mentioned above, DRAM is not suitable for certain environments, such as higher temperature environments.

[0010] It is desirable to arrive at several methods that provide high-speed access to memory in higher temperature applications without suffering the drawbacks of conventional methods. [Brief explanation of the drawing]

[0011] [Figure 1] This figure shows a non-volatile memory (NVM) device and high-speed access operation according to an embodiment. [Figure 2] This is a block diagram of an NVM device according to one embodiment. [Figure 3] This is a block diagram of an NVM device according to another embodiment. [Figure 4] This is a block diagram of an NVM device according to a further embodiment. [Figure 5] This is a timing diagram of high-speed access operation to an NVM device according to one embodiment. [Figure 6] This is a timing diagram of high-speed access operation to an NVM device according to another embodiment. [Figure 7] This is a block diagram of an NVM device having a double data rate (DDR) parallel interface (I / F) and a serial interface according to one embodiment. [Figure 8] This is a block diagram of an NVM device having a DDR parallel interface I / F and a serial I / F according to another embodiment. [Figure 9] A block diagram showing the NVM device address space according to one embodiment. [Figure 10] Figures 10A and 10B show registers of an NVM device that may be included in one embodiment, Figure 10C shows a conventional LPDDR4 command format, and Figure 10D shows a high-speed access command format according to one embodiment. [Figure 11] This is a schematic diagram of a memory cell array that may be included in one embodiment. [Figure 12] A perspective view of an integrated circuit device according to one embodiment is shown. [Figure 13] This is a block diagram of a memory controller according to one embodiment. [Figure 14] This is a block diagram of a system according to one embodiment. [Figure 15] This is a diagram of an automobile system according to one embodiment. [Figure 16] This is a flowchart of an NVM method according to one embodiment. [Figure 17] This is a flowchart of a memory controller method according to one embodiment. [Figure 18] This is a flowchart of a system method according to one embodiment. [Figure 19] This is a timing diagram of a conventional LPDDR4-compatible read access according to one embodiment. [Modes for carrying out the invention]

[0012] According to the embodiments, a non-volatile memory (NVM) device can process a decreasing sequence of commands (NVR commands) to read data from one or more array NVM cells. In some embodiments, an NVR command pair may have all the command and address data necessary for a read operation. The read data corresponding to the NVR commands can be output from the NVM device at double data rate (DDR). In some embodiments, the read data can be output in bursts of eight data units.

[0013] In some embodiments, the NVM device may have an interface compatible with a physical interface that conforms to the LPDDR4 standard.

[0014] In some embodiments, the NVR command pair can have a command value that is distributed across both NVR commands of the pair. In some embodiments, the NVR command pair can have an address value that is distributed across both NVR commands of the pair.

[0015] In some embodiments, the NVR command can have a format that follows commands according to the LPDDR4 standard. However, one or more bit positions that provide command data within the LPDDR4 command can provide address data within the NVR command.

[0016] In some embodiments, the NVM device can include a serial interface in addition to a DDR interface.

[0017] In some embodiments, the NVM device can be part of a system that performs cache line reads on the cache memory. High-speed access operations (read accesses performed by NVR commands) on one or more NVM devices can fill (fill) the cache line without having to discard any read data.

[0018] In some embodiments, the NVM device can be part of a system having a memory controller. The memory controller can issue a read command sequence having NVR commands to the NVM device and a read command sequence according to an existing standard (e.g., LPDDR4) to other devices (e.g., dynamic random access memory (DRAM)). The read sequence according to the existing standard can have more commands (e.g., four commands) compared to a sequence of NVR commands (e.g., two commands).

[0019] In the following various embodiments, similar items are referred to by the same reference numeral, but the first digit of which corresponds to the drawing number.

[0020] Figure 1A is a block diagram of an NVM device 100 according to one embodiment. The NVM device 100 may include one or more memory cell arrays 102 and a DDR interface 104. In the illustrated embodiment, the memory cell array 102 may be an NVM cell array 102 which may include any suitable type of NVM cell that can hold data when power is unavailable. In some embodiments, the NVM cell array 102 may include decoder circuits for accessing NVM cells in response to address values ​​and write circuits (e.g., program and erase circuits) for storing data values ​​within the NVM cells. In some embodiments, the memory cell array 102 may include volatile memory cells, including but not limited to dynamic random access memory (DRAM) cells and / or static RAM (SRAM) cells, along with suitable access and auxiliary circuits (e.g., decoder circuits, refresh circuits for DRAM, etc.).

[0021] The DDR interface 104 may include a command and address (CA) input, a parallel data connection (DQ), and one or more clock inputs (CLK). The CA input can receive command and address data for accessing storage locations in the NVM cell array 102. The CLK input can receive one or more clock inputs for timing inputs and output signals for the NVM device 100. The DQ connection can output parallel data values ​​in response to requests received on the CA input. The output data values ​​can be provided synchronously with the rising and falling edges of the input clock (i.e., at double data rate). In some embodiments, the DQ may be unidirectional and only provide output data from the NVM device. However, in other embodiments, the DQ may be bidirectional and capable of both receiving and outputting data.

[0022] In some embodiments, the DDR interface 104 may have signal transmissions compatible with existing memory standards. In one embodiment, the DDR interface 104 may have signal transmissions compatible with the LPDDR4 standard published by JEDEC. That is, the DDR interface 104 may have a physical interface compatible with the LPDDR4 physical interface standard (i.e., LPDDR4 PHY).

[0023] The DDR interface 104 may have signal transmissions compatible with existing standards, but it may be able to handle shorter read command sequences than existing standards of this kind. In some embodiments, the DDR interface 104 may be compatible with LPDDR4 PHYs, but it may be able to handle faster read sequences of two commands, in contrast to the four-command read sequence defined by the LPDDR4 standard.

[0024] The DDR interface 104 may include a command decoder 105 for performing the high-speed access described in this specification. In some embodiments, the command decoder 105 may recognize high-speed access commands and enable access to the NVM cell array 102. In some embodiments, the command decoder 105 may distinguish high-speed access commands from other commands. A continuous sequence of high-speed access commands may be considered a high-speed command sequence. A high-speed command sequence may include all instructions and address data for performing access to the NVM device 100. In some embodiments, the DDR interface may be compatible with existing standards (e.g., LPDDR4), and the high-speed command sequence may include fewer commands than access according to existing standards.

[0025] In some embodiments, the CA input can be less than 7 bits wide, and the DQ connection can be less than 20 bits wide.

[0026] In some embodiments, the NVM device 100 can be an integrated circuit device that includes one or more integrated circuit (IC) substrates formed within a single IC package.

[0027] Figure 1B is a timing diagram showing access operations for an NVM device like the one in Figure 1A. Figure 1B shows a read access compatible with a given standard (Std) and a high-speed read access (fast) to the NVM device according to one embodiment that can occur in fewer clock cycles than a standard read access.

[0028] Figure 1B includes waveforms for the timing clock (CK), CA input for standard access (CA(Std)), CA input for high-speed access (CA(high-speed)), output data for standard access (DQ(Std)), and output data for high-speed access (DQ(high-speed)).

[0029] At time t0, a read command sequence is available to the memory device. A read command sequence can contain a command and address value for a single read operation. Figure 1B shows command address values ​​for the standard and fast cases. As illustrated, a standard read command sequence requires "n" commands (from Std0 to Stdn), where n is greater than 2. In contrast, fast access consists of fewer NVR commands (NVR1, NVR2, and possibly NVR3).

[0030] In response to receiving the first NVR command (NVR1), the command is evaluated (shown as 147) to determine if it is a fast access command. If the received command is a fast access command, the next command in the sequence is evaluated to determine if it is a fast access command. A set of consecutive fast access commands can form a fast access command sequence. Thus, Figure 1B shows the fast access command sequence for NVR1 / NVR2 (two sequences) and optionally the fast access command sequence for NVR1 / NVR2 / NVR3 (three sequences).

[0031] At time t1, the reception of the high-speed read command sequence (NVR1 / NVR2) can be completed. After time t1 and before time t2, the high-speed read command sequence (NVR1 / NVR2 / NVR3) can be completed.

[0032] At time t2, it is possible to complete the reception of a standard read command sequence (shown as ACT1, ACT2, READ, CAS2, but not limited to any specific protocol / standard) that requires more clock cycles than the fast case.

[0033] At time t3, data corresponding to the high-speed read command sequence can be output.

[0034] At time t4, data output for high-speed access from the NVM device can be completed. In the illustrated example, data corresponding to the standard read command sequence can also be output at this time.

[0035] Data output for standard access can be completed within time t5.

[0036] In the illustrated embodiment, the high-speed read operation can involve fewer commands (and therefore fewer clock cycles) and optionally capture data in a smaller burst sequence than a standard read access. As a result, the high-speed read operation can occupy less time on the CA bus and capture data in a shorter time than a standard read operation. In some embodiments, the smaller burst sequence can be an optional feature of the memory device, and larger burst sequences (including those of conventional size) are supported.

[0037] Figure 1B shows that an NVR command is received over two clock cycles of CK, but alternative embodiments may be able to receive NVR commands over a longer number of clock cycles. As just one example, the command and address data contained within NVR1 / NVR2 in Figure 1B may be contained within a single NVR command that occupies four clock cycles.

[0038] In some embodiments, NVR commands are receivable over j × 2 clock cycles, where j is an integer greater than or equal to 1.

[0039] Figure 1C shows various examples of fast read (NVR) command sequences according to an embodiment. It should be understood that this type of sequence occurs over time as a series of commands issued from and / or received by the controller device. The series of commands can be commands that are received one after another without an intervening delay, or without an intervening delay of a sufficiently long period.

[0040] The NVR command sequence 149A represents two command sequences (NVR1 / NVR2) that terminate when no further commands are received. From the bit values ​​of NVR1, the command decoder can determine that the command is an NVR command. As a result, the command decoder can treat the next consecutive command as a possible NVR command. Thus, NVR2 is detectable in the next NVR command of the sequence. In the illustrated embodiment, the NVR command sequence 149A terminates when there are no consecutive commands after NVR2. In some embodiments, commands are received over a predetermined number of timing clock cycles. Any NVR command sequence can be considered terminated if no commands are received over this amount of clock cycles.

[0041] When a command sequence finishes, the resulting NVR commands (NVR1 / NVR2) are used to access the NVM cell. That is, commands NVR1 / NVR2 are understood to contain all the necessary commands and address data for read access.

[0042] NVR command sequence 149B exhibits an NVR command sequence similar to 149A, but NVR command sequence 149B ends with the reception of a command that is not an NVR command. The command decoder detects NVR1 and then examines the next command (NVR2), which is also an NVR command, and can determine that it is part of the same NVR command sequence. Since NVR2 is an NVR command, the command decoder can then look at the next consecutive command (MRR1) and determine if it is an NVR command. However, in this case, MRR1 is not an NVR command. As a result, the NVR command sequence can end, and the NVM cell is accessed by the address values ​​of NVR1 / NVR2.

[0043] NVR command sequence 149C is an NVR command sequence similar to 149A, but with more NVR commands. In some embodiments, the address space of the target memory device may require more address bits than can be provided by two NVR commands. Therefore, one or more NVR commands (in this case, one command NVR3) can be added to the NVR command sequence. Longer fast read command sequences can be terminated in the same manner as described above. Furthermore, an NVR command sequence can have any number of NVR commands, including more than three NVR commands.

[0044] Please understand that an NVR command sequence can contain a single NVR command.

[0045] While embodiments can take various forms, some embodiments can be a single integrated circuit (IC) device having one or more integrated circuit dies. Figures 2 to 4 show three of the many possible IC devices according to the embodiments.

[0046] Figure 2 is a block diagram of an NVM IC device 200 having a single die 207 formed within an IC package 205. The IC package can take any suitable form, including but not limited to ball grid arrays (BGAs) including fine-pitch BGAs (FBGAs), small outline packages, flat packages, pin grid arrays, or chip carriers. The die 207 may include an NVM cell array 202, a DDR I / F 204, and a serial I / F 206. The NVM cell array 202 may take any form described in this specification or an equivalent. In some embodiments, the NVM cell array 202 may include a first bank 202-0 and a second bank 202-1.

[0047] The DDR I / F 204 may include a CS input, a clock input (CLK), a CA input, and DQ and data strobe outputs (DQS). The DDR I / F 204 may also include a command decoder 205 and equivalents capable of decoding the high-speed access commands described herein (e.g., NVR1, NVR2…NVRn). The DDR I / F 204 may enable access to the NVM cell array 202, including read and write operations. In some embodiments, in addition to high-speed access, the DDR I / F 204 may enable or be configurable to enable standard access. In some embodiments, the command decoder 205 may process a continuous, uninterrupted sequence of NVR commands (e.g., a first NVR1 / NVR2 pair followed immediately by a second NVR1 / NVR2 pair) for each of banks 202-0 / 1, enabling uninterrupted output of data from banks 202-0 / 1 on the DQ at double data rate.

[0048] The serial interface 206 can enable access to the NVM array 202 via a serial bus. The serial interface 206 can include a serial chip select input (SERIAL_CS), a serial clock input (SERIAL_CLK), and serial data I / O (SERIAL_DQ). SERIAL_CS can enable the selection of the NVM device 200 for access by other devices (e.g., a host device) via the serial interface 206. SERIAL_CLK can receive timing signals to synchronize data input to and data output from the NVM device 200. SERIAL_DQ can receive commands, addresses, and data values ​​for accessing storage locations (including configuration registers) of the NVM device 200. SERIAL_DQ can output serial data in response to access.

[0049] Figure 3 is a block diagram of an NVM IC device 300 having a first die 307A and a second die 307B formed within the same IC package 305. The IC package can take any suitable form as described herein. The first die 307A may include an NVM cell array 302A, a DDR I / F 304, and a serial I / F 306A, as in Figure 2. The second die 307B may include an NVM cell array 302B and a serial I / F 306B. The first and second dies 307A / B are connected by an internal bus 309. Access via the DDR I / F 304 allows access to the NVM cell array 302A on the first die 307A, and access via the internal bus 309 allows access to the NVM cell array 302B on the second die 307B. A shared serial bus 311 may allow access to one of the dies 307A / B via a common serial input 313.

[0050] The DDR I / F 304 can operate as shown in Figure 2. However, the command decoder 305 can process a continuous, uninterrupted NVR sequence targeted on banks of different dies (e.g., 302-0A / 302-0B) and enable uninterrupted output of data from banks 302-0A / 302-0B on DQ_A / B.

[0051] Figure 4 is a block diagram of an NVM IC device 400 having a first die 407A and a second die 407B formed within the same IC package 405. The NVM IC device 400 may have items similar to those in Figure 3. The NVM IC device 400 may differ from Figure 3 in that each die 407A / B may have a DDR I / F 404A / B, each including a chip select input (CS_A / B), clock input (CLK_As / Bs), CA input (CA_A / B), DQ (DQ_A / B), and DQS (DQS_A / B). Each DDR I / F 404A / B may also have its own command decoder 405A / B. In some embodiments, the command decoder 405A can process a continuous, uninterrupted NVR sequence targeted in banks 302-0A / 1A within the NVM cell array 402A, and the command decoder 405B can process a continuous, uninterrupted NVR sequence targeted in banks 302-0B / 1B within the NVM cell array 402B.

[0052] In the embodiments shown in Figures 2 to 4, the DDR interface (any of 204, 304, 404A, or 404B) can have signal transmission compatible with the DDR standard published by JEDEC. In some embodiments, this type of DDR interface can be compatible with the LPDDR4 standard published by JEDEC.

[0053] In the embodiments shown in Figures 2 to 4, the serial interface (either 206, 306A / B, or 406A / B) can be compatible with the Serial Peripheral Interface (SPI) standard, which includes having one serial data line or having multiple serial data lines (e.g., quad SPI).

[0054] Figure 5 is a timing diagram showing high-speed read operation for an NVM device according to one embodiment. In Figure 5, it is assumed that access may occur through a DDR interface having inputs compatible with the LPDDR4 PHY standard. However, the DDR interface can handle high-speed access commands that may include command sequences with fewer commands than conventional LPDDR4 access. Figure 5 shows the following waveforms, namely, CS represents the chip select input (CS), CA[5:0] represents the command address input (with a 6-bit bit width), CMD is the write representation of the instruction data received on CA, CK_t is the timing clock, DQS[1:0] represents the data strobe output, DQ[15:0] represents the data I / O with a 16-bit bit width, and DM[1:0] represents the output configured to provide error correction code (ECC) data corresponding to the data output on DQ.

[0055] At time t0, CS can go high and select the NVM device for access operation. Also at time t0, the NVM device can begin receiving a command sequence on CA for a first fast read operation. This type of command sequence can take the form of a first NVR command (NVR-1). The first NVR command (NVR-1) is received over one clock cycle (CK_t) and is followed by a second NVR command (NVR-2) received over the other clock cycle. However, it should be understood that alternative embodiments may include sequences of more than two NVR commands.

[0056] At time t1, CS can become high again and continue selecting an NVM device for access operations.

[0057] At time t2, the first access can be completed because the first command sequence has completed approximately three clock cycles. In response to the command sequence, the NVM device can initiate access to the NVM cell for the requested read data.

[0058] At time t3, CS can become high again and continue selecting an NVM device for the access operation. Also at time t3, a second fast access operation can be initiated. The second access operation can occur in the same way as the first access operation.

[0059] At time t4, the second access can be completed by the second command sequence being received over four clock cycles. In response to the second command sequence, the NVM device can initiate access to the NVM cell for a second set of read data. Time t2 through t4 can be the column-to-column delay time (tCCD), which can be four clock cycles.

[0060] Time t5 can mark the end of the read latency (RL) time, which can vary according to the clock speed and NVM device architecture. In the illustrated embodiment, RL can be 14 clock cycles.

[0061] At time t6, after RL time and an additional clock skew delay (tDQSK), the read data (D0 to D7) for the first access is available on DQ along with the corresponding data strobe signal DQS. The read data is available at double the data rate relative to CK_t and can have a burst length (BL) of 8. In addition, when DM is output, 2 bits of ECC data are available along with each read data value. In the illustrated embodiment, through each of the two clock cycles after t6, DQ / DM can output 64 bits of read data along with 8 bits of ECC data.

[0062] At time t7, the data read for the second access (D0 to D7) can be output on DQ immediately after the data read for the first access. This second set of data read can have the same general format as the first data read.

[0063] Referring still to Figure 5, the sequence of read commands NVR1 / NVR2 can take four clock cycles. Figure 5 shows a 16-bit (i.e., x16) DQ, but it should be understood that other embodiments may include a 32-bit (i.e., x32) access. As two of many possible examples, the NVR1 / NVR2 command can be targeted to two NVM devices, each of which returns x16 bits. Alternatively, the NVM devices can have x32-bit output. Thus, while Figure 5 shows data output at x16 bits per half-clock cycle, in a two-device / bank configuration, data can be output at x32 bits over eight half-clock cycles. In this type of configuration, two NVM devices (or one NVM device with x32DQ) can output 32 bytes of data over four clocks. This type of read operation is pipelined (i.e., Figure 5 shows two read operations being pipelined, but pipelined operation of a larger number of read operations is possible). In many systems, cache memory access writes data to a cache line with a size of 32 bytes. Therefore, each pipelined NVR read access can fill one cache line without any wasted data.

[0064] As shown in Figure 5, the time between the start of the high-speed read command (t0) and the time when all data is output (t7) can include 3 clock cycles for the command address data (NVR1 / 2), 14 clock cycles for RL, 2 clock cycles for tDQSK, and 4 clock cycles for the data (BL=8). At a clock speed of 800MHz, the total time can be 28.75ns. Thus, using pipelined high-speed read access, the first cache line can be filled with data from non-volatile memory in 28.75ns, and the next cache line is filled every 5ns (i.e., 4 clock cycles). This is in stark contrast to the conventional access operation in Figure 19, which takes 38.75ns for the first cache line, 10ns for each subsequent operation, and discards 32 bytes from each read dataset.

[0065] Figure 5 shows an embodiment having 8 BLs, but embodiments can also support larger BL sizes. In some embodiments, 8 BLs can be a selectable feature among other BL sizes (e.g., 32). Furthermore, other embodiments can provide BLs larger than 8, for example, 16 BLs, and do not support the shorter BL size of 8.

[0066] Figure 6 is a timing diagram showing access operation for an NVM device according to another embodiment. Figure 6 shows access through the DDR interface, as in Figure 5, but targets two different NVM devices. Figure 6 shows waveforms similar to Figure 5, except that there may be two chip select waveforms, CS0 and CS1. Furthermore, there may be two different data strobe signals, DQSA and DQSB.

[0067] The operation can occur in the same general manner as shown in Figure 5, but the first NVM device is selectable by signal CS0 between times t0 and t1, and the second NVM device is selectable by signal CS1 between times t2 and t3. In some embodiments, there may be a time tBT separating the NVR sequence for one device (NVR1A / NVR2A) from the NVR sequence for the next device (NVR1B / NVR2B). Time tBT can vary according to the device type and clock speed. As some of the many possible examples, at a clock speed of 800 MHz, tBT can be two clock cycles (CK_t), and at a clock speed of 1600 MHz, tBT can be four clock cycles. Data output on the DQ between times t4 and t5 may come from the first NVM device, and data output on the DQ after time t5 may come from the second NVM device. In some embodiments, there may be a time tDQBT separating the datasets.

[0068] Figure 7 is a block diagram of an NVM device 700 according to another embodiment. The NVM device 700 may be one embodiment of the devices and dies shown in the other embodiment. The NVM device 700 may include a first interface 704, a second interface 706, and many separately addressable banks 702-0 to 702-3. The first I / F 704 may be a parallel DDR I / F that receives command sequences at the CA input and provides parallel output data on the data output DQ synchronized with the rising and falling edges of the clock CLK. The first interface 704 is connectable to a parallel data bus 710. The parallel data bus 710 may have command and address values ​​transmitted through the CA bus, which is separate from the data bus DQ on which data can be output (or input). In some embodiments, signal transmission on the first I / F 704 may be compatible with the LPDDR4 standard. The first I / F 704 may also include a command decoder 705 and equivalents for handling the high-speed access described herein.

[0069] The second I / F 706 can be a serial I / F that enables serial data transactions on one or more serial data I / Os (S_DQ) in synchronization with the serial clock S_CK. The second I / F 706 is connectable to the serial bus 708. In some embodiments, the second I / F 706 can be compatible with the SPI standard.

[0070] Each bank (702-0 to 702-3) can contain many NVM cells. Within each bank (702-0 to 702-3), the NVM cells can be arranged in one or more arrays. The NVM cells can take any suitable form and, in some embodiments, can be "flash" type NVM cells. The banks (702-0 to 702-3) are independently addressable. That is, the physical addressing of device 700 can have separate bank addresses for each bank (702-0 to 702-3). All banks (702-0 to 702-3) can be connected to the first bus system 712A and the second bus system 712B. The first bus system 712A can connect banks (702-0 to 702-3) to the first I / F 704, and the second bus system 712B can connect banks (702-0 to 702-3) to the second I / F 706. Figure 7 shows a device with four banks, but embodiments may include more or fewer banks.

[0071] In some embodiments, bank addressing can enable pipelined access to NVM devices via high-speed access commands (e.g., command vs. NVR1 / NVR2). Command sequences for different banks are receivable on the first interface 704 in a pipelined manner (i.e., with no intervening data between command address values ​​and minimal or no delay between command address values). In response to this type of pipelined command sequence, data from different banks can be output on the DQ in sequential bursts, with minimal or no delay between these bursts.

[0072] Figure 8 is a block diagram of an NVM device 800 according to a further embodiment. The NVM device 800 can be any one embodiment of those shown in this specification. The NVM device 800 may include a DDR4 I / F 804, a Quad SPI (QSPI) compatible I / F 806, an LPDDR4 compatible physical layer interface (PHY) 816, a QSPI compatible PHY 818, a plurality of banks 802-0 to 802-7, first access paths 820-0 to 820-7 for each bank (802-0 to 802-7), second access paths 822-0 to 822-7 for each bank (802-0 to 802-7), and a parameter / configuration register 821.

[0073] The LPDDR4 PHY816 may include a first DQ[7:0] having a chip select CS input, a clock input CK_t, a CA input, and a corresponding data clock output DQS0_t, and a second DQ[15:8] having a corresponding data clock output DQS1_t. These types of inputs and outputs can be connected to an LPDDR4-compatible bus 810. The DDR4 I / F804 processes command and address data and may include a command decoder 805, which can process fast access command address values ​​that can be received in a command sequence (e.g., NVR1…NVRn), with each command in the sequence received through CK_t of two cycles or less. In some embodiments, the DDR4 I / F804 can also process LPDDR4-compatible commands (e.g., address data commands received through eight clocks). In some embodiments, the DDR4 I / F804 may be a read-only interface for user memory access and not an interface that processes write commands to user memory. In some embodiments, the DDR4 I / F 804 can handle write operations to the configuration and / or other registers of the NVM device 800.

[0074] The DDR4 I / F 804 can be connected to banks (814-0 to 814-7) via the first bus system 812A. The DDR4 I / F 804 can process pipelined high-speed access commands every four clock cycles and provide corresponding output data on the DQ at double data rate in bursts of eight. In some embodiments, this type of continuous pipelined high-speed access command can be for different banks 802-0 to 802-7.

[0075] The QSPI PHY818 can include a serial chip select SPI_CS, a serial clock input SPI_CK, and four serial data I / O SPI_DQ. These types of I / O can be connected to the SPI-compatible serial bus 808. The QSPI I / F 806 can process commands received by the QSPI PHY818, including QSPI-compatible commands. These commands can include both read and write (e.g., program, erase) commands.

[0076] The parameter / configuration register 821 can store parameter values ​​that indicate the capabilities of the NVM device 800, which are accessible by other devices. In some embodiments, register 821 can store parameter values ​​that indicate the NVM device 800 is capable of performing high-speed access operations.

[0077] Each bank (802-0 to 802-7) may contain NVM cells arranged in rows and columns. Each bank (802-0 to 802-7) is independently accessible via a unique bank address. In some embodiments, the NVM cells may be erasable (e.g., flash cells) groups. Read paths (820-0 to 820-7) may enable read access to their corresponding banks (802-0 to 802-7) from the DDR4 I / F 804 via the first bus system 812A. In some embodiments, the read paths (820-0 to 820-7) may also be write paths that enable writing data into the banks (802-0 to 802-7) from the DDR2 I / F 804. The R / W paths (822-0 to 822-7) can be used to enable read or write access to their corresponding banks (802-0 to 802-7) from the QSPI I / F 806 via the second bus system 812B.

[0078] According to the embodiment, the NVM device may include an address space for user data and storage locations for data specific to the NVM device. This type of address space may include locations for parameter data indicating high-speed access capability and / or configuration data for configuring the NVM device for high-speed access operation.

[0079] Figure 9 shows the NVM device 900, which has an address space 923, an LPDDR I / F 904 connectable to a parallel bus 908, and a serial I / F 906 connectable to a serial bus 910. The LPDDR4 PHY 904 can be compatible with the LPDDR4 standard PHY. The serial I / F 906 can be compatible with the SPI standard.

[0080] The address space 923 may include various storage locations accessible by a given address. In some embodiments, the NVM device 900 may have address reconfiguration capabilities for logical-to-physical address translation and / or wear leveling, just as an example. In the illustrated embodiment, the addressable space 923 may include any of the following: user space 902, LPDDR4 mode registers 921-0, device identification (ID) registers 921-1, device parameter registers 921-2, safe area 921-3, and serial I / F registers 921-4. The user space 902 may include an NVM cell array for storing user data in a non-volatile manner and may be accessible via the LPDDR4 I / F 904 and SPI I / F 906.

[0081] The LPDDR4 mode register 921-0 can store values ​​for configuring the LPDDR4 I / F 904. In some embodiments, the LPDDR4 mode register 921-0 may include a register for establishing the BL size, which includes, but is not limited to, short BL sizes such as 8 and / or larger BL sizes such as 16 or 32. In some embodiments, the LPDDR4 mode register 921-0 may include a standard access configuration register 924. Depending on the values ​​stored in the high-speed access control register 924, the NVM device 900 can execute a sequence of standard access commands, which may include more commands than high-speed access. In some embodiments, the NVM device 900 can perform high-speed access by determining whether a sequence of commands is an NVR command. The standard access configuration register 924 may enable an LPDDR4 command sequence of four commands in addition to high-speed commands. The LPDDR4 mode register 921-0 is accessible via the LPDDR4 I / F 904 or the SPI I / F 906.

[0082] The device ID register 921-1 can store a value that allows other devices in the system to identify the NVM device 900. In some embodiments, the value stored in the device ID register 921-1 may indicate that the NVM device is capable of executing fast access commands. The parameter register 921-2 can store a value that allows other devices in the system to identify the capabilities of the NVM device 900. In some embodiments, the parameter register 921-2 may include a fast access parameter register 925 that can indicate that the NVM device is capable of executing fast access commands. Other devices (i.e., the host and / or memory controller) can access the parameter register 921-2 and / or the device ID register 921-1 to determine that the NVM device 900 is capable of executing fast access commands.

[0083] The secure area 921-3 can store data values ​​that are not accessible by devices outside the NVM device or that can only be accessed through secure access procedures such as an authentication process. Some or all of the DDR I / F register 921-0, device ID register 921-1, parameter register 921-2, and serial I / F register 921-4 can be designated as a secure area.

[0084] The serial I / F registers 921-4 can store values ​​for configuring the serial I / F 906. In some embodiments, the device ID register 921-1, parameter register 921-2, and serial I / F registers 921-4 are accessible via the serial I / F 906 rather than via the DDR I / F 904.

[0085] Figure 10A shows an example of a DDR I / F register 1021-1 that may be included in an NVM device according to one embodiment. The DDR I / F register 1021-1 may include various registers for configuring the DDR I / F, including a high-speed access control register 1024. The high-speed access control register 1024 can store values ​​that control various characteristics of high-speed access operation, including but not limited to the number of clock cycles in a received command, any delay between back-to-back accesses (e.g., tBT), and burst length for data.

[0086] Figure 10B shows an example of parameter registers 1021-2 that may be included in an NVM device according to one embodiment. Parameter registers 1021-2 may include various registers for indicating parameters of the NVM device, including standard access compatible registers 1025. Standard access compatible registers 1025 are accessible by other devices (e.g., a host or controller), indicating that the NVM device may perform standard access and equivalents that may require longer command sequences than the fast access described in this specification.

[0087] Of course, the configuration or parameter registers can take any form appropriate to the architecture of the NVM device.

[0088] Figure 10C shows the format of a conventional LPDDR4 read command 1035. A conventional read command 1035 may include a first part 1035H that is received when CS is high (and during the first clock cycle) and a second part 1035L that is received when CS is low (and during the second clock). A conventional read command 1035 may include bit positions to store command data (CMD). The bit positions correspond to CA bus bits CA0 and CA1 during the first clock cycle. An LPDDR4 command sequence may include four commands ACT1, ACT2, READ, and CAS having this format.

[0089] Figure 10D shows the format of an NVR command 1039 according to one embodiment. The NVR command 1039 may have the same format as a conventional LPDDR4 command, including 6 bits received in two clock cycles. The NVR command 1039 may differ from a conventional LPDDR4 command in that the bit positions that provide command data in an LPDDR4 command (e.g., 1037 in Figure 10C) may provide address information 1041 in the NVR command. Figure 10D shows that CA1 provides address data, but in other embodiments, CA0 may provide address data (whereas CA1 provides command data). As emphasized in this specification, a command sequence for high-speed access operation may include two or three NVR commands, in contrast to the four commands required by a conventional LPDDR4 read operation.

[0090] The embodiments may include any suitable NVM array structure or NVM cell type, but some embodiments may include a 1-transistor (1T) NOR type array. Figure 11A is a schematic diagram of a 1T NOR array 1102A that may be included in one embodiment. Array 1102A may include many memory cells (one shown as 1126-0) arranged in rows and columns, where memory cells in the same row are connected to the same word line (one shown as 1126-2), and memory cells in the same column are connected to the same bit line (one shown as 1126-3). In some embodiments, the memory cell (1126-0) has a charge storage structure 1126-1 between a control gate and a channel, which can be formed by a single transistor structure. The charge storage structure 1126-1 can store data of one or more bits as charge (including the absence of charge). The charge storage structure 1126-1 can take any suitable form, including but not limited to floating gates, charge storage dielectrics (e.g., replacement gates), or combinations thereof.

[0091] The embodiments may include any suitable volatile array structure or volatile memory cell type. Figure 11B is a schematic diagram of a possible volatile memory cell array that may be included in the embodiments. Figure 11B shows array 1102B, which may include many volatile memory cells (one shown as 1126-0V) arranged in rows and columns and connected to one or more bit lines (e.g., 1126-3) and word lines (e.g., 1126-2). The volatile memory cell (1126-0V) may take any suitable form, including but not limited to DRAM cell 1126-0V1 and / or SRAM cell 1126-0V2. The SRAM cell 1126-0V2 includes, but is not limited to, 4-transistor (4T), 6T and / or 8T variations.

[0092] In some embodiments, volatile memory cells can be accessed using high-speed read commands (NVR1 / NVR2) in the same manner as the NVM cells described in this specification. In some embodiments, the memory device may include both NVM cells and volatile memory cells, both of which are accessible by high-speed read commands. In other embodiments, the memory device may receive high-speed access commands that access only the volatile memory cells.

[0093] The embodiments may include a system having a memory device that operates in conjunction with a host device, but the embodiments may also include a standalone NVM device having a parallel I / F formed within a single IC package. This type of embodiment is shown in Figure 12. Figure 12 shows a packaged NVM device in a perspective top view 1200T and a bottom view 1200B. The NVM device 1200T / B may include many physical connections (e.g., 1127), all or some of which are connectable to the DDR I / F described herein. This type of DDR I / F is capable of handling the high-speed access commands and equivalents described herein. However, it should be understood that the memory device according to the embodiments may include any other suitable package type, including directly bonding the memory device die onto a system circuit board.

[0094] The embodiment may include an NVM device, but the embodiment may also include a memory controller capable of generating high-speed commands and address values ​​through a DDR I / F for the NVM device. Figure 13 shows a memory controller 1330 according to one embodiment.

[0095] The memory controller 1330 may include a command queue 1334, a write queue 1336, a read queue 1338, a transaction processing circuit 1340, a PHY interface circuit 1342, an LPDDR4 PHY 1316, and an ECC circuit 1348. The command queue 1334, write queue 1336, and read queue 1338 are connectable to a controller I / F 1332, which is connectable to a controller (e.g., a host processor). The command queue 1334 can receive memory requests through the controller I / F 1332 and access NVM devices connected to an LPDDR4-compatible bus 1310. The write queue 1336 can receive write data to be programmed into the NVM device via the LPDDR4 PHY 1316. The read queue 1338 can output read data received from the NVM device via the LPDDR4 PHY 1316.

[0096] The transaction processing circuit 1340 may include a command encoding circuit 1344 and a configuration register 1320. The command encoding circuit 1344 may include standard encoding 1346-0 and high-speed encoding 1346-1. Standard encoding 1346-0 converts memory requests into a format compatible with the LPDDR4 standard. encoding This is possible (for example, a sequence of four commands is transmitted through eight clock cycles). High-speed coding 1346-1 allows memory requests to be converted into a high-speed access format (e.g., a sequence of one or more consecutive NVR commands). encoding It is possible. In some embodiments, commands can be used between different formats (e.g., standard / fast). encoding This can be done in response to requests received through command queue 1334. That is, requests from the controller can indicate whether access should take a standard or fast format. Additionally or alternatively, commands encoding The process involves storing high speed in the configuration register 1320. encodingIt can be controlled according to register value 1324.

[0097] The PHY I / F circuit 1342 can generate input signals from command and address values ​​for appropriate signal transmission by the LPDDR4 PHY 1316, and can organize data values ​​from signals received by the LPDDR4 PHY 1316. The LPDDR4 PHY 1316 is connected to the LPDDR4 bus 1310 and can transmit signals and receive data, including transmitting command address values ​​for high-speed access operation and receiving read data from high-speed access. The ECC circuit 1348 can perform error detection and correction operations on data values ​​received by the LPDDR4 PHY 1316. In some embodiments, the ECC circuit 1348 can use ECC values ​​received on the DM input of the LPDDR4 bus 1310.

[0098] The embodiment may also include a system that can use high-speed access operations to an NVM device to fill the cache memory lines of a controller device (e.g., a system or host CPU). Figure 14 shows a system 1450 according to one embodiment of this type.

[0099] System 1450 may include one or more NVM devices (two of which are indicated as 1400-0 and 1400-1), a host system 1443, and optionally a dynamic random access memory (DRAM) device 1458. NVM devices 1400-0 / 1 may include an NVM array 1402, a DDR I / F 1404, and a serial I / F 1406. NVM devices 1400-0 / 1 may be connected to a DDR bus 1410 via the DDR I / F 1404 and to a serial bus 1432 via the serial I / F 1406. NVM devices 1400-0 / 1 may perform the high-speed access operations or equivalents described herein.

[0100] The host system 1443 may include a DDR memory controller 1430, a CPU subsystem 1452, and a serial bus memory controller 1445. The DDR memory controller 1430 is connectable to the DDR bus 1410 and the CPU subsystem 1452. In response to a request from the CPU subsystem 1452, the DDR memory controller 1430 can generate a command sequence, including the NVR commands and equivalents described herein, through the CA portion of the DDR bus 1410. The CPU subsystem 1452 may include one or more processing circuits 1429, instructions 1431 that can be executed by the processing circuits 1429, and a cache memory 1454. The serial bus memory controller 1445 is connectable to the serial bus 1432. In response to a request from the CPU subsystem 1452, the serial bus memory controller 1445 can generate serial commands and data and access devices on the serial bus 1432, including NVM devices 1400-0 / 1.

[0101] Having described various parts of System 1450, the following describes the cache-fill operation for the system.

[0102] The cache memory 1454 can be organized into cache lines (one of which is indicated as 1454-0) accessible by the processing circuit 1429. According to the embodiment, the DDR memory controller 1430 can access one or more NVM devices 1400-0 / 1 by two fast read operations to capture data to fill the cache lines (two of which are indicated as 1454-0) without discarding any data. In some embodiments, a fast read command sequence for one or two NVM devices 1400-0 / 1 can capture an amount of read data equal to the cache lines. In some embodiments, each fast read command sequence consists of a command sequence of only two commands. However, as can be understood from the embodiments of this specification, a fast command sequence may include fewer or more fast read (i.e., NVR) commands.

[0103] In some embodiments, this type of cache line fill operation is possible for a single NVM device. For example, via data path 1433-0, the DDR memory controller 1430 can issue a high-speed read sequence to the NVM device 1400-0 to access data 1455a. Data 1455a can be output in a burst sequence, which can be equal to a cache line. In some embodiments, this type of data burst can be x32 (32-bit wide), have a burst length of 8, and can fill a 32-byte cache line.

[0104] In some embodiments, the high-speed read sequence is pipelined (e.g., output without delay or without other intervening commands or operations). As just one example, in pipelined operation, data 1455a and 1455b can be output successively to fill two cache lines 1454-0 without discarding any data. In some embodiments, data 1455a can be stored in one bank of NVM device 1400-0, and data 1455b can be stored in the other bank of NVM device 1400-0.

[0105] In some embodiments, cache line fill operations are possible for different NVM devices. For example, the DDR memory controller 1430 can output a fast read sequence to both NVM device 1400-0 and NVM device 1400-1. The fast read sequence can access data 1455a and data 1455b'. Data 1455a and data 1455b' can be equal to the size of the cache line. In some embodiments, NVM devices 1400-0 and 1400-1 can each provide 8 x16 data bursts in parallel, filling a 32-byte cache line. Fast read operations for multiple devices can be pipelined, each outputting sequential datasets that fill a cache line.

[0106] In some embodiments, a cache fill operation is possible for the DRAM device 1458. The DRAM device 1458 may include a DDR interface 1404' that is compatible with (or programmable to be compatible with) the execution of high-speed read commands.

[0107] Still referring to Figure 14, in some embodiments, the CPU subsystem 1452 may include either a parameter request procedure 1431-0 or a high-speed access configuration procedure 1431-1. The parameter request procedure 1431-0 may request parameter data from an NVM device 1400-0 / 1 that can identify whether this type of device is compatible with high-speed access operation. The high-speed access configuration procedure 1431-1 may write data values ​​and configure the DDR memory controller 1430 for high-speed access operation.

[0108] In some embodiments, the DRAM device 1458 may have a DDR interface 1404' that is compatible with high-speed access commands, as described above. In other embodiments, the DRAM DDR I / F 1404' may not be compatible with high-speed access commands.

[0109] Referring to Figure 15, a vehicle system 1566 according to one embodiment is illustrated. The vehicle system 1566 may have a number of subsystems (two shown as 1550-0 and 1550-1) operated by a host device (e.g., a CPU subsystem) that communicates with one or more NVM devices. This type of subsystem (1550-0, 1550-1) may include an electronic control unit (ECU) and / or an advanced driver-assistance system (ADAS). However, in other embodiments, this type of subsystem may include a dashboard display / control subsystem and / or an information entertainment subsystem, as just two of many possible examples. Each subsystem (1550-0, 1550-1) may include a host device that can access the NVM device by fast access commands and equivalents for fast data acquisition, as described in this specification. In some embodiments, this type of access may be for fast cache line filling. In some embodiments, the host device may be configured to execute code directly from the NVM device (i.e., execute in place). This is in stark contrast to conventional systems where data (e.g., code) can be loaded into volatile memory (e.g., SRAM) from a conventional NVM device for access by the host device.

[0110] The devices and systems described disclose various methods according to embodiments, but additional methods are described with reference to flowcharts. Figure 16 is a flowchart of method 1670 of executing a fast access command by an NVM device according to one embodiment.

[0111] Method 1670 may include receiving a command (1670-0). This type of action may include receiving a command from the command address (CA) input of an NVM device. Method 1670 may determine whether the received command is an NVR command (1670-2). This type of action may include determining whether a particular bit position in the command identifies the command as an NVR command. If the command is not an NVR command (N in 1670-2), Method 1670 may process the command as a set of a given size (1670-14). This type of action may include processing the command as if they were a set of four commands, rather than a variable-size NVR sequence.

[0112] If it is determined that the received command is an NVR command (Y in 1760-2), method 1670 can determine whether the next command has been received (1670-6). This type of action may include receiving the command with virtually no delay to a previously received command. If no next command has been received (N in 1670-6), the NVR sequence can be terminated (1670-12). In this way, an NVR command sequence of one or more NVR commands can be determined.

[0113] If the following command is received (Y in 1670-6), method 1670 can determine if the next command is an NVR command (1670-8). If the next command is an NVR command (Y in 1670-8), method 1670 can return to 1670-4 and add the next NVR command to the NVR sequence. If the next command is not an NVR command (N in 1670-8), the NVR sequence can be terminated (1670-10), and the commands that are not NVR commands can be processed as a given set (1670-14).

[0114] When the NVR command sequence is completed (1670-10 or 1670-12), method 1670 can access the memory device location by the address data of the NVR sequence (1670-16).

[0115] Figure 17 is a flowchart of another method 1770 according to one embodiment. Method 1770 is performed by a memory controller or the like and can access data stored in an NVM device. Method 1770 may include requesting parameter values ​​from the NVM device (1770-0). This type of action may include reading parameter values ​​from a storage location (e.g., parameter registers) in the NVM device. In some embodiments, this type of request may occur through the DDR I / F of the NVM device. However, in other embodiments, this type of request may occur through the serial I / F of the NVM device.

[0116] Method 1770 can determine whether the received parameter data indicates that the NVM device is capable of performing high-speed access operations (1770-2). This type of action may include determining that one or more bits of a configuration value read from the NVM device have a predetermined value.

[0117] If the parameter value indicates that the NVM device can perform high-speed access (Y in 1770-2), method 1770 can configure the NVR sequence size according to the size of the NVM device to be accessed (1770-4). For example, for some NVM devices, two NVR commands may have enough address bits to access all address locations. However, for larger devices, additional NVR commands may be included to provide more address bits. Method 1770 may further include receiving requests to access the NVM device (1770-6). Such requests can be received by the memory controller from a CPU subsystem (e.g., a host). In response to a request, method 1770 may output an NVR sequence of the configured size (1770-8). This type of action may include outputting a sequence of NVR commands on the CA portion of a DDR bus, e.g., an LPDDR4-compatible bus. Method 1770 may also include receiving data corresponding to the NVR sequence in a DDR burst of read data values ​​(1770-10). This type of action may include receiving data with ECC data. Furthermore, in some embodiments, the data received in bursts of 8 may match the size of the cache line for the system or a fraction of an integer of the cache line size (e.g., 1 / 2, 1 / 4). In some embodiments, the DDR burst of read data values ​​may be 8 or less. However, other embodiments may include larger bursts.

[0118] If the parameter value indicates that the NVM device cannot perform fast access (N in 1770-2), method 1770 may include receiving a request to access the NVM device (1770-12). However, in response to such a request, method 1770 may output a read sequence of four or more commands (1770-14). Furthermore, the data may be received in DDR bursts of data values ​​(1770-16). In some embodiments, such data values ​​may be bursts greater than 8, e.g., bursts of 16 or 32.

[0119] Figure 18 is a flowchart of another method 1870 according to another embodiment. Method 1870 is executable by the system to fill cache lines of cache memory with data read directly from one or more NVM devices. Method 1870 may include a host device or memory controller 1830 receiving a cache fill request for a cache having cache lines having a size of X bytes (1870-2). This type of action may include the host device issuing a read request to the memory controller. The value X is understood to be a number greater than 1. In some embodiments, X may be an even number greater than 4. Method 1870 may include issuing an NVR command sequence for each cache line of the cache fill request (1870-4). This type of action may include issuing this type of command sequence on a data bus and a separate command address bus. In some embodiments, this type of command address bus may have a width of 6 bits or less.

[0120] Method 1870 may include outputting X bytes of data in a DDR burst for each NVR sequence (1870-6). This type of action may include outputting data from more than one NVM device on the DDR bus. In some embodiments, this type of action may include outputting data from two different NVM devices in response to the same command address value. In some embodiments, this type of DDR burst may have a burst length of 8. However, in other embodiments, the DDR burst may be of a larger size, for example, 16 or 32.

[0121] Method 1870 can fill a cache line with X bytes of data received from one or more NVM devices (1870-8). This type of action may include filling a cache line without discarding any read data received from the NVM device.

[0122] According to the embodiment, the NVM device can provide high-speed access for higher temperature systems. This type of NVM device can eliminate the need for volatile memory, such as SRAM or DRAM. This can enable a more compact system and / or reduced system costs.

[0123] According to the embodiment, the NVM device can provide more efficient use of the CA bus for smaller data transfers by enabling high-speed access requests through four clock cycles, in contrast to eight clock cycles. Furthermore, smaller data transfers can enable more efficient cache filling. As one of many possible examples, as shown in Figures 5 and 19, in an x32 configuration, the NVM device can have a cache line fill latency of 28.75 ns (at an 800 MHz clock), in contrast to a DRAM device latency of 38.75 ns. Furthermore, DRAM access can ultimately result in data discarding. This kind of capability can enable fresh cache line filling every 5 ns (at an 800 MHz clock), in contrast to every 10 ns (with data discarding).

[0124] Throughout this specification, any reference to “one embodiment” or “embodiment” should be understood to mean that a particular feature, structure, or characteristic described in relation to that embodiment is included in at least one embodiment of the present invention. Therefore, it should be emphasized and acknowledged that two or more references to “embodiment” or “one embodiment” or “alternative embodiment” in different parts of this specification do not necessarily all refer to the same embodiment. Furthermore, certain features, structures, or characteristics may be appropriately combined in one or more embodiments of the present invention.

[0125] Similarly, in the exemplary embodiments of the invention described above, it should be understood that various features of the invention are sometimes grouped together in a single embodiment, drawing, or description in order to streamline the disclosure and help understand one or more of the various embodiments of the invention. However, this method of disclosure should not be interpreted as indicating an intention that the claims require more features than those explicitly detailed in each claim. Rather, the embodiments of the invention are fewer than all the features of a single embodiment of the disclosure described above. Therefore, the claims following the detailed description are explicitly incorporated into this detailed description, and each claim stands on its own as a separate embodiment of the invention.

Claims

1. A step of receiving a series of commands on a unidirectional command address (CA) bus input of a discrete non-volatile memory (NVM) device, wherein the commands are synchronized with a timing clock. For each received command, the step of determining whether the command is a fast read (NVR) command, If it is determined that a command is an NVR command, the step of determining whether the next sequence of commands is an NVR command is a step of determining whether the sequence of NVR commands forms an NVR command sequence. The steps include: accessing read data stored in the NVM cell of the NVM device in response only to the aforementioned NVR command sequence; A step of driving the read data on the parallel data input / output (I / O) of the NVM device in a burst of data values, wherein the data values ​​of the burst are output in synchronization with the rising and falling edges of the timing clock. Includes, The CA bus input includes a plurality of parallel CA signal inputs. method.

2. The NVR command on the CA bus input and the data value on the parallel data I / O are generated by signal transmission compatible with the LPDDR4 standard. The method according to claim 1.

3. The aforementioned NVR command includes bit value positions corresponding to bit value positions of commands compatible with the LPDDR4 standard, At least one NVR command is LPDDR4 compatible and includes address data at the bit position containing command data. The method according to claim 1.

4. The method further includes the step of receiving each NVR command through an integer multiple of two cycles of the timing clock, wherein the integer is 1 or greater. The method according to claim 1.

5. The NVR command sequence includes all command values ​​and address values ​​necessary to access the read data. The method according to claim 1.

6. Each NVR command has a format compatible with LPDDR4 standard commands, including the command bit position that identifies the command. The step of determining whether the command is an NVR command includes the step of determining whether the command bit position of the NVR command matches a predetermined value. The method according to claim 1.

7. The aforementioned method, The step of receiving serial commands and serial address values ​​on the serial port of the NVM device, wherein the serial port is a step different from the CA bus input and parallel data I / O, Steps include accessing the NVM cell of the NVM device in response to the serial command and serial address value, Further including, The method according to claim 1.

8. The burst of the data value has a burst length (BL) that can be configured as one of a plurality of burst length (BL) values, and at least one BL value is 8 or less. The method according to claim 1.

9. A unidirectional command address (CA) bus, A bidirectional data bus, A host system equipped with a memory controller, The memory system and, A system equipped with, The memory controller is configured to issue a sequence of continuous high-speed memory read (NVR) commands on the CA bus, each NVR command being issued in synchronization with a timing clock and including a bit value that distinguishes the NVR command from other commands. The memory controller is configured to receive read data corresponding to the sequence of NVR commands on the data bus. The memory system includes at least one NVM cell array, a command decoder circuit, and an access circuit. The command decoder circuit described above is For each received command, it is determined whether the command is a fast read (NVR) command. If a command is determined to be an NVR command, then it is determined whether the next consecutive command is an NVR command. It is configured in such a way, A series of NVR commands forms an NVR command sequence. The access circuit responds only to the NVR command sequence, Access the at least one NVM cell array and access the read data stored in the NVM cell array. In a burst of data values, the read data is output on the data bus. The data value of the burst is configured to be output in synchronization with the rising and falling edges of the timing clock. system.

10. The memory controller includes a controller interface (I / F) connected to the CA bus and the data bus, The memory system includes a memory device interface connected to the CA bus and the data bus. The controller interface and memory device interface are compatible with the LPDDR4 physical interface standard. The system according to claim 9.

11. The aforementioned NVR command includes bit value positions corresponding to bit value positions of commands compatible with the LPDDR4 standard, At least one NVR command is LPDDR4 compatible and includes address data at the bit position containing command data. The system according to claim 9.

12. The host system includes at least one cache memory having a cache line of a predetermined size, The size of the read data output by the NVM system in the aforementioned burst of data values ​​matches the predetermined size. The system according to claim 9.

13. The memory controller issues each NVR command through an integer multiple of two cycles of the timing clock, and the integer is 1 or greater. The system according to claim 9.

14. The host system is configured to request parameter data from the NVM system. In response to the parameter data having a predetermined value, a read request to the NVM system is encoded into an NVR command sequence. The system according to claim 9.

15. The memory system further includes at least one volatile memory cell array and a volatile memory access circuit. The volatile memory access circuit responds only to NVR command sequences. Accessing the at least one volatile memory cell array, and accessing the volatile read data stored in the volatile memory cell array, A volatile memory burst of volatile data values ​​outputs the volatile read data on the data bus. The volatile data values ​​of the volatile memory burst are output in synchronization with the rising and falling edges of the timing clock. The system according to claim 9.

16. The burst of the data value has a burst length (BL) that can be configured as one of a plurality of burst length (BL) values, and at least one BL value is 8 or less. The system according to claim 9.

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