Drive control device, drive control method, information processing system, and information processing method for information processing system

Abstract

The present disclosure pertains to a drive control device, a drive control method, an information processing system, and an information processing method for the information processing system that enable suppression of generation of an abnormal sound in an LED display device of a passive matrix drive scheme. In the present disclosure, a blanking period between frames is set shorter than a time period set according to a display standard so that the blinking period ends before ripple voltage rises. Accordingly, by suppressing the rise of the ripple voltage caused by dropping of current flowing through an LED during the blanking period, voltage application to an MLCC is suppressed, and by suppressing distortion of a substrate resulting from expansion / shrinkage of the MLCC caused in association with the voltage application, generation of an abnormal sound is suppressed. This disclosure can be applied to an LED display device of the passive matrix drive scheme.

Description

Drive control device, drive control method, information processing system, and information processing method for information processing system

[0001] The present disclosure relates to a drive control device, a drive control method, an information processing system, and an information processing method for an information processing system, and more particularly to a drive control device, a drive control method, an information processing system, and an information processing method for an information processing system that are capable of suppressing abnormal noise generated in a direct-view LED (Light Emitting Diode) display at low cost.

[0002] In recent years, the market for direct-view displays using LEDs (Light Emitting Diodes) has been expanding.

[0003] Of these, the tiling type uses a board equipped with LEDs (LED module board: hereafter also referred to as module board), but this module board and its built-in power supply system can sometimes make strange noises such as buzzing or beeping.

[0004] This phenomenon is mainly caused by the vibration of MLCCs (Multilayer Ceramic Capacitors) installed as bypass capacitors on power lines, or by the vibration of coils used in power supply systems at a specific frequency.

[0005] Conventionally, the noise generated by MLCCs (the generation of abnormal noise) has been addressed by using low-distortion MLCCs (low-noise products) or by replacing them with solid capacitors such as tantalum capacitors.

[0006] Coils are generally subjected to vibration suppression using impregnation treatments and other methods.

[0007] Furthermore, a technique has been proposed in which multiple bypass capacitors are provided to generate vibrations of opposite phases, thereby suppressing the generation of vibration noise (see Patent Document 1).

[0008] Japanese Patent Application Laid-Open No. 2000-056727

[0009] However, in the technology described in Patent Document 1, the mechanism for generating the vibrations of opposite phases is actually very complicated in configuration.

[0010] Even if a mechanism for generating reverse-phase vibrations could be constructed, the device configuration would be doubled. In particular, components such as bypass capacitors are used in large numbers, and even if the individual unit prices are low, the overall cost of the set would increase significantly.

[0011] Furthermore, since tantalum capacitors fail in a short circuit mode, the use of a large number of them may result in a decrease in product quality.

[0012] The present disclosure has been made in view of the above circumstances, and particularly aims to make it possible to suppress abnormal noise generated in direct-view LED (Light Emitting Diode) displays at low cost.

[0013] A drive control device according to a first aspect of the present disclosure includes a light emission control unit that controls the emission of LEDs that constitute an LED (Light Emitting Diode) array, and the light emission control unit controls the length of the period during which the LEDs are turned off so that it is shorter than the time indicated by an input signal.

[0014] A drive control method according to a first aspect of the present disclosure includes a light emission control step of controlling the light emission of LEDs constituting an LED (Light Emitting Diode) array, and the processing of the light emission control step is a drive control method that controls the length of a period during which the LEDs are turned off to be shorter than a time indicated by an input signal.

[0015] In a first aspect of the present disclosure, light emission of LEDs constituting an LED (Light Emitting Diode) array is controlled, and the length of the period during which the LEDs are turned off is controlled to be shorter than the time indicated by an input signal.

[0016] An information processing system according to a second aspect of the present disclosure includes a display section consisting of a display unit having LEDs (Light Emitting Diodes) arranged in an array and a drive control device that controls the driving of the LEDs, and a distribution section that receives input of a video signal, performs predetermined signal processing on the video signal, and distributes it to the display unit, wherein the drive control device includes an emission control section that controls the emission of the LEDs, and the emission control section controls the length of the period during which the LEDs are off to be shorter than the time indicated by the input signal.

[0017] An information processing method for an information processing system according to a second aspect of the present disclosure is an information processing method for an information processing system that includes a display section consisting of a display unit having LEDs (Light Emitting Diodes) arranged in an array and a drive control device that controls the drive of the LEDs, and a distribution section that receives input of a video signal, performs predetermined signal processing on the video signal, and distributes it to the display unit, wherein the drive control device includes an emission control step that controls the emission of the LEDs, and the processing of the emission control step controls the length of the period during which the LEDs are turned off to be shorter than the time indicated by the input signal.

[0018] In a second aspect of the present disclosure, there is provided a display section consisting of a display unit having LEDs (Light Emitting Diodes) arranged in an array and a drive control device that controls the driving of the LEDs, and a distribution section that receives input of a video signal, performs predetermined signal processing on the video signal, and distributes it to the display unit, and the drive control device controls the light emission of the LEDs so that the length of the period during which the LEDs are off is shorter than the time indicated by the input signal.

[0019] FIG. 1 is a diagram illustrating an example configuration of a display system according to the present disclosure. FIG. 2 is a diagram illustrating an example configuration of the video wall controller and display unit of FIG. 1. FIG. 3 is a diagram illustrating an example configuration of an LED array. FIG. 4 is a diagram illustrating the principle of generating abnormal sound. FIG. 5 is a diagram illustrating the principle of generating abnormal sound. FIG. 6 is a simplified circuit diagram illustrating the circuit configuration of a substrate. FIG. 7 is a diagram illustrating distortion of an MLCC. FIG. 8 is a timing chart illustrating a conventional blanking period. FIG. 9 is a timing chart illustrating a blanking period according to the present disclosure. FIG. 10 is a timing chart illustrating light emission timing for each row in an LED array. FIG. 11 is a timing chart illustrating light emission timing for each row in an LED array. FIG. 12 is a diagram illustrating a method for setting a blanking period. FIG. 13 is a diagram illustrating the effect of setting a short blanking period. FIG. 14 is a flowchart illustrating display processing. FIG. 15 is a flowchart illustrating driver control processing.

[0020] Preferred embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. In this specification and drawings, components having substantially the same functional configurations are designated by the same reference numerals, and redundant description will be omitted.

[0021] Hereinafter, embodiments of the present technology will be described in the following order: 1. Example of a display system configuration 2. Detailed configuration of a video wall controller and a display unit 3. Example of an LED array configuration 4. Ripple voltage 5. Principle of abnormal noise generation 6. Blanking period 7. Setting the length of the blanking period 8. Display processing 9. Driver control processing by the display unit

[0022] <<1. Configuration Example of Display System>> The present disclosure is directed to making it possible to suppress, at low cost, abnormal noise generated in, in particular, a direct-view LED (Light Emitting Diode) display.

[0023] FIG. 1 shows an example of the configuration of a display system to which the technology of the present disclosure is applied.

[0024] The display system 11 in FIG. 1 displays video content on a large display configured by arranging a plurality of display units in a tiled pattern.

[0025] More specifically, the display system 11 is made up of a PC (personal computer) 30 , a video server 31 , a video wall controller 32 , and a video wall 33 .

[0026] The PC (personal computer) 30 is a general-purpose computer that accepts operation inputs from a user and supplies commands corresponding to the operation content to the video wall controller 32 .

[0027] The video server 31 is, for example, a server computer, and supplies video signal data such as video content to the video wall controller 32 .

[0028] The video wall controller 32 operates in response to commands supplied from the PC 30, and distributes data consisting of video content image signals to the display units 51-1 to 51-n that make up the video wall 33 for display.

[0029] When there is no need to distinguish between the display units 51-1 to 51-n, they will be simply referred to as display units 51.

[0030] As shown in the upper right corner of Figure 1, the video wall 33 is made up of display units 51-1 to 51-n, each of which has an array of LED pixels, arranged in a tiled pattern.The images displayed by each display unit 51 are combined in a tiled pattern to display a single image across the entire video wall 33.

[0031] The video wall controller 32 performs predetermined signal processing on the data consisting of the video signal of the video content supplied from the video server 31, distributes and supplies the data according to the arrangement of the display units 51-1 to 51-n, controls the individual displays of the display units 51-1 to 51-n, and controls the video wall 33 as a whole to display a single image.

[0032] The video wall controller 32 and the video wall 33 may be integrated into one unit, or may be integrated into one display device (information processing system).

[0033] <<2. Detailed Configuration of Video Wall Controller and Display Unit>> Next, with reference to FIG. 2, a detailed configuration example of the video wall controller 32 and the display unit 51 will be described.

[0034] The video wall controller 32 includes a LAN (Local Area Network) terminal 71, an HDMI (High Definition Multimedia Interface) (registered trademark) terminal 72, a DP (Display Port) terminal 73, a DVI (Digital Visual Interface) terminal 74, a network IF (Interface) 75, an MPU (Micro Processor Unit) 76, a signal input IF 77, a signal processing unit 78, a DRAM (Dynamic Random Access Memory) 79, a signal distribution unit 80, and output IFs 81-1 to 81-n.

[0035] The LAN (Local Area Network) terminal 71 is, for example, a connection terminal for a LAN cable or the like, and is operated by a user to realize communication via LAN with a personal computer (PC) 30, supplying control commands and the like according to the operation content to the video wall controller 32, and supplies the input control commands and the like to the MPU 76 via the network IF 75.

[0036] The LAN terminal 71 may be configured to be physically connected by a wired LAN cable, or may be configured to be connected by a so-called wireless LAN, which is realized by wireless communication.

[0037] The MPU 76 receives control commands from the PC 30 via the LAN terminal 71 and the network IF 75 , and supplies a control signal corresponding to the received control command to the signal processing unit 78 .

[0038] The HDMI terminal 72, DP terminal 73, and DVI terminal 74 are all input terminals for data consisting of video signals, and are connected to, for example, a server computer that functions as a video server 31, and supply data consisting of video signals to a signal processing unit 78 via a signal input IF 77.

[0039] In addition, in Figure 2, an example is shown in which the video server 31 is connected to the HDMI terminal 72, but the HDMI terminal 72, DP terminal 73, and DVI terminal 74 all have different standards and basically have the same functions, so any one of them can be selected and connected as needed.

[0040] Based on the control signal supplied from the MPU 76, the signal processing unit 78 adjusts the color temperature, contrast, brightness, etc. of the data made up of the video signal supplied via the signal input IF 77, and supplies the adjusted data to the signal distribution unit 80. At this time, the signal processing unit 78 uses the connected DRAM 79 to expand the data made up of the video signal, as necessary, executes signal processing based on the control signal, and supplies the signal processing result to the signal distribution unit 80.

[0041] The signal distribution unit 80 distributes the data consisting of the signal-processed video signal supplied from the signal processing unit 78, and distributes and transmits the data individually to the display units 51-1 to 51-n via the output IFs 81-1 to 81-n.

[0042] The display unit 51 includes a driver control unit 91 and an LED block 92 .

[0043] The driver control unit 91 supplies data consisting of video signals that control the light emission of the LEDs that make up the LED arrays 122-1 to 122-N to the plurality of LED drivers 121-1 to 121-N that make up the LED block 92.

[0044] More specifically, the driver control unit 91 includes a signal input IF 111, a signal processing unit 112, a DRAM 113, and output IFs 114-1 through 114-N.

[0045] The signal input IF 111 receives input of video signal data supplied from the video wall controller 32 and supplies it to the signal processing unit 112 .

[0046] The signal processing unit 112 corrects the color and brightness of each display unit 51 based on the video signal data supplied from the signal input IF 111, generates data for setting the light emission intensity of each LED that makes up the LED arrays 122-1 to 122-N, and distributes and supplies this data to the LED drivers 121-1 to 121-N of the LED block 92 via the output IFs 114-1 to 114-N.

[0047] More specifically, the video signal data also includes information such as the length of a blanking period defined by a general standard. Therefore, the signal processing unit 112 takes into consideration information such as the length of a blanking period included in the video data signal to generate data for setting the number of LED rows (number of scan lines), the number of times light is repeatedly emitted in one frame (number of cycles), and the light emission intensity of each LED constituting the LED arrays 122-1 to 122-N, and distributes and supplies this data to the LED drivers 121-1 to 121-N of the LED block 92 via the output IFs 114-1 to 114-N.

[0048] The LED block 92 includes LED drivers 121 - 1 to 121 -N, LED arrays 122 - 1 to 122 -N, and a ROM (Read Only Memory) 123 .

[0049] The LED drivers 121-1 to 121-N use PWM (Pulse Width Modulation) to control the light emission of the LEDs arranged in an array that make up the corresponding LED arrays 122-1 to 122-N based on data that sets the light emission intensity of the LEDs 141, which data is composed of a video signal supplied from the driver control unit 91.

[0050] ROM 123 stores board mounting information including the type (capacity) and number of capacitors such as MLCCs mounted on board 153 ( FIG. 4 ) that constitutes LED block 92, and when power is applied, signal processing unit 112 sets the processing of the video signal by reading the board mounting information from ROM 123. More specifically, signal processing unit 112 sets the length of the blanking period to be shorter than the blanking period specified by general standards based on the board mounting information read from ROM 123 when power is applied. The setting of the blanking period will be described in detail later.

[0051] <<3. Configuration Example of LED Array>> Next, a configuration example of the LED array 122 will be described with reference to Fig. 3. Fig. 3 shows a configuration example of the LED array 122 in a passive matrix drive type LED drive wiring. Therefore, the light emission of the LEDs 141 of the LED array 122 is controlled by a passive matrix drive method.

[0052] In the LED array 122 of FIG. 3, common cathode type LEDs 141 are arranged in an array, and each LED 141 is connected to a Sig line (brightness control wiring) wired vertically and a Scan line (row selection wiring) wired horizontally.

[0053] 3, when Scan line 1 is set to a predetermined fixed potential and turned ON, current is supplied to the LED from the Sign line, causing the LED to emit light. Note that the predetermined fixed potential is generally GND = 0 V potential, but this is not limited to this.

[0054] 4 to 7, the ripple voltage that causes abnormal noise will be described. First, the power supply configuration for supplying power to the display units 51-1 to 51-n will be described.

[0055] FIG. 4 shows an outline of the power supply configuration for supplying power to the display units 51-1 to 51-n.

[0056] The power supply configuration in FIG. 4 is composed of an AC power supply device 151 that receives AC (Alternating Current) power input and supplies power to a subsequent stage, a board / wiring (board with wiring formed thereon) 152 on which the various circuits and wiring that make up the video wall controller 32 are arranged, and boards / wiring (boards with wiring formed thereon) 153-1 to 153-n on which the various circuits and wiring that make up each of the display units 51-1 to 51-n that make up the video wall 33 are arranged.

[0057] In addition, the AC power supply device 151 and the board 152 are electrically connected via wiring 161, and the board 152 and each of the boards 153-1 to 153-n are electrically connected via wiring 162-1 to 162-n.

[0058] As shown in FIG. 5, the AC power supply device 151, the circuit boards 152 and 153, and the wiring 161, 162-1 through 162-n have internal impedances Z151, Z152 and Z153, and impedances Z161 and Z162, respectively.

[0059] For this reason, as shown in FIG. 6 , assuming that AC power supply device 151 receives an AC power input of voltage V0 when there is no load, the output voltage of AC power supply device 151 will drop by a voltage ΔV151 (=Z151×I1 (written as Z151×I1 in the drawing, and this also applies hereinafter)) corresponding to impedance Z151, where I1 is the internal current relative to voltage V0.

[0060] Similarly, in the wiring 161, if the internal current is the current I2, a voltage drop occurs by a voltage Δ161 (=Z161×I1) corresponding to the impedance Z161.

[0061] Similarly, in the substrate 152, if the internal current is a current I3, a voltage drop occurs by a voltage Δ152 (=Z152×I3) corresponding to the impedance Z152.

[0062] Similarly, in the wiring 162, if the internal current is a current I4, a voltage drop occurs by a voltage Δ162 (=Z162×I4) corresponding to the impedance Z162.

[0063] Similarly, in the substrate 153, if the internal current is a current I5, a voltage drop occurs by a voltage Δ153 (=Z153×I5) corresponding to the impedance Z153.

[0064] As a result, a voltage drop occurs of ΔV (= ΔV151 + ΔV161 + ΔV152 + ΔV162 + ΔV153) across all voltages of AC power supply 151, substrates 152, 153, and wiring 161, 162, which is the difference between the power supply voltage V0 supplied from AC power supply 151 and the voltage Vx applied to substrate 153.

[0065] Furthermore, if the circuit configuration formed on the substrate 153 is expressed in a simple circuit diagram, as shown in Figure 7, the LED driver 121 and capacitance C such as an MLCC provided on the substrate 153 can be considered to be a circuit connected in parallel.

[0066] Therefore, when the LED 141 is emitting light, a current flows through the LED driver 121 and the MLCC, i.e., a load is applied, and a voltage Vx that has a voltage drop of ΔV from the power supply voltage V1 is applied to the LED driver 121.

[0067] On the other hand, when the LED 141 is turned off, the current of the LED driver 121 and the MLCC is reduced, resulting in an unloaded state, so that no voltage drop corresponding to the voltage ΔV occurs, and the voltage V1 is applied to the LED driver 121.

[0068] That is, depending on whether or not a voltage drop of voltage ΔV occurs according to the light emission state of the LED 141, the voltage applied to the LED driver 121 and the MLCC changes between voltage V0 and Vx. When the load state voltage Vx temporarily changes to an unloaded state, the voltage changes to voltage V0, and the voltage drop ΔV that appears to be a square wave is the ripple voltage ΔV. This ripple voltage ΔV is the cause of the generation of abnormal noise. The principle of the generation of abnormal noise due to the ripple voltage ΔV will be described later.

[0069] <<5. Principle of Abnormal Noise Generation>> Next, before explaining the principle of abnormal noise generation caused by the ripple voltage ΔV, we will explain voltage distortion caused by the MLCCs mounted on the substrate 153. Note that, while the explanation will be given here using the substrate 153 as an example, the same applies to the substrate 152.

[0070] FIG. 8 is a side cross-sectional view illustrating distortion that occurs when a voltage is applied to an MLCC 171 connected to a substrate 153 by a connecting portion 172 made of solder, adhesive, or the like.

[0071] MLCC 171 is configured with ceramic ferroelectric materials stacked in the vertical direction in the figure, and when voltage is applied, it expands as indicated by the black arrow D2 in a direction parallel to the direction of electric field application (the vertical direction in the figure) shown by arrow D1 in the figure, and also contracts in a direction perpendicular to arrow D1, the direction of electric field application in the figure, as indicated by the black arrow D2 in the horizontal direction in the figure.

[0072] Accordingly, as indicated by dotted arrow D3, substrate 153 is drawn to the side of MLCC 171 via connection portion 172 that fixes MLCC 171 on substrate 153.

[0073] As a result, as shown by arrow D4, substrate 153 is distorted (bent) into a shape that is convex downward in the drawing, centered on the portion bonded to MLCC 171.

[0074] That is, as shown in Figure 8, when a ripple voltage ΔV occurs, a voltage is applied to the MLCC 171, causing the substrate 153 to bend (distort) as shown in Figure 8, and when the ripple voltage ΔV is eliminated, the voltage applied to the MLCC 171 is no longer applied, the substrate 153 returns to a flat state, and the distortion is eliminated.

[0075] In this way, the substrate 153 changes between being distorted and being flat depending on whether or not the ripple voltage ΔV is generated, and thus abnormal noise is generated from the substrate 153.

[0076] <<6. Blanking Period>> On the other hand, the standards for displaying images on display devices are also compatible with standards established during the era of conventional cathode ray tube display devices, and therefore stipulate that the display image should be displayed at a predetermined frequency in frame units.

[0077] According to this provision, a blanking period is set between frames, i.e., from the time when the last line of the previous frame is displayed until the first line of the next frame is displayed, during which no image is displayed.

[0078] That is, as shown by the waveform of the LED light emission timing in the upper row of Figure 9, the LED driver 121 causes a current to flow to cause the LED 141 to emit light during times t0 to t1, t2 to t3, t4 to t5, etc., which are the light emission periods of the LED 141 during which an image is displayed in frame units.

[0079] On the other hand, during blanking periods Tblks between frames, such as times t1 to t2, t3 to t4, and t5 to t6, the LED 141 is turned off, and the flow of current to emit light is essentially zero.

[0080] Therefore, the voltage applied to the MLCC 171 changes depending on whether or not there is a current for illuminating the LED 141, as shown by the power supply voltage waveform in the lower part of Figure 9, and therefore a ripple voltage ΔV as shown by a rectangular wave is generated during the blanking period Tblks.

[0081] As a result, during the blanking period Tblks, the applied voltage of MLCC 171 changes at intervals when ripple voltage ΔV occurs, and accordingly, distortion occurs in substrate 153, which in turn causes abnormal noise.

[0082] Therefore, in the present disclosure, as shown in FIG. 10, by setting the blanking period Tblks to a shorter blanking period Tblkm (<Tblks), the generated ripple voltage is reduced to a voltage ΔV' (<ΔV), thereby reducing the applied voltage to MLCC 171, suppressing distortion of substrate 153 and suppressing the generation of abnormal noise caused thereby.

[0083] The blanking period will now be described in more detail with reference to Figures 11 and 12. In Figure 11, the left portion shows a configuration diagram of the LED driver 121 and LED array 122 described with reference to Figure 3, and the right portion shows the light emission timing of the LEDs constituting the LED array 122 in row units (scan line units).

[0084] That is, as indicated by the downward arrow on the right side of FIG. 11, the LED driver 121 repeats the process of sequentially emitting light from top to bottom row by row, i.e., from scan line 1 to scan line N, for each frame.

[0085] The squares on the right side of FIG. 11 that are penetrated by downward arrows indicate the light emission timing of each row in frames F1, F2, . . . , and show that the LEDs emit light in a time series on a row-by-row basis.

[0086] For example, when the light emission timing for Scan line N in frame F1 ends, the position of the row that emits light changes, as indicated by the diagonally upward arrow, from Scan line N, the bottom row, to Scan line 1, the top row of the next frame F2. At this timing, a blanking period Tblk is set.

[0087] At this time, the waveforms of the currents flowing through the LED driver 121 and the MLCC 171 in each frame are expressed by the waveforms shown in the top and middle rows of Fig. 12. Note that the top row of Fig. 12 shows a current waveform for explaining the conventional blanking period Tblks, and the middle row of Fig. 12 shows a current waveform for explaining the blanking period Tblkm of the present disclosure.

[0088] Here, in each of frames F1, F2, ..., as shown in the bottom row of Figure 12, the fine rectangular waveforms represent the light emission time for each scan line, the periods between each rectangular waveform represent the switching time between scan lines, and the timing between frames F1 and F2 where no waveform is present represents blanking periods Tblks, Tblkm, respectively.

[0089] That is, in the bottom row of FIG. 12, the periods from time t101 to t102, t103 to t104, and t105 to t106 are the light emission times for each row, and the periods from time t102 to t103 and t104 to t105 are the switching times for each row.

[0090] As described above, the ripple voltage ΔV occurs during this blanking period Tblks because the current is substantially zero.

[0091] Therefore, in the present disclosure, as shown in the middle part of Figure 12, the blanking period Tblks is shortened to a blanking period Tblkm (<Tblks), so that light emission of the next frame begins before the ripple voltage rises significantly, thereby reducing the generated ripple voltage ΔV and suppressing the generation of abnormal noise.

[0092] <<7. Setting the Length of the Blanking Period>> Next, setting the length of the blanking period to reduce the ripple voltage ΔV will be described.

[0093] As shown in the top row of Figure 13, the conventional blanking period Tblks consists of a rise period T1 in which the ripple voltage rises exponentially to voltage Vr, a steady period indicated by the dotted line in which the voltage remains steady at Vr, and a fall period T2 in which the voltage drops linearly, and as a whole was set to be approximately 5 to 8% of the light emission period of one frame.

[0094] In order to reduce the ripple voltage, it is necessary to shorten the blanking period Tblks, but even if the steady period is eliminated and the blanking period is set to Tblks', for example, as shown in the middle part of Figure 13, the magnitude of the ripple voltage Vr does not change and the occurrence of abnormal noise cannot be suppressed. However, when the steady period is shortened, as in the case of the blanking period Tblks', the frequency of the abnormal noise that is generated changes, and so the sound range changes.

[0095] To reduce the ripple voltage Vr to a smaller ripple voltage Vr', for example, as shown by the rising period T1' in the lower part of Figure 13, it is necessary to set the falling period T2' so that it starts before the ripple voltage Vr rises to Vr, i.e., to set the blanking period Tblkm short so that the emission of the next frame starts quickly.

[0096] Here, the change in the rising period and the change in the falling period of the ripple voltage will be considered.

[0097] The rising voltage Vru of the ripple voltage during the rising period can be expressed by, for example, the following equation (1).

[0098] Vru=Vr(1-e(-T1' / τ))...(1)

[0099] Here, Vru is the ripple voltage in the rising period T1 shown in the upper part of FIG. 13, Vr is the maximum value of the ripple voltage in the steady state, and T1' is the length of the rising period.

[0100] Furthermore, τ is a constant (=R·C) consisting of a DC resistance component R, which is the main component of the impedance Z of the MLCC 171, and a capacitance C.

[0101] Furthermore, the ripple voltage Vrd during the drop period can be expressed by, for example, the following equation (2).

[0102] Vrd=I・T2' / C...(2)

[0103] where I is the current value flowing through the LED, T2' is the length of the fall period, and C is the capacitance of the MLCC 171.

[0104] When the maximum value of the ripple voltage is reduced by 1 / n from the conventional voltage Vr to Vr / n, the rise period T1' and fall period T2' can be calculated as shown in the following equations (3) and (4), respectively.

[0105] Vru=Vr / n=Vr(1-e(-T1' / τ)) 1 / n=1-e(-T1' / τ) T1'=-τ・ln(1-1 / n) ...(3)

[0106] Vrd=Vr / n=I・T2' / C T2'=Vr・C / (n・I)...(4)

[0107] Therefore, the blanking period Tblkm when the voltage Vr / n is reduced to 1 / n of the voltage Vr that is the maximum value of the conventional ripple voltage can be set as shown in the following equation (5).

[0108] Tblkm=T1'+T2' =-τ·ln(1-1 / n)+Vr·C / (n·I) =-R·C·ln(1-1 / n)+Vr·C / (n·I) =C(-R·ln(1-1 / n)+Vr / (n·I)) ...(5)

[0109] As described above, the signal processing unit 112 of the driver control unit 91 in the display unit 51 reads the mounting board information from ROM 123 at startup, sets the blanking period Tblkm in this manner based on the read mounting board information, and controls a clock (not shown) used to PWM control the LEDs, thereby controlling the light emission timing of the LEDs, thereby realizing the blanking period Tblkm.

[0110] When setting the blanking period Tblkm, n is set as a parameter included in the above-mentioned equation (5) to specify the extent to which the ripple voltage is to be reduced.

[0111] Furthermore, by setting the blanking period to the shortest possible value, it is possible to set the capacitance C of MLCC 171 to the minimum possible value, thereby suppressing the occurrence of abnormal noise and reducing costs by reducing the capacitance of MLCC 171.

[0112] Furthermore, by increasing the capacitance C of the MLCC 171, it is possible to set the blanking period Tblkm longer while suppressing the generation of abnormal noise.

[0113] For example, if the impedance R of the MLCC 171 is 40 mΩ, the capacitance C is 2400 uF, the steady-state ripple voltage Vr is 200 mV, n is 3, and the current I is 4.7 A, when substituted into equation (5), the blanking period Tblkm becomes 73 uS.

[0114] In this case, when the frame rate is 60 Hz, the blanking period Tblkm is about 0.43% of the time per frame, and when the frame rate is 120 Hz, it is about 0.86%.

[0115] That is, by applying the above-mentioned formula (5) to the blanking period Tblkm, the occurrence of abnormal noise can be suppressed by setting it to be smaller than a predetermined value based on the impedance R and capacitance C of the MLCC 171 for the time per frame.

[0116] More specifically, the force F that generates distortion in the MLCC 171 (the force that vibrates the substrate 153) is generally expressed by the following equation (6).

[0117] F = d ΔV (N: Newton) (6)

[0118] Here, d is the piezoelectric strain constant that is a constant that each MLCC 171 has, and ΔV is the strength of the applied electric field, that is, the ripple voltage ΔV.

[0119] As described above, abnormal noise is generated when the force F that generates distortion in the MLCC 171 vibrates the substrate 153. In acoustic engineering, the radiation power W(w) of this generated abnormal noise satisfies the relationship expressed by the following equation (7) based on the area of ​​the substrate 153, the vibration speed of the substrate 153, the density of the substrate 153 that serves as a medium, and the propagation speed of the sound.

[0120] W∝S・(Δv average) 2ρc (w: watt) (7)

[0121] Here, S is the area of ​​the substrate 153, Δv average is the vibration velocity of the substrate 153, ρ is the density of the substrate 153 that serves as a medium, and c is the propagation velocity of sound.

[0122] Furthermore, since the average vibration velocity Δv of the substrate 153 is proportional to the force F that generates distortion in the MLCC 171 (the force that vibrates the substrate 153), the relationship of the following equation (8) is satisfied.

[0123] Δv average ∝F...(8)

[0124] In Newtonian mechanics, the force F that generates distortion in the MLCC 171 (the force that vibrates the substrate 153) is expressed as the product of mass and acceleration (F = m a (m: mass, a: acceleration)), so the greater the force F that generates distortion in the MLCC 171 (the force that vibrates the substrate 153), the greater the acceleration a. As a result, the following relationship (9) holds.

[0125] W∝S・(F average) 2 ・ρc=S・(d・ΔV average) 2 ρc (w: watt) (9)

[0126] In this way, the radiation power W(w) of the abnormal noise, which indicates the loudness of the noise, is proportional to the square of the ripple voltage ΔV.

[0127] From these facts, when n in the above-mentioned formula (5) is set to 3, the voltage Vr at which the ripple voltage ΔV reaches its maximum value becomes 1 / 3 (= 1 / n: n = 3), and as a result, the radiation power W (w) of the abnormal noise, which indicates the loudness of the sound, becomes 1 / 9 (= (1 / 3) ２ )

[0128] That is, by setting the blanking period so that n is set to 3 or more in equation (5), it is possible to reduce the radiation power W(w) of the abnormal sound, which indicates the loudness of the sound, to about 1 / 9≒1 / 10 or less, which makes it possible to give the human ear the impression that the sound has become quieter.

[0129] However, since there are control limits for the scanline switching times shown at times t102 to t103 and t104 to t105 in the bottom row of Figure 12, the blanking period Tblkm set by equation (5) cannot be set shorter than the control limits for the scanline switching times.

[0130] If the blanking period is of a length that conforms to the conventional standard, a ripple voltage will be generated during the blanking period as the current flowing through the LED decreases, as shown, for example, in the area surrounded by the dotted line on the left side of Figure 14.

[0131] In contrast, by setting a short blanking period using the method disclosed herein, the decrease in current flowing through the LED is suppressed, as shown by the waveform on the right side of Figure 14, and therefore the generation of ripple voltage is suppressed.

[0132] As a result, distortion of the substrate 153 due to expansion and contraction of the MLCC 171 is eliminated, and the generation of abnormal noise is suppressed.

[0133] 14 shows, from the top, the waveforms of the current, the power supply input voltage, the voltage applied to the LED driver 121, and the ground potential.

[0134] Furthermore, for example, when multiple display units 51 are mounted on the substrate 153, it is possible to completely synchronize the operations of the multiple display units 51. By having the multiple display units 51 operate in synchronization in this manner, it becomes possible to display high-definition images with movement with higher precision. Furthermore, since it becomes possible to display high-definition images with high precision, it becomes possible to realize high-precision re-imaging and the like.

[0135] On the other hand, if the operations of the multiple display units 51 are completely synchronized, the blanking period will be set according to conventional regulations, which will result in a larger ripple voltage ΔV and, accordingly, a larger abnormal noise.

[0136] However, even when the operations of multiple display units 51 are completely synchronized, as described above, it is possible to suppress the generation of ripple voltage ΔV by shortening the blanking period to suppress the generation of ripple voltage ΔV. Therefore, according to the technology disclosed herein, it is possible to suppress the generation of even larger abnormal noises that occur when high-definition images are displayed with high precision.

[0137] 11 shows that scan lines 1 to N are displayed once for each frame in chronological order, with frames F1, F2, ... being displayed sequentially, but in actual processing, the process of sequentially displaying scan lines 1 to N of the same frame is cyclically repeated multiple times. The video signal contains information specifying the number of cycles and N, which is the number of scan lines, as well as information on blanking periods defined by general standards. The signal processing unit 112 takes into account video information including this information and board mounting information for the board 153 stored in ROM 123, and sets a blanking period that is shorter than the blanking period defined by general standards.

[0138] In addition, in the above, we have described an example in which LEDs 141 are configured in horizontally arranged row units as ScanLines, and are illuminated sequentially from top to bottom row units (ScanLine units) to display an image on the entire LED display, but it is also possible to illuminate sequentially row units (ScanLine units) from bottom to top.

[0139] Alternatively, the LEDs 141 may be configured so that a vertically aligned column unit is set as a ScanLine, and the LEDs 141 are caused to emit light in a horizontally aligned column unit (ScanLine unit) sequentially from right to left or left to right to display an image. In other words, the LEDs 141 constituting a ScanLine unit may be configured in units of horizontally aligned rows or vertically aligned columns.

[0140] <<8. Display Processing>> Next, the display processing by the display system 11 of FIG. 1 will be described with reference to the flowchart of FIG.

[0141] In step S11, the signal processing unit 78 receives an input of a video signal consisting of content data or the like supplied from the video server 31 via one of the HDMI terminal 72, the DP terminal 73, and the DVI terminal 74 and the signal input IF 77.

[0142] In step S12, the signal processing unit 78 converts the video format of the received input video signal.

[0143] In step S13, the signal processing unit 78 receives the input of a control signal supplied from the MPU 76 in response to the operation of the PC 30, and executes signal processing such as color temperature, contrast, and brightness.

[0144] In step S14, the signal processing unit 78 allocates and distributes the processed video signals to the display units 51-1 to 51-n of the video wall 33.

[0145] In step S15, the signal processing unit 78 transmits and outputs the distributed video signals to the corresponding display units 51-1 to 51-n.

[0146] Through the above series of processes, the video signal read from the video server 31 is subjected to signal processing, and then distributed and transmitted to each of the display units 51-1 to 51-n that make up the video wall 33, so that individual images are displayed on the display units 51-1 to 51-n, thereby enabling the video wall 33 as a whole to display the video content images.

[0147] <<9. Driver Control Processing by Display Unit>> Next, driver control processing by the display unit 51 will be described with reference to the flowchart of FIG.

[0148] In step S31, the signal processing unit 112 in the driver control unit 91 of the display unit 51 receives the input of the video signals distributed and supplied from the video wall controller 32 via the signal input IF 111 on a row-by-row basis.

[0149] In step S32, the signal processing unit 112 determines whether or not it is a blanking period. That is, the signal processing unit 112 determines whether or not it is time to enter a blanking period based on whether or not the row-by-row video signal received via the signal input IF 111 is the video signal for the top row of a new frame.

[0150] If it is determined in step S32 that the blanking period is in progress, the process proceeds to step S33.

[0151] In step S33, the signal processing unit 112 suspends processing for the time set as the length of the blanking period. However, the length of the blanking period set here is a length that can suppress the increase in the ripple voltage ΔV described above and suppress the generation of abnormal noise caused by distortion of the substrate 153 due to expansion and contraction of the MLCC 171. In other words, the length of the blanking period set here is set to a time shorter than the blanking period included in the video signal that serves as the input signal received via the signal input IF 111, i.e., the length of the blanking period specified by a general standard.

[0152] If it is determined in step S32 that the blanking period is not in progress, the process of step S33 is skipped.

[0153] In step S34, the signal processing unit 112 performs video signal processing on the row-by-row video signals distributed as the display units 51, such as applying color and brightness correction corresponding to each display unit 51.

[0154] In step S35, the signal processing unit 112 allocates the row-by-row video signals that have been subjected to the video signal processing to the LED drivers 121-1 to 121-N in the LED block 92, and transmits them via the corresponding output IFs 114-1 to 114-N.

[0155] In step S36, the LED drivers 121-1 to 121-N in the LED block 92 execute LED drive control processing based on the row-by-row video signal, and display images row by row at appropriate brightness using PWM control in the respective LED arrays 122-1 to 122-N.

[0156] Through the above processing, appropriate brightness adjustment is performed on each of the display units 51 that make up the video wall 33, and the brightness is output to the LED block 92, making it possible to display images row by row in sequence.

[0157] In addition, at this time, if the input video signal corresponds to the first row of a new frame, processing is stopped for a blanking period set by the above-mentioned equation (5) that is shorter than the length of the blanking period specified in the conventional standard.

[0158] This shortens the time during which the LED is turned off during the blanking period compared to the blanking period specified in the conventional standard, making it possible to suppress the generation of ripple voltage ΔV.

[0159] As a result, the application of ripple voltage ΔV to MCLL 171 is suppressed, which suppresses the occurrence of distortion of substrates 152 and 153 due to the expansion and contraction of MLCC 171 caused by the application of ripple voltage ΔV to MLCC 171, thereby making it possible to suppress the occurrence of abnormal noise.

[0160] Furthermore, since the blanking time using the above-described formula (5) is set in proportion to the capacitance C of the MLCC 171, the blanking time can be shortened by reducing the capacitance of the MLCC 171. This makes it possible to suppress the generation of abnormal noise and further reduce costs.

[0161] The present disclosure may also be configured as follows. <1> A drive control device including a light-emission control unit that controls light emission of LEDs constituting an LED (Light Emitting Diode) array, wherein the light-emission control unit controls the length of a period during which the LEDs are off to be shorter than a time indicated by an input signal. <2> The drive control device according to <1>, wherein the light-emission control unit controls the light emission of the LEDs constituting the LED array using a passive matrix drive method that controls the light emission of the LEDs constituting the LED array on a scan line basis. <3> The drive control device according to <1>, wherein the period during which the LEDs are off is a period from when the last row of the previous frame is displayed to when the first row of the next frame is displayed. <4> The drive control device according to <1>, wherein the time indicated by the input signal corresponds to a blanking period of the input signal. <5> The drive control device according to <1>, wherein the light-emission control unit controls the length of the period during which the LEDs are off to change a voltage applied to a capacitor provided on a substrate constituting the device. <6> The drive control device according to <5>, wherein the light-emission control unit controls the length of the period during which the LEDs are off to reduce the voltage applied to the capacitor to one-third or less. <7> The drive control device according to <1>, wherein the light-emission control unit controls the length of the period during which the LED is turned off in accordance with the capacitance or impedance of a capacitor provided on a substrate constituting the device. <8> The drive control device according to <7>, wherein the capacitor is an MLCC (Multilayer Ceramic Capacitor). <9> The drive control device according to <8>, wherein the light-emission control unit acquires information about the capacitor provided on a substrate constituting the device, and controls the length of the period during which the LED is turned off based on the acquired information about the capacitor. <10> A drive control method including a light-emission control step of controlling light emission of LEDs constituting an LED (Light Emitting Diode) array, wherein the processing of the light-emission control step controls the length of the period during which the LED is turned off to be shorter than the time indicated by an input signal.<11> The drive control method according to <10>, wherein the light emission control step is performed using a passive matrix drive method that controls the light emission of the LEDs constituting the LED array on a scan line basis. <12> The drive control method according to <10>, wherein the period during which the LEDs are turned off is the period from when the last row of the previous frame is displayed until the first row of the next frame is displayed. <13> The drive control method according to <10>, wherein the time indicated by the input signal corresponds to a blanking period of the input signal. <14> The drive control method according to <10>, wherein the light emission control step is performed by controlling the length of the period during which the LEDs are turned off so as to change the voltage applied to a capacitor provided on a substrate constituting the device. <15> The drive control method according to <14>, wherein the light emission control step is performed by controlling the length of the period during which the LEDs are turned off so that the voltage applied to the capacitor is one-third or less. <16> The drive control method according to <10>, wherein the light emission control step is performed by controlling the length of the period during which the LEDs are turned off in accordance with the capacitance or impedance of a capacitor provided on a substrate constituting the device. <17> The drive control method according to <16>, wherein the capacitor is a multilayer ceramic capacitor (MLCC) provided on a substrate constituting the device. <18> The drive control method according to <17>, wherein the light-emission control step acquires information about the capacitor provided on the substrate constituting the device, and controls the length of a period during which the LED is turned off based on the acquired information about the capacitor. <19> An information processing system comprising: a display unit including a display unit having LEDs (Light Emitting Diodes) arranged in an array and a drive control device that controls driving of the LEDs; and a distribution unit that receives input of a video signal, performs predetermined signal processing on the video signal, and distributes the video signal to the display unit, wherein the drive control device comprises: a light-emission control unit that controls light emission of the LEDs, and the light-emission control unit controls the length of the period during which the LED is turned off to be shorter than the time indicated by the input signal.<20> An information processing method for an information processing system including: a display section consisting of a display unit having LEDs (Light Emitting Diodes) arranged in an array and a drive control device that controls the drive of the LEDs; and a distribution section that receives an input of a video signal, performs predetermined signal processing on the video signal, and distributes it to the display unit, wherein the drive control device includes a light emission control step that controls light emission of the LEDs, and the processing of the light emission control step controls the length of a period during which the LEDs are turned off to be shorter than a time indicated by an input signal.

[0162] 11 Display system, 30 PC, 31 Video server, 32 Video wall controller, 33 Video wall, 51, 51-1 to 51-n Display unit, 78 Signal processing section, 91 Driver control section, 92 Driver block, 112 Signal processing section, 121, 121-1 to 121-N Drive circuit, 122 Pixel array, 151 AC power supply unit, 152, 153 Substrate / wiring, 161, 162 Wiring, 171 MLCC, 172 Connection section

Claims

1. A drive control device that includes a light emission control unit that controls the light emission of LEDs that make up an LED (Light Emitting Diode) array, and the light emission control unit controls the length of the period during which the LEDs are off so that it is shorter than the time indicated by an input signal.

2. The drive control device according to claim 1, wherein the light emission control unit controls the light emission of the LEDs that make up the LED array using a passive matrix drive method that controls the light emission of the LEDs in the LED array on a scan line basis.

3. The drive control device according to claim 1, wherein the period during which the LED is turned off is the period from when the last line of the previous frame is displayed until when the first line of the next frame is displayed.

4. The drive control device according to claim 1, wherein the time indicated by the input signal corresponds to a blanking period of the input signal.

5. The drive control device according to claim 1, wherein the light emission control unit controls the length of the period during which the LED is turned off so as to change the voltage applied to a capacitor provided on a substrate constituting the device.

6. The drive control device according to claim 5, wherein the light emission control unit controls the length of the period during which the LED is turned off so that the voltage applied to the capacitor is one-third or less.

7. The drive control device according to claim 1, wherein the light emission control unit controls the length of the period during which the LED is turned off in accordance with the capacitance or impedance of a capacitor provided on a substrate constituting the device.

8. The drive control device according to claim 7, wherein the capacitor is an MLCC (Multilayer Ceramic Capacitor).

9. The drive control device according to claim 8, wherein the light emission control unit acquires information about the capacitor provided on a substrate constituting the device, and controls the length of the period during which the LED is turned off based on the acquired information about the capacitor.

10. A drive control method including a light emission control step of controlling the light emission of LEDs constituting an LED (Light Emitting Diode) array, wherein the processing of the light emission control step controls the length of the period during which the LEDs are turned off to be shorter than the time indicated by an input signal.

11. A drive control method according to claim 10, wherein the light emission control step is performed using a passive matrix drive method that controls the light emission of the LEDs that make up the LED array in units of scan lines.

12. The drive control method according to claim 10, wherein the period during which the LED is turned off is the period from when the last line of the previous frame is displayed until when the first line of the next frame is displayed.

13. The drive control method according to claim 10, wherein the time indicated by the input signal corresponds to a blanking period of the input signal.

14. A drive control method according to claim 10, wherein the light emission control step controls the length of the period during which the LED is turned off so as to change the voltage applied to a capacitor provided on a substrate constituting the device.

15. A drive control method according to claim 14, wherein the light emission control step controls the length of the period during which the LED is turned off so that the voltage applied to the capacitor is one-third or less.

16. A drive control method according to claim 10, wherein the light emission control step controls the length of the period during which the LED is turned off in accordance with the capacitance or impedance of a capacitor provided on a substrate constituting the device.

17. The drive control method according to claim 16, wherein the capacitor is an MLCC (Multilayer Ceramic Capacitor) provided on a substrate that constitutes the device.

18. A drive control method according to claim 17, wherein the light emission control step acquires information about the capacitor provided on a substrate constituting the device, and controls the length of the period during which the LED is turned off based on the acquired information about the capacitor.

19. An information processing system comprising: a display section consisting of a display unit having LEDs (Light Emitting Diodes) arranged in an array and a drive control device that controls the driving of the LEDs; and a distribution section that receives input of a video signal, performs predetermined signal processing on the video signal, and distributes it to the display unit, wherein the drive control device comprises a light emission control section that controls the light emission of the LEDs, and the light emission control section controls the length of the period during which the LEDs are turned off to be shorter than the time indicated by the input signal.

20. An information processing method for an information processing system comprising: a display section consisting of a display unit having LEDs (Light Emitting Diodes) arranged in an array and a drive control device that controls the drive of the LEDs; and a distribution section that receives input of a video signal, performs predetermined signal processing on the video signal, and distributes it to the display unit, wherein the drive control device includes a light emission control step that controls the light emission of the LEDs, and the processing of the light emission control step controls the length of the period during which the LEDs are turned off to be shorter than the time indicated by the input signal.