Solid-state imaging device

Abstract

This solid-state imaging device comprises: a pixel that is provided on a first surface side serving as a light incident side of a substrate, and has a photoelectric conversion element for converting light into charges; a pixel separation region that is formed in the thickness direction of the substrate, extends in a first direction and a second direction to surround side surfaces of the pixel as seen from the second surface side of the substrate, and separates the pixel from other regions; a transistor that is provided at a position corresponding to the pixel on the second surface side of the substrate surrounded by the pixel separation region, a gate longitudinal direction of the transistor being oblique relative to the first direction and the second direction; and an FD region, transfer gate electrode of a transfer transistor, or substrate connection part provided at a position corresponding to the pixel in a gate width direction of the transistor on the second surface side of the substrate.

Description

solid-state imaging device

[0001] The present disclosure relates to a solid-state imaging device.

[0002] Patent Document 1 discloses a solid-state imaging device. In this solid-state imaging device, one pixel is formed in an area surrounded by an inter-pixel light-shielding wall. At a position corresponding to one pixel, a photodiode is formed on the back side of a semiconductor substrate, and a pixel circuit is formed on the front side of the semiconductor substrate. The pixel circuit is constructed of an amplification transistor, a selection transistor, a floating diffusion conversion gain switching transistor, and a reset transistor.

[0003] Japanese Patent Application Laid-Open No. 2018-148116

[0004] In solid-state imaging devices, the area of ​​an element isolation region that separates the multiple transistors that make up a pixel circuit, the floating diffusion region, the transfer transistor, and the well contact at a position corresponding to one pixel is large. As a result, as pixels become smaller, it becomes more difficult to secure the area for arranging the transistors. Therefore, in solid-state imaging devices, it is desirable to increase the area for arranging the transistors and improve their performance.

[0005] a pixel isolation region formed in the thickness direction of the base, and extending in a first direction and a second direction intersecting the first direction when viewed from a second surface side of the base opposite to the first surface, to surround a periphery of a side surface of the first pixel and electrically and optically isolate the first pixel from other regions; a first transistor disposed on the second surface side of the base surrounded by the pixel isolation region at a position corresponding to the first pixel, and having a gate length direction oblique to the first direction or the second direction; a first floating diffusion region disposed on the second surface side of the base at a position corresponding to the first pixel in the gate width direction of the first transistor; and a first base connection portion for supplying a voltage to the base or a first transfer gate electrode of a first transfer transistor that transfers charge from the first pixel to the first floating diffusion region.

[0006] A solid-state imaging device according to a second embodiment of the present disclosure includes: a first pixel disposed on a first surface side of a substrate, which is a light incident side, and having a first photoelectric conversion element that converts light into an electric charge; a pixel isolation region formed in the thickness direction of the substrate, which extends in a first direction and a second direction intersecting the first direction when viewed from a second surface side of the substrate opposite the first surface, surrounding a lateral periphery of the first pixel, and electrically and optically isolating the first pixel from other regions; and a first transistor disposed on the second surface side of the substrate, the periphery of which is surrounded by the pixel isolation region, at a position corresponding to the first pixel, and having a gate length direction oblique to the first direction or the second direction. The pixel isolation region includes a second transistor disposed on a second surface side of a substrate surrounded by a pixel isolation region at a position corresponding to the first pixel, the second transistor having a gate length direction oblique to the first direction or the second direction and electrically connected in series to the first transistor, a first floating diffusion region disposed on the second surface side of the substrate at a position corresponding to the first pixel in the gate width direction of the first transistor and the second transistor, and a first substrate connection portion that supplies voltage to the substrate or a first transfer gate electrode of the first transfer transistor that transfers charge from the first pixel to the first floating diffusion region.

[0007] A solid-state imaging device according to a third embodiment of the present disclosure includes: a plurality of arranged pixels, each having a photoelectric conversion element that converts light into an electric charge, and arranged on a first surface side of a substrate that is the light incident side; a pixel isolation region that is formed in the thickness direction of the substrate, surrounds the side surfaces of the plurality of pixels, and electrically and optically isolates the plurality of pixels; transistors that are arranged on a second surface side of the substrate surrounded by the pixel isolation region at positions corresponding to the pixels, and have a gate length direction oblique to the pixel arrangement direction; floating diffusion regions that are arranged in the gate width direction of the transistor on the second surface side of the substrate at positions corresponding to the pixels; and a first substrate connection portion that supplies voltage to the substrate or to transfer gate electrodes of transfer transistors that transfer electric charge from the pixels to the floating diffusion region.

[0008] A solid-state imaging device according to a fourth embodiment of the present disclosure includes a first pixel disposed on a first surface side of a substrate, which is the light incident side, and having a first photoelectric conversion element that converts light into an electric charge; a second pixel disposed adjacent to the first pixel and on the first surface side of the substrate, and having a second photoelectric conversion element that converts light into an electric charge; a pixel isolation region disposed between the first pixel and the second pixel, formed in the thickness direction of the substrate, and electrically and optically isolating the first pixel and the second pixel; a first transistor disposed on the second surface side of the substrate at a position corresponding to the first pixel, and having a gate length direction oblique to the arrangement direction of the first pixel and the second pixel; a second transistor disposed on the second surface side of the substrate at a position corresponding to the second pixel, and having a gate length direction oblique to the arrangement direction of the first pixel and the second pixel; and a shared connection portion electrically connected directly to one of a pair of main electrodes of the first transistor and one of a pair of main electrodes of the second transistor, and supplying a power supply voltage.

[0009] 14 is a circuit diagram showing a pixel and a pixel circuit of a solid-state imaging device according to a first embodiment of the present disclosure. It is a plan configuration diagram illustrating a basic configuration of a transistor constituting the pixel circuit shown in FIG. 1. It is a specific plan configuration diagram of the pixel circuit shown in FIG. 1. It is a longitudinal cross-sectional configuration diagram of a portion of the pixel and pixel circuit shown in FIG. 1 (a cross-sectional diagram cut along the A-A section line shown in FIG. 3). It is a specific plan configuration diagram illustrating a wiring connection state in the pixel circuit shown in FIG. 3. It is a cross-sectional diagram corresponding to FIG. 4 at a first step, illustrating a manufacturing method of the solid-state imaging device according to the first embodiment. It is a cross-sectional diagram corresponding to FIG. 4 at a second step. It is a cross-sectional diagram corresponding to FIG. 12 at a third step. It is a cross-sectional diagram at a fourth step. It is a cross-sectional diagram at a fifth step. It is a cross-sectional diagram corresponding to FIG. 12 at a sixth step. It is a specific plan configuration diagram corresponding to FIG. 3 of a pixel circuit of a solid-state imaging device according to a second embodiment of the present disclosure. It is a longitudinal cross-sectional configuration diagram (a cross-sectional diagram cut along the B-B section line shown in FIG. 12) of a portion of the pixel and pixel circuit shown in FIG. 12. It is a circuit diagram corresponding to FIG. 1 showing a pixel and a pixel circuit of a solid-state imaging device according to a third embodiment of the present disclosure. It is a specific plan configuration diagram corresponding to FIG. 3 of the pixel circuit shown in FIG. 16 is a specific planar configuration diagram corresponding to FIG. 3 of a portion of a pixel circuit of a solid-state imaging device according to a fourth embodiment of the present disclosure. FIG. 17 is a longitudinal cross-sectional configuration diagram (a cross-sectional view taken along the C-C section line shown in FIG. 16) of a portion of the pixel circuit shown in FIG. 16. FIG. 18 is a longitudinal cross-sectional configuration diagram (a cross-sectional view taken along the D-D section line shown in FIG. 16) of a portion of the pixel circuit of a solid-state imaging device according to a first modified example of the fourth embodiment, corresponding to FIG. 16. FIG. 19 is a longitudinal cross-sectional configuration diagram (a cross-sectional view taken along the E-E section line shown in FIG. 19). FIG. 19 is a longitudinal cross-sectional configuration diagram (a cross-sectional view taken along the F-F section line shown in FIG. 19) of a portion of the pixel circuit of a solid-state imaging device according to a second modified example of the fourth embodiment, corresponding to FIG. 16. FIG. 22 is a longitudinal cross-sectional configuration diagram (a cross-sectional view taken along the G-G section line shown in FIG. 22) of a portion of the pixel circuit. 23 is a vertical cross-sectional configuration diagram of a portion of the pixel circuit shown in FIG. 22 (a cross-sectional view taken along the HH cutting line shown in FIG. 22).29 is a specific planar configuration diagram corresponding to FIG. 3 of a portion of a pixel circuit of a solid-state imaging device according to a fifth embodiment of the present disclosure. 29 is a longitudinal cross-sectional configuration diagram (cross-sectional view taken along the II section line shown in FIG. 25 ) of a portion of the pixel circuit shown in FIG. 25 . 30 is a specific planar configuration diagram corresponding to FIG. 5 , illustrating a wiring connection state in a pixel circuit of a solid-state imaging device according to a sixth embodiment of the present disclosure. 31 is a specific planar configuration diagram corresponding to FIG. 5 , illustrating a pixel circuit and a wiring connection state of a solid-state imaging device according to a seventh embodiment of the present disclosure. 32 is a specific planar configuration diagram corresponding to FIG. 3 of a pixel circuit of a solid-state imaging device according to an eighth embodiment of the present disclosure. 33 is a longitudinal cross-sectional configuration diagram (cross-sectional view taken along the J-J section line shown in FIG. 29 ) of a pixel and a portion of the pixel circuit. 34 is a specific planar configuration diagram corresponding to FIG. 5 , illustrating a wiring connection state of the pixel circuit shown in FIG. 29 . 35 is a specific planar configuration diagram corresponding to FIG. 3 of a pixel circuit of a solid-state imaging device according to a ninth embodiment of the present disclosure. 36 is a longitudinal cross-sectional configuration diagram (cross-sectional view taken along the K-K section line shown in FIG. 36 ) of a pixel and a portion of the pixel circuit. 39 is a plan configuration diagram corresponding to FIG. 33 illustrating an array layout of pixels and pixel circuits in a solid-state imaging device according to a first modified example of the tenth embodiment. FIG. 40 is a plan configuration diagram corresponding to FIG. 33 illustrating an array layout of pixels and pixel circuits in a solid-state imaging device according to a second modified example of the tenth embodiment. FIG. 41 is a plan configuration diagram corresponding to FIG. 33 illustrating an array layout of pixels and pixel circuits in a solid-state imaging device according to a third modified example of the tenth embodiment. FIG. 42 is a plan configuration diagram corresponding to FIG. 33 illustrating an array layout of pixels and pixel circuits in a solid-state imaging device according to a fourth modified example of the tenth embodiment. FIG. 43 is a longitudinal sectional configuration diagram corresponding to FIG. 4 of a portion of pixels and pixel circuits in a solid-state imaging device according to an eleventh embodiment of the present disclosure. FIG. 44 is a circuit diagram showing pixels and pixel circuits in a solid-state imaging device according to a twelfth embodiment of the present disclosure. FIG. 45 is a specific plan configuration diagram of the pixel circuit shown in FIG. 39. FIG. 46 is a longitudinal sectional configuration diagram (a cross-sectional view taken along the L-L cutting line shown in FIG. 40) of a portion of pixels and pixel circuits shown in FIG. 41. FIG. 47 is a cross-sectional view schematically illustrating a first process, illustrating a method for manufacturing a solid-state imaging device according to the twelfth embodiment. FIG. 48 is a cross-sectional view corresponding to FIG. 48. FIG. 49 is a cross-sectional view corresponding to FIG. 49. FIG. 50 is a cross-sectional view corresponding to FIG. 50. FIG. 51 is a cross-sectional view corresponding to FIG. 50.42 ; FIG. 43 is a cross-sectional view illustrating a seventh process; FIG. 44 is a longitudinal cross-sectional configuration diagram corresponding to FIG. 42 of a portion of pixels and pixel circuits of a solid-state imaging device according to a thirteenth embodiment of the present disclosure; FIG. 44 is a cross-sectional view illustrating a first process corresponding to FIG. 42 , illustrating a manufacturing method of a solid-state imaging device according to the thirteenth embodiment; FIG. 45 is a cross-sectional view illustrating a second process; FIG. 46 is a specific plan configuration diagram corresponding to FIG. 40 of a pixel circuit of a solid-state imaging device according to a fourteenth embodiment of the present disclosure; FIG. 47 is a specific plan configuration diagram corresponding to FIG. 40 of a pixel circuit of a solid-state imaging device according to a fifteenth embodiment of the present disclosure; FIG. 48 is a specific plan configuration diagram corresponding to FIG. 40 of a pixel circuit of a solid-state imaging device according to a sixteenth embodiment of the present disclosure; FIG. 49 is a plan configuration diagram illustrating a basic arrangement configuration corresponding to FIG. 40 of a pixel circuit of a solid-state imaging device according to a seventeenth embodiment of the present disclosure; FIG. 55 is a plan configuration diagram illustrating a specific arrangement configuration corresponding to FIG. 55 of a pixel circuit of a solid-state imaging device according to a modification of the seventeenth embodiment; FIG. 56 is a plan configuration diagram illustrating a specific arrangement configuration of pixels, color filters, and optical lenses of a solid-state imaging device according to an eighteenth embodiment of the present disclosure; and FIG. 57 is a plan configuration diagram illustrating pixels, pixel circuits, and a wiring connection state of a solid-state imaging device according to the eighteenth embodiment. 19 is a plan view illustrating a pixel in which a color filter of a specific color is arranged, a pixel circuit, and a wiring connection state in a solid-state imaging device according to an eighteenth embodiment. 20 is a block diagram illustrating an example of a schematic configuration of a vehicle control system, which is a first application example according to an embodiment of the present disclosure. 21 is an explanatory diagram illustrating an example of installation positions of an outside-vehicle information detection unit and an imaging unit.

[0010] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. The description will be made in the following order. 1. First Embodiment The first embodiment will describe an example in which the present technology is applied to a solid-state imaging device. The first embodiment will describe in detail the circuit configuration, planar configuration, longitudinal cross-sectional configuration of the pixels and pixel circuits of the solid-state imaging device, and a manufacturing method for the solid-state imaging device. 2. Second Embodiment The second embodiment will describe a first example in which the configuration of transistors in the pixel circuit is changed in the solid-state imaging device according to the first embodiment. 3. Third Embodiment The third embodiment will describe a second example in which the configuration of transistors in the pixel circuit is changed in the solid-state imaging device according to the first embodiment. 4. Fourth Embodiment The fourth embodiment will describe an example in which the configuration of the gate electrode of the transfer transistor of the pixel is changed in the solid-state imaging device according to any of the first to third embodiments. The fourth embodiment will further describe several modifications. 5. Fifth Embodiment The fifth embodiment will describe a first example in which the planar layout configuration of transistors in the pixel circuit is changed in the solid-state imaging device according to any of the first to fourth embodiments. 6. Sixth Embodiment The sixth embodiment describes a second example in which the planar layout configuration of pixel circuit transistors is changed in a solid-state imaging device according to any one of the first to fourth embodiments. 7. Seventh Embodiment The seventh embodiment describes a third example in which the planar layout configuration of pixel circuit transistors is changed in a solid-state imaging device according to any one of the first to fourth embodiments. 8. Eighth Embodiment The eighth embodiment describes an example in which the configuration of the shared connection section of the pixel circuit is changed in a solid-state imaging device according to any one of the first to seventh embodiments. 9. Ninth Embodiment The ninth embodiment describes an example in which the connection configuration of the pixel circuit wiring is changed in a solid-state imaging device according to any one of the first to seventh embodiments. 10. Tenth Embodiment The tenth embodiment describes a fourth example in which the planar layout configuration of pixel circuit transistors is changed in a solid-state imaging device according to the fifth embodiment. The tenth embodiment further describes several modifications.11. Eleventh Embodiment The eleventh embodiment describes an example in which the configuration of the element isolation region of the pixel circuit is changed in the solid-state imaging device according to any one of the first to tenth embodiments. 12. Twelfth Embodiment The twelfth embodiment describes an example in which the configuration of the supply of power supply voltage is changed in the solid-state imaging device according to any one of the first to eleventh embodiments. The twelfth embodiment provides detailed descriptions of the circuit configuration, planar configuration, longitudinal cross-sectional configuration, and manufacturing method of the pixel and pixel circuit of the solid-state imaging device. 13. Thirteenth Embodiment The thirteenth embodiment describes an example in which the configuration of the shared connection section of the pixel circuit is changed in the solid-state imaging device according to the twelfth embodiment. The thirteenth embodiment also describes a manufacturing method of the solid-state imaging device. 14. Fourteenth Embodiment The fourteenth embodiment describes a first example in which the array layout configuration of the shared connection section of the pixel circuit is changed in the solid-state imaging device according to the twelfth or thirteenth embodiment. 15. Fifteenth Embodiment The fifteenth embodiment describes a second example in which the array layout configuration of the shared connection portion of the pixel circuits is changed in the solid-state imaging device according to the twelfth or thirteenth embodiment. 16. Sixteenth Embodiment The sixteenth embodiment describes a third example in which the array layout configuration of the shared connection portion of the pixel circuits is changed in the solid-state imaging device according to the twelfth or thirteenth embodiment. 17. Seventeenth Embodiment The seventeenth embodiment describes a fourth example in which the array layout configuration of the shared connection portion of the pixel circuits is changed in the solid-state imaging device according to the twelfth or thirteenth embodiment. The seventeenth embodiment also describes a further modification. 18. Eighteenth Embodiment The eighteenth embodiment describes an application example of the solid-state imaging device according to the twelfth or thirteenth embodiment. The eighteenth embodiment describes the planar layout configuration of pixels and pixel circuits, the planar layout configuration of color filters, and the planar layout configuration of optical lenses. 19. Application Example to a Mobile Body An example in which the present technology is applied to a vehicle control system, which is an example of a mobile body control system, is described. 20. Other Embodiments

[0011] 1. First Embodiment A solid-state imaging device 1 according to a first embodiment of the present disclosure will be described with reference to FIGS.

[0012] Here, the arrow X direction shown as appropriate in the figures indicates one planar direction of the solid-state imaging device 1 placed on a flat surface for convenience. The arrow Y direction indicates another planar direction perpendicular to the arrow X direction. The arrow Z direction indicates an upward direction perpendicular to the arrow X direction and the arrow Y direction. In other words, the arrow X direction, arrow Y direction, and arrow Z direction exactly correspond to the X-axis direction, Y-axis direction, and Z-axis direction, respectively, of a three-dimensional coordinate system. Note that these directions are shown to facilitate understanding of the explanation and do not limit the directions of the present technology.

[0013] [Configuration of solid-state imaging device 1] (1) Circuit configuration of pixel 10 and pixel circuit 20 of solid-state imaging device 1 FIG. 1 shows an example of the circuit configuration of pixel 10 and pixel circuit 20 that constitutes solid-state imaging device 1 according to the first embodiment.

[0014] One pixel 10 is composed of a series circuit of a photoelectric conversion element (photodiode) 11 and a transfer transistor 12. Here, four pixels 10 are configured as a unit pixel (BP). The photoelectric conversion element 11 converts light incident from outside the solid-state imaging device 1 into an electric charge (electrical signal). The transfer transistor 12 includes a transfer gate electrode and a pair of main electrodes. One of the pair of main electrodes is connected to the photoelectric conversion element 11. The other main electrode is connected to the pixel circuit 20 via a floating diffusion region (hereinafter simply referred to as the "FD region") 25. The transfer gate electrode is connected to a horizontal signal line (not shown). A control signal TG is input to the transfer gate electrode from the horizontal signal line.

[0015] Here, a pixel circuit 20 is provided for each unit pixel. That is, one pixel circuit 20 is provided for four pixels 10. The pixel circuit 20 performs signal processing of the charge converted from light in the pixel 10. In the first embodiment, the pixel circuit 20 is configured to include four transistors, a first transistor to a fourth transistor.

[0016] Here, the first transistor is an amplification transistor 21 having a gate electrode and a pair of main electrodes. The second transistor is a selection transistor 22 having a gate electrode and a pair of main electrodes. The third transistor is a floating diffusion conversion gain switching transistor (hereinafter simply referred to as "FD conversion gain switching transistor") 23 having a gate electrode and a pair of main electrodes. And the fourth transistor is a reset transistor 24 having a gate electrode and a pair of main electrodes.

[0017] The gate electrode of the amplification transistor 21 is connected to the FD region 25. One main electrode of the amplification transistor 21 is connected to a power supply voltage terminal VDD, and the other main electrode is connected to one main electrode of the selection transistor 22. Here, the power supply voltage is, for example, 2.8 V. Alternatively, the power supply voltage may be, for example, 2.2 V. The gate electrode of the selection transistor 22 is connected to a selection signal line SEL. The other main electrode of the selection transistor 22 is connected to a vertical signal line VSL and a current source load LC. The current source load LC is connected to a reference voltage terminal GND. The gate electrode of the FD conversion gain switching transistor 23 is connected to a floating diffusion control signal line FDG. One main electrode of the FD conversion gain switching transistor 23 is connected to the FD region 25, and the other main electrode is connected to one main electrode of the reset transistor 24. The gate electrode of the reset transistor 24 is connected to a reset signal line RST. The other main electrode of the reset transistor 24 is connected to the power supply voltage terminal VDD.

[0018] In the solid-state imaging device 1, the pixel circuits 20 are further connected to an image processing circuit (not shown). The image processing circuit includes, for example, an analog-to-digital converter (ADC) and a digital signal processor (DSP). The charges converted from light by the pixels 10 are analog signals. These analog signals are amplified in the pixel circuits 20. The ADC converts the analog signals output from the pixel circuits 20 into digital signals. The DSP performs functional processing of the digital signals. In other words, the image processing circuit performs signal processing for image creation.

[0019] (2) Basic Layout Configuration of the Transistor 200 Constituting the Pixel 10 and the Pixel Circuit 20 Fig. 2 shows an example of the basic configuration of the transistor 200 constituting the pixel 10 and the pixel circuit 20. When viewed from the direction of the arrow Z (hereinafter simply referred to as "in a plan view"), the transistor 200 constituting one pixel 10 and one pixel circuit 20 is disposed in an area surrounded by a pixel isolation region 16. The side opposite to the direction of the arrow Z is configured as a light incident surface. A photoelectric conversion element 11 constituting the pixel 10 is disposed on the light incident surface side.

[0020] The pixel isolation regions 16 extend in the direction of the arrow X with a constant width, and a plurality of pixel isolation regions 16 are arranged in the direction of the arrow Y with a constant spacing therebetween. Similarly, the pixel isolation regions 16 extend in the direction of the arrow Y with a constant width, and a plurality of pixel isolation regions 16 are arranged in the direction of the arrow X with a constant spacing therebetween. In other words, the pixel isolation regions 16 are arranged in a lattice shape in a plan view, and the pixels 10 and transistors 200 are arranged in the areas partitioned by the pixel isolation regions 16.

[0021] Although not particularly limited, in the first embodiment, the pixels 10 and the transistors 200 are arranged in a region defined by the pixel isolation region 16 in a square shape in plan view. Here, one pixel 10 is arranged in one region defined by the pixel isolation region 16. One transistor 200 that constitutes the pixel circuit 20 is arranged in one region defined by the pixel isolation region 16. The respective longitudinal cross-sectional structures of the pixel isolation region 16 and the transistor 200 will be described later.

[0022] The transistor 200 is a first transistor, a second transistor, a third transistor, or a fourth transistor. That is, the transistor 200 is any one of the amplification transistor 21, the selection transistor 22, the FD conversion gain switching transistor 23, and the reset transistor 24.

[0023] The transistor 200 is surrounded by an element isolation region 26 and is electrically and optically isolated from other regions. The transistor 200 includes a channel formation region 201, a gate insulating film 202, a gate electrode 203, and a pair of main electrodes 204. The main electrodes 204 are formed of an n-type semiconductor region having a first conductivity type, and are used as a source electrode or a drain electrode. Here, the transistor 200 is an n-channel insulated gate field effect transistor (IGFET). IGFETs include metal oxide semiconductor field effect transistors (MOSFETs) and metal insulator semiconductor field effect transistors (MISFETs).

[0024] The transistor 200 is disposed in a region corresponding to the pixel 10, obliquely relative to the extension direction of the pixel isolation region 16. More specifically, the transistor 200 is disposed in a region (a square region in a plan view) partitioned by the pixel isolation region 16, with the gate length Lg direction aligned with the diagonal line D1-D1 extending from the upper left to the lower right, shown as an imaginary line. The gate length Lg is the effective length between the pair of main electrodes 204 of the gate electrode 203. The gate width Wg is the length in a direction perpendicular to the gate length Lg direction, aligned with the diagonal line D2-D2 extending from the lower left to the upper right, shown as an imaginary line. Here, the minimum angle α1 formed by the pixel isolation region 16 extending in the direction indicated by the arrow X and the diagonal line D1-D1 is 45 degrees. The maximum angle is 135 degrees. The minimum angle α2 formed by the pixel isolation region 16 extending in the direction of the arrow Y and the diagonal line D1-D1 is, of course, 45 degrees. When the angle α1 is set to 45 degrees, the gate length Lg and gate width Wg of the transistor 200 can be maximized.

[0025] The angle α1 can be set appropriately to an angle equal to or greater than 15 degrees and less than 75 degrees. In other words, when the transistor 200 is arranged obliquely, the gate length Lg and gate width Wg of the transistor 200 can be increased compared to when the transistor 200 is not arranged obliquely.

[0026] Meanwhile, in the region partitioned by the pixel isolation region 16, an FD region 25 and a base connection portion 27 are arranged so as to coincide with the diagonal line D2-D2. The FD region 25 is arranged at the lower left corner where the pixel isolation region 16 extending in the direction of the arrow X intersects with the pixel isolation region 16 extending in the direction of the arrow Y. The FD region 25 is formed of an n-type semiconductor region. The FD region 25 is arranged with the element isolation region 26 interposed between it and the transistor 200.

[0027] A transfer gate electrode (vertical gate electrode) 205 is disposed at a position spaced apart to the right of the FD region 25. The transfer gate electrode 205 is the gate electrode of the transfer transistor 200, and extends on the base 15 with the thickness direction of the base 15 as the gate length Lg direction.

[0028] The base connection portion 27 is disposed at the upper right corner where the pixel isolation region 16 extending in the direction of the arrow X intersects with the pixel isolation region 16 extending in the direction of the arrow Y. The base connection portion 27 is formed of a p-type semiconductor region as the second conductivity type. In the first embodiment, the base 15 is formed as a p-type well region. That is, the base 15 is connected to the reference voltage terminal GND via the base connection portion 27. Like the FD region 25, the base connection portion 27 is disposed relative to the transistor 200 with the element isolation region 26 interposed therebetween.

[0029] 2, the portion indicated by a black circle is a connection region (contact region) with wiring disposed in an upper layer on the opposite side of the transistor 200 from the photoelectric conversion element 11. The wiring is, for example, the wiring 7 shown in FIG. 4. For example, copper (Cu) wiring is used as the wiring. The connection region is, for example, the connection hole 6H shown in FIG. 4.

[0030] (3) Basic Layout Configuration of Shared Contacts 31 to 33 A shared contact 31, a shared contact 32, and a shared contact 33 are disposed between a plurality of pixels 10.

[0031] Here, the shared connection portion 31 is disposed between the transistor 200 of the pixel 10 and the transistor 200 of another pixel 10 (not shown) adjacent in the direction of the arrow Y. To explain in more detail, one end of the shared connection portion 31 is electrically and directly connected to one main electrode 204 of the transistor 200, and the other end is electrically and directly connected across the pixel isolation region 16 to one main electrode of the other transistor 200. In other words, the shared connection portion 31 directly connects the main electrodes 204 of the transistors 200 across the pixel isolation region 16 without forming a wiring on the transistor 200 and a connection hole in the interlayer insulating film between the transistor 200 and the wiring.

[0032] Here, the shared connection portion 32 is disposed between the FD region 25 of the pixel 10 and the FD region 25 of another pixel 10 (not shown) adjacent in the directions of the arrow X and the arrow Y. To explain in more detail, the shared connection portion 32 is formed across the FD regions 25 of a total of four pixels 10 adjacent in the directions of the arrow X and the arrow Y, and is electrically connected directly to the total of four FD regions 25.

[0033] Here, the shared connection portion 33 is disposed between the base connection portion 27 of the pixel 10 and the base connection portion 27 of another pixel 10 (not shown) adjacent in the directions of the arrow X and the arrow Y. Similar to the shared connection portion 32, the shared connection portion 33 is formed across the base connection portions 27 of a total of four pixels 10 adjacent in the directions of the arrow X and the arrow Y, and is electrically connected directly to the total of four base connection portions 27.

[0034] (4) Layout and longitudinal cross-sectional configuration of pixel 10 and pixel circuit 20 Fig. 3 shows an example of a specific planar configuration of the pixel 10 and pixel circuit 20. Fig. 4 shows a longitudinal cross-sectional configuration (a cross-section taken along the A-A section line shown in Fig. 3) of a portion of the pixel 10 and pixel circuit 20. Fig. 5 shows an array layout configuration of the unit pixel BP shown in Fig. 3 and the surrounding pixels 10 (or unit pixels BP).

[0035] 3 and 5, in the first embodiment, one pixel circuit 20 is provided for four pixels 10. More specifically, the four pixels 10 are two pixels 10A and 10B adjacent to each other in the direction indicated by the arrow X, and two pixels 10C and 10D adjacent to pixels 10A and 10B in the direction indicated by the arrow Y and also adjacent to pixels 10A and 10B in the direction indicated by the arrow X. These four pixels 10A, 10B, 10C, and 10D constitute a unit pixel BP.

[0036] First, a selection transistor 22 of a pixel circuit 20 is disposed at a position corresponding to pixel 10D. The selection transistor 22 is disposed in an area partitioned by pixel isolation region 16, with the direction of gate length Lg aligned with diagonal line D1-D1.

[0037] As shown in Figure 4, the select transistor 22 is disposed on the main surface of the base 15 opposite the light incident side (in Figure 4, this is the second surface as the top surface of the base 15). Here, for example, a semiconductor substrate is used for the base 15. More specifically, a single crystal silicon substrate having a p-type semiconductor region (or p-type well region) 151 is used. A photoelectric conversion element 11 is disposed on the light incident side of the base 15 (in Figure 4, this is the first surface side as the bottom surface of the base 15). The photoelectric conversion element 11 is formed at a pn junction between the p-type semiconductor region 151 and an n-type semiconductor region (reference numeral omitted).

[0038] Here, the pixel isolation region 16 includes a first groove 161 and a first embedded member 162. The first groove 161 is formed as a deep groove penetrating the base 15 in the thickness direction from the upper surface to the lower surface. The first embedded member 162 is embedded in the first groove 161. Here, the first embedded member 162 is formed by an insulator 162A provided along the inner wall of the first groove 161 and an embedded member 162B embedded in the first groove 161 with the insulator 162A interposed therebetween. The insulator 162A is made of, for example, a silicon oxide film, a silicon nitride film, or the like. The embedded member 162B is made of, for example, a silicon oxide film, a polycrystalline silicon film, or the like. In other words, the pixel isolation region 16 has a trench isolation structure. Although detailed illustration and description are omitted here, in the region corresponding to the photoelectric conversion element 11, a pinning region is disposed between the photoelectric conversion element 11 inside the base 15 and the pixel isolation region 16.

[0039] As explained in the transistor 200, the select transistor 22 includes a channel formation region 201, a gate insulating film 202, a gate electrode 203, and a pair of main electrodes 204. The channel formation region 201 is formed by the p-type semiconductor region 151 of the substrate 15. The gate insulating film 202 is formed on the surface of the channel formation region 201. The gate insulating film 202 is formed, for example, by a single layer film such as a silicon oxide film, a silicon nitride film, or an oxynitride film, or a composite film thereof. The gate electrode 203 is formed on the surface of the gate insulating film 202 opposite to the channel formation region 201. The gate electrode 203 is formed, for example, by a single layer film of a gate electrode material such as a polycrystalline silicon film, a refractory metal film, or a refractory metal silicide film which is a compound of polycrystalline silicon and a refractory metal, or a composite film thereof. As shown in FIGS. 2 and 3, the main electrodes 204 are arranged in pairs on the main surface of the substrate 15 in the gate length Lg direction, with the gate electrode 203 at the center, and are formed of n-type semiconductor regions.

[0040] 2, 3, and 5, an FD region 25 and a base connection portion 27 are disposed at positions that coincide with the diagonal line D2-D2 and face each other with the select transistor 22 at the center. Element isolation regions 26 are formed between the FD region 25 and the select transistor 22, and between the base connection portion 27 and the select transistor 22. The FD region 25 is disposed on the main surface of the base 15, and is formed of an n-type semiconductor region, similar to the main electrode 204 of the select transistor 22. The base connection portion 27 is disposed on the main surface of the base 15, and is formed of a p-type semiconductor region having a higher impurity density than the p-type semiconductor region 151 of the base 15.

[0041] 4, the element isolation region 26 includes a second groove 261 and a second embedded member 262. The second groove 261 is a groove formed in the thickness direction from the upper surface of the base 15 toward the lower surface. The second groove 261 is a groove that does not reach the photoelectric conversion element 11, and the depth of the second groove 261 is shallower than the depth of the first groove 161. The second embedded member 262 is embedded in the second groove 261. The second embedded member 262 is formed, for example, from a silicon oxide film or the like, similar to the insulator 162A.

[0042] 3 and 5, an amplifier transistor 21 of a pixel circuit 20 is disposed at a position corresponding to pixel 10B. The amplifier transistor 21 is disposed in an area partitioned by pixel isolation region 16, with the direction of its gate length Lg aligned with diagonal line D2-D2.

[0043] The amplification transistor 21, like the selection transistor 22, is disposed on the main surface of the base 15. Like the selection transistor 22, the amplification transistor 21 includes a channel formation region 201, a gate insulating film 202, a gate electrode 203, and a pair of main electrodes 204.

[0044] 3 and 5, an FD region 25 and a base connection portion 27 are disposed at positions that coincide with the diagonal line D1-D1 and face each other with the amplifying transistor 21 at the center. Element isolation regions 26 are formed between the FD region 25 and the amplifying transistor 21, and between the base connection portion 27 and the amplifying transistor 21, respectively.

[0045] In a plan view, the amplification transistor 21 is formed in a shape that is line-symmetrical with respect to the selection transistor 22, with the pixel isolation region 16 extending in the direction of the arrow X as the center. Therefore, one main electrode 204 of the selection transistor 22 is disposed close to one main electrode 204 of the amplification transistor 21 in the direction of the arrow Y, with the pixel isolation region 16 interposed therebetween. One main electrode (input electrode or drain electrode) 204 of the selection transistor 22 and one main electrode (output electrode or source electrode) 204 of the amplification transistor 21 are electrically connected by a shared connection portion 31.

[0046] 3 and 5, the FD conversion gain switching transistor 23 of the pixel circuit 20 is disposed at a position corresponding to the pixel 10A. The FD conversion gain switching transistor 23 is disposed in an area partitioned by the pixel isolation region 16, with the gate length Lg direction aligned with the diagonal line D1-D1, similar to the selection transistor 22.

[0047] 4, the FD conversion gain switching transistor 23 is disposed on the main surface of the base 15. Like the selection transistor 22, the FD conversion gain switching transistor 23 includes a channel formation region 201, a gate insulating film 202, a gate electrode 203, and a pair of main electrodes 204.

[0048] 3 and 5, an FD region 25 and a base connection portion 27 are disposed at positions that coincide with the diagonal line D2-D2 and face each other with the FD conversion gain switching transistor 23 at the center. An element isolation region 26 is formed between the FD region 25 and the FD conversion gain switching transistor 23, and between the base connection portion 27 and the FD conversion gain switching transistor 23. In a plan view, the FD conversion gain switching transistor 23 is formed in line symmetry with respect to the amplification transistor 21, with the pixel isolation region 16 extending in the direction of the arrow Y at the center.

[0049] Furthermore, a reset transistor 24 of the pixel circuit 20 is disposed at a position corresponding to the pixel 10C. The reset transistor 24 is disposed in a region partitioned by the pixel isolation region 16, with the gate length Lg direction aligned with the diagonal line D2-D2, similar to the amplification transistor 21.

[0050] The reset transistor 24, like the select transistor 22, is disposed on the main surface of the base 15. Like the select transistor 22, the reset transistor 24 includes a channel formation region 201, a gate insulating film 202, a gate electrode 203, and a pair of main electrodes 204.

[0051] 3 and 5, an FD region 25 and a base connection portion 27 are disposed at positions that coincide with the diagonal line D1-D1 and face each other with the reset transistor 24 at the center. Element isolation regions 26 are formed between the FD region 25 and the reset transistor 24, and between the base connection portion 27 and the reset transistor 24, respectively.

[0052] In a plan view, the reset transistor 24 is formed in a shape that is line-symmetrical with respect to the FD conversion gain switching transistor 23, with the pixel isolation region 16 extending in the direction of the arrow X as the center. Therefore, one main electrode 204 of the reset transistor 24 is disposed close to one main electrode 204 of the FD conversion gain switching transistor 23 in the direction of the arrow Y, with the pixel isolation region 16 interposed therebetween. One main electrode (input electrode or drain electrode) 204 of the reset transistor 24 and one main electrode (output electrode or source electrode) 204 of the FD conversion gain switching transistor 23 are electrically connected by a shared connection portion 31.

[0053] In addition, in plan view, the reset transistor 24 is formed in a shape that is line-symmetrical with respect to the selection transistor 22, with the pixel isolation region 16 extending in the direction of the arrow Y as the center.

[0054] (5) Specific Vertical Cross-Sectional Configurations of Shared Connections 31-33 As shown in FIGS. 3 to 5 , a total of four FD regions 25 disposed in each of pixels 10A, 10B, 10C, and 10D are gathered in the center of the unit pixel BP and electrically connected by a shared connection 32. One end of the shared connection 32 is directly connected to the surface of the FD region 25 of pixel 10A, for example. The other end of the shared connection 32 is directly connected across the pixel isolation region 16 to the surfaces of the FD regions 25 of pixels 10B, 10C, and 10D, respectively. In this example, the shared connection 32 is formed in a rectangular shape in plan view. Specifically, the shared connection 32 is formed in a square shape.

[0055] The shared connection portion 32 is formed of a gate electrode material, such as a polycrystalline silicon film. This polycrystalline silicon film contains impurities that reduce the resistance value at a high impurity density. For example, phosphorus, which is an n-type impurity, can be used as the impurity.

[0056] The shared connection portion 31 electrically connects one main electrode 204 of the FD conversion gain switching transistor 23 of the pixel 10A to one main electrode 204 of the reset transistor 24 of the pixel 10C. In other words, one end of the shared connection portion 31 is directly connected to the surface of one main electrode 204 of the FD conversion gain switching transistor 23. The other end of the shared connection portion 31 is directly connected to the surface of one main electrode 204 of the reset transistor 24 across the pixel isolation region 16.

[0057] The shared connection portion 31 also electrically connects one main electrode 204 of the amplification transistor 21 of pixel 10B to one main electrode 204 of the selection transistor 22 of pixel 10D. That is, one end of the shared connection portion 31 is directly connected to the surface of one main electrode 204 of the amplification transistor 21. The other end of the shared connection portion 31 is directly connected to the surface of one main electrode 204 of the selection transistor 22 across the pixel isolation region 16. In this example, the shared connection portion 31 is formed in a rectangular shape in plan view. Specifically, the shared connection portion 31 is formed in a rectangular shape. Like the shared connection portion 32, the shared connection portion 31 is formed from, for example, a gate electrode material.

[0058] A total of four base connection portions 27 are disposed in each of pixels 10A, 10B, 10C, and 10D, and are disposed at the four corners of the unit pixel BP. The base connection portions 27 are electrically connected to the base connection portions 27 of other unit pixels BP adjacent to the unit pixel BP via shared connection portions 33. The shared connection portions 33 are formed with a configuration similar to that of the shared connection portions 32 that connect the four FD regions 25.

[0059] 4, and as simply shown in Fig. 5, wiring 7 is disposed above the amplifying transistor 21 etc. of the pixel circuit 20, with an interlayer insulating film 6 interposed therebetween. The wiring 7 is connected to the gate electrode 203, the main electrode 204, the shared connection portion 31, the shared connection portion 32, the shared connection portion 33 etc. through connection holes 6H formed in the interlayer insulating film 6. As described above, for example, copper wiring is used as the wiring 7.

[0060] [Method of Manufacturing Solid-State Imaging Device 1] FIGS. 6 to 11 show an example of a method of manufacturing the solid-state imaging device 1 step by step.

[0061] First, a base 15 is prepared. As shown in Fig. 6, a p-type semiconductor region (p-type well region) 151 is formed in the base 15, and a photoelectric conversion element 11 is formed in a region where a pixel 10 is formed. The p-type semiconductor region 151 and the photoelectric conversion element 11 are each formed by, for example, introducing an impurity and activating the introduced impurity.

[0062] As shown in FIG. 7 , a pixel isolation region 16 and an element isolation region 26 are formed. The pixel isolation region 16 is formed in a region between the pixels 10 of the base 15. The pixel isolation region 16 is formed, for example, by forming a first groove 161 penetrating from the upper surface to the lower surface of the base 15 and embedding a first embedding member 162 in the first groove 161. The first groove 161 is formed by anisotropic etching such as reactive ion etching (RIE). The insulator 162A of the first embedding member 162 is formed by, for example, thermal oxidation, chemical vapor deposition (CVD), or the like. The embedding member 162B of the first embedding member 162 is formed by, for example, CVD, or the like.

[0063] On the other hand, the element isolation region 26 is formed on the main surface side of the base 15 in part of the pixel isolation region 16 and part of the p-type semiconductor region 151. The element isolation region 26 is formed by forming a second groove 261 from the upper surface to the lower surface side of the base 15 and embedding a second embedding member 262 in the second groove 261. The second groove 261 is formed shallower than the first groove 161. Anisotropic etching such as RIE is used to form the second groove 261. The second embedding member 262 is formed by CVD, for example.

[0064] 8 , a transfer gate electrode 205 is formed in a region surrounded by the pixel isolation region 16 and the element isolation region 26, in a region where the transfer transistor 12 is formed. The transfer gate electrode 205 includes a groove (reference numeral omitted) formed from the upper surface to the lower surface of the base 15, a buried member (reference numeral omitted) buried in the groove with a gate insulating film interposed therebetween, and a gate electrode connected to the buried member. Furthermore, a gate insulating film 202 and a gate electrode 203 are formed on the surface of the base 15 in each of the regions where the amplification transistor 21, the selection transistor 22, the FD conversion gain switching transistor 23, and the reset transistor 24 are formed.

[0065] As shown in FIG. 9 , a base connection portion 27 and an FD region 25 are formed in a region surrounded by the pixel isolation region 16 and the element isolation region 26, aligned with or along the gate width Wg direction of the amplification transistor 21. The base connection portion 27 is formed by implanting p-type impurities using photolithography and ion implantation. The FD region 25 is formed by implanting n-type impurities using photolithography and ion implantation. Although not shown in FIG. 9 , main electrodes 204 for the amplification transistor 21, selection transistor 22, FD conversion gain switching transistor 23, and reset transistor 24 are formed in the same process as the process for forming the FD region 25. By forming the main electrodes 204, the amplification transistor 21, selection transistor 22, FD conversion gain switching transistor 23, and reset transistor 24 are each formed. Note that the impurities may be introduced by solid-phase diffusion.

[0066] As shown in FIG. 10 , a shared connection portion 33 that connects the base connection portions 27 and a shared connection portion 32 that connects the FD regions 25 are formed. The shared connection portion 33 is formed, for example, from a polycrystalline silicon film that serves as a gate electrode material. The polycrystalline silicon film is formed, for example, by CVD, and p-type impurities are introduced into the polycrystalline silicon film. The p-type impurities are introduced by ion implantation or solid-phase diffusion. The shared connection portion 32 is formed, for example, by the same process as the polycrystalline silicon film of the shared connection portion 33. N-type impurities are introduced into this polycrystalline silicon film. Although not shown in FIG. 10 , the shared connection portion 31 that connects the main electrodes 204 is formed by the same process as the process that forms the shared connection portion 32.

[0067] An interlayer insulating film 6 is formed to cover the amplifying transistor 21, the selecting transistor 22, the FD conversion gain switching transistor 23, the reset transistor 24, the shared connecting portion 31, the shared connecting portion 32, and the shared connecting portion 33 (see FIG. 11). Subsequently, a connection hole 6H is formed in the interlayer insulating film 6, as shown in FIG.

[0068] 4 and 5, wiring 7 is formed in the interlayer insulating film 6. The wiring 7 is connected to each region through the connection hole 6H. When this series of steps is completed, the solid-state imaging device 1 according to the first embodiment is completed, and the manufacturing method is finished. Note that impurities may be introduced into the shared connection portion 31 and the shared connection portion 32, or the shared connection portion 33, for example, during the formation of the polycrystalline silicon film.

[0069] [Effects] As shown in FIGS. 2 to 5 , the solid-state imaging device 1 according to the first embodiment includes a pixel 10, a pixel isolation region 16, a transistor 200, an FD region 25, a transfer gate electrode 205, or a base connection portion 27. The pixel 10 is disposed on a first surface side of the base 15, which is the light incident side, and includes a photoelectric conversion element 11 that converts light into an electric charge. The pixel 10 is a "first pixel" according to the present technology and is any one of pixels 10A, 10B, 10C, and 10D. The photoelectric conversion element is a "first photoelectric conversion element" according to the present technology. The pixel isolation region 16 is formed in the thickness direction of the base 15 and, when viewed from a second surface side of the base 15 opposite the first surface, extends in a first direction and a second direction intersecting the first direction to surround the side periphery of the pixel 10, electrically and optically isolating the pixel 10 from other regions. The first direction is, for example, the direction of arrow X. The second direction is, for example, the direction of the arrow Y. The first direction and the second direction are the extension direction of the pixel isolation region 16 or the arrangement direction of the pixels 10, respectively. The transistor 200 is disposed on the second surface side of the base 15, which is surrounded by the pixel isolation region 16, at a position corresponding to the pixel 10, with the gate length direction oblique to the first direction or the second direction. The transistor 200 processes converted electric charges. The transistor 200 is a "first transistor" according to the present disclosure. In the first embodiment, the "first transistor" is the FD conversion gain switching transistor 23 disposed at a position corresponding to the pixel 10A, but it may be any of the amplification transistor 21, the selection transistor 22, and the reset transistor 24. The FD region 25 is disposed on the second surface of the base 15 at a position corresponding to the pixel 10, in the direction of the gate width Wg of the transistor 200. The FD region 25 is a "first FD region" according to the present technology. Similarly, the transfer gate electrode 205 is disposed in the gate width Wg direction of the transistor 200 on the second surface side of the base 15 at a position corresponding to the pixel 10. The transfer gate electrode 205 is a gate electrode of the transfer transistor 12 that transfers charges from the pixel 10 to the FD region 25. The transfer transistor 12 and the transfer gate electrode 205 are a "first transfer transistor" and a "first transfer gate electrode" according to the present technology. The base connection portion 27 supplies a voltage to the base 15.The substrate connection portion 27 is a "first substrate connection portion" according to the present technology. The first substrate connection portion is a well contact region. With this configuration, the transistor 200 is disposed in a region corresponding to the pixel 10 and surrounded by the pixel isolation region 16, with the gate length Lg direction at an angle, thereby ensuring a sufficient area for the transistor 200. More specifically, the lengths of the transistor 200 in the gate length Lg direction and the gate width Wg direction can be sufficiently ensured. This allows the transistor 200 to be constructed with excellent noise resistance, thereby improving the electrical reliability of the solid-state imaging device 1. Additionally, the pair of main electrodes 204 is not formed in the gate width Wg direction of the transistor 200. This region can be utilized as free space. The FD region 25, the transfer gate electrode 205, or the substrate connection portion 27 is disposed in this free space. Although all of these are disposed in the first embodiment, at least one of them may be disposed. This allows the region corresponding to the pixel 10 to be effectively utilized.

[0070] 2 and 3, in the solid-state imaging device 1, the FD region 25, the transfer gate electrode 205, or the base connecting portion 27 is disposed with the element isolation region 26 interposed between the transistor 200. Therefore, the isolation capability between the transistor 200 and the FD region 25, the transfer gate electrode 205, or the base connecting portion 27 can be improved compared to when the element isolation region 26 is not interposed.

[0071] 4 , in the solid-state imaging device 1, the pixel isolation region 16 includes a first groove 161 formed from the second surface toward the first surface of the base 15, and a first embedded member 162 embedded in the first groove 161. The element isolation region 26 includes a second groove 261 formed from the second surface toward the first surface of the base 15, and deeper than the first groove 161, and a second embedded member 262 embedded in the second groove 261. Therefore, in the element isolation region 26, the separation distance between elements can be increased in the thickness direction of the base 15, and the isolation capability between the transistor 200 and the FD region 25, the transfer gate electrode 205, or the base connection portion 27 can be further improved.

[0072] 2, 3, and 5, in the solid-state imaging device 1, the pixels 10 are partitioned by the pixel isolation region 16 and are formed in a rectangular shape when viewed from the second surface side. The pair of main electrodes 204 of the transistor 200 are arranged to coincide with, for example, a diagonal line D1-D1 of the rectangular shape of the pixel 10. The FD region 25, the transfer gate electrode 205, or the base connection portion 27 are arranged to coincide with, for example, another diagonal line D2-D2 that intersects with the diagonal line D1-D1, or along the diagonal line D2-D2. Therefore, the gate length Lg and gate width Wg of the transistor 200 are longer than when the gate length Lg direction is aligned with the extension direction of the pixel isolation region 16. This improves the noise resistance and electrical characteristics of the transistor 200.

[0073] In particular, in the solid-state imaging device 1, the direction of the gate length Lg of the transistor 200 is inclined at 45 degrees with respect to the first direction or the second direction, so that the gate length Lg and gate width Wg of the transistor 200 are both longest.

[0074] 2 to 5 , the solid-state imaging device 1 according to the first embodiment includes a pixel 10, a pixel isolation region 16, a transistor 200, an FD region 25, and a transfer gate electrode 205 or a base connection portion 27. The pixel 10 is adjacent to a "first pixel" according to the present technology in the first direction, is disposed on a first surface side of a base 15 with the pixel isolation region 16 interposed therebetween, and has a photoelectric conversion element 11 that converts light into electric charges. The pixel 10 is a "second pixel" according to the present technology; for example, if the "first pixel" is pixel 10A, the "second pixel" is pixel 10B. The photoelectric conversion element is a "second photoelectric conversion element" according to the present technology. The pixel isolation region 16 is formed in the thickness direction of the base 15 and extends in the first direction and a second direction intersecting the first direction when viewed from a second surface of the base 15 opposite the first surface, surrounding the lateral periphery of the pixel 10 and electrically and optically isolating the pixel 10 from other regions. The transistor 200 is disposed on the second surface of the base 15, surrounded by the pixel isolation region 16, at a position corresponding to the pixel 10, with its gate length direction oblique to the first direction or the second direction, and processes converted electric charges. The transistor 200 is a "second transistor" according to the present disclosure. In the first embodiment, for example, if the "first transistor" is the FD conversion gain switching transistor 23, the "second transistor" is the amplification transistor 21. The "second transistor" is formed in a shape that is linearly symmetrical with respect to the "first transistor," with the pixel isolation region 16 between the "first pixel" and the "second pixel" as the center. The FD region 25 is disposed in the gate width Wg direction of the transistor 200 on the second surface side of the base 15 at a position corresponding to the pixel 10. The FD region 25 is a "second FD region" according to the present technology. Similarly, the transfer gate electrode 205 is disposed in the gate width Wg direction of the transistor 200 on the second surface of the base 15 at a position corresponding to the pixel 10. The transfer gate electrode 205 is a gate electrode of the transfer transistor 12 that transfers charges from the pixel 10 to the FD region 25. The transfer transistor 12 and the transfer gate electrode 205 are a "second transfer transistor" and a "second transfer gate electrode" according to the present technology. The base connection portion 27 supplies a voltage to the base 15. The base connection portion 27 is a "second base connection portion" according to the present technology.With this configuration, the transistor 200 is disposed in a region corresponding to the pixel 10 and surrounded by the pixel isolation region 16, with the gate length Lg direction oblique, thereby ensuring a sufficient area for the transistor 200. More specifically, the lengths of the transistor 200 in the gate length Lg direction and the gate width Wg direction can be sufficiently ensured. This allows the transistor 200 to be constructed with excellent noise resistance, thereby improving the electrical reliability of the solid-state imaging device 1. Additionally, the pair of main electrodes 204 is not formed in the gate width Wg direction of the transistor 200. This region can be utilized as free space. The FD region 25, the transfer gate electrode 205, or the base connection portion 27 are disposed in this free space. In the first embodiment, all of these are disposed, but at least one of them may be disposed. This allows the region corresponding to the pixel 10 to be effectively utilized. Furthermore, the "second transistor" is formed in a shape that is linearly symmetrical with respect to the "first transistor," thereby simplifying the layout of the pixel 10 and the transistor 200. In particular, between adjacent pixels 10, the FD regions 25 or the base connection portions 27 can be disposed close to each other. This enables a shared connection using the shared connection portion 32 or the shared connection portion 33, and the area required for arranging the transistor 200 in the pixel 10 can be sufficiently secured.

[0075] The effects described here can be similarly obtained for the "third pixel" and "third transistor" and the "fourth pixel" and "fourth transistor" according to the present technology. The "third pixel" and "third transistor" are, for example, the pixel 10C and the reset transistor 24. The "fourth pixel" and "fourth transistor" are, for example, the pixel 10D and the selection transistor 22.

[0076] 2 to 5 , in the solid-state imaging device 1, one of the pair of main electrodes 204 of one transistor 200 and one of the pair of main electrodes 204 of another adjacent transistor 200 are shared by a shared connection portion 31. Specifically, the main electrode 204 of the FD conversion gain switching transistor 23 and the main electrode 204 of the reset transistor 24 are shared by the shared connection portion 31. Similarly, the main electrode 204 of the amplification transistor 21 and the main electrode 204 of the selection transistor 22 are shared by the shared connection portion 31. The shared connection portion 31 is directly connected to the surface of the main electrode 204. With this configuration, the main electrodes 204 of the transistors 200 can be electrically connected by the shared connection portion 31 without forming wiring and connection holes that straddle the pixel isolation region 16. In a plan view, the shared connection portion 31 is disposed so as to overlap the main electrodes 204, and an alignment margin dimension, unlike that required for connection holes, is not required for the connection between the two. Therefore, the area on the main surface of the base 15 connecting the main electrodes 204 does not increase, so a sufficient area can be secured for arranging the transistor 200 in the pixel 10. In addition, since a sufficient area can be secured for arranging the transistor 200 in the pixel 10, the gate length Lg and gate width Wg of the transistor 200 can be increased. This makes it possible to construct a transistor 200 with excellent noise resistance, thereby improving the electrical reliability of the solid-state imaging device 1.

[0077] Furthermore, in the solid-state imaging device 1, adjacent FD regions 25 are shared by a shared connection portion 32, and adjacent base connection portions 27 are shared by a shared connection portion 33. The shared connection portion 32 is directly connected to the surface of the FD regions 25, and the shared connection portion 33 is directly connected to the surface of the base connection portion 27. With this configuration, the FD regions 25 can be electrically connected by the shared connection portion 32 without forming wiring and connection holes that straddle the pixel isolation region 16. In a plan view, the shared connection portion 32 is disposed overlapping the FD regions 25, and the connection between the two does not require an alignment margin, as is the case with connection holes. Therefore, the area on the main surface of the base 15 that connects the FD regions 25 does not increase. In addition, because the connection is not via wiring 7, the parasitic capacitance added to the FD regions 25 can be reduced. Similarly, the base connection portions 27 can be electrically connected by the shared connection portion 33 without forming wiring and connection holes that straddle the pixel isolation region 16. In a plan view, the shared connection portion 33 is disposed so as to overlap the base connection portion 27, and no alignment margin, such as a connection hole, is required for the connection between the two. Therefore, the area on the main surface of the base 15 connecting the base connection portions 27 does not increase. Therefore, a sufficient area is ensured in the pixel 10 for arranging the transistor 200, and the gate length Lg and gate width Wg of the transistor 200 can be increased. In other words, a transistor 200 with excellent noise resistance can be constructed, thereby improving the electrical reliability of the solid-state imaging device 1.

[0078] 2 to 5, in the solid-state imaging device 1, one transistor 200 is provided per pixel 10. One FD region 25 is provided for multiple pixels 10, and the FD region 25 is shared by multiple pixels 10. The same applies to the transfer gate electrode 205 and the base connection portion 27. This allows the area of ​​the element isolation region 26 that separates the FD region 25, the transfer gate electrode 205, or the base connection portion 27 from other regions to be reduced, thereby enabling further miniaturization of the pixels 10.

[0079] 2. Second Embodiment A solid-state imaging device 1 according to a second embodiment of the present disclosure will be described using Figures 12 and 13. Note that in the second embodiment and the following embodiments, components that are the same as or substantially the same as components of the solid-state imaging device 1 according to the first embodiment are denoted by the same reference numerals, and duplicated descriptions will be omitted.

[0080] [Configuration of Solid-State Imaging Device 1] Fig. 12 shows an example of a specific planar configuration of the pixel 10 and pixel circuit 20 of the solid-state imaging device 1 according to the second embodiment. Fig. 13 shows a vertical cross-sectional configuration of a portion of the pixel 10 and pixel circuit 20 (a cross-section taken along the B-B cutting line shown in Fig. 12).

[0081] As shown in FIGS. 12 and 13, in the solid-state imaging device 1 according to the second embodiment, a fin structure is adopted for the transistor 200 in the solid-state imaging device 1 according to the first embodiment.

[0082] More specifically, the amplification transistor 21, the selection transistor 22, the FD conversion gain switching transistor 23, and the reset transistor 24 are configured in a fin structure. The fin structure is a structure in which the end of the gate electrode 203 in the gate width Wg direction extends from the second surface to the first surface of the base 15. Here, both ends of the gate electrode 203 in the gate width Wg direction are embedded in grooves formed in the base 15 and extend into the base 15. Both ends of the gate electrode 203 in the gate width Wg direction are formed exactly along the element isolation region 26, and the gate width Wg of the gate electrode 203 is defined by the element isolation region 26.

[0083] Components other than the above-mentioned components are the same or substantially the same as the components of the solid-state imaging device 1 according to the first embodiment. The fin-type structure may be adopted for one selected from the amplifying transistor 21, the selecting transistor 22, the FD conversion gain switching transistor 23, and the reset transistor 24. For example, the fin-type structure may be adopted for only the amplifying transistor 21.

[0084] [Operational Effects] According to the solid-state imaging device 1 of the second embodiment, it is possible to obtain the same operational effects as those obtained by the solid-state imaging device 1 of the first embodiment.

[0085] Furthermore, in the solid-state imaging device 1, as shown in FIGS. 12 and 13 , the transistor 200 has a fin-type structure in which the end of the gate electrode 203 in the gate width Wg direction extends from the second surface to the first surface of the base 15. The fin-type structure allows the transistor 200 to maintain the gate width Wg dimension in the thickness direction of the base 15. With this configuration, the transistor 200 has an obliquely oriented gate length Lg direction, thereby increasing the gate length Lg dimension and effectively suppressing or preventing the occurrence of short channel effects or noise. In particular, the transistor 200 can effectively suppress or prevent the occurrence of RTN (Random Telegraph Signal) noise. Furthermore, the fin-type structure allows the gate width Wg dimension of the transistor 200 to be expanded, improving the transconductance (gm). Furthermore, the improved transconductance of the transistor 200 allows for an increased operating speed of the pixel circuit 200.

[0086] 3. Third Embodiment A solid-state imaging device 1 according to a third embodiment of the present disclosure will be described with reference to FIGS.

[0087] [Configuration of solid-state imaging device 1] (1) Circuit configuration of pixel 10 and pixel circuit 20 of solid-state imaging device 1 Figure 14 shows an example of the circuit configuration of the pixel 10 and pixel circuit 20 that constitute the solid-state imaging device 1 related to the third embodiment.

[0088] 14 , in the pixel circuit 20 of the solid-state imaging device 1, the amplification transistor 21 includes an amplification transistor 21A and an amplification transistor 21B, and the selection transistor 22 includes a selection transistor 22A and a selection transistor 22B. The amplification transistor 21A and the amplification transistor 21B are electrically connected in parallel. Similarly, the selection transistor 22A and the selection transistor 22B are electrically connected in parallel. The amplification transistor 21A and the selection transistor 22A are electrically connected in series. Similarly, the amplification transistor 21B and the selection transistor 22B are electrically connected in series.

[0089] (2) Layout Configuration of Pixel 10 and Pixel Circuit 20 Fig. 15 shows an example of a specific planar configuration of the pixel 10 and pixel circuit 20. As shown in Fig. 15, in the third embodiment, an amplifier transistor 21B of the amplifier transistor 21 and a select transistor 22B of the select transistor 22 are disposed at a position corresponding to the pixel 10A. The amplifier transistor 21B and the select transistor 22B are disposed along the diagonal line D1-D1 (see Fig. 2). The gate length Lg of the amplifier transistor 21B is longer than the gate length Lg of the select transistor 22B.

[0090] On the other hand, an amplifying transistor 21A of the amplifying transistor 21 and a selecting transistor 22A of the selecting transistor 22 are disposed at a position corresponding to pixel 10B. The amplifying transistor 21A and the selecting transistor 22A are disposed along the diagonal line D2-D2 (see FIG. 2). The gate length Lg of the amplifying transistor 21A is longer than the gate length Lg of the selecting transistor 22A. The amplifying transistor 21A and the selecting transistor 22A are formed in line symmetry with respect to the amplifying transistor 21B and the selecting transistor 22B, with the pixel isolation region 16 disposed between the pixels 10A and 10B as the center.

[0091] Furthermore, a reset transistor 24 is disposed at a position corresponding to pixel 10C. The reset transistor 24 is disposed so as to coincide with the diagonal line D2-D2 (see FIG. 2). A FD conversion gain switching transistor 23 is disposed at a position corresponding to pixel 10D. The FD conversion gain switching transistor 23 is disposed so as to coincide with the diagonal line D1-D1 (see FIG. 2). The FD conversion gain switching transistor 23 is formed in a shape that is line-symmetrical with respect to the reset transistor 24, with the pixel isolation region 16 disposed between the pixel 10C and the pixel 10D as the center.

[0092] Furthermore, the FD conversion gain switching transistor 23 is formed in a shape that is substantially line-symmetrical with respect to the amplifier transistor 21B and the selection transistor 22B, with the pixel isolation region 16 disposed between the pixel 10A and the pixel 10C as the center. Similarly, the reset transistor 24 is formed in a shape that is substantially line-symmetrical with respect to the amplifier transistor 21A and the selection transistor 22A, with the pixel isolation region 16 disposed between the pixel 10B and the pixel 10D as the center.

[0093] In the third embodiment, the main electrode 204 of the FD conversion gain switching transistor 23 and the main electrode 204 of the reset transistor 24 are connected by a wiring 7 (see FIG. 4). Here, a parasitic capacitance due to the wiring 7 is intentionally formed.

[0094] The components other than those described above are the same or substantially the same as the components of the solid-state imaging device 1 according to the first embodiment.

[0095] [Operational Effects] According to the solid-state imaging device 1 of the third embodiment, it is possible to obtain the same operational effects as those obtained by the solid-state imaging device 1 of the first embodiment.

[0096] 14 and 15 , in the solid-state imaging device 1, the amplification transistor 21 of the pixel circuit 20 is configured with an amplification transistor 21A and an amplification transistor 21B electrically connected in parallel. In addition, the selection transistor 22 of the pixel circuit 20 is configured with a selection transistor 22A and a selection transistor 22B electrically connected in parallel. The amplification transistor 21A and the selection transistor 22A are disposed at a position corresponding to the pixel 10B. The amplification transistor 21B and the selection transistor 22B are disposed at a position corresponding to the pixel 10A. Here, the gate length Lg of the amplification transistor 21A and the amplification transistor 21B is formed longer than the gate length Lg of the selection transistor 22A and the selection transistor 22B. This improves the noise resistance of the amplification transistor 21 configured with the amplification transistor 21A and the amplification transistor 21B.

[0097] 4. Fourth Embodiment A solid-state imaging device 1 according to a fourth embodiment of the present disclosure will be described with reference to FIGS.

[0098] [Configuration of Solid-State Imaging Device 1] Fig. 16 shows an example of a specific planar configuration of the pixel 10 and pixel circuit 20. Fig. 17 shows a longitudinal cross-sectional configuration of a portion of the pixel 10 and pixel circuit 20 (a cross-section taken along the CC cutting line shown in Fig. 16). Fig. 18 shows a longitudinal cross-sectional configuration of another portion of the pixel 10 and pixel circuit 20 (a cross-section taken along the D-D cutting line shown in Fig. 16).

[0099] 16 to 18, in the solid-state imaging device 1 according to the fourth embodiment, a plurality of transfer gate electrodes 205 of the transfer transistor 12 (see FIG. 1) are arranged. To explain in more detail, a transistor 200 is arranged at a position corresponding to one pixel 10, and two transfer gate electrodes 205 are also arranged here. In plan view, the two transfer gate electrodes 205 are arranged along the diagonal line D2-D2, sandwiching the FD region 25 therebetween. The planar shape of the transfer gate electrode 205 is rectangular, specifically, square.

[0100] Here, the pixel 10 is the pixel 10A, the pixel 10B, the pixel 10C, or the pixel 10D. The transistor 200 is an amplification transistor 21, a selection transistor 22, an FD conversion gain switching transistor 23, or a reset transistor 24.

[0101] The components other than those described above are the same or substantially the same as the components of the solid-state imaging device 1 according to the first embodiment.

[0102] [Operational Effects] According to the solid-state imaging device 1 of the fourth embodiment, it is possible to obtain the same operational effects as those obtained by the solid-state imaging device 1 of the first embodiment.

[0103] 16 to 18, in the solid-state imaging device 1, a plurality of transfer gate electrodes 205 are disposed at positions corresponding to the pixels 10. This increases the effective gate width Wg of the transfer gate electrodes 205 of the transfer transistors 12, thereby improving the efficiency of reading out charges from the pixels 10 to the pixel circuits 20.

[0104] [First Modification] A solid-state imaging device 1 according to a first modification of the fourth embodiment will be described with reference to Figures 19 to 21. Figure 19 shows an example of a specific planar configuration of the pixel 10 and pixel circuit 20. Figure 20 shows a longitudinal cross-sectional configuration of a portion of the pixel 10 and pixel circuit 20 (a cross-section taken along the E-E cutting line shown in Figure 19). Figure 21 shows a longitudinal cross-sectional configuration of another portion of the pixel 10 and pixel circuit 20 (a cross-section taken along the F-F cutting line shown in Figure 19).

[0105] 19 to 21, in the solid-state imaging device 1 according to the first modification of the fourth embodiment, the transfer gate electrode 205 of the transfer transistor 12 (see FIG. 1) is formed in a rectangular shape in a plan view. To explain in more detail, a transistor 200 is disposed at a position corresponding to one pixel 10, and one transfer gate electrode 205 is also disposed therein. In a plan view, the transfer gate electrode 205 is formed in a rectangular shape with its long sides aligned along the diagonal line D2-D2 and its short sides aligned along the diagonal line D1-D1. The FD region 25 is disposed opposite the central portion of the transfer gate electrode 205.

[0106] The components other than those described above are the same or substantially the same as the components of the solid-state imaging device 1 according to the fourth embodiment.

[0107] [Operational Effects] According to the solid-state imaging device 1 of the first modified example of the fourth embodiment, it is possible to obtain operational effects similar to those obtained by the solid-state imaging device 1 of the fourth embodiment.

[0108] 19 to 21 , in the solid-state imaging device 1, a transfer gate electrode 205 having a rectangular shape in a plan view is disposed at a position corresponding to the pixel 10. This increases the effective gate width Wg of the transfer gate electrode 205 of the transfer transistor 12, thereby improving the efficiency of reading out electric charges from the pixel 10 to the pixel circuit 20.

[0109] [Second Modification] A solid-state imaging device 1 according to a second modification of the fourth embodiment will be described with reference to Figures 22 to 24. Figure 22 shows an example of a specific planar configuration of the pixel 10 and pixel circuit 20. Figure 23 shows a longitudinal cross-sectional configuration of a portion of the pixel 10 and pixel circuit 20 (a cross-section taken along the G-G cutting line shown in Figure 22). Figure 24 shows a longitudinal cross-sectional configuration of another portion of the pixel 10 and pixel circuit 20 (a cross-section taken along the H-H cutting line shown in Figure 22).

[0110] As shown in FIGS. 22 to 24 , in a solid-state imaging device 1 according to a second modification of the fourth embodiment, a plurality of transfer gate electrodes 205 of the transfer transistor 12 (see FIG. 1 ) are disposed. More specifically, a transistor 200 is disposed at a position corresponding to one pixel 10, and two transfer gate electrodes 205 are also disposed therein. In plan view, the two transfer gate electrodes 205 are disposed along the diagonal line D2-D2, sandwiching the FD region 25 therebetween. The planar shape of the transfer gate electrodes 205 here is formed in a triangular shape. Furthermore, one of the two transfer gate electrodes 205 is formed in a shape that is line-symmetrical with respect to the other transfer gate electrode 205, with the diagonal line D1-D1 as the center.

[0111] Components other than those described above are the same or substantially the same as the components of the solid-state imaging device 1 according to the fourth embodiment. Note that the planar shape of the transfer gate electrode 205 may be a circle, an ellipse, or a polygon having pentagons or more sides, in addition to the above.

[0112] [Operational Effects] According to the solid-state imaging device 1 of the second modified example of the fourth embodiment, it is possible to obtain operational effects similar to those obtained by the solid-state imaging device 1 of the fourth embodiment.

[0113] 22 to 24, in the solid-state imaging device 1, a plurality of transfer gate electrodes 205 are disposed at positions corresponding to the pixels 10. This increases the effective gate width Wg of the transfer gate electrodes 205 of the transfer transistors 12, thereby improving the efficiency of reading out charges from the pixels 10 to the pixel circuits 20.

[0114] 5. Fifth Embodiment A solid-state imaging device 1 according to a fifth embodiment of the present disclosure will be described with reference to FIGS. 25 and 26. FIG.

[0115] [Configuration of Solid-State Imaging Device 1] Fig. 25 shows an example of a specific planar configuration of the pixel 10 and the pixel circuit 20. Fig. 26 shows a vertical cross-sectional configuration of a portion of the pixel 10 and the pixel circuit 20 (a cross-section taken along the II cutting line shown in Fig. 25).

[0116] 25 and 26, in the solid-state imaging device 1 according to the fifth embodiment, the pixels 10 shown in FIG. 2 and described in the solid-state imaging device 1 according to the first embodiment are repeatedly arranged in the directions of the arrows X and Y. More specifically, the pixels 10 are not formed in an axisymmetric shape in the arrangement direction. That is, in the plurality of arranged pixels 10, transistors 200 are arranged whose gate lengths Lg directions are aligned with the diagonal line D1-D1. In other words, the gate lengths Lg directions of the transistors 200 of the plurality of arranged pixels 10 are all in the same direction.

[0117] Furthermore, the main electrodes 204 of the transistors 200, the FD regions 25, and the base connection portions 27 are electrically connected to each other by wiring 7. The shared connection portions 31, 32, and 33 of the solid-state imaging device 1 according to the first embodiment are not formed.

[0118] Components other than the above components are the same or substantially the same as the components of the solid-state imaging device 1 according to the first embodiment. Note that a plurality of pixels 10 may be arranged, each having the gate length Lg direction of the transistor 200 aligned with the diagonal line D2-D2.

[0119] [Operational Effects] According to the solid-state imaging device 1 of the fifth embodiment, it is possible to obtain the same operational effects as those obtained by the solid-state imaging device 1 of the first embodiment.

[0120] 25 and 26 , in the solid-state imaging device 1, transistors 200 are arranged in each of a plurality of arranged pixels 10, with the gate lengths Lg aligned in the same direction. The main electrodes 204, the FD regions 25, and the base connection portions 27 of the transistors 200 are electrically connected to each other by wiring 7. With this configuration, it is possible to omit the components of the shared connection portion 31 connecting the main electrodes 204, the shared connection portion 32 connecting the FD regions 25, and the shared connection portion 33 connecting the base connection portions 27. This simplifies the manufacturing process for the shared connection portion 31, the shared connection portion 32, and the shared connection portion 33.

[0121] 6. Sixth Embodiment A solid-state imaging device 1 according to a sixth embodiment of the present disclosure will be described with reference to FIG.

[0122] [Configuration of Solid-State Imaging Device 1] Fig. 27 shows an example of a specific planar configuration of the pixel 10 and the pixel circuit 20. As shown in Fig. 27, in the solid-state imaging device 1 according to the sixth embodiment, the pixel circuit 20 includes two amplification transistors 21, a selection transistor 22, and a reset transistor 24 electrically connected in parallel.

[0123] One of the two amplifier transistors 21 is disposed at a position corresponding to pixel 10A. The other of the two amplifier transistors 21 is disposed at a position corresponding to pixel 10B adjacent to pixel 10A in the direction of arrow X. The other amplifier transistor 21 is formed in a shape that is linearly symmetrical to one amplifier transistor 21, with the pixel isolation region 16 between pixel 10A and pixel 10B as the center.

[0124] On the other hand, a reset transistor 24 is disposed at a position corresponding to pixel 10C adjacent to pixel 10A in the direction indicated by the arrow Y. The reset transistor 24 is formed in a shape that is line-symmetrical with respect to one of the amplifier transistors 21, with the pixel isolation region 16 between pixel 10A and pixel 10C as the center. A selection transistor 22 is disposed at a position corresponding to pixel 10D adjacent to pixel 10B in the direction opposite to the direction indicated by the arrow Y. The selection transistor 22 is formed in a shape that is line-symmetrical with respect to the other amplifier transistor 21, with the pixel isolation region 16 between pixel 10B and pixel 10D as the center.

[0125] The FD region 25 and the gate electrode 203 of the amplifier transistor 21 , the main electrode 204 of the amplifier transistor 21 and the main electrode 204 of the selection transistor 22 , etc. are electrically connected by wiring 7 .

[0126] The components other than those described above are the same or substantially the same as the components of the solid-state imaging device 1 according to the first embodiment.

[0127] [Operational Effects] According to the solid-state imaging device 1 of the sixth embodiment, it is possible to obtain operational effects similar to those obtained by the solid-state imaging device 1 of the first embodiment.

[0128] 27 , in the solid-state imaging device 1, amplification transistors 21 electrically connected in parallel are disposed at positions corresponding to pixels 10A and 10B. A reset transistor 24 is disposed at a position corresponding to pixel 10C disposed adjacent to pixel 10A. A selection transistor 22 is disposed at a position corresponding to pixel 10D disposed adjacent to pixel 10B. Therefore, the pixels 10 and the transistors 200 are disposed at positions suitable for the connection locations, making it easier to make connections using the wiring 7. In addition, the wiring length of the wiring 7 is shortened, so the parasitic capacitance added to the wiring 7 can be reduced.

[0129] 7. Seventh Embodiment A solid-state imaging device 1 according to a seventh embodiment of the present disclosure will be described with reference to FIG.

[0130] [Configuration of Solid-State Imaging Device 1] Fig. 28 shows an example of a specific planar configuration of the pixel 10 and the pixel circuit 20. As shown in Fig. 28, in the solid-state imaging device 1 according to the seventh embodiment, similar to the solid-state imaging device 1 according to the sixth embodiment, the pixel circuit 20 includes two amplification transistors 21, a selection transistor 22, and a reset transistor 24 electrically connected in parallel.

[0131] One of the two amplifier transistors 21 is disposed at a position corresponding to pixel 10A. The other of the two amplifier transistors 21 is disposed at a position corresponding to pixel 10B adjacent to pixel 10A in the direction of arrow X. The other amplifier transistor 21 is formed in a shape that is linearly symmetrical to one amplifier transistor 21, with the pixel isolation region 16 between pixel 10A and pixel 10B as the center.

[0132] On the other hand, a reset transistor 24 is disposed at a position corresponding to pixel 10C adjacent to pixel 10A in the direction of the arrow Y. The reset transistor 24 is formed in a shape that is line-symmetrical with respect to one of the amplifier transistors 21, with the pixel isolation region 16 between pixel 10A and pixel 10C as the center. A selection transistor 22 is disposed at a position corresponding to pixel 10D adjacent to pixel 10B in the direction of the arrow Y. The selection transistor 22 is formed in a shape that is line-symmetrical with respect to the other amplifier transistor 21, with the pixel isolation region 16 between pixel 10B and pixel 10D as the center.

[0133] The FD region 25 and the gate electrode 203 of the amplifier transistor 21 , the main electrode 204 of the amplifier transistor 21 and the main electrode 204 of the selection transistor 22 , etc. are electrically connected by wiring 7 .

[0134] The components other than those described above are the same or substantially the same as the components of the solid-state imaging device 1 according to the sixth embodiment.

[0135] [Operational Effects] According to the solid-state imaging device 1 of the seventh embodiment, it is possible to obtain operational effects similar to those obtained by the solid-state imaging device 1 of the first embodiment.

[0136] 8. Eighth Embodiment A solid-state imaging device 1 according to an eighth embodiment of the present disclosure will be described with reference to Figs. 29 to 31. [Configuration of Solid-State Imaging Device 1] Fig. 29 shows an example of a specific planar configuration of the pixel 10 and pixel circuit 20. Fig. 30 shows a longitudinal cross-sectional configuration of a portion of the pixel 10 and pixel circuit 20 (a cross-section taken along the J-J cutting line shown in Fig. 29). Fig. 31 shows an array layout configuration of the unit pixel BP shown in Fig. 29 and the surrounding pixels 10 (or unit pixels BP).

[0137] 29 to 31 , in the solid-state imaging device 1 according to the eighth embodiment, similarly to the solid-state imaging device 1 according to the first embodiment, the unit pixel BP includes a pixel 10A, a pixel 10B, a pixel 10C, and a pixel 10D. An FD conversion gain switching transistor 23 is disposed at a position corresponding to the pixel 10A. An amplification transistor 21 is disposed at a position corresponding to the pixel 10B. A reset transistor 24 is disposed at a position corresponding to the pixel 10C. A selection transistor 22 is disposed at a position corresponding to the pixel 10D.

[0138] The main electrode 204 of the amplification transistor 21 and the main electrode of the selection transistor 22 are electrically connected by a shared connection part 31. The main electrode 204 of the FD conversion gain switching transistor 23 and the main electrode 204 of the reset transistor 204 are electrically connected by a shared connection part 31.

[0139] As shown in FIG. 30 , the shared connection portion 31 includes a shared groove 311 and a connecting conductor 312. The shared groove 311 is formed as a stop hole dug between the main electrodes 204 from the upper surface (second surface) of the pixel isolation region 16 toward the lower surface (first surface). The depth of the shared groove 311 is formed, for example, to be approximately the same as the junction depth of the main electrode 204. Here, the depth of the shared groove 311 is formed shallower than the depth of the second groove 261 of the element isolation region 26. The connecting conductor 312 is buried in the shared groove 311. The connecting conductor 312 is directly connected to the side surface of the main electrode 204. The connecting conductor 312 is formed of a gate electrode material, for example, a polycrystalline silicon film. This polycrystalline silicon film contains impurities that reduce resistance at a high impurity density. For example, phosphorus, an n-type impurity, can be used as the impurity.

[0140] Similar to the shared connection part 31, the shared connection part 32 includes a shared groove 321 and a connection conductor 322. Similar to the shared connection part 31, the shared connection part 33 includes a shared groove 331 and a connection conductor 332. Here, when the connection conductor 332 is formed of, for example, a polycrystalline silicon film, the polycrystalline silicon film contains a high impurity density of p-type impurities that improve the resistance value.

[0141] The components other than those described above are the same or substantially the same as the components of the solid-state imaging device 1 according to the first embodiment.

[0142] [Operational Effects] According to the solid-state imaging device 1 of the eighth embodiment, it is possible to obtain operational effects similar to those obtained by the solid-state imaging device 1 of the first embodiment.

[0143] 29 to 31 , the solid-state imaging device 1 also includes a shared connection portion 31. The shared connection portion 31 includes a shared groove 311 and a connection conductor 312 embedded in the shared groove 311. This configuration allows electrical connection between the main electrodes 204 of the transistors 200 without forming wiring or connection holes spanning the pixel isolation region 16. This effectively eliminates the area on the main surface of the base 15 connecting the main electrodes 204, ensuring sufficient area for arranging the transistors 200 in the pixel 10. Additionally, the shared connection portion 31 is directly connected to the side surface of the main electrode 204 of the transistor 200. In other words, the area connecting the shared connection portion 31 and the main electrode 204 is secured in the direction indicated by the arrow Z, and is not substantially required on the main surface of the base 15. Furthermore, the solid-state imaging device 1 also includes, in addition to the shared connection portion 31, a shared connection portion 32 connecting the FD regions 25 and a shared connection portion 33 connecting the base connection portions 27. Therefore, the same effects as those obtained by the shared connection portion 31 can be obtained.

[0144] 9. Ninth Embodiment A solid-state imaging device 1 according to a ninth embodiment of the present disclosure will be described with reference to Fig. 32 and Fig. 33. [Configuration of Solid-State Imaging Device 1] Fig. 32 shows an example of a specific planar configuration of the pixel 10 and pixel circuit 20. Fig. 33 shows a vertical cross-sectional configuration of a portion of the pixel 10 and pixel circuit 20 (a cross-section taken along the K-K cutting line shown in Fig. 30).

[0145] 32 and 33 , the solid-state imaging device 1 according to the ninth embodiment does not include the shared connection portion 31, the shared connection portion 32, and the shared connection portion 33 that are included in the solid-state imaging device 1 according to the eighth embodiment. The wiring 7 is directly connected to the main electrode 204, the FD region 25, the base connection portion 27, etc. of the transistor 200.

[0146] The components other than those described above are the same or substantially the same as the components of the solid-state imaging device 1 according to the first embodiment.

[0147] [Operational Effects] According to the solid-state imaging device 1 of the ninth embodiment, it is possible to obtain the same operational effects as those obtained by the solid-state imaging device 1 of the first embodiment.

[0148] 32 and 33 , in the solid-state imaging device 1, the wiring 7 is connected to the main electrode 204 of the transistor 200, the FD region 25, the base connection portion 27, etc. In particular, the FD regions 25 gathered in the center of the plurality of pixels 10 are not shared, but are individually connected to the wiring 7 without being provided with the shared connection portion 32 of the solid-state imaging device 1 according to the eighth embodiment. This makes it possible to reduce the parasitic capacitance generated between the FD region 25 and, for example, the transfer gate electrode 205, thereby improving the efficiency of reading out charges from the pixels 10 to the pixel circuit 20.

[0149] 34 to 37, a solid-state imaging device 1 according to a tenth embodiment of the present disclosure will be described. In the tenth embodiment, an example of construction of the unit pixel BP of the solid-state imaging device 1 will be described.

[0150] [Configuration of Solid-State Imaging Device 1] Fig. 34 shows an example of a specific planar configuration of the pixel 10 and pixel circuit 20. As shown in Fig. 34, in the solid-state imaging device 1 according to the tenth embodiment, a unit pixel BP is constructed by a total of three pixels 10, namely, pixel 10A, pixel 10B, and pixel 10C, which are arranged in the direction indicated by the arrow Y in the solid-state imaging device 1 according to the fifth embodiment. A reset transistor 24 is disposed at a position corresponding to pixel 10A. An amplifier transistor 21 is disposed at a position corresponding to pixel 10B. A selection transistor 22 is disposed at a position corresponding to pixel 10C. The reset transistor 24, amplifier transistor 21, and selection transistor 22 are each disposed such that the direction of the gate length Lg coincides with the diagonal line D1-D1 (see Fig. 2).

[0151] That is, the pixels 10A, 10B, and 10C that form the unit pixel BP are repeatedly arranged in the direction of the arrow X. The unit pixels BP are repeatedly arranged in the directions of the arrow X and the arrow Y.

[0152] The components other than those described above are the same or substantially the same as the components of the solid-state imaging device 1 according to the fifth embodiment.

[0153] [Operational Effects] According to the solid-state imaging device 1 of the tenth embodiment, it is possible to obtain the same operational effects as those obtained by the solid-state imaging device 1 of the fifth embodiment.

[0154] [First Modification] Fig. 35 shows an example of a specific planar configuration of the pixel 10 and pixel circuit 20 of a solid-state imaging device 1 according to a first modification of the tenth embodiment. As shown in Fig. 35, in the solid-state imaging device 1 according to the first modification, a unit pixel BP is formed by a total of four pixels 10: pixel 10A, pixel 10B, pixel 10C, and pixel 10D, which are arranged in the direction indicated by the arrow Y. A reset transistor 24 is disposed at a position corresponding to pixel 10A. An FD conversion gain switching transistor 23 is disposed at a position corresponding to pixel 10B. An amplifier transistor 21 is disposed at a position corresponding to pixel 10C. A selection transistor 22 is disposed at a position corresponding to pixel 10D. The reset transistor 24, FD conversion gain switching transistor 23, amplifier transistor 21, and selection transistor 22 are each disposed such that the gate length Lg direction is aligned with the diagonal line D1-D1 (see Fig. 2).

[0155] That is, the pixels 10A, 10B, 10C, and 10D that constitute the unit pixel BP are repeatedly arranged in the direction of the arrow X. The unit pixels BP are repeatedly arranged in the directions of the arrow X and the arrow Y.

[0156] The components other than those described above are the same or substantially the same as the components of the solid-state imaging device 1 according to the fifth embodiment.

[0157] [Operational Effects] According to the solid-state imaging device 1 of the first modified example of the tenth embodiment, it is possible to obtain operational effects similar to those obtained by the solid-state imaging device 1 of the fifth embodiment.

[0158] 36 shows an example of a specific planar configuration of the pixels 10 and pixel circuits 20 of a solid-state imaging device 1 according to a second modification of the tenth embodiment. As shown in Fig. 36, in the solid-state imaging device 1 according to the second modification, a unit pixel BP is constructed by a total of eight pixels 10, pixels 10A to 10H, which are arranged in the directions of arrows X and Y.

[0159] The pixel 10A and the pixel 10B are arranged adjacent to each other in the direction of the arrow X. A reset transistor 24 is arranged at a position corresponding to each of the pixel 10A and the pixel 10B. The pixel 10C and the pixel 10D are arranged adjacent to each other in the direction of the arrow X, and are further arranged adjacent to the pixels 10A and the pixel 10B in the direction of the arrow Y. An FD conversion gain switching transistor 23 is arranged at a position corresponding to each of the pixel 10C and the pixel 10D. The pixel 10E and the pixel 10F are arranged adjacent to each other in the direction of the arrow X, and are further arranged adjacent to the pixels 10C and the pixel 10D in the direction of the arrow Y. An amplifier transistor 21 is arranged at a position corresponding to each of the pixel 10E and the pixel 10F. The pixel 10G and the pixel 10H are arranged adjacent to each other in the direction of the arrow X, and are further arranged adjacent to the pixels 10E and the pixel 10F in the direction of the arrow Y. A selection transistor 22 is disposed at a position corresponding to each of the pixels 10G and 10H. The reset transistor 24, the FD conversion gain switching transistor 23, the amplification transistor 21, and the selection transistor 22 are each disposed with the gate length Lg direction aligned with the diagonal line D1-D1 (see FIG. 2).

[0160] That is, the pixels 10A to 10H that form the unit pixel BP are repeatedly arranged in the direction of the arrow X. The unit pixels BP are repeatedly arranged in the directions of the arrow X and the arrow Y.

[0161] The components other than those described above are the same or substantially the same as the components of the solid-state imaging device 1 according to the fifth embodiment.

[0162] [Operational Effects] According to the solid-state imaging device 1 of the second modified example of the tenth embodiment, it is possible to obtain operational effects similar to those obtained by the solid-state imaging device 1 of the fifth embodiment.

[0163] 37 shows an example of a specific planar configuration of the pixel 10 and pixel circuit 20 of a solid-state imaging device 1 according to a third modification of the tenth embodiment. As shown in Fig. 37 , in the solid-state imaging device 1 according to the third modification, a unit pixel BP is constructed by a total of four pixels 10, namely, pixel 10A, pixel 10B, pixel 10C, and pixel 10D, which are arranged in the direction of the arrow Y, similar to the solid-state imaging device 1 according to the first modification.

[0164] A reset transistor 24 is disposed at a position corresponding to pixel 10A. An FD conversion gain switching transistor 23 is disposed at a position corresponding to pixel 10B. The FD conversion gain switching transistor 23 is formed in a line-symmetrical shape with respect to the reset transistor 24. An amplifier transistor 21 is disposed at a position corresponding to pixel 10C. The amplifier transistor 21 is formed in a line-symmetrical shape with respect to the FD conversion gain switching transistor 23. A selection transistor 22 is disposed at a position corresponding to pixel 10D. The selection transistor 22 is formed in a line-symmetrical shape with respect to the amplifier transistor 21.

[0165] That is, the pixels 10A, 10B, 10C, and 10D that constitute the unit pixel BP are formed in line symmetry with respect to the X and Y directions.

[0166] The components other than those described above are the same or substantially the same as the components of the solid-state imaging device 1 according to the fifth embodiment.

[0167] [Operational Effects] According to the solid-state imaging device 1 of the third modified example of the tenth embodiment, it is possible to obtain operational effects similar to those obtained by the solid-state imaging device 1 of the fifth embodiment.

[0168] 11. Eleventh embodiment A solid-state imaging device 1 according to an eleventh embodiment of the present disclosure will be described with reference to Fig. 38. [Configuration of solid-state imaging device 1] Fig. 38 shows a vertical cross-sectional configuration of a portion of a pixel 10 and a pixel circuit 20 (the vertical cross-sectional configuration corresponding to the above-described Fig. 4).

[0169] 38 , the solid-state imaging device 1 according to the eleventh embodiment includes an element isolation region 26P instead of the element isolation region 26 of the solid-state imaging device 1 according to the first embodiment. The element isolation region 26P is formed of a semiconductor region that is of the same p-type as the base 15 and has a higher impurity density than the impurity density of the p-type semiconductor region 151 of the base 15. The element isolation region 26P is formed using, for example, an ion implantation method, a solid-phase diffusion method, or the like.

[0170] In the eleventh embodiment, an element isolation region 26P is also formed in a part of the second surface side of the pixel isolation region 16, and the pixel isolation region 16 is configured to include the element isolation region 26P.

[0171] The components other than those described above are the same or substantially the same as the components of the solid-state imaging device 1 according to the first embodiment.

[0172] [Operational Effects] According to the solid-state imaging device 1 of the eleventh embodiment, it is possible to obtain the same operational effects as those obtained by the solid-state imaging device 1 of the first embodiment.

[0173] 38 , the solid-state imaging device 1 includes an element isolation region 26P. In the element isolation region 26P, it is not necessary to form the second groove 261 and the second embedded member 262 of the element isolation region 26. This allows the solid-state imaging device 1 to be easily constructed.

[0174] 12. Twelfth Embodiment A solid-state imaging device 1 according to a twelfth embodiment of the present disclosure will be described with reference to FIGS.

[0175] [Configuration of solid-state imaging device 1] (1) Circuit configuration of pixel 10 and pixel circuit 20 of solid-state imaging device 1 Figure 39 shows an example of the circuit configuration of the pixel 10 and pixel circuit 20 that constitute the solid-state imaging device 1 related to the 12th embodiment.

[0176] 39 , the basic configuration of the pixel 10 and pixel circuit 20 of the solid-state imaging device 1 is the same as the configuration of the pixel 10 and pixel circuit 20 of the solid-state imaging device 1 according to the first embodiment. In the twelfth embodiment, a power supply voltage terminal VDD connected to each of the amplifier transistor 21 and reset transistor 24 of the pixel circuit 20 constituting the unit pixel BP1 is shared. In addition, a power supply voltage terminal VDD connected to each of the amplifier transistor 21 and reset transistor 24 of the pixel circuit 20 constituting the unit pixel BP2 disposed adjacent to the unit pixel BP1 is shared. The power supply voltage terminal VDD is shared between the unit pixels BP1 and BP2.

[0177] (2) Layout and longitudinal cross-sectional configuration of pixel 10 and pixel circuit 20 Fig. 40 shows an example of a specific planar configuration of the pixel 10 and pixel circuit 20. Fig. 41 shows a longitudinal cross-sectional configuration of a portion of the pixel 10 and pixel circuit 20 (a cross-section taken along the L-L cutting line shown in Fig. 40).

[0178] 40 and 41 , in the solid-state imaging device 1, similarly to the solid-state imaging device 1 according to the first embodiment, one pixel circuit 20 is arranged for four pixels 10. To explain in detail, the four pixels 10 are two pixels 10A and 10B adjacent to each other in the direction of the arrow X, and two pixels 10C and 10D adjacent to pixels 10A and 10B in the direction of the arrow Y and also adjacent to pixels 10A and 10B in the direction of the arrow X. These four pixels 10A, 10B, 10C, and 10D constitute a unit pixel BP1.

[0179] A reset transistor 24 of the pixel circuit 20 is disposed at a position corresponding to pixel 10D. The reset transistor 24 is disposed in a region partitioned by the pixel isolation region 16, with its gate length Lg aligned with the diagonal line D1-D1 (see FIG. 2). An amplifier transistor 21 of the pixel circuit 20 is disposed at a position corresponding to pixel 10B. The amplifier transistor 21 is disposed in a region partitioned by the pixel isolation region 16, with its gate length Lg aligned with the diagonal line D2-D2. A selection transistor 22 of the pixel circuit 20 is disposed at a position corresponding to pixel 10A. The selection transistor 22 is disposed in a region partitioned by the pixel isolation region 16, with its gate length Lg aligned with the diagonal line D1-D1 (see FIG. 2). An FD conversion gain switching transistor 23 of the pixel circuit 20 is disposed at a position corresponding to pixel 10C. The FD conversion gain switching transistor 23 is arranged in an area partitioned by the pixel isolation region 16 with the gate length Lg direction aligned with the diagonal line D2-D2.

[0180] In the unit pixel BP1, the amplification transistor 21 is formed in a line-symmetrical shape with respect to the selection transistor 22, with the pixel isolation region 16 between the pixel 10A and the pixel 10B as the center. The reset transistor 24 is formed in a line-symmetrical shape with respect to the FD conversion gain switching transistor 23, with the pixel isolation region 16 between the pixel 10C and the pixel 10BD as the center. Furthermore, the reset transistor 24 and the FD conversion gain switching transistor 23 are formed in a line-symmetrical shape with respect to the amplification transistor 21 and the selection transistor 22, with the pixel isolation region 16 between the pixel 10A and the pixel 10B and the pixel 10C and the pixel 10D as the center.

[0181] On the other hand, the unit pixel BP2 is disposed adjacent to the unit pixel BP1 in the direction of the arrow X. The unit pixel BP2 is formed in a shape that is line-symmetrical with respect to the unit pixel BP1, with the pixel isolation region 16 between the unit pixels BP1 and BP2 as the center.

[0182] With this configuration, the pixel 10B of the unit pixel BP1 and the pixel 10B of the unit pixel BP2 are arranged in close proximity to each other. In addition, the pixel 10D of the unit pixel BP1 and the pixel 10D of the unit pixel BP2 are arranged in close proximity to each other. That is, the main electrodes 204 of the amplifier transistor 21 and the reset transistor 24 of the unit pixel BP1 and the main electrodes 204 of the amplifier transistor 21 and the reset transistor 24 of the unit pixel BP2 are gathered in one location. The four main electrodes 204 gathered in one location are electrically connected to each other by the shared connection portion 34 and are shared.

[0183] The shared connection portion 34 is electrically and directly connected to the surface of the main electrode 204, similar to the shared connection portions 31 and 32 of the solid-state imaging device 1 according to the first embodiment described above. More specifically, one end of the shared connection portion 34 is connected to, for example, the main electrode 204 of the amplification transistor 21 of the unit pixel BP1. The other end of the shared connection portion 34 is connected across the pixel isolation region 16 to the main electrodes 204 of the reset transistor 24 of the unit pixel BP1 and the amplification transistor 21 and reset transistor 24 of the unit pixel BP2. The shared connection portion 34 is connected to the power supply voltage terminal VDD through the wiring 7 (see FIG. 39 ).

[0184] As this has already been explained, the explanation will be omitted here, but the main electrodes 204 are connected to each other by shared connection portions 31, the FD regions 25 are connected to each other by shared connection portions 32, and the base connection portions 27 are connected to each other by shared connection portions 33.

[0185] The components other than those described above are the same or substantially the same as the components of the solid-state imaging device 1 according to the first embodiment.

[0186] [Method of Manufacturing Solid-State Imaging Device 1] FIGS. 42 to 48 show an example of a method of manufacturing the solid-state imaging device 1 step by step.

[0187] First, the base 15 is prepared. As shown in Fig. 42, a first groove 161 is formed in the base 15 in a region where the pixel isolation region 16 is to be formed. The first groove 161 is formed by anisotropic etching such as RIE. Here, a mask 165 is formed on the inner wall of the first groove 161 on the second surface side. The mask 165 is used as an impurity introduction resistant mask. For example, a silicon nitride film is used as the mask 165.

[0188] 43 , a mask 165 is used to introduce, for example, p-type impurities into the base 15 from the inner wall of the first groove 161, thereby forming a pinning region 166. Thereafter, the mask 165 is removed. As shown in FIG. 44 , a first filling member 162 is buried in the first groove 161, thereby forming a pixel isolation region 16.

[0189] As shown in FIG. 45 , an element isolation region 26 is formed. The element isolation region 26 is formed between the transistor 200, the FD region 25, and the base connection portion 27, and in this case, is also formed in a part of the second surface side of the pixel isolation region 16. The element isolation region 26 is formed by forming a second groove 261 from the upper surface to the lower surface side of the base 15 and embedding a second embedding member 262 in the second groove 261. The second groove 261 is formed shallower than the first groove 161. Anisotropic etching such as RIE is used to form the second groove 261. The second embedding member 262 is formed by CVD, for example.

[0190] A gate insulating film 202 and a gate electrode 203 (not shown) are sequentially formed on the second surface of the substrate 15 in the region surrounded by the pixel isolation region 16 and the element isolation region 26 (see FIG. 8). Subsequently, as shown in FIG. 46, a main electrode 204 of the transistor 200 is formed. Once the main electrode 204 is formed, the transistor 200 is completed.

[0191] 47 , a shared connection portion 34 is formed to connect the main electrodes 204 of the transistors 200 across the pixel isolation region 16. The shared connection portion 34 is formed by the same process as the process for forming the shared connection portions 31 and 32, which are not shown here.

[0192] An interlayer insulating film 6 and a connection hole 6H are formed in this order, and the wiring 7 is formed as shown in Fig. 48. The wiring 7 shown in Fig. 48 connects the shared connection portion 34 to the power supply voltage terminal VDD.

[0193] When this series of steps is completed, the solid-state imaging device 1 according to the twelfth embodiment is completed, and the manufacturing method is completed.

[0194] [Operational Effects] According to the solid-state imaging device 1 of the twelfth embodiment, it is possible to obtain the same operational effects as those obtained by the solid-state imaging device 1 of the first embodiment.

[0195] As shown in FIGS. 40 and 41 , the solid-state imaging device 1 includes a pixel 10, a transistor 200, a pixel isolation region 16, and a shared connection portion 34. The pixel 10 is disposed on a first surface side of the base 15, which is the light incident side, and includes a photoelectric conversion element 11 that converts light into electric charges. Here, the pixel 10 refers to each of the “first pixel” and the “second pixel” according to the present technology. The “first pixel” is, for example, pixel 10B or pixel 10D of the unit pixel BP1. The “second pixel” is, for example, pixel 10A or pixel 10C of the unit pixel BP2. The pixel isolation region 16 is disposed between the pixels 10 and is formed in the thickness direction of the base 15 to electrically and optically isolate each of the pixels 10. The transistor 200 is disposed on the second surface side of the base 15 at a position corresponding to the pixel 10, with its gate length Lg direction oblique to the arrangement direction of the pixels 10, and processes the converted electric charges. Here, the transistor 200 is each a "first transistor" and a "second transistor" according to the present technology. For example, when the "first transistor" is arranged at a position corresponding to pixel 10B of unit pixel BP1, the "first transistor" is an amplifier transistor 21. When the "second transistor" is arranged at a position corresponding to pixel 10A of unit pixel BP2, the "second transistor" is an amplifier transistor 21. Furthermore, when the "first transistor" is arranged at a position corresponding to pixel 10D of unit pixel BP1, the "first transistor" is a reset transistor 24. When the "second transistor" is arranged at a position corresponding to pixel 10D of unit pixel BP2, the "second transistor" is a reset transistor 24. The shared connection portion 34 electrically connects the main electrodes 204 of the transistors 200 directly to supply a power supply voltage. With this configuration, a power supply voltage can be supplied to the main electrodes 204 of multiple transistors 200 at a single location without forming wiring and connection holes across the pixel isolation region 16. This reduces the number of connection points between the main electrode 204 and the power supply voltage terminal VDD, ensuring a sufficient area for arranging the transistor 200 in the pixel 10. Here, four connection points are reduced to one connection point.In addition, for example, in the pixel 10, a sufficient area is secured for arranging the transistor 200, so that the transistor 200 can be constructed with excellent noise resistance, and the electrical reliability of the solid-state imaging device 1 can be improved.

[0196] 40 and 41 , in the solid-state imaging device 1, the shared connection portion 34 is connected to the power supply voltage terminal VDD through the wiring 7 at a position overlapping the pixel isolation region 16. This allows the distance between the wiring 7 and the transfer gate electrode 205 or the FD region 25 to be increased, thereby weakening the electric field strength from the wiring 7 to the transfer gate electrode 205 or the FD region 25.

[0197] Furthermore, in the solid-state imaging device 1 according to the twelfth embodiment, the shared connection portion 34 is connected to the surface of the main electrode 204 of the transistor 200, as in the solid-state imaging device 1 according to the first embodiment.

[0198] 49 to 51, a solid-state imaging device 1 according to a thirteenth embodiment of the present disclosure will be described. [Configuration of Solid-State Imaging Device 1] Fig. 49 shows a vertical cross-sectional configuration of a portion of a pixel 10 and a pixel circuit 20 (the vertical cross-sectional configuration corresponding to the above-described Fig. 48).

[0199] 49 , in the solid-state imaging device 1 according to the thirteenth embodiment, the structure of the shared connection portion 34 of the solid-state imaging device 1 according to the twelfth embodiment is similar to the shared connection portions 31 and 32 of the solid-state imaging device 1 according to the eighth embodiment. More specifically, the shared connection portion 34 includes a shared groove 341 and a connection conductor 342. The shared groove 341 has the same configuration as the shared groove 311 of the shared connection portion 31 of the solid-state imaging device according to the eighth embodiment, and the connection conductor 342 has the same configuration as the connection conductor 312. Although not shown in the figure, the shared connection portions 31, 32, and 33 are each formed to have the same structure as the shared connection portion 34.

[0200] The components other than those described above are the same or substantially the same as the components of the solid-state imaging device 1 according to the eighth embodiment.

[0201] [Method of Manufacturing Solid-State Imaging Device 1] FIGS. 50 and 51 show an example of a method of manufacturing the solid-state imaging device 1 step by step.

[0202] 45 in the method for manufacturing the solid-state imaging device 1 according to the twelfth embodiment, a shared groove 341 is formed in a part of the second surface side of the pixel isolation region 16 (see FIG. 50 ). The shared groove 341 is formed by the same process as the shared groove 311 of the shared connection portion 31 (not shown). As shown in FIG. 50 , a connection conductor 342 is formed in the shared groove 341. The connection conductor 341 is formed by the same process as the connection conductor 312 of the shared connection portion 31 (not shown).

[0203] 51, an n-type impurity is introduced into the connection conductor 342 to form the shared connection portion 34. The shared connection portion 34 is formed in the same process as the shared connection portion 31.

[0204] The interlayer insulating film 6 and the connection hole 6H are formed in this order, and the wiring 7 is formed as shown in Fig. 49. The wiring 7 shown in Fig. 49 connects the shared connection portion 34 to the power supply voltage terminal VDD.

[0205] When this series of steps is completed, the solid-state imaging device 1 according to the thirteenth embodiment is completed, and the manufacturing method is completed.

[0206] [Effects] The solid-state imaging device 1 according to the thirteenth embodiment can achieve the same effects as those achieved by the solid-state imaging device 1 according to the twelfth embodiment. Furthermore, the solid-state imaging device 1 according to the thirteenth embodiment can achieve the effects achieved by combining the solid-state imaging device 1 according to the twelfth embodiment and the solid-state imaging device 1 according to the eighth embodiment.

[0207] 14. Fourteenth Embodiment A solid-state imaging device 1 according to an eleventh embodiment of the present disclosure will be described with reference to Fig. 52. [Configuration of Solid-State Imaging Device 1] Fig. 52 shows an example of a specific planar configuration of the pixel 10 and the pixel circuit 20.

[0208] 52 , in the solid-state imaging device 1, similarly to the solid-state imaging device 1 according to the twelfth embodiment, one pixel circuit 20 is arranged for four pixels 10. To explain in detail, the four pixels 10 are two pixels 10A and 10B adjacent to each other in the direction of the arrow X, and two pixels 10C and 10D adjacent to pixels 10A and 10B in the direction of the arrow Y and also adjacent to pixels 10A and 10B in the direction of the arrow X. These four pixels 10A, 10B, 10C, and 10D constitute a unit pixel BP1.

[0209] A reset transistor 24 of the pixel circuit 20 is disposed at a position corresponding to pixel 10C. The reset transistor 24 is disposed in a region partitioned by the pixel isolation region 16, with its gate length Lg aligned with the diagonal line D2-D2 (see FIG. 2). An amplifier transistor 21 of the pixel circuit 20 is disposed at a position corresponding to pixel 10D. The amplifier transistor 21 is disposed in a region partitioned by the pixel isolation region 16, with its gate length Lg aligned with the diagonal line D1-D1. An FD conversion gain switching transistor 23 of the pixel circuit 20 is disposed at a position corresponding to pixel 10A. The FD conversion gain switching transistor 23 is disposed in a region partitioned by the pixel isolation region 16, with its gate length Lg aligned with the diagonal line D1-D1. A selection transistor 22 of the pixel circuit 20 is disposed at a position corresponding to pixel 10B. The selection transistor 22 is arranged in a region partitioned by the pixel isolation region 16 with the direction of the gate length Lg aligned with the diagonal line D2-D2 (see FIG. 2).

[0210] In the unit pixel BP1, the selection transistor 22 is formed in a line-symmetrical shape with respect to the FD conversion gain switching transistor 23, with the pixel isolation region 16 between the pixel 10A and the pixel 10B as the center. The amplification transistor 21 is formed in a line-symmetrical shape with respect to the reset transistor 24, with the pixel isolation region 16 between the pixel 10C and the pixel 10D as the center. Furthermore, the reset transistor 24 and the amplification transistor 21 are formed in a line-symmetrical shape with respect to the FD conversion gain switching transistor 23 and the selection transistor 22, with the pixel isolation region 16 between the pixel 10A and the pixel 10B and the pixel 10C and the pixel 10BD as the center.

[0211] On the other hand, the unit pixel BP2 is disposed adjacent to the unit pixel BP1 in the direction of the arrow Y. The unit pixel BP2 is formed in a shape that is line-symmetrical with respect to the unit pixel BP1, with the pixel isolation region 16 between the unit pixels BP1 and BP2 as the center.

[0212] The components other than those described above are the same or substantially the same as the components of the solid-state imaging device 1 according to the twelfth embodiment.

[0213] [Operational Effects] According to the solid-state imaging device 1 of the fourteenth embodiment, it is possible to obtain the same operational effects as those obtained by the solid-state imaging device 1 of the twelfth embodiment.

[0214] 15. Fifteenth embodiment A solid-state imaging device 1 according to a fifteenth embodiment of the present disclosure will be described with reference to Fig. 53. [Configuration of solid-state imaging device 1] Fig. 53 shows an example of a specific planar configuration of the pixel 10 and the pixel circuit 20.

[0215] 53 , in the solid-state imaging device 1 according to the twelfth embodiment, a shared connection portion 34 is disposed across two pixels 10. To explain in more detail, the shared connection portion 34 electrically connects the main electrode 204 of the amplification transistor 21 disposed at a position corresponding to pixel 10B of the unit pixel BP2 to the main electrode 204 of the reset transistor 24 disposed at a position corresponding to pixel 10D of the same unit pixel BP2. In other words, the shared connection portion 34 is formed in a rectangular shape that is elongated in the direction of the arrow Y in a plan view.

[0216] A wiring 7 is connected to each of the main electrode 204 of the amplification transistor 21 arranged at a position corresponding to pixel 10B of unit pixel BP1 and the main electrode 204 of the reset transistor 24 arranged at a position corresponding to pixel 10D of the same unit pixel BP1.

[0217] The components other than those described above are the same or substantially the same as the components of the solid-state imaging device 1 according to the twelfth embodiment.

[0218] [Operational Effects] According to the solid-state imaging device 1 of the fifteenth embodiment, it is possible to obtain the same operational effects as those obtained by the solid-state imaging device 1 of the twelfth embodiment.

[0219] 16. Sixteenth embodiment A solid-state imaging device 1 according to a sixteenth embodiment of the present disclosure will be described with reference to Fig. 54. [Configuration of solid-state imaging device 1] Fig. 54 shows an example of a specific planar configuration of the pixel 10 and the pixel circuit 20.

[0220] 54 , in the solid-state imaging device 1 according to the twelfth embodiment, a shared connection portion 34 is disposed across two pixels 10. To explain in more detail, the shared connection portion 34 electrically connects the main electrode 204 of the reset transistor 24 disposed at a position corresponding to the pixel 10D of the unit pixel BP1 with the main electrode 204 of the reset transistor 24 disposed at a position corresponding to the pixel 10D of the unit pixel BP2. In other words, the shared connection portion 34 is formed in a rectangular shape that is elongated in the direction of the arrow X in a plan view.

[0221] A wiring 7 is connected to each of the main electrodes 204 of the amplifier transistor 21 arranged at a position corresponding to pixel 10B of unit pixel BP1 and the main electrodes 204 of the amplifier transistor 21 arranged at a position corresponding to pixel 10B of unit pixel BP2.

[0222] The components other than those described above are the same or substantially the same as the components of the solid-state imaging device 1 according to the twelfth embodiment.

[0223] [Operational Effects] According to the solid-state imaging device 1 of the sixteenth embodiment, it is possible to obtain operational effects similar to those obtained by the solid-state imaging device 1 of the twelfth embodiment.

[0224] 54 , in the solid-state imaging device 1, the main electrodes 204 of two adjacent reset transistors 24 are connected by a shared connection portion 34. In addition, the main electrodes 204 of two adjacent amplifier transistors 21 are connected by a wiring 7. This allows power supply voltages to be supplied from two different power supply voltage terminals VDD.

[0225] 55 to 57, a solid-state imaging device 1 according to a seventeenth embodiment of the present disclosure will be described. [Configuration of Solid-State Imaging Device 1] Fig. 55 shows an example of a specific planar configuration of the pixel 10 and the pixel circuit 20.

[0226] As shown in FIG. 55, in the solid-state imaging device 1, two pixel circuits 20 are arranged for 16 pixels 10. More specifically, the 16 pixels 10 are pixels 10A to 10P. Four pixels 10A to 10D are adjacent to each other in the direction indicated by the arrow X. Four pixels 10E to 10H are adjacent to each other in the direction indicated by the arrow X and are adjacent to pixels 10A to 10D in the direction indicated by the arrow Y. Four pixels 10I to 10L are adjacent to each other in the direction indicated by the arrow X and are adjacent to pixels 10E to 10H in the direction indicated by the arrow Y. Four pixels 10M to 10P are adjacent to each other in the direction indicated by the arrow X and are adjacent to pixels 10I to 10L in the direction indicated by the arrow Y. These 16 pixels 10A to 10P constitute a unit pixel BP3. The unit pixel BP3 shown in FIG. 55 is a basic arrangement that can be expanded into several modified examples.

[0227] Selection transistors 22 of the pixel circuit 20 are disposed at positions corresponding to the pixels 10A and 10D. The selection transistors 22, etc., are disposed with their gate lengths Lg aligned with the diagonal line D1-D1 or the diagonal line D2-D2, similar to the selection transistors 22, etc., of the solid-state imaging device 1 according to the twelfth embodiment (see FIG. 2). Amplification transistors 21 of the pixel circuit 20 are disposed at positions corresponding to the pixels 10B and 10C. Amplification transistors 21 or selection transistors 22 of the pixel circuit 20 are disposed at positions corresponding to the pixels 10E to 10H, the pixel 10I, and the pixel 10L. Amplification transistors 21 of the pixel circuit 20 are disposed at positions corresponding to the pixels 10J and 10K. FD conversion gain switching transistors 23 of the pixel circuit 20 are disposed at positions corresponding to the pixels 10M and 10P. Reset transistors 24 of the pixel circuit 20 are disposed at positions corresponding to the pixels 10N and 10O.

[0228] The unit pixels BP3 configured in this manner are sequentially arranged in line symmetry in the arrow X direction and the arrow Y direction.

[0229] FIG. 56 shows an example of a specific planar configuration of the pixel 10 and pixel circuit 20. In the unit pixel BP3, the amplifier transistors 21 of the pixel circuit 20 are disposed at positions corresponding to pixels 10E to 10H, pixel 10I, and pixel 10L. According to the solid-state imaging device 1 configured in this manner, the main electrodes 204 of the amplifier transistors 21 disposed at positions corresponding to pixels 10B, 10C, 10F, and 10G are gathered in one location. This allows the multiple main electrodes 204 to be connected to the power supply voltage terminal VDD via the shared connection portion 34 and the wiring 7. Furthermore, the main electrodes 204 of the amplifier transistors 21 disposed at positions corresponding to pixels 10J and 10K, and the main electrodes 204 of the reset transistors 24 disposed at positions corresponding to pixels 10N and 10O, are also gathered in one location. This allows the multiple main electrodes 204 to be connected to the power supply voltage terminal VDD via the shared connection portion 34 and the wiring 7.

[0230] The components other than those described above are the same or substantially the same as the components of the solid-state imaging device 1 according to the twelfth embodiment.

[0231] [Operational Effects] According to the solid-state imaging device 1 of the seventeenth embodiment, it is possible to obtain operational effects similar to those obtained by the solid-state imaging device 1 of the twelfth embodiment.

[0232] [Modification] Fig. 57 shows an example of a specific planar configuration of the pixel 10 and pixel circuit 20 of a solid-state imaging device 1 according to a modification of the seventeenth embodiment. As shown in Fig. 57, in a unit pixel BP3 of the solid-state imaging device 1 according to the modification, a selection transistor 22 of the pixel circuit 20 is disposed at a position corresponding to pixel 10E, pixel 10H, pixel 10I, and pixel 10L. Furthermore, an amplification transistor 21 of the pixel circuit 20 is disposed at a position corresponding to pixel 10F and pixel 10G. With the solid-state imaging device 1 configured in this manner, the main electrodes 204 of the amplification transistors 21 disposed at positions corresponding to pixel 10B, pixel 10C, pixel 10F, and pixel 10G are gathered in one location. This allows the multiple main electrodes 204 to be connected to the power supply voltage terminal VDD via the shared connection portion 34 and the wiring 7. Furthermore, the main electrodes 204 of the amplification transistors 21 disposed at positions corresponding to the pixels 10J and 10K, and the main electrodes 204 of the reset transistors 24 disposed at positions corresponding to the pixels 10N and 10O, are gathered in one place. This allows the multiple main electrodes 204 to be connected to the power supply voltage terminal VDD through the shared connection portion 34 and the wiring 7.

[0233] The components other than those described above are the same or substantially the same as the components of the solid-state imaging device 1 according to the seventeenth embodiment.

[0234] [Operational Effects] According to the solid-state imaging device 1 according to the modified example of the seventeenth embodiment, it is possible to obtain the same operational effects as those obtained by the solid-state imaging device 1 according to the seventeenth embodiment.

[0235] 18. Eighteenth Embodiment A solid-state imaging device 1 according to an eighteenth embodiment of the present disclosure will be described with reference to FIGS.

[0236] [Configuration of Solid-State Imaging Device 1] (1) Layout Configuration of Pixels 10 and Pixel Circuits 20 of Solid-State Imaging Device 1 Fig. 58 shows an example of a specific planar layout configuration of the pixels 10, pixel circuits 20, color filters 4, and optical lenses 5. In the solid-state imaging device 1 according to the eighteenth embodiment, two pixels 10 adjacent in the direction of arrow X and sharing the FD region 25 constitute a unit pixel BP. The unit pixels BP are arranged in the direction of arrow X and adjacent in the direction of arrow Y, with a shift of one pixel 10 in the direction of arrow X.

[0237] (2) Layout Configuration of Pixel 10, Pixel Circuit 20, and Color Filter 4 A color filter 4 is arranged in the pixel 10. Although a description of the color filter 4 in a vertical cross section will be omitted, the color filter 4 is arranged on the first surface side of the base 15. In the eighteenth embodiment, the color filter 4 includes a red filter 41, a green filter 42, a green filter 43, and a blue filter 44.

[0238] In the color filter 4, red filters 41 and green filters 43 are alternately arranged in the direction of the arrow X. Green filters 42 are arranged adjacent to the red filters 41 in the direction of the arrow Y and on the opposite side thereof. Furthermore, blue filters 44 are arranged adjacent to the green filters 43 in the direction of the arrow Y and on the opposite side thereof. In other words, the green filters 42 and blue filters 44 are alternately arranged in the direction of the arrow X.

[0239] (3) Planar Layout Configuration of Red Filter 41 and Blue Filter 44 Fig. 59 shows an example of a planar layout configuration of the pixels 10 and pixel circuits 20. As shown in Fig. 58 and Fig. 59, in the 18th embodiment, a total of eight pixels 10 are constructed as one unit pixel BPR, and a red filter 41 is arranged in this unit pixel BPR.

[0240] In the eighteenth embodiment, an amplification transistor 21 is disposed at a position corresponding to pixel 10A. A selection transistor 22 is disposed at a position corresponding to pixel 10B. An FD conversion gain switching transistor 23 is disposed at a position corresponding to pixel 10C. A reset transistor 24 is disposed at a position corresponding to pixel 10D.

[0241] To explain in more detail, the unit pixel BPR includes pixel 10D and pixel 10C arranged adjacent to each other in the direction of the arrow X, pixel 10B, pixel 10A, pixel 10D, and pixel 10C arranged adjacent to each other in the direction of the arrow Y and also arranged adjacent to each other in the direction of the arrow X, and pixel 10B and pixel 10A arranged adjacent to each other in the direction of the arrow Y and also arranged adjacent to each other in the direction of the arrow X.

[0242] Similarly, a total of eight pixels 10 are constructed as one unit pixel BPB, and this unit pixel BPB is provided with a blue filter 44. The unit pixel BPB includes pixel 10D and pixel 10C arranged adjacent to each other in the direction of the arrow X, pixel 10B, pixel 10A, pixel 10D, and pixel 10C arranged adjacent to each other in the direction of the arrow Y and also adjacent to each other in the direction of the arrow X, and pixel 10B and pixel 10A arranged adjacent to each other in the direction of the arrow Y and also adjacent to each other in the direction of the arrow X.

[0243] (4) Planar Layout Configuration of Green Filter 42 and Green Filter 43 Fig. 60 shows an example of a planar layout configuration of a pixel 10 in which a green filter 43 is arranged. As shown in Figs. 58 to 60, in the 18th embodiment, a total of 10 pixels 10 are constructed as one unit pixel BPGb, and a green filter 43 is arranged in this unit pixel BPGb.

[0244] The unit pixel BPGb includes pixel 10, pixel 10C, pixel 10B, and pixel 10A arranged adjacent to each other in the direction of the arrow X, pixel 10D and pixel 10A arranged adjacent to each other in the direction of the arrow Y and also arranged adjacent to each other in the direction of the arrow X, and pixel 10A, pixel 10B, pixel 10D, and pixel 10C arranged adjacent to each other in the direction of the arrow Y and also arranged adjacent to each other in the direction of the arrow X.

[0245] Similarly, a total of ten pixels 10 are configured as one unit pixel BPGr, and a green filter 42 is disposed in this unit pixel BPGr.

[0246] The unit pixel BPGr includes pixel 10, pixel 10C, pixel 10B, and pixel 10A arranged adjacent to each other in the direction of the arrow X, pixel 10D and pixel 10A arranged adjacent to each other in the direction of the arrow Y and also arranged adjacent to each other in the direction of the arrow X, and pixel 10A, pixel 10B, pixel 10D, and pixel 10C arranged adjacent to each other in the direction of the arrow Y and also arranged adjacent to each other in the direction of the arrow X.

[0247] (5) Layout Configuration of Optical Lens 5 As shown in Fig. 58, the optical lens 5 is disposed on the first surface of the base 15 with the color filter 4 interposed therebetween. The optical lens 5 is formed to have a length equivalent to 10 minutes of two pixels in the direction of the arrow X, and a length equivalent to 10 minutes of one pixel in the direction of the arrow Y. In other words, the optical lens 5 is formed in an elliptical shape with a different aspect ratio in a plan view. One optical lens 5 is disposed corresponding to each unit pixel BP.

[0248] 59 , in the unit pixel BPR, in two adjacent pixels 10A and 10D in the direction of the arrow X, the main electrodes 204 of the amplifier transistor 21 and the reset transistor 24 are shared by a shared connection portion 34. Similarly, in the unit pixel BPB, in two adjacent pixels 10A and 10D in the direction of the arrow X, the main electrodes 204 of the amplifier transistor 21 and the reset transistor 24 are shared by a shared connection portion 34. The shared connection portion 34 is connected to the power supply voltage terminal VDD through the wiring 7.

[0249] On the other hand, in unit pixel BPGb, the main electrodes 204 of the amplifier transistor 21 and the reset transistor 24 are shared by a shared connection portion 34 between two pixels 10D and pixel 10A adjacent to each other in the direction of arrow X and one pixel 10D adjacent to each other in the direction of arrow Y. In other words, the shared connection portion 34 is disposed across a total of three pixels 10. Similarly, in unit pixel BPGr, the main electrodes 204 of the amplifier transistor 21 and the reset transistor 24 are shared by a shared connection portion 34 between two pixels 10D and pixel 10A adjacent to each other in the direction of arrow X and one pixel 10D adjacent to each other in the direction of arrow Y. The shared connection portion 34 is connected to the power supply voltage terminal VDD through wiring 7.

[0250] The components other than those described above are the same or substantially the same as the components of the solid-state imaging device 1 according to the twelfth embodiment.

[0251] [Operational Effects] According to the solid-state imaging device 1 of the eighteenth embodiment, it is possible to obtain operational effects similar to those obtained by the solid-state imaging device 1 of the twelfth embodiment.

[0252] 19. Application Examples to Mobile Bodies The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of mobile body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, or a robot.

[0253] FIG. 61 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology of the present disclosure can be applied.

[0254] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 61 , the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also shown as functional components of the integrated control unit 12050 are a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (Interface) 12053.

[0255] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0256] The body system control unit 12020 controls the operation of various devices equipped in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, backup lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches can be input to the body system control unit 12020. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0257] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture images outside the vehicle and receives the captured images. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc. based on the received images.

[0258] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0259] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.

[0260] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the distance between vehicles, maintaining vehicle speed, vehicle collision warning, vehicle lane departure warning, etc.

[0261] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle obtained by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0262] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12030 based on the information outside the vehicle acquired by the outside information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside information detection unit 12030, and perform cooperative control aimed at preventing glare, such as switching from high beams to low beams.

[0263] The audio / video output unit 12052 transmits at least one output signal of audio and / or video to an output device capable of visually or audibly notifying the passengers of the vehicle or the outside of the vehicle of information. In the example of Fig. 61, the output devices are exemplified by an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.

[0264] FIG. 62 is a diagram showing an example of the installation position of the imaging unit 12031.

[0265] In FIG. 62, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0266] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided on the front nose and the imaging unit 12105 provided on the top of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 provided on the top of the windshield inside the vehicle cabin is mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0267] 62 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, by overlaying the image data captured by the imaging units 12101 to 12104, an overhead image of the vehicle 12100 viewed from above can be obtained.

[0268] At least one of the image capturing units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the image capturing units 12101 to 12104 may be a stereo camera made up of multiple image capturing elements, or may be an image capturing element having pixels for phase difference detection.

[0269] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can calculate the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100), thereby extracting as a preceding vehicle, in particular, the three-dimensional object that is the closest three-dimensional object on the path of the vehicle 12100 and traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or higher). Furthermore, the microcomputer 12051 can set a vehicle-to-vehicle distance to be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. In this way, cooperative control can be performed for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation.

[0270] For example, the microcomputer 12051 classifies and extracts three-dimensional object data regarding three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines the collision risk, which indicates the risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drive system control unit 12010.

[0271] At least one of the image capturing units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether a pedestrian is present in the images captured by the image capturing units 12101 to 12104. Such pedestrian recognition is performed, for example, by extracting feature points from the images captured by the image capturing units 12101 to 12104 as infrared cameras and performing pattern matching on a series of feature points that indicate the outline of an object to determine whether the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the image capturing units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular outline on the recognized pedestrian for emphasis. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating the pedestrian at a desired position.

[0272] The above describes an example of a vehicle control system to which the technology according to the present disclosure can be applied. Of the configurations described above, the technology according to the present disclosure can be applied to the image capture unit 12031. By applying the technology according to the present disclosure to the image capture unit 12031, it is possible to realize an image capture unit 12031 with a simpler configuration.

[0273] 20. Other Embodiments The present technology is not limited to the above-described embodiments and may be modified in various ways without departing from the spirit of the present technology. For example, among the solid-state imaging devices according to the first embodiment to the eighteenth embodiment, the solid-state imaging devices according to two or more of the above-described embodiments may be combined. Furthermore, in the present technology, for example, in the solid-state imaging device according to the eighteenth embodiment, the number of pixel sets constituting a unit pixel and the array layout of the unit pixels may be modified as appropriate.

[0274] Furthermore, the present technology is not limited to imaging applications, but can be widely applied to light receiving devices, photoelectric conversion devices, photodetection devices, etc. used for sensing applications, etc. Furthermore, the incident light of the solid-state imaging device is not limited to visible light, and may be infrared light, ultraviolet light, electromagnetic waves, etc. Furthermore, the present technology may be configured to receive desired incident light by optionally providing a bandpass filter or the like above the light incident side of the photoelectric conversion element.

[0275] A solid-state imaging device according to a first embodiment of the present disclosure includes a first pixel, a pixel isolation region, a first transistor, a first floating diffusion region, a first transfer gate electrode, or a first substrate connection. The first pixel is disposed on a first surface side of the substrate, which is the light incident side, and has a first photoelectric conversion element that converts light into electric charges. The pixel isolation region is formed in the thickness direction of the substrate and, when viewed from a second surface side of the substrate opposite the first surface, extends in a first direction and a second direction intersecting the first direction to surround the side periphery of the first pixel, electrically and optically isolating the first pixel from other regions. The first transistor is disposed on the second surface of the substrate, surrounded by the pixel isolation region, at a position corresponding to the first pixel. The first transistor processes the converted electric charges with its gate length direction oblique to the first direction or the second direction. The first floating diffusion region, the first transfer gate electrode, or the first substrate connection is disposed on the second surface of the substrate at a position corresponding to the first pixel in the gate width direction of the first transistor. The first transfer gate electrode is a gate electrode of a first transfer transistor that transfers charges from the first pixel to the first floating diffusion region. The first base connection portion supplies a voltage to the base.

[0276] A solid-state imaging device according to a second embodiment of the present disclosure includes a first pixel, a pixel isolation region, a first transistor, a second transistor, a first floating diffusion region, a first transfer gate electrode, or a first substrate connection portion. The first pixel is disposed on a first surface side of the substrate, which is the light incident side, and has a first photoelectric conversion element that converts light into electric charges. The pixel isolation region is formed in the thickness direction of the substrate and, when viewed from a second surface side of the substrate opposite the first surface, extends in a first direction and a second direction intersecting the first direction to surround the side periphery of the first pixel and electrically and optically isolate the first pixel from other regions. The first transistor is disposed on the second surface of the substrate, which is surrounded by the pixel isolation region, at a position corresponding to the first pixel, and has a gate length direction oblique to the first direction or the second direction, and processes the converted electric charges. The second transistor is disposed on a second surface of the substrate surrounded by the pixel isolation region at a position corresponding to the first pixel, with its gate length direction oblique to the first direction or the second direction, and is electrically connected in series to the first transistor. The first floating diffusion region, the first transfer gate electrode, or the first substrate connection portion is disposed on the second surface of the substrate at a position corresponding to the first pixel in the gate width direction of the first transistor and the second transistor. The first transfer gate electrode is a gate electrode of the first transfer transistor that transfers charge from the first pixel to the first floating diffusion region. The first substrate connection portion supplies a voltage to the substrate.

[0277] A solid-state imaging device according to a third embodiment of the present disclosure includes pixels, a pixel isolation region, transistors, and a floating diffusion region, a transfer gate electrode, or a first substrate connection portion. The pixels are arranged on a first surface of the substrate, which is the light incident side, and each pixel has a photoelectric conversion element that converts light into electric charge. The pixel isolation region is formed in the thickness direction of the substrate, surrounds the side surfaces of the pixels, and electrically and optically isolates the pixels. The transistors are arranged on a second surface of the substrate, surrounded by the pixel isolation region, at positions corresponding to the pixels, with their gate length direction oblique to the pixel arrangement direction, and process the converted electric charge. The floating diffusion region, transfer gate electrode, or first substrate connection portion is arranged on the second surface of the substrate at positions corresponding to the pixels, in the gate width direction of the transistor. The transfer gate electrode is a gate electrode of a transfer transistor that transfers electric charge from the pixel to the floating diffusion region. The first substrate connection portion supplies a voltage to the substrate.

[0278] A solid-state imaging device according to a fourth embodiment of the present disclosure includes a first pixel, a second pixel, a pixel isolation region, a first transistor, a second transistor, and a shared connection portion. The first pixel is disposed on a first surface of a substrate, which is a light incident side, and has a first photoelectric conversion element that converts light into an electric charge. The second pixel is disposed adjacent to the first pixel on the first surface of the substrate and has a second photoelectric conversion element that converts light into an electric charge. The pixel isolation region is disposed between the first pixel and the second pixel, and is formed in the thickness direction of the substrate to electrically and optically isolate the first pixel and the second pixel. The first transistor is disposed on the second surface of the substrate at a position corresponding to the first pixel, with a gate length direction oblique to the arrangement direction of the first and second pixels, and processes the converted electric charge. The second transistor is disposed on the second surface of the substrate at a position corresponding to the second pixel, with a gate length direction oblique to the arrangement direction of the first and second pixels, and processes the converted electric charge. The shared connection portion is electrically and directly connected to one of the pair of main electrodes of the first transistor and one of the pair of main electrodes of the second transistor, and supplies a power supply voltage.

[0279] In the solid-state imaging devices according to the first to fourth embodiments of the present disclosure, the area in which the transistors are arranged can be increased, thereby improving the performance of the transistors.

[0280] <Configuration of the Present Technology> The present technology has the following configuration: According to the present technology having the following configuration, in a solid-state imaging device, it is possible to increase the area in which transistors are arranged and improve the performance of the transistors.

[0281] (1) A solid-state imaging device comprising: a first pixel disposed on a first surface side of a substrate, which is a light incident side, and having a first photoelectric conversion element that converts light into an electric charge; a pixel isolation region formed in a thickness direction of the substrate, and extending in a first direction and a second direction intersecting the first direction when viewed from a second surface side of the substrate opposite the first surface, to surround a periphery of a side surface of the first pixel and electrically and optically isolate the first pixel from other regions; a first transistor disposed on the second surface side of the substrate, the periphery of which is surrounded by the pixel isolation region, at a position corresponding to the first pixel, and having a gate length direction oblique to the first direction or the second direction; a first floating diffusion region disposed on the second surface side of the substrate at a position corresponding to the first pixel in a gate width direction of the first transistor; and a first transfer gate electrode of a first transfer transistor that transfers electric charge from the first pixel to the first floating diffusion region, or a first substrate connection portion that supplies a voltage to the substrate. (2) The solid-state imaging device according to (1), wherein the first floating diffusion region, the first transfer gate electrode, or the first base connection portion is disposed with respect to the first transistor via an element isolation region. (3) The solid-state imaging device according to (2), wherein the pixel isolation region comprises a first groove formed from the second surface of the base to the first surface, and a first embedded member embedded in the first groove. (4) The solid-state imaging device according to (3), wherein the element isolation region comprises a second groove formed from the second surface of the base to the first surface, the second groove being shallower than the first groove, and a second embedded member embedded in the second groove. (5) The solid-state imaging device described in any one of (1) to (4), wherein the first pixel is partitioned by the pixel separation region and is formed in a rectangular shape when viewed from the second surface side, a pair of main electrodes of the first transistor are arranged to coincide with a diagonal of the rectangle of the first pixel, and the first floating diffusion region, the first transfer gate electrode, or the first substrate connection portion are arranged to coincide with another diagonal that intersects with the diagonal or along the other diagonal.(6) The solid-state imaging device according to any one of (1) to (5), wherein the gate length direction of the first transistor is inclined at 45 degrees with respect to the first direction or the second direction. (7) The solid-state imaging device according to any one of (1) to (5), further comprising: a second pixel adjacent to the first pixel in a first direction, disposed on the first surface side of the substrate with the pixel isolation region interposed therebetween, and having a second photoelectric conversion element that converts light into electric charges; a second transistor disposed on the second surface side of the substrate surrounded by the pixel isolation region at a position corresponding to the second pixel, and formed in a shape linearly symmetrical to the first transistor with the pixel isolation region between the first pixel and the second pixel as a center; and a second floating diffusion region formed in a shape linearly symmetrical to the first floating diffusion region, the first transfer gate electrode, or the first substrate connection portion at a position corresponding to the second pixel with the pixel isolation region between the first pixel and the second pixel as a center; and a second transfer gate electrode of a second transfer transistor that transfers electric charges from the second pixel to the second floating diffusion region, or a second substrate connection portion that supplies a voltage to the substrate. (8) The solid-state imaging device according to (7), wherein at least one of the pair of main electrodes of the first transistor and the pair of main electrodes of the second transistor, the first floating diffusion region and the second floating diffusion region, the first base connection portion and the second base connection portion are arranged across the pixel isolation region and are shared by a shared connection portion that directly connects them electrically. (9) The solid-state imaging device according to (8), wherein one end of the shared connection portion is directly connected to a side surface of one of the main electrodes of the first transistor, a side surface of the first floating diffusion region, or a side surface of the first base connection portion, and the other end of the shared connection portion is directly connected to a side surface of one of the main electrodes of the second transistor, a side surface of the second floating diffusion region, or a side surface of the second base connection portion.(10) The solid-state imaging device according to (8) or (9), wherein the shared connection portion is embedded in a shared groove formed from the second surface toward the first surface of the pixel isolation region. (11) The solid-state imaging device according to (8), wherein one end of the shared connection portion is directly connected to a surface of one of the main electrodes of the first transistor, a surface of the first floating diffusion region, or a surface of the first base connection portion, and the other end of the shared connection portion is directly connected to a surface of one of the main electrodes of the second transistor, a surface of the second floating diffusion region, or a surface of the second base connection portion. (12) The solid-state imaging device according to any one of (8) to (11), wherein the shared connection portion is a gate electrode material. (13) The solid-state imaging device according to (7), further comprising: a third pixel adjacent to the first pixel in the second direction, disposed on the first surface side of the substrate with the pixel isolation region interposed therebetween, and having a third photoelectric conversion element that converts light into electric charges; a third transistor disposed on the second surface side of the substrate surrounded by the pixel isolation region at a position corresponding to the third pixel, and formed in an axisymmetric shape with respect to the first transistor, with the pixel isolation region between the first pixel and the third pixel as the center; a third floating diffusion region formed in an axisymmetric shape with respect to the first floating diffusion region, the first transfer gate electrode, or the first substrate connection portion at a position corresponding to the third pixel, with the pixel isolation region between the first pixel and the third pixel as the center; and a third transfer gate electrode of a third transfer transistor that transfers electric charges from the third pixel to the third floating diffusion region, or a third substrate connection portion that supplies a voltage to the substrate.(14) The solid-state imaging device according to (7) or (13), further comprising: a fourth pixel adjacent to the third pixel in a first direction, disposed on the first surface side of the substrate with the pixel isolation region interposed therebetween, and having a fourth photoelectric conversion element that converts light into electric charges; a fourth transistor disposed on the second surface side of the substrate surrounded by the pixel isolation region at a position corresponding to the fourth pixel, and formed in a shape linearly symmetrical with respect to the third transistor, with the pixel isolation region between the third pixel and the fourth pixel as the center; a fourth floating diffusion region formed in a shape linearly symmetrical with respect to the third floating diffusion region, the third transfer gate electrode, or the third substrate connection portion at a position corresponding to the fourth pixel, with the pixel isolation region between the third pixel and the fourth pixel as the center; and a fourth transfer gate electrode of a fourth transfer transistor that transfers electric charges from the fourth pixel to the fourth floating diffusion region, or a fourth substrate connection portion that supplies a voltage to the substrate. (15) The solid-state imaging device according to (14), wherein the first transistor, the second transistor, the third transistor, and the fourth transistor are any of an amplifying transistor, a selecting transistor, a floating diffusion conversion gain switching transistor, and a reset transistor that constitute a pixel circuit. (16) The solid-state imaging device according to (7), wherein the first transistor and the second transistor are amplifying transistors that constitute a pixel circuit and are electrically connected in parallel.(17) The solid-state imaging device described in (1), further comprising: a second pixel adjacent to the first pixel in a first direction, disposed on the first surface side of the substrate with the pixel isolation region interposed therebetween, and having a second photoelectric conversion element that converts light into electric charges; a second transistor disposed on the second surface side of the substrate surrounded by the pixel isolation region at a position corresponding to the second pixel, and formed in the same shape as the first transistor; and a second floating diffusion region formed in the same shape as the first floating diffusion region, the first transfer gate electrode, or the first substrate connection portion at a position corresponding to the second pixel, a second transfer gate electrode of a second transfer transistor that transfers electric charges from the second pixel to the second floating diffusion region, or a second substrate connection portion that supplies voltage to the substrate. (18) The solid-state imaging device according to (15), wherein at least one of the first transistor, the second transistor, the third transistor, and the fourth transistor has a fin structure in which an end of a gate electrode in a gate width direction extends from the second surface of the base toward the first surface. (19) The solid-state imaging device according to any one of (1) to (18), wherein, as viewed from the second surface side, the planar shape of the first transfer gate electrode is a circle, an ellipse, a triangle, a rectangle, or a polygon having pentagons or more, and wherein a plurality of the first transfer gate electrodes are arranged. (20) The solid-state imaging device according to (2), wherein the element isolation region is a semiconductor region formed to have the same conductivity type as the base and having a higher impurity concentration than the impurity concentration of the base.(21) A first pixel is disposed on a first surface side of a substrate, which is a light incident side, and has a first photoelectric conversion element that converts light into an electric charge; a pixel isolation region formed in a thickness direction of the substrate, and extending in a first direction and a second direction intersecting the first direction when viewed from a second surface side of the substrate opposite to the first surface, surrounding a periphery of a side surface of the first pixel, and electrically and optically isolating the first pixel from other regions; a first transistor is disposed on the second surface side of the substrate surrounded by the pixel isolation region at a position corresponding to the first pixel, and has a gate length direction oblique to the first direction or the second direction; and a second transistor is disposed on the second surface side of the substrate surrounded by the pixel isolation region at a position corresponding to the first pixel, and has a gate length direction oblique to the first direction or the second direction, and is electrically connected in series to the first transistor. a first floating diffusion region disposed in a gate width direction of the first transistor and the second transistor on the second surface side of the base at a position corresponding to the first pixel, and a first transfer gate electrode of a first transfer transistor that transfers charges from the first pixel to the first floating diffusion region, or a first base connection portion that supplies a voltage to the base. (22) A solid-state imaging device comprising: a plurality of arranged pixels, each having a photoelectric conversion element that converts light into electric charges, arranged on a first surface side of a substrate that is the light incident side; a pixel isolation region formed in the thickness direction of the substrate, surrounding the side surfaces of the plurality of pixels, and electrically and optically isolating the plurality of pixels; a transistor arranged on the second surface side of the substrate, surrounded by the pixel isolation region, at a position corresponding to the pixel, and having a gate length direction oblique to the arrangement direction of the pixels; a floating diffusion region arranged in the gate width direction of the transistor on the second surface side of the substrate at a position corresponding to the pixel; a transfer gate electrode of a transfer transistor that transfers electric charges from the pixel to the floating diffusion region, or a first substrate connection portion that supplies voltage to the substrate.(23) A solid-state imaging device comprising: a first pixel disposed on a first surface side of a substrate, which is a light incident side, and having a first photoelectric conversion element that converts light into an electric charge; a second pixel disposed adjacent to the first pixel, on the first surface side of the substrate, and having a second photoelectric conversion element that converts light into an electric charge; a pixel isolation region disposed between the first pixel and the second pixel, formed in the thickness direction of the substrate, and electrically and optically isolating the first pixel and the second pixel; a first transistor disposed on the second surface side of the substrate at a position corresponding to the first pixel, and having a gate length direction oblique to the arrangement direction of the first pixel and the second pixel; a second transistor disposed on the second surface side of the substrate at a position corresponding to the second pixel, and having a gate length direction oblique to the arrangement direction of the first pixel and the second pixel; and a shared connection portion electrically connected directly to one of a pair of main electrodes of the first transistor and one of a pair of main electrodes of the second transistor, and supplying a power supply voltage. (24) The solid-state imaging device according to (23), wherein one end of the shared connection portion is connected to a side surface of one of the main electrodes of the first transistor, and the other end of the shared connection portion is connected to a side surface of one of the main electrodes of the second transistor. (25) The solid-state imaging device according to (23) or (24), wherein the shared connection portion is embedded in a shared groove formed from the second surface toward the first surface of the pixel isolation region. (26) The solid-state imaging device according to (23), wherein one end of the shared connection portion is connected to a surface of one of the main electrodes of the first transistor, and the other end of the shared connection portion is connected to a surface of one of the main electrodes of the second transistor. (27) The solid-state imaging device according to any one of (23) to (26), wherein the second transistor is formed in an axisymmetric shape with respect to the first transistor with the pixel isolation region between the first pixel and the second pixel as a center, and one of the main electrodes of the first transistor and one of the main electrodes of the second transistor are closer to each other than the other of the main electrodes of the first transistor and the other of the main electrodes of the second transistor, and are connected by the shared connection portion.(28) The solid-state imaging device according to any one of (23) to (27), wherein the first transistor and the second transistor are an amplification transistor and a reset transistor that constitute a pixel circuit. (29) The solid-state imaging device according to any one of (23) to (28), further comprising: a third pixel adjacent to the first pixel or the second pixel, disposed on the first surface side of the base, and having a third photoelectric conversion element that converts light into an electric charge; the pixel isolation region disposed between the first pixel or the second pixel and the third pixel; and a third transistor disposed on the second surface side of the base at a position corresponding to the third pixel, and having a gate length direction oblique to an arrangement direction of the first pixel and the second pixel, wherein the shared connection portion is electrically and directly connected to one of the main electrodes of the first transistor, one of the main electrodes of the second transistor, and one of the pair of main electrodes of the third transistor, and supplies a power supply voltage. (30) The solid-state imaging device according to any one of (7) to (11) and (23) to (29), wherein the other first pixels and the other second pixels adjacent to the first pixels and the second pixels in a direction intersecting the arrangement direction of the first pixels and the second pixels are arranged with a shift of one pixel in the arrangement direction.

[0282] This application claims priority based on Japanese Patent Application No. 2022-020875, filed on February 14, 2022 in the Japan Patent Office, the entire contents of which are incorporated herein by reference.

[0283] Those skilled in the art will recognize that various modifications, combinations, subcombinations, and variations may occur depending on design requirements and other factors, and are intended to be within the scope of the appended claims and their equivalents.

Claims

1. A solid-state imaging device comprising: a first pixel disposed on a first surface side of a base, which is the light incident side, and having a first photoelectric conversion element that converts light into electric charges; a pixel isolation region formed in the thickness direction of the base, and extending in a first direction and a second direction intersecting the first direction when viewed from a second surface side of the base opposite the first surface, to surround the side periphery of the first pixel and electrically and optically isolate the first pixel from other regions; a first transistor disposed on the second surface side of the base, the periphery of which is surrounded by the pixel isolation region, at a position corresponding to the first pixel, and having a gate length direction oblique to the first direction or the second direction; a first floating diffusion region disposed on the second surface side of the base in the gate width direction of the first transistor at a position corresponding to the first pixel; and a first transfer gate electrode of a first transfer transistor that transfers electric charges from the first pixel to the first floating diffusion region, or a first base connection portion that supplies voltage to the base.

2. The solid-state imaging device according to claim 1, wherein the first floating diffusion region, the first transfer gate electrode or the first substrate connection portion is disposed with an element isolation region interposed between them and the first transistor.

3. The solid-state imaging device according to claim 2, wherein the pixel isolation region comprises a first groove formed from the second surface of the base toward the first surface, and a first embedded member embedded in the first groove.

4. A solid-state imaging device as described in claim 3, wherein the element isolation region is formed from the second surface of the base toward the first surface, and comprises a second groove shallower than the first groove, and a second embedded member embedded in the second groove.

5. The solid-state imaging device according to claim 1, wherein the first pixel is partitioned by the pixel isolation region and is formed in a rectangular shape when viewed from the second surface side, the pair of main electrodes of the first transistor are arranged to coincide with a diagonal of the rectangle of the first pixel, and the first floating diffusion region, the first transfer gate electrode or the first base connection portion are arranged to coincide with another diagonal that intersects with the diagonal or along the other diagonal.

6. The solid-state imaging device according to claim 1, wherein the gate length direction of the first transistor is inclined at 45 degrees with respect to the first direction or the second direction.

7. The solid-state imaging device according to claim 1, further comprising: a second pixel adjacent to the first pixel in the first direction, disposed on the first surface side of the base with the pixel isolation region interposed, and having a second photoelectric conversion element that converts light into electric charges; a second transistor disposed on the second surface side of the base surrounded by the pixel isolation region at a position corresponding to the second pixel, and formed in a shape linearly symmetrical to the first transistor with the pixel isolation region between the first pixel and the second pixel as the center; a second floating diffusion region formed in a shape linearly symmetrical to the first floating diffusion region, the first transfer gate electrode, or the first base connection portion at a position corresponding to the second pixel, with the pixel isolation region between the first pixel and the second pixel as the center; and a second transfer gate electrode of a second transfer transistor that transfers electric charges from the second pixel to the second floating diffusion region or a second base connection portion that supplies voltage to the base.

8. A solid-state imaging device as described in claim 7, wherein at least one of the pair of main electrodes of the first transistor and the pair of main electrodes of the second transistor, the first floating diffusion region and the second floating diffusion region, the first substrate connection portion and the second substrate connection portion are arranged across the pixel isolation region and are shared by a shared connection portion that electrically connects them directly.

9. A solid-state imaging device as described in claim 8, wherein one end of the shared connection portion is directly connected to a side surface of one of the main electrodes of the first transistor, a side surface of the first floating diffusion region, or a side surface of the first base connection portion, and the other end of the shared connection portion is directly connected to a side surface of one of the main electrodes of the second transistor, a side surface of the second floating diffusion region, or a side surface of the second base connection portion.

10. The solid-state imaging device according to claim 9, wherein the shared connection portion is embedded in a shared groove formed from the second surface toward the first surface of the pixel isolation region.

11. A solid-state imaging device as described in claim 8, wherein one end of the shared connection portion is directly connected to the surface of one of the main electrodes of the first transistor, the surface of the first floating diffusion region, or the surface of the first base connection portion, and the other end of the shared connection portion is directly connected to the surface of one of the main electrodes of the second transistor, the surface of the second floating diffusion region, or the surface of the second base connection portion.

12. The solid-state imaging device according to claim 8, wherein the shared connection portion is a gate electrode material.

13. The solid-state imaging device according to claim 7, further comprising: a third pixel adjacent to the first pixel in the second direction, disposed on the first surface side of the base with the pixel isolation region interposed, and having a third photoelectric conversion element that converts light into electric charges; a third transistor disposed on the second surface side of the base surrounded by the pixel isolation region at a position corresponding to the third pixel, and formed in a shape linearly symmetrical to the first transistor with the pixel isolation region between the first pixel and the third pixel as the center; a third floating diffusion region formed in a shape linearly symmetrical to the first floating diffusion region, the first transfer gate electrode, or the first base connection portion at a position corresponding to the third pixel, with the pixel isolation region between the first pixel and the third pixel as the center; and a third transfer gate electrode of a third transfer transistor that transfers electric charges from the third pixel to the third floating diffusion region or a third base connection portion that supplies a voltage to the base.

14. The solid-state imaging device of claim 13, further comprising: a fourth pixel adjacent to the third pixel in the first direction, disposed on the first surface side of the base with the pixel isolation region interposed, and having a fourth photoelectric conversion element that converts light into electric charges; a fourth transistor disposed on the second surface side of the base surrounded by the pixel isolation region at a position corresponding to the fourth pixel, and formed in a shape linearly symmetrical to the third transistor with the pixel isolation region between the third pixel and the fourth pixel as the center; a fourth floating diffusion region formed in a shape linearly symmetrical to the third floating diffusion region, the third transfer gate electrode, or the third base connection portion at a position corresponding to the fourth pixel, with the pixel isolation region between the third pixel and the fourth pixel as the center; and a fourth transfer gate electrode of a fourth transfer transistor that transfers electric charges from the fourth pixel to the fourth floating diffusion region or a fourth base connection portion that supplies voltage to the base.

15. The solid-state imaging device according to claim 14, wherein the first transistor, the second transistor, the third transistor, and the fourth transistor are any of an amplification transistor, a selection transistor, a floating diffusion conversion gain switching transistor, and a reset transistor that constitute a pixel circuit.

16. The solid-state imaging device according to claim 7, wherein the first transistor and the second transistor are amplifying transistors that constitute a pixel circuit and are electrically connected in parallel.

17. The solid-state imaging device of claim 1, further comprising: a second pixel adjacent to the first pixel in the first direction, disposed on the first surface side of the base with the pixel isolation region interposed, and having a second photoelectric conversion element that converts light into electric charges; a second transistor disposed on the second surface side of the base surrounded by the pixel isolation region at a position corresponding to the second pixel, and formed in the same shape as the first transistor; a second floating diffusion region formed in the same shape as the first floating diffusion region, the first transfer gate electrode, or the first base connection portion at a position corresponding to the second pixel, and a second transfer gate electrode of a second transfer transistor that transfers electric charges from the second pixel to the second floating diffusion region, or a second base connection portion that supplies voltage to the base.

18. A solid-state imaging device according to claim 15, wherein at least one of the first transistor, the second transistor, the third transistor and the fourth transistor has a fin-type structure in which an end of a gate electrode in the gate width direction is extended from the second surface of the base toward the first surface.

19. A solid-state imaging device as described in claim 1, wherein the planar shape of the first transfer gate electrode when viewed from the second surface side is a circle, an ellipse, a triangle, a rectangle, or a polygon having pentagons or more, and wherein a plurality of the first transfer gate electrodes are arranged.

20. The solid-state imaging device according to claim 2, wherein the element isolation region is a semiconductor region formed to have the same conductivity type as the substrate and having an impurity concentration higher than the impurity concentration of the substrate.

21. A first pixel is disposed on a first surface side of a substrate, which is the light incident side, and has a first photoelectric conversion element that converts light into an electric charge; a pixel isolation region formed in the thickness direction of the substrate, and extending in a first direction and a second direction intersecting the first direction when viewed from a second surface side of the substrate opposite to the first surface, surrounding a side periphery of the first pixel and electrically and optically isolating the first pixel from other regions; a first transistor is disposed on the second surface side of the substrate surrounded by the pixel isolation region at a position corresponding to the first pixel, and has a gate length direction oblique to the first direction or the second direction; and a second transistor is disposed on the second surface side of the substrate surrounded by the pixel isolation region at a position corresponding to the first pixel, and has a gate length direction oblique to the first direction or the second direction, and is electrically connected in series to the first transistor. a first floating diffusion region disposed in a gate width direction of the first transistor and the second transistor on the second surface side of the base at a position corresponding to the first pixel, and a first transfer gate electrode of a first transfer transistor that transfers charges from the first pixel to the first floating diffusion region, or a first base connection portion that supplies a voltage to the base.

22. A solid-state imaging device comprising: a plurality of arranged pixels, each having a photoelectric conversion element that converts light into electric charges, arranged on a first surface side of a substrate that is the light incident side; a pixel isolation region formed in the thickness direction of the substrate, surrounding the side surfaces of the plurality of pixels, and electrically and optically isolating the plurality of pixels; a transistor arranged on the second surface side of the substrate, surrounded by the pixel isolation region, at a position corresponding to the pixel, and having a gate length direction oblique to the pixel arrangement direction; a floating diffusion region arranged in the gate width direction of the transistor on the second surface side of the substrate at a position corresponding to the pixel; a transfer gate electrode of a transfer transistor that transfers electric charges from the pixel to the floating diffusion region, or a first substrate connection portion that supplies voltage to the substrate.

23. A solid-state imaging device comprising: a first pixel disposed on a first surface side of a substrate, which is the light incident side, and having a first photoelectric conversion element that converts light into an electric charge; a second pixel disposed adjacent to the first pixel and on the first surface side of the substrate, and having a second photoelectric conversion element that converts light into an electric charge; a pixel isolation region disposed between the first pixel and the second pixel, formed in the thickness direction of the substrate, and electrically and optically isolating the first pixel and the second pixel; a first transistor disposed on the second surface side of the substrate at a position corresponding to the first pixel, and having a gate length direction oblique to the arrangement direction of the first pixel and the second pixel; a second transistor disposed on the second surface side of the substrate at a position corresponding to the second pixel, and having a gate length direction oblique to the arrangement direction of the first pixel and the second pixel; and a shared connection part electrically and directly connected to one of a pair of main electrodes of the first transistor and one of a pair of main electrodes of the second transistor, and supplying a power supply voltage.

24. A solid-state imaging device as described in claim 23, wherein one end of the shared connection portion is connected to a side surface of one of the main electrodes of the first transistor, and the other end of the shared connection portion is connected to a side surface of one of the main electrodes of the second transistor.

25. The solid-state imaging device according to claim 24, wherein the shared connection portion is embedded in a shared groove formed from the second surface toward the first surface of the pixel isolation region.

26. A solid-state imaging device as described in claim 23, wherein one end of the shared connection portion is connected to the surface of one of the main electrodes of the first transistor, and the other end of the shared connection portion is connected to the surface of one of the main electrodes of the second transistor.

27. A solid-state imaging device as described in claim 23, wherein the second transistor is formed in a shape that is linearly symmetrical to the first transistor with the pixel isolation region between the first pixel and the second pixel as the center, and one of the main electrodes of the first transistor and one of the main electrodes of the second transistor are closer to each other than the other of the main electrodes of the first transistor and the other of the main electrodes of the second transistor, and are connected by the shared connection portion.

28. The solid-state imaging device according to claim 23, wherein the first transistor and the second transistor are an amplifier transistor and a reset transistor that constitute a pixel circuit.

29. A solid-state imaging device according to claim 23, further comprising: a third pixel adjacent to the first pixel or the second pixel, disposed on the first surface side of the base, and having a third photoelectric conversion element that converts light into an electric charge; the pixel isolation region disposed between the first pixel or the second pixel and the third pixel; and a third transistor disposed on the second surface side of the base at a position corresponding to the third pixel, the third transistor having a gate length direction oblique to the arrangement direction of the first pixel and the second pixel, wherein the shared connection portion is electrically and directly connected to one of the main electrodes of the first transistor, one of the main electrodes of the second transistor, and one of the pair of main electrodes of the third transistor, and supplies a power supply voltage.

30. A solid-state imaging device according to claim 7, wherein the other first pixels and the other second pixels adjacent to the first pixels and the second pixels in a direction intersecting the arrangement direction of the first pixels and the second pixels are arranged offset by one pixel in the arrangement direction.

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