Voltage sensing circuit, display driver, display device, and comparator

Abstract

In the present invention, first, a differential current pair corresponding to a difference between a reference voltage and a sensed voltage is generated. Next, the differential current pair is converted into a first current based on a first voltage and a second current based on a second voltage, and voltage, which is generated at a first output end by extracting the second current from the first output end while supplying the first current to the first output end, is outputted as a first signal. The differential current pair is further converted into a third current based on the first voltage and a fourth current based on the second voltage, and voltage, which is generated at a second output end by extracting the fourth current from the second output end while supplying the third current to the second output end, is outputted as a second signal. Then, whether the sensed voltage has changed from a reference state or not is determined on the basis of the first and second signals. Note that, in the reference state, the first current is set to be higher than the second current, and the third current is set to be lower than the fourth current.

Description

Voltage detection circuit, display driver, display device and comparator

[0001] The present invention relates to a voltage detection circuit, a display driver including the voltage detection circuit, a display device, and a comparator.

[0002] Currently, active matrix drive display devices using liquid crystal or organic EL display panels are commonly known as the main display devices.

[0003] A display panel includes an insulating transparent substrate made of glass, plastic, or the like, on which a plurality of data lines each extending vertically of a two-dimensional screen and a plurality of gate lines each extending horizontally of the two-dimensional screen are arranged, intersecting each other. Furthermore, at each intersection of the data lines and the gate lines, a pixel section connected to the data line and the gate line is formed. Each pixel section includes a TFT (thin film transistor) switch and a pixel electrode. When the TFT switch is turned on by a gate signal supplied to the gate line, the grayscale data signal supplied to the data line is supplied to the pixel electrode via the TFT.

[0004] The display panel of a liquid crystal display device consists of a semiconductor substrate on which a thin-film semiconductor circuit is formed and a counter substrate with a counter electrode formed over the entire surface, between which a liquid crystal device is sealed. Liquid crystal display devices display gradations by controlling the transmittance of the backlight provided on the back of the display panel with the voltage applied to the liquid crystal. Color display is achieved by combining an LED backlight with a color filter or color conversion layer, which assigns one of the three primary colors (RGB) to each pixel and synthesizes the three primary colors.

[0005] On the other hand, the display panel of an organic EL display device is composed of a semiconductor substrate on which a thin-film semiconductor circuit and an organic EL element are formed for each pixel portion, and each pixel portion has a pixel circuit that converts a gradation data signal supplied to a pixel electrode into a current and supplies the current to the organic EL element. The organic EL display device displays gradations by controlling the light emission intensity of the organic EL element in each pixel portion using the current supplied to the organic EL element. Color display is achieved by emitting light from the organic EL elements of the three primary colors (RGB) assigned to each pixel, or by combining the light emitted by a single-color organic EL element with a color filter to synthesize the three primary colors.

[0006] Such a display device includes, in addition to the display panel described above, a gate driver that supplies horizontal scanning signals to gate lines to control the TFT switches to be turned on sequentially for each pixel row, and a data driver that supplies gradation signals having analog voltage values ​​corresponding to the luminance level of each pixel to the data lines with data pulses in units of one horizontal scanning period.

[0007] FIG. 1 is a block diagram showing a schematic configuration of an active matrix display device.

[0008] 1 is composed of a display panel 150 having gate lines GL1 to GLr wired in the horizontal direction on an insulating substrate, data lines DL1 to DLm wired in the vertical direction, pixel units 154 arranged in a matrix at the intersections of the gate lines and data lines, a gate driver 110 that drives each gate line, a data driver 120 that drives each data line, and a controller 130 that adjusts the output timing of the gate driver 110 and the data driver 120. Note that TFT switches, pixel electrodes, display devices, etc. included in the pixel units 154 are omitted from the illustration.

[0009] The gate driver 110 receives a group of signals GS from the controller 130 and outputs scanning signals to be supplied to each gate line based on the group of signals GS.

[0010] The data driver 120 receives a signal group VDS, which is a collection of CLK, control signals, video data signals, etc., from the controller 130, and outputs grayscale signals to be supplied to each data line based on the signal group VDS.

[0011] In recent years, the gate driver 110 has generally been configured as a thin-film transistor circuit integrally formed with the pixel section and wiring on the display panel 150. The data driver 120 is typically formed of a silicon LSI and mounted on the edge of the display panel 150 using COG (chip on glass) or COF (chip on film). When the data driver 120 is configured with multiple individual ICs, a group of signals VDS corresponding to the data lines that each IC drives is supplied from the controller 130 to each data driver IC. When the data driver 120 is a single IC or a small number of ICs, the controller 130 may be built into the data driver 120. In this case, a group of signals externally supplied to the controller 130 is directly supplied to the data driver 120.

[0012] Furthermore, in recent years, display panels have become increasingly high-resolution, and as pixel pitches have become smaller, the wiring width and spacing between the wiring have also become smaller, which increases the risk of display panel failure.

[0013] Therefore, there is an increasing demand for display panels equipped with gate drivers, data drivers, and controllers to be equipped with a function for detecting abnormalities and failures. In particular, in-vehicle display panels require a function for quickly detecting abnormalities in the display panel to prevent display freeze, i.e., image freezing.

[0014] Therefore, a configuration has been proposed in which a circuit for detecting and determining defects or faulty states of a display panel is built into the data driver without requiring an external inspection device (see, for example, FIGS. 1 and 4 of Patent Document 1).

[0015] In Patent Document 1, a switching circuit for switching between a normal operation mode and an inspection mode is provided for each output. The switching circuit has a determination circuit that, in the inspection mode, compares the signal voltage supplied to the data line with a preset reference voltage and determines whether the signal is normal or abnormal based on the comparison result.

[0016] Specifically, the determination circuit shown in FIG. 4 of Patent Document 1 includes two comparators (COMP1, COMP2) that compare a signal voltage supplied via an output voltage monitor line with two reference voltages (¼ VCC, ¾ VCC) relative to the output power supply voltage VCC. The determination circuit compares the signal voltage with the two reference voltages using the two comparators, and outputs the results of these comparisons synchronized with a reference clock CK via a serial I / O 74 as a determination signal indicating whether the signal voltage is normal or abnormal. In other words, the determination circuit uses the two reference voltages to determine whether the signal voltage is normal or abnormal based on the voltage level range the signal voltage falls within relative to the two reference voltages.

[0017] Japanese Patent Application Laid-Open No. 2000-275610

[0018] The determination circuit described in Patent Document 1 is configured with high-voltage circuits because at least two comparators (COMP1, COMP2) and the input section of the serial I / O 74 process relatively high signal voltages capable of driving a display panel. Accordingly, a high-voltage circuit is also required for the circuit that generates the reference clock that synchronizes the outputs of the two comparators.

[0019] Therefore, when implementing a determination circuit, the area occupied by the high-voltage circuit becomes large, which causes a problem of increased chip size and higher costs.

[0020] In particular, the in-vehicle semiconductor device (including a display data driver) described in Patent Document 1 requires a large number of abnormality detection circuits for detecting whether there are any abnormalities in various signals. Therefore, if a large number of detection circuits for detecting abnormalities in high-voltage signals are each composed of high-voltage circuits, the chip size of the semiconductor device increases, resulting in increased costs.

[0021] Furthermore, a general comparator used in the determination circuit has a problem in that it is difficult to detect voltages with high precision due to variations in threshold voltages of transistors that make up the circuit.

[0022] Therefore, an object of the present invention is to provide a voltage detection circuit that detects whether the voltage of the detection target has varied from a reference state with high speed response and high accuracy while minimizing the device scale, as well as a display driver, a display device, and a comparator that include the voltage detection circuit.

[0023] A voltage detection circuit according to the present invention is a voltage detection circuit that detects that a detection voltage of a detection target has varied from a reference state having a voltage value within a predetermined voltage range including a reference voltage, and includes: a differential stage that outputs a differential current pair corresponding to a difference between the reference voltage and the detection voltage; and a coupling circuit having first and second voltages and first and second junctions, that outputs first and second signals from the first and second junctions based on first to fourth currents generated by current mirror converting the differential current pair with respect to the first and second voltages, respectively; the other of the differential current pair into the first and third currents forming one of a source type (current sink type), the other of the differential current pair into the second and fourth currents forming the other of a source type and a sink type based on the second voltage, the voltage generated at the first junction where the first current and the second current are combined is generated as the first signal, and the voltage generated at the second junction where the third current and the fourth current are combined is generated as the second signal, and the combining circuit is set so that the first current is larger than the second current and the fourth current is larger than the third current in the reference state.

[0024] A display driver according to the present invention is a display driver that generates grayscale signals corresponding to the brightness level of each pixel based on a video data signal and supplies the first to k-th grayscale signals to first to k-th (k is an integer of 2 or more) data lines of a display panel, respectively, and has a display mode in which an image is displayed on the display panel, and a detection mode in which the grayscale signals supplied to the first to k-th data lines are normal or not, and includes: a setting unit that sets a voltage value of the grayscale signal corresponding to a predetermined brightness level to a reference voltage; a selection unit that, in the detection mode, selects one of the first to k-th grayscale signals and obtains the voltage value of the selected one grayscale signal as a detection voltage; and a voltage detection circuit that detects whether the detection voltage has deviated from a reference state having a voltage value within a predetermined voltage range including the reference voltage, and the voltage detection circuit has first and second voltages and first and second connection points, and performs current mirror conversion of the differential current pair with respect to the first and second voltages, respectively. a coupling circuit that outputs first and second signals from the first and second junction points based on the first to fourth currents generated; and a determination circuit that determines whether the detection voltage has fluctuated from the reference state based on the first and second signals and outputs a determination signal indicative of the determination result, wherein the coupling circuit converts one of the differential current pair to the first and third currents that are one of a source type (current source type) and a sink type (current sink type) based on the first voltage, and converts the other of the differential current pair to the second and fourth currents that are the other of a source type and a sink type based on the second voltage, generates a voltage generated at the first junction point where the first current and the second current are coupled as the first signal, and generates a voltage generated at the second junction point where the third current and the fourth current are coupled as the second signal, and the coupling circuit is set so that the first current is larger than the second current and the fourth current is larger than the third current in the reference state.

[0025] a setting unit that sets a voltage value of the gradation signal corresponding to a predetermined luminance level to a reference voltage; a selection unit that selects one of the first to k-th gradation signals in the detection mode and obtains the voltage value of the selected one gradation signal as a detection voltage; a control unit that controls the selection unit to periodically select the first to k-th gradation signals one by one in order; and a voltage detection circuit that detects that the detection voltage has varied from a reference state having a voltage value within a predetermined voltage range including the reference voltage; a coupling circuit having first and second voltages and first and second junctions, and outputting first and second signals from the first and second junctions based on first to fourth currents generated by current mirror converting the differential current pair with respect to the first and second voltages, respectively; and a determination circuit determining whether the detection voltage has deviated from the reference state based on the first and second signals and outputting a determination signal indicative of the determination result, wherein the coupling circuit couples one of the differential current pairs to the first voltage the other of the differential current pair into the second and fourth currents which are the other of the source type and sink type based on the second voltage; a voltage generated at the first junction where the first current and the second current are coupled is generated as the first signal; and a voltage generated at the second junction where the third current and the fourth current are coupled is generated as the second signal; and in the coupling circuit:The first current is set to be larger than the second current and the fourth current is set to be larger than the third current in the reference state.

[0026] A comparator according to the present invention receives an input voltage and a reference voltage, and outputs a comparison result indicating whether the input voltage is greater than the reference voltage. The comparator comprises: a differential stage that outputs a differential current pair corresponding to the difference between the reference voltage and the input voltage; and a circuit unit having first and second voltages and an output terminal, and that outputs the comparison result signal from the output terminal based on first and second currents generated by current mirror converting the differential current pair with respect to the first and second voltages, respectively. The circuit unit converts one of the differential current pair to the first current that is either a source type (current source type) or a sink type (current sink type) based on the first voltage, and converts the other of the differential current pair to the second current that is the other of the source type and the sink type based on the second voltage, and generates the voltage generated at the output terminal where the first current and the second current are combined as the comparison result signal.

[0027] In the present invention, a differential current pair is generated corresponding to the difference between the detection voltage of the high voltage to be detected and a reference voltage, and this differential current pair is converted into a source current and a sink current based on the low voltage, respectively. Then, both currents are combined at the output terminal, and based on the voltage generated at this output terminal, it is determined whether the detection voltage of the high voltage to be detected has deviated from a reference state based on the reference voltage.

[0028] This makes it possible to output the detection result at high speed in accordance with the input detection voltage with high sensitivity and high accuracy.

[0029] FIG. 1 is a block diagram schematically showing the configuration of an active matrix display device. FIG. 2 is a circuit diagram showing the configuration of a voltage detection circuit 50 according to a first embodiment. FIG. 3 is a diagram showing aspects of detection results by the voltage detection circuit 50. FIG. 4 is a circuit diagram showing an example of the internal configuration of a differential stage 10. FIG. 5 is a circuit diagram showing another example of the internal configuration of the differential stage 10. FIG. 6 is a circuit diagram showing the configuration of a coupling circuit 30A as another example of the coupling circuit 30. FIG. 7 is a circuit diagram showing the configuration of a coupling circuit 30B as another example of the coupling circuit 30. FIG. 8 is a circuit diagram showing the configuration of a voltage detection circuit 50_1 including a coupling circuit 30C as another example of the voltage detection circuit 50. FIG. 9 is a diagram showing aspects of a first detection result (O1, O2, JD1) by the voltage detection circuit 50_1. FIG. 10 is a diagram showing aspects of a second detection result (O3, O4, JD2) by the voltage detection circuit 50_1. FIG. 11 is a block diagram showing the configuration of a display device 200 according to a second embodiment of the present invention. FIG. 12 is a block diagram showing the internal configuration of a data driver 120_1 included in the display device 200. FIG. 13 is a circuit diagram showing the configuration of a comparator 51 according to a third embodiment of the present invention.

[0030] 2A is a circuit diagram showing an example of the configuration of a voltage detection circuit 50 according to a first embodiment of the present invention. The voltage detection circuit 50 is a voltage detection circuit that detects whether a detection voltage to be detected has deviated from a predetermined reference state by comparing the detection voltage with a reference voltage.

[0031] As shown in FIG. 2A, the voltage detection circuit 50 includes a differential stage 10, a coupling circuit 30, and a determination circuit 40.

[0032] The differential stage 10 outputs a pair of differential currents (Is1, Is2) corresponding to the difference between a reference voltage (Vref) and a detection voltage (Vdet) of a high voltage to be detected.

[0033] The combining circuit 30 converts the differential current pair (Is1, Is2) into a first system of current pair (I1, I2) and a second system of current pair (I3, I4). In FIG. 2A , the currents I1 and I3 are source-type currents based on the logic power supply voltage VDD, i.e., current-source currents, and the currents I2 and I4 are sink-type currents based on the ground voltage VSS, i.e., current-sink currents. The combining circuit 30 then combines the source-type and sink-type current pairs of the first system of current pair (I1, I2) and the second system of current pair (I3, I4), and outputs first and second low-voltage logic signals O1 and O2 from respective junctions (n5, n6).

[0034] In the coupling circuit 30, the first source-type current (I1) in the current pair (I1, I2) of the first system is greater than the second sink-type current (I2) in the reference state. Furthermore, the coupling circuit 30 is configured such that the fourth sink-type current (I4) in the current pair (I3, I4) of the second system is greater than the third source-type current (I3) in the reference state.

[0035] As shown in FIG. 2B , the determination circuit 40 determines whether the detection voltage (Vdet) has deviated from the reference state (within a predetermined voltage range including the reference voltage Vref) based on the first and second logic signals O1 and O2 output from the coupling circuit 30. That is, as shown in FIG. 2B , the determination circuit 40 determines that the detection voltage Vdet is in the reference state when the first and second logic signals O1 and O2 have different logical values, and that the detection voltage Vdet is in the reference state when the first and second logic signals O1 and O2 have the same logical value, indicating an abnormality (the detection voltage Vdet deviates from the reference state). That is, the determination circuit 40 receives the 2-bit logic signals O1 and O2 and converts them into a 1-bit logic signal JD indicating normality (one of H or L) or abnormality (the other of H or L). Since the 2-bit logic signals O1 and O2 alone can be used to determine normality or abnormality, the voltage detection circuit of the present invention may be configured without including the determination circuit 40.

[0036] Here, when the voltage detection circuit 50 detects a high voltage signal, the differential stage 10 is formed of high voltage elements corresponding to the high voltage range (AVSS to AVDD), and the coupling circuit 30 and the determination circuit 40 are formed of low voltage elements corresponding to the low voltage range (VSS to VDD) based on the logic power supply.

[0037] The voltage detection circuit 50 shown in FIGS. 2A and 2B will be described in detail below.

[0038] The voltage detection circuit 50 detects whether the detection voltage Vdet is maintained in a reference state (normal) where its voltage value is within a predetermined voltage range including the reference voltage Vref. In other words, if the reference state is defined as when the detection voltage Vdet is substantially equal to the reference voltage Vref, the voltage detection circuit 50 detects an abnormality when the detection voltage Vdet deviates from the reference voltage Vref by a predetermined value or more. For ease of explanation, the following embodiments will be described assuming that the reference state is when the reference voltage Vref and the detection voltage Vdet are equal. Furthermore, the embodiments of the present invention will be described using a voltage detection circuit configuration that performs detection operations on high-voltage signals that are higher than the logic power supply voltage.

[0039] 2A, differential stage 10 is a high-voltage circuit having an AVDD power supply terminal receiving a high-potential analog power supply voltage AVDD and an AVSS power supply terminal receiving an analog ground voltage AVSS, and is composed of high-voltage elements operating at a voltage between AVDD and AVSS. Coupling circuit 30 is a low-voltage circuit composed of low-withstand voltage elements operating between a VDD power supply terminal receiving a low-potential logic power supply voltage VDD and a VSS power supply terminal receiving a logic ground voltage VSS.

[0040] In each embodiment, the relationship between the analog power supply voltage AVDD, analog ground voltage AVSS, logic power supply voltage VDD, and logic ground voltage VSS will be described as AVDD>VDD>VSS≧AVSS.

[0041] 2A, the differential stage 10, which is composed of, for example, an operational amplifier, receives a reference voltage Vref for a high-voltage signal and a detection voltage Vdet to be detected, and generates differential output currents Is1 and Is2 corresponding to the difference voltage between the reference voltage Vref and the detection voltage Vdet. The differential stage 10 supplies the differential output current Is1 to the coupling circuit 30 via a node n1, and supplies the differential output current Is2 to the coupling circuit 30 via a node n2.

[0042] The coupling circuit 30 has N-channel MOS transistors 21, 22, 33 to 35, and P-channel MOS transistors 23 to 25.

[0043] The drain and gate of transistor 21 are connected to node n1, and the source is connected to the VSS power supply terminal. The gate of transistor 22 is connected to the gate of transistor 21, and the source is connected to the VSS power supply terminal. Furthermore, the drain of transistor 22 is connected to the drain and gate of transistor 23. The source of transistor 23 is connected to the VDD power supply terminal. The sources of transistors 24 and 25 are connected to the VDD power supply terminal, and the gates of transistors 24 and 25 are connected to the gate of transistor 23 via node n3.

[0044] The transistor 33 has its drain and gate connected to the node n2, and its source connected to the VSS power supply terminal.

[0045] The sources of the transistors 34 and 35 are connected to the VSS power supply terminal, and the gates of the transistors 34 and 35 are connected to the gate of the transistor 33 via the node n2. The drain of the transistor 34 is connected to the drain of the transistor 24 via the node n5. The drain of the transistor 35 is connected to the drain of the transistor 24 via the node n5.

[0046] Here, a signal having a voltage generated at the node n5 is supplied from the node n5 to the determination circuit 40 as the logic signal O1. Furthermore, a signal having a voltage generated at the node n6 is supplied from the node n6 to the determination circuit 40 as the logic signal O2.

[0047] With this configuration, the differential output current Is1 supplied from the differential stage 10 is folded back to the logic ground voltage VSS by the current mirror (21, 22) configured with N-channel transistors. This folded current is then folded back to the logic power supply voltage VDD by the current mirrors (23, 24) and (23, 25) configured with P-channel transistors, generating two systems of source-type currents I1 and I3. Furthermore, the differential output current Is2 from the differential stage 10 is folded back to the logic ground voltage VSS by the current mirrors (33, 34) and (33, 35) configured with N-channel transistors, generating two systems of sink-type currents I2 and I4.

[0048] Generally, in a source-type and sink-type current pair, one of the differential output currents Is1 and Is2 is generated by folding back an odd number of current mirror sections, and the other is generated by folding back an even number of current mirror sections.

[0049] Here, the source-type current I1 and the sink-type current I2 form a first system of current pairs, and the source-type current I3 and the sink-type current I4 form a second system of current pairs. In this case, the source-type current I1 of the first system of current pairs is sent to node n5, while the sink-type current I2 is drawn from node n5, so that the two currents (I1, I2) are combined at node n5, and a logic signal O1 having a voltage generated at node n5 is output.

[0050] In addition, the source-type current I3 of the second system current pair is sent to node n6, while the sink-type current I4 is drawn out from node n6, so that the two currents (I3, I4) are combined at node n6, and a logic signal O2 having a voltage generated at node n6 is output.

[0051] Each of the logic signals O1 and O2 is generated by combining a source-type current and a sink-type current that are current mirror converted from one of the differential output currents Is1 and Is2, where one decreases as the other increases, with respect to the power supply voltage VDD and the ground voltage VSS, respectively, and therefore quickly changes to the state of the logic power supply voltage VDD or the logic ground voltage VSS that represents the detection result (logical value), thereby achieving a high-speed response.

[0052] In the coupling circuit 30, the current drive capabilities (current amounts) of the transistors 24, 25, 34, and 35 that generate the currents I1 to I4, respectively, are set so that I1>I2 and I3<I4 when the potential relationship between the reference voltage Vref and the detection voltage Vdet is in the reference state. In the reference state, the voltage at the junction of the sink-type current and the source-type current is pulled toward the one with the larger current drive capability (current amount), and is stable at the logic power supply voltage VDD or the logic ground voltage VSS. The actual current that flows is the smaller of the combined sink-type and source-type currents.

[0053] The current difference between currents I1 and I2 and the current difference between currents I3 and I4 in the reference state are set taking into consideration the allowable error range of the detection voltage Vdet considered to be in the reference state, manufacturing variations in the transistors that make up the voltage detection circuit, etc.

[0054] As a result, in a reference state where the detection voltage Vdet is approximately equal to the reference voltage Vref (Vref-dV1≦Vdet≦Vref+dV2), the voltage at the first output terminal (node ​​n5) of the coupling circuit 30 is H: high level (VDD), and the voltage at the second output terminal (node ​​n6) is L: low level (VSS). Note that dV1 indicates the lower limit of the allowable deviation from the reference voltage Vref toward the low voltage side, and dV2 indicates the upper limit of the allowable deviation toward the high voltage side.

[0055] Therefore, at this time, the combining circuit 30 outputs a logic signal O1 of high level (H) and a logic signal O2 of low level (L), as shown in FIG. 2B.

[0056] On the other hand, when the detection voltage Vdet is lower than a preset lower limit voltage for the reference voltage Vref (Vdet<Vref-dV1), the coupling circuit 30 outputs a low-level (L) logic signal O1 and a low-level (L) logic signal O2. When the detection voltage Vdet is higher than a preset upper limit voltage for the reference voltage Vref (Vdet>Vref+dV2), the coupling circuit 30 outputs a high-level (H) logic signal O1 and a high-level (H) logic signal O2.

[0057] The determination circuit 40 receives the logic signals O1 and O2 output from the coupling circuit 30, determines whether the detection voltage Vdet has deviated from the reference state based on the logic signals O1 and O2, and outputs a determination signal JD.

[0058] 2B, when the logic signals O1 and O2 are at a low level (L) and a high level (H), respectively, the determination circuit 40 determines that the state is equivalent to the reference state, i.e., normal. When the logic signals O1 and O2 are both at a low level (L), the determination circuit 40 detects that the detection voltage Vdet is lower than the reference state and determines that an abnormality has occurred. When the logic signals O1 and O2 are both at a high level (H), the determination circuit 40 detects that the detection voltage Vdet is higher than the reference state and determines that an abnormality has occurred.

[0059] The voltage detection circuit 50 may include a control switch that receives a control signal instructing activation or deactivation and activates (operates) or deactivates (stops) itself in response to the control signal. The control switches include a first switch pair that, when off, blocks the differential output currents Is1 and Is2 output from the differential stage 10 from being supplied to the coupling circuit 30, and a second switch pair that, when on, fixes the first and second output terminals (nodes n5 and n6) of the coupling circuit 30 to the same logical value as the reference state (the potential of the VDD power supply terminal or the VSS power supply terminal). That is, when the control signal indicates activation, the first switch pair is set to the on state and the second switch pair is set to the off state. When the control signal indicates deactivation, the first switch pair is set to the off state and the second switch pair is set to the on state.

[0060] This allows the current consumption of the voltage detection circuit 50 to be minimized by activating the voltage detection circuit 50 only during a predetermined detection operation period.

[0061] Next, the setting of the current driving capability (current amount) for the currents I1 to I4 in the reference state in the coupling circuit 30 will be described.

[0062] The ratio of the current amounts of the currents I1 to I4 in the reference state can be set by, for example, the channel width ratio of the input transistor and the output transistor of the current mirror, which determines the current mirror ratio of the current mirror.

[0063] Here, when the differential stage 10 is in a reference state in which the detection voltage Vdet is equal to the reference voltage Vref, the differential output currents Is1 and Is2 are Is1=Is2, when the detection voltage Vdet is higher than the reference voltage Vref, Is1>Is2, and when the detection voltage Vdet is lower than the reference voltage Vref, Is1<Is2.

[0064] Here, the current mirror ratio of the N-channel current mirrors (21, 22) and (33, 34) is set to 1, i.e., the ratio of the channel width W of the input transistor to the output transistor is set to the same channel width (W = Wn). Furthermore, the current mirror ratio of the P-channel current mirror (23, 25) is set to 1, i.e., the ratio of the channel width W of the input transistor to the output transistor is set to the same channel width (W = Wp). For convenience, the following description will be given assuming that the channel lengths of the same conductivity type transistors in the coupling circuit 30 are the same.

[0065] On the other hand, the current mirror ratio of the P-channel current mirror (23, 24) is set to be greater than 1, i.e., the channel width of the output-side transistor 24 is set to be larger (W=Wp+) than the channel width of the input-side transistor 23 (W=Wp).

[0066] As a result, the current amounts of the currents I1 and I2 in the reference state are I1>I2.

[0067] The current mirror ratio of the N-channel current mirror (33, 35) is also set to be greater than 1, i.e., the channel width ratio of the output-side transistor 35 is set to a larger channel width (W=Wn+) than the channel width (W=Wn) of the input-side transistor 33. As a result, the current amounts of the currents I3 and I4 in the reference state are I3<I4.

[0068] The current amounts of the currents I1 and I2 in the reference state are set so that, for example, when the detection voltage Vdet is a predetermined allowable lower limit voltage (Vref-dV1) with respect to the reference voltage Vref, the current amounts of the currents I1 and I2 are I1=I2.

[0069] Similarly, the current amounts of currents I3 and I4 in the reference state are set so that when the detection voltage Vdet is a predetermined allowable upper limit voltage (Vref+dV2) with respect to the reference voltage Vref, the current amounts of currents I3 and I4 are I3=I4.

[0070] In this case, if the detection voltage Vdet is within the range from the upper limit voltage to the lower limit voltage, including the reference voltage Vref, it can be determined to be in the reference state, and if it is outside the range from the upper limit voltage to the lower limit voltage, it can be determined to be in an abnormal state. In other words, by setting the ratio of the current amounts of the currents I1 to I4 described above in the reference state, an arbitrary tolerance range can be set for determining the reference state of the detection voltage Vdet. This makes it possible to realize a voltage detection circuit with sufficient margin for manufacturing variations in the transistors that make up the voltage detection circuit and characteristic fluctuations due to environmental temperature.

[0071] Next, the effect of the voltage detection circuit 50 shown in FIG. 2A will be described.

[0072] In the voltage detection circuit 50, one of the differential output currents Is1 and Is2 of the differential stage 10 is converted into a source-type and sink-type current pair, respectively, to generate two systems of current pairs. Then, the source-type and sink-type currents for each system are combined, and two systems of logic signals O1 and O2 are extracted from the combined point.

[0073] When a voltage difference occurs between the reference voltage Vref and the detection voltage Vdet, the differential stage 10 increases one of the differential output currents Is1 and Is2 and decreases the other. As a result, the voltages at the first and second junctions (nodes n5 and n6) of the coupling circuit 30 quickly change to the logic power supply voltage VDD or the logic ground voltage VSS. In other words, the logic signals O1 and O2 output from the coupling circuit 30 can quickly determine the logic of the detection results.

[0074] 2A, the voltage detection circuit 50 is less susceptible to the influence of manufacturing variations in transistors, and can quickly determine the logical value of the detection result (O1, O2) for the input detection voltage Vdet with high sensitivity and accuracy. Also, the voltage detection circuit 50 shown in FIG. 2A implements an analog-to-digital conversion circuit that converts the state of the detection voltage Vdet relative to the reference voltage Vref into a 2-bit digital signal (O1, O2).

[0075] Furthermore, according to the voltage detection circuit 50, it is possible to determine whether the detection voltage Vdet is within a normal voltage range without using two reference voltages that respectively indicate the allowable lower limit voltage and the allowable upper limit voltage as shown in FIG. 4 of Patent Document 1, thereby simplifying the circuit configuration.

[0076] 2A, only the differential stage 10 needs to be configured with high-voltage (high-withstand voltage) transistors for the high-voltage (AVDD to AVSS) detection voltage. In other words, the other components, the coupling circuit 30 and the determination circuit 40, can be configured with low-voltage (low-withstand voltage) transistors that operate at low voltages (VDD to VSS), making it possible to realize a voltage detection circuit with a small circuit area and low power consumption.

[0077] 2A shows an example of a configuration in which the potential relationship of the power supply voltages is AVDD>VDD>VSS≧AVSS (1). For example, when the potential relationship is reversed to AVSS≧VSS>VDD>AVDD (2), the conductivity types of the transistors in the coupling circuit 30 in FIG. 2A may be swapped. Each embodiment including FIG. 2A will be described using the potential relationship configuration of (1) above.

[0078] Fig. 3 is a circuit diagram showing a specific example of the differential stage 10 shown in Fig. 2A. Note that the coupling circuit 30 and the determination circuit 40 are the same as those in Fig. 2A, and therefore their explanation will be omitted.

[0079] In the example shown in FIG. 3, the differential stage 10 is composed of a P-channel differential pair (11, 12) that differentially inputs a reference voltage Vref and a detection voltage Vdet, and a current source transistor 13 that supplies current to the tail of the differential pair.

[0080] Specifically, the P-channel differential pair (11, 12) is composed of a P-channel transistor 11 whose gate is supplied with a reference voltage Vref and whose drain is connected to the input terminal (node ​​n1) of a current mirror (21, 22), and a P-channel transistor 12 whose gate is supplied with a detection voltage Vdet and whose drain is connected to the input terminal (node ​​n2) of a current mirror (33, 34), (33, 35).

[0081] The differential output currents Is1 and Is2 are output from the drains of the transistors 11 and 12. The sources of the transistors 11 and 12 are connected together and form the tail of a P-channel differential pair (11, 12).

[0082] The current source transistor 13 is configured as a P-channel transistor having a gate supplied with a bias voltage BIASP, a source connected to the AVDD power supply terminal, and a drain connected to the tail of the P-channel differential pair (11, 12).

[0083] According to the configuration shown in FIG. 3, with a simple configuration including only three high-voltage transistors (11 to 13), it is possible to detect the detection voltage Vdet in the voltage range [AVSS to (AVDD-|Vtp|)] excluding the range from the analog power supply voltage AVDD to the threshold voltage |Vtp| of the P-channel differential pair (11, 12).

[0084] In addition, a clamp circuit or clamp element that maintains the voltages of the nodes n1 and n2 connecting the differential stage 10 and the coupling circuit 30 within a low voltage range [VDD to VSS] based on the logic power supply voltage VDD may be provided between the P-channel differential pair (11, 12) of the differential stage 10 and the transistors 21 and 33 of the coupling circuit 30.

[0085] Fig. 4 is a circuit diagram showing another example of the differential stage 10 shown in Fig. 2A. The coupling circuit 30 and the determination circuit 40 are the same as those in Fig. 2A, and therefore their explanation will be omitted.

[0086] In the example shown in FIG. 4, the differential stage 10 is composed of an N-channel differential pair (11a, 12a) that differentially inputs a reference voltage Vref and a detection voltage Vdet, a current source transistor 13a that supplies current to the tail of the differential pair, and P-channel current mirrors (14, 15) and P-channel current mirrors (16, 17).

[0087] Specifically, the N-channel differential pair (11a, 12a) is composed of an N-channel transistor 11a, the gate of which is supplied with a reference voltage Vref and the drain of which is connected to the input terminal (node ​​n7) of a current mirror (14, 15), and an N-channel transistor 12a, the gate of which is supplied with a detection voltage Vdet and the drain of which is connected to the input terminal (node ​​n8) of a current mirror (16, 17).

[0088] The current mirror (14, 15) includes P-channel transistors 14 and 15 whose gates and sources are connected to each other. The drain and gate of transistor 14 are connected to node n7, and its source is connected to the AVDD power supply terminal. The drain of transistor 15 is connected to node n1, and its source is connected to the AVDD power supply terminal. The current mirror (16, 17) includes P-channel transistors 16 and 17 whose gates and sources are connected to each other. The drain and gate of transistor 16 are connected to node n8, and its source is connected to the AVDD power supply terminal. The drain of transistor 17 is connected to node n2, and its source is connected to the AVDD power supply terminal.

[0089] Here, the differential output current Is1 is output from the drain of transistor 11a and supplied to node n1 via a P-channel current mirror (14, 15). The differential output current Is2 is output from the drain of transistor 12a and supplied to node n2 via a P-channel current mirror (16, 17). The sources of transistors 11a and 12a are connected together and form the tail of the N-channel differential pair (11a, 12a).

[0090] The current source transistor 13a is configured as an N-channel transistor having a gate supplied with a bias voltage BIASN, a source connected to the AVSS power supply terminal, and a drain connected to the tail of the N-channel differential pair (11a, 12a).

[0091] When the configuration shown in FIG. 4 is adopted as the differential stage 10, it becomes possible to detect a detection voltage Vdet in a voltage range [(AVSS+Vtn) to AVDD] excluding the range from the analog power supply voltage AVSS to the threshold voltage Vtn of the N-channel differential pair (11a, 12a).

[0092] Fig. 5 is a circuit diagram showing the configuration of a coupling circuit 30A as a modified example of the coupling circuit 30 shown in Fig. 2A. The coupling circuit 30A in Fig. 5 is configured to enable adjustment of the detection sensitivity, i.e., adjustment of the upper and lower limit voltages of the allowable voltage range determined with the detection voltage Vdet as the reference state.

[0093] For ease of explanation, the coupling circuit 30A shown in Fig. 5 shows only the changes from the coupling circuit 30 shown in Fig. 2A. That is, the coupling circuit 30A includes a circuit made up of transistors 21 to 23 and 33, similar to the coupling circuit 30 shown in Fig. 2A, but the illustration of these transistors 21 to 23 and 33 is omitted in Fig. 5.

[0094] In the coupling circuit 30A shown in FIG. 5, the transistor 24 shown in FIG. 2A is replaced with a circuit 24A, and the transistor 35 shown in FIG. 2A is replaced with a circuit 35A, with the transistors 25 and 34 being the same as those shown in FIG. 2A.

[0095] 5, a voltage that generates source-type currents I1 and I3 is supplied to node n3, and a voltage that generates sink-type currents I2 and I4 is supplied to node n2. The current amounts of currents I1 to I4 are set so that I1>I2 and I3<I4 in the reference state.

[0096] The coupling circuit 30A includes a P-channel transistor 25 having a source-type current I3 set to a fixed value in the reference state, and an N-channel transistor 34 having a sink-type current I2 set to a fixed value. The coupling circuit 30A further includes circuits 24A and 35A that can variably adjust the amounts of the source-type current I1 and sink-type current I4 in the reference state.

[0097] Circuits 24A and 35A will now be described.

[0098] The circuit 24A has a configuration in which a plurality of pairs of a P-channel transistor and a switch are connected in series in parallel between the VDD power supply terminal and node n5. That is, the logic power supply voltage VDD is supplied to the source of each of the plurality of parallel P-channel transistors 24a_1, 24a_2, ..., and the gates of each are commonly connected to node n3. As a result, each of the transistors 24a_1, 24a_2, ... generates a mirror current corresponding to the voltage of node n3. The on / off of each of the plurality of parallel switches 26a_1, 26a_2, ... is controlled by an external current amount control signal CNTA.

[0099] Therefore, in the circuit 24A, the current I1 is the combined current of at least one transistor connected to a switch controlled to be on by the current control signal CNTA. That is, by controlling each of the multiple switches 26a_1, 26a_2, ..., the current I1 can be optimally adjusted relative to the current I2. This allows adjustment of the allowable lower limit voltage, which is determined based on the detection voltage Vdet as the reference state.

[0100] The circuit 35A has a configuration in which a plurality of pairs of an N-channel transistor and a switch are connected in series in parallel between the VSS power supply terminal and node n6. That is, the logic ground voltage VSS is supplied to the source of each of the plurality of parallel N-channel transistors 35a_1, 35a_2, ..., and the gates of each are commonly connected to node n2. As a result, each of the transistors 35a_1, 35a_2, ... generates a mirror current corresponding to the voltage of node n2. The on / off of each of the plurality of parallel switches 36a_1, 36a_2, ... is controlled by a current amount control signal CNTA.

[0101] Therefore, in the circuit 35A, the current I4 is the combined current of at least one transistor connected to a switch controlled to be on by the current control signal CNTA. That is, by controlling each of the multiple switches 36a_1, 36a_2, ..., the current I4 can be optimally adjusted relative to the current I3. This makes it possible to adjust the allowable upper limit voltage determined with the detection voltage Vdet as the reference state.

[0102] Fig. 6 is a circuit diagram showing a coupling circuit 30B as yet another modification of the coupling circuit 30 shown in Fig. 2A. The coupling circuit 30B in Fig. 6 is also configured to be capable of adjusting the upper and lower limit voltages of the allowable voltage range determined with the detection voltage Vdet as the reference state.

[0103] Similar to the coupling circuit 30A, the coupling circuit 30B shown in Fig. 6 also shows only the changes from the coupling circuit 30 shown in Fig. 2A. That is, the coupling circuit 30B includes a circuit made up of transistors 21 to 23 and 33, similar to the coupling circuit 30 shown in Fig. 2A, but the illustration of these transistors 21 to 23 and 33 is omitted in Fig. 6.

[0104] In the coupling circuit 30B shown in FIG. 6, the transistor 24 shown in FIG. 2A is replaced with a circuit 24B, and the transistor 35 shown in FIG. 2A is replaced with a circuit 35B, with the transistors 25 and 34 being the same as those shown in FIG. 2A.

[0105] 6, a voltage that generates source-type currents I1 and I3 is supplied to node n3, and a voltage that generates sink-type currents I2 and I4 is supplied to node n2. The amounts of currents I1 to I4 are set so that I1>I2 and I3<I4 in the reference state.

[0106] The coupling circuit 30B includes a transistor 25 having a source-type current I3 set to a fixed value in the reference state, a transistor 34 having a sink-type current I2 set to a fixed value, and circuits 24B and 35B that can variably adjust the amounts of the source-type current I1 and sink-type current I4 in the reference state.

[0107] The transistors 25 and 34 have the same configuration as the transistors 25 and 34 of the coupling circuit 30 shown in Fig. 2A. Circuits 24B and 35B will be described below.

[0108] The circuit 24B has a configuration in which a P-channel transistor 24b_1 and a variable current source 24b_2 are provided in parallel between the VDD power supply terminal and a node n6. The transistor 24b_1 has a source supplied with the logic power supply voltage VDD and a gate connected to a node n3, and generates a mirror current corresponding to the voltage of the node n3 and outputs it from the drain.

[0109] The current amount of the variable current source 24b_2 is controlled by an external current amount control signal CNTB. The combined current of the transistor 24b_1 and the variable current source 24b_2 is set as the current amount of the current I1. That is, by controlling the current amount of the variable current source 24b_2, the current amount of the current I1 relative to the current I2 can be optimally set. This makes it possible to adjust the allowable lower limit voltage that is determined with the detection voltage Vdet as the reference state.

[0110] The circuit 35B has a configuration in which an N-channel transistor 35b_1 and a variable current source 35b_2 are provided in parallel between the VSS power supply terminal and a node n6. The transistor 35b_1 has a source supplied with the logic ground voltage VSS and a gate connected to a node n2, and generates a mirror current corresponding to the voltage of the node n2 and outputs it from its source.

[0111] The current value of the variable current source 35b_2 is controlled by an external current amount control signal CNTB. The combined current of the transistor 35b_1 and the variable current source 35b_2 is set as the amount of current I4. That is, by controlling the current of the variable current source 35b_2, the amount of current I4 relative to current I3 can be optimally set. This makes it possible to adjust the allowable upper limit voltage determined with the detection voltage Vdet as the reference state.

[0112] 2A, 5, and 6 show examples in which the setting of the amount of each of currents I1 and I2, and currents I3 and I4, is adjusted by the size of the transistors that generate current I1 and current I4, or the number of parallel stages of transistors, but such an adjustment function may be provided in the generation circuits of current I2 and current I3.

[0113] Next, a specific example of the determination circuit 40 will be described. The determination circuit 40 receives the 2-bit logic signals O1 and O2 output from the combining circuit 30 and outputs a 1-bit determination signal JD. The determination circuit 40 can be realized by, for example, an exclusive OR circuit (referred to as an EXOR circuit).

[0114] That is, the EXOR circuit receives the detection voltage Vdet and the reference voltage Vref at two input terminals, and outputs a determination signal JD that indicates a logical value H indicating normality (the detection voltage Vdet is in the reference state) when the logic signals O1 and O2 are different, and a logical value L indicating abnormality (the detection voltage Vdet deviates from the reference state) when the logic signals O1 and O2 are the same.

[0115] The determination circuit 40, which is composed of an EXOR circuit, expresses the presence or absence of a fluctuation in the detection voltage Vdet from the reference state in two values, but cannot determine the direction of fluctuation in the detection voltage Vdet. Therefore, if it is desired to obtain the direction of fluctuation (increase or decrease) of the detection voltage Vdet as a determination result, the logic signals O1 and O2 output from the combining circuit 30 may be directly output as a 2-bit signal. Alternatively, two logic signals O1 and O2 may be output in addition to the determination signal JD of the determination circuit 40.

[0116] Fig. 7 is a circuit diagram showing the configuration of a voltage detection circuit 50_1 as another example of the configuration of the voltage detection circuit 50. The voltage detection circuit 50_1 shown in Fig. 7 employs a coupling circuit 30C instead of the coupling circuit 30 shown in Fig. 2A, and has the same configuration as that shown in Fig. 2A except that a determination circuit 40a is newly added.

[0117] In addition, in the coupling circuit 30C, the transistors 21 to 25 and 33 to 35 are the same as those shown in the coupling circuit 30 shown in FIG. 2A.

[0118] However, in the combined circuit 30C, a circuit consisting of transistors 24, 25, 34, and 35, which are also included in the combined circuit 30 of Figure 2A, is used as the first conversion unit CV1, and a second conversion unit CV2 and a judgment circuit 40a are newly added.

[0119] The second conversion unit CV2 has P-channel MOS transistors 24a and 25a and N-channel MOS transistors 34a and 35a. The transistors 24a and 25a have their sources connected to the VDD power supply terminal and their gates connected to the gate of the transistor 23 via node n3. The transistors 34a and 35a have their sources connected to the VSS power supply terminal and their gates connected to the gate of the transistor 33 via node n2. The drain of the transistor 34a is connected to the drain of the transistor 24a via node n5a. The drain of the transistor 35a is connected to the drain of the transistor 25a via node n6a.

[0120] Here, a signal having a voltage generated at the node n5a is supplied to the determination circuit 40a from the node n5a as a logic signal O3. Furthermore, a signal having a voltage generated at the node n6a is supplied to the determination circuit 40a from the node n6a as a logic signal O4.

[0121] With this configuration, in the coupling circuit 30C, first, the differential output current Is1 supplied from the differential stage 10 is folded by the current mirrors (21, 22) to form a current that is folded back to the logic ground voltage VSS. At this time, in the first conversion unit CV1, the folded current is folded back to the logic power supply voltage VDD by the current mirrors (23, 24) and (23, 25), generating two systems of source-type currents I1 and I3. Furthermore, in the first conversion unit CV1, the differential output current Is2 supplied from the differential stage 10 is folded back to the logic ground voltage VSS by the current mirrors (33, 34) and (33, 35), generating two systems of sink-type currents I2 and I4.

[0122] At this time, in the first conversion unit CV1, a source-type current I1 is sent to node n5 while a sink-type current I2 is drawn from node n5, so that the two currents (I1, I2) are combined at node n5, and a logic signal O1 having a voltage generated at node n5 is output. Furthermore, in the first conversion unit CV1, a source-type current I3 is sent to node n6 while a sink-type current I4 is drawn from node n6, so that the two currents (I3, I4) are combined at node n6, and a logic signal O2 having a voltage generated at node n6 is output.

[0123] Furthermore, the current driving capabilities (current amounts) of the transistors 24, 25, 34, and 35 of the first conversion unit CV1, which generate the currents I1 to I4, respectively, are set so that I1>I2 and I3<I4 when the potential relationship between the reference voltage Vref and the detection voltage Vdet is in the first reference state.

[0124] As a result, when the detection voltage Vdet is included in the following first range centered around the reference voltage Vref: Vref-dV1≦Vdet≦Vref+dV2, where dV1 is a first allowable lower limit range and dV2 is a first allowable upper limit range, the voltage at the first output terminal (node ​​n5) of the coupling circuit 30C becomes H: high level (VDD), and the voltage at the second output terminal (node ​​n6) becomes L: low level (VSS). Also, when the detection voltage Vdet is lower than a first allowable lower limit voltage preset with respect to the reference voltage Vref (Vdet<Vref-dV1), the voltages at both the first output terminal (node ​​n5) and the second output terminal (node ​​n6) become L: low level (VSS). Furthermore, when the detection voltage Vdet is higher than a first allowable upper limit voltage preset with respect to the reference voltage Vref (Vdet>Vref+dV2), the voltages of the first output terminal (node ​​n5) and the second output terminal (node ​​n6) both become H: high level (VDD).

[0125] As a result, when the detection voltage Vdet is in a state where Vref-dV1≦Vdet≦Vref+dV2, the first conversion unit CV1 outputs a logic signal O1 indicating a high level and a logic signal O2 indicating a low level, as shown in Figure 8A.

[0126] Furthermore, when the detection voltage Vdet is in a state where Vdet<Vref-dV1, the first conversion unit CV1 outputs logic signals O1 and O2 both indicating a low level, as shown in FIG. 8A.

[0127] Furthermore, when the detection voltage Vdet is in a state where Vdet>Vref+dV2, the first conversion unit CV1 outputs logic signals O1 and O2 both indicating a high level, as shown in FIG. 8A.

[0128] Based on the logic signals O1 and O2 output from the first conversion unit CV1, the judgment circuit 40 judges whether the detection voltage Vdet is within a first range (Vref-dV1≦Vdet≦Vref+dV2) as shown in FIG. 8A, and outputs a judgment signal JD1 indicating the judgment result.

[0129] In this way, the first conversion unit CV1 and the judgment circuit 40 generate a judgment signal JD1 that indicates whether the voltage value of the detection voltage Vdet is within a predetermined first range centered on the reference voltage Vref, as shown in Figure 8A, or whether it is outside the first range.

[0130] Meanwhile, in the second conversion unit CV2, the folded current corresponding to the differential output current Is1 folded back by the current mirror (21, 22) is folded back to the logic power supply voltage VDD by the current mirrors (23, 24a) and (23, 25a), generating two systems of source-type currents I1a and I3. Furthermore, in the second conversion unit CV2, the differential output current Is2 supplied from the differential stage 10 is folded back to the logic ground voltage VSS by the current mirrors (33, 34a) and (33, 35a), generating two systems of sink-type currents I2 and I4a.

[0131] At this time, in the second conversion unit CV2, a source-type current I1a is sent to node n5a while a sink-type current I2 is drawn from node n5a, so that the two currents (I1a, I2) are combined at node n5a, and a logic signal O3 having a voltage generated at node n5a is output.Furthermore, in the second conversion unit CV2, a source-type current I3 is sent to node n6a while a sink-type current I4a is drawn from node n6a, so that the two currents (I3, I4a) are combined at node n6a, and a logic signal O2 having a voltage generated at node n6a is output.

[0132] The current driving capabilities (amounts of current) of the transistors 24a, 25a, 34a, and 35a of the second conversion unit CV2, which generate the currents I1a, I2, I3, and I4a, respectively, are set so that I1a>I1>I2 and I3<I4<I4a when the potential relationship between the reference voltage Vref and the detection voltage Vdet is in the standard state.

[0133] For example, the channel width of transistor 25a in the second conversion unit CV2 is set to the same as the channel width Wp of transistor 25 in the first conversion unit CV1, and the channel width of transistor 34a in the second conversion unit CV2 is set to the same as the channel width Wn of transistor 34 in the first conversion unit CV1. Furthermore, the channel width of transistor 24a in the second conversion unit CV2 is set to Wp++, which is wider than the channel width Wp+ of transistor 24 in the first conversion unit CV1, and the channel width of transistor 35a in the second conversion unit CV2 is set to Wn++, which is wider than the channel width Wn+ of transistor 35 in the first conversion unit CV1.

[0134] As a result, when the detection voltage Vdet is included in the following second range centered around the reference voltage Vref: Vref-dV3≦Vdet≦Vref+dV4, dV3 (dV3>dV1): second allowable lower limit range, and dV4 (dV4>dV2): second allowable upper limit range, the voltage at the third output terminal (node ​​n5a) of the coupling circuit 30C becomes H: high level (VDD), and the voltage at the fourth output terminal (node ​​n6a) becomes L: low level (VSS). Also, when the detection voltage Vdet is lower than a second allowable lower limit voltage preset with respect to the reference voltage Vref (Vdet<Vref-dV3), the voltages at the third output terminal (node ​​n5a) and the fourth output terminal (node ​​n6a) both become L: low level (VSS). Furthermore, when the detection voltage Vdet is higher than a second allowable upper limit voltage preset with respect to the reference voltage Vref (Vdet>Vref+dV4), the voltages of the third output terminal (node ​​n5a) and the fourth output terminal (node ​​n6a) both become H: high level (VDD).

[0135] As a result, when the detection voltage Vdet is in a state where Vref-dV3≦Vdet≦Vref+dV4, the second conversion unit CV2 outputs a logic signal O1 indicating a high level and a logic signal O2 indicating a low level, as shown in FIG. 8B.

[0136] Furthermore, when the detection voltage Vdet is in a state where Vdet<Vref-dV3, the second conversion unit CV2 outputs logic signals O1 and O2 both indicating a low level, as shown in FIG. 8B.

[0137] Furthermore, when the detection voltage Vdet is in a state where Vdet>Vref+dV4, the second conversion unit CV2 outputs logic signals O1 and O2 both indicating a high level, as shown in FIG. 8B.

[0138] The judgment circuit 40a judges whether the detection voltage Vdet is within the second range (Vref-dV3≦Vdet≦Vref+dV4) as shown in FIG. 8B based on the logic signals O3 and O4 output from the second conversion unit CV2, and outputs a judgment signal JD2 indicating the judgment result.

[0139] In this way, the second conversion unit CV2 and the judgment circuit 40a generate a judgment signal JD2 indicating whether the voltage value of the detection voltage Vdet is within a second range centered on the reference voltage Vref, which is wider than the first range, as shown in Figure 8B, or whether it is outside the second range.

[0140] That is, as shown in FIG. 8B, the voltage detection circuit 50_1 can obtain a judgment result (JD1) indicating whether the voltage value of the detection voltage Vdet is within a first range centered on the reference voltage Vref, as well as a judgment result (JD2) indicating whether the voltage value is within a second range wider than the first range.

[0141] In the above embodiment, the source type current I1 (I1a) is set to be larger than the sink type current I2 and the sink type current I4 (I4a) is set to be larger than the source type current I3 in the reference state, but the source type current I1 (I1a) may be set to be smaller than the sink type current I2 and the sink type current I4 (I4a) may be set to be smaller than the source type current I3.

[0142] In short, the voltage detection circuit according to the present invention includes at least the following differential stage and coupling circuit, and may further include a determination circuit.

[0143] The differential stages (10, 11 to 17, 11a to 13a) output a differential current pair (Is1, Is2) corresponding to the difference between a reference voltage (Vref) and a detection voltage (Vdet) to be detected.

[0144] The coupling circuits (30, 30A to 30C) have first and second voltages (VDD, VSS) and first and second coupling points (n5, n6), and output first and second signals (O1 or O3, O2 or O4) from the first and second coupling points (n5 or n5a, n6 or n6a) based on first to fourth currents (I1 or I1a, I2, I3, I4 or I4a) generated by current mirror conversion of the differential current pair (Is1, Is2) with respect to the first and second voltages (VDD, VSS), respectively. The coupling circuit also converts one of the differential current pairs (Is1) into first and third currents (I1 or I1a, I3) of a source type (current discharge type) based on a first voltage (VDD), converts the other of the differential current pairs (Is2) into second and fourth currents (I2, I4 or I4a) of a sink type based on a second voltage (VSS), generates a voltage generated at a first junction (n5 or n5a) where the first current (I1 or I1a) and the second current (I2) are coupled as a first signal (O1 or O3), and generates a voltage generated at a second junction (n6 or n6a) where the third current (I3) and the fourth current (I4 or I4a) are coupled as a second signal (O2 or O4). Furthermore, the coupling circuit is set so that in the reference state the first current (I1 or I1a) is greater than the second current (I2) and the fourth current (I4 or I4a) is greater than the third current (I3).

[0145] The judgment circuit (40, 40a) judges whether the detection voltage (Vdet) has fluctuated from the reference state (first range or second range) based on the first and second signals (O1 or O3, O2 or O4), and outputs a judgment signal (JD, JD1, JD2) indicating the judgment result.

[0146] FIG. 9 is a block diagram showing the configuration of a display device 200 according to a second embodiment of the present invention.

[0147] 9, the display device 200 includes a display panel 150 including gate lines GL1 to GLr (r is an integer of 2 or more) wired in the horizontal direction on an insulating substrate, data lines DL1 to DLk (k is an integer of 2 or more) wired in the vertical direction, and pixel units 154 arranged in a matrix at the intersections of the gate lines and data lines, and a controller 130. Note that a gate driver 110 that drives each gate line and a data driver 120_1 that drives each data line are connected to the display panel 150, and the controller 130 adjusts the output timing of these gate driver 110 and data driver 120_1.

[0148] The gate driver 110 receives a signal group GS from the controller 130 and outputs scanning signals to be supplied to each gate line based on the signal group GS. The gate driver 110 generally has a thin film transistor circuit configuration that is formed integrally with the pixel portion and wiring of the display panel 150.

[0149] The data driver 120_1 receives a video data signal VDS from the controller 130, which includes a clock signal, various control signals, and a video data signal, and outputs a grayscale voltage signal to be supplied to the data lines DL1 to DLk based on the video data signal VDS.

[0150] The data driver 120_1 is usually formed of a silicon LSI and is mounted on the edge of the display panel 150 using COG (chip on glass) or COF (chip on film). When the data driver 120_1 is composed of multiple individual ICs, a video data signal VDS including various control signals related to the data lines that each IC drives is supplied to each data driver IC from the controller 130. When the data driver 120_1 is a single IC or a small number of ICs, the controller 130 may be built into the data driver 120_1, in which case a group of signals supplied from outside to the controller 130 is directly supplied to the data driver 120_1.

[0151] FIG. 10 is a block diagram showing an example of the internal configuration of the data driver 120_1.

[0152] As shown in FIG. 10, the data driver 120_1 includes output sections 80_1 to 80_k that drive loads (data line loads) 90_1 to 90_k, each including a plurality of pixel sections 154, via data lines DL1 to DLk.

[0153] Furthermore, the data driver 120_1 includes at least the following voltage detection circuit 50, a selection switch group 54, a reference voltage setting section 55, a grayscale voltage generation section 70, and a control section 60.

[0154] The voltage detection circuit 50 detects whether or not there is an abnormality in the output voltage of each of the output units 80_1 to 80_k. The selection switch group 54 selects one of the output voltages output from the output units 80_1 to 80_k and supplies the selected output voltage to the voltage detection circuit 50 as a detection voltage Vdet. The reference voltage setting unit 55 sets a reference voltage Vref and supplies it to the voltage detection circuit 50. The control unit 60 generates pixel data PD1 to PDk representing the luminance level of each pixel for each horizontal scanning period based on a digital data signal (including video data and control signals) VDS supplied from an external device, and supplies each of the pixel data to the corresponding output units 80_1 to 80_k. Furthermore, the control unit 60 supplies a control signal ctla for controlling the voltage detection circuit 50, a control signal ctlb for controlling the selection switch group 54, and a control signal ctlc for controlling the reference voltage setting unit 55.

[0155] Each of the output units 80_1 to 80_k includes a level shifter (LS) that receives pixel data PD assigned to each output unit by the control unit 60 and converts the pixel data from a low voltage of the logic power supply level to a high voltage for driving a load, a digital-to-analog conversion circuit (DAC) that converts the gradation voltage group generated by the gradation voltage generation unit 70 into a corresponding gradation voltage signal based on a pixel data signal converted from the gradation voltage group generated by the gradation voltage generation unit 70 into a high voltage, an AMP that amplifies and outputs the gradation voltage signal, and an output SW that controls whether the gradation voltage signal output from the AMP is supplied to the load or not.

[0156] The first to k-th gray scale voltage signals output from the output sections 80_1 to 80_k are supplied to the loads 90_1 to 90_k via the output pads P1 to Pk.

[0157] The selection switch group 54 is composed of switches 54_1 to 54_k that select one of the k grayscale voltage signals output from each output unit and supply it as a detection voltage Vdet to the voltage detection circuit 50. The selection control and inactivation control (turning off all of the switches 54_1 to 54_k) of the selection switch group 54 are controlled by a control signal ctla from the control unit 60.

[0158] 2A, 3, 4, etc., including a differential stage 10, a coupling circuit 30, and a determination circuit 40. The detection operation of the voltage detection circuit 50 is controlled by a control signal ctlb from the control unit 60.

[0159] The reference voltage setting unit 55 inputs a gradation voltage to be used as a reference voltage for voltage detection from the gradation voltage group generated by the gradation voltage generation unit 70, and supplies the gradation voltage specified by the control signal ctlc from the control unit 60 to the voltage detection circuit 50 as the reference voltage Vref.

[0160] The control unit 60 controls a display mode in which grayscale voltage signals corresponding to video data are output to the data lines DL1 to DLk to display a video on the display panel 150, and a detection mode in which the control unit 60 detects whether the grayscale signals supplied to the first to kth data lines are normal. In the display mode, the output SWs of the output units 80_1 to 80_k are turned on, and grayscale voltage signals are supplied from the amplifiers AMP to the data lines DL1 to DLk. In the display mode, the voltage detection circuit 50 and the selection switch group 54 are inactivated. On the other hand, the detection mode is generally set during a period that does not overlap with the display mode. Below, we will explain the operation of the voltage detection circuit 50 and the control unit 60 in the detection mode to detect voltage abnormalities in the grayscale signals output by each of the output units 80_1 to 80_k.

[0161] In this case, the control unit 60 first supplies a control signal ctlb to the voltage detection circuit 50 to instruct it to perform the detection operation, and also specifies pixel data PD1 to PDk so that each of the output units 80_1 to 80_k outputs a gradation voltage signal having the same voltage value as the reference voltage Vref. Next, the control unit 60 controls the selection switch group 54 to sequentially select the k gradation voltage signals output from the output units 80_1 to 80_k one by one. As a result, one gradation voltage signal selected by the selection switch group 54 is supplied to the voltage detection circuit 50 as the detection voltage Vdet, and the voltage detection circuit 50 determines whether the detection voltage Vdet is in a reference state (a voltage value equal to or close to the reference voltage Vref). A determination signal JD indicating the determination result is then fed back to the control unit 60. The control unit 60 has an abnormality avoidance processing function that, upon receiving the determination signal JD, activates a means for notifying an abnormality or stops the data driver 120_1 when an abnormality is determined.

[0162] The grayscale voltage signal extracted as the detection voltage Vdet from each output section is preferably the voltage at the connection point between the output terminal of the amplifier AMP and the output SW. In this case, if the detection operation is performed with the output SW turned on, an abnormality on the load side (such as a short circuit between the loads) can be detected. Also, if the detection operation is performed with the output SW turned off, an abnormality in the data driver 120_1 can be detected. Furthermore, by performing these processes together, it is possible to determine which of the loads 90_1 to 90_k has an abnormality, even if there is no abnormality in the wiring connecting the data driver 120_1 and the loads 90_1 to 90_k.

[0163] Furthermore, it is preferable that the voltage abnormality detection operation described above be performed during a blanking period when the display device 200 is turned on or between single-screen display operations. Alternatively, the output units 80_1 to 80_k may be divided into a plurality of output groups, and the output group to be subjected to the detection operation may be switched in sequence for each blanking period.

[0164] As described above in detail, the data driver 120_1 shown in FIG. 10 can perform voltage abnormality detection for multiple gradation voltage signals output from multiple output units (80_1 to 80_k) that drive multiple loads (90_1 to 90_k) using only one shared voltage detection circuit 50.

[0165] Furthermore, in the voltage detection circuit 50, only the differential stage 10 is configured with high-voltage elements for detecting high-voltage signals, while the coupling circuit 30 and the determination circuit 40 are configured with low-voltage elements, thereby enabling area savings. Furthermore, the voltage detection circuit 50 can determine whether the voltage to be detected is normal or abnormal with a single detection operation, allowing for a simple circuit configuration that does not require a complex control circuit.

[0166] 10 illustrates an example of an operation for detecting voltage abnormalities in grayscale voltage signals output from each output section of a data driver included in a display device, but the devices subject to voltage abnormality detection are not limited to data drivers of display devices. In other words, the selection switch group 54 and voltage detection circuit 50 may be provided in electronic devices that handle, for example, multiple control voltages or set voltages other than load-driving voltages such as display grayscale voltage signals. By employing the voltage detection circuit of the present invention, it is possible to reduce the area required for detection voltages that fall within a high-voltage range.

[0167] FIG. 11 is a circuit diagram showing the configuration of a comparator 51 according to a third embodiment of the present invention.

[0168] The comparator 51 compares a high-voltage reference voltage Vref with a high-voltage detection voltage Vdet, and outputs a comparison result signal O1 that represents the comparison result, in terms of the level of the low-voltage logic power supply voltage, indicating whether the detection voltage Vdet is greater (or less) than the reference voltage Vref.

[0169] The configuration of the comparator 51 shown in Fig. 11 is the same as that of the voltage detection circuit 50 shown in Fig. 2A except that the transistors 25 and 35 are omitted. However, in the comparator 51, the current driving capabilities of the transistors 24 and 34 are the same.

[0170] The comparator 51 includes the following differential stage 10 and coupling circuit 30D.

[0171] The differential stage 10 generates a pair of differential currents (Is1, Is2) corresponding to the difference between the reference voltage Vref and the detection voltage Vdet. The differential stage 10 is a high-voltage circuit that receives a high-potential analog power supply voltage AVDD and an analog ground voltage AVSS and is composed of high-voltage elements that operate at a voltage between AVDD and AVSS.

[0172] The coupling circuit 30D includes N-channel MOS transistors 21, 22, 33, and 34 and P-channel MOS transistors 23 and 24.

[0173] The drain and gate of transistor 21 are connected to node n1, and its source is connected to the VSS power supply terminal. The gate of transistor 22 is connected to the gate of transistor 21, and its source is connected to the VSS power supply terminal. Furthermore, the drain of transistor 22 is connected to the drain and gate of transistor 23. The source of transistor 23 is connected to the VDD power supply terminal. The source of transistor 24 is connected to the VDD power supply terminal, and its gate is connected to the gate of transistor 23 via node n3. The drain and gate of transistor 33 are connected to node n2, and its source is connected to the VSS power supply terminal. The source of transistor 34 is connected to the VSS power supply terminal, and its gate is connected to the gate of transistor 33 via node n2. The drain of transistor 34 is connected to the drain of transistor 24 via node n5. A signal having the voltage generated at node n5 is output from node n5 as the above-mentioned comparison result signal O1.

[0174] In this configuration, when the detection voltage Vdet is lower than the reference voltage Vref (Vdet<Vref), the coupling circuit 30D outputs a low-level (VSS) logic signal O1. On the other hand, when the detection voltage Vdet is higher than the reference voltage Vref (Vdet>Vref), the coupling circuit 30D outputs a high-level (VDD) comparison result signal O1.

[0175] 11, one of the differential output currents Is1 and Is2 of the differential stage 10 is converted into a source-type and sink-type current pair, and the current pairs are coupled together. A comparison result signal O1 representing the comparison result is generated from the coupling point. When a voltage difference occurs between the reference voltage Vref and the detection voltage Vdet, one of the differential output currents Is1 and Is2 increases and the other decreases. Therefore, the voltage at the output end (node ​​n5) of the coupling circuit 30D quickly changes to the logic power supply voltage VDD or the logic ground voltage VSS.

[0176] That is, the comparison result signal O1 output from the coupling circuit 30D is quickly determined to a level that indicates the result of the comparison with the reference voltage Vref in response to the input of the detection voltage Vdet.

[0177] Furthermore, with the configuration shown in FIG. 11, particularly when a high-voltage signal is compared with a reference voltage and the comparison result is output as a low-voltage signal at a logical level, it is possible to reduce the area since only the differential stage 10 needs to be formed from high-voltage elements.

[0178] 10 Differential stage 30, 30A to 30C Coupling circuit 40, 40a Determination circuit 50, 50_1 Voltage detection circuit 51 Comparator 60 Determination circuit 120_1 Data driver 200 Display device

Claims

1. A voltage detection circuit that detects that a detection voltage of a detection target has changed from a reference state having a voltage value within a predetermined voltage range including a reference voltage, a differential stage for outputting a differential current pair corresponding to a difference between the reference voltage and the detection voltage; a coupling circuit having first and second voltages and first and second coupling points, and outputting first and second signals from the first and second coupling points based on first to fourth currents generated by current mirror converting the differential current pair with respect to the first and second voltages, respectively; the coupling circuit converts one of the differential current pair into the first and third currents that are one of a source type and a sink type based on the first voltage, converts the other of the differential current pair into the second and fourth currents that are the other of a source type and a sink type based on the second voltage, generates a voltage generated at the first coupling point where the first current and the second current are coupled as the first signal, and generates a voltage generated at the second coupling point where the third current and the fourth current are coupled as the second signal; The voltage detection circuit, wherein the coupling circuit is set such that, in the reference state, the first current is greater than the second current and the fourth current is greater than the third current.

2. 2. The voltage detection circuit according to claim 1, further comprising a determination circuit that determines whether or not the detection voltage has deviated from the reference state based on the first and second signals output from the coupling circuit, and outputs a determination signal indicative of the determination result.

3. 3. The voltage detection circuit according to claim 1, wherein the determination circuit determines that the detection voltage is in the reference state when the first and second signals have different logical values, and determines that the detection voltage has fluctuated from the reference state when the first and second signals have the same logical value.

4. the coupling circuit operates within a first voltage range consisting of the first voltage and the second voltage; the differential stage operates within a second voltage range consisting of one of the first voltage and the second voltage and a third voltage; 3. The voltage detection circuit according to claim 1, wherein the second voltage range is set to be larger than the first voltage range.

5. the differential stage is formed of a high-voltage element that operates on a high-voltage power supply voltage that is higher than a low-voltage power supply voltage consisting of the first voltage and the second voltage, 3. The voltage detection circuit according to claim 1, wherein the coupling circuit is formed of low-voltage elements that operate on the low-voltage power supply voltage.

6. 3. The voltage detection circuit according to claim 1, wherein the coupling circuit generates the first current and the third current, respectively, by performing two current mirror conversions of one of the differential current pairs based on the second voltage and the first voltage, and generates the second current and the fourth current, respectively, by performing one current mirror conversion of the other of the differential current pairs based on the second voltage.

7. The coupling circuit includes: a first transistor circuit that receives the first voltage and outputs a current corresponding to the one of the differential current pair as the first current to the first node; a second transistor circuit that receives the second voltage and outputs a current corresponding to the other of the differential current pair as the second current to the first node; a third transistor circuit that receives the first voltage and outputs a current corresponding to the one of the differential current pair as the third current to the second node; a fourth transistor circuit that receives the second voltage and outputs a current corresponding to the other of the differential current pair as the fourth current to the second node, at least one of the first transistor circuit and the second transistor circuit includes a plurality of transistors that are individually controlled to be active or inactive and connected in parallel, and generates, as the first current or the second current, a composite current obtained by combining currents output from transistors that are controlled to be active among the plurality of transistors; 3. The voltage detection circuit according to claim 1, wherein at least one of the third transistor circuit and the fourth transistor circuit includes a plurality of transistors whose activation / deactivation is individually controlled and connected in parallel, and the third current or the fourth current is generated by combining currents output from each of the plurality of transistors that are controlled to be active.

8. The coupling circuit includes: a first transistor circuit that receives the first voltage and outputs a current corresponding to the one of the differential current pair as the first current to the first node; a second transistor circuit that receives the second voltage and outputs a current corresponding to the other of the differential current pair as the second current to the first node; a third transistor circuit that receives the first voltage and outputs a current corresponding to the one of the differential current pair as the third current to the second node; a fourth transistor circuit that receives the second voltage and outputs a current corresponding to the other of the differential current pair as the fourth current to the second node, the first transistor circuit includes a first transistor that outputs a current obtained by current mirror conversion of one of the differential current pair, and a first current source that is connected in parallel with the first transistor and is capable of variably controlling a current value, and generates, as the first current, a composite current obtained by combining a current output from the first current source and a current output from the first transistor; 3. The voltage detection circuit according to claim 1, wherein the fourth transistor circuit includes a second transistor that outputs a current obtained by current mirror conversion of the other of the differential current pair, and a second current source that is connected in parallel with the second transistor and is capable of variably controlling a current value, and generates a composite current as the fourth current by combining the current output from the second current source and the current output from the second transistor.

9. A display driver that generates a grayscale signal corresponding to a luminance level of each pixel based on a video data signal and supplies the first to k-th grayscale signals to first to k-th (k is an integer equal to or greater than 2) data lines of a display panel, a display mode for displaying an image on the display panel, and a detection mode for detecting whether the grayscale signals supplied to the first to kth data lines are normal or not; a setting unit that sets a voltage value of a grayscale signal corresponding to a predetermined luminance level to a reference voltage; a selection unit that selects one of the first to kth grayscale signals in the detection mode and acquires a voltage value of the selected one grayscale signal as a detection voltage; and a voltage detection circuit that detects whether the detection voltage has deviated from a reference state having a voltage value within a predetermined voltage range including the reference voltage, The voltage detection circuit includes: a differential stage for outputting a differential current pair corresponding to a difference between the reference voltage and the detection voltage; a coupling circuit having first and second voltages and first and second coupling points, and outputting first and second signals from the first and second coupling points based on first to fourth currents generated by current mirror converting the differential current pair with respect to the first and second voltages, respectively; a determination circuit that determines whether or not the detection voltage has deviated from the reference state based on the first and second signals and outputs a determination signal indicative of a determination result; the coupling circuit converts one of the differential current pair into the first and third currents that are one of a source type and a sink type based on the first voltage, converts the other of the differential current pair into the second and fourth currents that are the other of a source type and a sink type based on the second voltage, generates a voltage generated at the first coupling point where the first current and the second current are coupled as the first signal, and generates a voltage generated at the second coupling point where the third current and the fourth current are coupled as the second signal; The display driver is characterized in that, in the coupling circuit, in the reference state, the first current is set to be larger than the second current and the fourth current is set to be larger than the third current.

10. 10. The display driver according to claim 9, further comprising a control section that controls the selection section so as to select the first to k-th grayscale signals one by one at a predetermined timing.

11. 11. The display driver according to claim 9, wherein the voltage detection circuit operates only during a period in which the first to kth grayscale signals are not supplied to the first to kth data lines of the display panel.

12. a display panel having first to k-th (k is an integer of 2 or more) data lines, each of which has a plurality of pixel units formed thereon; a display driver that generates a grayscale signal corresponding to a luminance level of each pixel based on a video data signal and supplies the first to kth grayscale signals (k is an integer equal to or greater than 2) to the first to kth data lines of the display panel, respectively; The display driver includes: a display mode for displaying an image on the display panel and a detection mode for detecting whether the grayscale signals supplied to the first to kth data lines are normal or not, a setting unit for setting a voltage value of the grayscale signal corresponding to a predetermined luminance level to a reference voltage; a selection unit that selects one of the first to kth grayscale signals in the detection mode and obtains a voltage value of the selected one grayscale signal as a detection voltage; a control unit that controls the selection unit to periodically select the first to k-th grayscale signals one by one in sequence; a voltage detection circuit that detects whether the detection voltage varies from a reference state having a voltage value within a predetermined voltage range including the reference voltage; The voltage detection circuit includes: a differential stage for outputting a differential current pair corresponding to a difference between the reference voltage and the detection voltage; a coupling circuit having first and second voltages and first and second coupling points, and outputting first and second signals from the first and second coupling points based on first to fourth currents generated by current mirror converting the differential current pair with respect to the first and second voltages, respectively; a determination circuit that determines whether or not the detection voltage has deviated from the reference state based on the first and second signals and outputs a determination signal indicative of a determination result; the coupling circuit converts one of the differential current pair into the first and third currents that are one of a source type and a sink type based on the first voltage, converts the other of the differential current pair into the second and fourth currents that are the other of a source type and a sink type based on the second voltage, generates a voltage generated at the first coupling point where the first current and the second current are coupled as the first signal, and generates a voltage generated at the second coupling point where the third current and the fourth current are coupled as the second signal; The display device according to claim 1, wherein the coupling circuit is set so that, in the reference state, the first current is greater than the second current and the fourth current is greater than the third current.

13. A comparator that receives an input voltage and a reference voltage and outputs a comparison result indicating whether the input voltage is greater than the reference voltage, a differential stage for outputting a differential current pair corresponding to a difference between the reference voltage and the input voltage; a circuit section having first and second voltages and an output terminal, and outputting the comparison result signal from the output terminal based on first and second currents generated by current mirror converting the differential current pair with respect to the first and second voltages, respectively; a comparator characterized in that the circuit unit converts one of the differential current pair to the first current that is one of a source type and a sink type based on the first voltage, converts the other of the differential current pair to the second current that is the other of a source type and a sink type based on the second voltage, and generates, as the comparison result signal, a voltage generated at the output terminal where the first current and the second current are combined.

14. the circuit portion operates within a first voltage range that is made up of the first voltage and the second voltage; the differential stage operates within a second voltage range consisting of one of the first voltage and the second voltage and a third voltage; 14. The comparator according to claim 13, wherein the second voltage range is set to be larger than the first voltage range.

15. the differential stage is formed of a high-voltage element that operates on a high-voltage power supply voltage that is higher than a low-voltage power supply voltage consisting of the first voltage and the second voltage, 15. The comparator according to claim 13, wherein the coupling circuit is formed of low-voltage elements that operate at the low power supply voltage.