Display device

Abstract

The present invention provides a display device less susceptible to noise. This display device comprises a signal line drive circuit, a demultiplexer circuit, and pixels. The demultiplexer circuit has a transistor in which a semiconductor layer is provided within an opening formed in an interlayer insulating layer on a substrate. A first conductive layer provided under the opening is used as one of a source electrode and a drain electrode of the transistor, and a second conductive layer covering a side surface of the opening in plan view is used as the other of the source electrode and the drain electrode. The first conductive layer is electrically connected with the pixels, and the second conductive layer is electrically connected with the signal line drive circuit.

Description

display device

[0001] 1. Field of the Invention One embodiment of the present invention relates to a display device, a semiconductor device, a display module, and an electronic device. 2. Description of the Related Art One embodiment of the present invention relates to a method for manufacturing a display device and a method for manufacturing a semiconductor device.

[0002] One embodiment of the present invention is not limited to the above technical field, and examples of the technical field of one embodiment of the present invention include a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, an electronic device, a lighting device, an input device (for example, a touch sensor), an input / output device (for example, a touch panel), a driving method thereof, or a manufacturing method thereof.

[0003] Semiconductor devices having transistors are widely used in display devices and electronic devices, and there is a demand for higher integration and higher speed of the semiconductor devices. For example, when a semiconductor device is applied to a high-resolution display device, a highly integrated semiconductor device is required. As one means for increasing the integration degree of transistors, the development of fine-sized transistors is underway.

[0004] In recent years, there has been a demand for display devices applicable to virtual reality (VR), augmented reality (AR), substitutional reality (SR), or mixed reality (MR). VR, AR, SR, and MR are collectively referred to as XR (Extended Reality). Display devices for XR are desired to have high resolution and high color reproducibility in order to enhance the sense of realism and immersion. Examples of display devices applicable to such devices include liquid crystal display devices, organic electroluminescence (EL) elements, and light-emitting devices equipped with light-emitting elements such as light-emitting diodes (LEDs).

[0005] Patent Document 1 discloses a display device for VR that uses an organic EL element (also called an organic EL device).

[0006] International Publication No. 2018 / 087625

[0007] As display devices become higher in definition, the impact of noise on the driving of the display device increases. For example, if image data generated by a signal line driver circuit is affected by noise before being supplied to pixels, the displayed image may be affected by the noise, resulting in a decrease in display quality of the display device.

[0008] Therefore, an object of one embodiment of the present invention is to provide a display device that is less affected by noise and a manufacturing method thereof. Another object of one embodiment of the present invention is to provide a display device with high display quality and a manufacturing method thereof. Another object of one embodiment of the present invention is to provide a high-resolution display device and a manufacturing method thereof. Another object of one embodiment of the present invention is to provide a small-sized display device and a manufacturing method thereof. Another object of one embodiment of the present invention is to provide a display device with a narrow frame and a manufacturing method thereof. Another object of one embodiment of the present invention is to provide a display device including a micro-sized transistor and a manufacturing method thereof. Another object of one embodiment of the present invention is to provide a display device including a transistor with high on-state current and a manufacturing method thereof. Another object of one embodiment of the present invention is to provide a display device with favorable electrical characteristics and a manufacturing method thereof. Another object of one embodiment of the present invention is to provide a novel semiconductor device and a manufacturing method thereof.

[0009] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Note that problems other than these can be extracted from the description of the specification, drawings, claims, etc.

[0010] One embodiment of the present invention includes a signal line driver circuit, a transistor, a first insulating layer, and a pixel. The transistor includes a first conductive layer, a second conductive layer, a third conductive layer, a semiconductor layer, and a second insulating layer. The first insulating layer is provided over the first conductive layer. The second conductive layer is provided over the first insulating layer. The first insulating layer has a first opening reaching the first conductive layer. The second conductive layer has a second opening having a region overlapping with the first opening. The semiconductor layer has a region in contact with the first conductive layer and a region in contact with the second conductive layer. and is provided so as to have a region located inside the first opening and a region located inside the second opening, the second insulating layer is provided on the semiconductor layer so as to have a region located inside the first opening and a region located inside the second opening, the third conductive layer is provided on the second insulating layer so as to have a region located inside the first opening and a region located inside the second opening, the first conductive layer is electrically connected to pixels, and the second conductive layer is electrically connected to a signal line driver circuit.

[0011] Alternatively, one embodiment of the present invention includes a signal line driver circuit, a first transistor, a second transistor, a first insulating layer, a first pixel, and a second pixel. The first transistor includes a first conductive layer, a second conductive layer, a third conductive layer, a first semiconductor layer, and a second insulating layer. The second transistor includes a second conductive layer, a fourth conductive layer, a fifth conductive layer, a second semiconductor layer, and a second insulating layer. The first insulating layer is a first conductive layer. the second conductive layer is provided on the first insulating layer, the first insulating layer having a first opening reaching the first conductive layer and a second opening reaching the fourth conductive layer, the second conductive layer having a third opening having a region overlapping with the first opening and a fourth opening having a region overlapping with the second opening, and the first semiconductor layer has a region in contact with the first conductive layer and a region in contact with the second conductive layer, and is located inside the first opening. the second semiconductor layer has a region in contact with the second conductive layer and a region in contact with the fourth conductive layer and also has a region located inside the second opening and a region located inside the fourth opening; the second insulating layer is provided on the first semiconductor layer and the second semiconductor layer so as to have a region located inside the first to fourth openings, respectively; the third conductive layer is provided on the second insulating layer so as to have a region located inside the first opening and a region located inside the third opening; the fifth conductive layer is provided on the second insulating layer so as to have a region located inside the second opening and a region located inside the fourth opening; the first conductive layer is electrically connected to the first pixel, the fourth conductive layer is electrically connected to the second pixel, and the second conductive layer is electrically connected to a signal line driver circuit.

[0012] Another embodiment of the present invention includes a signal line driver circuit, a first transistor, a second transistor, a third transistor, a fourth transistor, a first insulating layer, a first pixel, a second pixel, a third pixel, and a fourth pixel. The first transistor includes a first conductive layer, a second conductive layer, a third conductive layer, a first semiconductor layer, and a second insulating layer. The second transistor includes a second conductive layer, a fourth conductive layer, a fifth conductive layer, a second semiconductor layer, and a second insulating layer. The third transistor includes a third conductive layer, a sixth conductive layer, and a seventh conductive layer. the fourth transistor has a fifth conductive layer, a seventh conductive layer, an eighth conductive layer, a fourth semiconductor layer, and a second insulating layer; the first insulating layer is provided on the first conductive layer, the fourth conductive layer, the sixth conductive layer, and the eighth conductive layer; the second conductive layer and the seventh conductive layer are provided on the first insulating layer; the first insulating layer has a first opening reaching the first conductive layer, a second opening reaching the fourth conductive layer, a third opening reaching the sixth conductive layer, and a fourth opening reaching the eighth conductive layer; and the second conductive layer overlaps the first opening. the seventh conductive layer has a seventh opening having a region overlapping with the third opening and an eighth opening having a region overlapping with the fourth opening; the first semiconductor layer has a region in contact with the first conductive layer and a region in contact with the second conductive layer, and is provided with a region located inside the first opening and a region located inside the fifth opening; the second semiconductor layer has a region in contact with the second conductive layer and a region in contact with the fourth conductive layer, and is provided with a region located inside the second opening and a region located inside the sixth opening. the third semiconductor layer has a region in contact with the sixth conductive layer and a region in contact with the seventh conductive layer, and has a region located inside the third opening and a region located inside the seventh opening; the fourth semiconductor layer has a region in contact with the seventh conductive layer and a region in contact with the eighth conductive layer, and has a region located inside the fourth opening and a region located inside the eighth opening; the second insulating layer is formed on the first semiconductor layer, the second semiconductor layer, and the third insulating layer has a region in contact with the sixth conductive layer and a region in contact with the seventh conductive layer, and has a region located inside the fourth opening and a region located inside the eighth opening,a display device provided on a third semiconductor layer and a fourth semiconductor layer, the third conductive layer being provided on the second insulating layer so as to have a region located inside the first opening, a region located inside the third opening, a region located inside the fifth opening, and a region located inside the seventh opening; the fifth conductive layer being provided on the second insulating layer so as to have a region located inside the second opening, a region located inside the fourth opening, a region located inside the sixth opening, and a region located inside an eighth opening; the first conductive layer being electrically connected to the first pixel, the fourth conductive layer being electrically connected to the second pixel, the sixth conductive layer being electrically connected to the third pixel, the eighth conductive layer being electrically connected to the fourth pixel; and the second conductive layer and the seventh conductive layer being electrically connected to a signal line driver circuit.

[0013] Alternatively, in the above aspect, the first to fourth semiconductor layers may each contain a metal oxide, which may contain indium, zinc, and M (M is one or more elements selected from aluminum, titanium, gallium, germanium, tin, yttrium, zirconium, lanthanum, cerium, neodymium, and hafnium).

[0014] Alternatively, in the above aspect, the display device may include a control circuit having a function of generating a first signal and outputting it to the third conductive layer, and the control circuit may have a function of generating a second signal and outputting it to the fifth conductive layer, and the first signal and the second signal may be complementary to each other.

[0015] According to one embodiment of the present invention, a display device that is less affected by noise and a manufacturing method thereof can be provided. According to one embodiment of the present invention, a display device with high display quality and a manufacturing method thereof can be provided. According to one embodiment of the present invention, a high-resolution display device and a manufacturing method thereof can be provided. According to one embodiment of the present invention, a small-sized display device and a manufacturing method thereof can be provided. According to one embodiment of the present invention, a display device with a narrow frame and a manufacturing method thereof can be provided. According to one embodiment of the present invention, a display device including a micro-sized transistor and a manufacturing method thereof can be provided. According to one embodiment of the present invention, a display device including a transistor with high on-state current and a manufacturing method thereof can be provided. According to one embodiment of the present invention, a display device with favorable electrical characteristics and a manufacturing method thereof can be provided. According to one embodiment of the present invention, a novel semiconductor device and a manufacturing method thereof can be provided.

[0016] Note that the description of these effects does not preclude the existence of other effects. One embodiment of the present invention does not necessarily have all of these effects. Effects other than these can be extracted from the description in the specification, drawings, and claims.

[0017] FIG. 1 is a block diagram showing an example of the configuration of a display device. FIGS. 2A1 to 2A3 are plan views showing an example of the configuration of a display device. FIG. 2B is a cross-sectional view showing an example of the configuration of a display device. FIG. 3A is a plan view showing an example of the configuration of a display device. FIG. 3B is a cross-sectional view showing an example of the configuration of a display device. FIG. 4A is a plan view showing an example of the configuration of a display device. FIG. 4B is a cross-sectional view showing an example of the configuration of a display device. FIGS. 5A to 5C are plan views showing an example of the configuration of a display device. FIG. 6A is a plan view showing an example of the configuration of a display device. FIG. 6B is a cross-sectional view showing an example of the configuration of a display device. FIG. 7A is a plan view showing an example of the configuration of a display device. FIG. 7B is a cross-sectional view showing an example of the configuration of a display device. FIG. 8A is a plan view showing an example of the configuration of a display device. FIGS. 8B1 to 8B3 are cross-sectional views showing an example of the configuration of a display device. FIGS. 9A and 9B are plan views showing an example of the configuration of a display device. FIGS. 10A1 and 10A2 are plan views showing an example of the configuration of a display device. FIG. 10B is a cross-sectional view showing an example of the configuration of a display device. FIG. 11A is a plan view showing an example of the configuration of a display device. FIG. 11B is a cross-sectional view showing an example of the configuration of a display device. FIG. 12A is a plan view showing an example of the configuration of a display device. FIG. 12B is a cross-sectional view showing an example of the configuration of a display device. FIG. 13A is a plan view showing an example of the configuration of a display device. FIG. 13B is a cross-sectional view showing an example of the configuration of a display device. FIGS. 14A1 and 14A2 are plan views showing an example of the configuration of a display device. FIG. 14B is a cross-sectional view showing an example of the configuration of a display device. FIG. 15A is a plan view showing an example of the configuration of a display device. FIG. 15B is a cross-sectional view showing an example of the configuration of a display device. FIG. 16A is a plan view showing an example of the configuration of a display device. FIG. 16B is a cross-sectional view showing an example of the configuration of a display device. FIGS. 17A and 17B are plan views showing an example of the configuration of a display device. FIGS. 18A1 and 18A2 are plan views showing an example of the configuration of a display device. FIG. 18B is a cross-sectional view showing an example of the configuration of a display device. FIG. 19A is a plan view showing an example of the configuration of a display device. FIGS. 19B1 and 19B2 are cross-sectional views showing an example of the configuration of a display device. 20A and 20B are cross-sectional views showing a configuration example of a display device, 21A and 21B are cross-sectional views showing a configuration example of a display device, and 22A and 22B are cross-sectional views showing a configuration example of a display device.FIG. 23A is a plan view showing an example of the configuration of a display device. FIG. 23B is a cross-sectional view showing an example of the configuration of a display device. FIGS. 24A and 24B are plan views showing an example of the configuration of a display device. FIG. 25A is a plan view showing an example of the configuration of a display device. FIG. 25B is a cross-sectional view showing an example of the configuration of a display device. FIGS. 26A to 26C are plan views showing an example of the configuration of a display device. FIGS. 27A to 27C are plan views showing an example of the configuration of a display device. FIGS. 28A and 28B are plan views showing an example of the configuration of a display device. FIG. 29A is a plan view showing an example of the configuration of a display device. FIG. 29B is a cross-sectional view showing an example of the configuration of a display device. FIG. 30A is a plan view showing an example of the configuration of a display device. FIG. 30B is a cross-sectional view showing an example of the configuration of a display device. FIG. 31A is a plan view showing an example of the configuration of a display device. FIG. 31B is a cross-sectional view showing an example of the configuration of a display device. FIGS. 32A to 32C are plan views showing an example of the configuration of a display device. FIGS. 33A and 33B are plan views showing an example of the configuration of a display device. FIG. 34A is a plan view showing a structural example of a display device. FIG. 34B is a cross-sectional view showing a structural example of a display device. FIGS. 35A1 and 35A2 are plan views showing a structural example of a display device. FIG. 35B is a cross-sectional view showing a structural example of a display device. FIG. 36A is a plan view showing a structural example of a display device. FIG. 36B is a cross-sectional view showing a structural example of a display device. FIG. 37A is a plan view showing a structural example of a display device. FIG. 37B is a cross-sectional view showing a structural example of a display device. FIG. 38A is a plan view showing a structural example of a display device. FIG. 38B is a cross-sectional view showing a structural example of a display device. FIGS. 39A to 39C are plan views showing a structural example of a display device. FIGS. 40A to 40C are plan views showing a structural example of a display device. FIGS. 41A and 41B are plan views showing a structural example of a display device. FIG. 42A is a plan view showing a structural example of a display device. FIG. 42B is a cross-sectional view showing a structural example of a display device. FIGS. 43A1 and 43B1 are plan views showing an example of a method for manufacturing a display device. 43A2 and 43B2 are cross-sectional views illustrating an example of a method for manufacturing a display device. 44A1 and 44B1 are plan views illustrating an example of a method for manufacturing a display device. 44A2 and 44B2 are cross-sectional views illustrating an example of a method for manufacturing a display device.FIGS. 45A1 and 45B1 are plan views showing an example of a method for manufacturing a display device. FIGS. 45A2 and 45B2 are cross-sectional views showing an example of a method for manufacturing a display device. FIGS. 46A1 and 46B1 are plan views showing an example of a method for manufacturing a display device. FIGS. 46A2 and 46B2 are cross-sectional views showing an example of a method for manufacturing a display device. FIGS. 47A1 and 47B1 are plan views showing an example of a method for manufacturing a display device. FIGS. 47A2 and 47B2 are cross-sectional views showing an example of a method for manufacturing a display device. FIG. 48 is a plan view showing an example of a configuration of a display device. FIGS. 49A to 49E are circuit diagrams showing an example of a configuration of a pixel. FIG. 50A is a plan view showing an example of a configuration of a display device. FIG. 50B is a cross-sectional view showing an example of a configuration of a display device. FIG. 51A is a plan view showing an example of a configuration of a display device. FIG. 51B is a cross-sectional view showing an example of a configuration of a display device. FIG. 52A is a block diagram showing an example of a configuration of a memory device. FIGS. 52B to 52F are circuit diagrams showing an example of a configuration of a memory cell. 53A to 53G are plan views showing configuration examples of pixels. FIGS. 54A to 54K are plan views showing configuration examples of pixels. FIG. 55 is a perspective view showing a configuration example of a display device. FIG. 56 is a cross-sectional view showing a configuration example of a display device. FIG. 57A is a cross-sectional view showing a configuration example of a display device. FIGS. 57B and 57C are cross-sectional views showing configuration examples of transistors. FIG. 58 is a cross-sectional view showing a configuration example of a display device. FIG. 59 is a cross-sectional view showing a configuration example of a display device. FIG. 60 is a cross-sectional view showing a configuration example of a display device. FIGS. 61A to 61F are cross-sectional views showing configuration examples of light-emitting elements. FIGS. 62A to 62C are cross-sectional views showing configuration examples of light-emitting elements. FIGS. 63A to 63D are diagrams showing an example of an electronic device. FIGS. 64A to 64F are diagrams showing an example of an electronic device. FIGS. 65A to 65G are diagrams showing an example of an electronic device.

[0018] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be readily understood by those skilled in the art that various changes can be made in form and detail without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below.

[0019] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations thereof will be omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be assigned.

[0020] For ease of understanding, the position, size, range, etc. of each component shown in the drawings may not represent the actual position, size, range, etc. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings.

[0021] It should be noted that the terms "film" and "layer" can be interchangeable in some cases or depending on the situation. For example, the term "conductive layer" can be changed to the term "conductive film." Or, for example, the term "insulating film" can be changed to the term "insulating layer."

[0022] Furthermore, the terms "electrode" and "wiring" used in this specification and the like do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wiring," and vice versa. Furthermore, the terms "electrode" and "wiring" also include cases where multiple "electrodes" or "wirings" are integrally formed.

[0023] In this specification and the like, a structure in which at least light-emitting layers are separately formed for light-emitting elements with different emission wavelengths may be referred to as an SBS (Side By Side) structure. The SBS structure allows the materials and configuration to be optimized for each light-emitting element, increasing the degree of freedom in selecting materials and configurations and facilitating improvements in brightness and reliability.

[0024] In this specification and the like, holes or electrons may be referred to as "carriers." Specifically, a hole injection layer or an electron injection layer may be referred to as a "carrier injection layer," a hole transport layer or an electron transport layer may be referred to as a "carrier transport layer," and a hole block layer or an electron block layer may be referred to as a "carrier block layer." Note that the above-mentioned carrier injection layer, carrier transport layer, and carrier block layer may not be clearly distinguishable from each other depending on their cross-sectional shapes, properties, etc. Furthermore, one layer may have two or three functions among the carrier injection layer, carrier transport layer, and carrier block layer.

[0025] In this specification and the like, a light-emitting element (also referred to as a light-emitting device) has an EL layer between a pair of electrodes. The EL layer has at least a light-emitting layer. Here, examples of layers (also referred to as functional layers) included in the EL layer include a light-emitting layer, a carrier injection layer (a hole injection layer and an electron injection layer), a carrier transport layer (a hole transport layer and an electron transport layer), and a carrier block layer (a hole block layer and an electron block layer).

[0026] In this specification and the like, a light-receiving element (also referred to as a light-receiving device) has at least an active layer that functions as a photoelectric conversion layer between a pair of electrodes.

[0027] In this specification, the term "island-like" refers to a state in which two or more layers made of the same material and formed in the same process are physically separated. For example, an island-like light-emitting layer refers to a state in which the light-emitting layer is physically separated from an adjacent light-emitting layer.

[0028] In this specification, a tapered shape refers to a shape in which at least a portion of the side surface of a structure is inclined relative to the substrate surface or the surface to be formed. For example, it is preferable to have a region in which the angle (also called the taper angle) between the inclined side surface and the substrate surface or the surface to be formed is less than 90 degrees. Note that the side surface of the structure, the substrate surface, and the surface to be formed do not necessarily have to be completely flat, and may be approximately planar with a slight curvature or approximately planar with a slight unevenness.

[0029] In this specification and the like, a mask layer (also referred to as a sacrificial layer) refers to a layer that is located at least above a light-emitting layer (more specifically, a layer that is processed into an island shape among the layers that constitute the EL layer) and has the function of protecting the light-emitting layer during the manufacturing process.

[0030] In this specification and the like, the term "step discontinuity" refers to a phenomenon in which a layer, film, or electrode is separated due to the shape of the surface on which it is formed (for example, a step or the like).

[0031] In this specification, the phrase "planar shapes that are approximately the same" means that at least a portion of the contours of stacked layers overlap. For example, this includes cases where the upper and lower layers are processed using the same mask pattern, or where only a portion of the mask pattern is the same. However, strictly speaking, the contours may not overlap, and the upper layer may be located inside the lower layer, or the upper layer may be located outside the lower layer. In these cases, the phrase "planar shapes that are approximately the same" is also used.

[0032] Furthermore, in this specification, terms indicating position, such as "above" and "below," are used for convenience in describing the positional relationship between components with reference to the drawings. Furthermore, the positional relationship between components changes as appropriate depending on the direction in which each component is depicted. Therefore, the terms are not limited to those described in the specification, and can be rephrased appropriately depending on the situation.

[0033] In this specification and the like, a metal oxide refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductors or simply as OS), and the like. For example, when a metal oxide is used for a semiconductor layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. In other words, an OS transistor can be rephrased as a transistor including a metal oxide or an oxide semiconductor. Note that metal oxides containing nitrogen may also be collectively referred to as metal oxides. Furthermore, metal oxides containing nitrogen may also be referred to as metal oxynitrides.

[0034] Embodiment 1 In this embodiment, a display device of one embodiment of the present invention, a manufacturing method thereof, and the like will be described with reference to drawings.

[0035] One embodiment of the present invention relates to a display device including a signal line driver circuit, a demultiplexer circuit, and a plurality of columns of pixels. Input terminals of the demultiplexer circuit are electrically connected to the signal line driver circuit, and output terminals of the demultiplexer circuit are electrically connected to the pixels. The demultiplexer circuit includes switches, for example, transistors functioning as switches.

[0036] The signal line driver circuit has a function of generating image data. The demultiplexer circuit has a function of allocating the image data to one of the pixels in the plurality of columns. The pixels display an image corresponding to the image data, specifically, emit light with a brightness represented by the image data. By providing a demultiplexer circuit in a display device, the number of wirings connected to the signal line driver circuit can be reduced. Therefore, assuming the same pixel density, the density of transistors provided in the signal line driver circuit can be lowered, for example, compared to when a demultiplexer circuit is not provided. This allows pixels to be miniaturized, thereby realizing a high-definition display device. Furthermore, since the signal line driver circuit can be miniaturized, a compact display device can be realized. Furthermore, a display device with a narrow frame can be realized.

[0037] In a display device according to one embodiment of the present invention, a transistor in a demultiplexer circuit includes a semiconductor layer provided inside an opening formed in an interlayer insulating layer over a substrate. With this structure, the channel length of the transistor can be aligned along the side surface of the opening. Therefore, the channel length is not affected by the performance of an exposure device used to fabricate the transistor, and the channel length can be set to a value smaller than the resolution limit of the exposure device. Therefore, the transistors included in the demultiplexer circuit can be miniaturized.

[0038] Here, in the transistor having the above structure, a first conductive layer provided under the opening is used as one of the source electrode or drain electrode of the transistor. Specifically, an interlayer insulating layer is provided on the first conductive layer, and the opening is provided in the interlayer insulating layer so as to reach the first conductive layer. Then, the semiconductor layer is provided so as to have a region inside the opening that is in contact with the first conductive layer. Furthermore, a second conductive layer that covers the outer periphery of the opening in a plan view is used as the other of the source electrode or drain electrode of the transistor. Then, a gate insulating layer is provided on the semiconductor layer and the second conductive layer, and a gate electrode is provided on the gate insulating layer.

[0039] In the transistor having the above structure, a second conductive layer is provided on a first conductive layer, and a gate electrode is provided on the second conductive layer. Therefore, in the transistor having the above structure, the distance between the second conductive layer and the gate electrode is shorter than the distance between the first conductive layer and the gate electrode. Therefore, the parasitic capacitance formed between the second conductive layer and the gate electrode is larger than the parasitic capacitance formed between the first conductive layer and the gate electrode. As a result, among the noises generated before image data generated by the signal line driver circuit is supplied to a pixel, the noise caused by the second conductive layer functioning as the other of the source and drain electrodes of the transistor is larger than the noise caused by the first conductive layer functioning as one of the source and drain electrodes of the transistor. For example, the switching noise generated when a transistor functioning as a switch switches between an on state and an off state is larger in the second conductive layer than in the first conductive layer.

[0040] Therefore, in a display device according to one embodiment of the present invention, the first conductive layer is electrically connected to a pixel, and the second conductive layer is electrically connected to a signal line driver circuit. By electrically connecting the first conductive layer, which is unlikely to be a noise source, to a pixel, the influence of noise on an image displayed by the display device can be reduced. Therefore, a display device with high display quality can be realized.

[0041] 1 is a block diagram showing a configuration example of a display device 10, which is a display device of one embodiment of the present invention. The display device 10 includes a display unit 20, a scanning line driver circuit 11, a signal line driver circuit 13, a demultiplexer circuit 31, and a control circuit 15. The display unit 20 includes a plurality of pixels 21 arranged in a matrix of m rows and n columns (m and n are integers equal to or greater than 1).

[0042] In this specification and the like, the pixel 21 in the i-th row and j-th column (i is an integer of 1 to m, and j is an integer of 1 to n) is represented as pixel 21[i,j]. In addition, for example, [i] is added to the symbol representing a wiring electrically connected to the pixel 21 in the i-th row, and [j] is added to the symbol representing a wiring electrically connected to the pixel 21 in the j-th column.

[0043] The demultiplexer circuit 31 has a plurality of transistors 33 that function as switches. Fig. 1 shows an example in which the demultiplexer circuit 31 has two transistors 33. The display device 10 also has a plurality of demultiplexer circuits 31, and Fig. 1 shows an example in which the display device 10 has n / 2 demultiplexer circuits 31. The plurality of demultiplexer circuits 31 are collectively referred to as a demultiplexer circuit group 30.

[0044] In this specification and the like, when the same reference numeral is used for multiple elements, and particularly when it is necessary to distinguish between them, an identifying symbol such as "( )" or "_" may be added to the reference numeral. For example, n / 2 demultiplexer circuits 31 are distinguished by being written as demultiplexer circuit 31(1) to demultiplexer circuit 31(n / 2).

[0045] The scanning line driver circuit 11 is electrically connected to the pixels 21 via wiring 41. For example, the pixels 21[i,1] to 21[i,n] are electrically connected to the scanning line driver circuit 11 via wiring 41[i].

[0046] The signal line driving circuit 13 is electrically connected to an input terminal of the demultiplexer circuit 31 via a wiring 43. For example, an input terminal of a demultiplexer circuit 31(k) (where k is an integer between 1 and n / 2) is electrically connected to the signal line driving circuit 13 via a wiring 43(k).

[0047] The control circuit 15 is electrically connected to the selection signal input terminal of the demultiplexer circuit 31 through a wiring 45. For example, the demultiplexer circuits 31(1) to 31(n / 2) are electrically connected to wirings 45_1 and 45_2, respectively. That is, the demultiplexer circuit 31 can have a configuration including a plurality of selection signal input terminals.

[0048] The output terminal of the demultiplexer circuit 31 is electrically connected to the pixel 21 via a wiring 47. For example, the output terminal of the demultiplexer circuit 31(k) is electrically connected to the pixels 21[1, 2k-1] to 21[m, 2k-1] via a wiring 47[2k-1] and to the pixels 21[1, 2k] to 21[m, 2k] via a wiring 47[2k]. In other words, the demultiplexer circuit 31 can have a plurality of output terminals.

[0049] The demultiplexer circuit 31(k) includes a transistor 33[2k-1] and a transistor 33[2k]. One of the source and the drain of the transistor 33[2k-1] is electrically connected to a wiring 47[2k-1], and one of the source and the drain of the transistor 33[2k] is electrically connected to a wiring 47[2k]. The other of the source and the drain of the transistor 33[2k-1] and the other of the source and the drain of the transistor 33[2k] are electrically connected to a wiring 43(k). The gate of the transistor 33[2k-1] is electrically connected to a wiring 45_1, and the gate of the transistor 33[2k] is electrically connected to a wiring 45_2.

[0050] As described above, one of the source or drain of transistor 33[2k-1] and one of the source or drain of transistor 33[2k] can be used as an output terminal of the demultiplexer circuit 31(k). The other of the source or drain of transistor 33[2k-1] and the other of the source or drain of transistor 33[2k] can be used as an input terminal of the demultiplexer circuit 31(k). Furthermore, the gate of transistor 33[2k-1] and the gate of transistor 33[2k] can be used as a selection signal input terminal of the demultiplexer circuit 31(k).

[0051] The pixel 21 has a display element (also called a display device), and can display an image on the display unit 20 by using the display element. As the display element, for example, a light-emitting element (also called a light-emitting device) can be used, and specifically, an organic EL element can be used.

[0052] The scanning line driver circuit 11 has a function of selecting the pixel 21 to which image data is written. Specifically, the scanning line driver circuit 11 can select the pixel 21 to which image data is written by outputting a signal to a wiring 41. Here, the scanning line driver circuit 11 can output the signal to the wirings 41[1] to 41[m] in order, for example. Therefore, the signal output by the scanning line driver circuit 11 to the wiring 41 is a scanning signal, and the wiring 41 can be called a scanning line.

[0053] The signal line driver circuit 13 has a function of generating image data, which is supplied to a demultiplexer circuit 31.

[0054] The demultiplexer circuit 31 has a function of outputting the image data generated by the signal line driving circuit 13 from one of the output terminals of the demultiplexer circuit 31. The demultiplexer circuit 31 can determine the output terminal to output the image data in accordance with a selection signal input to a selection signal input terminal of the demultiplexer circuit 31.

[0055] The control circuit 15 has a function of generating a selection signal and supplying it to the demultiplexer circuit 31 to control driving of the demultiplexer circuit 31. For example, the control circuit 15 can generate a first signal and a second signal as selection signals and output the first signal to the wiring 45_1 and the second signal to the wiring 45_2. Here, for example, by setting the first signal to a signal that turns on the transistor 33[2k-1] and the second signal to a signal that turns off the transistor 33[2k], the demultiplexer circuit 31(k) can output image data to the wiring 47[2k-1]. Furthermore, by setting the first signal to a signal that turns off the transistor 33[2k-1] and the second signal to a signal that turns on the transistor 33[2k], the demultiplexer circuit 31(k) can output image data to the wiring 47[2k].

[0056] As described above, for example, when the first signal is a signal that turns on the transistor 33, the second signal can be a signal that turns off the transistor 33, and when the first signal is a signal that turns off the transistor 33, the second signal can be a signal that turns on the transistor 33. Therefore, the first signal and the second signal can be complementary to each other. For example, when the first signal and the second signal are 1-bit digital signals, when the first signal is at a high potential, the second signal can be at a low potential, and when the first signal is at a low potential, the second signal can be at a high potential.

[0057] As described above, the image data generated by the signal line driver circuit 13 is supplied to the pixels 21 via the wiring 43, the demultiplexer circuit 31, and the wiring 47. For example, by setting the first signal to a signal that turns on the transistor 33 and then setting the second signal to a signal that turns on the transistor 33, the image data can be written to all the pixels 21 included in the row selected by the scanning line driver circuit 11. Here, the image data can be expressed as a signal. Therefore, the wiring 43 and the wiring 47 can be called signal lines.

[0058] By providing a demultiplexer circuit in the display device, the number of wirings connected to the signal line driver circuit can be reduced. For example, if the demultiplexer circuit group 30 is not provided in the display device 10, n wirings 43 are connected to the signal line driver circuit 13. On the other hand, by providing the demultiplexer circuit group 30 in the display device 10, the number of wirings 43 electrically connected to the signal line driver circuit 13 can be reduced to less than n. As a result, assuming the pixel density of the display unit 20 is the same, the density of transistors provided in the signal line driver circuit 13 can be lower than in a case where the demultiplexer circuit group 30 is not provided. Therefore, assuming the density of transistors provided in the signal line driver circuit 13 is the same, the pixel density of the display unit 20 can be increased. This allows the pixels 21 to be miniaturized, thereby making the display device 10 a high-resolution display device. Furthermore, if the density of transistors provided in the signal line driver circuit 13 is increased, the signal line driver circuit 13 can be miniaturized, thereby making the display device 10 a compact display device and a display device with a narrow frame.

[0059] 1 shows an example in which the demultiplexer circuit 31 has two transistors 33, but the demultiplexer circuit 31 may have, for example, three or more transistors 33. For example, if the demultiplexer circuit 31 has three transistors 33, the display device 10 can be configured to have n / 3 demultiplexer circuits 31. In this case, the demultiplexer circuit 31 can be configured to have three output terminals and three selection signal input terminals. The demultiplexer circuit 31 may also have four or more transistors 33. In this case, the demultiplexer circuit 31 can be configured to have four or more output terminals and four or more selection signal input terminals.

[0060] For example, if the demultiplexer circuit 31 has three selection signal input terminals, first to third signals are input to the respective selection signal input terminals as selection signals. One of the first to third signals is a signal that turns on the transistor 33, and the remaining two are signals that turn off the transistor 33. For example, if the first signal is a signal that turns on the transistor 33, the second and third signals are signals that turn off the transistor 33. Then, in the demultiplexer circuit 31, the first signal is first written as a signal that turns on only the transistor 33, then the second signal is written as a signal that turns on only the transistor 33, and then the third signal is written as a signal that turns on only the transistor 33. By doing so, image data can be written to all of the pixels 21 included in the row selected by the scanning line driving circuit 11. Similarly, when the demultiplexer circuit 31 has four or more selection signal input terminals, one of the four or more selection signals is a signal that turns on the transistor 33, and the remaining signals are signals that turn off the transistor 33.

[0061] The more the number of transistors 33 included in one demultiplexer circuit 31 is increased, the fewer the number of wirings 43 electrically connected to the signal line driver circuit 13 can be. Therefore, the display device 10 can have higher resolution, be more compact, and have a narrower frame.

[0062] 2A1 is a plan view illustrating a structural example of a semiconductor device included in a display device of one embodiment of the present invention, specifically, a transistor 33 and its peripheral structure. FIG. 2B is a cross-sectional view along dashed dotted line A1-A2 in FIG. 2A1. Note that some components of the transistor 33, such as an insulating layer, are omitted in FIG. 2A1. In the plan views of the transistor, some components, such as an insulating layer, are also omitted in the subsequent drawings.

[0063] In this specification and the like, a plan view may be referred to as a top view.

[0064] The transistor 33 is provided on a substrate 101. The transistor 33 includes a conductive layer 111, a conductive layer 112, a semiconductor layer 113, an insulating layer 105, and a conductive layer 115. In FIG. 2A1, an example is shown in which the conductive layer 112 extends in a direction parallel to the conductive layer 111 and in a direction perpendicular to the conductive layer 115.

[0065] 2A1 and 2B, as shown on the coordinate axes, the direction in which the conductive layer 112 extends is the X direction. Furthermore, the direction perpendicular to the X direction and parallel to, for example, the upper surface of the substrate 101 is the Y direction, and the direction perpendicular to the upper surface of the substrate 101 is the Z direction. The definitions of the X direction, Y direction, and Z direction may be the same in the subsequent drawings or may be different. The X direction, Y direction, and Z direction may be perpendicular to each other.

[0066] In the explanation of plan views in this specification, the X direction may be referred to as the right side or the left side, and the Y direction may be referred to as the top side or the bottom side. In addition, the right side may be referred to as the X direction, the left side as the −X direction, the top side as the Y direction, and the bottom side as the −Y direction.

[0067] The conductive layer 111 functions as one of a source electrode and a drain electrode of the transistor 33. The conductive layer 112 functions as the other of the source electrode and the drain electrode of the transistor 33. The insulating layer 105 functions as a gate insulating layer of the transistor 33. The conductive layer 115 functions as a gate electrode of the transistor 33.

[0068] In the semiconductor layer 113, an entire region that overlaps with the gate electrode between the source electrode and the drain electrode via the gate insulating layer functions as a channel formation region. In addition, in the semiconductor layer 113, a region in contact with the source electrode functions as a source region, and a region in contact with the drain electrode functions as a drain region.

[0069] A conductive layer 111 is provided over a substrate 101, an insulating layer 103 is provided over the substrate 101 and the conductive layer 111, and a conductive layer 112 is provided over the insulating layer 103. The insulating layer 103 can function as an interlayer insulating layer. The conductive layer 111 and the conductive layer 112 have a region where they overlap with each other with the insulating layer 103 interposed therebetween.

[0070] The insulating layer 103 has an opening 121 that reaches the conductive layer 111. The conductive layer 112 has an opening 123 that reaches the opening 121. In other words, the opening 123 has a region that overlaps with the opening 121.

[0071] 2A1 shows conductive layers 111, 112, semiconductor layers 113, conductive layers 115, openings 121, and 123 as components of the transistor 33. Here, FIG. 2A2 shows a configuration example in which the conductive layer 115 is omitted from the elements shown in FIG. 2A1. That is, FIG. 2A2 shows the conductive layers 111, 112, semiconductor layers 113, openings 121, and 123. Furthermore, FIG. 2A3 shows a configuration example in which the semiconductor layer 113 is further omitted from the elements shown in FIG. 2A2. That is, FIG. 2A3 shows the conductive layers 111, 112, openings 121, and 123.

[0072] 2A3 and 2B , the conductive layer 112 has an opening 123 in a region overlapping with the conductive layer 111. As shown in Fig. 2A3 , the conductive layer 112 can be configured to cover the entire outer periphery of the opening 121 in a plan view. Here, it is preferable that the conductive layer 112 is not provided inside the opening 121. In other words, it is preferable that the conductive layer 112 not be in contact with the side surface of the insulating layer 103 on the opening 121 side.

[0073] 2A1, 2A2, and 2A3 show an example in which the shapes of the openings 121 and 123 are each circular in a plan view. By making the planar shapes of the openings 121 and 123 circular, the processing accuracy when forming the openings 121 and 123 can be improved, and the openings 121 and 123 can be formed with fine sizes. Note that in this specification, a circle is not limited to a perfect circle. Furthermore, the planar shapes of the openings 121 and 123 may be, for example, elliptical.

[0074] 2B shows an example in which the end of the conductive layer 112 on the opening 123 side coincides with or roughly coincides with the end of the insulating layer 103 on the opening 121 side. It can also be said that the planar shape of the opening 123 coincides with or roughly coincides with the planar shape of the opening 121. Note that in this specification, the end of the conductive layer 112 on the opening 123 side and the end of the opening 123 refer to the lower surface end of the conductive layer 112 on the opening 123 side. The lower surface of the conductive layer 112 refers to the surface on the insulating layer 103 side. The end of the insulating layer 103 on the opening 121 side and the end of the opening 121 refer to the upper surface end of the insulating layer 103 on the opening 121 side. The upper surface of the insulating layer 103 refers to the surface on the conductive layer 112 side. Furthermore, the planar shape of the opening 123 refers to the planar shape of the lower surface end of the conductive layer 112 on the opening 123 side. The planar shape of the opening 121 refers to the planar shape of the upper surface edge of the insulating layer 103 on the opening 121 side.

[0075] Note that "edges that are aligned or approximately aligned" can also be said to mean that the edges are aligned or approximately aligned. When the edges are aligned or approximately aligned, and when the planar shapes are aligned or approximately aligned, it can be said that at least a portion of the contours of the stacked layers overlap in a planar view (also referred to as a top view). For example, this includes cases where the upper and lower layers are processed using the same mask pattern or partially the same mask pattern. However, strictly speaking, the contours may not overlap, and the upper layer may be located inside the lower layer, or the upper layer may be located outside the lower layer. In these cases, the edges are also said to be approximately aligned, or the planar shapes are said to be approximately aligned.

[0076] The opening 121 can be formed, for example, using the resist mask used to form the opening 123. Specifically, after the conductive layer 111 is first formed over the substrate 101, the insulating layer 103, a conductive film to be the conductive layer 112 over the insulating layer 103, and a resist mask over the conductive film are formed over the substrate 101 and the conductive layer 111. Then, the opening 123 is formed in the conductive film using the resist mask, and then the opening 121 is formed in the insulating layer 103 using the resist mask. This allows the edge of the opening 121 to coincide or approximately coincide with the edge of the opening 123. This structure can simplify the process.

[0077] The semiconductor layer 113 is provided to cover the openings 121 and 123 and to have regions located inside the openings 121 and 123. The semiconductor layer 113 has a shape that follows the shapes of the upper surface and side surfaces of the conductive layer 112, the side surfaces of the insulating layer 103, and the upper surface of the conductive layer 111. The semiconductor layer 113 has regions that are in contact with, for example, the upper surface and side surfaces of the conductive layer 112, the side surfaces of the insulating layer 103, and the upper surface of the conductive layer 111.

[0078] The semiconductor layer 113 preferably covers the end of the conductive layer 112 on the opening 123 side. For example, FIG. 2B shows a structure in which the end of the semiconductor layer 113 is located on the conductive layer 112. It can also be said that the end of the semiconductor layer 113 is in contact with the top surface of the conductive layer 112.

[0079] 2B shows the semiconductor layer 113 having a single-layer structure, one embodiment of the present invention is not limited thereto, and the semiconductor layer 113 may have a stacked structure of two or more layers.

[0080] The insulating layer 105, which functions as a gate insulating layer of the transistor 33, is provided to cover the openings 121 and 123 and to have regions located inside the openings 121 and 123. The insulating layer 105 is provided over the semiconductor layer 113, the conductive layer 112, and the insulating layer 103. The insulating layer 105 can have regions in contact with the top surface and side surfaces of the semiconductor layer 113, the top surface and side surfaces of the conductive layer 112, and the top surface of the insulating layer 103. The insulating layer 105 has a shape that follows the shapes of the top surface of the insulating layer 103, the top surface and side surfaces of the conductive layer 112, and the top surface and side surfaces of the semiconductor layer 113.

[0081] The conductive layer 115 functioning as the gate electrode of the transistor 33 is provided over the insulating layer 105 and can have a region in contact with the top surface of the insulating layer 105. The conductive layer 115 has a region overlapping with the semiconductor layer 113 with the insulating layer 105 interposed therebetween. The conductive layer 115 has a shape that follows the shape of the top surface of the insulating layer 105.

[0082] 2B , in the openings 121 and 123, the conductive layer 115 has a region that overlaps with the semiconductor layer 113 with the insulating layer 105 interposed therebetween. In the example shown in FIG. 2B , the conductive layer 115 has a region that overlaps with the conductive layer 111 and the conductive layer 112 with the insulating layer 105 and the semiconductor layer 113 interposed therebetween. The conductive layer 115 also covers the entire semiconductor layer 113. With this structure, a gate electric field can be applied to the entire semiconductor layer 113, thereby improving the electrical characteristics of the transistor 33 and increasing, for example, the on-state current of the transistor.

[0083] The transistor 33 is a so-called top-gate transistor having a gate electrode above the semiconductor layer 113. Furthermore, since the lower surface of the semiconductor layer 113 has a region in contact with the source electrode and the drain electrode, the transistor 33 can be called a TGBC (Top Gate Bottom Contact) transistor.

[0084] Note that a transistor having a similar structure to that applicable to the transistor 33 can also be applied to circuits other than the demultiplexer circuit 31 included in the display device 10. For example, a transistor having a similar structure to that applicable to the transistor 33 can be applied to a transistor included in the signal line driver circuit 13. A transistor having a similar structure to that applicable to the transistor 33 can be applied to one or both of a transistor included in the scanning line driver circuit 11 and a transistor included in the control circuit 15. Furthermore, a transistor having a similar structure to that applicable to the transistor 33 can be applied to a transistor included in the pixel 21.

[0085] The channel length and channel width of the transistor 33 will now be described with reference to FIGS. 3A and 3B. FIG. 3A is an enlarged plan view showing an example of the configuration of the transistor 33 and its periphery shown in FIG. 2A1. FIG. 3B is an enlarged cross-sectional view showing an example of the configuration of the transistor 33 and its periphery shown in FIG. 2B.

[0086] In the semiconductor layer 113, a region in contact with the conductive layer 111 functions as one of a source region and a drain region, a region in contact with the conductive layer 112 functions as the other of the source region and the drain region, and a region between the source region and the drain region functions as a channel formation region.

[0087] The channel length of the transistor 33 is the distance between the source region and the drain region. In Fig. 3B, the channel length L33 of the transistor 33 is indicated by a dashed double-headed arrow. In a cross-sectional view, the channel length L33 is the distance between the end of the region where the semiconductor layer 113 and the conductive layer 111 contact each other and the end of the region where the semiconductor layer 113 and the conductive layer 112 contact each other.

[0088] Here, the channel length L33 of the transistor 33 corresponds to the length of the side surface of the insulating layer 103 on the opening 121 side in a cross-sectional view. In other words, the channel length L33 is determined by the film thickness T103 of the insulating layer 103 and the angle θ103 between the side surface of the insulating layer 103 on the opening 121 side and the surface on which the insulating layer 103 is to be formed (here, the upper surface of the conductive layer 111), and is not affected by the performance of the exposure device used to fabricate the transistor. Therefore, the channel length L33 can be set to a value smaller than the limit resolution of the exposure device. For example, the channel length L33 is preferably 0.010 μm or more and less than 3.0 μm, more preferably 0.050 μm or more and less than 3.0 μm, even more preferably 0.10 μm or more and less than 3.0 μm, even more preferably 0.15 μm or more and less than 3.0 μm, even more preferably 0.20 μm or more and less than 3.0 μm, even more preferably 0.20 μm or more and less than 2.5 μm, even more preferably 0.20 μm or more and less than 2.0 μm, even more preferably 0.20 μm or more and less than 1.5 μm, even more preferably 0.30 μm or more and less than 1.5 μm, even more preferably 0.30 μm or more and 1.2 μm or less, even more preferably 0.40 μm or more and 1.2 μm or less, even more preferably 0.40 μm or more and 1.0 μm or less, and even more preferably 0.50 μm or more and 1.0 μm or less. In FIG. 3B, the thickness T103 of the insulating layer 103 is indicated by a dashed line with a double-headed arrow.

[0089] By reducing the channel length L33, the on-state current of the transistor 33 can be increased. Therefore, by configuring the transistor 33 of the demultiplexer circuit 31 as shown in FIG. 3B, for example, the demultiplexer circuit 31 can be driven at high speed. Therefore, even if one demultiplexer circuit 31 has a configuration including multiple transistors 33, i.e., a configuration including multiple output terminals, the frame frequency of the display device 10 can be ensured. Therefore, the number of wirings connected to the signal line driver circuit 13 can be suitably reduced. As a result, assuming the pixel density of the display unit 20 is the same, the density of transistors provided in the signal line driver circuit 13 can be lower than in a case where the demultiplexer circuit group 30 is not provided. Therefore, assuming the density of transistors provided in the signal line driver circuit 13 is the same, the pixel density of the display unit 20 can be increased. Therefore, the pixels 21 can be miniaturized, and the display device 10 can be a high-resolution display device. Furthermore, if the density of the transistors provided in the signal line driver circuit 13 is increased, the signal line driver circuit 13 can be made smaller, and therefore the display device 10 can be made smaller and have a narrower frame.

[0090] By adjusting the film thickness T103 and angle θ103 of the insulating layer 103, the channel length L33 can be controlled.

[0091] The thickness T103 of the insulating layer 103 is preferably 0.010 μm or more and less than 3.0 μm, more preferably 0.050 μm or more and less than 3.0 μm, even more preferably 0.10 μm or more and less than 3.0 μm, even more preferably 0.15 μm or more and less than 3.0 μm, even more preferably 0.20 μm or more and less than 3.0 μm, even more preferably 0.20 μm or more and less than 2.5 μm, and even more preferably 0. Preferably, the thickness is 20 μm or more and less than 2.0 μm, more preferably 0.20 μm or more and less than 1.5 μm, even more preferably 0.30 μm or more and less than 1.5 μm, even more preferably 0.30 μm or more and 1.2 μm or less, even more preferably 0.40 μm or more and 1.2 μm or less, even more preferably 0.40 μm or more and 1.0 μm or less, and even more preferably 0.50 μm or more and 1.0 μm or less.

[0092] The side surface of the insulating layer 103 on the opening 121 side is preferably tapered. The angle θ103 formed between the side surface of the insulating layer 103 on the opening 121 side and the surface on which the insulating layer 103 is to be formed (here, the top surface of the conductive layer 111) is preferably less than 90 degrees. By reducing the angle θ103, the coverage of a layer (e.g., the semiconductor layer 113) provided on the insulating layer 103 can be improved. However, reducing the angle θ103 reduces the contact area between the semiconductor layer 113 and the conductive layer 111, which may increase the contact resistance between the semiconductor layer 113 and the conductive layer 111. The angle θ103 is preferably 45 degrees or more and less than 90 degrees, more preferably 50 degrees or more and less than 90 degrees, even more preferably 55 degrees or more and less than 90 degrees, even more preferably 60 degrees or more and less than 90 degrees, even more preferably 60 degrees or more and less than 85 degrees, even more preferably 65 degrees or more and less than 85 degrees, even more preferably 65 degrees or more and less than 80 degrees, even more preferably 70 degrees or more and less than 80 degrees. By setting the angle θ103 within the above range, the coverage of the conductive layer 111 and the layer (e.g., the semiconductor layer 113) formed on the insulating layer 103 can be improved, and defects such as discontinuities or voids in the layer can be suppressed. Furthermore, the contact resistance between the semiconductor layer 113 and the conductive layer 111 can be reduced.

[0093] 3B shows a cross-sectional view in which the side surface of the insulating layer 103 on the opening 121 side has a straight line shape, but one embodiment of the present invention is not limited to this. In the cross-sectional view, the side surface of the insulating layer 103 on the opening 121 side may have a curved line shape, or the side surface may have both a straight line region and a curved line region.

[0094] The channel width of the transistor 33 is the width of the source region or the width of the drain region in a direction perpendicular to the channel length direction. That is, the channel width is the width of the region where the semiconductor layer 113 and the conductive layer 111 contact each other or the width of the region where the semiconductor layer 113 and the conductive layer 112 contact each other in a direction perpendicular to the channel length direction. Here, the channel width of the transistor 33 is described as the width of the region where the semiconductor layer 113 and the conductive layer 112 contact each other in a direction perpendicular to the channel length direction. In Figures 3A and 3B, the channel width W33 of the transistor 33 is indicated by a solid double-headed arrow. The channel width W33 is the length of the bottom end of the conductive layer 112 on the opening 123 side in a plan view.

[0095] The channel width W33 is determined by the planar shape of the opening 123. In Figures 3A and 3B, the width D123 of the opening 123 is indicated by a two-dot chain line with a double arrow. The width D123 refers to the short side of the smallest rectangle circumscribing the opening 123 in a planar view. When the opening 123 is formed using photolithography, the width D123 of the opening 123 is equal to or greater than the resolution limit of the exposure device. The width D123 is, for example, preferably 0.20 μm or more and less than 5.0 μm, more preferably 0.20 μm or more and less than 4.5 μm, even more preferably 0.20 μm or more and less than 4.0 μm, even more preferably 0.20 μm or more and less than 3.5 μm, even more preferably 0.20 μm or more and less than 3.0 μm, even more preferably 0.20 μm or more and less than 2.5 μm, even more preferably 0.20 μm or more and less than 2.0 μm, even more preferably 0.20 μm or more and less than 1.5 μm, even more preferably 0.30 μm or more and less than 1.5 μm, even more preferably 0.30 μm or more and 1.2 μm or less, even more preferably 0.40 μm or more and 1.2 μm or less, even more preferably 0.40 μm or more and 1.0 μm or less, and even more preferably 0.50 μm or more and 1.0 μm or less. When the planar shape of the opening 123 is circular, the width D123 corresponds to the diameter of the opening 123, and the channel width W33 can be made equal to the length of the periphery of the opening 123 in a planar view, and can be calculated as "D123 x π".

[0096] 4A is a plan view showing an example of the configuration of the demultiplexer circuit group 30 shown in FIG. 1, illustrating the demultiplexer circuit 31(1) and the demultiplexer circuit 31(n / 2). Fig. 4B is a cross-sectional view of the dashed line A3-A4 shown in Fig. 4A. Fig. 4A shows transistors 33[1], 33[2], 33[n-1], and 33[n]. Fig. 4B also shows transistors 33[1] and 33[2].

[0097] The transistor 33[1] includes a conductive layer 111[1], a conductive layer 112(1), a semiconductor layer 113[1], an insulating layer 105, and a conductive layer 115_1. The semiconductor layer 113[1] and the insulating layer 105 are provided to have regions located inside the openings 121[1] and 123[1] so as to cover the openings 121[1] and 123[1] that reach the conductive layer 111[1].

[0098] The transistor 33[2] includes a conductive layer 111[2], a conductive layer 112(1), a semiconductor layer 113[2], an insulating layer 105, and a conductive layer 115_2. The semiconductor layer 113[2] and the insulating layer 105 are provided to have regions located inside the openings 121[2] and 123[2] so as to cover the openings 121[2] and 123[2] that reach the conductive layer 111[2].

[0099] The transistor 33[n-1] includes a conductive layer 111[n-1], a conductive layer 112(n / 2), a semiconductor layer 113[n-1], an insulating layer 105, and a conductive layer 115_1. The semiconductor layer 113[n-1] and the insulating layer 105 are provided to have regions located inside the opening 121[n-1] and the opening 123[n-1] so as to cover the opening 121[n-1] and the opening 123[n-1] that reach the conductive layer 111[n-1].

[0100] The transistor 33[n] includes a conductive layer 111[n], a conductive layer 112(n / 2), a semiconductor layer 113[n], an insulating layer 105, and a conductive layer 115_2. The semiconductor layer 113[n] and the insulating layer 105 are provided to have regions located inside the opening 121[n] and the opening 123[n] so as to cover the opening 121[n] and the opening 123[n] that reach the conductive layer 111[n].

[0101] The conductive layers 111[1] to 111[n] function as wirings 47[1] to 47[n] electrically connected to the pixel 21. The conductive layers 112(1) to 112(n / 2) function as wirings 43(1) to 43(n / 2) electrically connected to the signal line driver circuit 13. The conductive layer 115_1 functions as wiring 45_1 electrically connected to the control circuit 15, and the conductive layer 115_2 functions as wiring 45_2 electrically connected to the control circuit 15.

[0102] As described above, in the display device of one embodiment of the present invention, the conductive layer 111 functioning as one of the source electrode and drain electrode of the transistor 33 is used as the wiring 47 electrically connected to the pixel 21. That is, the conductive layer 111 is used as the output terminal of the demultiplexer circuit 31. The conductive layer 112 functioning as the other of the source electrode and drain electrode of the transistor 33 is used as the wiring 43 electrically connected to the signal line driver circuit 13. Here, the transistor 33 has a region in which the distance between the conductive layer 112 and the conductive layer 115 is shorter than the distance between the conductive layer 111 and the conductive layer 115. Therefore, the parasitic capacitance formed between the conductive layer 112 and the conductive layer 115 is larger than the parasitic capacitance formed between the conductive layer 111 and the conductive layer 115. Therefore, among the noises generated before image data generated by the signal line driver circuit 13 is supplied to the pixel 21, the noise caused by the conductive layer 112 is larger than the noise caused by the conductive layer 111. For example, the switching noise generated when the transistor 33 switches between an off state and an on state is larger in the conductive layer 112 than in the conductive layer 111 .

[0103] In the display device of one embodiment of the present invention, the conductive layer 111, which is unlikely to be a noise source, is electrically connected to the pixel 21. This can reduce the influence of noise on an image displayed in the display portion 20. Therefore, the display device of one embodiment of the present invention can have high display quality. Note that the conductive layer 111 may be electrically connected to the signal line driver circuit 13, and the conductive layer 112 may be electrically connected to the pixel 21. Since the conductive layer 111 is located below the conductive layer 112, electrically connecting the conductive layer 111 to the signal line driver circuit 13 can sometimes shorten the wiring distance from the signal line driver circuit 13 to the transistor 33, specifically, for example, the wiring distance from an output terminal of the signal line driver circuit 13 to the semiconductor layer 113.

[0104] 4A shows an example in which the conductive layer 112(1) is shared by the transistor 33[1] and the transistor 33[2], and the conductive layer 112(n / 2) is shared by the transistor 33[n-1] and the transistor 33[n]. This allows the other of the source or the drain of the transistor 33[1] to be electrically connected to the other of the source or the drain of the transistor 33[2], and the other of the source or the drain of the transistor 33[n-1] to be electrically connected to the other of the source or the drain of the transistor 33[n]. Also, in FIG. 4A, the conductive layer 115_1 is shared by the transistor 33[1] and the transistor 33[n-1], and the conductive layer 115_2 is shared by the transistor 33[2] and the transistor 33[n]. This allows the gate of transistor 33[1] to be electrically connected to the gate of transistor 33[n-1], and the gate of transistor 33[2] to be electrically connected to the gate of transistor 33[n].

[0105] 2A1 , in a plan view, both the Y-direction end and the −Y-direction end of the conductive layer 112 as viewed from the opening 123 have regions that overlap with the conductive layer 111. That is, the Y-direction end of the conductive layer 112 as viewed from the opening 123 is located inside the Y-direction end of the conductive layer 111 as viewed from the opening 123, and the −Y-direction end of the conductive layer 112 as viewed from the opening 123 is located inside the −Y-direction end of the conductive layer 111 as viewed from the opening 123. However, one embodiment of the present invention is not limited to this. FIG. 5A illustrates an example in which the −Y-direction end of the conductive layer 112 as viewed from the opening 123 does not overlap with the conductive layer 111 in a plan view. That is, in the example illustrated in FIG. 5A , the −Y-direction end of the conductive layer 112 as viewed from the opening 123 is located outside the −Y-direction end of the conductive layer 111 as viewed from the opening 123. For example, when the transistor 33[1] shown in Fig. 4A has the structure shown in Fig. 5A, an end of the conductive layer 112(1) in a region functioning as the transistor 33[1] can be configured to protrude toward the conductive layer 111[2] beyond the end of the conductive layer 111[1]. When the transistor 33[n-1] shown in Fig. 4A has the structure shown in Fig. 5A, an end of the conductive layer 112(n / 2) in a region functioning as the transistor 33[n-1] can be configured to protrude toward the conductive layer 111[n] beyond the end of the conductive layer 111[n-1].

[0106] 5B shows an example in which, in a plan view, the end of the conductive layer 112 in the Y direction as viewed from the opening 123 does not overlap with the conductive layer 111. That is, in the example shown in FIG. 5B , the end of the conductive layer 112 in the Y direction as viewed from the opening 123 is located outside the end of the conductive layer 111 in the Y direction as viewed from the opening 123. For example, when the transistor 33[2] shown in FIG. 4A has the structure shown in FIG. 5B , the end of the conductive layer 112(1) in the region functioning as the transistor 33[2] can be configured to protrude toward the conductive layer 111[1] beyond the end of the conductive layer 111[2]. Furthermore, when the transistor 33[n] shown in FIG. 4A has the structure shown in FIG. 5B , the end of the conductive layer 112(n / 2) in the region functioning as the transistor 33[n] can be configured to protrude toward the conductive layer 111[n-1] beyond the end of the conductive layer 111[n].

[0107] 5C shows an example in which, in a plan view, neither the Y-direction end nor the −Y-direction end of the conductive layer 112 as viewed from the opening 123 overlaps with the conductive layer 111. That is, in the example shown in Fig. 5C , the Y-direction end of the conductive layer 112 as viewed from the opening 123 is located outside the upper Y-direction end of the conductive layer 111 as viewed from the opening 123, and the −Y-direction end of the conductive layer 112 as viewed from the opening 123 is located outside the −Y-direction end of the conductive layer 111 as viewed from the opening 123.

[0108] Note that for a cross-sectional view of the configurations shown in FIGS. 5A, 5B, and 5C taken along the dashed dotted line A1-A2, refer to FIG. 2B.

[0109] The components included in the display device of this embodiment will be described below.

[0110] <Component 1 of Display Device> [Semiconductor Layer 113] The semiconductor material that can be used for the semiconductor layer 113 is not particularly limited. For example, an elemental semiconductor or a compound semiconductor can be used. As the elemental semiconductor, for example, silicon or germanium can be used. As the compound semiconductor, for example, gallium arsenide and silicon germanium can be used. As the compound semiconductor, an organic substance having semiconductor properties or a metal oxide (also called an oxide semiconductor) having semiconductor properties can be used. Note that these semiconductor materials may contain impurities as dopants.

[0111] The crystallinity of the semiconductor material used for the semiconductor layer 113 is not particularly limited, and any of an amorphous semiconductor and a crystalline semiconductor (a single-crystalline semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, or a semiconductor having a crystalline region in part) may be used. Use of a crystalline semiconductor is preferable because it can suppress deterioration of transistor characteristics.

[0112] Silicon can be used for the semiconductor layer 113. Examples of silicon include single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. Examples of polycrystalline silicon include low temperature polysilicon (LTPS).

[0113] A transistor using amorphous silicon for the semiconductor layer 113 can be formed over a large glass substrate and can be manufactured at low cost. A transistor using polycrystalline silicon for the semiconductor layer 113 has high field-effect mobility and can operate at high speed. A transistor using microcrystalline silicon for the semiconductor layer 113 has higher field-effect mobility than a transistor using amorphous silicon and can operate at high speed.

[0114] The semiconductor layer 113 preferably includes a metal oxide (oxide semiconductor). Examples of metal oxides that can be used for the semiconductor layer 113 include indium oxide, gallium oxide, and zinc oxide. The metal oxide preferably includes at least indium (In) or zinc (Zn). The metal oxide preferably includes two or three elements selected from indium, an element M, and zinc. The element M is one or more elements selected from gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, cobalt, and magnesium. In particular, the element M is preferably one or more elements selected from aluminum, gallium, yttrium, and tin.

[0115] For the semiconductor layer 113, for example, indium oxide, indium zinc oxide (In—Zn oxide), indium tin oxide (In—Sn oxide), indium titanium oxide (In—Ti oxide), indium aluminum zinc oxide (In—Al—Zn oxide, also referred to as IAZO), indium tin zinc oxide (In—Sn—Zn oxide), indium titanium zinc oxide (In—Ti—Zn oxide), indium gallium zinc oxide (In—Ga—Zn oxide, also referred to as IGZO), indium gallium tin zinc oxide (In—Ga—Sn—Zn oxide), indium gallium aluminum zinc oxide (In—Ga—Al—Zn oxide, also referred to as IGAZO or IAGZO), or the like can be used. Alternatively, indium tin oxide containing silicon can be used.

[0116] The element M is preferably one or more elements selected from the group consisting of gallium, aluminum, yttrium, and tin, and is particularly preferably gallium.

[0117] Here, the composition of the metal oxide contained in the semiconductor layer 113 greatly affects the electrical characteristics and reliability of the transistor 33 .

[0118] For example, by increasing the content of indium in the metal oxide, a transistor with a large on-state current can be realized.

[0119] When an In—Zn oxide is used for the semiconductor layer 113, it is preferable to use a metal oxide in which the atomic ratio of indium is equal to or greater than the atomic ratio of zinc. For example, a metal oxide in which the atomic ratio of metal elements is In:Zn=1:1, In:Zn=2:1, In:Zn=3:1, In:Zn=4:1, In:Zn=5:1, In:Zn=7:1, or In:Zn=10:1, or a ratio close to these, can be used.

[0120] When an In—Sn oxide is used for the semiconductor layer 113, it is preferable to use a metal oxide in which the atomic ratio of indium is equal to or greater than the atomic ratio of tin. For example, a metal oxide in which the atomic ratio of metal elements is In:Sn=1:1, In:Sn=2:1, In:Sn=3:1, In:Sn=4:1, In:Sn=5:1, In:Sn=7:1, or In:Sn=10:1, or a ratio close to these values, can be used.

[0121] When an In—Sn—Zn oxide is used for the semiconductor layer 113, a metal oxide in which the atomic ratio of indium is higher than the atomic ratio of tin can be used. Furthermore, it is preferable to use a metal oxide in which the atomic ratio of zinc is higher than the atomic ratio of tin. For example, the atomic ratios of metal elements may be In:Sn:Zn=2:1:3, In:Sn:Zn=3:1:2, In:Sn:Zn=4:2:3, In:Sn:Zn=4:2:4.1, In:Sn:Zn=5:1:3, In:Sn:Zn=5:1:6, In:Sn:Zn=5:1:7, In:Sn:Zn=5:1:8, In:Sn:Zn=6:1:6, In:Sn:Zn=5:1:3, In:Sn:Zn=5:1:8, In:Sn:Zn=6:1:6, In:Sn:Zn=5:1:3, In:Sn:Zn=5:1:7, In:Sn:Zn=5:1:8, In:Sn:Zn=6:1:6, In:Sn:Zn=5:1:3 ...3, In:Sn:Zn=5:1:8, In:Sn:Zn=5:1:6, In:Sn:Zn=5:1:3, In:Sn:Zn=5:1:3, In:Sn:Zn=5:1:3, In:Sn:Zn=5:1:3, In:Sn:Zn=5 In:Sn:Zn = 10:1:3, In:Sn:Zn = 10:1:6, In:Sn:Zn = 10:1:7, In:Sn:Zn = 10:1:8, In:Sn:Zn = 5:2:5, In:Sn:Zn = 10:1:10, In:Sn:Zn = 20:1:10, In:Sn:Zn = 40:1:10, or metal oxides thereof having a similar ratio can be used.

[0122] When an In-Al-Zn oxide is used for the semiconductor layer 113, a metal oxide in which the atomic ratio of indium is higher than that of aluminum can be used. Furthermore, it is preferable to use a metal oxide in which the atomic ratio of zinc is higher than that of aluminum. For example, the atomic ratios of metal elements may be In:Al:Zn=2:1:3, In:Al:Zn=3:1:2, In:Al:Zn=4:2:3, In:Al:Zn=4:2:4.1, In:Al:Zn=5:1:3, In:Al:Zn=5:1:6, In:Al:Zn=5:1:7, In:Al:Zn=5:1:8, In:Al:Zn=6:1:6, In:Al:Zn=5:1:3, In:Al:Zn=5:1:7, In:Al:Zn=5:1:8, In:Al:Zn=6:1:6, In:Al:Zn=5:1:3, In:Al:Zn=5:1:3, In:Al:Zn=5:1:3, In:Al:Zn=5:1:3, In:Al:Zn=5:1:3, In:Al:Zn=5:1:8, In:Al:Zn=5:1:6, In:Al:Zn=5:1:7 ...7, In:Al:Zn=5:1:8 It is possible to use metal oxides such as In:Al:Zn = 10:1:3, In:Al:Zn = 10:1:6, In:Al:Zn = 10:1:7, In:Al:Zn = 10:1:8, In:Al:Zn = 5:2:5, In:Al:Zn = 10:1:10, In:Al:Zn = 20:1:10, In:Al:Zn = 40:1:10, or metal oxides in the vicinity of these.

[0123] When an In—Ga—Zn oxide is used for the semiconductor layer 113, a metal oxide in which the atomic ratio of indium to the number of atoms of the metal element is higher than the atomic ratio of gallium can be used. Furthermore, it is more preferable to use a metal oxide in which the atomic ratio of zinc is higher than the atomic ratio of gallium. For example, the semiconductor layer 113 may have an atomic ratio of metal elements of In:Ga:Zn=2:1:3, In:Ga:Zn=3:1:2, In:Ga:Zn=4:2:3, In:Ga:Zn=4:2:4.1, In:Ga:Zn=5:1:3, In:Ga:Zn=5:1:6, In:Ga:Zn=5:1:7, In:Ga:Zn=5:1:8, or In:Ga:Zn=6:1. :6, In:Ga:Zn=10:1:3, In:Ga:Zn=10:1:6, In:Ga:Zn=10:1:7, In:Ga:Zn=10:1:8, In:Ga:Zn=5:2:5, In:Ga:Zn=10:1:10, In:Ga:Zn=20:1:10, In:Ga:Zn=40:1:10, or metal oxides thereof can be used.

[0124] When an In-M-Zn oxide is used for the semiconductor layer 113, a metal oxide in which the atomic ratio of indium to the number of atoms of the metal element is higher than the atomic ratio of the element M can be used. Furthermore, it is more preferable to use a metal oxide in which the atomic ratio of zinc is higher than the atomic ratio of the element M. For example, the semiconductor layer 113 may have atomic ratios of metal elements of In:M:Zn=2:1:3, In:M:Zn=3:1:2, In:M:Zn=4:2:3, In:M:Zn=4:2:4.1, In:M:Zn=5:1:3, In:M:Zn=5:1:6, In:M:Zn=5:1:7, In:M:Zn=5:1:8, In:M:Zn=6:1 :6, In:M:Zn=10:1:3, In:M:Zn=10:1:6, In:M:Zn=10:1:7, In:M:Zn=10:1:8, In:M:Zn=5:2:5, In:M:Zn=10:1:10, In:M:Zn=20:1:10, In:M:Zn=40:1:10, or metal oxides thereof having a similar structure can be used.

[0125] When a plurality of metal elements are contained as the element M, the sum of the atomic ratios of the metal elements can be taken as the atomic ratio of the element M. For example, in the case of an In-Ga-Al-Zn oxide having gallium and aluminum as the element M, the sum of the atomic ratio of gallium and the atomic ratio of aluminum can be taken as the atomic ratio of the element M. Furthermore, it is preferable that the atomic ratios of indium, the element M, and zinc are within the above-mentioned ranges.

[0126] It is preferable to use a metal oxide in which the ratio of the number of indium atoms to the number of atoms of metal elements contained in the metal oxide is 30 atomic % or more and 100 atomic % or less, preferably 30 atomic % or more and 95 atomic % or less, more preferably 35 atomic % or more and 95 atomic % or less, more preferably 35 atomic % or more and 90 atomic % or less, more preferably 40 atomic % or more and 90 atomic % or less, more preferably 45 atomic % or more and 90 atomic % or less, more preferably 50 atomic % or more and 80 atomic % or less, more preferably 60 atomic % or more and 80 atomic % or less, and more preferably 70 atomic % or more and 80 atomic % or less. For example, when an In—Ga—Zn oxide is used for the semiconductor layer 113, it is preferable that the ratio of the number of indium atoms to the total number of atoms of indium, the element M, and zinc be in the above-mentioned range.

[0127] In this specification and the like, the ratio of the number of indium atoms to the number of atoms of the contained metal element may be referred to as the indium content. The same applies to other metal elements.

[0128] By increasing the indium content of the metal oxide, a transistor with a large on-state current can be obtained. By applying the transistor to a transistor that is required to have a high on-state current, a display device with excellent electrical characteristics can be provided.

[0129] The composition of the metal oxide can be analyzed by, for example, energy dispersive X-ray spectroscopy (EDX), X-ray photoelectron spectroscopy (XPS), inductively coupled plasma mass spectrometry (ICP-MS), or inductively coupled plasma atomic emission spectrometry (ICP-AES). Alternatively, a combination of these techniques may be used for the analysis. For elements with low content, the actual content may differ from the content obtained by analysis due to the influence of analytical accuracy. For example, when the content of element M is low, the content of element M obtained by analysis may be lower than the actual content.

[0130] In this specification, a "nearby composition" includes a range of ±30% of the desired atomic ratio. For example, when an atomic ratio is described as In:M:Zn = 4:2:3 or a composition near there, this includes a case where, when the atomic ratio of indium is 4, the atomic ratio of M is 1 to 3 and the atomic ratio of zinc is 2 to 4. Furthermore, when an atomic ratio is described as In:M:Zn = 5:1:6 or a composition near there, this includes a case where, when the atomic ratio of indium is 5, the atomic ratio of M is greater than 0.1 and less than 2 and the atomic ratio of zinc is greater than 5 and less than 7. Furthermore, when an atomic ratio is described as In:M:Zn = 1:1:1 or a composition near there, this includes a case where, when the atomic ratio of indium is 1, the atomic ratio of M is greater than 0.1 and less than 2 and the atomic ratio of zinc is greater than 0.1 and less than 2.

[0131] The metal oxide can be preferably formed by sputtering or atomic layer deposition (ALD). When forming a metal oxide by sputtering, the atomic ratio of the target may differ from the atomic ratio of the metal oxide. In particular, the atomic ratio of zinc in the metal oxide may be smaller than the atomic ratio of the target. Specifically, the atomic ratio of zinc in the metal oxide may be approximately 40% to 90% of the atomic ratio of zinc contained in the target.

[0132] Here, the reliability of a transistor will be described. One of the indicators for evaluating the reliability of a transistor is a Gate Bias Temperature (GBT) stress test, in which the transistor is held in a state in which an electric field is applied to the gate. Among these, a test in which a positive potential (positive bias) is applied to the gate with respect to the source potential and the drain potential and the transistor is held at a high temperature is called a Positive Bias Temperature (PBTS) test, and a test in which a negative potential (negative bias) is applied to the gate and the transistor is held at a high temperature is called a Negative Bias Temperature (NBTS) test. The PBTS test and the NBTS test performed under light irradiation are called a PBTIS (Positive Bias Temperature Illumination Stress) test and an NBTIS (Negative Bias Temperature Illumination Stress) test, respectively.

[0133] In an n-type transistor, a positive potential is applied to the gate when the transistor is turned on (a state in which current flows). Therefore, the amount of variation in threshold voltage in the PBTS test is one of the important items to be noted as an index of the reliability of the transistor.

[0134] By using a metal oxide that does not contain gallium or has a low gallium content for the semiconductor layer 113, a transistor with high reliability against positive bias application can be obtained. That is, a transistor with a small amount of fluctuation in threshold voltage in a PBTS test can be obtained. Furthermore, when a metal oxide containing gallium is used, it is preferable to make the gallium content lower than the indium content. This allows a highly reliable transistor to be realized.

[0135] One of the factors that causes the threshold voltage to fluctuate in the PBTS test is defect levels at or near the interface between the semiconductor layer and the gate insulating layer. The higher the defect level density, the more significant the degradation in the PBTS test. By reducing the gallium content in the region of the semiconductor layer that contacts the gate insulating layer, the generation of the defect levels can be suppressed.

[0136] The following is a possible reason why using a metal oxide containing no gallium or with a low gallium content for the semiconductor layer can suppress fluctuations in threshold voltage in the PBTS test. Gallium contained in metal oxides has the property of attracting oxygen more easily than other metal elements (e.g., indium or zinc). Therefore, it is presumed that gallium combines with excess oxygen in the gate insulating layer at the interface between the gallium-rich metal oxide and the gate insulating layer, making it easier to generate carrier (here, electron) trap sites. Therefore, when a positive potential is applied to the gate, carriers are trapped at the interface between the semiconductor layer and the gate insulating layer, which is thought to cause fluctuations in threshold voltage.

[0137] More specifically, when an In—Ga—Zn oxide is used for the semiconductor layer 113, a metal oxide in which the atomic ratio of indium is higher than the atomic ratio of gallium can be used for the semiconductor layer 113. It is more preferable to use a metal oxide in which the atomic ratio of zinc is higher than the atomic ratio of gallium. In other words, it is preferable to use a metal oxide in which the atomic ratios of metal elements satisfy In>Ga and Zn>Ga for the semiconductor layer 113.

[0138] For example, the semiconductor layer 113 has an atomic ratio of metal elements of In:Ga:Zn=2:1:3, In:Ga:Zn=3:1:2, In:Ga:Zn=4:2:3, In:Ga:Zn=4:2:4.1, In:Ga:Zn=5:1:3, In:Ga:Zn=5:1:6, In:Ga:Zn=5:1:7, In:Ga:Zn=5:1:8, In:Ga:Zn=6:1 :6, In:Ga:Zn=10:1:3, In:Ga:Zn=10:1:6, In:Ga:Zn=10:1:7, In:Ga:Zn=10:1:8, In:Ga:Zn=5:2:5, In:Ga:Zn=10:1:10, In:Ga:Zn=20:1:10, In:Ga:Zn=40:1:10, or metal oxides thereof can be used.

[0139] The semiconductor layer 113 preferably uses a metal oxide in which the ratio of the number of gallium atoms to the number of atoms of the contained metal element is greater than 0 atomic % and less than 50 atomic %, preferably 0.1 atomic % to 40 atomic %, more preferably 0.1 atomic % to 35 atomic %, more preferably 0.1 atomic % to 30 atomic %, more preferably 0.1 atomic % to 25 atomic %, more preferably 0.1 atomic % to 20 atomic %, more preferably 0.1 atomic % to 15 atomic %, and more preferably 0.1 atomic % to 10 atomic %. By reducing the gallium content in the semiconductor layer, a transistor with high resistance to the PBTS test can be obtained. Note that by including gallium in the metal oxide, oxygen deficiency (V Ｏ This has the effect of making oxygen vacancy less likely to occur.

[0140] A metal oxide that does not contain gallium may be used for the semiconductor layer 113. For example, In—Zn oxide may be used for the semiconductor layer 113. In this case, increasing the atomic ratio of indium to the atomic number of metal elements contained in the metal oxide can increase the field-effect mobility of the transistor. On the other hand, increasing the atomic ratio of zinc to the atomic number of metal elements contained in the metal oxide can result in a metal oxide with high crystallinity, thereby suppressing fluctuations in the electrical characteristics of the transistor and improving reliability. Alternatively, a metal oxide that does not contain gallium or zinc, such as indium oxide, may be used for the semiconductor layer 113. Using a metal oxide that does not contain gallium can significantly reduce fluctuations in threshold voltage, particularly in a PBTS test.

[0141] For example, an oxide containing indium and zinc can be used for the semiconductor layer 113. In this case, a metal oxide in which the atomic ratio of metal elements is, for example, In:Zn=2:3, In:Zn=4:1, or a ratio close to these values ​​can be used.

[0142] Although gallium has been used as a representative example in the description, the present invention can also be applied to a case where the element M is used instead of gallium. For the semiconductor layer 113, it is preferable to use a metal oxide in which the atomic ratio of indium is higher than the atomic ratio of the element M. It is also preferable to use a metal oxide in which the atomic ratio of zinc is higher than the atomic ratio of the element M.

[0143] A transistor having high reliability when a positive bias is applied can be obtained by using a metal oxide having a low content of the element M for the semiconductor layer 113. When the transistor is used as a transistor that is required to have high reliability when a positive bias is applied, a display device having high reliability can be obtained.

[0144] Next, the reliability of the transistor against light will be described.

[0145] Light incident on a transistor may cause fluctuations in the electrical characteristics of the transistor. In particular, it is preferable that a transistor applied to a region where light may be incident exhibits small fluctuations in electrical characteristics under light irradiation and has high reliability against light. The reliability against light can be evaluated, for example, by the amount of fluctuation in threshold voltage in an NBTIS test.

[0146] Increasing the content of the element M in the metal oxide can provide a transistor with high reliability against light. That is, a transistor with a small variation in threshold voltage in an NBTIS test can be provided. Specifically, a metal oxide in which the atomic ratio of the element M is equal to or greater than the atomic ratio of indium has a larger band gap, and can reduce the variation in threshold voltage of the transistor in an NBTIS test. The band gap of the metal oxide in the semiconductor layer 113 is preferably 2.0 eV or more, more preferably 2.5 eV or more, even more preferably 3.0 eV or more, still more preferably 3.2 eV or more, even more preferably 3.3 eV or more, still more preferably 3.4 eV or more, and even more preferably 3.5 eV or more.

[0147] For example, the semiconductor layer 113 can use metal oxides having an atomic ratio of metal elements of In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=1:3:2, In:M:Zn=1:3:3, In:M:Zn=1:3:4, or similar ratios thereof.

[0148] The semiconductor layer 113 can suitably use a metal oxide in which the ratio of the number of atoms of element M to the number of atoms of the contained metal element is 20 atomic % or more and 70 atomic % or less, preferably 30 atomic % or more and 70 atomic % or less, more preferably 30 atomic % or more and 60 atomic % or less, more preferably 40 atomic % or more and 60 atomic % or less, and more preferably 50 atomic % or more and 60 atomic % or less.

[0149] When an In—Ga—Zn oxide is used for the semiconductor layer 113, a metal oxide in which the atomic ratio of indium to the number of atoms of the metal element is equal to or less than the atomic ratio of gallium can be used. For example, a metal oxide in which the atomic ratio of the metal element is In:Ga:Zn=1:1:1, In:Ga:Zn=1:1:1.2, In:Ga:Zn=1:3:2, In:Ga:Zn=1:3:3, In:Ga:Zn=1:3:4, or a ratio close to these can be used.

[0150] The semiconductor layer 113 can suitably use a metal oxide in which the ratio of the number of gallium atoms to the number of atoms of the contained metal elements is 20 atomic % or more and 60 atomic % or less, preferably 20 atomic % or more and 50 atomic % or less, more preferably 30 atomic % or more and 50 atomic % or less, more preferably 40 atomic % or more and 60 atomic % or less, and more preferably 50 atomic % or more and 60 atomic % or less.

[0151] A transistor with high reliability to light can be obtained by using a metal oxide having a high content of element M for the semiconductor layer 113. By using the transistor as a transistor that is required to have high reliability to light, a display device with high reliability can be obtained.

[0152] As described above, the electrical characteristics and reliability of a transistor vary depending on the composition of the metal oxide used for the semiconductor layer 113. Therefore, by varying the composition of the metal oxide depending on the electrical characteristics and reliability required of the transistor, a display device that has both excellent electrical characteristics and high reliability can be obtained.

[0153] The semiconductor layer 113 may have a stacked structure including two or more metal oxide layers. The two or more metal oxide layers included in the semiconductor layer 113 may have the same or approximately the same composition. By using a stacked structure of metal oxide layers having the same composition, for example, the same sputtering target can be used for formation, thereby reducing manufacturing costs.

[0154] The two or more metal oxide layers included in the semiconductor layer 113 may have different compositions. For example, a stacked structure of a first metal oxide layer having an atomic ratio of In:M:Zn=1:3:4 or a composition similar thereto and a second metal oxide layer having an atomic ratio of In:M:Zn=1:1:1 or a composition similar thereto provided on the first metal oxide layer can be preferably used. Furthermore, it is particularly preferable to use gallium or aluminum as the element M. For example, a stacked structure of any one selected from indium oxide, indium gallium oxide, and IGZO and any one selected from IAZO, IAGZO, and ITZO (registered trademark) can be used.

[0155] A crystalline metal oxide layer is preferably used for the semiconductor layer 113. For example, a metal oxide layer having a c-axis aligned crystal (CAAC) structure, a polycrystalline structure, a nanocrystalline (nc) structure, or the like can be used. By using a crystalline metal oxide layer for the semiconductor layer 113, the density of defect states in the semiconductor layer 113 can be reduced, and a highly reliable display device can be realized.

[0156] The higher the crystallinity of the metal oxide layer used for the semiconductor layer 113, the more the density of defect states in the semiconductor layer 113 can be reduced. On the other hand, by using a metal oxide layer with low crystallinity, a transistor capable of passing a large current can be realized.

[0157] When a metal oxide layer is formed by a sputtering method, the higher the substrate temperature (stage temperature) during formation, the higher the crystallinity of the formed metal oxide layer.Furthermore, the higher the ratio of the flow rate of oxygen gas to the total deposition gas used during formation (hereinafter also referred to as oxygen flow rate ratio), the higher the crystallinity of the formed metal oxide layer.

[0158] The semiconductor layer 113 may have a stacked structure of two or more metal oxide layers with different crystallinity. For example, the semiconductor layer 113 may have a stacked structure of a first metal oxide layer and a second metal oxide layer provided on the first metal oxide layer, where the second metal oxide layer has a region with higher crystallinity than the first metal oxide layer. Alternatively, the second metal oxide layer may have a region with lower crystallinity than the first metal oxide layer. The two or more metal oxide layers included in the semiconductor layer 113 may have the same or approximately the same composition. By using a stacked structure of metal oxide layers with the same composition, for example, the same sputtering target can be used to form the layers, thereby reducing manufacturing costs. For example, by using the same sputtering target and varying the oxygen flow rate, a stacked structure of two or more metal oxide layers with different crystallinity can be formed. Note that the two or more metal oxide layers included in the semiconductor layer 113 may have different compositions.

[0159] The thickness of the semiconductor layer 113 is preferably 3 nm or more and 100 nm or less, more preferably 5 nm or more and 100 nm or less, even more preferably 10 nm or more and 100 nm or less, even more preferably 10 nm or more and 70 nm or less, even more preferably 15 nm or more and 70 nm or less, even more preferably 15 nm or more and 50 nm or less, even more preferably 20 nm or more and 50 nm or less, even more preferably 20 nm or more and 40 nm or less, even more preferably 25 nm or more and 40 nm or less.

[0160] The substrate temperature during the formation of the semiconductor layer 113 is preferably from room temperature (25° C.) to 200° C., more preferably from room temperature to 130° C. By setting the substrate temperature within the above range, bending or distortion of the substrate can be suppressed when a large-area glass substrate is used.

[0161] Here, oxygen vacancies that can be formed in the semiconductor layer 113 will be described.

[0162] When an oxide semiconductor is used for the semiconductor layer 113, hydrogen contained in the oxide semiconductor reacts with oxygen bonded to metal atoms to form water, and oxygen vacancies (V Ｏ In addition, defects in which hydrogen enters oxygen vacancies (hereinafter referred to as V ＯHydrogen atoms (H) may function as donors and generate electrons as carriers. Furthermore, some of the hydrogen atoms may bond with oxygen atoms that are bonded to metal atoms to generate electrons as carriers. Therefore, a transistor using an oxide semiconductor containing a large amount of hydrogen is likely to have normally-on characteristics. Furthermore, hydrogen in an oxide semiconductor is easily moved by stress such as heat or an electric field. Therefore, if an oxide semiconductor contains a large amount of hydrogen, the reliability of the transistor may be reduced.

[0163] V Ｏ H can function as a donor in an oxide semiconductor. However, it is difficult to quantitatively evaluate such defects. Therefore, in an oxide semiconductor, evaluation is sometimes performed using the carrier concentration rather than the donor concentration. Therefore, in this specification and the like, the carrier concentration assuming a state in which no electric field is applied may be used as a parameter of the oxide semiconductor, rather than the donor concentration. In other words, the "carrier concentration" described in this specification and the like may be rephrased as the "donor concentration."

[0164] From the above, when an oxide semiconductor is used for the semiconductor layer 113, V in the semiconductor layer 113 Ｏ It is preferable to reduce H as much as possible to obtain high-purity intrinsic or substantially high-purity intrinsic. Ｏ To obtain an oxide semiconductor in which H is sufficiently reduced, impurities such as water and hydrogen in the oxide semiconductor are removed (this may be referred to as dehydration or dehydrogenation treatment), and oxygen vacancies (V Ｏ It is important to repair the Ｏ By using an oxide semiconductor in which impurities such as H are sufficiently reduced for a channel formation region of a transistor, stable electrical characteristics can be obtained. Ｏ ) is sometimes referred to as oxygenation treatment.

[0165] In the case where an oxide semiconductor is used for the semiconductor layer 113, the carrier concentration of the oxide semiconductor in a region functioning as a channel formation region is 1×10 １８ cm −３ Preferably, it is 1×10 or less. １７ cm−３ More preferably, it is less than 1×10 １６ cm −３ More preferably, it is less than 1×10 １３ cm −３ More preferably, it is less than 1×10 １２ cm −３ The lower limit of the carrier concentration of the oxide semiconductor in the region functioning as a channel formation region is not particularly limited, but is preferably, for example, 1×10 −９ cm −３ It can be said that:

[0166] A transistor using an oxide semiconductor (hereinafter referred to as an OS transistor) has significantly higher field-effect mobility than a transistor using amorphous silicon. Furthermore, an OS transistor has significantly lower source-drain leakage current in an off state (hereinafter also referred to as an off-state current), and can hold charge accumulated in a capacitor connected in series with the transistor for a long period of time. Furthermore, the use of an OS transistor can reduce the power consumption of a display device.

[0167] Here, to increase the emission luminance of a light-emitting element included in a pixel of a display device, it is necessary to increase the amount of current flowing through the light-emitting element. To achieve this, it is necessary to increase the source-drain voltage of a driving transistor included in the pixel. Since an OS transistor has a higher withstand voltage between the source and drain than a transistor using silicon (hereinafter referred to as a Si transistor), a high voltage can be applied between the source and drain of the OS transistor. Therefore, by using an OS transistor as the driving transistor included in a pixel, it is possible to increase the amount of current flowing through the light-emitting element and increase the emission luminance of the light-emitting element.

[0168] When a transistor operates in the saturation region, an OS transistor can reduce the change in source-drain current with respect to a change in gate-source voltage compared to a Si transistor. Therefore, by using an OS transistor as a driving transistor included in a pixel, the current flowing between the source and drain can be precisely controlled by changing the gate-source voltage, thereby controlling the amount of current flowing to the light-emitting element. This allows for a wider gradation range in the pixel.

[0169] In terms of saturation characteristics of the current that flows when a transistor operates in a saturation region, an OS transistor can pass a more stable current (saturation current) than a Si transistor, even when the source-drain voltage gradually increases. Therefore, by using an OS transistor as a driving transistor, a stable current can be passed to a light-emitting element, even when the current-voltage characteristics of the light-emitting element vary. In other words, when an OS transistor operates in a saturation region, the source-drain current of the OS transistor remains almost unchanged even when the source-drain voltage increases, thereby stabilizing the light-emitting luminance of the light-emitting element.

[0170] As described above, by using an OS transistor for a driving transistor included in a pixel, it is possible to achieve "suppression of black floating," "increase in light-emitting luminance," "multiple gray levels," "suppression of variations in light-emitting elements," and the like.

[0171] [Insulating Layer 103] An inorganic insulating material or an organic insulating material can be used for the insulating layer 103. The insulating layer 103 may have a stacked structure of an inorganic insulating material and an organic insulating material.

[0172] An inorganic insulating material can be suitably used for the insulating layer 103. Examples of the inorganic insulating material that can be used include one or more of oxide, oxynitride, nitride oxide, and nitride. For example, the insulating layer 103 can include one or more of silicon oxide, silicon oxynitride, aluminum oxide, hafnium oxide, yttrium oxide, zirconium oxide, gallium oxide, tantalum oxide, magnesium oxide, lanthanum oxide, cerium oxide, neodymium oxide, silicon nitride, silicon nitride oxide, and aluminum nitride.

[0173] In this specification and the like, an oxynitride refers to a material whose composition contains more oxygen than nitrogen. A nitride oxide refers to a material whose composition contains more nitrogen than oxygen. For example, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, and silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0174] The oxygen and nitrogen contents can be analyzed using, for example, secondary ion mass spectrometry (SIMS) or X-ray photoelectron spectroscopy (XPS). XPS is suitable when the content of the target element is high (e.g., 0.5 atomic% or more, or 1 atomic% or more). On the other hand, SIMS is suitable when the content of the target element is low (e.g., 0.5 atomic% or less, or 1 atomic% or less). When comparing the element contents, it is more preferable to perform a combined analysis using both SIMS and XPS analytical techniques.

[0175] The insulating layer 103 may have a stacked structure of two or more layers. For example, FIG. 2B shows a configuration in which the insulating layer 103 has a stacked structure of an insulating layer 103a and an insulating layer 103b over the insulating layer 103a. The insulating layer 103a and the insulating layer 103b can each be made of the materials that can be used for the insulating layer 103 described above. Note that the insulating layer 103a and the insulating layer 103b may be made of the same material or different materials. Note that the insulating layer 103a may have a stacked structure of two or more layers. The insulating layer 103b may have a stacked structure of two or more layers.

[0176] The insulating layer 103a can be thicker than the insulating layer 103b. The deposition rate of the insulating layer 103a is preferably fast. In particular, when the insulating layer 103a is thick, the deposition rate of the insulating layer 103a is preferably fast. By increasing the deposition rate of the insulating layer 103a, productivity can be increased. For example, the deposition rate can be increased by increasing the power when forming the insulating layer 103a.

[0177] The insulating layer 103a preferably has a small stress. If the insulating layer 103a is made thick, the stress of the insulating layer 103a increases, which may cause warping of the substrate. By reducing the stress of the insulating layer 103a, it is possible to prevent problems during processing that are caused by stress, such as warping of the substrate.

[0178] The insulating layer 103b functions as a blocking film that suppresses gas desorption from the insulating layer 103a. The insulating layer 103b is preferably made of a material that does not easily diffuse gas. The insulating layer 103b preferably has a region with a higher film density than the insulating layer 103a. Increasing the film density of the insulating layer 103b can improve the blocking property. For example, the insulating layer 103b can be made of a material that has a higher nitrogen content than the insulating layer 103a. Increasing the nitrogen content of the insulating layer 103b can improve the blocking property.

[0179] The insulating layer 103b may have any thickness that functions as a blocking film for preventing gas from being released from the insulating layer 103a, and may be thinner than the insulating layer 103a. The deposition rate of the insulating layer 103b is preferably slower than that of the insulating layer 103a. By slowing down the deposition rate of the insulating layer 103b, the film density of the insulating layer 103b can be increased, thereby improving the blocking property. Similarly, by increasing the substrate temperature during deposition of the insulating layer 103b, the film density of the insulating layer 103b can be increased, thereby improving the blocking property.

[0180] The film density can be evaluated using, for example, Rutherford Backscattering Spectrometry (RBS) or X-ray Reflection (XRR). Differences in film density can sometimes be evaluated using cross-sectional transmission electron microscope (TEM) images. In TEM observation, a high film density results in a darker (darker) transmission electron (TE) image, whereas a low film density results in a lighter (brighter) transmission electron (TE) image. Therefore, the insulating layer 103b may appear darker (darker) in the transmission electron (TE) image than the insulating layer 103a. Even when the insulating layer 103a and the insulating layer 103b are made of the same material, the film density is different, and therefore the boundary between them can sometimes be observed as a difference in contrast in a cross-sectional TEM image.

[0181] The insulating layer 103b may have a region where the hydrogen concentration in the film is lower than that in the insulating layer 103a. The difference in hydrogen concentration between the insulating layer 103a and the insulating layer 103b can be evaluated by, for example, secondary ion mass spectrometry (SIMS).

[0182] Here, the insulating layer 103 will be specifically described using an example in which a metal oxide is used for the semiconductor layer 113.

[0183] When an oxide semiconductor is used for the semiconductor layer 113, an inorganic insulating material can be suitably used for each of the insulating layers 103a and 103b.

[0184] The insulating layer 103a is preferably formed using an oxide or an oxynitride. The insulating layer 103a is preferably formed using a film that releases oxygen when heated. For example, silicon oxide or silicon oxynitride can be suitably used for the insulating layer 103a.

[0185] When the insulating layer 103a releases oxygen, oxygen can be supplied from the insulating layer 103a to the semiconductor layer 113. When oxygen is supplied from the insulating layer 103a to the semiconductor layer 113, particularly to the channel formation region of the semiconductor layer 113, oxygen vacancies (V Ｏ ) and V ＯH can be reduced, and a highly reliable transistor can be obtained, exhibiting favorable electrical characteristics. The insulating layer 103a preferably has a high oxygen diffusion coefficient. By increasing the oxygen diffusion coefficient of the insulating layer 103a, oxygen can be easily diffused in the insulating layer 103a, and oxygen can be efficiently supplied from the insulating layer 103a to the semiconductor layer 113. Note that other treatments for supplying oxygen to the semiconductor layer 113 include heat treatment in an atmosphere containing oxygen, plasma treatment in an atmosphere containing oxygen, and the like.

[0186] The insulating layer 103a preferably releases little impurities (for example, water and hydrogen) from itself. By reducing the release of impurities from the insulating layer 103a, the impurities are prevented from diffusing into the semiconductor layer 113, and a highly reliable transistor can be obtained, which has favorable electrical characteristics.

[0187] The insulating layer 103a can be preferably formed using, for example, silicon oxide or silicon oxynitride by a PECVD method. In this case, a mixed gas of a silicon-containing gas and an oxygen-containing gas is preferably used as a source gas. As the silicon-containing gas, for example, one or more of silane, disilane, trisilane, and silane fluoride can be used. As the oxygen-containing gas, for example, oxygen (O ２ ), ozone (O ３ ), nitrous oxide (N ２ O), nitric oxide (NO), or nitrogen dioxide (NO ２ Note that by increasing the power used in forming the insulating layer 103a, the amount of impurities (for example, water and hydrogen) released from the insulating layer 103a can be reduced.

[0188] The insulating layer 103b is preferably impermeable to oxygen. The insulating layer 103b functions as a blocking film that suppresses oxygen from being released from the insulating layer 103a. Furthermore, the insulating layer 103b is preferably impermeable to hydrogen. The insulating layer 103b functions as a blocking film that suppresses hydrogen from diffusing from the outside of the transistor to the semiconductor layer 113 through the insulating layer 103. The insulating layer 103b preferably has a high film density. Increasing the film density of the insulating layer 103b can improve the blocking property of oxygen and hydrogen. The film density of the insulating layer 103b is preferably higher than that of the insulating layer 103a. When silicon oxide or silicon oxynitride is used for the insulating layer 103a, the insulating layer 103b can be preferably made of, for example, silicon nitride, silicon nitride oxide, or aluminum oxide. The insulating layer 103b preferably has a region with a higher nitrogen content than the insulating layer 103a, for example. The insulating layer 103b can be formed using, for example, a material having a higher nitrogen content than the insulating layer 103a. The insulating layer 103b is preferably formed using a nitride or a nitride oxide. For example, silicon nitride or silicon nitride oxide can be suitably used for the insulating layer 103b.

[0189] When oxygen contained in the insulating layer 103a diffuses upward from a region of the insulating layer 103a that is not in contact with the semiconductor layer 113 (for example, the upper surface of the insulating layer 103a), the amount of oxygen supplied from the insulating layer 103a to the semiconductor layer 113 may decrease. By providing the insulating layer 103b on the insulating layer 103a, it is possible to prevent the oxygen contained in the insulating layer 103a from diffusing from a region of the insulating layer 103a that is not in contact with the semiconductor layer 113. Therefore, the amount of oxygen supplied from the insulating layer 103a to the semiconductor layer 113 increases, and oxygen vacancies (V Ｏ ) and V Ｏ H can be reduced. Therefore, a highly reliable transistor can be obtained that exhibits favorable electrical characteristics.

[0190] The conductive layer 112 may be oxidized by the oxygen contained in the insulating layer 103a, resulting in an increase in resistance. Furthermore, the conductive layer 112 may be oxidized by the oxygen contained in the insulating layer 103a, resulting in a decrease in the amount of oxygen supplied from the insulating layer 103a to the semiconductor layer 113. By providing the insulating layer 103b on the insulating layer 103a, it is possible to prevent the conductive layer 112 from being oxidized and the resistance from increasing. At the same time, the amount of oxygen supplied from the insulating layer 103a to the semiconductor layer 113 increases, resulting in an oxygen deficiency (V Ｏ ) and V Ｏ H can be reduced, and a highly reliable transistor can be obtained that exhibits favorable electrical characteristics.

[0191] When hydrogen diffuses into the semiconductor layer 113, it reacts with oxygen atoms contained in the oxide semiconductor to form water, and oxygen vacancies (V Ｏ ) may be formed. Ｏ By providing the insulating layer 103b on the insulating layer 103a, oxygen vacancies (V Ｏ ) and V Ｏ H can be reduced, and a highly reliable transistor can be obtained that exhibits favorable electrical characteristics.

[0192] The insulating layer 103b preferably has a thickness that functions as a blocking film for oxygen and hydrogen. If the insulating layer 103b is too thin, its function as a blocking film may be reduced. On the other hand, if the insulating layer 103b is too thick, the region of the semiconductor layer 113 in contact with the insulating layer 103a may be narrowed, and the amount of oxygen supplied from the insulating layer 103a to the semiconductor layer 113 may be reduced. The insulating layer 103b may have a thickness thinner than that of the insulating layer 103a. The insulating layer 103b has a thickness preferably from 5 nm to 100 nm, more preferably from 5 nm to 70 nm, further preferably from 10 nm to 70 nm, further preferably from 10 nm to 50 nm, further preferably from 20 nm to 50 nm, and further preferably from 20 nm to 40 nm. By setting the thickness of the insulating layer 103b within the above range, oxygen vacancies (V Ｏ) and V Ｏ H can be reduced, and a highly reliable transistor can be obtained that exhibits favorable electrical characteristics.

[0193] The insulating layer 103b preferably releases little impurities (for example, water and hydrogen) from itself. By reducing the release of impurities from the insulating layer 103b, the impurities are prevented from diffusing into the semiconductor layer 113, and a highly reliable transistor can be obtained, which has favorable electrical characteristics.

[0194] In the transistor 33, a region of the semiconductor layer 113 in contact with the insulating layer 103 can function as a channel formation region. That is, oxygen is selectively supplied to the channel formation region, and oxygen vacancies (V Ｏ ) and V Ｏ H can be reduced. Therefore, a highly reliable transistor can be obtained that exhibits favorable electrical characteristics.

[0195] [Conductive Layer 111, Conductive Layer 112, and Conductive Layer 115] The conductive layers 111 and 112 functioning as source and drain electrodes, and the conductive layer 115 functioning as a gate electrode can be formed using one or more of chromium, copper, aluminum, gold, silver, zinc, molybdenum, tantalum, titanium, tungsten, manganese, nickel, iron, cobalt, molybdenum, and niobium, or an alloy containing one or more of the above metals. The conductive layers 115, 111, and 112 can be formed using a low-resistance conductive material containing one or more of copper, silver, gold, and aluminum. Copper or aluminum is particularly preferred because of its excellent mass productivity.

[0196] A metal oxide film (also referred to as an oxide conductor) can be used for the conductive layer 115, the conductive layer 111, and the conductive layer 112. Examples of the oxide conductor (OC) include In—Sn oxide (ITO), In—W oxide, In—W—Zn oxide, In—Ti oxide, In—Ti—Sn oxide, In—Zn oxide, In—Sn—Si oxide (ITSO), and In—Ga—Zn oxide.

[0197] Here, oxide conductors (OC) will be explained. For example, when oxygen vacancies are formed in a metal oxide having semiconductor properties and hydrogen is added to the oxygen vacancies, a donor level is formed near the conduction band. As a result, the metal oxide becomes more conductive and becomes an electric conductor. A metal oxide that has become an electric conductor can be called an oxide conductor.

[0198] The conductive layers 115, 111, and 112 may each have a stacked structure of a conductive film containing the oxide conductor (metal oxide) and a conductive film containing a metal or an alloy. By using a conductive film containing a metal or an alloy, wiring resistance can be reduced.

[0199] A Cu-X alloy film (X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti) may be applied to the conductive layer 115, the conductive layer 111, and the conductive layer 112. By using a Cu-X alloy film, it is possible to process the film by a wet etching process, thereby reducing manufacturing costs.

[0200] Note that the conductive layer 115, the conductive layer 111, and the conductive layer 112 may be formed using the same material or different materials.

[0201] Here, the conductive layer 111 and the conductive layer 112 will be specifically described using an example in which a metal oxide is used for the semiconductor layer 113 .

[0202] When an oxide semiconductor is used for the semiconductor layer 113, the conductive layers 111 and 112 are oxidized by oxygen contained in the semiconductor layer 113, which may increase the resistance. The conductive layers 111 and 112 are oxidized by oxygen contained in the insulating layer 103a, which may increase the resistance. Furthermore, the conductive layers 111 and 112 are oxidized by oxygen contained in the semiconductor layer 113, which may increase the oxygen vacancy (V Ｏ When the conductive layers 111 and 112 are oxidized by oxygen contained in the insulating layer 103a, the amount of oxygen supplied from the insulating layer 103a to the semiconductor layer 113 may decrease.

[0203] The conductive layers 111 and 112 are preferably made of a material that is resistant to oxidation. The conductive layers 111 and 112 are preferably made of an oxide conductor. For example, In—Sn oxide (ITO) or In—Sn—Si oxide (ITSO) can be suitably used. The conductive layers 111 and 112 may each be made of a nitride conductor. Examples of nitride conductors include tantalum nitride and titanium nitride. The conductive layers 111 and 112 may have a stacked structure of the above-mentioned materials.

[0204] By using a material that is difficult to oxidize for the conductive layer 111 and the conductive layer 112, it is possible to prevent the conductive layer 111 and the conductive layer 112 from being oxidized by oxygen contained in the semiconductor layer 113 or oxygen contained in the insulating layer 103a, which can prevent the resistance from increasing. Ｏ ) in the semiconductor layer 113 can be suppressed, and the amount of oxygen supplied from the insulating layer 103a to the semiconductor layer 113 can be increased. Ｏ ) and V Ｏ H can be reduced, and a highly reliable transistor can be obtained, which has favorable electrical characteristics. Note that the conductive layers 111 and 112 may be formed using the same material or different materials.

[0205] [Insulating Layer 105] The insulating layer 105 functioning as a gate insulating layer preferably has a low defect density. The low defect density of the insulating layer 105 enables a transistor to exhibit favorable electrical characteristics. Furthermore, the insulating layer 105 preferably has a high withstand voltage. The high withstand voltage of the insulating layer 105 enables a highly reliable transistor.

[0206] The insulating layer 105 can be formed using, for example, one or more of an oxide, an oxynitride, a nitride oxide, and a nitride having insulating properties. The insulating layer 105 can be formed using, for example, one or more of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, and Ga—Zn oxide. The insulating layer 105 can be formed as a single layer or a stacked layer. The insulating layer 105 can have, for example, a stacked structure of an oxide and a nitride.

[0207] In a miniaturized transistor, a thin gate insulating layer may result in a large leakage current. By using a material with a high relative dielectric constant (also referred to as a high-k material) for the gate insulating layer, a low voltage can be achieved during transistor operation while maintaining the physical film thickness. Examples of high-k materials include gallium oxide, hafnium oxide, zirconium oxide, an oxide containing aluminum and hafnium, an oxynitride containing aluminum and hafnium, an oxide containing silicon and hafnium, an oxynitride containing silicon and hafnium, and a nitride containing silicon and hafnium.

[0208] The insulating layer 105 preferably releases little impurities (for example, water and hydrogen) from itself. When the insulating layer 105 releases little impurities, the impurities are prevented from diffusing into the semiconductor layer 113, and a highly reliable transistor can be obtained, which has favorable electrical characteristics.

[0209] Since the insulating layer 105 is formed over the semiconductor layer 113, it is preferable that the insulating layer 105 be a film formed under conditions that cause little damage to the semiconductor layer 113. For example, the insulating layer 105 can be formed under conditions that cause a sufficiently slow film formation rate. For example, when the insulating layer 105 is formed by a plasma CVD method, damage to the semiconductor layer 113 can be reduced by forming the insulating layer 105 under low power conditions.

[0210] Here, the insulating layer 105 will be specifically described using an example in which a metal oxide is used for the semiconductor layer 113 .

[0211] In order to improve the interface characteristics with the semiconductor layer 113, it is preferable to use an oxide for at least the side of the insulating layer 105 that is in contact with the semiconductor layer 113. For example, one or more of silicon oxide and silicon oxynitride can be suitably used for the insulating layer 105. It is more preferable to use a film that releases oxygen by heating for the insulating layer 105.

[0212] Note that the insulating layer 105 may have a stacked structure. The insulating layer 105 can have a stacked structure of an oxide film on the side in contact with the semiconductor layer 113 and a nitride film on the side in contact with the conductive layer 115. For example, one or more of silicon oxide and silicon oxynitride can be preferably used as the oxide film. For example, silicon nitride can be preferably used as the nitride film.

[0213] [Substrate 101] For example, there are no significant limitations on the material of the substrate 101, but it must have at least heat resistance sufficient to withstand subsequent heat treatment. For example, a single crystal semiconductor substrate made of silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, an SOI substrate, a glass substrate, a quartz substrate, a sapphire substrate, a ceramic substrate, or an organic resin substrate may be used as the substrate 101. Furthermore, any of these substrates on which semiconductor elements are provided may also be used as the substrate 101. Furthermore, a printed circuit board may also be used as the substrate 101. The shape of the semiconductor substrate and the insulating substrate may be circular or rectangular.

[0214] A flexible substrate may be used as the substrate 101, and the transistor 33, for example, may be formed directly on the flexible substrate. Alternatively, a peeling layer may be provided between the substrate 101 and the transistor 33 or the like. The peeling layer can be used to separate a display device, after a part or the whole of the display device is completed thereon, from the substrate 101 and transfer the display device to another substrate. In this case, the transistor 33 or the like can also be transferred to a substrate with poor heat resistance or a flexible substrate.

[0215] The above is a description of the components.

[0216] The following describes a configuration example of a transistor that is partially different from the above-described <Configuration Example 1 of the display device>. Note that, in the following, descriptions of parts that overlap with the above-described <Configuration Example 1 of the display device> may be omitted. Furthermore, in the drawings shown below, parts that have the same function as the above-described <Configuration Example 1 of the display device> may be hatched with the same pattern and may not be assigned reference numerals.

[0217] <Configuration Example 2 of Display Device> Fig. 6A is a modified example of the configuration shown in Fig. 2A1, and Fig. 6B is a cross-sectional view taken along dashed line A1-A2 in Fig. 6A. Figs. 6A and 6B show an example in which the end of the conductive layer 115 is located inside the end of the semiconductor layer 113 in the X direction, that is, on the opening 123 side. In the example shown in Figs. 6A and 6B, the semiconductor layer 113 has a region that does not overlap with the conductive layer 115. With this configuration, the area of ​​the region where the conductive layer 115 and the conductive layer 112 overlap can be reduced. Therefore, parasitic capacitance can be reduced.

[0218] Fig. 7A is a modified example of the configuration shown in Fig. 6A, and Fig. 7B is a cross-sectional view taken along dashed line A1-A2 in Fig. 7A. Figs. 7A and 7B show an example in which the end of conductive layer 115 is located more inward in the X direction than the end of conductive layer 112 on the opening 123 side. In the example shown in Figs. 7A and 7B, openings 121 and 123 have regions that do not overlap with conductive layer 115. This configuration can further reduce the area of ​​the region where conductive layer 115 and conductive layer 112 overlap. This can further reduce parasitic capacitance.

[0219] 8A is a modified example of the structure shown in FIG. 2A1, and FIG. 8B1 is a cross-sectional view taken along dashed line A1-A2 in FIG. 8A. FIGS. 8A and 8B1 show an example in which, in the region where the conductive layer 111 and the conductive layer 112 overlap, the end of the conductive layer 115 in the X direction is positioned outside the end of the conductive layer 112. In the example shown in FIGS. 8A and 8B1, the conductive layer 115 covers the entire region where the conductive layer 111 and the conductive layer 112 overlap. With this structure, for example, when the conductive layer 115 is formed using photolithography and etching, the alignment accuracy of the photomask can be reduced. Therefore, the transistor 33 can be easily manufactured.

[0220] 8B2 is a modified example of the structure shown in Fig. 8B1, and shows an example in which the top surface edge of the insulating layer 105 coincides with or approximately coincides with the bottom surface edge of the conductive layer 115. For example, when the conductive layer 115 is formed by photolithography and etching, if the etching selectivity between the conductive layer 115 and the insulating layer 105 is low, the structure shown in Fig. 8B2 may be formed.

[0221] 8B3 is a modified example of the configuration shown in Fig. 8B2, and shows an example in which the bottom edge of the conductive layer 115 is located inside the top edge of the insulating layer 105, that is, on the conductive layer 112 side. For example, when the etching rate of the conductive layer 115 in the X direction is faster than the etching rate of the insulating layer 105 in the X direction, the configuration shown in Fig. 8B3 may be formed.

[0222] For plan views of the configurations shown in FIGS. 8B2 and 8B3, refer to FIG. 8A.

[0223] 9A and 9B are modified examples of the configuration shown in Fig. 2A1, and show an example in which the openings 121 and 123 are rectangular with rounded corners in a plan view. Fig. 9A shows an example in which the length of the openings 121 and 123 in the X direction is longer than the length of the openings 121 and 123 in the Y direction, and Fig. 9B shows an example in which the length of the openings 121 and 123 in the X direction is shorter than the length of the openings 121 and 123 in the Y direction. Note that Fig. 2B can be referred to for cross-sectional views of the configurations shown in Figs. 9A and 9B.

[0224] In the example shown in Figures 9A and 9B, the side surfaces of the opening 121 and the opening 123 have flat or approximately flat regions rather than curved surfaces. This allows for improved coverage of the semiconductor layer 113, the insulating layer 105, and the conductive layer 115 inside the opening 121 and the opening 123. In plan view, the corners of the openings 121 and 123 do not have to be rounded. For example, the planar shapes of the openings 121 and 123 may be rectangular, rhombic, or square. The planar shapes of the openings 121 and 123 may also be triangular or triangular with rounded corners. Furthermore, the planar shapes of the openings 121 and 123 may be polygonal, such as a pentagon, or polygonal with rounded corners. The above is applicable to all configurations shown in this specification.

[0225] Fig. 10A1 is a modified example of the configuration shown in Fig. 2A1 , showing an example in which, in a plan view, the conductive layer 112 covers part of the outer periphery of the opening 121 but does not cover the entirety. Fig. 10A2 is a modified example of the configuration shown in Fig. 10A1 , showing an example in which, in a plan view, an end of the conductive layer 112 contacts the outer periphery of the opening 121 at a single point. In the example shown in Fig. 10A2, the opening 121 is circular in a plan view, and one of the ends of the conductive layer 112 extending in the Y direction is a tangent to the opening 121. Fig. 10B is a cross-sectional view taken along dashed line A1-A2 shown in Figs. 10A1 and 10A2.

[0226] 10A1, 10A2, and 10B, the area of ​​the region where the conductive layer 112 and the conductive layer 115 overlap can be reduced, thereby reducing the parasitic capacitance. On the other hand, in the examples shown in FIG. 2A1 and 2B, the width of the other of the source region and the drain region can be increased.

[0227] 10A1 and 10A2, and shows an example in which, in a plan view, the conductive layer 112 does not cover the opening 121 and the conductive layer 112 does not contact the opening 121. Fig. 11B is a cross-sectional view taken along the dashed dotted line A1-A2 shown in Fig. 11A.

[0228] 11A and 11B, the area of ​​the region where the conductive layer 112 and the conductive layer 115 overlap can be further reduced, thereby further reducing the parasitic capacitance.

[0229] Fig. 12A is a modified example of the configuration shown in Fig. 2A1, and shows an example in which the conductive layer 111 does not entirely overlap with the opening 121, but overlaps with a portion thereof. Fig. 12B is a cross-sectional view taken along dashed dotted line A1-A2 shown in Fig. 12A. In the examples shown in Fig. 12A and 12B, the semiconductor layer 113 has a region in the opening 121 that does not overlap with the conductive layer 111.

[0230] 12A and 12B, it is possible to reduce the parasitic capacitance formed between the conductive layer 111 and the conductive layer 115. On the other hand, in the examples shown in Fig. 2A1 and 2B, it is possible to increase the width of one of the source region and the drain region.

[0231] Fig. 13A is a modified example of the configuration shown in Fig. 12A, and shows an example in which openings 121 and 123 are rectangular with rounded corners in a plan view. Fig. 13B is a cross-sectional view taken along dashed line A1-A2 shown in Fig. 13A.

[0232] 13A , the side surfaces of opening 121 and opening 123 have regions that are flat or approximately flat rather than curved. This can improve coverage of semiconductor layer 113, insulating layer 105, and conductive layer 115 inside opening 121 and opening 123. Note that while FIG. 13A shows an example in which the length of opening 121 and opening 123 in the X direction is longer than the length of opening 121 and opening 123 in the Y direction, the length of opening 121 and opening 123 in the X direction may be shorter than the length of opening 121 and opening 123 in the Y direction.

[0233] Fig. 14A1 is a modified example of the configuration shown in Fig. 12A , showing an example in which, in plan view, the conductive layer 112 covers part of the outer periphery of the opening 121 but does not cover the entirety. Fig. 14A2 is a modified example of the configuration shown in Fig. 14A1 , showing an example in which, in plan view, an end of the conductive layer 112 contacts the outer periphery of the opening 121 at a single point. In the example shown in Fig. 14A2, the opening 121 is circular in plan view, and one of the ends of the conductive layer 112 extending in the Y direction is a tangent to the opening 121. Fig. 14B is a cross-sectional view taken along dashed line A1-A2 shown in Figs. 14A1 and 14A2.

[0234] 14A1, 14A2, and 14B, the area of ​​the region where the conductive layer 112 and the conductive layer 115 overlap can be reduced, thereby reducing the parasitic capacitance. On the other hand, in the examples shown in FIGS. 12A and 12B, the width of the other of the source region and the drain region can be increased.

[0235] Fig. 15A is a modified example of the configuration shown in Fig. 14A1 and Fig. 14A2, and shows an example in which the conductive layer 112 does not overlap the opening 121. Fig. 15B is a cross-sectional view taken along the dashed dotted line A1-A2 shown in Fig. 15A.

[0236] 15A and 15B, the area of ​​the region where the conductive layer 112 and the conductive layer 115 overlap can be further reduced, thereby further reducing the parasitic capacitance.

[0237] 16A is a modified example of the configuration shown in Fig. 13A, in which, in plan view, part of one side of opening 121 contacts an end of conductive layer 112 and the length of opening 121 in the X direction is shorter than the length of opening 121 in the Y direction. Fig. 16B is a cross-sectional view taken along dashed dotted line A1-A2 shown in Fig. 16A.

[0238] 16A and 16B, the area of ​​the region where the conductive layer 112 and the conductive layer 115 overlap can be reduced, thereby reducing the parasitic capacitance. On the other hand, in the examples shown in FIGS. 13A and 13B, the width of the other of the source region and the drain region can be increased.

[0239] 17A is a modified example of the configuration shown in Fig. 16A , and shows an example in which the length of opening 121 in the X direction is longer than the length in the Y direction. In the example shown in Fig. 17A , it is possible to configure opening 121 so that one entire side thereof contacts the end of conductive layer 112 in plan view.

[0240] 17B is a modified example of the configuration shown in Fig. 17A , and shows an example in which, in plan view, parts of three sides of opening 121 contact the ends of conductive layer 112. In the example shown in Fig. 17B , in plan view, the entire side of opening 121 on the conductive layer 112 side extending in the Y direction and parts of the side extending in the X direction are covered by conductive layer 112.

[0241] 17B, ​​the width of the other of the source region and the drain region can be increased. On the other hand, in the example shown in Fig. 17A, the area of ​​the region where the conductive layer 112 and the conductive layer 115 overlap can be reduced, thereby reducing the parasitic capacitance. Note that Fig. 16B can be referred to for the cross-sectional view of the dashed dotted line A1-A2 shown in Figs. 17A and 17B.

[0242] Fig. 18A1 is a modified example of the configuration shown in Fig. 16A , showing an example in which, in a plan view, conductive layer 112 does not cover opening 121 and conductive layer 112 does not contact opening 121. Fig. 18A2 is a modified example of the configuration shown in Fig. 18A1 , showing an example in which the length of opening 121 in the X direction is longer than the length in the Y direction. Fig. 18B is a cross-sectional view taken along dashed line A1-A2 shown in Figs. 18A1 and 18A2.

[0243] 18A1, 18A2, and 18B, the area of ​​the region where the conductive layer 112 and the conductive layer 115 overlap can be further reduced, thereby further reducing the parasitic capacitance.

[0244] 19A is a modified example of the configuration shown in FIG. 2A1 , showing an example in which the planar shape of opening 121 and the planar shape of opening 123 do not match. In the example shown in FIG. 19A , the planar shape of opening 123 is a circle with a larger radius than opening 121. Note that one or both of the planar shapes of opening 121 and opening 123 do not have to be circular. Specifically, one or both of the planar shapes of opening 121 and opening 123 can be the above-mentioned shapes, such as a rectangle with rounded corners. FIG. 19B1 is a cross-sectional view taken along dashed line A1-A2 shown in FIG. 19A .

[0245] For example, when the openings 121 and 123 are formed in different processes, the openings 121 and 123 may have the shapes shown in Figures 19A and 19B1. Even when the openings 121 and 123 are formed in the same process, for example, if the etching rate of the conductive layer 112 in the X direction and the Y direction is different from the etching rate of the insulating layer 103 in the X direction and the Y direction, the openings 121 and 123 may have the shapes shown in Figures 19A and 19B1. For example, when the etching rate of the conductive layer 112 in the X direction and the Y direction is faster than the etching rate of the insulating layer 103 in the X direction and the Y direction, the openings 121 and 123 may have the shapes shown in Figures 19A and 19B1, even when the openings 121 and 123 are formed in the same process.

[0246] 19B2 is a modified example of the configuration shown in Fig. 19B1, and shows an example in which the upper surface of the semiconductor layer 113 has a region in contact with the conductive layer 112. For example, the configuration shown in Fig. 19B2 can be formed by forming an opening 121 in the insulating layer 103, then forming the semiconductor layer 113, and then depositing a film that will become the conductive layer 112 and forming an opening 123 in the film.

[0247] As described above, the channel width of the transistor 33 can be made equal to the length of the periphery of the opening 123 in a plan view. Therefore, for example, if the area of ​​the opening 123 is larger than the area of ​​the opening 121, the channel width of the transistor 33 can be increased in some cases. On the other hand, for example, if the area of ​​the opening 123 is equal to the area of ​​the opening 121, the transistor 33 can be miniaturized in some cases.

[0248] 20A is an enlarged view showing an example of the configuration of transistor 33 and its periphery shown in Fig. 19B1, and Fig. 20B is an enlarged view showing an example of the configuration of transistor 33 and its periphery shown in Fig. 19B2. As shown in Fig. 20A and Fig. 20B, the side surface of insulating layer 103a facing opening 121 has tapered portion 161a, and the side surface of insulating layer 103b facing opening 121 has tapered portion 161b.

[0249] 20A and 20B , the upper surface edge of insulating layer 103a on the opening 121 side and the lower surface edge of insulating layer 103b on the opening 121 side can be aligned or approximately aligned. Furthermore, the taper angle of tapered portion 161a and the taper angle of tapered portion 161b can be made equal or approximately equal. Here, the taper angle of the side surface of conductive layer 112 on the opening 123 side may be larger or smaller than the taper angles of tapered portions 161a and 161b.

[0250] 21A and 21B are modified examples of the configurations shown in FIGS. 20A and 20B, respectively, showing examples in which the taper angle of tapered portion 161a is different from the taper angle of tapered portion 161b. In FIGS. 21A and 21B, the straight line extending from tapered portion 161b toward insulating layer 103a is shown by a dashed line. For example, if the materials of insulating layer 103a and insulating layer 103b are different, which results in differences in the processability of insulating layer 103a and insulating layer 103b, the taper angle of tapered portion 161a may be different from the taper angle of tapered portion 161b.

[0251] 21A and 21B show an example in which the taper angle of tapered portion 161a is smaller than the taper angle of tapered portion 161b. The taper angle of tapered portion 161a may be larger than the taper angle of tapered portion 161b. Here, the taper angle of the side surface of conductive layer 112 on the opening 123 side may be larger or smaller than the taper angle of tapered portion 161a, and may also be larger or smaller than the taper angle of tapered portion 161b.

[0252] 22A and 22B are modified examples of the configuration shown in Figures 20A and 20B, respectively, and show an example in which the upper surface edge of insulating layer 103a and the lower surface edge of insulating layer 103b do not coincide, specifically, an example in which the edge of insulating layer 103b on the opening 121 side is positioned outside the edge of insulating layer 103a on the opening 121 side. In Figures 22A and 22B, opening 121 provided in insulating layer 103a is referred to as opening 121a, and opening 121 provided in insulating layer 103b is referred to as opening 121b.

[0253] For example, if the etching rate of insulating layer 103a in the X direction is different from the etching rate of insulating layer 103b in the X direction, the upper surface edge of insulating layer 103a may not coincide with the lower surface edge of insulating layer 103b. Specifically, if the etching rate of insulating layer 103b in the X direction is faster than the etching rate of insulating layer 103a in the X direction, the configuration shown in Figures 22A and 22B may be formed. Here, the taper angle of tapered portion 161a and the taper angle of tapered portion 161b may be equal, approximately equal, or different. Furthermore, the taper angle of the side surface of conductive layer 112 facing opening 123 may be larger or smaller than the taper angle of tapered portion 161a, and may also be larger or smaller than the taper angle of tapered portion 161b.

[0254] The taper angles of the side surfaces of the tapered portion 161a, the tapered portion 161b, and the conductive layer 112, as well as the positional relationship between the ends of the insulating layer 103a, the insulating layer 103b, and the conductive layer 112, which have been described using Figures 20 to 22, can be applied to all structures shown in this specification, etc.

[0255] 2A1, and shows an example in which the semiconductor layer 113 extends in the X direction to an end of the conductive layer 112 that does not face the opening 123. Fig. 23B is a cross-sectional view taken along the dashed dotted line A1-A2 shown in Fig. 23A.

[0256] 23B , when viewed from the XZ plane, the semiconductor layer 113 covers the end of the conductive layer 112 that does not face the opening 123. In addition, the semiconductor layer 113 can have a region in contact with the upper surface of the insulating layer 103.

[0257] 2A1, and shows an example in which, in the Y direction, the end of the semiconductor layer 113 is located outside the end of the conductive layer 112 and inside the end of the conductive layer 111. In the example shown in Fig. 24A, a part of the end of the semiconductor layer 113 overlaps with the conductive layer 111 but does not overlap with the conductive layer 112.

[0258] 2A1, and shows an example in which the end of the semiconductor layer 113 is located outside the end of the conductive layer 112 and the end of the conductive layer 111 in the Y direction. In the example shown in Fig. 24B, a part of the end of the semiconductor layer 113 does not overlap with either the conductive layer 111 or the conductive layer 112. Note that Fig. 2B can be referred to for the cross-sectional view of the dashed dotted line A1-A2 shown in Figs. 24A and 24B.

[0259] Fig. 25A is a modified example of the configuration shown in Fig. 2A1 , showing an example in which transistor 33 has two openings 121 and two openings 123, which are arranged in the X direction. Fig. 25B is a cross-sectional view taken along dashed dotted line A1-A2 shown in Fig. 25A . Here, in describing a configuration in which one transistor 33 has multiple openings 121 and multiple openings 123, the X direction may be referred to as the row direction and the Y direction may be referred to as the column direction.

[0260] 25A and 25B, the two openings 121 are distinguished by being referred to as opening 121_1 and opening 121_2, and the two openings 123 are distinguished by being referred to as opening 123_1 and opening 123_2. Also, in Fig. 25A and 25B, an example is shown in which different semiconductor layers 113 are provided inside the openings 121_1 and 123_1 and inside the openings 121_2 and 123_2, and these two semiconductor layers 113 are distinguished by being referred to as semiconductor layer 113_1 and semiconductor layer 113_2, respectively. Similar descriptions may be used in the subsequent drawings.

[0261] Fig. 26A is a modified example of the configuration shown in Fig. 25A , showing an example in which two openings 121 and openings 123 are arranged in the Y direction. Fig. 26B is a modified example of the configuration shown in Fig. 26A , showing an example in which one opening 121 and opening 123 are provided to the right of the two openings 121 and openings 123 arranged in the Y direction. Here, if the two openings 121 and openings 123 arranged in the Y direction are provided in a first row and one opening 121 and opening 123 is provided in a second row, for example, the centers of the openings 121 and openings 123 in the second row can be located between the centers of the upper openings 121 and openings 123 in the first row and the centers of the lower openings 121 and openings 123 in the first row in the Y direction.

[0262] 26C is a modified example of the configuration shown in Fig. 26A, and shows an example in which one opening 121 and one opening 123 are provided on each of the left and right sides of two openings 121 and 123 arranged in the Y direction. Here, if one opening 121 and one opening 123 are provided in the first row and the third row, and two openings 121 and 123 arranged in the Y direction are provided in the second row, for example, the centers of the openings 121 and 123 in the first row and the centers of the openings 121 and 123 in the third row can be located between the centers of the upper openings 121 and 123 in the second row and the centers of the lower openings 121 and 123 in the second row in the Y direction.

[0263] Fig. 27A is a modified example of the configuration shown in Fig. 2A1 , showing an example in which four openings 121 and openings 123 are arranged in a matrix of two rows and two columns. Fig. 27B is a modified example of the configuration shown in Fig. 25A , showing an example in which one opening 121 and opening 123 are provided below two openings 121 and opening 123 arranged in the X direction. Here, if two openings 121 and opening 123 arranged in the X direction are provided in the first row and one opening 121 and opening 123 is provided in the second row, for example, the centers of the openings 121 and opening 123 in the second row can be located between the centers of the openings 121 and opening 123 on the left side of the first row and the centers of the openings 121 and opening 123 on the right side of the first row in the X direction.

[0264] Fig. 27C is a modified example of the configuration shown in Fig. 27A, and shows an example in which the lower two openings 121 and opening 123 are located to the right of Fig. 27A. In the configuration shown in Fig. 27C, the four openings 121 and openings 123 are arranged in a zigzag pattern.

[0265] Fig. 28A is a modified example of the configuration shown in Fig. 2A1, showing an example in which nine apertures 121 and apertures 123 are arranged in a matrix of three rows and three columns. Fig. 28B is a modified example of the configuration shown in Fig. 28A, showing an example in which two apertures 121 and apertures 123 are provided in the center row. In the example shown in Fig. 28B, the apertures 121 and apertures 123 in the upper row and the apertures 121 and apertures 123 in the center row are arranged in a zigzag pattern. In addition, in the example shown in Fig. 28B, the apertures 121 and apertures 123 in the lower row and the apertures 121 and apertures 123 in the center row are arranged in a zigzag pattern.

[0266] Increasing the number of openings 121 and openings 123 provided in the transistor 33 can lengthen the peripheries of the openings 121 and openings 123 in a plan view. As described above, the channel width of the transistor 33 can be made equal to, for example, the length of the periphery of the opening 123 in a plan view. Therefore, providing the transistor 33 with a plurality of openings 121 and openings 123 can sometimes lengthen the channel width of the transistor 33. On the other hand, reducing the number of openings 121 and openings 123 provided in the transistor 33 can sometimes facilitate the manufacture of the transistor 33 and enable miniaturization of the transistor 33.

[0267] 29A is a modification of the configuration shown in Fig. 25A , and illustrates an example in which the semiconductor layer 113 provided inside the openings 121_1 and 123_1 is the same as the semiconductor layer 113 provided inside the openings 121_2 and 123_2. That is, Fig. 29A illustrates an example in which the transistor 33 has two openings 121 and two openings 123, and one semiconductor layer 113. Fig. 29B is a cross-sectional view taken along dashed dotted line A1-A2 shown in Fig. 29A .

[0268] 29A and 29B, for example, when the semiconductor layer 113 is formed by photolithography and etching, the alignment accuracy of the photomask can be reduced. Therefore, the transistor 33 can be easily manufactured. On the other hand, in the structure shown in FIG. 25A, the surface area of ​​the semiconductor layer 113 can be reduced, which may prevent impurities from being mixed into the semiconductor layer 113, for example. Note that the structures shown in FIGS. 26A to 28B can also include a single semiconductor layer 113.

[0269] Fig. 30A is a modified example of the configuration shown in Fig. 2A1, and shows an example in which conductive layer 112 extends in a direction parallel to conductive layer 115 and extends in a direction perpendicular to conductive layer 111. That is, in the example shown in Fig. 30A, conductive layer 112 and conductive layer 115 extend in the X direction, and conductive layer 111 extends in the Y direction. Fig. 30B is a cross-sectional view taken along dashed line B1-B2 shown in Fig. 30A.

[0270] 31A is a modification of the configuration shown in Fig. 4A, and is an example in which the configuration shown in Fig. 30A is applied to transistors 33[1], 33[2], 33[n-1], and 33[n]. In the example shown in Fig. 31A, the conductive layer 112 has a region extending in the Y direction in a region that does not overlap with the conductive layer 111 and the semiconductor layer 113.

[0271] Fig. 31B is a cross-sectional view taken along dashed line B3-B4 in Fig. 31A, showing a transistor 33[1] and a transistor 33[2].

[0272] 30A , in a plan view, both the Y-direction end and the −Y-direction end of the conductive layer 115 as viewed from the opening 123 have regions that overlap with the conductive layer 112. That is, the Y-direction end of the conductive layer 115 as viewed from the opening 123 is located inside the Y-direction end of the conductive layer 112 as viewed from the opening 123, and the −Y-direction end of the conductive layer 115 as viewed from the opening 123 is located inside the −Y-direction end of the conductive layer 112 as viewed from the opening 123, but this is not a limitation of one embodiment of the present invention. FIG. 32A illustrates an example in which the −Y-direction end of the conductive layer 115 as viewed from the opening 123 does not overlap with the conductive layer 112 in a plan view. That is, in the example illustrated in FIG. 32A , the −Y-direction end of the conductive layer 115 as viewed from the opening 123 is located outside the −Y-direction end of the conductive layer 112 as viewed from the opening 123. 32A , the end of the conductive layer 115_2 in the region functioning as the transistor 33[2] can be configured to protrude toward the conductive layer 115_1 with respect to the end of the conductive layer 112(1). Also, the end of the conductive layer 115_2 in the region functioning as the transistor 33[n] can be configured to protrude toward the conductive layer 115_1 with respect to the end of the conductive layer 112(n / 2).

[0273] 32B shows an example in which, in a plan view, the end of the conductive layer 115 in the Y direction as viewed from the opening 123 does not overlap with the conductive layer 112. That is, in the example shown in FIG. 32B , the end of the conductive layer 115 in the Y direction as viewed from the opening 123 is positioned outside the end of the conductive layer 112 in the Y direction as viewed from the opening 123. For example, when the transistor 33[1] shown in FIG. 31A has the structure shown in FIG. 32B , the end of the conductive layer 115_1 in the region functioning as the transistor 33[1] can be configured to protrude toward the conductive layer 115_2 beyond the end of the conductive layer 112(1). Furthermore, when the transistor 33[n-1] shown in FIG. 31A has the structure shown in FIG. 32B , the end of the conductive layer 115_1 in the region functioning as the transistor 33[n-1] can be configured to protrude toward the conductive layer 115_2 beyond the end of the conductive layer 112(n / 2).

[0274] 32C shows an example in which, in a plan view, neither the Y-direction end nor the −Y-direction end of conductive layer 115 as viewed from opening 123 overlaps with conductive layer 112. That is, in the example shown in Fig. 32C , the Y-direction end of conductive layer 115 as viewed from opening 123 is located outside the Y-direction end of conductive layer 112 as viewed from opening 123, and the −Y-direction end of conductive layer 115 as viewed from opening 123 is located outside the −Y-direction end of conductive layer 112 as viewed from opening 123.

[0275] Figure 33A is a modified example of the configuration shown in Figure 30A. Figure 33A shows an example in which the end of the conductive layer 115 is located more inward than the end of the semiconductor layer 113 in the Y direction, that is, on the opening 123 side. In the example shown in Figure 33A, the semiconductor layer 113 has a region that does not overlap with the conductive layer 115. With this configuration, the area of ​​the region where the conductive layer 115 and the conductive layer 112 overlap can be reduced. Therefore, the parasitic capacitance can be reduced.

[0276] Fig. 33B is a modified example of the configuration shown in Fig. 33A. Fig. 33B shows an example in which the end of conductive layer 115 is located more inward in the Y direction than the end of conductive layer 112 on the opening 123 side. In the example shown in Fig. 33B, openings 121 and 123 have areas that do not overlap with conductive layer 115. With this configuration, the area of ​​the overlapping area between conductive layer 115 and conductive layer 112 can be further reduced. Therefore, the parasitic capacitance can be further reduced.

[0277] Note that for cross-sectional views taken along dashed dotted line B1-B2 shown in Figures 32A, 32B, 32C, 33A, and 33B, refer to Figure 30B.

[0278] Fig. 34A is a modified example of the configuration shown in Fig. 30A , showing an example in which conductive layer 111 does not entirely overlap opening 121 but overlaps only a portion of it. Fig. 34B is a cross-sectional view taken along dashed dotted line B1-B2 shown in Fig. 34A . In the examples shown in Fig. 34A and 34B , semiconductor layer 113 has a region in opening 121 that does not overlap conductive layer 111.

[0279] 34A and 34B, it is possible to reduce the parasitic capacitance formed between the conductive layer 111 and the conductive layer 115. On the other hand, in the examples shown in Figures 30A and 30B, it is possible to increase the width of one of the source region and the drain region.

[0280] Fig. 35A1 is a modified example of the configuration shown in Fig. 34A , showing an example in which, in plan view, the conductive layer 112 covers part of the outer periphery of the opening 121 but does not cover the entirety. Fig. 35A2 is a modified example of the configuration shown in Fig. 35A1 , showing an example in which, in plan view, an end of the conductive layer 112 contacts the outer periphery of the opening 121 at a single point. In the example shown in Fig. 35A2, the opening 121 is circular in plan view, and one of the ends of the conductive layer 112 extending in the Y direction is a tangent to the opening 121. Fig. 35B is a cross-sectional view taken along dashed line B1-B2 shown in Figs. 35A1 and 35A2.

[0281] 35A1, 35A2, and 35B, the area of ​​the region where the conductive layer 112 and the conductive layer 115 overlap can be reduced. This reduces the parasitic capacitance. On the other hand, in the examples shown in FIGS. 34A and 34B, the width of the other of the source region and the drain region can be increased.

[0282] Fig. 36A is a modified example of the configuration shown in Fig. 35A1 and Fig. 35A2, and shows an example in which the conductive layer 112 does not overlap the opening 121. Fig. 36B is a cross-sectional view taken along the dashed dotted line B1-B2 shown in Fig. 36A.

[0283] 36A and 36B, the area of ​​the region where the conductive layer 112 and the conductive layer 115 overlap can be further reduced, thereby further reducing the parasitic capacitance.

[0284] Fig. 37A is a modified example of the configuration shown in Fig. 30A , and shows an example in which the semiconductor layer 113 extends in the X direction to an end of the conductive layer 112 that does not face the opening 123. Fig. 37B is a cross-sectional view taken along the dashed dotted line B1-B2 shown in Fig. 37A .

[0285] 37B , when viewed from the XZ plane, the semiconductor layer 113 covers the end of the conductive layer 112 that does not face the opening 123. In addition, the semiconductor layer 113 can have a region in contact with the upper surface of the insulating layer 103.

[0286] Fig. 38A is a modified example of the configuration shown in Fig. 30A, and shows an example in which transistor 33 has two openings 121 and two openings 123, which are arranged in the X direction. Fig. 38B is a cross-sectional view taken along dashed line B1-B2 shown in Fig. 38A.

[0287] Fig. 39A is a modified example of the configuration shown in Fig. 38A , showing an example in which two openings 121 and openings 123 are arranged in the Y direction. Fig. 39B is a modified example of the configuration shown in Fig. 39A , showing an example in which one opening 121 and opening 123 are provided to the right of the two openings 121 and openings 123 arranged in the Y direction. Here, if the two openings 121 and openings 123 arranged in the Y direction are provided in a first row and one opening 121 and opening 123 is provided in a second row, for example, the centers of the openings 121 and openings 123 in the second row can be located between the centers of the upper openings 121 and openings 123 in the first row and the centers of the lower openings 121 and openings 123 in the first row in the Y direction.

[0288] 39C is a modified example of the configuration shown in Fig. 39A, and shows an example in which one opening 121 and one opening 123 are provided on each of the left and right sides of two openings 121 and 123 arranged in the Y direction. Here, if one opening 121 and one opening 123 are provided in the first row and the third row, and two openings 121 and 123 arranged in the Y direction are provided in the second row, for example, the centers of the openings 121 and 123 in the first row and the centers of the openings 121 and 123 in the third row can be located between the centers of the upper openings 121 and 123 in the second row and the centers of the lower openings 121 and 123 in the second row in the Y direction.

[0289] Fig. 40A is a modified example of the configuration shown in Fig. 30A , showing an example in which four openings 121 and openings 123 are arranged in a matrix of two rows and two columns. Fig. 40B is a modified example of the configuration shown in Fig. 38A , showing an example in which one opening 121 and opening 123 are provided below two openings 121 and opening 123 arranged in the X direction. Here, if two openings 121 and opening 123 arranged in the X direction are provided in the first row and one opening 121 and opening 123 is provided in the second row, for example, the centers of the openings 121 and opening 123 in the second row can be located between the centers of the openings 121 and opening 123 on the left side of the first row and the centers of the openings 121 and opening 123 on the right side of the first row in the X direction.

[0290] Fig. 40C is a modified example of the configuration shown in Fig. 40A, and shows an example in which the lower two openings 121 and opening 123 are located to the right of Fig. 40A. In the configuration shown in Fig. 40C, the four openings 121 and openings 123 are arranged in a zigzag pattern.

[0291] Fig. 41A is a modified example of the configuration shown in Fig. 30A , showing an example in which nine apertures 121 and apertures 123 are arranged in a matrix of three rows and three columns. Fig. 41B is a modified example of the configuration shown in Fig. 41A , showing an example in which two apertures 121 and apertures 123 are provided in the center row. In the example shown in Fig. 41B , the apertures 121 and apertures 123 in the top row and the apertures 121 and apertures 123 in the center row are arranged in a zigzag pattern. In addition, in the example shown in Fig. 41B , the apertures 121 and apertures 123 in the bottom row and the apertures 121 and apertures 123 in the center row are arranged in a zigzag pattern.

[0292] As described above, the outer peripheries of the openings 121 and 123 in a plan view can be increased by increasing the number of openings 121 and 123 provided in the transistor 33. As described above, the channel width of the transistor 33 can be made equal to, for example, the outer periphery of the opening 123 in a plan view. Therefore, the channel width of the transistor 33 can be increased by providing a plurality of openings 121 and 123 in the transistor 33. On the other hand, the transistor 33 can be easily manufactured and miniaturized by reducing the number of openings 121 and 123 provided in the transistor 33.

[0293] 38A , the semiconductor layer 113 provided inside the openings 121_1 and 123_1 is the same as the semiconductor layer 113 provided inside the openings 121_2 and 123_2. That is, Fig. 42A shows an example in which the transistor 33 has two openings 121 and two openings 123, and one semiconductor layer 113. Fig. 42B is a cross-sectional view taken along dashed line B1-B2 shown in Fig. 42A .

[0294] 42A and 42B, for example, when the semiconductor layer 113 is formed by photolithography and etching, the alignment accuracy of the photomask can be reduced. Therefore, the transistor 33 can be easily manufactured. On the other hand, in the structure shown in FIG. 38A, the surface area of ​​the semiconductor layer 113 can be reduced, which may prevent impurities from being mixed into the semiconductor layer 113. Note that the structures shown in FIGS. 39A to 41B can also be formed using a single semiconductor layer 113.

[0295] <Example 1 of Manufacturing Method of Display Device> A manufacturing method of a display device according to one embodiment of the present invention will be described below with reference to the drawings. Here, the manufacturing method of a display device including the transistor 33 shown in FIGS. 2A1 and 2B will be described as an example.

[0296] Thin films (insulating films, semiconductor films, conductive films, etc.) constituting the display device can be formed using a sputtering method, a chemical vapor deposition (CVD) method, a vacuum evaporation method, a pulsed laser deposition (PLD) method, an atomic layer deposition (ALD) method, etc. CVD methods include a plasma enhanced chemical vapor deposition (PECVD) method and a thermal CVD method. One type of thermal CVD method is a metal organic chemical vapor deposition (MOCVD) method.

[0297] Furthermore, thin films (insulating films, semiconductor films, conductive films, etc.) constituting the display device may be formed by methods such as spin coating, dipping, spray coating, inkjet, dispensing, screen printing, offset printing, doctor knife, slit coating, roll coating, curtain coating, or knife coating.

[0298] The thin film can be processed by, for example, forming a resist mask by photolithography and then etching the thin film according to the pattern of the resist mask. Alternatively, the thin film may be processed by nanoimprinting, sandblasting, lift-off, or the like. Furthermore, an island-shaped thin film may be directly formed by a film formation method using a shielding mask such as a metal mask. Furthermore, a photosensitive thin film can be processed by exposure and development. In other words, a photosensitive thin film can be processed by photolithography.

[0299] In photolithography, the light used for exposure may be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture of these. Other light sources that can be used include ultraviolet light, KrF laser light, ArF laser light, etc. Exposure may also be performed by immersion exposure technology. Extreme ultraviolet (EUV) light or X-rays may also be used as the light used for exposure. An electron beam may also be used instead of the light used for exposure. Extreme ultraviolet light, X-rays, or an electron beam are preferred because they enable extremely fine processing. When exposure is performed by scanning a beam such as an electron beam, a photomask is not required.

[0300] The thin film can be etched by dry etching, wet etching, or the like.

[0301] 43A1 to 46B2 are diagrams illustrating a method for fabricating the configuration shown in Fig. 2A1 and Fig. 2B. A1 and B1 in each diagram are plan views, and A2 and B2 in each diagram are cross-sectional views taken along dashed line A1-A2 shown in each plan view.

[0302] [Formation of Conductive Layer 111] A conductive film to be the conductive layer 111 is formed over the substrate 101. The conductive film can be formed by, for example, a sputtering method. After a resist mask is formed on the conductive film by a photolithography process, the conductive film is processed to form an island-shaped conductive layer 111 that functions as one of a source electrode and a drain electrode (FIGS. 43A1 and 43A2). The conductive film can be processed by one or both of a wet etching method and a dry etching method.

[0303] [Formation of Insulating Layer 103a and Insulating Layer 103b] Next, the insulating layer 103a and the insulating layer 103b are formed on the substrate 101 and the conductive layer 111 (FIGS. 43B1 and 43B2). The insulating layer 103a and the insulating layer 103b can be formed, for example, by a PECVD method. After forming the insulating layer 103a, it is preferable to form the insulating layer 103b in succession in a vacuum without exposing the surface of the insulating layer 103a to the atmosphere. By successively forming the insulating layer 103a and the insulating layer 103b, it is possible to prevent impurities from the atmosphere from adhering to the surface of the insulating layer 103a. Examples of such impurities include water and organic substances.

[0304] The substrate temperature during the formation of the insulating layer 103a and the insulating layer 103b is preferably 180° C. or higher and 450° C. or lower, more preferably 200° C. or higher and 450° C. or lower, further preferably 250° C. or higher and 450° C. or lower, further preferably 300° C. or higher and 450° C. or lower, further preferably 300° C. or higher and 400° C. or lower, and further preferably 350° C. or higher and 400° C. or lower. By setting the substrate temperature within the above range during the formation of the insulating layer 103a and the insulating layer 103b, release of impurities (e.g., water and hydrogen) from the insulating layer itself can be reduced, and diffusion of the impurities into the semiconductor layer 113 can be suppressed. Therefore, a transistor exhibiting good electrical characteristics and high reliability can be manufactured.

[0305] Note that the insulating layer 103a and the insulating layer 103b are formed before the semiconductor layer 113. Therefore, there is no need to worry about oxygen being released from the semiconductor layer 113 due to heat applied when the insulating layer 103a and the insulating layer 103b are formed.

[0306] After the insulating layers 103a and 103b are formed, heat treatment may be performed. By performing the heat treatment, water and hydrogen can be released from the surfaces and the interior of the insulating layers 103a and 103b.

[0307] The temperature of the heat treatment is preferably 150° C. or higher and lower than the strain point of the substrate, more preferably 200° C. or higher and 450° C. or lower, further preferably 250° C. or higher and 450° C. or lower, further preferably 300° C. or higher and 450° C. or lower, further preferably 300° C. or higher and 400° C. or lower, and further preferably 350° C. or higher and 400° C. or lower. The heat treatment can be performed in an atmosphere containing one or more of a rare gas, nitrogen, or oxygen. As the nitrogen-containing atmosphere or the oxygen-containing atmosphere, dry air (CDA) may be used. Note that the atmosphere preferably contains as little hydrogen, water, or the like as possible. As the atmosphere, it is preferable to use a high-purity gas with a dew point of −60° C. or lower, preferably −100° C. or lower. Using an atmosphere containing as little hydrogen, water, or the like as possible can prevent hydrogen, water, or the like from being taken into the insulating layers 103a and 103b as much as possible. The heat treatment can be performed using an oven, a rapid thermal annealing (RTA) device, etc. By using an RTA device, the heat treatment time can be shortened.

[0308] [Formation of Conductive Film 112f] Subsequently, a conductive film 112f that will become the conductive layer 112 is formed on the insulating layer 103b (FIGS. 44A1 and 44A2). The conductive film 112f can be preferably formed by, for example, sputtering.

[0309] [Formation of Opening 121 and Opening 123] Subsequently, at least a portion of the conductive film 112f overlapping with the conductive layer 111 is removed to form the conductive layer 112A having the opening 123. The opening 123 can be formed by one or both of a wet etching method and a dry etching method. For example, the wet etching method can be suitably used to form the opening 123.

[0310] Next, the insulating layer 103 (insulating layer 103a and insulating layer 103b) is removed from at least a portion of the region overlapping with the conductive layer 111. This forms an opening 121 in the insulating layer 103 (FIGS. 44B1 and 44B2). The opening 121 can be formed by either or both of a wet etching method and a dry etching method. For example, the dry etching method can be suitably used to form the opening 121.

[0311] The opening 121 can be formed using, for example, the resist mask used to form the opening 123. Specifically, a resist mask can be formed over the conductive film 112f, the conductive film 112f is removed using the resist mask to form the opening 123, and the insulating layer 103 is removed using the resist mask to form the opening 121. Note that by processing the width of the opening 123 to be larger than that of the resist mask, a transistor 33 in which the width of the opening 123 is larger than that of the opening 121 can be manufactured, as shown in FIGS. 19A and 19B1 . Here, for example, when a transistor 33 in which the width of the opening 123 is different from that of the opening 121 is manufactured, the opening 121 may be formed using a resist mask different from the resist mask used to form the opening 123.

[0312] [Formation of Conductive Layer 112] Next, the conductive layer 112A is processed into a desired shape to form the conductive layer 112 (FIGS. 45A1 and 45A2). The conductive layer 112 can be formed by either or both of a wet etching method and a dry etching method. For example, the wet etching method can be suitably used to form the conductive layer 112.

[0313] [Formation of Semiconductor Layer 113] Subsequently, a semiconductor film 113f that will become the semiconductor layer 113 is formed so as to cover the openings 121 and 123 ( FIGS. 45B1 and 45B2 ). The semiconductor film 113f can be provided so as to have regions in contact with the upper surface and side surfaces of the conductive layer 112, the upper surface and side surfaces of the insulating layer 103, and the upper surface of the conductive layer 111.

[0314] The semiconductor film 113f is preferably formed by a sputtering method using a metal oxide target.

[0315] The semiconductor film 113f is preferably a dense film with as few defects as possible. Furthermore, the semiconductor film 113f is preferably a high-purity film in which impurities including hydrogen are reduced as much as possible. In particular, it is preferable to use a crystalline metal oxide film as the semiconductor film 113f.

[0316] When the semiconductor film 113f is formed, oxygen gas is preferably used. By using oxygen gas when the semiconductor film 113f is formed, oxygen can be suitably supplied into the insulating layer 103. For example, when an oxide is used for the insulating layer 103a, oxygen can be suitably supplied into the insulating layer 103a.

[0317] By supplying oxygen to the insulating layer 103a, oxygen is supplied to the semiconductor layer 113 in a later process, and oxygen vacancies (V Ｏ ) and V Ｏ H can be reduced.

[0318] When forming the semiconductor film 113f, oxygen gas may be mixed with an inert gas (e.g., helium gas, argon gas, or xenon gas). Note that the higher the ratio of oxygen gas to the total deposition gas when forming the semiconductor film 113f (oxygen flow ratio), the more the crystallinity of the semiconductor film 113f can be improved, resulting in a highly reliable transistor. On the other hand, the lower the oxygen flow ratio, the more the crystallinity of the semiconductor film 113f can be reduced, resulting in a transistor with a high on-state current.

[0319] The higher the substrate temperature when forming the semiconductor film 113f, the higher the crystallinity and density of the semiconductor film 113f. On the other hand, the lower the substrate temperature, the lower the crystallinity and electrical conductivity of the semiconductor film 113f.

[0320] The substrate temperature during the formation of the semiconductor film 113f may be set to a range from room temperature to 250° C., preferably from room temperature to 200° C., and more preferably from room temperature to 140° C. For example, it is preferable to set the substrate temperature to a range from room temperature to less than 140° C., because productivity is increased. Furthermore, by setting the substrate temperature to room temperature or by forming the semiconductor film 113f without heating the substrate, the crystallinity can be reduced.

[0321] Before forming the semiconductor film 113f, it is preferable to perform at least one of a treatment for removing water, hydrogen, organic substances, and the like adsorbed on the surface of the insulating layer 103 and a treatment for supplying oxygen into the insulating layer 103. For example, heat treatment can be performed at a temperature of 70° C. or higher and 200° C. or lower in a reduced pressure atmosphere. Alternatively, plasma treatment in an atmosphere containing oxygen may be performed. ２ Oxygen may be supplied to the insulating layer 103 by plasma treatment in an atmosphere containing an oxidizing gas such as nitrous oxide (NO). When plasma treatment containing nitrous oxide gas is performed, oxygen can be supplied while organic substances on the surface of the insulating layer 103 are suitably removed. After such treatment, it is preferable to form a semiconductor film 113f in succession without exposing the surface of the insulating layer 103 to the air.

[0322] In addition, when the semiconductor layer 113 has a stacked structure, it is preferable to form a metal oxide film first and then form a subsequent metal oxide film without exposing the surface of the first metal oxide film to the air.

[0323] Subsequently, the semiconductor film 113f is processed into an island shape to form the semiconductor layer 113 (FIGS. 46A1 and 46A2).

[0324] The semiconductor layer 113 can be formed by one or both of a wet etching method and a dry etching method. For example, a wet etching method can be suitably used for forming the semiconductor layer 113. At this time, a part of the conductive layer 112 in a region that does not overlap with the semiconductor layer 113 may be etched and become thinner. Similarly, a part of the insulating layer 103 in a region that does not overlap with either the semiconductor layer 113 or the conductive layer 112 may be etched and become thinner. For example, the insulating layer 103b of the insulating layer 103 may be removed by etching, and the surface of the insulating layer 103a may be exposed. Note that by using a material having a high etching selectivity with respect to the semiconductor film 113f for the insulating layer 103b, the thickness of the insulating layer 103b can be prevented from becoming thinner.

[0325] Heat treatment is preferably performed after the semiconductor film 113f is formed or after the semiconductor film 113f is processed into the semiconductor layer 113. The heat treatment can remove hydrogen or water contained in or adsorbed on the surface of the semiconductor film 113f or the semiconductor layer 113. Furthermore, the heat treatment may improve the film quality of the semiconductor film 113f or the semiconductor layer 113 (for example, reduce defects, improve crystallinity, etc.).

[0326] By the heat treatment, oxygen can also be supplied from the insulating layer 103a to the semiconductor film 113f or the semiconductor layer 113. In this case, it is more preferable to perform the heat treatment before processing into the semiconductor layer 113. The above description can be referred to for the heat treatment, and therefore detailed description thereof will be omitted.

[0327] Note that this heat treatment does not have to be performed if it is not necessary. Alternatively, the heat treatment may be omitted here and may be performed in a subsequent step. Furthermore, there are cases where a high-temperature treatment in a subsequent step, such as a film formation step, can also serve as the heat treatment.

[0328] [Formation of Insulating Layer 105] Subsequently, the insulating layer 105 is formed to cover the semiconductor layer 113, the conductive layer 112, and the insulating layer 103 (FIGS. 46B1 and 46B2). The insulating layer 105 can be preferably formed by PECVD.

[0329] When an oxide semiconductor is used for the semiconductor layer 113, the insulating layer 105 preferably functions as a barrier film that suppresses oxygen diffusion. The insulating layer 105 has a function of suppressing oxygen diffusion, which suppresses oxygen from diffusing from above the insulating layer 105 to the conductive layer 115 formed in a later step, thereby suppressing oxidation of the conductive layer 115. As a result, a highly reliable transistor with favorable electrical characteristics can be manufactured.

[0330] By increasing the temperature during the formation of the insulating layer 105 that functions as a gate insulating layer, the insulating layer can have fewer defects. However, if the temperature during the formation of the insulating layer 105 is high, oxygen is released from the semiconductor layer 113, and oxygen vacancies (V Ｏ ) and V ＯH may increase. The substrate temperature during the formation of the insulating layer 105 is preferably 180° C. or higher and 450° C. or lower, more preferably 200° C. or higher and 450° C. or lower, further preferably 250° C. or higher and 450° C. or lower, further preferably 300° C. or higher and 450° C. or lower, and further preferably 300° C. or higher and 400° C. or lower. By setting the substrate temperature during the formation of the insulating layer 105 within the above range, defects in the insulating layer 105 can be reduced and oxygen can be prevented from being released from the semiconductor layer 113. Therefore, a transistor with good electrical characteristics and high reliability can be manufactured.

[0331] Before forming the insulating layer 105, plasma treatment may be performed on the surface of the semiconductor layer 113. The plasma treatment can reduce impurities such as water adsorbed to the surface of the semiconductor layer 113. Therefore, impurities at the interface between the semiconductor layer 113 and the insulating layer 105 can be reduced, and a highly reliable transistor can be realized. This is particularly suitable when the surface of the semiconductor layer 113 is exposed to the air between the formation of the semiconductor layer 113 and the formation of the insulating layer 105. The plasma treatment can be performed in an atmosphere of oxygen, ozone, nitrogen, nitrous oxide, argon, or the like, for example. Furthermore, the plasma treatment and the formation of the insulating layer 105 are preferably performed successively without exposure to the air.

[0332] [Formation of Conductive Layer 115] Subsequently, a conductive film to be the conductive layer 115 is formed over the insulating layer 105. The conductive film can be preferably formed by, for example, a sputtering method. After a resist mask is formed over the conductive film by a photolithography process, the conductive film is processed to form the island-shaped conductive layer 115 that functions as a gate electrode.

[0333] Through the above steps, the transistor 33 shown in FIGS. 2A1 and 2B can be manufactured.

[0334] <Manufacturing Method Example 2 of Display Device> A manufacturing method different from the manufacturing method of the transistor 33 described in the above <Manufacturing Method Example 1 of Display Device> will be described. Note that descriptions of parts that overlap with the above description will be omitted, and only different parts will be described.

[0335] Figures 47A1, 47A2, 47B1, and 47B2 are diagrams illustrating a method for fabricating the configurations shown in Figures 2A1 and 2B. Figures 47A1 and 47B1 are plan views, and Figures 47A2 and 47B2 are cross-sectional views taken along dashed dotted line A1-A2 shown in Figures 47A1 and 47B1, respectively.

[0336] First, the steps up to the formation of the conductive film 112f are performed in the same manner as in <Manufacturing Method Example 1 of a Display Device>. Since the description of the steps up to the formation of the conductive film 112f can be referred to in connection with FIGS. 43A1 to 44A2, detailed description thereof will be omitted.

[0337] Next, the conductive film 112f is processed to form the conductive layer 112B (FIGS. 47A1 and 47A2). Here, the opening 123 does not need to be formed in the conductive layer 112B. The conductive layer 112B can be formed by one or both of a wet etching method and a dry etching method. For example, the wet etching method can be suitably used to form the conductive layer 112B.

[0338] Subsequently, the conductive layer 112B is removed from at least a portion of the region overlapping with the conductive layer 111, thereby forming the conductive layer 112 having the opening 123.

[0339] Next, the insulating layer 103 (insulating layer 103a and insulating layer 103b) is removed from at least a portion of the region overlapping with the conductive layer 111. This forms an opening 121 in the insulating layer 103 (FIGS. 47B1 and 47B2).

[0340] The openings 121 and 123 can be formed by referring to the description in <Example 1 of manufacturing method of display device>, and therefore detailed description thereof will be omitted.

[0341] Subsequently, a semiconductor film 113f to be the semiconductor layer 113 is formed so as to cover the openings 121 and 123 (FIGS. 45B1 and 45B2). Since the above-described description of <Example 1 of manufacturing method of display device> can be referred to for the process after the formation of the semiconductor film 113f, detailed description thereof will be omitted.

[0342] Through the above steps, the transistor 33 having the structure shown in FIGS. 2A1 and 2B can be manufactured.

[0343] <Configuration Example 3 of Display Device> Fig. 48 is a plan view showing a configuration example of a display device 10. As described above, the display device 10 has a display unit 20, in which pixels 21 are arranged in a matrix. Each pixel 21 has a plurality of sub-pixels. Fig. 48 shows two rows and two columns of pixels 21. Furthermore, each pixel 21 has three sub-pixels (sub-pixel 23R, sub-pixel 23G, and sub-pixel 23B), so that two rows and six columns of sub-pixels are shown. Furthermore, a connection unit 140 is provided on the outside of the display unit 20.

[0344] Each subpixel has a display element. Examples of the display element include a light-emitting element and a liquid crystal element (also referred to as a liquid crystal device). It is preferable to use, for example, an organic light-emitting diode (OLED) or a quantum-dot light-emitting diode (QLED). Examples of light-emitting materials included in the light-emitting element include a fluorescent material (fluorescent material), a phosphorescent material (phosphorescent material), a thermally activated delayed fluorescence (TADF) material), and an inorganic compound (such as a quantum dot material). Furthermore, an LED such as a micro light-emitting diode (LED) can also be used as the light-emitting element.

[0345] The light-emitting element can emit light of infrared, red, green, blue, cyan, magenta, yellow, white, etc. Furthermore, the color purity can be improved by providing the light-emitting element with a microcavity structure.

[0346] In the following, a configuration using a light-emitting element as a display element will be described as an example.

[0347] A display device according to one embodiment of the present invention has light-emitting elements each manufactured for a different light-emitting color and is capable of full-color display.

[0348] 48 corresponds to the planar shape of the light-emitting region of the light-emitting element. For an example of the planar shape of the sub-pixels and the arrangement of the sub-pixels, refer to Embodiment 2.

[0349] Each subpixel has a pixel circuit that controls a light-emitting element. The pixel circuit is not limited to the range of the subpixel shown in Fig. 48 and may be located outside it. For example, the transistor included in the pixel circuit of subpixel 23R may be located within the range of subpixel 23G shown in Fig. 48, or part or all of the transistor may be located outside the range of subpixel 23R.

[0350] 48 shows the subpixels 23R, 23G, and 23B as having the same or approximately the same aperture ratio (which can also be referred to as the size or the size of the light-emitting region), but this is not a limitation of one embodiment of the present invention. The aperture ratios of the subpixels 23R, 23G, and 23B can be determined as appropriate. The aperture ratios of the subpixels 23R, 23G, and 23B may be different from one another, or two or more of them may be the same or approximately the same.

[0351] A stripe arrangement is applied to the pixel 21 shown in FIG. 48 . The pixel 21 shown in FIG. 48 is composed of three subpixels: subpixel 23R, subpixel 23G, and subpixel 23B. The subpixels 23R, 23G, and 23B each emit light of a different color. Examples of the subpixels 23R, 23G, and 23B include subpixels of three colors: red (R), green (G), and blue (B), and subpixels of three colors: yellow (Y), cyan (C), and magenta (M). The number of colors of the subpixels is not limited to three, and may be four or more. Examples of four-color subpixels include subpixels of R, G, B, and white (W), subpixels of R, G, B, and Y, and subpixels of R, G, B, and infrared light (IR).

[0352] Although Figure 48 shows an example in which the connection portion 140 is located below the display unit in a plan view, the location of the connection portion 140 is not particularly limited. The connection portion 140 only needs to be located in at least one of the upper, right, left, and lower sides of the display unit in a plan view, and may be located so as to surround all four sides of the display unit. The planar shape of the connection portion 140 is not particularly limited, and may be strip-shaped, L-shaped, U-shaped, frame-shaped, or the like. Furthermore, the connection portion 140 may be singular or plural.

[0353] 49A to 49E are circuit diagrams showing configuration examples of a sub-pixel 23 (e.g., sub-pixel 23R, sub-pixel 23G, or sub-pixel 23B). The sub-pixel 23 has a pixel circuit 51 (pixel circuit 51A, pixel circuit 51B, pixel circuit 51C, pixel circuit 51D, or pixel circuit 51E) and a display element. 49A to 49D show an example having a light-emitting element 61 as the display element, and Fig. 49E shows an example having a liquid crystal element 62 as the display element.

[0354] A pixel circuit 51A shown in FIG. 49A is a 2Tr1C type pixel circuit having a transistor 52, a capacitor 53, and a transistor .

[0355] In the pixel circuit 51A, one of the source and drain of the transistor 52 is electrically connected to the gate of the transistor 54. The gate of the transistor 54 is electrically connected to one electrode of the capacitor 53. The other electrode of the capacitor 53 is electrically connected to one of the source and drain of the transistor 54. One of the source and drain of the transistor 54 is electrically connected to one electrode of the light-emitting element 61.

[0356] The other of the source and the drain of the transistor 52 is electrically connected to a wiring 47. The gate of the transistor 52 is electrically connected to a wiring 41. The other of the source and the drain of the transistor 54 is electrically connected to a wiring 63. The other electrode of the light-emitting element 61 is electrically connected to a wiring 65.

[0357] As described above, the wiring 41 functions as a scan line, and the wiring 47 functions as a signal line. The wiring 65 is a wiring that applies a potential for supplying current to the light-emitting element 61. The transistor 52 functions as a switch and controls the conduction or non-conduction state between the wiring 47 and the gate of the transistor 54 based on the potential of the wiring 41. For example, a high power supply potential (hereinafter also simply referred to as "VDD" or "high potential") is supplied to the wiring 63, and a low power supply potential (hereinafter also simply referred to as "VSS" or "low potential") is supplied to the wiring 65. Thus, the wiring 63 and the wiring 65 function as power supply lines.

[0358] The transistor 54 has a function of controlling the amount of current flowing through the light-emitting element 61. The capacitor 53 has a function of holding the gate potential of the transistor 54. The intensity of light emitted by the light-emitting element 61 is controlled in accordance with the potential supplied to the gate of the transistor 54 and corresponding to image data.

[0359] 49B has a configuration in which a transistor 55 is added to the pixel circuit 51A. The pixel circuit 51B is a 3Tr1C type pixel circuit.

[0360] One of the source and the drain of the transistor 55 is electrically connected to one of the source and the drain of the transistor 54, the other electrode of the capacitor 53, and one electrode of the light-emitting element 61. The other of the source and the drain of the transistor 55 is electrically connected to a wiring 67. A gate of the transistor 55 is electrically connected to a wiring 41.

[0361] The transistor 55 functions as a switch and controls conduction or non-conduction between the wiring 67 and one of the source and drain of the transistor 54, based on the potential of the wiring 41. A reference potential, for example, is supplied to the wiring 67. The reference potential of the wiring 67 supplied via the transistor 55 can suppress variations in the gate-source potential of the transistor 54.

[0362] Furthermore, a current value that can be used to set pixel parameters can be obtained using the wiring 67. More specifically, the wiring 67 can function as a monitor line for outputting the current flowing through the transistor 54 or the current flowing through the light-emitting element 61 to the outside. The current output to the wiring 67 can be converted into a voltage by, for example, a source follower circuit and output to the outside. Alternatively, it can be converted into a digital signal by an A-D converter or the like and output to the outside.

[0363] 49C has a configuration in which a transistor 56 is added to the pixel circuit 51B. The pixel circuit 51C is a 4Tr1C type pixel circuit.

[0364] The source or the drain of the transistor 56 is electrically connected to the source or the drain of the transistor 52, one electrode of the capacitor 53, and the gate of the transistor 54. The other of the source or the drain of the transistor 56 is electrically connected to a wiring 67.

[0365] The pixel circuit 51C is electrically connected to wirings 41a, 41b, and 41c as the wiring 41. The wiring 41a is electrically connected to the gate of the transistor 52. The wiring 41b is electrically connected to the gate of the transistor 55. The wiring 41c is electrically connected to the gate of the transistor 56. The transistor 56 functions as a switch and controls conduction or non-conduction between the wiring 67 and the gate of the transistor 54 based on the potential of the wiring 41c.

[0366] By turning on the transistors 55 and 56, the source and gate of the transistor 54 have the same potential, and the transistor 54 can be turned off. This forcibly cuts off the current flowing through the light-emitting element 61. Such a pixel circuit is suitable for use in a display method in which a display period and an off period are alternately provided.

[0367] 49D has a configuration in which a capacitor 57 is added to the pixel circuit 51C. The pixel circuit 51D is a 4Tr2C type pixel circuit.

[0368] One electrode of the capacitor 57 is electrically connected to one of the source and drain of the transistor 52, one electrode of the capacitor 53, the gate of the transistor 54, and one of the source and drain of the transistor 56. The other electrode of the capacitor 57 is electrically connected to a wiring 63.

[0369] A pixel circuit 51E shown in FIG. 49E is a 1Tr1C type pixel circuit having a transistor 52 and a capacitor 53.

[0370] In the pixel circuit 51E, one of the source and the drain of the transistor 52 is electrically connected to one electrode of the capacitor 53 and one electrode of the liquid crystal element 62. The other of the source and the drain of the transistor 52 is electrically connected to the wiring 47. The gate of the transistor 52 is electrically connected to the wiring 41.

[0371] In the pixel circuit 51E, the transistor 52 functions as a switch and controls the conduction or non-conduction state between the wiring 47 and one electrode of the liquid crystal element 62 based on the potential of the wiring 41. The capacitor 53 holds the potential of one electrode of the liquid crystal element 62. The alignment state of the liquid crystal element 62 is controlled in accordance with the potential supplied to one electrode of the liquid crystal element 62, which corresponds to image data.

[0372] The liquid crystal element 62 may be in any of the following modes: TN mode, STN mode, VA mode, ASM (Axially Symmetric Aligned Micro-cell) mode, OCB (Opticaly Compensated Birefringence) mode, FLC (Ferroelectric Liquid Crystal) mode, AFLC (AntiFerroelectric Liquid Crystal) mode, MVA mode, PVA (Patterned Vertical Alignment) mode, IPS mode, FFS mode, and TBA (Transverse Bend Alignment) mode. Other examples include an electrically controlled birefringence (ECB) mode, a polymer dispersed liquid crystal (PDLC) mode, a polymer network liquid crystal (PNLC) mode, and a guest host mode, but are not limited to these, and various other modes may be used.

[0373] The transistors 52, 54, 55, and 56 preferably have a structure similar to that applicable to the above-described transistor 33. This allows the on-state current of the transistor included in the subpixel 23 to be increased, thereby enabling the display device to be driven at high speed.

[0374] Note that the transistors 52, 54, 55, and 56 do not have to have the same configuration as the transistor 33. For example, at least one of the transistors 52, 54, 55, and 56 may have a configuration without the openings 121 and 123, specifically, may be a planar transistor. Here, when at least one of the transistors 52, 54, 55, and 56 has a configuration similar to the configuration applicable to the above-described transistor 33, the transistor 33 included in the demultiplexer circuit group 30 may have a configuration without the openings 121 and 123, for example. Alternatively, the display device 10 does not have to include the demultiplexer circuit group 30.

[0375] The transistors 52 and 56 are preferably OS transistors. As described above, an OS transistor has an extremely small off-state current and can therefore hold charge accumulated in the capacitor 53 electrically connected to the source or drain of the transistor 52 for a long period of time. This reduces the frequency of refresh operations compared to when a transistor with a large off-state current is used as the transistor 52. Therefore, the power consumption of the display device 10 can be reduced.

[0376] The transistors 54 and 55 may or may not be OS transistors. The transistors 54 and 55 may be, for example, Si transistors. The transistors 52 and 56 may not be, for example, OS transistors.

[0377] Fig. 50A is a plan view showing a configuration example of a pixel circuit 51 A. Fig. 50B is a cross-sectional view taken along dashed dotted line C1-C2 shown in Fig. 50A, showing a configuration example of a transistor 52, a capacitor 53, etc.

[0378] 50A and 50B , the structures of the transistor 52 and the transistor 54 are similar to those shown in FIGS. 2A1 and 2B . Here, the conductive layer 111, the conductive layer 112, the semiconductor layer 113, and the conductive layer 115 included in the transistor 52 are referred to as the conductive layer 111a, the conductive layer 112a, the semiconductor layer 113a, and the conductive layer 115a, respectively. The conductive layer 111, the conductive layer 112, the semiconductor layer 113, and the conductive layer 115 included in the transistor 54 are referred to as the conductive layer 111b, the conductive layer 112b, the semiconductor layer 113b, and the conductive layer 115b, respectively. Furthermore, the opening 121 and the opening 123 where the transistor 52 is provided are referred to as the opening 121a and the opening 123a, respectively, and the opening 121 and the opening 123 where the transistor 54 is provided are referred to as the opening 121b and the opening 123b, respectively.

[0379] The capacitor 53 includes a conductive layer 137 over the insulating layer 103, an insulating layer 105 over the conductive layer 137, and a conductive layer 139 that is provided over the insulating layer 105 and has a region overlapping with the conductive layer 137. The conductive layer 137 can be made of the same material as the conductive layers 112a and 112b and can be formed in the same process. The conductive layer 139 can be made of the same material as the conductive layers 115a and 115b and can be formed in the same process.

[0380] In the example shown in Figures 50A and 50B, a conductive layer 131 is provided. The conductive layer 131 can be made of the same material as the conductive layers 111a and 111b and can be formed in the same process. An insulating layer 103 is provided on the conductive layer 131. The insulating layer 103 has an opening 133a that reaches the conductive layer 131, and a conductive layer 112a is provided inside the opening 133a. For example, the conductive layer 112a is provided inside the opening 133a so as to have a region in contact with the conductive layer 131. This allows the conductive layer 131 and the conductive layer 112a to be electrically connected.

[0381] Furthermore, the insulating layer 103 has an opening 133b that reaches the conductive layer 111a, and a conductive layer 137 is provided inside the opening 133b. For example, the conductive layer 137 is provided inside the opening 133b so as to have a region in contact with the conductive layer 111a. This allows the conductive layer 111a and the conductive layer 137 to be electrically connected.

[0382] The insulating layer 103 and the insulating layer 105 have an opening 133c that reaches the conductive layer 111a, and the conductive layer 115b is provided inside the opening 133c. For example, the conductive layer 115b is provided inside the opening 133c so as to have a region in contact with the conductive layer 111a. This allows the conductive layer 111a and the conductive layer 115b to be electrically connected.

[0383] Furthermore, the insulating layer 103 and the insulating layer 105 have an opening 133d that reaches the conductive layer 111b, and a conductive layer 139 is provided inside the opening 133d. For example, the conductive layer 139 is provided inside the opening 133d so as to have a region that contacts the conductive layer 111b. This allows the conductive layer 111b and the conductive layer 139 to be electrically connected.

[0384] In FIG. 50A, the shape of the opening 133 is circular; however, one embodiment of the present invention is not limited to this, and the opening 133 can have a shape similar to that of the opening 121 or the opening 123 described above.

[0385] The conductive layer 131 functions as a wiring 47 that functions as a signal line. The conductive layer 115a functions as a wiring 41 that functions as a scan line. The conductive layer 112b functions as a wiring 63 that functions as a power supply line.

[0386] 50A and 50B , the conductive layer 112a serving as one of the source and drain electrodes of the transistor 52 is electrically connected to the conductive layer 137 serving as one electrode of the capacitor 53 and the conductive layer 115b serving as the gate electrode of the transistor 54. The conductive layer 112a serving as the other of the source and drain electrodes of the transistor 52 is electrically connected to the conductive layer 131 serving as the wiring 47. The transistor 52 shown in FIG. 50B has a region in which the distance between the conductive layer 112a and the conductive layer 115a is shorter than the distance between the conductive layer 111a and the conductive layer 115a. Therefore, the parasitic capacitance formed between the conductive layer 112a and the conductive layer 115a is larger than the parasitic capacitance formed between the conductive layer 111a and the conductive layer 115a. 1 is supplied to the gate electrode of the transistor 54. For example, the switching noise generated when the transistor 52 switches between an off state and an on state is larger in the conductive layer 112a than in the conductive layer 111a.

[0387] 50A and 50B , the conductive layer 111a, which is unlikely to be a noise source, is electrically connected to the conductive layer 115b, which functions as the gate electrode of the transistor 54. This can reduce the influence of noise on an image displayed in the display portion 20. Therefore, the display device of one embodiment of the present invention can have high display quality. Note that, for example, the conductive layer 111a may be used as the wiring 47, which functions as a signal line, and the conductive layer 112a may be electrically connected to, for example, the gate electrode of the transistor 54. This eliminates the need to provide the openings 133a, 133b, and 133c in the insulating layer 105.

[0388] Fig. 51A shows a configuration example in which a pixel electrode 311 of a light-emitting element 61 is added to the plan view shown in Fig. 50A. Fig. 51B is a cross-sectional view taken along dashed dotted line C3-C4 shown in Fig. 51A, and shows a configuration example of, for example, a transistor 54. Fig. 51B also shows a configuration example of layers above the transistor 54. Note that some of the reference numerals shown in Fig. 50A have been omitted in Figs. 51A and 51B.

[0389] An insulating layer 218 and an insulating layer 235 over the insulating layer 218 are provided so as to cover the transistor 52, the capacitor 53, and the transistor 54. A light-emitting element 61 is provided over the insulating layer 235, and a protective layer 331 is provided so as to cover the light-emitting element 61. A substrate 152 is attached to the protective layer 331 with an adhesive layer 142.

[0390] The light-emitting element 61 includes a pixel electrode 311 over an insulating layer 235, an island-shaped layer 313 over the pixel electrode 311, and a common electrode 315 over the island-shaped layer 313. The layer 313 includes at least a light-emitting layer. The layer 313 can be referred to as an EL layer. The common electrode is also referred to as a counter electrode.

[0391] The insulating layers 103, 105, 218, and 235 each have an opening 133e that reaches the conductive layer 111b. A pixel electrode 311 is provided to cover the opening 133e. The pixel electrode 311 has a shape that conforms to the upper and side surfaces of the insulating layer 235, the side surfaces of the insulating layer 218, the side surfaces of the insulating layer 105, the side surfaces of the insulating layer 103, and the upper surface of the conductive layer 111b. The pixel electrode 311 has regions that contact, for example, the upper and side surfaces of the insulating layer 235, the side surfaces of the insulating layer 218, the side surfaces of the insulating layer 105, the side surfaces of the insulating layer 103, and the upper surface of the conductive layer 111b. The pixel electrode 311 can be connected to the conductive layer 111b inside the opening 133e.

[0392] As described above, in the display device having the structure shown in Figures 51A and 51B, the conductive layer 111b functioning as one of the source and drain electrodes of the transistor 54 is electrically connected to the pixel electrode 311 functioning as one electrode of the light-emitting element 61. The conductive layer 112b functioning as the other of the source and drain electrodes of the transistor 54 is used as the wiring 63 functioning as a power supply line. The transistor 54 shown in Figure 51B has a region in which the distance between the conductive layer 112b and the conductive layer 115b is shorter than the distance between the conductive layer 111b and the conductive layer 115b. Therefore, the parasitic capacitance formed between the conductive layer 111b and the conductive layer 115b is smaller than the parasitic capacitance formed between the conductive layer 112b and the conductive layer 115b. Therefore, noise caused by the conductive layer 111b when the light-emitting element 61 emits light is smaller than the noise caused by the conductive layer 112b.

[0393] In the display device having the structure shown in FIGS. 51A and 51B , the conductive layer 111b, which is unlikely to be a noise source, is electrically connected to the pixel electrode 311, which functions as one electrode of the light-emitting element 61. On the other hand, the conductive layer 112b, which is likely to be a noise source, is used as the wiring 63, which functions as a power line. As described above, the influence of noise on an image displayed in the display portion 20 can be reduced. Therefore, the display device of one embodiment of the present invention can have high display quality. Note that, for example, the conductive layer 111b may be used as the wiring 63, which functions as a power line, and the conductive layer 112b may be electrically connected to the pixel electrode 311, which functions as one electrode of the light-emitting element 61. This eliminates the need for the opening 133e. Furthermore, since the opening 133d is not required in the insulating layer 103, the wiring distance from the other electrode of the capacitor 53 to one of the source electrode and drain electrode of the transistor 54 can be shortened.

[0394] An insulating layer 237 can be provided so as to cover the upper end portion of the pixel electrode 311. The insulating layer 237 functions as a partition wall (also referred to as a bank or spacer). By providing the insulating layer 237, it is possible to prevent the pixel electrode 311 and the common electrode 315 from coming into contact with each other and causing a short circuit in the light-emitting element 61.

[0395] A recess is formed in the pixel electrode 311 so as to cover the opening 133e, and the recess is filled with an insulating layer 237. For example, after forming the insulating layer 237 that covers the upper surface end of the pixel electrode 311 and the opening 133e, the layer 313 can be formed using a fine metal mask (FMM).

[0396] A light-shielding layer 317 may be provided on the surface of the substrate 152 on the adhesive layer 142 side. The light-shielding layer 317 can be provided between adjacent light-emitting elements 61. By providing the light-shielding layer 317, light emitted from adjacent sub-pixels 23 is blocked, making it possible to prevent color mixing. Note that a configuration in which the light-shielding layer 317 is not provided is also possible.

[0397] The following describes the components included in the display device shown in FIG. 51B.

[0398] <Component 2 of Display Device> [Insulating Layer 218] The insulating layer 218 is preferably made of a material that is difficult for impurities to diffuse into. As a result, the insulating layer 218 functions as a blocking film that prevents impurities from diffusing from the outside into the transistor. Examples of impurities include water and hydrogen. Providing the insulating layer 218 can improve the reliability of the display device.

[0399] The insulating layer 218 can be an insulating layer containing an inorganic material or an insulating layer containing an organic material. For example, an inorganic material such as oxide or nitride can be suitably used for the insulating layer 218. More specifically, one or more of silicon nitride, silicon nitride oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, aluminum nitride, hafnium oxide, and hafnium aluminate can be used. For example, silicon nitride oxide is suitable for use as the insulating layer 218 because it emits little impurities (e.g., water and hydrogen) from itself and can function as a blocking film that suppresses impurity diffusion from above the transistor to the transistor. For example, one or more of acrylic resin and polyimide resin can be used as the organic material. A photosensitive material may be used as the organic material. Two or more of the above insulating films may be stacked. The insulating layer 218 may have a stacked structure of an insulating layer containing an inorganic material and an insulating layer containing an organic material.

[0400] [Insulating Layer 235] The insulating layer 235 has a function of reducing unevenness caused by the transistor 52, the capacitor 53, the transistor 54, and the like. In this specification and the like, the insulating layer 235 may be referred to as a planarizing layer.

[0401] An insulating layer containing an organic material can be suitably used for the insulating layer 235. It is preferable to use a photosensitive organic resin as the organic material, and for example, it is preferable to use a photosensitive resin composition containing an acrylic resin. Note that in this specification, the term "acrylic resin" does not refer only to polymethacrylic acid ester or methacrylic resin, but may refer to all acrylic polymers in a broad sense.

[0402] The insulating layer 235 may be made of acrylic resin, polyimide resin, epoxy resin, imide resin, polyamide resin, polyimideamide resin, silicone resin, siloxane resin, benzocyclobutene-based resin, phenolic resin, or precursors of these resins. The insulating layer 235 may also be made of organic materials such as polyvinyl alcohol (PVA), polyvinyl butyral, polyvinylpyrrolidone, polyethylene glycol, polyglycerin, pullulan, water-soluble cellulose, or alcohol-soluble polyamide resin. A photoresist may also be used as the photosensitive resin. Either a positive-type material or a negative-type material may be used as the photosensitive organic resin.

[0403] The insulating layer 235 may have a laminated structure of an organic insulating layer and an inorganic insulating layer. For example, the insulating layer 235 may have a laminated structure of an organic insulating layer and an inorganic insulating layer on the organic insulating layer. By providing an inorganic insulating layer on the outermost surface of the insulating layer 235, it can function as an etching protection layer. This prevents a portion of the insulating layer 235 from being etched when the pixel electrode 311 is formed, thereby preventing the insulating layer 235 from becoming less flat.

[0404] If the flatness of the top surface of the insulating layer 235, which is the surface on which the light-emitting element 61 is formed, is low, for example, connection failure due to step disconnection of the common electrode 315 or a local thinning of the film thickness of the common electrode 315 may occur, resulting in an increase in electrical resistance. Furthermore, if the flatness of the top surface of the insulating layer 235 is low, the processing accuracy of layers formed on the insulating layer 235 may decrease. By flattening the top surface of the insulating layer 235, for example, the processing accuracy of the light-emitting element 61 provided on the insulating layer 235 can be improved, resulting in a display device with high definition. Furthermore, connection failure due to step disconnection of the common electrode 315 and an increase in electrical resistance due to a local thinning of the film thickness of the common electrode 315 can be prevented, resulting in a display device with high display quality.

[0405] Note that a part of the insulating layer 235 may be removed when forming the pixel electrode 311. The insulating layer 235 may have a recess in a region that does not overlap with the pixel electrode 311.

[0406] [Insulating Layer 237] The insulating layer 237 can be an insulating layer containing an inorganic material or an insulating layer containing an organic material. The insulating layer 237 can be made of the same material as the insulating layer 218 or the insulating layer 235. The insulating layer 237 may have a stacked structure of an insulating layer containing an inorganic material and an insulating layer containing an organic material.

[0407] [Protective Layer 331] The protective layer 331 may have a single-layer structure or a stacked structure of two or more layers. The conductivity of the protective layer 331 does not matter. The protective layer 331 can be formed using at least one of an insulating film, a semiconductor film, and a conductive film.

[0408] The protective layer 331 having an inorganic film can prevent the common electrode 315 from being oxidized and prevent impurities (such as moisture and oxygen) from entering the light-emitting element 61. This prevents deterioration of the light-emitting element 61 and improves the reliability of the display device.

[0409] For example, an inorganic insulating film such as an insulating oxide film, an insulating nitride film, an insulating oxynitride film, or an insulating nitride oxide film can be used for the protective layer 331. In particular, the protective layer 331 preferably includes an insulating nitride film or an insulating nitride oxide film, and more preferably includes a nitride insulating film.

[0410] The protective layer 331 may be formed using an inorganic film containing In—Sn oxide (also referred to as ITO), In—Zn oxide, Ga—Zn oxide, Al—Zn oxide, indium gallium zinc oxide (In—Ga—Zn oxide, also referred to as IGZO), or the like. The inorganic film preferably has high resistance, specifically, preferably has higher resistance than the common electrode 315. The inorganic film may further contain nitrogen.

[0411] When light emitted from the light-emitting element is extracted through the protective layer 331, it is preferable that the protective layer 331 has high transparency to visible light. For example, ITO, IGZO, and aluminum oxide are preferable because they are inorganic materials that have high transparency to visible light.

[0412] The protective layer 331 may have, for example, a stacked structure of an aluminum oxide film and a silicon nitride film on the aluminum oxide film, or a stacked structure of an aluminum oxide film and an IGZO film on the aluminum oxide film, etc. The use of such a stacked structure can prevent impurities (such as water and oxygen) from entering the EL layer.

[0413] Furthermore, the protective layer 331 may include an organic film. For example, the protective layer 331 may include both an organic film and an inorganic film.

[0414] The protective layer 331 may have a two-layer structure formed by using different film formation methods. Specifically, the first layer of the protective layer 331 may be formed by the ALD method, and the second layer of the protective layer 331 may be formed by the sputtering method.

[0415] [Substrate 152] The substrate 152 can be made of glass, quartz, ceramics, sapphire, resin, metal, alloy, semiconductor, or the like. A material that transmits light is used for the substrate on the side from which light from the light-emitting element is extracted. Furthermore, using a flexible material for the substrate 152 can increase the flexibility of the display device. A polarizing plate may also be used for the substrate 152. Furthermore, a lamination film or a base film may also be used for the substrate 152.

[0416] The substrate 152 may be made of polyester resin such as polyethylene terephthalate (PET) or polyethylene naphthalate (PEN), polyacrylonitrile resin, acrylic resin, polyimide resin, polymethyl methacrylate resin, polycarbonate (PC) resin, polyethersulfone (PES) resin, polyamide resin (nylon, aramid, or the like), polysiloxane resin, cycloolefin resin, polystyrene resin, polyamideimide resin, polyurethane resin, polyvinyl chloride resin, polyvinylidene chloride resin, polypropylene resin, polytetrafluoroethylene (PTFE) resin, ABS resin, cellulose nanofiber, or the like. The substrate 152 may also be made of glass having a thickness sufficient to provide flexibility.

[0417] When a film is used as a substrate, the film may absorb water, which may cause changes in shape, such as wrinkles, in the display device. Therefore, it is preferable to use a film with low water absorption for the substrate. For example, it is preferable to use a film with a water absorption rate of 1% or less, more preferably 0.1% or less, and even more preferably 0.01% or less.

[0418] Various optical members can be disposed on the outside of the substrate 152. Examples of optical members include a polarizing plate (e.g., a circular polarizing plate), a retardation plate, a light diffusion layer (e.g., a diffusion film), an anti-reflection layer, and a light-collecting film. In addition, a surface protection layer such as an anti-static film that suppresses the adhesion of dust, a water-repellent film that makes it difficult for dirt to adhere, a hard coat film that suppresses the occurrence of scratches during use, or an impact absorbing layer may be disposed on the outside of the substrate 152. For example, a glass layer or a silica layer (SiO ｘ The surface protection layer can be preferably formed of a material such as DLC (diamond-like carbon), aluminum oxide (AlO ｘ ), polyester-based materials, polycarbonate-based materials, etc. may be used for the surface protection layer. It is preferable to use a material with high transmittance to visible light for the surface protection layer. It is also preferable to use a material with high hardness for the surface protection layer.

[0419] When a circularly polarizing plate is superimposed on a display device, it is preferable that the display device has a substrate with high optical isotropy. A substrate with high optical isotropy has low birefringence (or a small amount of birefringence).

[0420] The absolute value of the retardation (phase difference) of a substrate having high optical isotropy is preferably 30 nm or less, more preferably 20 nm or less, and even more preferably 10 nm or less.

[0421] Examples of films with high optical isotropy include triacetyl cellulose (TAC, also known as cellulose triacetate) films, cycloolefin polymer (COP) films, cycloolefin copolymer (COC) films, and acrylic films.

[0422] [Adhesive Layer 142] Various curable adhesives can be used for the adhesive layer 142, such as photo-curable adhesives such as ultraviolet curable adhesives, reactive curable adhesives, thermosetting adhesives, or anaerobic adhesives. Examples of such adhesives include epoxy resin, acrylic resin, silicone resin, phenolic resin, polyimide resin, imide resin, PVC (polyvinyl chloride) resin, PVB (polyvinyl butyral) resin, and EVA (ethylene vinyl acetate) resin. Materials with low moisture permeability, such as epoxy resin, are particularly preferred. Two-component resins may also be used. Alternatively, an adhesive sheet may be used, for example.

[0423] [Light-shielding layer 317] Examples of materials that can be used for the light-shielding layer 317 include carbon black, oxide semiconductors, and composite oxides containing a solid solution of multiple oxide semiconductors. Furthermore, a laminated film of films containing the materials of the colored layers can also be used for the light-shielding layer. For example, a laminated structure can be used of a film containing the material used for a colored layer that transmits light of a certain color and a film containing the material used for a colored layer that transmits light of another color.

[0424] <Memory Cell> One embodiment of the present invention can be applied not only to a display device but also to a memory device. FIG. 52A is a block diagram showing a configuration example of a memory device 70 to which one embodiment of the present invention can be applied. The memory device 70 includes a memory portion 80, a word line driver circuit 71, a bit line driver circuit 73, and a power supply circuit 75. The memory portion 80 includes a plurality of memory cells 81 arranged in a matrix. Note that the power supply circuit 75 may be provided outside the memory device 70.

[0425] The word line driving circuit 71 is electrically connected to the memory cells 81 via wiring 41. For example, similar to the display device 10 shown in Fig. 1, the wiring 41 extends in the row direction of the matrix. In the memory device 70, the wiring 41 functions as a word line.

[0426] The bit line driving circuit 73 is electrically connected to the memory cells 81 via the wiring 47. For example, similar to the display device 10 shown in Figure 1, the wiring 47 extends in the column direction of the matrix. In the memory device 70, the wiring 41 functions as a bit line.

[0427] The power supply circuit 75 is electrically connected to the memory cells 81 via wiring 67. For example, all the memory cells 81 can be electrically connected to the power supply circuit 75 via the same wiring 67. The wiring 67 functions as a power supply line.

[0428] The word line driver circuit 71 has a function of selecting, for each row, a memory cell 81 to which data is to be written. The word line driver circuit 71 also has a function of selecting, for each row, a memory cell 81 from which data is to be read. Specifically, the word line driver circuit 71 can select a memory cell 81 to which data is to be written or a memory cell 81 from which data is to be read by outputting a signal to the wiring 41.

[0429] The bit line driver circuit 73 has a function of writing data to the memory cell 81 selected by the word line driver circuit 71 via the wiring 47. The bit line driver circuit 73 also has a function of amplifying the data output from the memory cell 81 to the wiring 47 and outputting the amplified data to, for example, the outside of the memory device 70, thereby reading out the data held in the memory cell 81. The bit line driver circuit 73 also has a function of precharging the wiring 47 before reading out data from the memory cell 81.

[0430] The power supply circuit 75 has a function of generating a power supply potential and supplying it to the wiring 67. The power supply circuit 75 has a function of generating, for example, a high potential or a low potential and supplying it to the wiring 67.

[0431] 52B, 52C, 52D, 52E, and 52F are circuit diagrams showing configuration examples of memory cells 81. Here, the memory cells 81 shown in Figures 52B, 52C, 52D, 52E, and 52F are referred to as memory cell 81A, memory cell 81B, memory cell 81C, memory cell 81D, and memory cell 81E, respectively.

[0432] The memory cell 81A includes a transistor 52 and a capacitor 53. That is, the memory cell 81A is a 1Tr1C type memory cell.

[0433] In the memory cell 81A, one of the source and the drain of the transistor 52 is electrically connected to a wiring 47. The other of the source and the drain of the transistor 52 is electrically connected to one electrode of a capacitor 53. The gate of the transistor 52 is electrically connected to a wiring 41. The other electrode of the capacitor 53 is electrically connected to a wiring 67.

[0434] In the memory cell 81A, data is written to the memory cell 81A through the wiring 47 by turning on the transistor 52, and the written data is held by turning off the transistor 52. Furthermore, by turning on the transistor 52, the data held in the memory cell 81A can be output to the wiring 47, and the bit line driver circuit 73 can read the data.

[0435] The memory cell 81B includes a transistor 52, a transistor 54, and a capacitor 53. In other words, the memory cell 81B is a 2Tr1C type memory cell.

[0436] The memory cell 81B is electrically connected to wirings 41a and 41d as wirings 41, and to wirings 47a and 47b as wirings 47. Specifically, one of the source or drain of the transistor 52 is electrically connected to wiring 47a. The other of the source or drain of the transistor 52 is electrically connected to one electrode of a capacitor 53. One electrode of the capacitor 53 is electrically connected to the gate of the transistor 54. The gate of the transistor 52 is electrically connected to wiring 41a. The other electrode of the capacitor 53 is electrically connected to wiring 41d. One of the source or drain of the transistor 54 is electrically connected to wiring 47b. The other of the source or drain of the transistor 54 is electrically connected to wiring 67.

[0437] In memory cell 81B, data is written to memory cell 81B through wiring 47a by turning on transistor 52, and the written data is retained by turning off transistor 52. Therefore, in memory cell 81B, wiring 41a can be referred to as a write word line, and wiring 47a can be referred to as a write bit line. Furthermore, by controlling the potential of wiring 41d, the gate potential of transistor 54 can be changed by capacitive coupling, and the potential of wiring 47b can be set to a potential corresponding to the data retained in memory cell 81B. This allows bit line driver circuit 73 to read data retained in memory cell 81B. Therefore, in memory cell 81B, wiring 41d can be referred to as a read word line, and wiring 47b can be referred to as a read bit line.

[0438] The memory cell 81C is a modification of the memory cell 81B, and shows an example in which the other of the source and the drain of the transistor 54 is electrically connected to the wiring 41d, and the other electrode of the capacitor 53 is electrically connected to the wiring 67. The word line driver circuit 71 controls the potential of the other of the source and the drain of the transistor 54, so that the memory cell 81C can output data held in the memory cell 81C to the wiring 47b.

[0439] The memory cell 81D is a modified example of the memory cell 81C, and differs from the memory cell 81C in that it includes a transistor 55. The memory cell 81D is a 3Tr1C type memory cell.

[0440] The memory cell 81D is electrically connected to wirings 41a and 41b as wirings 41. Specifically, the gate of the transistor 55 is electrically connected to the wiring 41b. One of the source and the drain of the transistor 54 is electrically connected to the source and the drain of the transistor 55. The other of the source and the drain of the transistor 54 is electrically connected to a wiring 67. The other of the source and the drain of the transistor 55 is electrically connected to a wiring 47b.

[0441] The transistor 55 functions as a switch and controls the conduction or non-conduction state between the wiring 47b and one of the source and drain of the transistor 54 based on the potential of the wiring 41b. By turning on the transistor 55, the potential of the wiring 47b can be set to a potential corresponding to the data stored in the memory cell 81D. This allows the bit line driver circuit 73 to read the data stored in the memory cell 81D. As described above, the wiring 41b can be considered a read word line in the memory cell 81D.

[0442] The memory cell 81E is a modification of the memory cell 81D, and differs from the memory cell 81D in that it does not include the capacitor 53. In the memory cell 81E, the wiring 67 is electrically connected to the other of the source and the drain of the transistor .

[0443] For example, if the parasitic capacitance such as the gate capacitance of the transistor 54 is sufficiently large, data can be held in the memory cell without providing the capacitor 53 .

[0444] An OS transistor is preferably used as the transistor 52 included in each of the memory cells 81A to 81E. As described above, an OS transistor has an extremely low off-state current. Therefore, by using an OS transistor as the transistor 52, the charge stored in the capacitor 53 can be held for a long period of time. Furthermore, the gate potential of the transistor 54 can be held for a long period of time. As described above, data written to the memory cell 81 can be held for a long period of time, and therefore the frequency of refresh operations (rewriting data to the memory cell 81) can be reduced. Therefore, the power consumption of the memory device 70 can be reduced.

[0445] It is also preferable to use OS transistors as the transistors 54 and 55. As described above, OS transistors have higher field-effect mobility than, for example, transistors using amorphous silicon. Therefore, by using OS transistors as the transistors 52 to 55, the memory device 70 can be driven at high speed.

[0446] The memory cell 81A can be called a DOSRAM (registered trademark). DOSRAM is an abbreviation for "Dynamic Oxide Semiconductor Random Access Memory." DOSRAM refers to a RAM having 1Tr1C type memory cells. DOSRAM is a DRAM formed using OS transistors, and is a memory that temporarily stores information sent from the outside. DOSRAM is a memory that takes advantage of the low off-state current of OS transistors.

[0447] The memory cells 81B to 81E can be referred to as NOSRAM (registered trademark). NOSRAM is an abbreviation for "Nonvolatile Oxide Semiconductor Random Access Memory (RAM)." NOSRAM can read stored data without destroying it (non-destructive read). Therefore, NOSRAM is suitable for arithmetic processing that repeats a large number of data read operations.

[0448] A plurality of configuration examples shown in this embodiment mode can be combined as appropriate. This embodiment mode can also be combined as appropriate with other embodiment modes.

[0449] Embodiment 2 In this embodiment, a display device of one embodiment of the present invention will be described with reference to FIGS. 53 and 54. FIG.

[0450] In this embodiment, pixel layouts different from that shown in Fig. 48 will be mainly described. There are no particular limitations on the arrangement of sub-pixels, and various methods can be applied. Examples of sub-pixel arrangements include a stripe arrangement, an S-stripe arrangement, a matrix arrangement, a delta arrangement, a Bayer arrangement, and a pentile arrangement.

[0451] The planar shape of the sub-pixel shown in the drawings in this embodiment corresponds to the planar shape of the light-emitting region (or light-receiving region).

[0452] The planar shape of the subpixel may be, for example, a triangle, a quadrangle (including a rectangle and a square), a polygon such as a pentagon, a polygon with rounded corners, an ellipse, or a circle.

[0453] The layout of the circuits constituting the sub-pixels is not limited to the range of the sub-pixels shown in the figure, and may be arranged outside of the range.

[0454] An S-stripe arrangement is applied to the pixel 21 shown in Fig. 53A. The pixel 21 shown in Fig. 53A is made up of three types of sub-pixels: sub-pixel 23a, sub-pixel 23b, and sub-pixel 23c.

[0455] The pixel 21 shown in Figure 53B has sub-pixels 23a and 23b each having a substantially trapezoidal or triangular planar shape with rounded corners, and sub-pixel 23c having a substantially rectangular or hexagonal planar shape with rounded corners. Furthermore, sub-pixel 23b has a larger light-emitting area than sub-pixel 23a. In this way, the shape and size of each sub-pixel can be determined independently. For example, the more reliable the light-emitting element, the smaller the size of the sub-pixel can be.

[0456] The Pentile arrangement is applied to the pixels 21a and 21b shown in Fig. 53C. Fig. 53C shows an example in which the pixel 21a having the sub-pixels 23a and 23b and the pixel 21b having the sub-pixels 23b and 23c are arranged alternately.

[0457] 53D to 53F are arranged in a delta configuration. Pixel 21a has two subpixels (subpixels 23a and 23b) in the top row (first row) and one subpixel (subpixel 23c) in the bottom row (second row). Pixel 21b has one subpixel (subpixel 23c) in the top row (first row) and two subpixels (subpixels 23a and 23b) in the bottom row (second row).

[0458] Figure 53D is an example in which each sub-pixel has a roughly rectangular planar shape with rounded corners, Figure 53E is an example in which each sub-pixel has a circular planar shape, and Figure 53F is an example in which each sub-pixel has a roughly hexagonal planar shape with rounded corners.

[0459] In Figure 53F, each subpixel is arranged inside a closely packed hexagonal region. Focusing on a single subpixel, it is surrounded by six other subpixels. Subpixels emitting light of the same color are arranged so that they are not adjacent to each other. For example, when focusing on subpixel 23a, three subpixels 23b and three subpixels 23c are arranged alternately to surround it.

[0460] 53G shows an example in which subpixels of each color are arranged in a zigzag pattern. Specifically, the positions of the upper sides of two subpixels aligned in the column direction (e.g., subpixels 23a and 23b, or subpixels 23b and 23c) are misaligned in a plan view.

[0461] 53A to 53G, it is preferable that, for example, subpixel 23a be subpixel R that emits red light, subpixel 23b be subpixel G that emits green light, and subpixel 23c be subpixel B that emits blue light. Note that the configuration of the subpixels is not limited to this, and the colors that the subpixels emit and their order of arrangement can be determined appropriately. For example, subpixel 23b may be subpixel R that emits red light, and subpixel 23a may be subpixel G that emits green light.

[0462] In photolithography, the finer the pattern to be processed, the more significant the effect of light diffraction becomes. This impairs the fidelity of the photomask pattern when it is transferred by exposure, making it difficult to process the resist mask into the desired shape. Therefore, even if the photomask pattern is rectangular, a pattern with rounded corners is likely to be formed. As a result, the planar shape of the subpixel may become a polygon with rounded corners, an ellipse, a circle, or the like.

[0463] In order to make the planar shape of the sub-pixel a desired shape, a technique for correcting the mask pattern in advance (OPC (Optical Proximity Correction) technique) may be used so that the design pattern and the transfer pattern coincide with each other. Specifically, with the OPC technique, a correction pattern is added to the corners of the figure on the mask pattern, for example.

[0464] As shown in Figures 54A to 54I, a pixel can be configured to have four types of sub-pixels.

[0465] The pixels 21 shown in FIGS. 54A to 54C are arranged in a stripe pattern.

[0466] Figure 54A is an example in which each subpixel has a rectangular planar shape, Figure 54B is an example in which each subpixel has a planar shape that combines two semicircles and a rectangle, and Figure 54C is an example in which each subpixel has an elliptical planar shape.

[0467] The pixels 21 shown in FIGS. 54D to 54F are arranged in a matrix.

[0468] Figure 54D is an example in which each sub-pixel has a square planar shape, Figure 54E is an example in which each sub-pixel has an approximately square planar shape with rounded corners, and Figure 54F is an example in which each sub-pixel has a circular planar shape.

[0469] 54G and 54H show an example in which one pixel 21 is configured in two rows and three columns.

[0470] 54G has three subpixels (subpixels 23a, 23b, and 23c) in the top row (first row) and one subpixel (subpixel 23d) in the bottom row (second row). In other words, pixel 21 has subpixel 23a in the left column (first column), subpixel 23b in the center column (second column), subpixel 23c in the right column (third column), and further has subpixels 23d across these three columns.

[0471] The pixel 21 shown in Figure 54H has three subpixels (subpixels 23a, 23b, and 23c) in the top row (first row) and three subpixels 23d in the bottom row (second row). In other words, the pixel 21 has subpixels 23a and 23d in the left column (first column), subpixels 23b and 23d in the center column (second column), and subpixels 23c and 23d in the right column (third column). By aligning the subpixels in the top row and bottom row as shown in Figure 54H, it becomes possible to efficiently remove dust that may occur during the manufacturing process, for example. Therefore, a display device with high display quality can be provided.

[0472] FIG. 54I shows an example in which one pixel 21 is configured with three rows and two columns.

[0473] 54I has subpixel 23a in the top row (first row), subpixel 23b in the center row (second row), subpixel 23c across the first and second rows, and one subpixel (subpixel 23d) in the bottom row (third row). In other words, pixel 21 has subpixels 23a and 23b in the left column (first column), subpixel 23c in the right column (second column), and subpixel 23d across these two columns.

[0474] The pixel 21 shown in FIGS. 54A to 54I is composed of four subpixels: a subpixel 23a, a subpixel 23b, a subpixel 23c, and a subpixel 23d.

[0475] The sub-pixels 23a, 23b, 23c, and 23d may each have a light-emitting element that emits light of a different color, such as sub-pixels of four colors R, G, B, and white (W), sub-pixels of four colors R, G, B, and Y, or sub-pixels of R, G, B, and infrared light (IR).

[0476] 54A to 54I , it is preferable that, for example, subpixel 23a be subpixel R that emits red light, subpixel 23b be subpixel G that emits green light, subpixel 23c be subpixel B that emits blue light, and subpixel 23d be subpixel W that emits white light, subpixel Y that emits yellow light, or subpixel IR that emits near-infrared light. With such a configuration, the pixel 21 shown in FIGS. 54G and 54H has a stripe layout of R, G, and B, thereby improving display quality. Furthermore, the pixel 21 shown in FIG. 54I has a so-called S-stripe layout of R, G, and B, thereby improving display quality.

[0477] The pixel 21 may have a sub-pixel having a light-receiving element.

[0478] In each pixel 21 shown in FIGS. 54A to 54I, any one of the sub-pixels 23a to 23d may be a sub-pixel having a light-receiving element.

[0479] 54A to 54I , it is preferable that, for example, subpixel 23a be a subpixel R that emits red light, subpixel 23b be a subpixel G that emits green light, subpixel 23c be a subpixel B that emits blue light, and subpixel 23d be a subpixel S that has a light-receiving element. With this configuration, the pixel 21 shown in FIGS. 54G and 54H has a stripe layout of R, G, and B, which can improve display quality. Furthermore, the pixel 21 shown in FIG. 54I has a so-called S-stripe layout of R, G, and B, which can improve display quality.

[0480] There are no particular limitations on the wavelength of light detected by the subpixel S having a light receiving element. The subpixel S can be configured to detect either or both of visible light and infrared light.

[0481] As shown in Figures 54J and 54K, a pixel can be configured to have five types of sub-pixels.

[0482] FIG. 54J shows an example in which one pixel 21 is configured in two rows and three columns.

[0483] 54J has three subpixels (subpixels 23a, 23b, and 23c) in the top row (first row) and two subpixels (subpixels 23d and 23e) in the bottom row (second row). In other words, pixel 21 has subpixels 23a and 23d in the left column (first column), subpixel 23b in the center column (second column), subpixel 23c in the right column (third column), and subpixel 23e from the second column to the third column.

[0484] FIG. 54K shows an example in which one pixel 21 is configured with three rows and two columns.

[0485] 54K has subpixel 23a in the top row (first row), subpixel 23b in the middle row (second row), subpixel 23c from the first row to the second row, and two subpixels (subpixel 23d and subpixel 23e) in the bottom row (third row). In other words, pixel 21 has subpixels 23a, 23b, and 23d in the left column (first column), and subpixels 23c and 23e in the right column (second column).

[0486] 54J and 54K, it is preferable that the subpixel 23a be the subpixel R that emits red light, the subpixel 23b be the subpixel G that emits green light, and the subpixel 23c be the subpixel B that emits blue light. With this configuration, the pixel 21 shown in Fig. 54J has a stripe layout of R, G, and B, which can improve display quality. Furthermore, the pixel 21 shown in Fig. 54K has a so-called S-stripe layout of R, G, and B, which can improve display quality.

[0487] In each pixel 21 shown in Figures 54J and 54K, for example, it is preferable to apply a subpixel S having a light receiving element to at least one of the subpixels 23d and 23e. When a light receiving element is used for both the subpixels 23d and 23e, the configurations of the light receiving elements may be different from each other. For example, the wavelength ranges of light detected may be at least partially different from each other. Specifically, one of the subpixels 23d and 23e may have a light receiving element that mainly detects visible light, and the other may have a light receiving element that mainly detects infrared light.

[0488] 54J and 54K, it is preferable that one of the subpixels 23d and 23e is a subpixel S having a light-receiving element, and the other is a subpixel having a light-emitting element that can be used as a light source. For example, it is preferable that one of the subpixels 23d and 23e is a subpixel IR that emits infrared light, and the other is a subpixel S having a light-receiving element that detects infrared light.

[0489] In a pixel having sub-pixels R, G, B, IR, and S, an image is displayed using the sub-pixels R, G, and B, and the sub-pixel IR is used as a light source, allowing the sub-pixel S to detect reflected infrared light emitted by the sub-pixel IR.

[0490] As described above, the display device of one embodiment of the present invention can employ various layouts for a pixel having a subpixel including a light-emitting element. The display device of one embodiment of the present invention can also employ a pixel having both a light-emitting element and a light-receiving element. In this case, various layouts can also be employed.

[0491] A plurality of configuration examples shown in this embodiment mode can be combined as appropriate. This embodiment mode can also be combined as appropriate with other embodiment modes.

[0492] Embodiment 3 In this embodiment, a display device according to one embodiment of the present invention will be described.

[0493] The display device of the present embodiment can be a high-definition display device, and can therefore be used, for example, as a display unit for a wristwatch-type or bracelet-type information terminal (wearable device), as well as a display unit for a wearable device that can be worn on the head, such as a head-mounted display (HMD) for VR, or a glasses-type device for AR.

[0494] [Display Device 10A] Fig. 55 is a perspective view showing a configuration example of the display device 10A, and Fig. 56 is a cross-sectional view showing a configuration example of the display device 10A. The configuration of the display device 10 shown in the first embodiment can be applied to the display device 10A.

[0495] The display device 10A has a configuration in which a substrate 152 and a substrate 101 are bonded together. In Fig. 55, the substrate 152 is clearly indicated by a dashed line.

[0496] The display device 10A includes a display unit 20, a connection unit 140, a circuit 164, wiring 165, etc. Fig. 55 shows an example in which an IC 173 and an FPC 172 are mounted on the display device 10A. Therefore, the configuration shown in Fig. 55 can also be said to be a display module including the display device 10A, an IC (integrated circuit), and an FPC.

[0497] In this specification and the like, a display device having a connector such as an FPC attached to a substrate, or a display device having an IC mounted on the substrate, is referred to as a display module.

[0498] The connection portion 140 is provided on the outside of the display portion 20. The connection portion 140 can be provided along one side or multiple sides of the display portion 20. The connection portion 140 may be single or multiple. Figure 55 shows an example in which the connection portion 140 is provided so as to surround the four sides of the display portion. The connection portion 140 electrically connects the common electrode of the light-emitting element and the conductive layer, and a potential can be supplied to the common electrode via the conductive layer.

[0499] The circuit 164 can have at least one of the scanning line driver circuit 11, the signal line driver circuit 13, the control circuit 15, and the demultiplexer circuit 31 shown in FIG.

[0500] The wiring 165 has a function of supplying signals and power to the display portion 20 and the circuit 164. The signals and power are input to the wiring 165 from the outside via the FPC 172 or input to the wiring 165 from the IC 173.

[0501] 55 shows an example in which an IC 173 is provided on a substrate 101 by a chip-on-glass (COG) method, a chip-on-film (COF) method, or the like. The IC 173 can include at least one of the scanning line driver circuit 11, the signal line driver circuit 13, the control circuit 15, and the demultiplexer circuit 31 shown in FIG. 1 of Embodiment 1. Note that the display device 10A and the display module may not include an IC. Alternatively, the IC may be mounted on an FPC by, for example, a COF method.

[0502] Figure 56 shows an example of a cross section of the display device 10A when cutting a portion of the area including the FPC 172, a portion of the circuit 164, a portion of the display unit 20, a portion of the connection portion 140, and a portion of the area including the end portion.

[0503] The display device 10A shown in FIG. 56 includes a transistor 201, a transistor 205R, a transistor 205G, a transistor 205B, a light-emitting element 61R, a light-emitting element 61G, and a light-emitting element 61B between a substrate 101 and a substrate 152. The light-emitting element 61R, the light-emitting element 61G, and the light-emitting element 61B can have a structure similar to that of the light-emitting element 61 shown in FIG. 51B of Embodiment 1. The pixel electrode 311 and the layer 313 included in the light-emitting element 61R are referred to as a pixel electrode 311R and a layer 313R, respectively. The pixel electrode 311 and the layer 313 included in the light-emitting element 61G are referred to as a pixel electrode 311G and a layer 313G, respectively. The pixel electrode 311 and the layer 313 included in the light-emitting element 61B are referred to as a pixel electrode 311B and a layer 313B, respectively. A common electrode 315 is provided on the layer 313R, the layer 313G, and the layer 313B. The common electrode 315 is shared by the light-emitting element 61R, the light-emitting element 61G, and the light-emitting element 61B. Figure 56 shows an example in which the conductive layer 111 of the transistor 205R is electrically connected to the pixel electrode 311R, the conductive layer 111 of the transistor 205G is electrically connected to the pixel electrode 311G, and the conductive layer 111 of the transistor 205B is electrically connected to the pixel electrode 311B.

[0504] In this specification and the like, when describing matters common to the transistor 205R, the transistor 205G, and the transistor 205B, the alphabets that distinguish them may be omitted and they may be referred to as the transistor 205. When describing matters common to other elements that are distinguished by alphabets, they may also be described using symbols without the alphabets.

[0505] An insulating layer 237 is provided so as to cover the upper surface end portions of the pixel electrode 311R, the pixel electrode 311G, and the pixel electrode 311B. In addition, recesses are formed in the pixel electrode 311R, the pixel electrode 311G, and the pixel electrode 311B so as to cover the openings of the insulating layer 103, the insulating layer 105, the insulating layer 218, and the insulating layer 235. The insulating layer 237 is filled into the recesses.

[0506] 56 shows multiple cross sections of the insulating layer 237, but when the display device 10A is viewed from above, the insulating layer 237 is connected as one. In other words, the display device 10A can be configured to have one insulating layer 237. Note that the display device 10A may also have multiple insulating layers 237 that are separated from one another.

[0507] The layer 313R, the layer 313G, and the layer 313B each include at least a light-emitting layer. For example, the layer 313R includes a light-emitting layer that emits red light, the layer 313G includes a light-emitting layer that emits green light, and the layer 313B includes a light-emitting layer that emits blue light. In other words, the layer 313R includes a light-emitting material that emits red light, the layer 313G includes a light-emitting material that emits green light, and the layer 313B includes a light-emitting material that emits blue light. As described above, the light-emitting element 61R can emit red light, the light-emitting element 61G can emit green light, and the light-emitting element 61B can emit blue light.

[0508] Layer 313R, layer 313G, and layer 313B may each include one or more of a hole injection layer, a hole transport layer, a hole blocking layer, a charge generation layer, an electron blocking layer, an electron transport layer, and an electron injection layer.

[0509] For example, the layer 313R, the layer 313G, and the layer 313B may each include a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and an electron injection layer in this order. Alternatively, an electron blocking layer may be provided between the hole transport layer and the light-emitting layer. Alternatively, a hole blocking layer may be provided between the electron transport layer and the light-emitting layer.

[0510] For example, the layer 313R, the layer 313G, and the layer 313B may each include an electron injection layer, an electron transport layer, an emitting layer, a hole transport layer, and a hole injection layer in this order. Alternatively, a hole blocking layer may be provided between the electron transport layer and the emitting layer. Alternatively, an electron blocking layer may be provided between the hole transport layer and the emitting layer.

[0511] The light-emitting elements 61R, 61G, and 61B may have a single structure (a structure having only one light-emitting unit) or a tandem structure (a structure having multiple light-emitting units). The light-emitting unit has at least one light-emitting layer.

[0512] When a tandem structure is applied to the light-emitting elements 61R, 61G, and 61B, it is preferable that the layer 313R has a structure having a plurality of light-emitting units that emit red light, the layer 313G has a structure having a plurality of light-emitting units that emit green light, and the layer 313B has a structure having a plurality of light-emitting units that emit blue light. It is preferable to provide a charge generation layer between each of the light-emitting units. For example, when a tandem structure is applied to the light-emitting elements 61R, 61G, and 61B, the layer 313R, 313G, and 313B can have a first light-emitting unit, a charge generation layer on the first light-emitting unit, and a second light-emitting unit on the charge generation layer.

[0513] The layers 313R, 313G, and 313B can each be formed by, for example, a vacuum deposition method using a fine metal mask. When using a vacuum deposition method using a fine metal mask, deposition is often performed over an area wider than the openings of the fine metal mask. The layers 313R, 313G, and 313B can be formed over an area wider than the openings of the fine metal mask. The ends of the layers 313R, 313G, and 313B each have a tapered shape. The layers 313R, 313G, and 313B may also be formed on the insulating layer 237. The layers 313R, 313G, and 313B may also be formed by a sputtering method using a fine metal mask or an inkjet method.

[0514] A protective layer 331 is provided on the light-emitting elements 61R, 61G, and 61B. The protective layer 331 and the substrate 152 are bonded via an adhesive layer 142. A light-shielding layer 317 is provided on the substrate 152. A solid sealing structure, a hollow sealing structure, or the like can be applied to seal the light-emitting elements. In FIG. 56 , the space between the substrate 152 and the substrate 101 is filled with the adhesive layer 142, and a solid sealing structure is applied. Alternatively, the space may be filled with an inert gas (nitrogen, argon, etc.), and a hollow sealing structure may be applied. In this case, the adhesive layer 142 may be provided so as not to overlap with the light-emitting elements. Alternatively, the space may be filled with a resin different from the frame-shaped adhesive layer 142.

[0515] The protective layer 331 is provided at least on the display unit 20, and is preferably provided so as to cover the entire display unit 20. The protective layer 331 is preferably provided so as to cover not only the display unit 20 but also the connection unit 140 and the circuit 164. Furthermore, the protective layer 331 is preferably provided up to the edge of the display device 10A.

[0516] A connection portion 204 is provided in a region of the substrate 101 that does not overlap with the substrate 152. In the connection portion 204, the wiring 165 is electrically connected to the FPC 172 via a conductive layer 166 and a connection layer 242. The conductive layer 166 can be formed in the same process as the pixel electrodes 311R, 311G, and 311B. The conductive layer 166 is exposed on the top surface of the connection portion 204. This allows the connection portion 204 and the FPC 172 to be electrically connected via the connection layer 242.

[0517] Note that the connecting portion 204 has a portion where the protective layer 331 is not provided in order to electrically connect the FPC 172 and the conductive layer 166. For example, after the protective layer 331 is formed on the entire surface of the display device 10A, a mask is used to remove a region of the protective layer 331 that overlaps with the conductive layer 166, thereby exposing the conductive layer 166.

[0518] A laminated structure of at least one organic layer and a conductive layer may be provided on the conductive layer 166, and a protective layer 331 may be provided on the laminated structure. A peeling initiation point (a portion that triggers peeling) may then be formed on the laminated structure using a laser or a sharp blade (e.g., a needle or cutter), and the laminated structure and the protective layer 331 thereon may be selectively removed to expose the conductive layer 166. For example, the protective layer 331 can be selectively removed by pressing an adhesive roller against the substrate 101 and moving the roller relative to the substrate 101 while rotating. Alternatively, adhesive tape may be attached to the substrate 101 and peeled off. Because of poor adhesion between the organic layer and the conductive layer, or between the organic layers themselves, separation occurs at the interface between the organic layer and the conductive layer or within the organic layer. This allows selective removal of the region of the protective layer 331 that overlaps with the conductive layer 166. If an organic layer remains on the conductive layer 166, it can be removed using an organic solvent.

[0519] The organic layer can be, for example, at least one organic layer (a layer functioning as a light-emitting layer, a carrier blocking layer, a carrier transport layer, or a carrier injection layer) used in any of the layers 313B, 313G, and 313R. The organic layer may be formed when any of the layers 313B, 313G, and 313R is formed, or may be provided separately. The conductive layer can be formed in the same process and with the same material as the common electrode 315. For example, an ITO film is preferably formed as the common electrode 315 and the conductive layer. When a stacked structure is used for the common electrode 315, at least one of the layers constituting the common electrode 315 is provided as the conductive layer.

[0520] The upper surface of the conductive layer 166 may be covered with a mask so that the protective layer 331 is not formed on the conductive layer 166. The mask may be, for example, a metal mask (area metal mask), or an adhesive or adhesive tape or film. The protective layer 331 is formed with the mask in place, and then the mask is removed, so that the conductive layer 166 can remain exposed even after the protective layer 331 is formed.

[0521] By using such a method, a region where the protective layer 331 is not provided is formed in the connection portion 204 , and in this region, the conductive layer 166 and the FPC 172 can be electrically connected via the connection layer 242 .

[0522] In the connection portion 140, a conductive layer 323 is provided on the insulating layer 235. Ends of the conductive layer 323 are covered with the insulating layer 237. In addition, a common electrode 315 is provided on the conductive layer 323, and for example, the conductive layer 323 and the common electrode 315 have a region where they are in contact with each other in the connection portion 140. This allows the common electrode 315 to be electrically connected to the conductive layer 323 provided in the connection portion 140. For the conductive layer 323, it is preferable to use a conductive layer formed from the same material and in the same process as the pixel electrodes 311R, 311G, and 311B. It is preferable that the layers 313R, 313G, and 313B are not formed on the conductive layer 323.

[0523] The display device 10A is a top-emission type. Light emitted from the light-emitting elements is emitted toward the substrate 152. Therefore, it is preferable to use a material that is highly transparent to visible light for the substrate 152. On the other hand, the light-transmitting property of the material used for the substrate 101 is not an issue.

[0524] A material that is highly transparent to visible light is used for the common electrode 315. It is preferable that each of the pixel electrodes 311R, 311G, and 311B is made of a material that reflects visible light.

[0525] The transistor 201 and the transistor 205 are both formed over a substrate 101. These transistors can be manufactured using the same material and through the same process. The transistor 201 and the transistor 205 can preferably have a structure similar to that of the transistor 33 described in Embodiment 1. The transistor 201 provided in the circuit 164 can be applied to, for example, the transistor 33 shown in FIG. 1 of Embodiment 1.

[0526] The transistors included in the circuit 164 may have the same structure as or different from the transistors included in the display portion 20. The transistors included in the circuit 164 may all have the same structure or may have two or more types. Similarly, the transistors included in the display portion 20 may all have the same structure or may have two or more types.

[0527] All of the transistors included in the display portion 20 may be OS transistors, all of the transistors included in the display portion 20 may be Si transistors, or some of the transistors included in the display portion 20 may be OS transistors and the rest may be Si transistors.

[0528] For example, by using both an LTPS transistor and an OS transistor in the display portion 20, a display device with low power consumption and high driving capability can be realized. A configuration in which an LTPS transistor and an OS transistor are combined is sometimes referred to as LTPO. It is more preferable to use an OS transistor as a transistor that functions as a switch for controlling conduction / non-conduction between wirings and an LTPS transistor as a transistor for controlling current.

[0529] For example, one of the transistors included in the display unit 20 functions as a transistor for controlling a current flowing to a light-emitting element and can also be called a driving transistor. One of the source and drain of the driving transistor is electrically connected to a pixel electrode of the light-emitting element. It is preferable to use an LTPS transistor as the driving transistor. This allows a large current to flow to the light-emitting element in the pixel circuit.

[0530] On the other hand, another transistor included in the display unit 20 functions as a switch for controlling pixel selection / non-selection and can also be called a selection transistor. The gate of the selection transistor is electrically connected to a gate line, and one of the source and drain is electrically connected to a signal line. It is preferable to use an OS transistor as the selection transistor. This allows the gradation of pixels to be maintained even when the frame frequency is significantly reduced (for example, 1 fps or less), and therefore power consumption can be reduced by stopping the driver when displaying a still image.

[0531] It is preferable to provide a light-shielding layer 317 on the surface of the substrate 152 facing the substrate 101. The light-shielding layer 317 can be provided between adjacent light-emitting elements, on the connection section 140, on the circuit 164, etc. In addition, various optical members can be arranged on the outside of the substrate 152.

[0532] The connection layer 242 may be an anisotropic conductive film (ACF), an anisotropic conductive paste (ACP), or the like.

[0533] 57A is a cross-sectional view showing a configuration example of the display device 10B. The display device 10B is a modified example of the display device 10A, and differs from the display device 10A in the configurations of, for example, the transistor 201, the transistor 205R, the transistor 205G, and the transistor 205B.

[0534] The transistor 201 and the transistor 205 included in the display device 10B each include a conductive layer 221 functioning as a gate, an insulating layer 211 functioning as a first gate insulating layer, conductive layers 222a and 222b functioning as a source and a drain, a semiconductor layer 231, an insulating layer 213 functioning as a second gate insulating layer, and a conductive layer 323 functioning as a gate. Here, the same hatching pattern is applied to multiple layers obtained by processing the same conductive film. The insulating layer 211 is located between the conductive layer 221 and the semiconductor layer 231. The insulating layer 213 is located between the conductive layer 323 and the semiconductor layer 231. Figure 57A illustrates an example in which the conductive layer 222b of the transistor 205R is electrically connected to the pixel electrode 311R, the conductive layer 222b of the transistor 205G is electrically connected to the pixel electrode 311G, and the conductive layer 222b of the transistor 205B is electrically connected to the pixel electrode 311B.

[0535] For example, the conductive layer 221 can be formed using a material similar to that which can be used for the conductive layer 111. The conductive layers 222a and 222b can be formed using a material similar to that which can be used for the conductive layer 112. The conductive layer 323 can be formed using a material similar to that which can be used for the conductive layer 115. The insulating layers 211 and 213 can be formed using a material similar to that which can be used for the insulating layer 103a or that which can be used for the insulating layer 103b.

[0536] The semiconductor layer 231 can be formed using a material similar to that of the semiconductor layer 113. When LTPS, for example, is used for the semiconductor layer 231, the field-effect mobility of the transistor 201 and the transistor 205 can be increased. Thus, the display device 10B can be driven at high speed.

[0537] The structure of the transistor included in the display device of this embodiment is not particularly limited. For example, a planar transistor, a staggered transistor, an inverted staggered transistor, or the like can be used. Furthermore, either a top-gate transistor or a bottom-gate transistor structure may be used. Alternatively, gates may be provided above and below a semiconductor layer in which a channel is formed.

[0538] The transistor 201 and the transistor 205 have a structure in which a semiconductor layer in which a channel is formed is sandwiched between two gates. The two gates may be connected and the same signal may be supplied to drive the transistor. Alternatively, the threshold voltage of the transistor may be controlled by applying a potential for controlling the threshold voltage to one of the two gates and a potential for driving to the other.

[0539] 57A can be applied to, for example, a transistor included in the signal line driver circuit 13 shown in FIG. 1 of Embodiment 1. The transistor 201 shown in FIG. 57A can be applied to, for example, a transistor included in the scan line driver circuit 11 shown in FIG. 1 of Embodiment 1. The transistor 201 shown in FIG. 57A can be applied to, for example, a transistor included in the control circuit 15 shown in FIG. 1 of Embodiment 1.

[0540] 57B and 57C show other examples of transistor configurations.

[0541] The transistor 209 and the transistor 210 each include a conductive layer 221 functioning as a gate, an insulating layer 211 functioning as a first gate insulating layer, a semiconductor layer 231 including a channel formation region 231i and a pair of low-resistance regions 231n, a conductive layer 222a electrically connected to one of the pair of low-resistance regions 231n, a conductive layer 222b electrically connected to the other of the pair of low-resistance regions 231n, an insulating layer 225 functioning as a second gate insulating layer, a conductive layer 323 functioning as a gate, and an insulating layer 215 covering the conductive layer 323. The insulating layer 211 is located between the conductive layer 221 and the channel formation region 231i. The insulating layer 225 is located at least between the conductive layer 323 and the channel formation region 231i. Furthermore, an insulating layer 218 covering the transistor may be provided.

[0542] 57B shows an example in which the insulating layer 225 covers the top surface and side surface of the semiconductor layer 231. The conductive layer 222a and the conductive layer 222b are electrically connected to the low-resistance region 231n through openings provided in the insulating layer 225 and the insulating layer 215, respectively. One of the conductive layer 222a and the conductive layer 222b functions as a source, and the other functions as a drain.

[0543] 57C , the insulating layer 225 overlaps with the channel formation region 231i of the semiconductor layer 231 but does not overlap with the low-resistance region 231n. For example, the insulating layer 225 is processed using the conductive layer 323 as a mask, thereby manufacturing the structure shown in FIG. 57C . In FIG. 57C , the insulating layer 215 is provided to cover the insulating layer 225 and the conductive layer 323, and the conductive layer 222a and the conductive layer 222b are electrically connected to the low-resistance region 231n through the openings in the insulating layer 215.

[0544] 58 is a cross-sectional view showing a configuration example of a display device 10 C. The display device 10 C is a modification of the display device 10 A, and differs from the display device 10 A in the configuration of the transistor 201, for example.

[0545] The transistor 201 of the display device 10C includes conductive layers 112a and 112b on the insulating layer 103, a semiconductor layer 231 on the conductive layer 112a, the conductive layer 112b, and the insulating layer 103, an insulating layer 105 on the semiconductor layer 231, the conductive layer 112a, and the conductive layer 112b, and a conductive layer 115 on the insulating layer 105 that has an area overlapping with the semiconductor layer 231.

[0546] The conductive layer 112a and the conductive layer 112b can be formed using the same material and process as the conductive layer 112 included in the transistor 205. The conductive layer 112a functions as one of the source electrode and the drain electrode of the transistor 201, and the conductive layer 112b functions as the other of the source electrode and the drain electrode of the transistor 201. That is, in the transistor 201 having the structure shown in FIG. 58, the source electrode and the drain electrode can be formed in the same process.

[0547] The semiconductor layer 231 can be made of silicon, for example, LTPS. Using LTPS for the semiconductor layer 231 can increase the field-effect mobility of the transistor 201. Therefore, the circuit 164 including the transistor 201 can be driven at high speed. Note that the semiconductor layer 231 may contain the same material as the semiconductor layer 113, for example, the semiconductor layer 231 may contain a metal oxide.

[0548] 58 can be applied to, for example, a transistor included in the signal line driver circuit 13 shown in FIG. 1 of Embodiment 1. The transistor 201 shown in FIG. 58 can be applied to, for example, a transistor included in the scanning line driver circuit 11 shown in FIG. 1 of Embodiment 1. The transistor 201 shown in FIG. 58 can be applied to, for example, a transistor included in the control circuit 15 shown in FIG. 1 of Embodiment 1. Note that the transistor 201 shown in FIG. 58 may be applied to the transistor 33 shown in FIG. 1 of Embodiment 1.

[0549] In the display device 10C, the elements of the transistor 201 can be formed in the same process as the elements of the transistor 205. Therefore, the number of manufacturing steps of the display device can be reduced compared to when the elements of the transistor 201 are formed in a different process from the elements of the transistor 205. Therefore, the manufacturing method of the display device can be simplified. Note that when the semiconductor layer 231 contains the same material as the semiconductor layer 113, the semiconductor layer 231 can be formed in the same process as the semiconductor layer 113.

[0550] The structure of the transistor 201 included in the display device 10C can be applied to the transistors 201 and 205 included in the display device 10B. In this case, the semiconductor layer included in the transistor 201 and the semiconductor layer included in the transistor 205 may be manufactured in different processes. This allows the semiconductor layer included in the transistor 201 to be made of different materials from the semiconductor layer included in the transistor 205.

[0551] 59 is a cross-sectional view showing a configuration example of the display device 10D. The display device 10D is a modified example of the display device 10A, and differs from the display device 10A in that it is a bottom-emission type display device, for example.

[0552] In the display device 10D, light emitted from the light-emitting element 61 is emitted toward the substrate 101. It is preferable that a material having high transparency to visible light is used for the substrate 101. On the other hand, the light-transmitting property of the material used for the substrate 152 does not matter.

[0553] A light-shielding layer 317 is preferably formed between the substrate 101 and the transistor 201 and between the substrate 101 and the transistor 205. Fig. 59 shows an example in which the light-shielding layer 317 is provided over the substrate 101, an insulating layer 353 is provided over the light-shielding layer 317, and the transistors 201, 205, and the like are provided over the insulating layer 353.

[0554] The pixel electrodes 311R, 311G, and 311B are each made of a material that is highly transparent to visible light, and the common electrode 315 is preferably made of a material that reflects visible light.

[0555] The configuration of the display device 10D can also be applied to the display device 10B and the display device 10C. Specifically, the display device 10B and the display device 10C can be bottom-emission display devices. Furthermore, by using a material that is highly transparent to visible light for both the pixel electrode 311 and the common electrode 315, the display devices 10A to 10D can be dual-emission (dual-emission) display devices. In the dual-emission display device 10, it is preferable to use a material that is highly transparent to visible light for both the substrate 101 and the substrate 152.

[0556] 60 is a cross-sectional view showing an example of the configuration of the display device 10E. The display device 10E is a modified example of the display device 10A, and differs from the display device 10A, for example, in the configurations of the light-emitting elements 61R, 61G, and 61B. The display device 10E also differs from the display device 10A in that it does not have the insulating layer 237, that the layer 313 covers the upper and side surfaces of the pixel electrode 311, and that it has the insulating layer 325, the insulating layer 327, and the common layer 314.

[0557] The display device 10E differs from the display device 10A in that the pixel electrodes 311R, 311G, 311B, and conductive layer 323 have different configurations, and in that a layer 328 is provided.

[0558] 60 , the pixel electrode 311 included in the light-emitting element 61 has a stacked structure of a conductive layer 324, a conductive layer 326 on the conductive layer 324, and a conductive layer 329 on the conductive layer 326. Here, the conductive layer 324, the conductive layer 326, and the conductive layer 329 included in the pixel electrode 311R are referred to as conductive layer 324R, conductive layer 326R, and conductive layer 329R, respectively. The conductive layer 324, the conductive layer 326, and the conductive layer 329 included in the pixel electrode 311G are referred to as conductive layer 324G, conductive layer 326G, and conductive layer 329G, respectively. Furthermore, the conductive layer 324, the conductive layer 326, and the conductive layer 329 included in the pixel electrode 311B are referred to as conductive layer 324B, conductive layer 326B, and conductive layer 329B, respectively.

[0559] The conductive layer 324 is electrically connected to the conductive layer 111 included in the transistor 205 through openings provided in the insulating layer 103 , the insulating layer 105 , the insulating layer 218 , and the insulating layer 235 .

[0560] The end of the conductive layer 326 is located inside the end of the conductive layer 324 and the end of the conductive layer 329. In other words, the end of the conductive layer 326 is located on the conductive layer 324, and the top surface and side surfaces of the conductive layer 326 are covered with the conductive layer 329.

[0561] The visible light transmittance and reflectance of the conductive layer 324 are not particularly limited. The conductive layer 324 may be a conductive layer that is transparent to visible light or a conductive layer that is reflective to visible light. For example, an oxide conductive layer may be used as the conductive layer that is transparent to visible light. Specifically, In—Si—Sn oxide (ITSO) may be suitably used as the conductive layer 324. For example, a metal such as aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, silver, tin, zinc, silver, platinum, gold, molybdenum, tantalum, or tungsten, or an alloy containing any of these metals as a main component (for example, an alloy of silver, palladium, and copper (APC: Ag—Pd—Cu)), may be used as the conductive layer 324. The conductive layer 324 may have a stacked structure of a conductive layer that is transparent to visible light and a conductive layer that is reflective over the conductive layer. The conductive layer 324 is preferably made of a material that has high adhesion to a surface on which the conductive layer 324 is formed (here, the insulating layer 235). This can prevent the conductive layer 324 from peeling off.

[0562] The conductive layer 326 can be a conductive layer that is reflective to visible light. The conductive layer 326 may have a stacked structure of a conductive layer that is transparent to visible light and a conductive layer that is reflective over the conductive layer. The conductive layer 326 can be made of any material that can be used for the conductive layer 324. Specifically, the conductive layer 326 can preferably have a stacked structure of In—Si—Sn oxide (ITSO) and an alloy of silver, palladium, and copper (APC) on the In—Si—Sn oxide (ITSO).

[0563] The conductive layer 329 can be formed using a material that can be used for the conductive layer 324. For example, a conductive layer that is transparent to visible light can be used for the conductive layer 329. Specifically, the conductive layer 329 can be formed using In—Si—Sn oxide (ITSO).

[0564] When a material that is easily oxidized is used for the conductive layer 326, by using a material that is not easily oxidized for the conductive layer 329 and covering the conductive layer 326 with the conductive layer 329, oxidation of the conductive layer 326 can be suppressed. Furthermore, deposition of metal components contained in the conductive layer 326 can be suppressed. For example, when a material containing silver is used for the conductive layer 326, In—Si—Sn oxide (ITSO) can be suitably used for the conductive layer 329. This can suppress oxidation of the conductive layer 326 and deposition of silver.

[0565] The conductive layer 323 may have a stacked structure of, for example, a conductive layer 324p, a conductive layer 326p on the conductive layer 324p, and a conductive layer 329p on the conductive layer 326p. The conductive layer 324p may be formed in the same process as the conductive layers 324R, 324G, and 324B. The conductive layer 326p may be formed in the same process as the conductive layers 326R, 326G, and 326B. The conductive layer 329p may be formed in the same process as the conductive layers 329R, 329G, and 329B.

[0566] 60 shows an example in which the film thickness of the conductive layer 329p is different from the film thickness of the conductive layer 329R, the conductive layer 329G, and the conductive layer 329B. The film thicknesses of the conductive layer 329p, the conductive layer 329R, the conductive layer 329G, and the conductive layer 329B may be made different depending on the resistivity of the material used for these layers. When the film thicknesses are made different, the conductive layer 329p may be formed in a different process from the conductive layer 329R, the conductive layer 329G, and the conductive layer 329B. Alternatively, the process of forming the conductive layer 329p may be partially common to the process of forming the conductive layer 329R, the conductive layer 329G, and the conductive layer 329B.

[0567] Recesses are formed in the conductive layer 324R, the conductive layer 324G, and the conductive layer 324B so as to cover the openings provided in the insulating layer 103, the insulating layer 105, the insulating layer 218, and the insulating layer 235. A layer 328 is buried in the recesses.

[0568] The layer 328 has a function of planarizing the recesses of the conductive layer 324R, the conductive layer 324G, and the conductive layer 324B. The conductive layers 326R, 326G, and 326B, which are electrically connected to the conductive layers 324R, 324G, and 324B, are provided over the conductive layers 324R, 324G, 324B, and the layer 328. Therefore, the regions of the conductive layers 324R, 324G, and 324B that overlap with the recesses also function as light-emitting regions, and the aperture ratio of the pixel can be increased.

[0569] The layer 328 may be an insulating layer or a conductive layer. Various inorganic insulating materials, organic insulating materials, and conductive materials can be used as appropriate for the layer 328. In particular, the layer 328 is preferably formed using an insulating material, and more preferably using an organic insulating material. For example, the organic insulating material that can be used for the insulating layer 327 can be used for the layer 328.

[0570] When the layer 328 is a conductive layer, the layer 328 can function as a part of a pixel electrode.

[0571] The layer 328 included in the display device 10E can also be applied to the display devices 10A to 10D. For example, instead of the insulating layer 237, the layer 328 can be embedded in at least a part of the recesses of the pixel electrode 311R, the pixel electrode 311G, and the pixel electrode 311B.

[0572] 60 shows an example in which the end of the layer 313 is located outside the end of the pixel electrode 311. The layer 313 is formed so as to cover the end of the pixel electrode 311. With this configuration, it is possible to make the entire upper surface of the pixel electrode 311 the light-emitting region, and the aperture ratio can be increased compared to a configuration in which the end of the island-shaped layer 313 is located inside the end of the pixel electrode 311. Furthermore, by covering the side surface of the pixel electrode 311 with the layer 313, it is possible to prevent the pixel electrode 311 and the common electrode 315 from coming into contact with each other, thereby preventing short circuits in the light-emitting element 61.

[0573] The insulating layer 237 is not provided between the pixel electrode 311 and the layer 313. This allows the distance between adjacent light-emitting elements 61 to be small. Therefore, the display device 10E can be a high-definition or high-resolution display device. Furthermore, a mask for forming the insulating layer is not required, which reduces the manufacturing cost of the display device.

[0574] The layer 313 can be formed using, for example, photolithography and etching. Specifically, after forming a pixel electrode 311 for each subpixel, a film to become the layer 313 is formed over the multiple pixel electrodes 311. Subsequently, a mask layer is formed on the film to become the layer 313, and a resist mask is formed on the mask layer using photolithography. Then, the mask layer and the film to become the layer 313 are processed using, for example, etching, and the resist mask is removed. For example, the mask layer may have a two-layer stacked structure of a first mask layer and a second mask layer on the first mask layer. In this case, a resist mask is formed on the second mask layer, and the second mask layer is processed. Subsequently, the resist mask is removed. Then, the first mask layer and the film to become the layer 313 are processed using the second mask layer, for example, as a hard mask. As a result, one island-shaped layer 313 is formed for each pixel electrode 311. Thus, the layer 313 is divided into subpixels, and an island-shaped layer 313 can be formed for each subpixel. For example, by performing the steps from film formation to processing of the film that becomes the layer 313 three times, the layers 313R, 313G, and 313B can be separately produced.

[0575] By forming the island-shaped layer 313 without using a fine metal mask, it is possible to form a layer 313 with a fine size. Furthermore, by providing the layer 313 in an island shape for each light-emitting element 61, it is possible to suppress leakage current between adjacent light-emitting elements 61. This makes it possible to prevent crosstalk caused by unintended light emission, and to realize a display device with extremely high contrast. In particular, it is possible to realize a display de...

Claims

1. a signal line driver circuit, a control circuit, a first transistor, a second transistor, a first insulating layer, a first pixel, and a second pixel; the first transistor has a first conductive layer, a second conductive layer, a third conductive layer, a first semiconductor layer, and a second insulating layer; the second transistor includes the second conductive layer, a fourth conductive layer, a fifth conductive layer, a second semiconductor layer, and the second insulating layer; the first insulating layer is provided on the first conductive layer and on the fourth conductive layer; the second conductive layer is provided on the first insulating layer; the first insulating layer has a first opening reaching the first conductive layer and a second opening reaching the fourth conductive layer; the second conductive layer has a third opening having a region overlapping with the first opening and a fourth opening having a region overlapping with the second opening; the first semiconductor layer has a region in contact with the first conductive layer and a region in contact with the second conductive layer, and is provided to have a region located inside the first opening and a region located inside the third opening; the second semiconductor layer has a region in contact with the second conductive layer and a region in contact with the fourth conductive layer, and is provided to have a region located inside the second opening and a region located inside the fourth opening; the second insulating layer is provided on the first semiconductor layer and the second semiconductor layer so as to have regions located inside the first to fourth openings, respectively; the third conductive layer is provided on the second insulating layer so as to have a region located inside the first opening and a region located inside the third opening; the fifth conductive layer is provided on the second insulating layer so as to have a region located inside the second opening and a region located inside the fourth opening; the first conductive layer is electrically connected to the first pixel; the fourth conductive layer is electrically connected to the second pixel; the second conductive layer is electrically connected to the signal line driver circuit; the control circuit has a function of generating a first signal and outputting it to the third conductive layer; the control circuit has a function of generating a second signal and outputting it to the fifth conductive layer; A display device, wherein the first signal and the second signal are complementary to each other.

2. In claim 1, The display device, wherein the first semiconductor layer and the second semiconductor layer include a metal oxide.

3. a signal line driver circuit, a control circuit, a first transistor, a second transistor, a third transistor, a fourth transistor, a first insulating layer, a first pixel, a second pixel, a third pixel, and a fourth pixel; the first transistor has a first conductive layer, a second conductive layer, a third conductive layer, a first semiconductor layer, and a second insulating layer; the second transistor includes the second conductive layer, a fourth conductive layer, a fifth conductive layer, a second semiconductor layer, and the second insulating layer; the third transistor includes the third conductive layer, a sixth conductive layer, a seventh conductive layer, a third semiconductor layer, and the second insulating layer; the fourth transistor includes the fifth conductive layer, the seventh conductive layer, an eighth conductive layer, a fourth semiconductor layer, and the second insulating layer; the first insulating layer is provided on the first conductive layer, the fourth conductive layer, the sixth conductive layer, and the eighth conductive layer; the second conductive layer and the seventh conductive layer are provided on the first insulating layer; the first insulating layer has a first opening reaching the first conductive layer, a second opening reaching the fourth conductive layer, a third opening reaching the sixth conductive layer, and a fourth opening reaching the eighth conductive layer; the second conductive layer has a fifth opening having a region overlapping with the first opening and a sixth opening having a region overlapping with the second opening; the seventh conductive layer has a seventh opening having a region overlapping with the third opening and an eighth opening having a region overlapping with the fourth opening; the first semiconductor layer has a region in contact with the first conductive layer and a region in contact with the second conductive layer, and is provided to have a region located inside the first opening and a region located inside the fifth opening; the second semiconductor layer has a region in contact with the second conductive layer and a region in contact with the fourth conductive layer, and is provided to have a region located inside the second opening and a region located inside the sixth opening; the third semiconductor layer has a region in contact with the sixth conductive layer and a region in contact with the seventh conductive layer, and is provided to have a region located inside the third opening and a region located inside the seventh opening; the fourth semiconductor layer has a region in contact with the seventh conductive layer and a region in contact with the eighth conductive layer, and is provided to have a region located inside the fourth opening and a region located inside the eighth opening; the second insulating layer is provided on the first semiconductor layer, the second semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer so as to have regions located inside the first to eighth openings, respectively; the third conductive layer is provided on the second insulating layer so as to have a region located inside the first opening, a region located inside the third opening, a region located inside the fifth opening, and a region located inside the seventh opening; the fifth conductive layer is provided on the second insulating layer so as to have a region located inside the second opening, a region located inside the fourth opening, a region located inside the sixth opening, and a region located inside the eighth opening; the first conductive layer is electrically connected to the first pixel; the fourth conductive layer is electrically connected to the second pixel; the sixth conductive layer is electrically connected to the third pixel; the eighth conductive layer is electrically connected to the fourth pixel; the second conductive layer and the seventh conductive layer are electrically connected to the signal line driver circuit; the control circuit has a function of generating a first signal and outputting it to the third conductive layer; the control circuit has a function of generating a second signal and outputting it to the fifth conductive layer; A display device, wherein the first signal and the second signal are complementary to each other.

4. In claim 3, The first to fourth semiconductor layers include a metal oxide.

5. In claim 2 or claim 4, The display device, wherein the metal oxide comprises indium, zinc, and M (M is one or more selected from aluminum, titanium, gallium, germanium, tin, yttrium, zirconium, lanthanum, cerium, neodymium, and hafnium).