Semiconductor device and method for semiconductor device fabrication

Abstract

The present invention provides a semiconductor device having a transistor of a very small size. In the semiconductor device, a second conductive layer is provided above the first conductive layer, the second conductive layer has a first opening that overlaps with the first conductive layer, a third conductive layer is provided above the second conductive layer, the third conductive layer has a second opening that overlaps with the first opening, a first insulating layer is in contact with the sidewall of the first opening of the second conductive layer, a semiconductor layer is in contact with the top surface of the first conductive layer, the side surface of the first insulating layer, and the top surface of the third conductive layer, a second insulating layer is provided above the semiconductor layer, a fourth conductive layer is provided above the second insulating layer, the first insulating layer has a region sandwiched between the sidewall of the first opening of the second conductive layer and the semiconductor layer, and the semiconductor layer has a region sandwiched between the sidewall of the first opening of the second conductive layer and the fourth conductive layer.

Description

Semiconductor device and method for manufacturing the same

[0001] 1. Field of the Invention One embodiment of the present invention relates to a semiconductor device, a display device, a display module, and an electronic device. 1. Field of the Invention One embodiment of the present invention relates to a method for manufacturing a semiconductor device and a method for manufacturing a display device.

[0002] One embodiment of the present invention is not limited to the above technical field, and examples of the technical field of one embodiment of the present invention include a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, an electronic device, a lighting device, an input device (for example, a touch sensor), an input / output device (for example, a touch panel), a driving method thereof, or a manufacturing method thereof.

[0003] Semiconductor devices having transistors are widely used in display devices and electronic devices, and there is a demand for higher integration and higher speed of the semiconductor devices. For example, when a semiconductor device is applied to a high-resolution display device, a highly integrated semiconductor device is required. As one means for increasing the integration degree of transistors, the development of fine-sized transistors is underway.

[0004] In recent years, there has been a demand for display devices applicable to virtual reality (VR), augmented reality (AR), substitutional reality (SR), or mixed reality (MR). VR, AR, SR, and MR are collectively referred to as XR (Extended Reality). Display devices for XR are desired to have high resolution and high color reproducibility in order to enhance the sense of realism and immersion. Examples of display devices applicable to such devices include liquid crystal display devices, organic electroluminescence (EL) devices, and light-emitting devices including light-emitting devices (also referred to as light-emitting elements) such as light-emitting diodes (LEDs).

[0005] Patent Document 1 discloses a display device for VR that uses an organic EL device (also called an organic EL element).

[0006] International Publication No. 2018 / 087625

[0007] An object of one embodiment of the present invention is to provide a semiconductor device including a micro-sized transistor and a manufacturing method thereof. Another object of one embodiment of the present invention is to provide a small-sized semiconductor device and a manufacturing method thereof. Another object of one embodiment of the present invention is to provide a semiconductor device including a transistor with high on-state current and a manufacturing method thereof. Another object of one embodiment of the present invention is to provide a semiconductor device with favorable electrical characteristics and a manufacturing method thereof. Another object of one embodiment of the present invention is to provide a highly reliable semiconductor device and a manufacturing method thereof. Another object of one embodiment of the present invention is to provide a manufacturing method of a semiconductor device with high productivity. Another object of one embodiment of the present invention is to provide a novel semiconductor device and a manufacturing method thereof.

[0008] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Note that problems other than these can be extracted from the description of the specification, drawings, claims, etc.

[0009] One embodiment of the present invention includes a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, a first insulating layer, and a second insulating layer, wherein the second conductive layer is provided over the first conductive layer and has a first opening overlapping with the first conductive layer, the third conductive layer is provided over the second conductive layer and has a second opening overlapping with the first opening, and the first insulating layer overlaps with the first opening included in the second conductive layer. the semiconductor layer contacts the sidewall of the first opening, the semiconductor layer contacts the top surface of the first conductive layer, the side surface of the first insulating layer, and the top surface of the third conductive layer, the second insulating layer is provided on the semiconductor layer, and the fourth conductive layer is provided on the second insulating layer, the first insulating layer has a region sandwiched between the sidewall of the first opening in the second conductive layer and the semiconductor layer, and the semiconductor layer has a region sandwiched between the sidewall of the first opening in the second conductive layer and the fourth conductive layer.

[0010] In the above structure, the first insulating layer preferably has a region in contact with a sidewall of the second opening.

[0011] In the above structure, it is preferable that the first conductive layer functions as one of a source and a drain of the transistor, the third conductive layer functions as the other of the source and drain of the transistor, the second conductive layer functions as a first gate of the transistor, and the fourth conductive layer functions as a second gate of the transistor.

[0012] In the above structure, it is preferable that the first conductive layer functions as one of the source and drain of the transistor, the third conductive layer functions as the other of the source and drain of the transistor, the fourth conductive layer functions as a first gate of the transistor, and the second conductive layer is electrically connected to the first conductive layer.

[0013] Alternatively, one embodiment of the present invention includes a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, a first insulating layer, a second insulating layer, a third insulating layer, and a fourth insulating layer, in which the first insulating layer is provided over the first conductive layer, and the first insulating layer has a first opening overlapping with the first conductive layer, the second conductive layer is provided over the first insulating layer, and the second conductive layer has a second opening overlapping with the first opening, the second insulating layer is provided over the second conductive layer, and the second insulating layer has a third opening overlapping with the first opening, and the third conductive layer is provided over the second insulating layer. the third conductive layer has a fourth opening overlapping with the first opening; the third insulating layer is in contact with a sidewall of the first opening, a sidewall of the second opening, and a sidewall of the third opening; the semiconductor layer is in contact with a top surface of the first conductive layer, a side surface of the third insulating layer, and a top surface of the third conductive layer; the fourth insulating layer is provided on the semiconductor layer; the fourth conductive layer is provided on the fourth insulating layer; the third insulating layer has a region sandwiched between the sidewall of the first opening in the first insulating layer and the semiconductor layer; and the semiconductor layer has a region sandwiched between the sidewall of the second opening in the second conductive layer and the fourth conductive layer.

[0014] In the above structure, it is preferable that the first insulating layer has a laminated structure of a first layer and a second layer on the first layer, and that the first layer has an area with a higher film density than the second layer.

[0015] In addition, in the above structure, it is preferable that the second insulating layer has a laminated structure of a third layer and a fourth layer on the third layer, and that the fourth layer has an area with a higher film density than the third layer.

[0016] In the above structure, it is preferable that the third insulating layer has a stacked structure of a fifth layer and a sixth layer, the fifth layer has a region with a higher film density than the sixth layer, the fifth layer is in contact with the sidewall of the first opening, the sidewall of the second opening, and the sidewall of the third opening, and the sixth layer is in contact with the semiconductor layer.

[0017] Alternatively, one embodiment of the present invention includes forming a first conductive film, removing a part of the first conductive film to form a first conductive layer, forming a first insulating film over the first conductive layer, forming a second conductive film over the first insulating film, removing a part of the second conductive film to form a second conductive layer, forming a second insulating film over the second conductive layer, forming a third conductive film over the second insulating film, forming a resist mask over the third conductive film by photolithography, removing a region of the third conductive film that does not overlap with the resist mask by etching to form a first opening, and etching a region of the second insulating film that does not overlap with the resist mask. a resist mask is removed by etching to provide a second opening, a region of the second conductive layer that does not overlap with the resist mask is removed by etching to provide a third opening, a region of the first insulating film that does not overlap with the resist mask is removed by etching to provide a fourth opening to expose a top surface of the first conductive layer, a third insulating film is formed to cover the top surface of the third conductive film, the exposed top surface of the first conductive layer, sidewalls of the first opening, sidewalls of the second opening, sidewalls of the third opening, and sidewalls of the fourth opening, and the third insulating film is processed by anisotropic etching to form a sidewall insulating layer that covers the sidewalls of the third opening.

[0018] In the above structure, the sidewall insulating layer preferably covers the sidewall of the fourth opening and the sidewall of the second opening.

[0019] In the above structure, the sidewall insulating layer preferably covers the sidewall of the fourth opening, the sidewall of the second opening, and the sidewall of the first opening.

[0020] According to one embodiment of the present invention, a semiconductor device including a micro-sized transistor and a manufacturing method thereof can be provided. Alternatively, according to one embodiment of the present invention, a small-sized semiconductor device and a manufacturing method thereof can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device including a transistor with high on-state current and a manufacturing method thereof can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with favorable electrical characteristics and a manufacturing method thereof can be provided. Alternatively, according to one embodiment of the present invention, a highly reliable semiconductor device and a manufacturing method thereof can be provided. Alternatively, according to one embodiment of the present invention, a manufacturing method of a semiconductor device with high productivity can be provided. Alternatively, according to one embodiment of the present invention, a novel semiconductor device and a manufacturing method thereof can be provided.

[0021] Note that the description of these effects does not preclude the existence of other effects. One embodiment of the present invention does not necessarily have all of these effects. Effects other than these can be extracted from the description in the specification, drawings, and claims.

[0022] FIG. 1A is a top view illustrating an example of a transistor. FIG. 1B is a cross-sectional view illustrating an example of a transistor. FIG. 2 is a cross-sectional view illustrating an example of a transistor. FIGS. 3A and 3B are perspective views illustrating an example of a transistor. FIG. 4 is a cross-sectional view illustrating an example of a transistor. FIGS. 5A to 5D are cross-sectional views illustrating an example of a transistor. FIG. 6 is a cross-sectional view illustrating an example of a transistor. FIGS. 7A and 7B are cross-sectional views illustrating an example of a transistor. FIGS. 8A to 8D are cross-sectional views illustrating an example of a method for manufacturing a transistor. FIGS. 9A to 9D are cross-sectional views illustrating an example of a method for manufacturing a transistor. FIGS. 10A to 10C are cross-sectional views illustrating an example of a transistor. FIGS. 11A and 11B are cross-sectional views illustrating an example of a transistor. FIGS. 12A and 12B are cross-sectional views illustrating an example of a transistor. FIGS. 13A to 13D are cross-sectional views illustrating an example of a transistor. FIG. 14 is a perspective view illustrating an example of a display device. FIG. 15 is a cross-sectional view illustrating an example of a display device. FIG. 16 is a cross-sectional view illustrating an example of a display device. FIG. 17 is a cross-sectional view illustrating an example of a display device. FIG. 18 is a cross-sectional view illustrating an example of a display device. FIG. 19 is a cross-sectional view showing an example of a display device. FIGS. 20A to 20F are cross-sectional views showing an example of a manufacturing method of a display device. FIGS. 21A and 21B are diagrams showing a structural example of a display device. FIG. 22 is a diagram showing a structural example of a display device. FIG. 23 is a diagram showing a structural example of a display device. FIG. 24 is a diagram showing a structural example of a display device. FIGS. 25A to 25C are diagrams showing a structural example of a display device. FIG. 26 is a block diagram of a display device. FIGS. 27A to 27D are circuit diagrams of pixel circuits. FIGS. 28A to 28D are circuit diagrams of pixel circuits. FIGS. 29A and 29B are circuit diagrams of pixel circuits. FIGS. 30A to 30G are diagrams showing an example of a pixel. FIGS. 31A to 31K are diagrams showing an example of a pixel. FIGS. 32A to 32D are diagrams showing an example of an electronic device. FIGS. 33A to 33F are diagrams showing an example of an electronic device. FIGS. 34A to 34G are diagrams showing an example of an electronic device.

[0023] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be readily understood by those skilled in the art that various changes can be made in form and detail without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below.

[0024] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations thereof will be omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be assigned.

[0025] For ease of understanding, the position, size, range, etc. of each component shown in the drawings may not represent the actual position, size, range, etc. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings.

[0026] The terms "film" and "layer" can be interchangeable depending on the circumstances. For example, the term "conductive layer" can be changed to the term "conductive film." Or, for example, the term "insulating film" can be changed to the term "insulating layer."

[0027] In this specification, etc., a device fabricated using a metal mask or an FMM (fine metal mask, high-resolution metal mask) may be referred to as a device with an MM (metal mask) structure. Also, in this specification, etc., a device fabricated without using a metal mask or an FMM may be referred to as a device with an MML (metal maskless) structure.

[0028] In this specification and the like, a structure in which at least light-emitting layers are separately formed for light-emitting devices (also referred to as light-emitting elements) with different emission wavelengths may be referred to as an SBS (Side By Side) structure. The SBS structure allows the materials and configuration to be optimized for each light-emitting device, increasing the degree of freedom in selecting materials and configurations and facilitating improvements in brightness and reliability.

[0029] In this specification and the like, holes or electrons may be referred to as "carriers." Specifically, a hole injection layer or an electron injection layer may be referred to as a "carrier injection layer," a hole transport layer or an electron transport layer may be referred to as a "carrier transport layer," and a hole block layer or an electron block layer may be referred to as a "carrier block layer." Note that the above-mentioned carrier injection layer, carrier transport layer, and carrier block layer may not be clearly distinguishable from each other depending on their cross-sectional shapes or characteristics. Furthermore, one layer may have two or three functions among the carrier injection layer, carrier transport layer, and carrier block layer.

[0030] In this specification and the like, a light-emitting device has an EL layer between a pair of electrodes. The EL layer has at least a light-emitting layer. Here, layers (also referred to as functional layers) included in the EL layer include a light-emitting layer, a carrier injection layer (a hole injection layer and an electron injection layer), a carrier transport layer (a hole transport layer and an electron transport layer), and a carrier block layer (a hole block layer and an electron block layer).

[0031] In this specification and the like, a light-receiving device (also referred to as a light-receiving element) has at least an active layer that functions as a photoelectric conversion layer between a pair of electrodes.

[0032] In this specification, the term "island-like" refers to a state in which two or more layers made of the same material and formed in the same process are physically separated. For example, an island-like light-emitting layer refers to a state in which the light-emitting layer is physically separated from an adjacent light-emitting layer.

[0033] In this specification, the term "tapered shape" refers to a shape in which at least a portion of the side of the structure is inclined relative to the substrate surface or the surface to be formed. For example, it is preferable to have a region in which the angle (also referred to as the taper angle) between the inclined side and the substrate surface or the surface to be formed is less than 90 degrees, preferably 45 degrees or more and less than 90 degrees, more preferably 50 degrees or more and less than 90 degrees, even more preferably 55 degrees or more and less than 90 degrees, even more preferably 60 degrees or more and less than 90 degrees, even more preferably 60 degrees or more and less than 85 degrees, even more preferably 65 degrees or more and less than 85 degrees, even more preferably 65 degrees or more and less than 80 degrees, and even more preferably 70 degrees or more and less than 80 degrees. Note that the side of the structure, the substrate surface, and the surface to be formed do not necessarily have to be completely flat, but may be approximately planar with a slight curvature or approximately planar with a slight unevenness.

[0034] In this specification and the like, a mask layer (also referred to as a sacrificial layer) is located above at least the light-emitting layer (more specifically, a layer that is processed into an island shape among the layers that constitute the EL layer), and has the function of protecting the light-emitting layer during the manufacturing process.

[0035] In this specification and the like, the term "step discontinuity" refers to a phenomenon in which a layer, film, or electrode is separated due to the shape of the surface on which it is formed (for example, a step or the like).

[0036] In this specification, the phrase "top surface shapes generally match" means that at least a portion of the contours of stacked layers overlap. For example, this includes cases where the upper and lower layers are processed using the same mask pattern or a portion of the same mask pattern. However, strictly speaking, the contours may not overlap, and the upper layer may be located inside the lower layer, or outside the lower layer. In these cases, the phrase "top surface shapes generally match" also applies.

[0037] Furthermore, in this specification and the like, "approximately the same height" refers to a configuration in which the heights from a reference surface (for example, a flat surface such as the surface of a substrate) are approximately the same in a cross-sectional view. For example, the heights of the processed surfaces when a planarization process (typically a CMP (Chemical Mechanical Polishing) process) is performed are approximately the same. However, even when the planarization process is performed, the heights may not strictly match depending on the film material, etc., but in this specification and the like, this case is also considered to be "approximately the same height."

[0038] Embodiment 1 In this embodiment, a transistor of one embodiment of the present invention and a manufacturing method thereof will be described.

[0039] <Configuration Example 1> [Configuration Example 1-1] A transistor according to one embodiment of the present invention will be described. FIG. 1A shows a top view (also referred to as a plan view) of a transistor 100. FIG. 1B shows a cross-sectional view of the section taken along dashed dotted line A1-A2 in FIG. 1A , and FIG. 2 shows a cross-sectional view of the section taken along dashed dotted line B1-B2 in FIG. 3A shows a perspective view of some components of the transistor 100, and FIG. 3B shows a perspective view of the transistor 100. Note that some components of the transistor 100 (such as an insulating layer) are omitted in FIG. 1A . As with FIG. 1A , some components are omitted in the following top views of the transistor and the like. For clarity, some elements, such as an insulating layer, are omitted in FIG. 3 .

[0040] The transistor 100 is provided over a substrate 102. The transistor 100 includes a conductive layer 104, an insulating layer 106, a semiconductor layer 108, a conductive layer 114, an insulating layer 110s, a conductive layer 112a, and a conductive layer 112b. The conductive layer 104 functions as a gate electrode. The conductive layer 114 functions as a second gate electrode. A part of the insulating layer 106 functions as a gate insulating layer. The insulating layer 110s functions as a second gate insulating layer. The conductive layer 112a functions as one of a source electrode and a drain electrode, and the conductive layer 112b functions as the other. An entire region of the semiconductor layer 108 that overlaps with the gate electrode with the gate insulating layer interposed therebetween functions as a channel formation region. A region of the semiconductor layer 108 that is in contact with the source electrode functions as a source region, and a region of the semiconductor layer 108 that is in contact with the drain electrode functions as a drain region.

[0041] The detailed configuration of the transistor 100 will be described.

[0042] An insulating layer 115 and a conductive layer 112a are provided on a substrate 102, an insulating layer 110a is provided on the conductive layer 112a, a conductive layer 114 is provided on the insulating layer 110a, an insulating layer 110b is provided on the insulating layer 110a and the conductive layer 114, and a conductive layer 112b is provided on the insulating layer 110b. The insulating layer 110a and the insulating layer 110b have a region sandwiched between the conductive layer 112a and the conductive layer 112b. The conductive layer 112a has a region overlapping with the conductive layer 112b with the insulating layer 110a and the insulating layer 110b interposed therebetween.

[0043] 1B and 2, the insulating layer 110a has a laminated structure of an insulating layer 110a1 and an insulating layer 110a2 on the insulating layer 110a1, and the insulating layer 110b has a laminated structure of an insulating layer 110b2 and an insulating layer 110b1 on the insulating layer 110b2.

[0044] 1B and 2 , the conductive layer 114 has a region sandwiched between the insulating layers 110a2 and 110b2. The insulating layer 110a2 has a region in contact with the lower surface of the conductive layer 114. The insulating layer 110b2 is in contact with the upper surface of the conductive layer 114, for example.

[0045] The insulating layer 110a, the conductive layer 114, the insulating layer 110b, and the conductive layer 112b each have an opening. For example, each opening has a region overlapping with the conductive layer 112a.

[0046] An insulating layer 110s is provided on the conductive layer 112a. The insulating layer 110s is provided along the sidewalls of an opening (region not shown in the figure) in the insulating layer 110a, an opening 142 in the conductive layer 114, an opening (region not shown in the figure) in the insulating layer 110b, and an opening 143 in the conductive layer 112b. In Figures 1B and 2, etc., the sidewalls of the openings of the insulating layer 110a, the conductive layer 114, the insulating layer 110b, and the conductive layer 112b form a continuous side surface, and the insulating layer 110s is formed along this continuous side surface. The insulating layer 110s may be called a sidewall, a sidewall insulating layer, a sidewall protective layer, or the like.

[0047] The opening 142 and the opening 143 each have a region overlapping with the conductive layer 112a. The opening 142 and the opening 143 also have a region overlapping with each other.

[0048] The semiconductor layer 108 is provided along a recess (sometimes called a dent) whose bottom is the upper surface of the conductive layer 112a and whose inner wall is the sidewall 141 of the insulating layer 110s.

[0049] The semiconductor layer 108 overlaps with the conductive layer 112a in a region located inside the sidewall 141 of the insulating layer 110s in a plan view. In this region, the semiconductor layer 108 is in contact with, for example, the top surface of the conductive layer 112a.

[0050] The semiconductor layer 108 overlaps with the conductive layer 112b in a region that is on the outer side of the sidewall 141 of the insulating layer 110s in a plan view. In this region, the semiconductor layer 108 is in contact with, for example, the top surface of the conductive layer 112b.

[0051] The transistor 100 can be called a bottom contact transistor because the bottom surface of the semiconductor layer 108 is in contact with a source electrode and a drain electrode.

[0052] The semiconductor layer 108 has a region provided along the top surface of the conductive layer 112a, a region provided along the sidewall 141 of the insulating layer 110s, and a region provided along the top surface of the conductive layer 112b.

[0053] The semiconductor layer 108 has a region facing the sidewall of the opening 142 with the insulating layer 110s sandwiched therebetween. In addition, the semiconductor layer 108 preferably contacts the sidewall 141 of the insulating layer 110s in this region.

[0054] 1B and 2, a plurality of components selected from the five components, i.e., insulating layer 110a1, insulating layer 110a2, insulating layer 110b2, insulating layer 110b1, and insulating layer 110s, may be a continuous layer. For example, a common material may be used for the plurality of components that are a continuous layer. Furthermore, for example, the plurality of components that are a continuous layer may be manufactured in the same process.

[0055] Alternatively, multiple components may be observed as a continuous layer. For example, when a cross section of the transistor 100 is observed with an electron microscope, the insulating layer 110a2 and the insulating layer 110s may be observed as a continuous layer. Also, the insulating layer 110b2 and the insulating layer 110s may be observed as a continuous layer.

[0056] FIG. 4 shows an example of a cross section in which the insulating layer 110a2, the insulating layer 110b2, and the insulating layer 110s are observed as a continuous layer (shown as insulating layer 110_2 in FIG. 4).

[0057] The conductive layer 112a and the conductive layer 112b may each have a stacked structure. In FIG. 1B and other figures, the conductive layer 112a has a stacked structure of a conductive layer 112a_1 and a conductive layer 112a_2 over the conductive layer 112a_1. The conductive layer 112a_1 is embedded in an opening in the insulating layer 115, and the top surfaces of the conductive layer 112a_1 and the insulating layer 115 are planarized. The conductive layer 112a_2 is located over the conductive layer 112a_1 and the insulating layer 115. In FIG. 1B, the height of the top surface of the insulating layer 115 and the height of the top surface of the conductive layer 112a_1 are approximately the same.

[0058] 1B and other figures, by configuring the top surface of the insulating layer 115 to be approximately flush with the top surface of the conductive layer 112a_1, it is possible to reduce the step between the surfaces on which the insulating layer 110a, the insulating layer 110b, and the conductive layer 112b are formed. As a result, the step between the top surface of the conductive layer 112b and the top surface of the insulating layer 110b is reduced. Therefore, in the step of forming the insulating layer 110s (e.g., an etch-back step), it is possible to prevent the insulating layer from remaining on the top surface of the conductive layer 112b and the top surface of the insulating layer 110b, and it is possible to selectively form the insulating layer on the side walls of the openings in the insulating layer 110a, the insulating layer 110b, the conductive layer 114, and the conductive layer 112b.

[0059] 1B and other figures show an example in which the end of the conductive layer 112a_2 is located outside the end of the conductive layer 112a_1, but the end of the conductive layer 112a_2 may be located inside the end of the conductive layer 112a_1. Furthermore, when a plug is provided to connect the conductive layer 112a to an upper conductive layer, the conductive layer 112a_1 may be extended outside the conductive layer 112a_2, and the upper surface of the conductive layer 112a_1 may be in contact with the plug in the extended region. The plug is provided so as to fill openings in the insulating layers 110a, 110b, 195, etc.

[0060] An insulating layer 106 is provided over the semiconductor layer 108. The insulating layer 106 has a region overlapping with the conductive layer 112a with the semiconductor layer 108 therebetween, a region overlapping with the conductive layer 114 with the semiconductor layer 108 and the insulating layer 110s therebetween, and a region overlapping with the conductive layer 112b with the semiconductor layer 108 therebetween.

[0061] 1B and 2, the insulating layer 106 has a region facing the upper surface of the conductive layer 112a with the semiconductor layer 108 sandwiched therebetween, a region facing the side surface of the conductive layer 114 with the semiconductor layer 108 and the insulating layer 110s sandwiched therebetween, and a region facing the upper surface of the conductive layer 112b with the semiconductor layer 108 sandwiched therebetween.

[0062] An insulating layer 195 is provided to cover the conductive layer 112a, the semiconductor layer 108, the conductive layer 112b, the insulating layer 106, and the like included in the transistor 100. The insulating layer 195 functions as a protective layer for the transistor 100.

[0063] The conductive layer 104 is provided over the insulating layer 106. The conductive layer 104 has a region overlapping with the semiconductor layer 108 between the conductive layer 112a and the conductive layer 112b, with the insulating layer 106 sandwiched therebetween. The conductive layer 104 also has a region overlapping with the conductive layer 114, with the insulating layer 106, the semiconductor layer 108, and the insulating layer 110s sandwiched therebetween.

[0064] In a region in the transistor 100 where the conductive layer 104 and the conductive layer 112a are insulated from each other, for example, an insulating layer 106 is provided between the conductive layer 104 and the conductive layer 112a. In a region in the transistor 100 where the conductive layer 104 and the conductive layer 112b are insulated from each other, for example, an insulating layer 106 is provided between the conductive layer 104 and the conductive layer 112b.

[0065] The semiconductor layer 108 is provided along a recess whose bottom is the upper surface of the conductive layer 112a and whose inner wall is the sidewall 141 of the insulating layer 110s, and the upper surface of the semiconductor layer 108 has a recess. The insulating layer 106 is provided on the semiconductor layer 108, and the upper surface of the insulating layer 106 has a recess. In FIG. 1B and other figures, the conductive layer 104 is provided so as to fill the recess. This allows the conductive layer 104 to be thicker and the electrical resistance to be reduced.

[0066] In FIG. 1B and other figures, the conductive layer 104 is provided so as to fill the opening in the insulating layer 195, and the upper surfaces of the conductive layer 104 and the insulating layer 195 are generally flush with each other.

[0067] One of the conductive layer 104 and the conductive layer 114 can function as, for example, a gate, and the other can function as a back gate. The conductive layer 104 and the conductive layer 114 are preferably disposed so as to sandwich a channel formation region of the semiconductor layer 108 therebetween.

[0068] Applying a potential to the back gate can increase the field-effect mobility of the transistor. Furthermore, changing the potential of the back gate can change the threshold voltage of the transistor. The potential of the back gate can be the same as that of the gate. Alternatively, the potential of the back gate may be ground potential or any other potential. Furthermore, the potential of the back gate may be the same as that of the source or drain.

[0069] When the back gate is given the same potential as the gate, the back gate and the gate may be electrically connected to each other to provide electrical continuity. When the back gate is given the same potential as the source or drain, the back gate and the source or drain may be electrically connected to each other to provide electrical continuity. For example, reliability can be improved by electrically connecting the gate or the back gate to the source. Furthermore, for example, reliability can be improved by electrically connecting the gate or the back gate to the drain.

[0070] Note that in the case where the potential of the back gate is set to the ground potential or any arbitrary potential, a common wiring electrically connected to the back gates of a plurality of transistors may be provided, and the potential may be applied to the common wiring.

[0071] By providing a back gate, it may be possible to reduce variations in characteristics among a plurality of transistors, for example, variations in threshold voltage among a plurality of transistors.

[0072] The top surface shapes of the openings 142, 143, and sidewall 141 may each be, for example, circular or elliptical. The top surface shapes of the openings 142, 143, and sidewall 141 may each be polygonal, such as a triangle, a quadrangle (including a rectangle, a rhombus, and a square), or a pentagon, or may be polygonal shapes with rounded corners. As shown in FIG. 1A , the top surface shapes of the openings 142 and 143 are preferably circular. By making the top surface shapes of the openings 142 and 143 circular, the processing accuracy when forming the openings 142 and 143 can be improved, and the openings 142 and 143 can be formed with finer sizes. Note that in this specification, a circle is not limited to a perfect circle.

[0073] Furthermore, the top surface shape of the sidewall 141 of the insulating layer 110s varies depending on the shapes of the openings in the insulating layer 110a, the opening 142 in the conductive layer 114, the opening in the insulating layer 110b, and the opening 143 in the conductive layer 112b. By making each opening circular, the top surface shape of the sidewall 141 can also be circular. By making the top surface shape of the sidewall 141 circular, the coverage of the semiconductor layer 108 provided along the sidewall 141 can be improved. For example, if the top surface of the sidewall 141 has a corner, the thickness of the semiconductor layer 108 and the thickness of the insulating layer 106 formed on the semiconductor layer 108 may be non-uniform in the corner region compared to regions with a linear or circular top surface. There is a concern that electric field concentration may occur between the semiconductor layer 108 and the gate electrode in the region where the thickness is non-uniform. Electric field concentration may cause transistor degradation. Making the top surface shape of the sidewall 141 circular can improve the reliability of the transistor.

[0074] The openings in the insulating layer 110a, the opening 142 in the conductive layer 114, the opening in the insulating layer 110b, and the opening 143 in the conductive layer 112b can be formed, for example, by forming a mask on the surface to be processed and then performing an etching process. A resist mask or a hard mask made of an insulating or conductive layer may be used as the mask. After forming the mask, the opening 143 in the conductive layer 112b, the opening in the insulating layer 110b, the opening 142 in the conductive layer 114, and the opening in the insulating layer 110a are successively formed, and then the mask is removed. This process can also serve as a mask formation process, and the diameters of the openings can be made approximately the same. In this specification, the process of successively forming multiple openings using the same mask may be referred to as simultaneous opening formation.

[0075] After the collective openings are formed, the insulating layer 110s is formed, thereby fabricating the configuration shown in Fig. 1B and Fig. 2. In the above-described opening formation process, the diameters of the openings are made approximately the same, thereby improving the coverage of the insulating layer 110s.

[0076] Note that the opening in the insulating layer 110a, the opening 142 in the conductive layer 114, the opening in the insulating layer 110b, and the opening 143 in the conductive layer 112b do not have to be formed in succession. For example, a mask may be formed when each opening is provided.

[0077] 3A is a perspective view illustrating some of the components of the transistor 100. FIG. 3B is a perspective view illustrating the transistor 100 on a substrate 102. Note that FIG. 3B illustrates the conductive layer 112a, the conductive layer 114, the semiconductor layer 108, the conductive layer 112b, and the conductive layer 104 among the components of the transistor 100, but does not illustrate insulating layers such as the insulating layer 110s and the insulating layer 106. In addition, the conductive layer 104 is indicated by a dashed line to make the other components easier to see.

[0078] The channel length and channel width of the transistor 100 will be described.

[0079] In the semiconductor layer 108, a region in contact with the conductive layer 112a functions as one of a source region and a drain region, a region in contact with the conductive layer 112b functions as the other of the source region and the drain region, and a region between the source region and the drain region functions as a channel formation region.

[0080] The channel length of the transistor 100 is the distance between the source region and the drain region. In Figures 1B and 2, the channel length L100 of the transistor 100 is indicated by a dashed double-headed arrow. In the cross-sectional views shown in Figures 1B and 2, the channel length L100 is the length of the side surface and the top surface of the insulating layer 110s.

[0081] Furthermore, the total thickness T110 (indicated by a dashed-dotted double-headed arrow in FIGS. 1B and 2 ) of the insulating layer 110a, the conductive layer 114, and the insulating layer 110b in a region sandwiched between the top surface of the conductive layer 112a and the bottom surface of the conductive layer 112b may be used as the channel length L100 of the transistor 100. Alternatively, the sum of the thickness T110 and the thickness of the conductive layer 112b may be used as the channel length L100 of the transistor 100.

[0082] Here, the channel length L100 of the transistor 100 is determined by the thickness of the insulating layer 110a, the thickness of the conductive layer 114, the thickness of the insulating layer 110b, the thickness of the insulating layer 110s, the angle θ110 between the sidewall 141 of the insulating layer 110s and the surface on which the insulating layer 110a is to be formed (here, the upper surface of the conductive layer 112a), etc., and is not affected by the performance of the exposure equipment used to fabricate the transistor. Therefore, the channel length L100 can be set to a value smaller than the limit resolution of the exposure equipment, and a transistor with a fine size can be realized.

[0083] The channel length L100 is preferably 500 nm or less, 200 nm or less, 100 nm or less, 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, or 10 nm or less, and is preferably 1 nm or more, or 5 nm or more.

[0084] The thickness T110 is preferably 1 μm or less, 500 nm or less, 200 nm or less, 100 nm or less, 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, or 10 nm or less, and is preferably 1 nm or more, or 5 nm or more.

[0085] The angle between the conductive layer 112a and the surface on which the insulating layer 110s is to be formed is defined as the angle θ110. The angle θ110 is preferably approximately 90 degrees or close to 90 degrees. Specifically, the angle θ110 is, for example, 60 degrees or more and 115 degrees or less, preferably 70 degrees or more and 105 degrees or less, and more preferably 80 degrees or more and 95 degrees or less. By setting the angle θ110 within the above range, the insulating layer 110s can be selectively left on the side surfaces of the insulating layer 110a, the conductive layer 114, and the insulating layer 110b in a process for forming the insulating layer 110s (e.g., an etch-back process, etc.).

[0086] Note that the insulating layer 110s may not extend along the entire sidewall of the opening of the insulating layer 110a, the conductive layer 114, the insulating layer 110b, and the conductive layer 112b; for example, the insulating layer 110s may be provided so as to extend along only a portion of the sidewall of the opening 143 of the conductive layer 112b.

[0087] Fig. 5A is an enlarged view of a region 161 shown in Fig. 1B. Fig. 5A shows a configuration in which the height of the upper surface of the insulating layer 110s is approximately the same as the height of the upper surface of the conductive layer 112b.

[0088] 5B and 5C are examples of configurations that are different from those in FIG. 5A in terms of the height of the upper surface of the insulating layer 110s, etc.

[0089] 5B shows a configuration in which the height of the top surface of the insulating layer 110s is lower than the height of the top surface of the conductive layer 112b and higher than the height of the top surface of the insulating layer 110b1 located below the conductive layer 112b. In the configuration shown in FIG. 5B, for example, the side surface of the conductive layer 112b has a region in contact with the semiconductor layer 108. When the semiconductor layer 108 contacts the side surface of the conductive layer 112b, the contact area between the semiconductor layer 108 and the conductive layer 112b increases, which may reduce resistance.

[0090] 5C also shows a configuration in which the height of the upper surface of insulating layer 110s is lower than the height of the upper surface of insulating layer 110b1. In the configuration shown in FIG. 5C, for example, the side surface of conductive layer 112b has a region in contact with semiconductor layer 108, and the side surface of insulating layer 110b1 has a region in contact with semiconductor layer 108.

[0091] 5D also shows a configuration in which the height of the upper surface of insulating layer 110s is lower than the height of the upper surface of insulating layer 110b2. In the configuration shown in Fig. 5D, for example, the side surface of conductive layer 112b has a region in contact with semiconductor layer 108, the side surface of insulating layer 110b1 has a region in contact with semiconductor layer 108, and the side surface of insulating layer 110b2 has a region in contact with semiconductor layer 108.

[0092] In the etching for forming the insulating layer 110s, the thickness of the insulating layer 110s can be reduced by increasing the etching time. When the etching time is increased, the height of the upper surface of the insulating layer 110s may become lower than that of the conductive layer 112b. It is preferable that the height of the upper surface of the insulating layer 110s is at least higher than that of the conductive layer 114.

[0093] By reducing the channel length L100, the on-state current of the transistor 100 can be increased. By using the transistor 100, a circuit capable of high-speed operation can be manufactured. Furthermore, the area occupied by the circuit can be reduced. Therefore, when the transistor of one embodiment of the present invention is used in a semiconductor device, the device can be miniaturized.

[0094] For example, when the transistor of one embodiment of the present invention is applied to a display device, the frame of the display device can be narrowed.Furthermore, when the transistor of one embodiment of the present invention is applied to a large display device or a high-resolution display device, even if the number of wirings is increased, signal delay in each wiring can be reduced, and display unevenness can be suppressed.

[0095] The channel width of the transistor 100 is the width of the source region or the width of the drain region in a direction perpendicular to the channel length direction. That is, the channel width is the width of the region where the semiconductor layer 108 and the conductive layer 112a contact each other or the width of the region where the semiconductor layer 108 and the conductive layer 112b contact each other in a direction perpendicular to the channel length direction.

[0096] The semiconductor layer 108 is provided along a recess whose bottom is the upper surface of the conductive layer 112a and whose inner wall is the sidewall 141 of the insulating layer 110s. Therefore, the circumferential length of the inner wall of the sidewall 141 of the insulating layer 110s in a plan view may be used as the channel width. The insulating layer 110s can also be expressed as having a shape with an opening at or near the center of a cylinder, for example. The circumferential length of the opening can also be used as the channel width of the semiconductor layer 108.

[0097] Here, the channel width of the transistor 100 is described as the width of a region where the semiconductor layer 108 and the conductive layer 112b are in contact with each other in a direction perpendicular to the channel length direction. In Figures 1A, 1B, and 2, the channel width W100 of the transistor 100 is indicated by a solid double-headed arrow. The channel width W100 is the length of the opening 143 in a top view.

[0098] The channel width W100 is determined by the top surface shape of the opening 143. In FIGS. 1B and 2, the width D143 of the opening 143 is indicated by a two-dot chain line with a double arrow. The width D143 refers to the short side of the smallest rectangle circumscribing the opening 143 when viewed from above. When the opening 143 is formed using photolithography, the width D143 of the opening 143 is equal to or greater than the resolution limit of the exposure device. The width D143 is, for example, equal to or greater than 0.20 μm and less than 5.0 μm. When the top surface shape of the opening 143 is circular, the width D143 corresponds to the diameter of the opening 143, and the channel width W100 can be calculated as "D143 × π".

[0099] [Semiconductor Layer 108] The semiconductor material that can be used for the semiconductor layer 108 is not particularly limited. For example, an elemental semiconductor or a compound semiconductor can be used. As the elemental semiconductor, for example, silicon or germanium can be used. As the compound semiconductor, for example, gallium arsenide and silicon germanium can be used. As the compound semiconductor, an organic substance having semiconductor properties or a metal oxide (also referred to as an oxide semiconductor) having semiconductor properties can be used. Note that these semiconductor materials may contain impurities as dopants.

[0100] The crystallinity of the semiconductor material used for the semiconductor layer 108 is not particularly limited, and any of an amorphous semiconductor and a crystalline semiconductor (a single-crystalline semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, or a semiconductor having a crystalline region in part) may be used. Use of a crystalline semiconductor is preferable because it can suppress deterioration of transistor characteristics.

[0101] Silicon can be used for the semiconductor layer 108. Examples of silicon include single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. Examples of polycrystalline silicon include low temperature polysilicon (LTPS).

[0102] A transistor using amorphous silicon for the semiconductor layer 108 can be formed over a large glass substrate and can be manufactured at low cost. A transistor using polycrystalline silicon for the semiconductor layer 108 has high field-effect mobility and can operate at high speed. A transistor using microcrystalline silicon for the semiconductor layer 108 has higher field-effect mobility and can operate at high speed than a transistor using amorphous silicon.

[0103] The semiconductor layer 108 preferably includes a metal oxide (oxide semiconductor). Examples of metal oxides that can be used for the semiconductor layer 108 include indium oxide, gallium oxide, and zinc oxide. The metal oxide preferably includes at least indium (In) or zinc (Zn). The metal oxide preferably includes two or three elements selected from indium, element M, and zinc. The element M is one or more elements selected from gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, cobalt, and magnesium. In particular, the element M is preferably one or more elements selected from aluminum, gallium, yttrium, and tin. The element M is more preferably gallium.

[0104] The semiconductor layer 108 can be formed using, for example, indium oxide, indium zinc oxide (In—Zn oxide), indium tin oxide (In—Sn oxide), indium titanium oxide (In—Ti oxide), indium aluminum zinc oxide (In—Al—Zn oxide, also referred to as IAZO), indium tin zinc oxide (In—Sn—Zn oxide), indium titanium zinc oxide (In—Ti—Zn oxide), indium gallium zinc oxide (In—Ga—Zn oxide, also referred to as IGZO), indium gallium tin zinc oxide (In—Ga—Sn—Zn oxide, also referred to as IGZTO), indium gallium aluminum zinc oxide (In—Ga—Al—Zn oxide, also referred to as IGAZO or IAGZO), or the like. Alternatively, indium tin oxide containing silicon can be used.

[0105] The metal oxide can be preferably formed by sputtering or atomic layer deposition (ALD). When forming a metal oxide by sputtering, the atomic ratio of the target may differ from the atomic ratio of the metal oxide. In particular, the atomic ratio of zinc in the metal oxide may be smaller than the atomic ratio of the target. Specifically, the atomic ratio of zinc in the metal oxide may be approximately 40% to 90% of the atomic ratio of zinc contained in the target.

[0106] As a specific example of forming the semiconductor layer 108 by an atomic layer deposition (ALD) method, it is preferable to use a film formation method such as a thermal ALD (Atomic Layer Deposition) method or a PEALD (Plasma Enhanced ALD) method. The thermal ALD method is preferable because it exhibits extremely high step coverage. The PEALD method is also preferable because it exhibits high step coverage and allows low-temperature film formation.

[0107] The composition of the metal oxide in the semiconductor layer 108 greatly affects the electrical characteristics and reliability of the transistor 100 .

[0108] For example, by increasing the content of indium in the metal oxide, a transistor with a large on-state current can be realized. Furthermore, by using a metal oxide that does not contain gallium or has a low content of gallium in the semiconductor layer 108, a transistor with high reliability against application of a positive bias can be realized. Furthermore, by using a metal oxide with a low content of element M in the semiconductor layer 108, a transistor with high reliability against application of a positive bias can be realized. Furthermore, by increasing the content of element M in the metal oxide, a transistor with high reliability against light can be realized.

[0109] The composition of the metal oxide contained in the semiconductor layer 108 will be described in detail later.

[0110] It is preferable to use a crystalline metal oxide layer for the semiconductor layer 108. For example, a metal oxide layer having a c-axis aligned crystal (CAAC) structure, a polycrystalline structure, a nanocrystalline (nc) structure, or the like can be used. By using a crystalline metal oxide layer for the semiconductor layer 108, the density of defect states in the semiconductor layer 108 can be reduced, and a highly reliable transistor can be realized.

[0111] The higher the crystallinity of the metal oxide layer used for the semiconductor layer 108, the more the density of defect states in the semiconductor layer 108 can be reduced. On the other hand, by using a metal oxide layer with low crystallinity, a transistor capable of passing a large current can be realized.

[0112] The semiconductor layer 108 may have a stacked structure of two or more metal oxide layers with different crystallinity. For example, the semiconductor layer 108 may have a stacked structure of a first metal oxide layer and a second metal oxide layer provided on the first metal oxide layer, where the second metal oxide layer has a region with higher crystallinity than the first metal oxide layer. Alternatively, the second metal oxide layer may have a region with lower crystallinity than the first metal oxide layer. The two or more metal oxide layers included in the semiconductor layer 108 may have the same or approximately the same composition. By using a stacked structure of metal oxide layers with the same composition, for example, the same sputtering target can be used to form the layers, thereby reducing manufacturing costs. For example, by using the same sputtering target and varying the oxygen flow rate, a stacked structure of two or more metal oxide layers with different crystallinity can be formed. Note that the two or more metal oxide layers included in the semiconductor layer 108 may have different compositions.

[0113] The thickness of the semiconductor layer 108 is preferably 3 nm to 100 nm, more preferably 5 nm to 100 nm, even more preferably 10 nm to 100 nm, even more preferably 10 nm to 70 nm, even more preferably 15 nm to 70 nm, even more preferably 15 nm to 50 nm, even more preferably 20 nm to 50 nm, even more preferably 20 nm to 40 nm, and even more preferably 25 nm to 40 nm.

[0114] Here, oxygen vacancies that can be formed in the semiconductor layer 108 will be described.

[0115] When an oxide semiconductor is used for the semiconductor layer 108, hydrogen contained in the oxide semiconductor reacts with oxygen that is bonded to a metal atom to form water, and oxygen vacancies (V Ｏ In addition, defects in which hydrogen enters oxygen vacancies (hereinafter referred to as V Ｏ Hydrogen atoms (H) may function as donors and generate electrons as carriers. Furthermore, some of the hydrogen atoms may bond with oxygen atoms that are bonded to metal atoms to generate electrons as carriers. Therefore, a transistor using an oxide semiconductor containing a large amount of hydrogen is likely to have normally-on characteristics. Furthermore, hydrogen in an oxide semiconductor is easily moved by stresses such as heat and an electric field. Therefore, if an oxide semiconductor contains a large amount of hydrogen, the reliability of the transistor may be reduced.

[0116] V Ｏ H can function as a donor in an oxide semiconductor. However, it is difficult to quantitatively evaluate such defects. Therefore, in an oxide semiconductor, evaluation is sometimes performed using the carrier concentration rather than the donor concentration. Therefore, in this specification and the like, the carrier concentration assuming a state in which no electric field is applied may be used as a parameter of the oxide semiconductor, rather than the donor concentration. In other words, the "carrier concentration" described in this specification and the like may be rephrased as the "donor concentration."

[0117] From the above, when an oxide semiconductor is used for the semiconductor layer 108, V in the semiconductor layer 108 Ｏ It is preferable to reduce H as much as possible to obtain high-purity intrinsic or substantially high-purity intrinsic. Ｏ To obtain an oxide semiconductor in which H is sufficiently reduced, impurities such as water and hydrogen are removed from the oxide semiconductor (this may be referred to as dehydration or dehydrogenation treatment), and oxygen vacancies (V Ｏ It is important to repair the ＯBy using an oxide semiconductor in which impurities such as H are sufficiently reduced for a channel formation region of a transistor, stable electrical characteristics can be obtained. Ｏ ) is sometimes referred to as oxygenation treatment.

[0118] In the case where an oxide semiconductor is used for the semiconductor layer 108, the carrier concentration of the oxide semiconductor in a region functioning as a channel formation region is 1×10 １８ cm −３ Preferably, it is 1×10 or less. １７ cm −３ More preferably, it is less than 1×10 １６ cm −３ More preferably, it is less than 1×10 １３ cm −３ More preferably, it is less than 1×10 １２ cm −３ The lower limit of the carrier concentration of the oxide semiconductor in the region functioning as a channel formation region is not particularly limited, but is preferably, for example, 1×10 −９ cm −３ It can be said that:

[0119] A transistor using an oxide semiconductor (hereinafter referred to as an OS transistor) has significantly higher field-effect mobility than a transistor using amorphous silicon. Furthermore, an OS transistor has significantly lower source-drain leakage current in an off state (hereinafter also referred to as an off-state current) and can hold charge accumulated in a capacitor connected in series with the transistor for a long period of time. Furthermore, the use of an OS transistor in a semiconductor device can reduce the power consumption of the semiconductor device.

[0120] OS transistors can be applied to display devices. To increase the light-emitting luminance of a light-emitting device included in a pixel circuit of a display device, it is necessary to increase the amount of current flowing through the light-emitting device. To achieve this, it is necessary to increase the source-drain voltage of a driving transistor included in the pixel circuit. Since OS transistors have a higher source-drain breakdown voltage than transistors using silicon (hereinafter referred to as Si transistors), a high voltage can be applied between the source and drain of the OS transistor. Therefore, by using an OS transistor as a driving transistor in a pixel circuit, it is possible to increase the amount of current flowing through the light-emitting device and increase the light-emitting luminance of the light-emitting device.

[0121] When a transistor operates in the saturation region, an OS transistor can reduce the change in source-drain current with respect to a change in gate-source voltage compared to a Si transistor. Therefore, by using an OS transistor as a driving transistor included in a pixel circuit, the current flowing between the source and drain can be precisely determined by changing the gate-source voltage, and the amount of current flowing through the light-emitting device can be precisely controlled. This allows for a greater number of gray levels to be displayed in the pixel circuit.

[0122] In terms of saturation characteristics of the current that flows when a transistor operates in a saturation region, an OS transistor can pass a more stable current (saturation current) than a Si transistor, even when the source-drain voltage gradually increases. Therefore, by using an OS transistor as a driving transistor, a stable current can be passed through a light-emitting device, even when the current-voltage characteristics of the light-emitting device vary. In other words, when an OS transistor operates in a saturation region, the source-drain current of the OS transistor remains almost unchanged even when the source-drain voltage increases, thereby stabilizing the light-emitting luminance of the light-emitting device.

[0123] As described above, by using an OS transistor for a driving transistor included in a pixel circuit, it is possible to achieve "suppression of black floating," "increase in light emission luminance," "multiple gradations," "suppression of variations in light-emitting devices," and the like.

[0124] OS transistors exhibit little change in electrical characteristics due to radiation exposure, i.e., have high radiation resistance, and therefore can be suitably used in environments where radiation may be incident. It can also be said that OS transistors have high reliability against radiation. For example, OS transistors can be suitably used in pixel circuits of X-ray flat panel detectors. Furthermore, OS transistors can be suitably used in semiconductor devices used in outer space. Examples of radiation include electromagnetic radiation (e.g., X-rays and gamma rays) and particle radiation (e.g., alpha rays, beta rays, neutron rays, and proton rays).

[0125] In the transistor of one embodiment of the present invention, and in a semiconductor device, a display device, or the like to which the transistor of one embodiment of the present invention is applied, an inorganic insulating material or an organic insulating material can be used for the insulating layer. Alternatively, the insulating layer may have a stacked structure of an inorganic insulating material and an organic insulating material.

[0126] As the inorganic insulating material, one or more of an oxide, an oxynitride, a nitride oxide, and a nitride can be used.

[0127] In this specification and the like, an oxynitride refers to a material whose composition contains more oxygen than nitrogen. A nitride oxide refers to a material whose composition contains more nitrogen than oxygen. For example, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, and silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0128] The oxygen and nitrogen contents can be analyzed using, for example, secondary ion mass spectrometry (SIMS) or X-ray photoelectron spectrometry (XPS). XPS is suitable when the content of the target element is high (e.g., 0.5 atomic% or more, or 1 atomic% or more). On the other hand, SIMS is suitable when the content of the target element is low (e.g., 0.5 atomic% or less, or 1 atomic% or less). When comparing the element contents, it is more preferable to perform a combined analysis using both SIMS and XPS analytical techniques.

[0129] Furthermore, the film density of an insulating layer or the like can be evaluated using, for example, Rutherford Backscattering Spectrometry (RBS) or X-ray Reflection (XRR). Differences in film density can sometimes be evaluated using cross-sectional transmission electron microscopy (TEM) images. In TEM observation, a high film density results in a dense (dark) transmission electron (TE) image, whereas a low film density results in a pale (bright) transmission electron (TE) image. Even when the same material is used for the insulating layer, if the film densities are different, the boundary between these layers can sometimes be observed as a difference in contrast in a cross-sectional TEM image.

[0130] The nitrogen content of the insulating layer can be confirmed, for example, by EDX. For example, when silicon nitride, silicon oxynitride, or the like is used for the insulating layer, the nitrogen content can be evaluated using the ratio of the nitrogen peak height to the silicon peak height. In EDX, the peak of a certain element refers to the point at which the count of the element reaches a maximum value in a spectrum where the horizontal axis shows the energy of characteristic X-rays and the vertical axis shows the count number (detection value) of characteristic X-rays. Alternatively, the count number at the energy of characteristic X-rays specific to the element can be used to confirm the difference in nitrogen content by the ratio of the count number of nitrogen to the count number of silicon. For example, the count number at 1.739 keV (Si-Kα) can be used for silicon, and the count number at 0.392 keV (N-Kα) can be used for nitrogen.

[0131] The hydrogen concentration of the insulating layer can be evaluated by, for example, secondary ion mass spectrometry (SIMS).

[0132] By using an insulating layer that releases oxygen as an insulating layer in contact with the semiconductor layer 108 or an insulating layer located around the semiconductor layer 108, oxygen can be supplied from the insulating layer to the semiconductor layer 108. By supplying oxygen to the channel formation region of the semiconductor layer 108, oxygen vacancies (V Ｏ ) and V Ｏ The amount of H can be reduced, and a highly reliable transistor can be obtained, which has favorable electrical characteristics. Note that other treatments for supplying oxygen to the semiconductor layer 108 include heat treatment in an atmosphere containing oxygen, plasma treatment in an atmosphere containing oxygen, and the like.

[0133] When hydrogen diffuses into the semiconductor layer 108, it reacts with oxygen atoms contained in the oxide semiconductor to form water, and oxygen vacancies (V Ｏ ) may be formed. Ｏ By using a blocking film that suppresses hydrogen diffusion as an insulating layer in contact with the semiconductor layer 108 or an insulating layer located around the semiconductor layer 108, oxygen vacancies (V Ｏ ) and V ＯH can be reduced, and a highly reliable transistor can be obtained that exhibits favorable electrical characteristics.

[0134] Oxygen vacancies (V Ｏ ) and V Ｏ In particular, when the channel length L100 is short, oxygen vacancies (V Ｏ ) and V Ｏ For example, if VH is introduced from the source or drain region to the channel forming region, the influence of VH on the electrical characteristics and reliability will increase. Ｏ The diffusion of H increases the carrier concentration in the channel formation region, which may cause a change in the threshold voltage of the transistor 100 or a decrease in reliability. Ｏ The influence of the diffusion of H on the electrical characteristics and reliability becomes greater as the channel length L100 of the transistor 100 becomes shorter. Ｏ ) and V Ｏ By reducing H, it is possible to realize a transistor with a short channel length having good electrical characteristics and high reliability.

[0135] It is preferable that an insulating layer in contact with the semiconductor layer 108 or an insulating layer located around the semiconductor layer 108 releases little impurities (for example, water and hydrogen) from itself. By reducing the release of impurities, the diffusion of impurities into the semiconductor layer 108 is suppressed, and a highly reliable transistor can be obtained that exhibits favorable electrical characteristics.

[0136] Oxygen may be desorbed from the semiconductor layer 108 due to heat applied in a process after the formation of the semiconductor layer 108. However, oxygen may be supplied to the semiconductor layer 108 from an insulating layer in contact with the semiconductor layer 108 or an insulating layer located around the semiconductor layer 108, causing oxygen deficiency (V Ｏ ) and V ＯAn increase in H can be suppressed. Furthermore, the degree of freedom in the process temperature can be increased in the steps after the formation of the semiconductor layer 108. Specifically, the process temperature can be increased in the steps after the formation of the semiconductor layer 108. Therefore, the transistor 100 exhibiting favorable electrical characteristics and high reliability can be formed.

[0137] [Insulating Layer 110a, Insulating Layer 110b] The insulating layer 110a and the insulating layer 110b can be formed using an inorganic insulating material or an organic insulating material. The insulating layer 110a and the insulating layer 110b may have a stacked structure of an inorganic insulating material and an organic insulating material.

[0138] An inorganic insulating material can be suitably used for the insulating layer 110a and the insulating layer 110b. Examples of the inorganic insulating material that can be used include one or more of oxide, oxynitride, nitride oxide, and nitride. Examples of the insulating layer 110a and the insulating layer 110b include one or more of silicon oxide, silicon oxynitride, aluminum oxide, hafnium oxide, yttrium oxide, zirconium oxide, gallium oxide, tantalum oxide, magnesium oxide, lanthanum oxide, cerium oxide, neodymium oxide, silicon nitride, silicon nitride oxide, and aluminum nitride.

[0139] The insulating layer 110a and the insulating layer 110b may have a stacked structure of two or more layers. In FIG. 1B and other figures, the insulating layer 110a has a stacked structure of an insulating layer 110a1 and an insulating layer 110a2 on the insulating layer 110a1, and the insulating layer 110b has a stacked structure of an insulating layer 110b2 and an insulating layer 110b1 on the insulating layer 110b2. The insulating layers 110a1, 110a2, 110b2, and 110b1 may each be made of the same materials as those used for the insulating layers 110a and 110b. The insulating layers 110a1, 110a2, 110b2, and 110b1 may be made of the same material or different materials.

[0140] It is preferable that the insulating layer 110a1, the insulating layer 110a2, the insulating layer 110b2, and the insulating layer 110b1 each release little impurities (for example, water and hydrogen) from themselves.

[0141] The insulating layer 110a2 may be thicker than the insulating layer 110a1. The insulating layer 110b2 may be thicker than the insulating layer 110b1. The deposition rate of the insulating layer 110a2 is preferably fast. By increasing the deposition rate of a thick film, productivity can be improved.

[0142] The insulating layer 110a1 and the insulating layer 110b1 function as blocking films that suppress gas desorption from the insulating layer 110a2 and the insulating layer 110b1, respectively. The insulating layer 110a1 and the insulating layer 110b1 are preferably made of a material that does not easily diffuse gas. The insulating layer 110a1 preferably has a region with a higher film density than the insulating layer 110a2. The insulating layer 110b1 preferably has a region with a higher film density than the insulating layer 110b2. Increasing the film density of the insulating layer can improve the blocking property. Slowing the film formation rate of the insulating layer increases the film density, thereby improving the blocking property.

[0143] The insulating layers 110a2 and 110b2 are preferably formed using an oxide or an oxynitride. The insulating layers 110a2 and 110b2 are preferably formed using a film that releases oxygen when heated. The insulating layers 110a2 and 110b2 can be preferably formed using, for example, silicon oxide or silicon oxynitride.

[0144] When the insulating layers 110a2 and 110b2 release oxygen, oxygen can be supplied from the insulating layers 110a2 and 110b2 to the semiconductor layer 108. The insulating layers 110a2 and 110b2 preferably have a high oxygen diffusion coefficient. By increasing the oxygen diffusion coefficient, oxygen can be easily diffused in the insulating layer 110b, and oxygen can be efficiently supplied to the semiconductor layer 108.

[0145] The insulating layer 110a1, the insulating layer 110a2, the insulating layer 110b1, and the insulating layer 110b2 are preferably formed by a film formation method such as a sputtering method, an ALD method, or a plasma CVD method.

[0146] In particular, by forming a film by a sputtering method without using hydrogen gas as a film formation gas, a film with an extremely low hydrogen content can be obtained. Therefore, supply of hydrogen to the semiconductor layer 108 can be suppressed, and the electrical characteristics of the transistor 100 can be stabilized. When forming a silicon oxide film by a sputtering method, for example, the film can be formed using a silicon target in an atmosphere containing an oxidizing gas. When forming a silicon nitride film by a sputtering method, for example, the film can be formed using a silicon target in an atmosphere containing nitrogen gas. When forming an aluminum oxide film by a sputtering method, for example, the film can be formed using an aluminum target in an atmosphere containing an oxidizing gas.

[0147] Silicon oxide and silicon nitride can be deposited by, for example, the PEALD method. Aluminum oxide and hafnium oxide can be deposited by, for example, the thermal ALD method. By depositing an insulating layer by the PEALD method or the thermal ALD method, a dense insulating layer can be formed, thereby improving the blocking property against oxygen and hydrogen.

[0148] The insulating layer 110a1 can be made of a material having a higher nitrogen content than the insulating layer 110a2. The insulating layer 110b1 can be made of a material having a higher nitrogen content than the insulating layer 110b2. Increasing the nitrogen content of the insulating layer can improve blocking properties.

[0149] The insulating layer 110a1 may have a region in which the hydrogen concentration is lower than that of the insulating layer 110a2. The insulating layer 110b1 may have a region in which the hydrogen concentration is lower than that of the insulating layer 110b2.

[0150] The insulating layers 110a1 and 110b1 are preferably impermeable to oxygen. The insulating layers 110a1 and 110b1 function as blocking films that suppress oxygen from being released from the insulating layers 110a2 and 110b2. Furthermore, the insulating layers 110a1 and 110b1 are preferably impermeable to hydrogen. The insulating layers 110a1 and 110b1 function as blocking films that suppress hydrogen from diffusing from the outside of the transistor to the semiconductor layer 108 through the insulating layers 110a1 and 110b1. The insulating layers 110a1 and 110b1 preferably have high film density. Increasing the film density can improve the blocking properties of oxygen and hydrogen. When silicon oxide or silicon oxynitride is used for the insulating layers 110a2 and 110b2, silicon nitride or silicon nitride oxide can be used for the insulating layers 110a1 and 110b1. Furthermore, hafnium oxide or aluminum oxide can be suitably used for the insulating layer 110a1 and the insulating layer 110b1.

[0151] Furthermore, each of the insulating layer 110a1 and the insulating layer 110b1 can have a stacked structure of two or more materials selected from silicon nitride, silicon nitride oxide, hafnium oxide, and aluminum oxide.

[0152] When oxygen contained in the insulating layer 110b2 diffuses upward from a region of the insulating layer 110b2 that is not in contact with the semiconductor layer 108 (for example, the upper surface of the insulating layer 110b2), the amount of oxygen supplied from the insulating layer 110b2 to the semiconductor layer 108 may decrease. By providing the insulating layer 110b1 on the insulating layer 110b2, it is possible to prevent the oxygen contained in the insulating layer 110b2 from diffusing from a region of the insulating layer 110b2 that is not in contact with the semiconductor layer 108. Similarly, by providing the insulating layer 110a1 below the insulating layer 110a2, it is possible to prevent the oxygen from diffusing downward from a region of the insulating layer 110a2 that is not in contact with the semiconductor layer 108. Therefore, the amount of oxygen supplied from the insulating layer 110a2 to the semiconductor layer 108 increases, and oxygen vacancies (V Ｏ ) and V Ｏ H can be reduced.

[0153] Oxygen contained in the insulating layer 110a2 may oxidize the conductive layer 112a and the conductive layer 112b, resulting in an increase in resistance. Oxidation of the conductive layer 112a and the conductive layer 112b may reduce the amount of oxygen supplied from the insulating layer 110a2 to the semiconductor layer 108. By providing the insulating layer 110a1 between the insulating layer 110a2 and the conductive layer 112a, it is possible to prevent the conductive layer 112a from being oxidized and the resistance from increasing. Similarly, by providing the insulating layer 110b1 between the insulating layer 110b2 and the conductive layer 112b, it is possible to prevent the conductive layer 112b from being oxidized and the resistance from increasing. At the same time, the amount of oxygen supplied from the insulating layer 110b2 to the semiconductor layer 108 increases, reducing oxygen vacancies (V Ｏ ) and V Ｏ H can be reduced.

[0154] Furthermore, by providing the insulating layer 110a1 and the insulating layer 110b1, the diffusion of hydrogen into the semiconductor layer 108 is suppressed, and oxygen vacancies (V Ｏ ) and V Ｏ H can be reduced.

[0155] The insulating layer 110a1 and the insulating layer 110b1 each preferably have a thickness that allows them to function as a blocking film for oxygen and hydrogen. If the insulating layer 110a1 and the insulating layer 110b1 are too thin, their function as a blocking film may be reduced. On the other hand, if the insulating layer 110a1 and the insulating layer 110b1 are too thick, the region of the semiconductor layer 108 in contact with the insulating layer 110a2 and the insulating layer 110b2 may be narrowed, and the amount of oxygen supplied to the semiconductor layer 108 may be reduced. The thickness of the insulating layer 110a1 and the insulating layer 110b1 is preferably 1 nm or more, 2 nm or more, and more preferably 200 nm or less, 100 nm or less, 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, 10 nm or less, or 5 nm or less.

[0156] [Insulating Layer 106 and Insulating Layer 110s] The insulating layer 106 and the insulating layer 110s, which function as gate insulating layers, preferably have a low defect density. The low defect density of the insulating layer 106 and the insulating layer 110s enables a transistor to exhibit favorable electrical characteristics. Furthermore, the insulating layer 106 preferably has a high withstand voltage. The high withstand voltage of the insulating layer 106 and the insulating layer 110s enables a highly reliable transistor.

[0157] The insulating layer 106 and the insulating layer 110s can each use, for example, one or more of an oxide, an oxynitride, a nitride oxide, and a nitride having insulating properties. The insulating layer 106 and the insulating layer 110s can each use one or more of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, and Ga—Zn oxide. The insulating layer 106 and the insulating layer 110s can each be a single layer or a stacked layer. The insulating layer 106 and the insulating layer 110s can each have, for example, a stacked structure of an oxide and a nitride.

[0158] In a miniaturized transistor, if the thickness of the gate insulating layer becomes thin, leakage current may increase. By using a material with a high relative dielectric constant (also called a high-k material) for the gate insulating layer, it is possible to reduce the voltage during transistor operation while maintaining the physical film thickness. Examples of high-k materials include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0159] The insulating layer 106 and the insulating layer 110s preferably release little impurities (for example, water and hydrogen) from themselves. When the insulating layer 106 and the insulating layer 110s release little impurities, the impurities are prevented from diffusing into the semiconductor layer 108, and the transistor can have good electrical characteristics and high reliability.

[0160] The insulating layer 106 and the insulating layer 110s are preferably formed under conditions that cause little damage to the semiconductor layer 108 because they are formed over the semiconductor layer 108. For example, they can be formed under conditions that cause a sufficiently slow film formation rate. For example, when the insulating layer 106 is formed by a plasma CVD method, damage to the semiconductor layer 108 can be reduced by forming the insulating layer 106 under low power conditions.

[0161] Here, the insulating layer 106 and the insulating layer 110s will be specifically described using an example in which the semiconductor layer 108 is made of a metal oxide.

[0162] In order to improve the interface characteristics with the semiconductor layer 108, it is preferable to use an oxide for at least the insulating layer 106 and the insulating layer 110s on the side in contact with the semiconductor layer 108. For the insulating layer 106 and the insulating layer 110s, for example, one or more of silicon oxide and silicon oxynitride can be suitably used. It is more preferable to use a film that releases oxygen by heating for the insulating layer 106.

[0163] Note that the insulating layer 106 and the insulating layer 110s may have a stacked structure. The insulating layer 106 and the insulating layer 110s can have a stacked structure of an oxide film on the side in contact with the semiconductor layer 108 and a nitride film on the side in contact with the conductive layer 104. For example, one or more of silicon oxide and silicon oxynitride can be preferably used as the oxide film. For example, silicon nitride can be preferably used as the nitride film.

[0164] The thickness of the insulating layer 106 and the insulating layer 110s is preferably 1 nm to 20 nm, more preferably 0.5 nm to 15 nm, and even more preferably 0.5 nm to 10 nm. The insulating layer 106 and the insulating layer 110s may have a region with the above thickness in at least a portion thereof.

[0165] The insulating layers 106 and 110s preferably have a function of supplying oxygen.

[0166] [Conductive Layer 112a, Conductive Layer 112b] The conductive layer 112a and the conductive layer 112b, which function as a source electrode and a drain electrode, can be formed using one or more of chromium, copper, aluminum, gold, silver, zinc, tantalum, titanium, tungsten, manganese, nickel, iron, cobalt, molybdenum, and niobium, or an alloy containing one or more of the above metals. The conductive layer 112a and the conductive layer 112b can be formed using a low-resistance conductive material containing one or more of copper, silver, gold, and aluminum. Copper and aluminum are particularly preferred because of their excellent mass productivity.

[0167] The conductive layer 112a and the conductive layer 112b can each be a metal oxide film (also referred to as an oxide conductor). Examples of the oxide conductor (OC) include In—Sn oxide (ITO), In—W oxide, In—W—Zn oxide, In—Ti oxide, In—Ti—Sn oxide, In—Zn oxide, In—Sn—Si oxide (ITSO), and In—Ga—Zn oxide.

[0168] Here, oxide conductors (OC) will be explained. For example, when oxygen vacancies are formed in a metal oxide having semiconductor properties and hydrogen is added to the oxygen vacancies, a donor level is formed near the conduction band. As a result, the metal oxide becomes more conductive and becomes an electric conductor. A metal oxide that has become an electric conductor can be called an oxide conductor.

[0169] The conductive layers 112a and 112b may each have a stacked-layer structure of a conductive film containing the oxide conductor (metal oxide) and a conductive film containing a metal or an alloy. By using a conductive film containing a metal or an alloy, wiring resistance can be reduced.

[0170] The conductive layer 112 a and the conductive layer 112 b may each be a Cu—X alloy film (X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti). By using a Cu—X alloy film, they can be processed by a wet etching process, which makes it possible to reduce manufacturing costs.

[0171] Note that the conductive layers 112a and 112b may be formed using the same material or different materials.

[0172] Here, the conductive layers 112a and 112b will be specifically described using an example in which the semiconductor layer 108 is formed using a metal oxide.

[0173] When an oxide semiconductor is used for the semiconductor layer 108, the conductive layers 112a and 112b are oxidized by oxygen contained in the semiconductor layer 108, which may increase the resistance. The conductive layers 112a and 112b are oxidized by oxygen contained in the insulating layer 110b, which may increase the resistance. Furthermore, the conductive layers 112a and 112b are oxidized by oxygen contained in the semiconductor layer 108, which may increase the oxygen vacancy (V Ｏ When the conductive layers 112a and 112b are oxidized by oxygen contained in the insulating layer 110b, the amount of oxygen supplied from the insulating layer 110b to the semiconductor layer 108 may decrease.

[0174] The conductive layer 112a and the conductive layer 112b are preferably made of a material that is resistant to oxidation. The conductive layer 112a and the conductive layer 112b are preferably made of an oxide conductor. For example, In—Sn oxide (ITO) or In—Sn—Si oxide (ITSO) can be suitably used. The conductive layer 112a and the conductive layer 112b may each be made of a nitride conductor. Examples of nitride conductors include tantalum nitride and titanium nitride. The conductive layer 112a and the conductive layer 112b may each have a stacked structure of the above-mentioned materials.

[0175] By using a material that is difficult to oxidize for the conductive layer 112a and the conductive layer 112b, it is possible to prevent the conductive layer 112a and the conductive layer 112b from being oxidized by oxygen contained in the semiconductor layer 108 or oxygen contained in the insulating layer 110b, which can prevent the resistance from increasing. Ｏ ) can be suppressed, and the amount of oxygen supplied from the insulating layer 110b to the semiconductor layer 108 can be increased.

[0176] As described above, the conductive layer 112a and the conductive layer 112b in contact with the semiconductor layer 108 are preferably made of a material that is resistant to oxidation. However, when a material that is resistant to oxidation is used, the resistance may become high. Since the conductive layer 112a and the conductive layer 112b function as wirings, it is preferable that the resistance be low. Therefore, by using a material that is resistant to oxidation for the conductive layer 112a_2 having a region in contact with the semiconductor layer 108 and using a material with low resistance for the conductive layer 112a_1 not having a region in contact with the semiconductor layer 108, the resistance of the conductive layer 112a can be reduced. Furthermore, oxygen vacancies (V Ｏ ) and V Ｏ H can be reduced.

[0177] As described above, when the channel length L100 is short, oxygen vacancies (V Ｏ ) and V Ｏ By using a material that is not easily oxidized for the conductive layer 112a_2, oxygen vacancies (V Ｏ ) and V ＯIt is possible to suppress an increase in H. Therefore, a transistor having a short channel length, good electrical characteristics, and high reliability can be realized.

[0178] The conductive layer 112a_2 can preferably be made of one or more of an oxide conductor and a nitride conductor. The conductive layer 112a_1 is preferably made of a material having lower resistance than the conductive layer 112a_2. The conductive layer 112a_1 can preferably be made of, for example, one or more of copper, aluminum, titanium, tungsten, and molybdenum, or an alloy containing one or more of the above metals. Specifically, In—Sn—Si oxide (ITSO) can be preferably used for the conductive layer 112a_2, and tungsten can be preferably used for the conductive layer 112a_1.

[0179] Note that the structure of the conductive layer 112a may be determined depending on the wiring resistance required for the conductive layer 112a. For example, when the length of the wiring (conductive layer 112a) is short and the required wiring resistance is relatively high, the conductive layer 112a may have a single-layer structure and may be made of a material that is not easily oxidized. On the other hand, when the length of the wiring (conductive layer 112a) is long and the required wiring resistance is relatively low, it is preferable to use a stacked structure of a material that is not easily oxidized and a material with low resistance for the conductive layer 112a.

[0180] [Conductive Layer 104, Conductive Layer 114] The conductive layer 104 and the conductive layer 114 can be formed using, for example, one or more of chromium, copper, aluminum, gold, silver, zinc, molybdenum, tantalum, titanium, tungsten, manganese, nickel, iron, cobalt, and niobium, or an alloy containing one or more of the above-mentioned metals. Furthermore, the conductive layer 104 and the conductive layer 114 may be formed using the nitrides and oxides that can be used for the conductive layers 112a and 112b.

[0181] 6, the conductive layer 104 may have a two-layer structure of a conductive layer 104a and a conductive layer 104b over the conductive layer 104a. For example, a nitride or an oxide can be used as the conductive layer 104a, and one or more of chromium, copper, aluminum, gold, silver, zinc, molybdenum, tantalum, titanium, tungsten, manganese, nickel, iron, cobalt, and niobium, or an alloy containing one or more of the above metals can be used as the conductive layer 104b.

[0182] [Insulating Layer 195] The insulating layer 195, which functions as a protective layer for the transistor 100, is preferably made of a material that does not easily diffuse impurities. Providing the insulating layer 195 can effectively prevent external impurities from diffusing into the transistor, thereby improving the reliability of the transistor. Examples of impurities include water and hydrogen. The insulating layer 195 can be an insulating layer containing an inorganic material or an insulating layer containing an organic material. For example, an inorganic material such as an oxide or a nitride can be suitably used for the insulating layer 195. More specifically, one or more of silicon nitride, silicon nitride oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, aluminum nitride, hafnium oxide, and hafnium aluminate can be used. For example, one or more of an acrylic resin and a polyimide resin can be used as the organic material. A photosensitive material may be used as the organic material. Two or more of the above insulating layers may be stacked. The insulating layer 195 may have a stacked structure of an insulating layer containing an inorganic material and an insulating layer containing an organic material.

[0183] [Insulating Layer 115] An inorganic insulating material or an organic insulating material can be used for the insulating layer 115. The insulating layer 115 may have a stacked structure of an inorganic insulating material and an organic insulating material.

[0184] For the insulating layer 115, the materials and structures exemplified for the insulating layer 110a1, the insulating layer 110a2, the insulating layer 195, and the like can be suitably used.

[0185] [Substrate 102] There are no significant limitations on the material of the substrate 102, but it must have at least heat resistance sufficient to withstand subsequent heat treatment. For example, a single crystal semiconductor substrate made of silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, an SOI substrate, a glass substrate, a quartz substrate, a sapphire substrate, a ceramic substrate, or an organic resin substrate may be used as the substrate 102. Furthermore, any of these substrates on which semiconductor elements are provided may also be used as the substrate 102. The shape of the semiconductor substrate and the insulating substrate may be circular or rectangular.

[0186] A flexible substrate may be used as the substrate 102, and the transistor 100 and the like may be formed directly on the flexible substrate. Alternatively, a peeling layer may be provided between the substrate 102 and the transistor 100 and the like. The peeling layer can be used to separate a semiconductor device, after a part or all of the semiconductor device is completed thereon, from the substrate 102 and transfer the semiconductor device to another substrate. In this case, the transistor 100 and the like can also be transferred to a substrate with poor heat resistance or a flexible substrate.

[0187] [Composition of Metal Oxide in Semiconductor Layer 108] The composition of the metal oxide in the semiconductor layer 108 will be described below.

[0188] The composition of the metal oxide in the semiconductor layer 108 greatly affects the electrical characteristics and reliability of the transistor 100 .

[0189] For example, by increasing the content of indium in the metal oxide, a transistor with a large on-state current can be realized.

[0190] When an In—Zn oxide is used for the semiconductor layer 108, it is preferable to use a metal oxide in which the atomic ratio of indium is equal to or greater than the atomic ratio of zinc. For example, a metal oxide in which the atomic ratio of metal elements is In:Zn=1:1, In:Zn=2:1, In:Zn=3:1, In:Zn=4:1, In:Zn=5:1, In:Zn=7:1, or In:Zn=10:1, or a ratio close to these, can be used.

[0191] When an In—Sn oxide is used for the semiconductor layer 108, it is preferable to use a metal oxide in which the atomic ratio of indium is equal to or greater than the atomic ratio of tin. For example, a metal oxide in which the atomic ratio of metal elements is In:Sn=1:1, In:Sn=2:1, In:Sn=3:1, In:Sn=4:1, In:Sn=5:1, In:Sn=7:1, or In:Sn=10:1, or a ratio close to these values, can be used.

[0192] When an In-Sn-Zn oxide is used for the semiconductor layer 108, a metal oxide in which the atomic ratio of indium is higher than that of tin can be used. Furthermore, it is preferable to use a metal oxide in which the atomic ratio of zinc is higher than that of tin. For example, the atomic ratios of metal elements may be In:Sn:Zn=2:1:3, In:Sn:Zn=3:1:2, In:Sn:Zn=4:2:3, In:Sn:Zn=4:2:4.1, In:Sn:Zn=5:1:3, In:Sn:Zn=5:1:6, In:Sn:Zn=5:1:7, In:Sn:Zn=5:1:8, In:Sn:Zn=6:1:6, In :Sn:Zn=10:1:3, In:Sn:Zn=10:1:6, In:Sn:Zn=10:1:7, In:Sn:Zn=10:1:8, In:Sn:Zn=5:2:5, In:Sn:Zn=10:1:10, In:Sn:Zn=20:1:10, In:Sn:Zn=40:1:10, or metal oxides thereof having a ratio close to these can be used.

[0193] When an In-Al-Zn oxide is used for the semiconductor layer 108, a metal oxide in which the atomic ratio of indium is higher than that of aluminum can be used. Furthermore, it is preferable to use a metal oxide in which the atomic ratio of zinc is higher than that of aluminum. For example, the atomic ratios of metal elements may be In:Al:Zn=2:1:3, In:Al:Zn=3:1:2, In:Al:Zn=4:2:3, In:Al:Zn=4:2:4.1, In:Al:Zn=5:1:3, In:Al:Zn=5:1:6, In:Al:Zn=5:1:7, In:Al:Zn=5:1:8, In:Al:Zn=6:1:6, In In:Al:Zn=10:1:3, In:Al:Zn=10:1:6, In:Al:Zn=10:1:7, In:Al:Zn=10:1:8, In:Al:Zn=5:2:5, In:Al:Zn=10:1:10, In:Al:Zn=20:1:10, In:Al:Zn=40:1:10, or metal oxides thereof having a similar ratio can be used.

[0194] When an In—Ga—Zn oxide is used for the semiconductor layer 108, a metal oxide in which the atomic ratio of indium to the number of atoms of the metal element is higher than the atomic ratio of gallium can be used. Furthermore, it is more preferable to use a metal oxide in which the atomic ratio of zinc is higher than the atomic ratio of gallium. For example, the semiconductor layer 108 may have an atomic ratio of metal elements of In:Ga:Zn=2:1:3, In:Ga:Zn=3:1:2, In:Ga:Zn=4:2:3, In:Ga:Zn=4:2:4.1, In:Ga:Zn=5:1:3, In:Ga:Zn=5:1:6, In:Ga:Zn=5:1:7, In:Ga:Zn=5:1:8, or In:Ga:Zn=6:1. :6, In:Ga:Zn=10:1:3, In:Ga:Zn=10:1:6, In:Ga:Zn=10:1:7, In:Ga:Zn=10:1:8, In:Ga:Zn=5:2:5, In:Ga:Zn=10:1:10, In:Ga:Zn=20:1:10, In:Ga:Zn=40:1:10, or metal oxides thereof can be used.

[0195] When an In-M-Zn oxide is used for the semiconductor layer 108, a metal oxide in which the atomic ratio of indium to the number of atoms of the metal element is higher than the atomic ratio of the element M can be used. Furthermore, it is more preferable to use a metal oxide in which the atomic ratio of zinc is higher than the atomic ratio of the element M. For example, the semiconductor layer 108 may have an atomic ratio of metal elements in the range of In:M:Zn=2:1:3, In:M:Zn=3:1:2, In:M:Zn=4:2:3, In:M:Zn=4:2:4.1, In:M:Zn=5:1:3, In:M:Zn=5:1:6, In:M:Zn=5:1:7, In:M:Zn=5:1:8, In:M:Zn=6:1: In:M:Zn=10:1:6, In:M:Zn=10:1:3, In:M:Zn=10:1:6, In:M:Zn=10:1:7, In:M:Zn=10:1:8, In:M:Zn=5:2:5, In:M:Zn=10:1:10, In:M:Zn=20:1:10, In:M:Zn=40:1:10, or metal oxides thereof having a similar structure can be used.

[0196] In addition, when the element M has a plurality of metal elements, the sum of the atomic ratios of the metal elements can be taken as the atomic ratio of the element M. For example, in the case of an In-Ga-Al-Zn oxide having gallium and aluminum as the element M, the sum of the atomic ratio of gallium and the atomic ratio of aluminum can be taken as the atomic ratio of the element M. Furthermore, it is preferable that the atomic ratios of indium, the element M, and zinc are within the above-mentioned range. For example, in the case of an In-Ga-Sn-Zn oxide having gallium and tin as the element M, the sum of the atomic ratio of gallium and the atomic ratio of tin can be taken as the atomic ratio of the element M. Furthermore, it is preferable that the atomic ratios of indium, the element M, and zinc are within the above-mentioned range.

[0197] It is preferable to use a metal oxide in which the ratio of the number of indium atoms to the number of atoms of metal elements contained in the metal oxide is 30 atomic % or more and 100 atomic % or less, preferably 30 atomic % or more and 95 atomic % or less, more preferably 35 atomic % or more and 95 atomic % or less, more preferably 35 atomic % or more and 90 atomic % or less, more preferably 40 atomic % or more and 90 atomic % or less, more preferably 45 atomic % or more and 90 atomic % or less, more preferably 50 atomic % or more and 80 atomic % or less, more preferably 60 atomic % or more and 80 atomic % or less, and more preferably 70 atomic % or more and 80 atomic % or less. For example, when an In—Ga—Zn oxide is used for the semiconductor layer 108, it is preferable that the ratio of the number of indium atoms to the total number of atoms of indium, the element M, and zinc be in the above-mentioned range.

[0198] In this specification and the like, the ratio of the number of indium atoms to the number of atoms of the contained metal element may be referred to as the indium content. The same applies to other metal elements.

[0199] By increasing the indium content of the metal oxide, a transistor with a large on-state current can be obtained. By applying the transistor to a transistor that is required to have a high on-state current, a semiconductor device with excellent electrical characteristics can be obtained.

[0200] The composition of the metal oxide can be analyzed by, for example, energy dispersive X-ray spectrometry (EDX), X-ray photoelectron spectroscopy (XPS), inductively coupled plasma mass spectrometry (ICP-MS), or inductively coupled plasma atomic emission spectrometry (ICP-AES). Alternatively, a combination of these techniques may be used for the analysis. For elements with low content, the actual content may differ from the content obtained by analysis due to the influence of analytical accuracy. For example, when the content of element M is low, the content of element M obtained by analysis may be lower than the actual content.

[0201] In this specification, a "nearby composition" includes a range of ±30% of the desired atomic ratio. For example, when an atomic ratio is described as In:M:Zn = 4:2:3 or a composition thereabout, this includes a case where, when the atomic ratio of indium is 4, the atomic ratio of M is 1 or more and 3 or less, and the atomic ratio of zinc is 2 or more and 4 or less. Furthermore, when an atomic ratio is described as In:M:Zn = 5:1:6 or a composition thereabout, this includes a case where, when the atomic ratio of indium is 5, the atomic ratio of M is more than 0.1 and 2 or less, and the atomic ratio of zinc is 5 or more and 7 or less. Furthermore, when an atomic ratio is described as In:M:Zn = 1:1:1 or a composition thereabout, this includes a case where, when the atomic ratio of indium is 1, the atomic ratio of M is more than 0.1 and 2 or less, and the atomic ratio of zinc is more than 0.1 and 2 or less.

[0202] Here, the reliability of a transistor will be described. One of the indicators for evaluating the reliability of a transistor is a Gate Bias Temperature (GBT) stress test, in which the transistor is held in a state in which an electric field is applied to the gate. Among these, a test in which a positive potential (positive bias) is applied to the gate with respect to the source potential and the drain potential and the transistor is held at a high temperature is called a Positive Bias Temperature (PBTS) test, and a test in which a negative potential (negative bias) is applied to the gate and the transistor is held at a high temperature is called a Negative Bias Temperature (NBTS) test. The PBTS test and the NBTS test performed under light irradiation are called a PBTIS (Positive Bias Temperature Illumination Stress) test and an NBTIS (Negative Bias Temperature Illumination Stress) test, respectively.

[0203] In an n-type transistor, a positive potential is applied to the gate when the transistor is turned on (a state in which current flows). Therefore, the amount of variation in threshold voltage in the PBTS test is one of the important items to be noted as an index of the reliability of the transistor.

[0204] By using a metal oxide that does not contain gallium or has a low gallium content for the semiconductor layer 108, a transistor with high reliability against positive bias application can be obtained. That is, a transistor with a small amount of variation in threshold voltage in a PBTS test can be obtained. Furthermore, when a metal oxide containing gallium is used, it is preferable to make the gallium content lower than the indium content. This allows a highly reliable transistor to be realized.

[0205] One of the factors that causes the threshold voltage to fluctuate in the PBTS test is defect levels at or near the interface between the semiconductor layer and the gate insulating layer. The higher the defect level density, the more significant the degradation in the PBTS test. By reducing the gallium content in the region of the semiconductor layer that contacts the gate insulating layer, the generation of the defect levels can be suppressed.

[0206] The following is a possible reason why using a metal oxide containing no gallium or with a low gallium content for the semiconductor layer can suppress fluctuations in threshold voltage in the PBTS test. Gallium contained in the metal oxide has the property of attracting oxygen more easily than other metal elements (e.g., indium or zinc). Therefore, it is presumed that gallium combines with excess oxygen in the gate insulating layer at the interface between the gallium-rich metal oxide and the gate insulating layer, making it easier to generate carrier (here, electron) trap sites. Therefore, when a positive potential is applied to the gate, carriers are trapped at the interface between the semiconductor layer and the gate insulating layer, which is thought to cause fluctuations in threshold voltage.

[0207] More specifically, when an In—Ga—Zn oxide is used for the semiconductor layer 108, a metal oxide in which the atomic ratio of indium is higher than that of gallium can be used for the semiconductor layer 108. It is more preferable to use a metal oxide in which the atomic ratio of zinc is higher than that of gallium. In other words, it is preferable to use a metal oxide in which the atomic ratios of metal elements satisfy In>Ga and Zn>Ga for the semiconductor layer 108.

[0208] The semiconductor layer 108 preferably uses a metal oxide in which the ratio of the number of gallium atoms to the number of atoms of the contained metal element is greater than 0 atomic % and less than 50 atomic %, preferably 0.1 atomic % to 40 atomic %, more preferably 0.1 atomic % to 35 atomic %, more preferably 0.1 atomic % to 30 atomic %, more preferably 0.1 atomic % to 25 atomic %, more preferably 0.1 atomic % to 20 atomic %, more preferably 0.1 atomic % to 15 atomic %, and more preferably 0.1 atomic % to 10 atomic %. By reducing the gallium content in the semiconductor layer, a transistor with high resistance to the PBTS test can be obtained. Note that by including gallium in the metal oxide, oxygen deficiency (V Ｏ This has the effect of making oxygen vacancy less likely to occur.

[0209] A metal oxide that does not contain gallium may be used for the semiconductor layer 108. For example, In—Zn oxide may be used for the semiconductor layer 108. In this case, increasing the atomic ratio of indium to the atomic number of metal elements contained in the metal oxide can increase the field-effect mobility of the transistor. On the other hand, increasing the atomic ratio of zinc to the atomic number of metal elements contained in the metal oxide can result in a metal oxide with high crystallinity, thereby suppressing fluctuations in the electrical characteristics of the transistor and improving reliability. Alternatively, a metal oxide that does not contain gallium or zinc, such as indium oxide, may be used for the semiconductor layer 108. Using a metal oxide that does not contain gallium can significantly reduce fluctuations in threshold voltage, particularly in a PBTS test.

[0210] For example, an oxide containing indium and zinc can be used for the semiconductor layer 108. In this case, a metal oxide in which the atomic ratio of metal elements is, for example, In:Zn=2:3 or a ratio therebetween is approximately 2:3 can be used.

[0211] Although gallium has been used as a representative example in the description, the present invention can also be applied to a case where the element M is used instead of gallium. For the semiconductor layer 108, it is preferable to use a metal oxide in which the atomic ratio of indium is higher than the atomic ratio of the element M. It is also preferable to use a metal oxide in which the atomic ratio of zinc is higher than the atomic ratio of the element M.

[0212] A transistor having high reliability when a positive bias is applied can be obtained by using a metal oxide having a low content of the element M for the semiconductor layer 108. When the transistor is used as a transistor that is required to have high reliability when a positive bias is applied, a highly reliable semiconductor device can be obtained.

[0213] Next, the reliability of the transistor against light will be described.

[0214] Light incident on a transistor may cause fluctuations in the electrical characteristics of the transistor. In particular, it is preferable that a transistor applied to a region where light may be incident exhibits small fluctuations in electrical characteristics under light irradiation and has high reliability against light. The reliability against light can be evaluated, for example, by the amount of fluctuation in threshold voltage in an NBTIS test.

[0215] Increasing the content of the element M in the metal oxide can provide a transistor with high reliability against light. That is, a transistor with a small variation in threshold voltage in an NBTIS test can be provided. Specifically, a metal oxide in which the atomic ratio of the element M is equal to or greater than the atomic ratio of indium has a larger band gap, and can reduce the variation in threshold voltage of the transistor in an NBTIS test. The band gap of the metal oxide in the semiconductor layer 108 is preferably 2.0 eV or more, more preferably 2.5 eV or more, even more preferably 3.0 eV or more, still more preferably 3.2 eV or more, even more preferably 3.3 eV or more, still more preferably 3.4 eV or more, and still more preferably 3.5 eV or more.

[0216] For example, the semiconductor layer 108 can use metal oxides having an atomic ratio of metal elements of In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=1:3:2, In:M:Zn=1:3:3, In:M:Zn=1:3:4, or similar ratios thereof.

[0217] For the semiconductor layer 108, a metal oxide in which the ratio of the number of atoms of element M to the number of atoms of the contained metal element is 20 atomic % or more and 70 atomic % or less, preferably 30 atomic % or more and 70 atomic % or less, more preferably 30 atomic % or more and 60 atomic % or less, more preferably 40 atomic % or more and 60 atomic % or less, and more preferably 50 atomic % or more and 60 atomic % or less can be suitably used.

[0218] When an In—Ga—Zn oxide is used for the semiconductor layer 108, a metal oxide in which the atomic ratio of indium to the number of atoms of the metal element is equal to or less than the atomic ratio of gallium can be used. For example, a metal oxide in which the atomic ratio of the metal element is In:Ga:Zn=1:1:1, In:Ga:Zn=1:1:1.2, In:Ga:Zn=1:3:2, In:Ga:Zn=1:3:3, In:Ga:Zn=1:3:4, or a ratio close to these can be used.

[0219] For the semiconductor layer 108, a metal oxide in which the ratio of the number of gallium atoms to the number of atoms of the contained metal element is 20 atomic % or more and 60 atomic % or less, preferably 20 atomic % or more and 50 atomic % or less, more preferably 30 atomic % or more and 50 atomic % or less, more preferably 40 atomic % or more and 60 atomic % or less, and more preferably 50 atomic % or more and 60 atomic % or less can be suitably used.

[0220] A transistor with high reliability to light can be obtained by using a metal oxide having a high content of element M for the semiconductor layer 108. By using the transistor as a transistor that is required to have high reliability to light, a highly reliable semiconductor device can be obtained.

[0221] As described above, the electrical characteristics and reliability of a transistor vary depending on the composition of the metal oxide used in the semiconductor layer 108. Therefore, by varying the composition of the metal oxide depending on the electrical characteristics and reliability required of the transistor, a semiconductor device that has both excellent electrical characteristics and high reliability can be obtained.

[0222] The semiconductor layer 108 may have a stacked structure including two or more metal oxide layers. The two or more metal oxide layers included in the semiconductor layer 108 may have the same or approximately the same composition. By using a stacked structure of metal oxide layers having the same composition, for example, the same sputtering target can be used for formation, thereby reducing manufacturing costs.

[0223] The two or more metal oxide layers included in the semiconductor layer 108 may have different compositions. For example, a stacked structure of a first metal oxide layer having an atomic ratio of In:M:Zn=1:3:4 or a composition similar thereto and a second metal oxide layer having an atomic ratio of In:M:Zn=1:1:1 or a composition similar thereto, provided on the first metal oxide layer, can be preferably used. Furthermore, it is particularly preferable to use gallium or aluminum as the element M. For example, a stacked structure of any one selected from indium oxide, indium gallium oxide, and IGZO and any one selected from IAZO, IAGZO, and ITZO (registered trademark) can be used.

[0224] 7A illustrates a configuration example of the transistor 100. Fig. 7A illustrates a cross-sectional view of a cut surface taken along dashed dotted line A1-A2 in the top view illustrated in Fig. 1A, which is an example of a configuration different from that illustrated in Fig. 1B.

[0225] The transistor 100 shown in FIG. 7A differs from that shown in FIG. 1B mainly in that it includes a conductive layer 104b and that the top surface of the insulating layer 110b is planarized.

[0226] The conductive layer 104b is provided along the recessed portion of the insulating layer 106. The upper surface of the conductive layer 104b has a recessed portion, and the conductive layer 104 is provided so as to fill the recessed portion of the upper surface of the conductive layer 104b. The conductive layer 104 has a region that is thicker than the conductive layer 104b.

[0227] The conductive layer 104b functions as a gate electrode. The conductive layer 104 also functions as a gate electrode or as a conductive layer electrically connected to a gate electrode. In the structure shown in FIG. 7A, the conductive layer 104b is provided between the conductive layer 104 and the insulating layer 106.

[0228] The conductive layer 104b is preferably made of a material that is less likely to oxidize than the conductive layer 104. Furthermore, the conductive layer 104b is preferably made of a material that is more thermally stable than the conductive layer 104.

[0229] Furthermore, the conductive layer 104b can be thinner than the conductive layer 104. By reducing the thickness of the conductive layer, stress in the conductive layer can be reduced and adhesion between the conductive layer 104b and the insulating layer 106 can be improved in some cases.

[0230] Furthermore, it is preferable to use a material having lower resistance than the conductive layer 104b for the conductive layer 104. Even when the same material as the conductive layer 104b is used for the conductive layer 104, the conductive layer 104 may have a lower resistance because it has a region that is thicker than the conductive layer 104b.

[0231] For example, it is preferable to use a metal nitride as the conductive layer 104b, since the use of a metal nitride may improve adhesion between the conductive layer 104b and the insulating layer 106.

[0232] When the transistor 100 includes both the conductive layer 104b and the conductive layer 104, the resistance of the gate electrode can be reduced and the gate electrode can be stably formed, thereby improving the characteristics and reliability of the transistor.

[0233] 7A includes an insulating layer 110b3 between insulating layers 110a2 and 110b2. Conductive layer 114 is formed to fill the opening in insulating layer 110b3. By including insulating layer 110b3 in the configuration shown in FIG. 7A, the step on the top surface of insulating layer 110b2 can be further reduced, and the step on the top surface of conductive layer 112b can be further reduced, compared to the configuration shown in FIG. 1B.

[0234] 7A, the insulating layer 195 includes an insulating layer 195a, an insulating layer 195b on the insulating layer 195a, and an insulating layer 195c on the insulating layer 195b.

[0235] 7A can be formed by, for example, a dual damascene method, which allows the formation of the plug and the conductive layer to be performed simultaneously, thereby simplifying the process.

[0236] The insulating layer 195b preferably functions as an etching stopper when processing the insulating layer 195c. Therefore, it is preferable that the insulating layer 195b is made of a different material from the insulating layer 195c. For example, silicon oxide can be used for the insulating layer 195c, and silicon nitride can be used for the insulating layer 195b. However, the present invention is not limited to this. The insulating layer 195c can be made of a material that can be used for the insulating layer 110a2, etc., and the insulating layer 195b can be made of a material that can be used for the insulating layer 110a1, etc. Furthermore, the insulating layer 195a can be made of a material that can be used for the insulating layer 110a2, etc., for example.

[0237] Alternatively, the conductive layer 114 may have a two-layer structure of a conductive layer 114 a and a conductive layer 114 b over the conductive layer 114 a. For example, a nitride or an oxide can be used as the conductive layer 114 a, and one or more of chromium, copper, aluminum, gold, silver, zinc, molybdenum, tantalum, titanium, tungsten, manganese, nickel, iron, cobalt, and niobium, or an alloy containing one or more of the above metals can be used as the conductive layer 114 b.

[0238] 7B illustrates a configuration example of the transistor 100. Fig. 7B illustrates a cross-sectional view of a cut surface taken along dashed dotted line A1-A2 in the top view illustrated in Fig. 1A, showing an example of a configuration different from that in Fig. 1B.

[0239] The transistor 100 shown in FIG. 7B differs from that shown in FIG. 1B mainly in that the shape of the conductive layer 114 is different, the shape of the conductive layer 104 is different, the conductive layer 112a_1 is not embedded in the opening of the insulating layer 115, and the shape of the insulating layer 195 is different.

[0240] 7B , the outer side surface of the conductive layer 114 has a tapered shape. Here, the outer side surface of the conductive layer 114 refers to, for example, the side surface that is on the outside in a cross-sectional view of a region including the conductive layer 114. Furthermore, the inner side surface of the conductive layer 114 refers to, for example, the side surface that faces the insulating layer 110s. That is, at least a portion of the outer side surface of the conductive layer 114 is provided at an angle with respect to, for example, the substrate surface or the surface on which the conductive layer 114 is to be formed (here, for example, the upper surface of the insulating layer 110a on which the conductive layer 114 is to be formed).

[0241] The outer side surface of the conductive layer 114 is covered with the insulating layer 110b. The tapered shape of the outer side surface of the conductive layer 114 can improve the coverage of the insulating layer 110b, for example, at the corner formed by the top surface and side surface of the conductive layer 114 and at the side surface of the conductive layer 114. Improving the coverage of the insulating layer means, for example, that the thickness of the insulating layer formed on the surface to be covered is highly uniform. Alternatively, it means that the covering insulating layer is formed to follow the shape of the surface to be covered. Alternatively, it means that the covering insulating layer has high adhesion to the surface to be covered.

[0242] 7B , the conductive layer 104 is provided to fit the recess in the upper surface of the semiconductor layer 108, and the upper surface of the conductive layer 104 has a recess. The insulating layer 195 is provided to fit the recess in the upper surface of the conductive layer 104, and the upper surface of the insulating layer 195 has a recess. Neither the upper surface of the conductive layer 104 nor the upper surface of the insulating layer 195 is planarized.

[0243] 7B, the manufacturing process of the transistor can be simplified because the conductive layer 104 and the insulating layer 195 can be manufactured without a planarization step. Furthermore, the thicknesses of the conductive layer 104 and the insulating layer 195 can be thin, which is suitable for the use of a material with a slow deposition rate or a high cost material.

[0244] 7B , the conductive layer 112a is provided over the substrate 102, and the insulating layer 110a is provided over the conductive layer 112a. The conductive layer 112a has a stacked structure of a conductive layer 112a_1 and a conductive layer 112a_2. The insulating layer 110a is preferably provided in contact with a side surface of the conductive layer 112a_1 and a side surface and a top surface of the conductive layer 112a_2. As shown in FIG. 7B , the side surface of the conductive layer 112a_1 and the side surface of the conductive layer 112a_2 may both have a tapered shape. By having the side surface of the conductive layer 112a_1 and the side surface of the conductive layer 112a_2 both have a tapered shape, the coverage of the insulating layer 110a can be improved at a corner formed between the top surface and the side surface of the conductive layer 112a_1, the side surface of the conductive layer 112a_1, and the side surface of the conductive layer 112a_2.

[0245] 7B , the insulating layer 115 is not provided, and the conductive layer 112a_1 is not embedded in the opening of the insulating layer 115. By not forming the insulating layer 115 and not performing a step of planarizing the top surfaces of the conductive layer 112a_1 and the insulating layer 115, the manufacturing process of the transistor can be simplified.

[0246] <Manufacturing Method Example> A manufacturing method of a transistor according to one embodiment of the present invention will be described below with reference to the drawings. Here, the transistor 100 illustrated in FIG. 1B and the like will be described as an example.

[0247] Thin films (insulating films, semiconductor films, conductive films, etc.) constituting the semiconductor device can be formed using a sputtering method, a chemical vapor deposition (CVD) method, a vacuum evaporation method, a pulsed laser deposition (PLD) method, an atomic layer deposition (ALD) method, or the like.

[0248] Sputtering methods include RF sputtering, which uses a high-frequency power supply as the sputtering power source, DC sputtering, which uses a direct current power supply, and pulsed DC sputtering, which changes the voltage applied to the electrode in a pulsed manner. RF sputtering is mainly used to deposit insulating films, while DC sputtering is mainly used to deposit metal conductive films. Pulsed DC sputtering is mainly used to deposit films of compounds such as oxides, nitrides, or carbides using reactive sputtering.

[0249] CVD methods can be classified into plasma-enhanced CVD (PECVD), which uses plasma, thermal CVD (TCVD), which uses heat, and photo-CVD (photo-CVD), which uses light. CVD methods can also be further classified into metal CVD (MCVD) and metal organic CVD (MOCVD), depending on the source gas used.

[0250] The plasma CVD method can produce high-quality films at relatively low temperatures. Furthermore, the thermal CVD method is a film formation method that can minimize plasma damage to the workpiece because it does not use plasma. For example, wiring, electrodes, and elements (transistors, capacitors, etc.) included in a semiconductor device may become charged up by receiving electric charge from the plasma. In this case, the accumulated electric charge may destroy the wiring, electrodes, or elements included in the semiconductor device. On the other hand, the thermal CVD method, which does not use plasma, does not cause such plasma damage, and therefore can increase the yield of semiconductor devices. Furthermore, the thermal CVD method does not cause plasma damage during film formation, so films with fewer defects can be obtained.

[0251] As the ALD method, a thermal ALD method in which a reaction between a precursor and a reactant is carried out using only thermal energy, a PEALD method in which a plasma-excited reactant is used, or the like can be used.

[0252] The CVD and ALD methods differ from sputtering methods in that particles emitted from a target or the like are deposited. Therefore, they are film formation methods that are less affected by the shape of the workpiece and have good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surface of an opening with a high aspect ratio, for example. However, because the ALD method has a relatively slow film formation rate, it may be preferable to use it in combination with other film formation methods, such as the CVD method, which has a faster film formation rate.

[0253] Furthermore, the CVD method allows deposition of a film of any composition by adjusting the flow rate ratio of the source gases. For example, the CVD method allows deposition of a film with a continuously changing composition by changing the flow rate ratio of the source gases during deposition. When deposition is performed while changing the flow rate ratio of the source gases, the time required for deposition can be shortened compared to deposition using multiple deposition chambers because no time is required for transport or pressure adjustment. Therefore, the productivity of semiconductor devices can be improved in some cases.

[0254] In addition, in the ALD method, a film of any composition can be formed by simultaneously introducing multiple different precursors, or by controlling the number of cycles of each precursor when multiple different precursors are introduced.

[0255] Thin films (insulating films, semiconductor films, conductive films, etc.) that constitute semiconductor devices can be formed by methods such as spin coating, dipping, spray coating, inkjet printing, dispensing, screen printing, offset printing, doctor knife coating, slit coating, roll coating, curtain coating, and knife coating.

[0256] When processing a thin film that constitutes a semiconductor device, it can be processed using a photolithography method or the like. Alternatively, the thin film may be processed using a nanoimprint method, a sandblasting method, a lift-off method or the like. Furthermore, an island-shaped thin film may be directly formed by a film formation method using a shielding mask such as a metal mask.

[0257] There are two typical photolithography methods: one is to form a resist mask on the thin film to be processed, process the thin film by etching or the like, and then remove the resist mask; the other is to form a photosensitive thin film, and then process the thin film into the desired shape by exposure and development.

[0258] In photolithography, the light used for exposure may be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture of these. Other light sources that can be used include ultraviolet light, KrF laser light, ArF laser light, etc. Exposure may also be performed by immersion exposure technology. Extreme ultraviolet (EUV) light or X-rays may also be used as the light used for exposure. An electron beam may also be used instead of the light used for exposure. Extreme ultraviolet light, X-rays, or an electron beam are preferred because they enable extremely fine processing. When exposure is performed by scanning a beam such as an electron beam, a photomask is not required.

[0259] For etching the thin film, for example, dry etching, wet etching, or sandblasting can be used.

[0260] As a typical example of a planarization treatment for a thin film, a polishing treatment such as chemical mechanical polishing (CMP) can be preferably used. A reflow method in which a conductive layer is heated to fluidize it can also be preferably used. A combination of the reflow method and the CMP method can also be used. Other methods include dry etching and plasma treatment. The polishing treatment, dry etching treatment, and plasma treatment can be performed multiple times, or they can be combined. When combined, the order of the steps is not particularly limited and can be set appropriately according to the unevenness of the surface to be treated.

[0261] To precisely process a thin film to a desired thickness, for example, CMP is used. In this case, the thin film is first polished at a constant processing speed until a portion of the top surface thereof is exposed. Then, the thin film is polished at a slower processing speed until the thin film reaches the desired thickness, thereby enabling highly accurate processing.

[0262] Methods for detecting the end point of polishing include an optical method in which light is irradiated onto the surface of the surface to be treated and changes in the reflected light are detected, a physical method in which changes in the polishing resistance that the processing device receives from the surface to be treated are detected, and a method in which magnetic field lines are applied to the surface to be treated and changes in the magnetic field lines due to the eddy currents that are generated are used.

[0263] After the upper surface of the thin film is exposed, the thickness of the thin film can be controlled with high precision by performing a polishing process at a slow processing speed while monitoring the thickness of the thin film by an optical method such as a laser interferometer. If necessary, the polishing process may be performed multiple times until the thin film reaches the desired thickness.

[0264] 8A to 10C illustrate a method for manufacturing the transistor 100. Each diagram illustrates a cross-sectional view taken along dashed dotted line A1-A2.

[0265] An insulating film that will become the insulating layer 115 is formed over the substrate 102. Then, a part of the insulating film is removed to form the insulating layer 115 having an opening. A conductive film 112af_1 is formed so as to fill the opening of the insulating layer 115 (FIG. 8A).

[0266] Next, planarization treatment is performed on the conductive film 112af_1 so as to expose the surface of the insulating layer 115. In this manner, the conductive layer 112a_1 can be formed so as to be embedded in the insulating layer 115. As the planarization treatment, for example, a CMP method can be used.

[0267] Next, a conductive film to be the conductive layer 112a_2 is formed over the conductive layer 112a_1 and the insulating layer 115, and part of the conductive film is removed to form the conductive layer 112a_2 (FIG. 8B). The conductive film can be processed by one or both of a wet etching method and a dry etching method.

[0268] Subsequently, an insulating film 110a1_f is formed over the conductive layer 112a_2 and the insulating layer 115, and an insulating film 110a2_f is formed over the insulating film 110a1_f.

[0269] The insulating film 110a1_f can be formed using any of the materials that can be used for the insulating layer 110a1 described above.

[0270] For example, silicon nitride, silicon nitride oxide, aluminum oxide, hafnium oxide, or the like can be suitably used for the insulating film 110a1_f.

[0271] Specifically, the insulating film 110a1_f can be formed by, for example, a silicon nitride film by a sputtering method, a PEALD method, an aluminum oxide film by a sputtering method, or a silicon nitride film by a PEALD method.

[0272] Alternatively, for example, a structure in which aluminum oxide and silicon nitride are stacked can be used, for example, a structure in which aluminum oxide formed by sputtering and silicon nitride formed by PEALD are stacked.

[0273] The insulating film 110a2_f can be formed using any of the above-described materials that can be used for the insulating layer 110a2.

[0274] For example, silicon oxide, silicon oxynitride, or the like can be suitably used as the insulating film 110a2_f.

[0275] Specifically, the insulating film 110a2_f can be formed by, for example, a silicon oxide film by a sputtering method, a silicon oxide film by a PECVD method, or a silicon oxynitride film by a PECVD method.

[0276] Alternatively, for example, a silicon oxide film formed by sputtering and a silicon oxide or silicon oxynitride film formed by PECVD can be stacked and used.

[0277] After the insulating films 110a1_f and 110a2_f are formed, heat treatment may be performed. By performing the heat treatment, water and hydrogen can be released from the surfaces and the interiors of the insulating films 110a1_f and 110a2_f.

[0278] The temperature of the heat treatment is preferably 150° C. or higher and lower than the strain point of the substrate, more preferably 200° C. or higher and 450° C. or lower, further preferably 250° C. or higher and 450° C. or lower, further preferably 300° C. or higher and 450° C. or lower, further preferably 300° C. or higher and 400° C. or lower, and further preferably 350° C. or higher and 400° C. or lower. The heat treatment can be performed in an atmosphere containing one or more of a rare gas, nitrogen, or oxygen. As the nitrogen-containing atmosphere or the oxygen-containing atmosphere, dry air (CDA) may be used. Note that the atmosphere preferably contains as little hydrogen, water, or the like as possible. As the atmosphere, it is preferable to use a high-purity gas with a dew point of −60° C. or lower, preferably −100° C. or lower. Using an atmosphere containing as little hydrogen, water, or the like as possible can prevent hydrogen, water, or the like from being taken into the insulating film 110a1_f and the insulating film 110a2_f. The heat treatment can be performed using, for example, an oven or a rapid thermal annealing (RTA) device. By using an RTA device, the heat treatment time can be shortened.

[0279] Subsequently, a step of supplying oxygen to the insulating film may be performed. Here, as an example, after the insulating films 110a1_f and 110a2_f are formed, a metal oxide layer is formed to supply oxygen to the insulating film 110a1_f and the insulating layer 110a2_f. Alternatively, heat treatment may be performed after the metal oxide layer is formed. By performing heat treatment after the metal oxide layer is formed, oxygen can be effectively supplied from the metal oxide layer to the insulating film 110a1_f and the insulating film 110a2_f, and oxygen can be contained in the insulating film. When the oxygen supplied to the insulating film is supplied to the semiconductor layer 108 in a later step, oxygen vacancies (V Ｏ ) and V Ｏ H can be reduced.

[0280] After forming the metal oxide layer or after the heat treatment, oxygen may be further supplied to the insulating film through the metal oxide layer. Examples of oxygen supply methods include ion implantation, ion doping, plasma immersion ion implantation, and plasma treatment. For the plasma treatment, an apparatus that converts oxygen gas into plasma using high-frequency power can be suitably used. Examples of apparatus that convert gas into plasma using high-frequency power include a plasma etching apparatus and a plasma ashing apparatus.

[0281] The metal oxide layer may be an insulating layer or a conductive layer, and may be, for example, aluminum oxide, hafnium oxide, hafnium aluminate, indium oxide, indium tin oxide (ITO), or silicon-containing indium tin oxide (ITSO).

[0282] For the metal oxide layer, it is preferable to use an oxide material containing one or more of the same elements as those of the semiconductor layer 108. In particular, it is preferable to use an oxide semiconductor material that can be used for the semiconductor layer 108.

[0283] When a metal oxide material containing indium and gallium is used for the metal oxide layer, a material having a higher gallium content (content rate) than the semiconductor layer 108 can be used for the metal oxide layer. By using a material having a higher gallium content (content rate) for the metal oxide layer, the blocking property against oxygen can be further improved, which is preferable.

[0284] The metal oxide layer is preferably formed in an atmosphere containing oxygen, for example. In particular, it is preferably formed by a sputtering method in an atmosphere containing oxygen. This allows oxygen to be suitably supplied to the insulating film during the formation of the metal oxide layer.

[0285] Next, the metal oxide layer is removed, for example, by wet etching.

[0286] The process of supplying oxygen to the insulating films 110a1_f and 110a2_f is not limited to the above-described method. For example, oxygen radicals, oxygen atoms, oxygen atomic ions, oxygen molecular ions, or the like may be supplied to the insulating films 110a1_f and 110a2_f by ion doping, ion implantation, plasma treatment, or the like. Alternatively, a film that suppresses oxygen desorption may be formed over the insulating films 110a1_f and 110a2_f, and then oxygen may be supplied to the insulating films 110a1_f and 110a2_f through the film. The film is preferably removed after supplying oxygen. The film that suppresses oxygen desorption may be a conductive film or a semiconductor film containing one or more of indium, zinc, gallium, tin, aluminum, chromium, tantalum, titanium, molybdenum, nickel, iron, cobalt, or tungsten.

[0287] Next, a conductive film to be the conductive layer 114_e is formed over the insulating film 110a2_f, and then part of the conductive film is removed to process the conductive film 114_e (FIG. 8C). Note that in a later configuration, an opening can be provided in the conductive layer 114_e to form the conductive layer 114.

[0288] Subsequently, an insulating film 110b2_f is formed over the insulating film 110a2_f and the conductive layer 114_e, and an insulating film 110b1_f is formed over the insulating film 110b2_f.

[0289] The insulating film 110b2_f can be formed using any of the materials that can be used for the insulating layer 110b2 described above. The insulating film 110b1_f can be formed using any of the materials that can be used for the insulating layer 110b1 described above.

[0290] For a material that can be used for the insulating film 110b2_f and a deposition method thereof, the description of the insulating film 110a2_f can be referred to. For a material that can be used for the insulating film 110b1_f and a deposition method thereof, the description of the insulating film 110a1_f can be referred to.

[0291] Subsequently, a conductive film 112b_f is formed over the insulating film 110b1_f. The conductive film 112b_f can be formed using any of the materials that can be used for the conductive layer 112b described above.

[0292] Next, a resist mask 191a is formed over the conductive film 112b_f by photolithography (FIG. 8D).

[0293] Next, using the resist mask 191a as a mask, the conductive film 112b_f, the insulating film 110b1_f, the insulating film 110b2_f, the conductive layer 114_e, the insulating film 110a2_f, and the insulating film 110a1_f are partly removed to sequentially form the conductive layer 112b_e having an opening, the insulating layer 110b1 having an opening, the insulating layer 110b2 having an opening, the conductive layer 114 having an opening, the insulating layer 110a2 having an opening, and the insulating layer 110a1 having an opening, thereby exposing the top surface of the conductive layer 112a_2 in a region that does not overlap with the resist mask 191a. Then, the resist mask 191a is removed.

[0294] Next, an insulating film 110s_f is formed to cover the upper surface of the conductive layer 112b_e, the sidewalls of the opening in the conductive layer 112b_e, the sidewalls of the opening in the insulating layer 110b1, the sidewalls of the opening in the insulating layer 110b2, the sidewalls of the opening in the conductive layer 114, the sidewalls of the opening in the insulating layer 110a2, the sidewalls of the opening in the insulating layer 110a1, and the exposed upper surface of the conductive layer 112a_2 (Figure 9A).

[0295] The insulating film 110s_f can be formed using any of the materials that can be used for the insulating layer 110s described above.

[0296] Depositing the insulating film 110s_f using a CVD method, an ALD method, or the like is preferable because, for example, the insulating film 110s_f can be well coated on the side walls of the openings of the conductive layer 112b_e, the insulating layer 110b, the conductive layer 114, and the insulating layer 110a.

[0297] Subsequently, the insulating film 110s_f is partly removed by etching to form the insulating layer 110s. Specifically, the insulating film 110s_f is partly removed by etching to leave regions of the insulating film 110s_f that are in contact with the conductive layer 112b_e, the insulating layer 110b, the conductive layer 114, and the sidewalls of the openings in the insulating layer 110a, thereby forming the insulating layer 110s.

[0298] The insulating film 110s_f can be etched by, for example, anisotropic etching. More specifically, the insulating layer 110s can be formed by, for example, dry etching with high anisotropy.

[0299] The process of forming a planarizing film on an uneven film surface and then performing highly anisotropic etching (e.g., dry etching) on ​​the uneven film along with the planarizing film to reduce the unevenness of the film is sometimes called an "etch-back process."

[0300] The thickness of the insulating layer 110s can be adjusted by changing the anisotropic etching conditions or film thickness.

[0301] Next, a resist mask 191b is formed to cover the top surface of the conductive layer 112b_e (FIG. 9B). After that, part of the conductive layer 112b_e is removed using the resist mask 191b as a mask, thereby forming the conductive layer 112b. After the conductive layer 112b is formed, the resist mask 191b is removed (FIG. 9C).

[0302] Note that in FIG. 8D , before forming the resist mask 191a, a resist mask 191b may be formed over the conductive film 112b_f to process the conductive film 112b_f, and after removing the resist mask 191b, a resist mask 191a may be formed to process the conductive film 112b_f, the insulating film 110b1_f, the insulating film 110b2_f, the conductive layer 114_e, the insulating film 110a2_f, and the insulating film 110a1_f.

[0303] As shown in FIG. 9D , depending on the fabrication conditions, a sidewall insulating layer, exemplified as insulating layer 110w, may be formed on the side surface of conductive layer 112b. FIG. 9D corresponds to the region surrounded by the dashed line in FIG. 9C . For example, if a portion of conductive film 112b_f is removed before forming insulating film 110s_f to form a pattern, a sidewall insulating layer may be formed at the edge of the pattern. Furthermore, a sidewall insulating layer such as insulating layer 110w may be formed not only on the side surface of conductive layer 112b, but also in areas of the surface on which insulating film 110s_f is to be formed that have irregularities.

[0304] Next, a semiconductor film that becomes the semiconductor layer 108 is formed to cover the exposed top surface of the conductive layer 112a_2, the sidewall of the insulating layer 110s, the top surface of the conductive layer 112b, and the top surface of the insulating layer 110b1. Then, part of the semiconductor film is removed by etching to form the semiconductor layer 108. Next, the insulating layer 106 is formed to cover the semiconductor layer 108, the conductive layer 112b, and the insulating layer 110b1 ( FIG. 10A ).

[0305] The semiconductor layer 108 is preferably formed on the sidewall of the insulating layer 110s with a thickness as uniform as possible, and therefore is preferably formed by ALD.

[0306] As a specific example, it is preferable to use a film formation method such as a thermal ALD (Atomic Layer Deposition) method or a PEALD (Plasma Enhanced ALD) method. The thermal ALD method is preferable because it exhibits extremely high step coverage. The PEALD method is also preferable because it exhibits high step coverage and allows low-temperature film formation.

[0307] For example, when a metal oxide is used for the semiconductor layer 108, the semiconductor layer 108 can be formed by an ALD method using a precursor containing a constituent metal element and an oxidizing agent.

[0308] For example, when forming an In—Ga—Zn oxide film, three precursors, i.e., a precursor containing indium, a precursor containing gallium, and a precursor containing zinc, can be used, or two precursors, i.e., a precursor containing indium and a precursor containing gallium and zinc, can be used.

[0309] As the precursor containing indium, triethylindium, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)indium, cyclopentadienylindium, indium(III) chloride, and the like can be used.

[0310] Furthermore, examples of precursors that can be used that contain gallium include trimethylgallium, triethylgallium, gallium trichloride, tris(dimethylamido)gallium, gallium(III) acetylacetonate, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)gallium, dimethylchlorogallium, diethylchlorogallium, and gallium(III) chloride.

[0311] Furthermore, as a precursor containing zinc, dimethyl zinc, diethyl zinc, zinc bis(2,2,6,6-tetramethyl-3,5-heptanedionate), zinc chloride, etc. can be used.

[0312] As the oxidizing agent, for example, ozone, oxygen, water, etc. can be used.

[0313] Methods for controlling the composition of the resulting film include adjusting the flow rate ratio of the source gases, the time for which the source gases are flowed, the order in which the source gases are flowed, etc. By adjusting these, it is also possible to form a film whose composition changes continuously. It is also possible to form films with different compositions successively.

[0314] Heat treatment may be performed after the semiconductor film to be the semiconductor layer 108 is formed. The heat treatment can reduce water and hydrogen contained in the semiconductor film and supply oxygen from the insulating layer 110a, the insulating layer 110b, the insulating layer 110s, and the like. Note that the heat treatment may be performed after the semiconductor film is processed.

[0315] Note that as long as the sidewall of the insulating layer 110s can be sufficiently covered, the semiconductor layer 108 can be formed by any method other than the ALD method. For example, a sputtering method is preferable because a film with a low hydrogen content can be obtained relatively easily.

[0316] The substrate temperature during the formation of the semiconductor layer 108 is preferably from room temperature (25° C.) to 200° C., more preferably from room temperature to 130° C. By setting the substrate temperature within the above range, bending or distortion of the substrate can be suppressed when a large-area glass substrate is used.

[0317] When a metal oxide layer is formed by a sputtering method, the higher the substrate temperature (stage temperature) during formation, the higher the crystallinity of the formed metal oxide layer.Furthermore, the higher the ratio of the flow rate of oxygen gas to the total film formation gas used during formation (hereinafter also referred to as the oxygen flow rate ratio), the higher the crystallinity of the formed metal oxide layer.

[0318] The insulating layer 106 is also preferably formed by a film formation method with high step coverage, similar to the semiconductor layer 108, and is preferably formed by an ALD method. Note that, if the insulating layer 106 can sufficiently cover the semiconductor layer 108, the insulating layer 106 may be formed by a method other than the ALD method, such as a PECVD method or a sputtering method.

[0319] Subsequently, an insulating film 195f is formed to cover the insulating layer 106 (FIG. 10B).

[0320] The insulating film 195f can be formed using the same material and method as the insulating layer 110a2, for example.

[0321] Here, an insulating layer that functions as an etching stopper when etching the insulating film 195f may be provided above the insulating layer 106. For example, the insulating layer 106 may have a two-layer laminated structure, and the upper layer may be an insulating layer formed from the same material and by the same method as the insulating layer 110a1.

[0322] Next, a part of the insulating film 195f is removed to expose the insulating layer 106, thereby forming an insulating layer 195 having an opening. After that, a conductive film to be the conductive layer 104 is formed so as to fill the opening of the insulating layer 195, and then planarization treatment is performed until the top surface of the insulating layer 195 is exposed, thereby forming the conductive layer 104 ( FIG. 10C ).

[0323] Through the above steps, the transistor 100 can be manufactured.

[0324] [Configuration Example 1-4] Fig. 11A shows a configuration example of a transistor 100. Fig. 11A shows an example of a configuration different from that shown in Fig. 1B as a cross-sectional view taken along dashed dotted line A1-A2 in the top view shown in Fig. 1A. Fig. 11B is an enlarged view of a region 162 shown in Fig. 11A.

[0325] The transistor 100 shown in FIG. 11A differs from that shown in FIG. 1B mainly in that the insulating layer 110s has a stacked structure of an insulating layer 110s1 and an insulating layer 110s2 on the insulating layer 110s1.

[0326] For example, the material and manufacturing method used for the insulating layer 110a1 can be applied to the insulating layer 110s1. For example, the material and manufacturing method used for the insulating layer 110a2 can be applied to the insulating layer 110s2.

[0327] In the case where the insulating layer 110s2 having a function of supplying oxygen is in contact with the conductive layer 114, there is a concern that the conductive layer 114 is oxidized, the amount of oxygen contained in the insulating layer 110s2 is reduced, and the amount of oxygen supplied from the insulating layer 110s2 to the semiconductor layer 108 is reduced. By forming the insulating layer 110s as a stacked structure of the insulating layer 110s1 and the insulating layer 110s2, the insulating layer 110s2 and the conductive layer 114 can be prevented from being in contact with each other.

[0328] [Configuration Example 1-5] Fig. 12A shows a configuration example of the transistor 100. Fig. 12A shows an example of a configuration different from that shown in Fig. 1B as a cross-sectional view of a cut surface taken along dashed dotted line A1-A2 in the top view shown in Fig. 1A. Fig. 12B is an enlarged view of a region 163 shown in Fig. 12A.

[0329] 1B in that an insulating layer 110g is provided between the conductive layer 114 and the insulating layer 110s, the insulating layer 110a further includes an insulating layer 110a3 in addition to the insulating layers 110a1 and 110a2, and the insulating layer 110b further includes an insulating layer 110b3 in addition to the insulating layers 110b1 and 110b2. The insulating layer 110a3 has a region sandwiched between the conductive layer 114 and the insulating layer 110a2, and the insulating layer 110b3 has a region sandwiched between the conductive layer 114 and the insulating layer 110b2.

[0330] For example, the material, manufacturing method, film thickness, and the like that are used for the insulating layer 110a1 can be applied to the insulating layer 110a3 and the insulating layer 110b3.

[0331] The insulating layer 110g contains, for example, an oxide of an element contained in the conductive layer 114. If the conductive layer 114 is a metal, the insulating layer 110g is, for example, an oxide of the metal. If the conductive layer 114 is silicon, the insulating layer 110g is, for example, a silicon oxide. For example, a metal oxide such as aluminum oxide or tantalum oxide can be used as the insulating layer 110g, and aluminum oxide is particularly preferred.

[0332] 12, the insulating layer 110s and the insulating layer 110g function as the gate insulating layer of the transistor 100. In the structure illustrated in FIG.

[0333] In addition, since the transistor 100 uses a stacked structure of insulating layer 110s and insulating layer 110g as a gate insulating layer, even if the insulating property of insulating layer 110g is lower than that of insulating layer 110s, if sufficient insulating property can be obtained by stacking it with insulating layer 110s, the characteristics and reliability of the transistor 100 may be sufficiently ensured.

[0334] The transistor 100 includes the insulating layer 110g, which may allow the thickness of the insulating layer 110s to be thin. Reducing the thickness of the insulating layer 110s can increase the dielectric constant of the gate insulating layer of the transistor 100. Furthermore, for example, a material having a higher dielectric constant than the material used for the insulating layer 110s can be suitably used for the insulating layer 110g.

[0335] As described below, the insulating layer 110g can be formed in a self-aligned manner by depositing a layer capable of supplying oxygen so as to be in contact with the surface of the conductive layer 114. If, during etching to form the insulating layer 110s, the height of the insulating layer 110s becomes lower than the height of the top surface of the conductive layer 114, or if the height of the insulating layer 110s is higher than the height of the top surface of the conductive layer 114 but the difference is small, there is a concern that leakage current will flow between the semiconductor layer 108 and the conductive layer 114, resulting in a deterioration in the characteristics of the transistor 100. Even in such a case, the transistor 100 can suppress leakage between the semiconductor layer 108 and the conductive layer 114 by including the insulating layer 110g.

[0336] The insulating layer 110g is, for example, a layer formed by oxidizing the conductive layer 114. An example of a method for manufacturing the insulating layer 110g will be described below.

[0337] First, the structure shown in Fig. 13A is fabricated. Fig. 13A illustrates a structure in which an insulating layer 115, a conductive layer 112a, an insulating layer 110a, an insulating layer 110b, a conductive layer 112b_e, and an insulating film 110s_f are formed over a substrate 102.

[0338] The structure shown in Figure 13A can be manufactured by referring to the processes in Figures 8A to 9A. In addition, before forming the conductive film that becomes the conductive layer 114_e, an insulating film that becomes the insulating layer 110a3 can be formed over the insulating layer 110a2_f, and after forming the conductive layer 114_e, an insulating film that becomes the insulating layer 110b3 can be formed.

[0339] An aluminum film is preferably used as the conductive film to be the conductive layer 114_e. Aluminum has low resistance and is easily oxidized, and therefore, the conductivity of the conductive layer 114 can be increased and the insulating layer 110g can be suitably formed.

[0340] After the insulating film 110s_f is formed, heat treatment is preferably performed. Note that the heat treatment may be performed after the insulating film 110s_f is etched to form the insulating layer 110s.

[0341] 13B is an enlarged view of a region 163 shown in Fig. 13A. The dotted arrows in Fig. 13B schematically show how oxygen is supplied from the insulating layer 110a2 and the insulating layer 110b2 to the insulating film 110s_f, and the dashed arrows schematically show how oxygen is supplied from the insulating film 110s_f to the conductive layer 114.

[0342] Oxygen can be supplied from the insulating layer 110a2 and the insulating layer 110b2 to the insulating film 110s_f, for example, during heat treatment after the insulating film 110s_f is formed, or during the formation of the insulating film 110s_f. Alternatively, oxygen can be supplied due to heat or the like applied during the manufacturing process of the transistor 100.

[0343] Oxygen can be supplied from the insulating film 110s_f to the conductive layer 114, for example, during heat treatment after the formation of the insulating film 110s_f, or during the formation of the insulating film 110s_f. Alternatively, oxygen can be supplied due to heat or the like applied during the manufacturing process of the transistor 100.

[0344] The sidewall of the conductive layer 114 is oxidized by oxygen supplied from the insulating film 110s_f and the like, and an insulating layer 110g is formed (FIG. 13C).

[0345] Further, oxidation treatment may be performed on the sidewalls of the openings of the conductive layer 114. For example, oxidation treatment can be performed before the formation of the insulating film 110s_f. As shown in FIG. 13D , after the conductive layer 112b_e having an opening, the insulating layer 110b having an opening (insulating layers 110b1, 110b2, and 110b3), and the conductive layer 114 having an opening are formed, oxidation treatment may be performed on the sidewalls of the openings of the conductive layer 114 before forming openings in the film that becomes the insulating layer 110a (insulating films 110a1_f, 110a2_f, and 110a3_f). For example, plasma treatment or the like can be used as the oxidation treatment. In FIG. 13D , the upper surface of the conductive layer 112a_1 is covered with the insulating film 110a1_f or the like during oxidation treatment, which can suppress oxidation of the conductive layer 112a_1 and the conductive layer 112a_2.

[0346] Although the above describes an example in which oxidation treatment such as plasma treatment is performed with the sidewalls of the openings of the conductive layer 114 exposed, the oxidation treatment may be performed after the step of forming the insulating film 110s_f shown in FIG. 13A is performed. Alternatively, the oxidation treatment may be performed after the insulating film 110s_f is formed and the insulating layer 110s is formed by anisotropic etching. When oxidation treatment is performed through the insulating film 110s_f or when oxidation treatment is performed through the insulating layer 110s, oxygen can be supplied to the insulating film 110s_f and the insulating layer 110s in addition to oxidizing the sidewalls of the conductive layer 114.

[0347] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0348] Embodiment 2 In this embodiment, a display device of one embodiment of the present invention will be described with reference to FIGS.

[0349] The display device of this embodiment can be a high-resolution display device or a large-sized display device. Therefore, the display device of this embodiment can be used in electronic devices having relatively large screens, such as television devices, desktop or notebook personal computers, computer monitors, digital signage, and large game machines such as pachinko machines, as well as in display units of digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and sound reproducing devices.

[0350] The display device of the present embodiment can be a high-definition display device, and can therefore be used as a display unit for information terminals (wearable devices) such as wristwatches and bracelets, as well as for wearable devices that can be worn on the head, such as VR devices such as head-mounted displays (HMDs) and AR devices such as glasses.

[0351] The semiconductor device of one embodiment of the present invention can be used for a display device or a module including the display device. Examples of the module including the display device include a module in which a connector such as a flexible printed circuit (hereinafter referred to as FPC) or a tape carrier package (TCP) is attached to the display device, and a module in which an integrated circuit (IC) is mounted by a chip-on-glass (COG) method, a chip-on-film (COF) method, or the like.

[0352] [Display Device 50A] FIG. 14 shows a perspective view of the display device 50A.

[0353] The display device 50A has a configuration in which a substrate 152 and a substrate 151 are bonded together. In Fig. 14, the substrate 152 is indicated by a dashed line.

[0354] The display device 50A has a display unit 168, a connection unit 140, a circuit unit 164, wiring 165, etc. Fig. 14 shows an example in which an IC 173 and an FPC 172 are mounted on the display device 50A. Therefore, the configuration shown in Fig. 14 can also be said to be a display module having the display device 50A, an IC, and an FPC.

[0355] The connection portion 140 is provided on the outside of the display portion 168. The connection portion 140 can be provided along one side or multiple sides of the display portion 168. The number of connection portions 140 may be single or multiple. FIG. 14 shows an example in which the connection portion 140 is provided so as to surround the four sides of the display portion. The connection portion 140 electrically connects the common electrode of the display element to the conductive layer, and can supply a potential to the common electrode.

[0356] The circuit portion 164 includes, for example, a scan line driver circuit (also referred to as a gate driver). Alternatively, the circuit portion 164 may include both a scan line driver circuit and a signal line driver circuit (also referred to as a source driver).

[0357] The wiring 165 has a function of supplying signals and power to the display portion 168 and the circuit portion 164. The signals and power are input to the wiring 165 from the outside via the FPC 172 or input to the wiring 165 from the IC 173.

[0358] 14 shows an example in which an IC 173 is provided on a substrate 151 by a COG method, a COF method, or the like. The IC 173 may be, for example, an IC having one or both of a scanning line driver circuit and a signal line driver circuit. The display device 50A and the display module may be configured without an IC. The IC may also be mounted on an FPC by a COF method, or the like.

[0359] A transistor of one embodiment of the present invention can be applied to, for example, one or both of the display portion 168 and the circuit portion 164 of the display device 50A.

[0360] For example, when the transistor of one embodiment of the present invention is applied to a pixel circuit of a display device, the area occupied by the pixel circuit can be reduced, resulting in a high-resolution display device. Furthermore, when the transistor of one embodiment of the present invention is applied to a driver circuit of a display device (e.g., one or both of a gate line driver circuit and a source line driver circuit), the area occupied by the driver circuit can be reduced, resulting in a display device with a narrow frame. Furthermore, since the transistor of one embodiment of the present invention has favorable electrical characteristics, its use in a display device can improve the reliability of the display device.

[0361] The display section 168 is an area in the display device 50A that displays an image, and has a plurality of periodically arranged pixels 210. Fig. 14 shows an enlarged view of one pixel 210.

[0362] The pixel arrangement in the display device of this embodiment is not particularly limited, and various methods can be applied, such as a stripe arrangement, an S-stripe arrangement, a matrix arrangement, a delta arrangement, a Bayer arrangement, and a pentile arrangement.

[0363] The pixel 210 shown in FIG. 14 has a sub-pixel 11R that emits red light, a sub-pixel 11G that emits green light, and a sub-pixel 11B that emits blue light.

[0364] Each of the sub-pixels 11R, 11G, and 11B includes a display element and a circuit that controls the driving of the display element.

[0365] Various elements can be used as the display element, including, for example, a liquid crystal element and a light-emitting element. Other examples include shutter-type or optical interference-type MEMS (Micro Electro Mechanical Systems) elements, display elements that employ a microcapsule method, an electrophoresis method, an electrowetting method, or an electronic liquid powder (registered trademark) method, etc. Furthermore, a QLED (Quantum-dot LED) that uses a light source and color conversion technology using quantum dot materials may also be used.

[0366] Examples of liquid crystal elements include transmissive liquid crystal elements, reflective liquid crystal elements, and semi-transmissive liquid crystal elements.

[0367] Examples of the light-emitting element include self-luminous light-emitting elements such as LEDs (Light Emitting Diodes), OLEDs (Organic LEDs), semiconductor lasers, etc. Examples of the LED that can be used include mini LEDs and micro LEDs.

[0368] Examples of light-emitting substances that the light-emitting element has include fluorescent substances (fluorescent materials), phosphorescent substances (phosphorescent materials), substances that exhibit thermally activated delayed fluorescence (thermally activated delayed fluorescence: TADF materials), and inorganic compounds (quantum dot materials, etc.).

[0369] The light-emitting element can emit light of infrared, red, green, blue, cyan, magenta, yellow, white, etc. Furthermore, the color purity can be improved by providing the light-emitting element with a microcavity structure.

[0370] One of a pair of electrodes included in the light-emitting element functions as an anode, and the other electrode functions as a cathode.

[0371] In this embodiment, a case where a light-emitting element is used as a display element will be mainly described as an example.

[0372] Note that the display device of one embodiment of the present invention may be any of a top-emission type that emits light in a direction opposite to a substrate on which a light-emitting element is formed, a bottom-emission type that emits light toward a substrate on which a light-emitting element is formed, and a dual-emission type that emits light to both sides.

[0373] Figure 15 shows an example of a cross section of the display device 50A when a portion of the area including the FPC 172, a portion of the circuit section 164, a portion of the display section 168, a portion of the connection section 140, and a portion of the area including the end portion are cut away.

[0374] 15 includes transistors 205D, 205R, 205G, and 205B, a light-emitting element 130R, a light-emitting element 130G, and a light-emitting element 130B between a substrate 151 and a substrate 152. The light-emitting element 130R is a display element included in the sub-pixel 11R that emits red light, the light-emitting element 130G is a display element included in the sub-pixel 11G that emits green light, and the light-emitting element 130B is a display element included in the sub-pixel 11B that emits blue light.

[0375] The display device 50A employs an SBS structure, which allows the materials and configuration to be optimized for each light-emitting element, increasing the degree of freedom in the selection of materials and configurations and facilitating improvements in brightness and reliability.

[0376] The display device 50A is a top-emission type, which allows transistors and the like to be arranged overlapping the light-emitting region of the light-emitting element, thereby enabling a higher pixel aperture ratio than a bottom-emission type.

[0377] The transistors 205D, 205R, 205G, and 205B are all formed on the substrate 151. These transistors can be manufactured using the same material and the same process.

[0378] In this embodiment, an example in which OS transistors are used as the transistors 205D, 205R, 205G, and 205B will be described. The transistors according to one embodiment of the present invention can be used as the transistors 205D, 205R, 205G, and 205B. That is, the display device 50A includes the transistor according to one embodiment of the present invention in both the display portion 168 and the circuit portion 164. By using the transistor according to one embodiment of the present invention in the display portion 168, the pixel size can be reduced, leading to higher resolution. Furthermore, by using the transistor according to one embodiment of the present invention in the circuit portion 164, the area occupied by the circuit portion 164 can be reduced, leading to a narrower frame. The description of the previous embodiment can be referred to for the transistor according to one embodiment of the present invention.

[0379] Specifically, the transistors 205D, 205R, 205G, and 205B each include a conductive layer 104 that functions as one of a first gate and a second gate, a conductive layer 114 that functions as the other of the first gate and the second gate, an insulating layer 106 that functions as a gate insulating layer, an insulating layer 110s that functions as a gate insulating layer, a conductive layer 112a that functions as one of a source and a drain, a conductive layer 112b that functions as the other of the source and the drain, and a semiconductor layer 108 having a metal oxide.

[0380] Note that the transistor included in the display device of this embodiment is not limited to the transistor of one embodiment of the present invention. For example, the display device may include a combination of the transistor of one embodiment of the present invention and a transistor having another structure.

[0381] The display device of this embodiment may include, for example, one or more of a planar transistor, a staggered transistor, and an inverted staggered transistor. The transistor included in the display device of this embodiment may be either a top-gate transistor or a bottom-gate transistor. Alternatively, gates may be provided above and below a semiconductor layer in which a channel is formed.

[0382] The display device of this embodiment mode may also include a transistor using silicon for a channel formation region (Si transistor).

[0383] Examples of silicon include single crystal silicon, polycrystalline silicon, and amorphous silicon. In particular, a transistor having an LTPS semiconductor layer (hereinafter also referred to as an LTPS transistor) can be used. The LTPS transistor has high field-effect mobility and favorable frequency characteristics.

[0384] To increase the emission luminance of a light-emitting element included in a pixel circuit, it is necessary to increase the amount of current flowing through the light-emitting element. To achieve this, it is necessary to increase the source-drain voltage of a driving transistor included in the pixel circuit. Since an OS transistor has a higher withstand voltage between its source and drain than a Si transistor, a high voltage can be applied between the source and drain of the OS transistor. Therefore, by using an OS transistor as the driving transistor included in a pixel circuit, it is possible to increase the amount of current flowing through the light-emitting element and increase the emission luminance of the light-emitting element.

[0385] Furthermore, when a transistor operates in a saturation region, an OS transistor can reduce the change in source-drain current with respect to a change in gate-source voltage compared to a Si transistor. Therefore, by using an OS transistor as a driving transistor included in a pixel circuit, the current flowing between the source and drain can be precisely controlled by changing the gate-source voltage, thereby controlling the amount of current flowing to a light-emitting element. This allows a pixel circuit to have a larger number of gray levels.

[0386] Furthermore, in terms of the saturation characteristics of the current that flows when a transistor operates in a saturation region, an OS transistor can pass a more stable current (saturation current) than a Si transistor, even when the source-drain voltage gradually increases. Therefore, by using an OS transistor as a driving transistor, a stable current can be passed to a light-emitting element, even when the current-voltage characteristics of the EL element vary. In other words, when an OS transistor operates in a saturation region, the source-drain current hardly changes even when the source-drain voltage is changed, thereby stabilizing the light-emitting luminance of the light-emitting element.

[0387] The transistors included in the circuit portion 164 and the transistors included in the display portion 168 may have the same structure or different structures. The transistors included in the circuit portion 164 may all have the same structure or may have two or more types. Similarly, the transistors included in the display portion 168 may all have the same structure or may have two or more types.

[0388] All the transistors included in the display portion 168 may be OS transistors, all the transistors included in the display portion 168 may be Si transistors, or some of the transistors included in the display portion 168 may be OS transistors and the rest may be Si transistors.

[0389] For example, by using both an LTPS transistor and an OS transistor in the display portion 168, a display device with low power consumption and high driving capability can be realized. A structure in which an LTPS transistor and an OS transistor are combined is sometimes referred to as LTPO. Note that a more preferable example is a structure in which an OS transistor is used as a transistor that functions as a switch for controlling conduction / non-conduction between wirings, and an LTPS transistor is used as a transistor for controlling current.

[0390] For example, one of the transistors included in the display portion 168 functions as a transistor for controlling a current flowing to a light-emitting element and can also be called a driving transistor. One of the source and drain of the driving transistor is electrically connected to a pixel electrode of the light-emitting element. The driving transistor is preferably an LTPS transistor. This can increase the current flowing to the light-emitting element in the pixel circuit.

[0391] On the other hand, another transistor included in the display portion 168 functions as a switch for controlling pixel selection / non-selection and can also be called a selection transistor. The gate of the selection transistor is electrically connected to a gate line, and one of the source and drain is electrically connected to a source line (signal line). An OS transistor is preferably used as the selection transistor. This allows the gradation of a pixel to be maintained even when the frame frequency is significantly reduced (for example, 1 fps or less), and therefore power consumption can be reduced by stopping the driver when displaying a still image.

[0392] An insulating layer 195 is provided to cover the transistors 205D, 205R, 205G, and 205B, and an insulating layer 235 is provided over the insulating layer 195 .

[0393] The insulating layer 195 preferably functions as a protective layer for the transistor. The insulating layer 195 is preferably made of a material through which impurities such as water and hydrogen are less likely to diffuse. This allows the insulating layer 195 to function as a barrier layer. With such a structure, diffusion of impurities from the outside into the transistor can be effectively suppressed, and the reliability of the display device can be improved.

[0394] The insulating layer 195 preferably has one or more inorganic insulating films. Examples of the inorganic insulating film include an insulating oxide film, an insulating nitride film, an insulating oxynitride film, and an insulating nitride oxide film. Specific examples of these inorganic insulating films are as described above.

[0395] The insulating layer 235 preferably functions as a planarization layer, and is preferably an organic insulating film. Materials that can be used for the organic insulating film include acrylic resin, polyimide resin, epoxy resin, polyamide resin, polyimideamide resin, siloxane resin, benzocyclobutene resin, phenolic resin, and precursors of these resins. The insulating layer 235 may also have a laminated structure of an organic insulating film and an inorganic insulating film. The outermost layer of the insulating layer 235 preferably functions as an etching protection layer. This prevents recesses from being formed in the insulating layer 235 during processing of the pixel electrodes 111R, 111G, 111B, etc. Alternatively, recesses may be formed in the insulating layer 235 during processing of the pixel electrodes 111R, 111G, 111B, etc.

[0396] On the insulating layer 235, the light emitting elements 130R, 130G, and 130B are provided.

[0397] The light-emitting element 130R has a pixel electrode 111R on the insulating layer 235, an EL layer 113R on the pixel electrode 111R, and a common electrode 135 on the EL layer 113R. The light-emitting element 130R shown in Fig. 15 emits red light (R). The EL layer 113R has a light-emitting layer that emits red light.

[0398] The light-emitting element 130G has a pixel electrode 111G on the insulating layer 235, an EL layer 113G on the pixel electrode 111G, and a common electrode 135 on the EL layer 113G. The light-emitting element 130G shown in Fig. 15 emits green light (G). The EL layer 113G has a light-emitting layer that emits green light.

[0399] The light-emitting element 130B has a pixel electrode 111B on the insulating layer 235, an EL layer 113B on the pixel electrode 111B, and a common electrode 135 on the EL layer 113B. The light-emitting element 130B shown in Fig. 15 emits blue light (B). The EL layer 113B has a light-emitting layer that emits blue light.

[0400] 15, the EL layers 113R, 113G, and 113B are all shown with the same film thickness, but this is not limited thereto. The EL layers 113R, 113G, and 113B may have different film thicknesses. For example, it is preferable to set the film thickness of each of the EL layers 113R, 113G, and 113B in accordance with the optical path length that intensifies the light emitted by each of the EL layers. This allows for a microcavity structure to be realized, and the color purity of the light emitted from each light-emitting element to be improved.

[0401] The pixel electrode 111R is electrically connected to the conductive layer 112b of the transistor 205R through openings provided in the insulating layer 106, the insulating layer 195, and the insulating layer 235. Similarly, the pixel electrode 111G is electrically connected to the conductive layer 112b of the transistor 205G, and the pixel electrode 111B is electrically connected to the conductive layer 112b of the transistor 205B.

[0402] Ends of the pixel electrodes 111R, 111G, and 111B are covered with an insulating layer 237. The insulating layer 237 functions as a partition wall (also referred to as a bank, spacer, or bank). The insulating layer 237 can be formed to have a single-layer structure or a stacked-layer structure using one or both of an inorganic insulating material and an organic insulating material. For example, the material that can be used for the insulating layer 195 and the material that can be used for the insulating layer 235 can be used for the insulating layer 237. The insulating layer 237 can electrically insulate the pixel electrode and the common electrode. Furthermore, the insulating layer 237 can electrically insulate adjacent light-emitting elements from each other.

[0403] The common electrode 135 is a continuous film provided in common to the light-emitting elements 130R, 130G, and 130B. The common electrode 135 shared by the plurality of light-emitting elements is electrically connected to a conductive layer 123 provided in the connection portion 140. The conductive layer 123 is preferably formed using the same material and in the same process as the pixel electrodes 111R, 111G, and 111B.

[0404] In a display device according to one embodiment of the present invention, a conductive film that transmits visible light is preferably used for the pixel electrode and the common electrode, which are electrodes from which light is extracted, and a conductive film that reflects visible light is preferably used for the electrode from which light is not extracted.

[0405] A conductive film that transmits visible light may also be used for the electrode on the side from which light is not extracted. In this case, it is preferable to place the electrode between the reflective layer and the EL layer. That is, the light emitted from the EL layer may be reflected by the reflective layer and extracted from the display device.

[0406] Materials for forming the pair of electrodes of the light-emitting element can include metals, alloys, electrically conductive compounds, and mixtures thereof. Specific examples of such materials include metals such as aluminum, magnesium, titanium, chromium, manganese, iron, cobalt, nickel, copper, gallium, zinc, indium, tin, molybdenum, tantalum, tungsten, palladium, gold, platinum, silver, yttrium, and neodymium, as well as alloys containing these metals in combination. Examples of such materials include indium tin oxide (In-Sn oxide, also referred to as ITO), In-Si-Sn oxide (also referred to as ITSO), indium zinc oxide (In-Zn oxide), and In-W-Zn oxide. Examples of such materials include aluminum-containing alloys (aluminum alloys), such as an alloy of aluminum, nickel, and lanthanum (Al-Ni-La), and silver-containing alloys, such as an alloy of silver and magnesium and an alloy of silver, palladium, and copper (Ag-Pd-Cu, also referred to as APC). Other examples of the material include elements belonging to Group 1 or 2 of the periodic table (e.g., lithium, cesium, calcium, and strontium) that are not listed above as examples, rare earth metals such as europium and ytterbium, alloys containing appropriate combinations of these, and graphene.

[0407] The light-emitting element preferably has a micro-optical resonator (microcavity) structure. Therefore, one of the pair of electrodes of the light-emitting element preferably has an electrode that is transparent and reflective to visible light (semi-transmissive / semi-reflective electrode), and the other preferably has an electrode that is reflective to visible light (reflective electrode). By having the light-emitting element have a microcavity structure, the light emitted from the light-emitting layer can be resonated between both electrodes, thereby intensifying the light emitted from the light-emitting element.

[0408] The light transmittance of the transparent electrode is 40% or more. For example, it is preferable to use an electrode having a visible light (light with a wavelength of 400 nm or more and less than 750 nm) transmittance of 40% or more for the transparent electrode of the light-emitting element. The visible light reflectance of the semi-transmissive / semi-reflective electrode is 10% or more and 95% or less, preferably 30% or more and 80% or less. The visible light reflectance of the reflective electrode is 40% or more and 100% or less, preferably 70% or more and 100% or less. Furthermore, the resistivity of these electrodes is 1×10 −２ Preferably, it is Ωcm or less.

[0409] The EL layers 113R, 113G, and 113B are each provided in an island shape. In FIG. 15 , the ends of adjacent EL layers 113R and 113G overlap, the ends of adjacent EL layers 113G and 113B overlap, and the ends of adjacent EL layers 113R and 113B overlap. When forming island-shaped EL layers using a fine metal mask, the ends of adjacent EL layers may overlap as shown in FIG. 15 , but this is not limited to this. In other words, adjacent EL layers may not overlap but may be spaced apart. Furthermore, the display device may have both overlapping portions between adjacent EL layers and portions between adjacent EL layers that do not overlap but are spaced apart.

[0410] Each of the EL layers 113R, 113G, and 113B includes at least a light-emitting layer. The light-emitting layer includes one or more light-emitting materials. As the light-emitting material, a material that emits light of a color such as blue, purple, blue-purple, green, yellow-green, yellow, orange, or red is appropriately used. Furthermore, a material that emits near-infrared light can also be used as the light-emitting material.

[0411] The light-emitting material may include a fluorescent material, a phosphorescent material, a TADF material, and a quantum dot material.

[0412] The light-emitting layer may contain one or more organic compounds (host materials, assist materials, etc.) in addition to a light-emitting substance (guest material). As the one or more organic compounds, one or both of a substance with high hole-transport properties (hole-transport material) and a substance with high electron-transport properties (electron-transport material) can be used. Furthermore, as the one or more organic compounds, a bipolar substance (a substance with high electron-transport properties and high hole-transport properties) or a TADF material can be used.

[0413] The light-emitting layer preferably includes, for example, a phosphorescent material and a hole-transporting material and an electron-transporting material, which are a combination that easily forms an exciplex. This configuration allows efficient emission using Exciplex-Triple Energy Transfer (ExTET), which is energy transfer from the exciplex to the light-emitting material (phosphorescent material). By selecting a combination that forms an exciplex that emits light that overlaps with the wavelength of the lowest-energy absorption band of the light-emitting material, energy transfer becomes smooth, allowing efficient emission. This configuration simultaneously enables high efficiency, low-voltage operation, and long life of the light-emitting element.

[0414] In addition to the light-emitting layer, the EL layer may include one or more of a layer containing a substance with high hole-injecting properties (hole-injecting layer), a layer containing a hole-transporting material (hole-transporting layer), a layer containing a substance with high electron-blocking properties (electron-blocking layer), a layer containing a substance with high electron-injecting properties (electron-injecting layer), a layer containing an electron-transporting material (electron-transporting layer), and a layer containing a substance with high hole-blocking properties (hole-blocking layer).In addition, the EL layer may include one or both of a bipolar material and a TADF material.

[0415] The light-emitting element can be made of either a low-molecular-weight compound or a high-molecular-weight compound, and may contain an inorganic compound. The layers constituting the light-emitting element can be formed by a method such as a vapor deposition method (including a vacuum vapor deposition method), a transfer method, a printing method, an inkjet method, or a coating method.

[0416] The light-emitting element may have a single structure (a structure having only one light-emitting unit) or a tandem structure (a structure having multiple light-emitting units). The light-emitting unit has at least one light-emitting layer. The tandem structure is a structure in which multiple light-emitting units are connected in series via a charge-generating layer. When a voltage is applied between a pair of electrodes, the charge-generating layer injects electrons into one of the two light-emitting units and holes into the other. The tandem structure allows the light-emitting element to emit light with high brightness. Furthermore, the tandem structure can reduce the current required to achieve the same brightness compared to a single structure, thereby improving reliability. The tandem structure may also be called a stack structure.

[0417] In Figure 15, when light-emitting elements with a tandem structure are used, it is preferable that the EL layer 113R has a structure having multiple light-emitting units that emit red light, the EL layer 113G has a structure having multiple light-emitting units that emit green light, and the EL layer 113B has a structure having multiple light-emitting units that emit blue light.

[0418] A protective layer 131 is provided on the light-emitting elements 130R, 130G, and 130B. The protective layer 131 and the substrate 152 are bonded via an adhesive layer 149. A light-shielding layer 117 is provided on the substrate 152. For example, a solid sealing structure or a hollow sealing structure can be applied to seal the light-emitting elements. In FIG. 15 , the space between the substrates 152 and 151 is filled with the adhesive layer 149, and a solid sealing structure is applied. Alternatively, the space may be filled with an inert gas (such as nitrogen or argon), and a hollow sealing structure may be applied. In this case, the adhesive layer 149 may be provided so as not to overlap with the light-emitting elements. Alternatively, the space may be filled with a resin different from the frame-shaped adhesive layer 149.

[0419] The protective layer 131 is preferably provided on at least the display unit 168, and is preferably provided so as to cover the entire display unit 168. The protective layer 131 is preferably provided so as to cover not only the display unit 168, but also the connection unit 140 and the circuit unit 164. The protective layer 131 is preferably provided up to the edge of the display device 50A. On the other hand, in the connection unit 204, the FPC 172 and the conductive layer 167 are electrically connected to each other, so that a portion where the protective layer 131 is not provided is generated.

[0420] By providing the protective layer 131 on the light emitting elements 130R, 130G, and 130B, the reliability of the light emitting elements can be improved.

[0421] The protective layer 131 may have a single layer structure or a stacked structure of two or more layers. The conductivity of the protective layer 131 does not matter. The protective layer 131 can be formed of at least one of an insulating film, a semiconductor film, and a conductive film.

[0422] The protective layer 131 has an inorganic film, which can prevent oxidation of the common electrode 135, prevent impurities (moisture, oxygen, etc.) from entering the light-emitting element, and so on, thereby suppressing deterioration of the light-emitting element and improving the reliability of the display device.

[0423] For the protective layer 131, for example, an inorganic insulating film such as an insulating oxide film, an insulating nitride film, an insulating oxynitride film, or an insulating nitride oxide film can be used. Specific examples of these inorganic insulating films are as described above. In particular, the protective layer 131 preferably includes an insulating nitride film or an insulating nitride oxide film, and more preferably includes an insulating nitride film.

[0424] Alternatively, an inorganic film containing ITO, In—Zn oxide, Ga—Zn oxide, Al—Zn oxide, IGZO, or the like may be used for the protective layer 131. The inorganic film preferably has high resistance, specifically, preferably has higher resistance than the common electrode 135. The inorganic film may further contain nitrogen.

[0425] When light emitted from the light-emitting element is extracted through the protective layer 131, it is preferable that the protective layer 131 has high transparency to visible light. For example, ITO, IGZO, and aluminum oxide are preferable because they are inorganic materials that have high transparency to visible light.

[0426] For example, a stacked structure of an aluminum oxide film and a silicon nitride film on the aluminum oxide film, or a stacked structure of an aluminum oxide film and an IGZO film on the aluminum oxide film can be used as the protective layer 131. By using such a stacked structure, impurities (water, oxygen, etc.) can be prevented from entering the EL layer side.

[0427] Furthermore, the protective layer 131 may have an organic film. For example, the protective layer 131 may have both an organic film and an inorganic film. Examples of organic films that can be used for the protective layer 131 include the organic insulating films that can be used for the insulating layer 235.

[0428] A connection portion 204 is provided in a region of the substrate 151 where the substrate 152 does not overlap. In the connection portion 204, a wiring 165 is electrically connected to the FPC 172 via conductive layers 166 and 167 and a connection layer 242. The wiring 165 has an example of a stacked structure of a conductive film obtained by processing the same conductive film as the conductive layer 112a_1 and a conductive film obtained by processing the same conductive film as the conductive layer 112a_2. The conductive layer 166 has an example of a single-layer structure of a conductive layer obtained by processing the same conductive film as the conductive layer 112b. The conductive layer 167 has an example of a single-layer structure of a conductive layer obtained by processing the same conductive film as the pixel electrodes 111R, 111G, and 111B. The conductive layer 167 is exposed on the top surface of the connection portion 204. This allows the connection portion 204 and the FPC 172 to be electrically connected via the connection layer 242.

[0429] The display device 50A is a top-emission type. Light emitted by the light-emitting elements is emitted toward the substrate 152. The substrate 152 is preferably made of a material that is highly transparent to visible light. The pixel electrodes 111R, 111G, and 111B contain a material that reflects visible light, and the counter electrode (common electrode 135) contains a material that transmits visible light.

[0430] It is preferable to provide a light-shielding layer 117 on the surface of the substrate 152 facing the substrate 151. The light-shielding layer 117 can be provided between adjacent light-emitting elements, in the connection section 140, in the circuit section 164, and the like.

[0431] Furthermore, a colored layer such as a color filter may be provided on the surface of the substrate 152 on the substrate 151 side or on the protective layer 131. When a color filter is provided over the light-emitting element, the color purity of light emitted from the pixel can be increased.

[0432] Various optical members can be disposed on the outer side of the substrate 152 (the surface opposite to the substrate 151). Examples of optical members include a polarizing plate, a retardation plate, a light diffusion layer (such as a diffusion film), an anti-reflection layer, and a light-collecting film. Furthermore, a surface protection layer such as an anti-static film that suppresses the adhesion of dust, a water-repellent film that makes it difficult for dirt to adhere, a hard coat film that suppresses the occurrence of scratches during use, or an impact absorbing layer may be disposed on the outer side of the substrate 152. For example, a glass layer or a silica layer (SiO ｘ The surface protection layer can be preferably formed of a material such as DLC (diamond-like carbon), aluminum oxide (AlO ｘ ), polyester-based materials, or polycarbonate-based materials may also be used. Note that it is preferable to use a material with high transmittance to visible light for the surface protection layer. It is also preferable to use a material with high hardness for the surface protection layer.

[0433] The substrate 151 and the substrate 152 can each be made of glass, quartz, ceramic, sapphire, resin, metal, alloy, semiconductor, or the like. A material that transmits light is used for the substrate on the side from which light from the light-emitting element is extracted. When a flexible material is used for the substrate 151 and the substrate 152, the flexibility of the display device can be increased, and a flexible display can be realized. Furthermore, a polarizing plate may be used for at least one of the substrates 151 and 152.

[0434] Substrates 151 and 152 may each be made of polyester resin such as polyethylene terephthalate (PET) or polyethylene naphthalate (PEN), polyacrylonitrile resin, acrylic resin, polyimide resin, polymethyl methacrylate resin, polycarbonate (PC) resin, polyethersulfone (PES) resin, polyamide resin (nylon, aramid, etc.), polysiloxane resin, cycloolefin resin, polystyrene resin, polyamideimide resin, polyurethane resin, polyvinyl chloride resin, polyvinylidene chloride resin, polypropylene resin, polytetrafluoroethylene (PTFE) resin, ABS resin, cellulose nanofiber, etc. At least one of substrates 151 and 152 may be made of glass having a thickness sufficient to provide flexibility.

[0435] When a circularly polarizing plate is superimposed on a display device, it is preferable that the display device has a substrate with high optical isotropy. A substrate with high optical isotropy has low birefringence (it can also be said that the amount of birefringence is small). Examples of films with high optical isotropy include triacetyl cellulose (TAC, also known as cellulose triacetate) films, cycloolefin polymer (COP) films, cycloolefin copolymer (COC) films, and acrylic films.

[0436] The adhesive layer 149 can be made of various curable adhesives, such as a photo-curable adhesive (e.g., an ultraviolet curable adhesive), a reactive curable adhesive, a thermosetting adhesive, or an anaerobic adhesive. Examples of such adhesives include epoxy resin, acrylic resin, silicone resin, phenolic resin, polyimide resin, imide resin, PVC (polyvinyl chloride) resin, PVB (polyvinyl butyral) resin, and EVA (ethylene vinyl acetate) resin. In particular, a material with low moisture permeability, such as epoxy resin, is preferable. Alternatively, a two-component resin may be used. Alternatively, an adhesive sheet or the like may be used.

[0437] The connection layer 242 may be an anisotropic conductive film (ACF), an anisotropic conductive paste (ACP), or the like.

[0438] 16 is different from the display device 50A mainly in that a light-emitting element having a common EL layer 113 and a colored layer (such as a color filter) are used for each subpixel of each color. Note that in the following description of the display device, descriptions of parts that are the same as those of the display devices described above may be omitted.

[0439] The display device 50B shown in Figure 16 has, between the substrate 151 and the substrate 152, transistors 205D, 205R, 205G, and 205B, light-emitting elements 130R, 130G, and 130B, a colored layer 132R that transmits red light, a colored layer 132G that transmits green light, and a colored layer 132B that transmits blue light.

[0440] The light emitting element 130R has a pixel electrode 111R, an EL layer 113 on the pixel electrode 111R, and a common electrode 135 on the EL layer 113. Light emitted from the light emitting element 130R is extracted as red light to the outside of the display device 50B via the colored layer 132R.

[0441] The light emitting element 130G has a pixel electrode 111G, an EL layer 113 on the pixel electrode 111G, and a common electrode 135 on the EL layer 113. Light emitted from the light emitting element 130G is extracted as green light to the outside of the display device 50B via the colored layer 132G.

[0442] The light emitting element 130B has a pixel electrode 111B, an EL layer 113 on the pixel electrode 111B, and a common electrode 135 on the EL layer 113. Light emitted from the light emitting element 130B is extracted as blue light to the outside of the display device 50B via the colored layer 132B.

[0443] The light-emitting elements 130R, 130G, and 130B each share an EL layer 113 and a common electrode 135. A configuration in which the EL layer 113 is common to the subpixels of each color can reduce the number of manufacturing steps compared to a configuration in which different EL layers are provided for the subpixels of each color.

[0444] For example, the light emitting elements 130R, 130G, and 130B shown in Fig. 16 emit white light. The white light emitted from the light emitting elements 130R, 130G, and 130B passes through the colored layers 132R, 132G, and 132B, thereby obtaining light of a desired color.

[0445] A light-emitting element that emits white light preferably includes two or more light-emitting layers. When two light-emitting layers are used to obtain white light emission, light-emitting layers may be selected such that the emission colors of the two light-emitting layers have a complementary color relationship. For example, by making the emission color of the first light-emitting layer and the emission color of the second light-emitting layer have a complementary color relationship, a configuration in which the light-emitting element as a whole emits white light can be obtained. Furthermore, when three or more light-emitting layers are used to obtain white light emission, the emission colors of the three or more light-emitting layers may be combined to form a configuration in which the light-emitting element as a whole emits white light.

[0446] The EL layer 113 preferably includes, for example, a light-emitting layer having a light-emitting substance that emits blue light and a light-emitting layer having a light-emitting substance that emits visible light with a wavelength longer than blue. The EL layer 113 preferably includes, for example, a light-emitting layer that emits yellow light and a light-emitting layer that emits blue light. Alternatively, the EL layer 113 preferably includes, for example, a light-emitting layer that emits red light, a light-emitting layer that emits green light, and a light-emitting layer that emits blue light.

[0447] A tandem structure is preferably used for the light-emitting element emitting white light. Specifically, a two-stage tandem structure having a light-emitting unit that emits yellow light and a light-emitting unit that emits blue light, a two-stage tandem structure having a light-emitting unit that emits red and green light and a light-emitting unit that emits blue light, a three-stage tandem structure having a light-emitting unit that emits blue light, a light-emitting unit that emits yellow, yellow-green, or green light, and a light-emitting unit that emits blue light, in this order, or a three-stage tandem structure having a light-emitting unit that emits blue light, a light-emitting unit that emits yellow, yellow-green, or green light, and red light, and a light-emitting unit that emits blue light, in this order, or the like can be applied. For example, the number of layers of the light-emitting units and the order of the colors can be, from the anode side, a two-layer structure of B and Y, a two-layer structure of B and light-emitting unit X, a three-layer structure of B, Y, and B, and the number of layers of the light-emitting layers in light-emitting unit X and the order of the colors can be, from the anode side, a two-layer structure of R and Y, a two-layer structure of R and G, a two-layer structure of G and R, a three-layer structure of G, R, and G, or a three-layer structure of R, G, and R. Furthermore, another layer can be provided between the two light-emitting layers.

[0448] Alternatively, for example, the light-emitting elements 130R, 130G, and 130B shown in FIG. 16 emit blue light. In this case, the EL layer 113 includes one or more light-emitting layers that emit blue light. In the sub-pixel 11B that emits blue light, the blue light emitted by the light-emitting element 130B can be extracted. Furthermore, in the sub-pixel 11R that emits red light and the sub-pixel 11G that emits green light, a color conversion layer can be provided between the light-emitting element 130R or light-emitting element 130G and the substrate 152 to convert the blue light emitted by the light-emitting element 130R or light-emitting element 130G into light with a longer wavelength, thereby extracting red or green light. Furthermore, it is preferable to provide a coloring layer 132R between the color conversion layer and the substrate 152 on the light-emitting element 130R, and a coloring layer 132G between the color conversion layer and the substrate 152 on the light-emitting element 130G. A portion of the light emitted by the light-emitting element may be transmitted directly without being converted by the color conversion layer. By extracting the light transmitted through the color conversion layer via the colored layer, light other than the desired color can be absorbed by the colored layer, thereby increasing the color purity of the light emitted by the sub-pixel.

[0449] [Display Device 50C] A display device 50C shown in FIG. 17 differs from the display device 50B mainly in that it is a bottom-emission display device.

[0450] Light emitted from the light-emitting element is emitted toward the substrate 151. A material that is highly transparent to visible light is preferably used for the substrate 151. On the other hand, the light-transmitting property of a material used for the substrate 152 does not matter.

[0451] 17 shows an example in which the light-shielding layer 117 is provided over the substrate 151, the insulating layer 153 is provided over the light-shielding layer 117, and the transistors 205D, 205R (not shown), 205G, and 205B are provided over the insulating layer 153. In addition, the coloring layer 132R (not shown), the coloring layer 132G, and the coloring layer 132B are provided over the insulating layer 195, and the insulating layer 235 is provided over the coloring layer 132R (not shown), the coloring layer 132G, and the coloring layer 132B.

[0452] The light emitting element 130G overlapping the colored layer 132G includes a pixel electrode 111G, an EL layer 113, and a common electrode 135.

[0453] The light emitting element 130B overlapping the colored layer 132B has a pixel electrode 111B, an EL layer 113 and a common electrode 135.

[0454] The pixel electrodes 111G and 111B are each made of a material that is highly transparent to visible light. It is preferable to use a material that reflects visible light for the common electrode 135. In a bottom-emission display device, a low-resistance metal or the like can be used for the common electrode 135, which can suppress voltage drops caused by the resistance of the common electrode 135 and achieve high display quality.

[0455] The transistor of one embodiment of the present invention can be miniaturized and its occupation area can be reduced; therefore, in a bottom-emission display device, the aperture ratio of a pixel can be increased or the pixel size can be reduced.

[0456] [Display Device 50D] A display device 50D shown in FIG. 18 differs from the display device 50A mainly in that it has a light receiving element 130S.

[0457] The display device 50D has a light-emitting element and a light-receiving element in each pixel. In the display device 50D, it is preferable to use an organic EL element as the light-emitting element and an organic photodiode as the light-receiving element. The organic EL element and the organic photodiode can be formed on the same substrate. Therefore, an organic photodiode can be built into a display device using an organic EL element.

[0458] In the display device 50D, in which pixels have a light-emitting element and a light-receiving element, the pixels have a light-receiving function, so that it is possible to detect contact or proximity of an object while displaying an image. Therefore, the display unit 168 has one or both of an imaging function and a sensing function in addition to an image display function. For example, in addition to displaying an image using all of the sub-pixels of the display device 50D, it is also possible for some sub-pixels to emit light as a light source, other sub-pixels to perform light detection, and the remaining sub-pixels to display an image.

[0459] Therefore, there is no need to provide a light receiving unit and a light source separately from the display device 50D, and the number of components in the electronic device can be reduced. For example, there is no need to provide a separate biometric authentication device or a capacitive touch panel for scrolling, etc. Therefore, by using the display device 50D, it is possible to provide an electronic device with reduced manufacturing costs.

[0460] When a light receiving element is used as an image sensor, the display device 50D can capture an image using the light receiving element. For example, the image sensor can capture an image for personal authentication using a fingerprint, palm print, iris, pulse shape (including vein shape and artery shape), face, or the like.

[0461] The light receiving element can be used as a touch sensor (also called a direct touch sensor) or a non-contact sensor (also called a hover sensor, hover touch sensor, or touchless sensor). A touch sensor can detect an object (such as a finger, hand, or pen) when the object comes into direct contact with the display device. A non-contact sensor can detect an object without the object touching the display device.

[0462] The light receiving element 130S has a pixel electrode 111S on an insulating layer 235, a functional layer 113S on the pixel electrode 111S, and a common electrode 135 on the functional layer 113S. Light Lin is incident on the functional layer 113S from outside the display device 50D.

[0463] The pixel electrode 111S is electrically connected to the conductive layer 112b of the transistor 205S through openings provided in the insulating layer 106, the insulating layer 195, and the insulating layer 235.

[0464] The end of the pixel electrode 111S is covered with an insulating layer 237.

[0465] The common electrode 135 is a continuous film commonly provided to the light-receiving element 130S, the light-emitting element 130R (not shown), the light-emitting element 130G, and the light-emitting element 130B. The common electrode 135 shared by the light-emitting element and the light-receiving element is electrically connected to the conductive layer 123 provided in the connection portion 140. The light-shielding layer 117 is provided between two adjacent light-emitting elements and between adjacent light-emitting elements and light-receiving elements. As shown in FIG. 18 , the spacing W1 between the light-shielding layers 117 provided in the region adjacent to the light-receiving element may be narrower than the spacing W2 between the light-shielding layers 117 provided in the region adjacent to the light-emitting element. Narrowing the spacing between the light-shielding layers can, for example, reduce noise in the light-receiving element. Furthermore, widening the spacing between the light-shielding layers can, for example, increase brightness by not blocking light emitted from the light-emitting element.

[0466] The functional layer 113S has at least an active layer (also referred to as a photoelectric conversion layer). The active layer includes a semiconductor. Examples of the semiconductor include inorganic semiconductors such as silicon and organic semiconductors including organic compounds. In this embodiment, an example in which an organic semiconductor is used as the semiconductor included in the active layer is shown. Using an organic semiconductor is preferable because the light-emitting layer and the active layer can be formed by the same method (for example, vacuum deposition), allowing common use of manufacturing equipment.

[0467] The functional layer 113S may further include a layer containing a substance with high hole transport properties, a substance with high electron transport properties, or a bipolar substance (a substance with high electron transport properties and high hole transport properties) as a layer other than the active layer. Furthermore, without being limited to the above, the functional layer 113S may further include a layer containing a substance with high hole injection properties, a hole blocking material, a material with high electron injection properties, or an electron blocking material. For the layer other than the active layer of the light-receiving element, for example, the materials that can be used for the light-emitting element described above can be used.

[0468] The light-receiving element can be made of either a low-molecular-weight compound or a high-molecular-weight compound, and may contain an inorganic compound. The layers constituting the light-receiving element can be formed by a method such as vapor deposition (including vacuum vapor deposition), transfer, printing, inkjet printing, or coating.

[0469] 19 is an example of a display device employing an MML (metal maskless) structure. That is, the display device 50E has light-emitting elements fabricated without using a fine metal mask. The stacked structures from the substrate 151 to the insulating layer 235 and from the protective layer 131 to the substrate 152 are similar to those of the display device 50A, and therefore will not be described here.

[0470] In FIG. 19, light emitting elements 130 R, 130 G, and 130 B are provided on an insulating layer 235 .

[0471] The light-emitting element 130R includes a conductive layer 124R on the insulating layer 235, a conductive layer 126R on the conductive layer 124R, a layer 133R on the conductive layer 126R, a common layer 134 on the layer 133R, and a common electrode 135 on the common layer 134. The light-emitting element 130R shown in FIG. 19 emits red light (R). The layer 133R includes a light-emitting layer that emits red light. In the light-emitting element 130R, the layer 133R and the common layer 134 can be collectively referred to as an EL layer. One or both of the conductive layer 124R and the conductive layer 126R can be referred to as a pixel electrode.

[0472] The light-emitting element 130G includes a conductive layer 124G on the insulating layer 235, a conductive layer 126G on the conductive layer 124G, a layer 133G on the conductive layer 126G, a common layer 134 on the layer 133G, and a common electrode 135 on the common layer 134. The light-emitting element 130G shown in FIG. 19 emits green light (G). The layer 133G includes a light-emitting layer that emits green light. In the light-emitting element 130G, the layer 133G and the common layer 134 can be collectively referred to as an EL layer. One or both of the conductive layer 124G and the conductive layer 126G can be referred to as a pixel electrode.

[0473] The light-emitting element 130B has a conductive layer 124B on the insulating layer 235, a conductive layer 126B on the conductive layer 124B, a layer 133B on the conductive layer 126B, a common layer 134 on the layer 133B, and a common electrode 135 on the common layer 134. The light-emitting element 130B shown in FIG. 19 emits blue light (B). The layer 133B has a light-emitting layer that emits blue light. In the light-emitting element 130B, the layer 133B and the common layer 134 can be collectively referred to as an EL layer. Furthermore, one or both of the conductive layer 124B and the conductive layer 126B can be referred to as a pixel electrode.

[0474] In this specification and the like, among the EL layers included in the light-emitting elements, a layer provided in an island shape for each light-emitting element is referred to as a layer 133B, a layer 133G, or a layer 133R, and a layer shared by a plurality of light-emitting elements is referred to as a common layer 134. Note that in this specification and the like, the layer 133R, the layer 133G, and the layer 133B may be referred to as an island-shaped EL layer, an EL layer formed in an island shape, or the like, without including the common layer 134.

[0475] The layers 133R, 133G, and 133B are spaced apart from one another. By providing an island-shaped EL layer for each light-emitting element, leakage current between adjacent light-emitting elements can be suppressed. This prevents crosstalk caused by unintended light emission, and realizes a display device with extremely high contrast.

[0476] 19, the layers 133R, 133G, and 133B are all shown to have the same thickness, but this is not limitative and the layers 133R, 133G, and 133B may have different thicknesses.

[0477] The conductive layer 124R is electrically connected to the conductive layer 112b of the transistor 205R through openings provided in the insulating layer 106, the insulating layer 195, and the insulating layer 235. Similarly, the conductive layer 124G is electrically connected to the conductive layer 112b of the transistor 205G, and the conductive layer 124B is electrically connected to the conductive layer 112b of the transistor 205B.

[0478] The conductive layers 124R, 124G, and 124B are formed so as to cover the openings provided in the insulating layer 235. A layer 128 is buried in the recesses of the conductive layers 124R, 124G, and 124B, respectively.

[0479] The layer 128 has a function of planarizing the recesses of the conductive layers 124R, 124G, and 124B. Conductive layers 126R, 126G, and 126B, which are electrically connected to the conductive layers 124R, 124G, and 124B, are provided on the conductive layers 124R, 124G, and 124B and the layer 128. Therefore, the regions overlapping with the recesses of the conductive layers 124R, 124G, and 124B can also be used as light-emitting regions, thereby increasing the aperture ratio of the pixel. It is preferable to use a conductive layer that functions as a reflective electrode for the conductive layers 124R and 126R.

[0480] The layer 128 may be an insulating layer or a conductive layer. Various inorganic insulating materials, organic insulating materials, and conductive materials can be used as appropriate for the layer 128. In particular, the layer 128 is preferably formed using an insulating material, and more preferably using an organic insulating material. For example, the organic insulating material that can be used for the insulating layer 237 described above can be used for the layer 128.

[0481] 19 shows an example in which the top surface of layer 128 has a flat portion, but there are no particular limitations on the shape of layer 128. The top surface of layer 128 may have at least one of a convex curved surface, a concave curved surface, and a flat surface.

[0482] Furthermore, the height of the upper surface of layer 128 and the height of the upper surface of conductive layer 124R may be the same or approximately the same, or may be different from each other. For example, the height of the upper surface of layer 128 may be lower or higher than the height of the upper surface of conductive layer 124R.

[0483] The edge of the conductive layer 126R may be flush with the edge of the conductive layer 124R, or may cover the side surface of the edge of the conductive layer 124R. The edges of the conductive layer 124R and the conductive layer 126R preferably have a tapered shape. Specifically, the edges of the conductive layer 124R and the conductive layer 126R preferably have a tapered shape with a taper angle of less than 90°. When the edge of the pixel electrode has a tapered shape, the layer 133R provided along the side surface of the pixel electrode also has a tapered shape. By tapering the side surface of the pixel electrode, the coverage of the EL layer provided along the side surface of the pixel electrode can be improved.

[0484] The conductive layers 124G, 126G and the conductive layers 124B, 126B are similar to the conductive layers 124R, 126R, and therefore detailed description thereof will be omitted.

[0485] The upper surface and side surfaces of the conductive layer 126R are covered with the layer 133R. Similarly, the upper surface and side surfaces of the conductive layer 126G are covered with the layer 133G, and the upper surface and side surfaces of the conductive layer 126B are covered with the layer 133B. Therefore, the entire region where the conductive layers 126R, 126G, and 126B are provided can be used as the light-emitting region of the light-emitting elements 130R, 130G, and 130B, thereby increasing the aperture ratio of the pixel.

[0486] Part of the top surface and side surfaces of each of the layers 133R, 133G, and 133B are covered with insulating layers 125 and 127. A common layer 134 is provided on the layers 133R, 133G, 133B, and insulating layers 125 and 127, and a common electrode 135 is provided on the common layer 134. The common layer 134 and the common electrode 135 are each a continuous film provided in common to a plurality of light-emitting elements.

[0487] 19, the insulating layer 237 shown in FIG. 15 and other figures is not provided between the conductive layer 126R and the layer 133R. In other words, the display device 50E does not have an insulating layer (also called a partition, bank, spacer, or the like) that is in contact with the pixel electrode and covers the upper edge of the pixel electrode. Therefore, the distance between adjacent light-emitting elements can be made extremely narrow. This allows a high-definition or high-resolution display device to be obtained. Furthermore, a mask for forming the insulating layer is not required, thereby reducing the manufacturing cost of the display device.

[0488] As described above, the layers 133R, 133G, and 133B each have a light-emitting layer. The layers 133R, 133G, and 133B each preferably have a light-emitting layer and a carrier transport layer (electron transport layer or hole transport layer) on the light-emitting layer. Alternatively, the layers 133R, 133G, and 133B each preferably have a light-emitting layer and a carrier block layer (hole block layer or electron block layer) on the light-emitting layer. Alternatively, the layers 133R, 133G, and 133B each preferably have a light-emitting layer, a carrier block layer on the light-emitting layer, and a carrier transport layer on the carrier block layer. Because the surfaces of the layers 133R, 133G, and 133B are exposed during the manufacturing process of the display device, providing one or both of a carrier transport layer and a carrier block layer on the light-emitting layer can prevent the light-emitting layer from being exposed to the outermost surface and reduce damage to the light-emitting layer. This can improve the reliability of the light-emitting element.

[0489] The common layer 134 includes, for example, an electron injection layer or a hole injection layer. Alternatively, the common layer 134 may include a stack of an electron transport layer and an electron injection layer, or a stack of a hole transport layer and a hole injection layer. The common layer 134 is shared by the light-emitting elements 130R, 130G, and 130B.

[0490] The side surfaces of the layers 133R, 133G, and 133B are covered with the insulating layer 125. The insulating layer 127 covers the side surfaces of the layers 133R, 133G, and 133B with the insulating layer 125 interposed therebetween.

[0491] The side surfaces (and even part of the upper surfaces) of the layers 133R, 133G, and 133B are covered with at least one of the insulating layer 125 and the insulating layer 127, which prevents the common layer 134 (or the common electrode 135) from coming into contact with the pixel electrodes and the side surfaces of the layers 133R, 133G, and 133B, thereby preventing short circuits in the light-emitting elements, thereby improving the reliability of the light-emitting elements.

[0492] The insulating layer 125 is preferably in contact with each side surface of the layer 133R, the layer 133G, and the layer 133B. By configuring the insulating layer 125 to be in contact with the layer 133R, the layer 133G, and the layer 133B, peeling of the layer 133R, the layer 133G, and the layer 133B can be prevented, and the reliability of the light-emitting element can be improved.

[0493] The insulating layer 127 is provided on the insulating layer 125 so as to fill the recesses in the insulating layer 125. The insulating layer 127 preferably covers at least a part of the side surface of the insulating layer 125.

[0494] By providing the insulating layers 125 and 127, the gaps between adjacent island-shaped layers can be filled, which reduces the extreme unevenness of the surface on which layers (e.g., the carrier injection layer, the common electrode, etc.) are formed on the island-shaped layers, thereby making the surface flatter, thereby improving the coverage of the carrier injection layer, the common electrode, etc.

[0495] The common layer 134 and the common electrode 135 are provided over the layer 133R, the layer 133G, the layer 133B, the insulating layer 125, and the insulating layer 127. Before the insulating layer 125 and the insulating layer 127 are provided, a step is generated between a region where the pixel electrode and the island-shaped EL layer are provided and a region where the pixel electrode and the island-shaped EL layer are not provided (a region between light-emitting elements). In the display device of one embodiment of the present invention, the insulating layer 125 and the insulating layer 127 can flatten the step, thereby improving the coverage of the common layer 134 and the common electrode 135. Therefore, poor connection due to disconnection of the step can be suppressed. Furthermore, the step can be suppressed from locally thinning the common electrode 135, thereby suppressing an increase in electrical resistance.

[0496] The upper surface of the insulating layer 127 preferably has a highly flat shape. The upper surface of the insulating layer 127 may have at least one of a flat surface, a convex curved surface, and a concave curved surface. For example, the upper surface of the insulating layer 127 preferably has a highly flat, smooth convex curved surface shape.

[0497] The insulating layer 125 can be an insulating layer containing an inorganic material. For example, an inorganic insulating film such as an insulating oxide film, a nitride insulating film, an oxynitride insulating film, or a nitride oxide insulating film can be used for the insulating layer 125. Specific examples of these inorganic insulating films are as described above. The insulating layer 125 may have a single-layer structure or a stacked-layer structure. Aluminum oxide is particularly preferable because it has a high etching selectivity with respect to the EL layer and protects the EL layer in the formation of the insulating layer 127 described later. By using an inorganic insulating film such as an aluminum oxide film, a hafnium oxide film, or a silicon oxide film formed by an ALD method as the insulating layer 125, the insulating layer 125 can be formed with fewer pinholes and excellent protection of the EL layer. The insulating layer 125 may also have a stacked-layer structure of a film formed by an ALD method and a film formed by a sputtering method. For example, the insulating layer 125 may have a stacked-layer structure of an aluminum oxide film formed by an ALD method and a silicon nitride film formed by a sputtering method.

[0498] The insulating layer 125 preferably functions as a barrier insulating layer against at least one of water and oxygen. The insulating layer 125 preferably has a function of suppressing diffusion of at least one of water and oxygen. The insulating layer 125 preferably has a function of capturing or fixing (also referred to as gettering) at least one of water and oxygen.

[0499] In this specification and the like, a barrier insulating layer refers to an insulating layer having barrier properties. In addition, in this specification and the like, the barrier properties refer to a function of suppressing the diffusion of a corresponding substance (also referred to as low permeability) or a function of capturing or fixing (also referred to as gettering) a corresponding substance.

[0500] The insulating layer 125 has a function as a barrier insulating layer or a gettering function, which can suppress the intrusion of impurities (typically, at least one of water and oxygen) that may diffuse into each light-emitting element from the outside. With this structure, a highly reliable light-emitting element and a highly reliable display device can be provided.

[0501] The insulating layer 125 preferably has a low impurity concentration. This can prevent impurities from entering the EL layer from the insulating layer 125 and causing deterioration of the EL layer. Furthermore, a low impurity concentration in the insulating layer 125 can improve the barrier properties against at least one of water and oxygen. For example, it is desirable that the insulating layer 125 has a sufficiently low hydrogen concentration or a sufficiently low carbon concentration, or preferably both of them.

[0502] The insulating layer 127 provided on the insulating layer 125 has the function of flattening the extreme unevenness of the insulating layer 125 formed between adjacent light-emitting elements. In other words, the presence of the insulating layer 127 has the effect of improving the flatness of the surface on which the common electrode 135 is formed.

[0503] An insulating layer containing an organic material can be suitably used as the insulating layer 127. As the organic material, a photosensitive organic resin is preferably used, for example, a photosensitive resin composition containing an acrylic resin is preferably used. Note that in this specification and the like, the term "acrylic resin" does not refer only to polymethacrylic acid ester or methacrylic resin, but may refer to all acrylic polymers in a broad sense.

[0504] The insulating layer 127 may also be made of acrylic resin, polyimide resin, epoxy resin, imide resin, polyamide resin, polyimideamide resin, silicone resin, siloxane resin, benzocyclobutene-based resin, phenolic resin, or precursors of these resins. The insulating layer 127 may also be made of organic materials such as polyvinyl alcohol (PVA), polyvinyl butyral, polyvinylpyrrolidone, polyethylene glycol, polyglycerin, pullulan, water-soluble cellulose, or alcohol-soluble polyamide resin. The photosensitive resin may also be a photoresist. Either a positive-type material or a negative-type material may be used as the photosensitive organic resin.

[0505] The insulating layer 127 may be made of a material that absorbs visible light. The insulating layer 127 absorbs light emitted from the light-emitting element, thereby suppressing leakage of light from the light-emitting element to an adjacent light-emitting element through the insulating layer 127 (stray light). This can improve the display quality of the display device. Furthermore, since the display quality can be improved without using a polarizing plate in the display device, the display device can be made lighter and thinner.

[0506] Examples of materials that absorb visible light include materials containing pigments such as black, materials containing dyes, light-absorbing resin materials (e.g., polyimide), and resin materials that can be used for color filters (color filter materials). In particular, using a resin material in which two or more color filter materials are laminated or mixed is preferable because it can enhance the visible light blocking effect. In particular, mixing three or more color filter materials makes it possible to form a black or nearly black resin layer.

[0507] The transistor of one embodiment of the present invention can be miniaturized and its occupation area can be reduced; therefore, in a bottom-emission display device, the aperture ratio of a pixel can be increased or the pixel size can be reduced.

[0508] [Example of a Method for Manufacturing a Display Device] A method for manufacturing a display device using an MML (metal maskless) structure will be described below with reference to Fig. 20. Here, a process for manufacturing light-emitting elements without using a fine metal mask will be described in detail. Fig. 20 shows cross-sectional views of three light-emitting elements and a connection portion 140 included in a display unit 168 at each step.

[0509] The light-emitting element can be fabricated using vacuum processes such as vapor deposition, and solution processes such as spin coating and inkjet printing. Vapor deposition methods include physical vapor deposition (PVD) methods such as sputtering, ion plating, ion beam deposition, molecular beam deposition, and vacuum deposition, and chemical vapor deposition (CVD). In particular, functional layers included in the EL layer (hole injection layer, hole transport layer, hole blocking layer, light-emitting layer, electron blocking layer, electron transport layer, electron injection layer, charge generation layer, etc.) can be formed by vapor deposition (vacuum deposition, etc.), coating methods (dip coating, die coating, bar coating, spin coating, spray coating, etc.), printing methods (inkjet printing, screen (stencil printing), offset (lithographic printing), flexography (relief printing), gravure printing, microcontact printing, etc.), etc.

[0510] The island-shaped layer (layer including the light-emitting layer) manufactured by the manufacturing method of the display device described below is not formed using a fine metal mask, but is formed by forming the light-emitting layer on the entire surface and then processing it using photolithography. Therefore, it is possible to realize a high-definition display device or a display device with a high aperture ratio, which has been difficult to achieve until now. Furthermore, since the light-emitting layer can be made separately for each color, it is possible to realize a display device that is extremely vivid, has high contrast, and has high display quality. Furthermore, by providing a sacrificial layer on the light-emitting layer, damage to the light-emitting layer during the manufacturing process of the display device can be reduced, thereby improving the reliability of the light-emitting element.

[0511] For example, if a display device is composed of three types of light-emitting elements, namely, a light-emitting element that emits blue light, a light-emitting element that emits green light, and a light-emitting element that emits red light, three types of island-shaped light-emitting layers can be formed by repeating the deposition of the light-emitting layer and processing by photolithography three times.

[0512] First, the pixel electrodes 111R, 111G, and 111B and the conductive layer 123 are formed on the substrate 151 on which the transistors 205R, 205G, and 205B (not shown) are provided.

[0513] The conductive film to be the pixel electrodes can be formed by, for example, sputtering or vacuum evaporation. After a resist mask is formed on the conductive film by a photolithography process, the conductive film is processed to form the pixel electrodes 111R, 111G, and 111B and the conductive layer 123. The conductive film can be processed by either or both of a wet etching method and a dry etching method.

[0514] Subsequently, a film 133Bf, which will later become the layer 133B, is formed on the pixel electrodes 111R, 111G, and 111B. The film 133Bf (later layer 133B) includes a light-emitting layer that emits blue light.

[0515] In this embodiment mode, an example is shown in which an island-shaped EL layer included in a light-emitting element that emits blue light is first formed, and then an island-shaped EL layer included in a light-emitting element that emits light of another color is formed.

[0516] In the process of forming the island-shaped EL layer, the pixel electrodes of the light-emitting elements of the colors formed second or later may be damaged in the previous process, which may result in a higher driving voltage for the light-emitting elements of the colors formed second or later.

[0517] Therefore, when manufacturing a display device according to one embodiment of the present invention, it is preferable to start with an island-shaped EL layer of a light-emitting element that emits light with the shortest wavelength (for example, a blue light-emitting element). For example, it is preferable to form the island-shaped EL layers in the order of blue, green, and red, or blue, red, and green.

[0518] This maintains a good state of the interface between the pixel electrode and the EL layer in the blue light-emitting element, and prevents the drive voltage of the blue light-emitting element from increasing. It also extends the life of the blue light-emitting element and improves its reliability. Since the red and green light-emitting elements are less susceptible to increases in drive voltage, etc., compared to the blue light-emitting element, the drive voltage of the entire display device can be reduced and reliability can be improved.

[0519] The order of forming the island-shaped EL layers is not limited to the above, and may be, for example, red, green, and blue.

[0520] 20A , the film 133Bf is not formed on the conductive layer 123. For example, by using an area mask, the film 133Bf can be formed only in a desired region. By employing a film formation process using an area mask and a processing process using a resist mask, the light-emitting element can be manufactured through a relatively simple process.

[0521] The heat resistance temperature of the compounds contained in the film 133Bf is preferably 100° C. or higher and 180° C. or lower, more preferably 120° C. or higher and 180° C. or lower, and more preferably 140° C. or higher and 180° C. or lower. This can improve the reliability of the light-emitting element. Also, the upper limit of the temperature that can be applied in the manufacturing process of the display device can be increased. Therefore, the range of choices for materials and manufacturing methods used in the display device can be expanded, and the yield and reliability can be improved.

[0522] The heat resistance temperature can be, for example, any one of the glass transition point, softening point, melting point, thermal decomposition temperature, and 5% weight loss temperature, preferably the lowest temperature among these.

[0523] The film 133Bf can be formed by, for example, a vapor deposition method, specifically a vacuum deposition method. Alternatively, the film 133Bf may be formed by a transfer method, a printing method, an inkjet method, a coating method, or the like.

[0524] Subsequently, a sacrificial layer 118B is formed on the film 133Bf and the conductive layer 123 (FIG. 20A). After a resist mask is formed by a photolithography process on the film that will become the sacrificial layer 118B, the film is processed to form the sacrificial layer 118B.

[0525] By providing the sacrificial layer 118B over the film 133Bf, damage to the film 133Bf during the manufacturing process of the display device can be reduced, and the reliability of the light-emitting element can be improved.

[0526] The sacrificial layer 118B is preferably provided so as to cover the respective ends of the pixel electrodes 111R, 111G, and 111B. This means that the ends of the layer 133B, which will be formed in a later process, will be located outside the ends of the pixel electrode 111B. This allows the entire upper surface of the pixel electrode 111B to be used as a light-emitting region, thereby increasing the aperture ratio of the pixel. Furthermore, since the ends of the layer 133B may be damaged in a process after the formation of the layer 133B, it is preferable that they be located outside the ends of the pixel electrode 111B, i.e., not be used as a light-emitting region. This makes it possible to suppress variations in the characteristics of the light-emitting elements and improve reliability.

[0527] Furthermore, since the layer 133B covers the top and side surfaces of the pixel electrode 111B, each step after the formation of the layer 133B can be performed without exposing the pixel electrode 111B. If the edge of the pixel electrode 111B is exposed, corrosion may occur during an etching step or the like. By suppressing corrosion of the pixel electrode 111B, the yield and characteristics of the light-emitting element can be improved.

[0528] In addition, the sacrificial layer 118B is preferably provided also in a position overlapping with the conductive layer 123. This can prevent the conductive layer 123 from being damaged during the manufacturing process of the display device.

[0529] The sacrificial layer 118B is made of a film that is highly resistant to the processing conditions of the film 133Bf, specifically, a film that has a large etching selectivity with respect to the film 133Bf.

[0530] The sacrificial layer 118B is formed at a temperature lower than the heat resistance temperature of each compound contained in the film 133Bf. The substrate temperature when forming the sacrificial layer 118B is typically 200° C. or lower, preferably 150° C. or lower, more preferably 120° C. or lower, more preferably 100° C. or lower, and even more preferably 80° C. or lower.

[0531] A high heat resistance temperature of the compound contained in the film 133Bf is preferable because the film formation temperature of the sacrificial layer 118B can be increased. For example, the substrate temperature during the formation of the sacrificial layer 118B can be set to 100°C or higher, 120°C or higher, or 140°C or higher. The higher the film formation temperature, the denser the inorganic insulating film can be and the higher the barrier properties can be. Therefore, by forming the sacrificial layer at such a temperature, damage to the film 133Bf can be further reduced, and the reliability of the light-emitting element can be improved.

[0532] The same applies to the film formation temperatures of other layers (for example, the insulating film 125f) formed on the film 133Bf.

[0533] The sacrificial layer 118B can be formed by, for example, sputtering, ALD (including thermal ALD and PEALD), CVD, or vacuum deposition. Alternatively, the sacrificial layer 118B may be formed by the wet film formation method described above.

[0534] The sacrificial layer 118B (a layer provided in contact with the film 133Bf when the sacrificial layer 118B has a laminated structure) is preferably formed using a formation method that causes less damage to the film 133Bf. For example, it is preferable to use the ALD method or the vacuum deposition method rather than the sputtering method.

[0535] The sacrificial layer 118B can be processed by wet etching or dry etching, and is preferably processed by anisotropic etching.

[0536] By using the wet etching method, damage to the film 133Bf during processing of the sacrificial layer 118B can be reduced compared to when using the dry etching method. When using the wet etching method, it is preferable to use, for example, a developer, a tetramethylammonium hydroxide (TMAH) aqueous solution, dilute hydrofluoric acid, oxalic acid, phosphoric acid, acetic acid, nitric acid, or a mixed solution containing two or more of these. Furthermore, when using the wet etching method, a mixed acid chemical solution containing water, phosphoric acid, dilute hydrofluoric acid, and nitric acid may also be used. Note that the chemical solution used in the wet etching process may be alkaline or acidic.

[0537] The sacrificial layer 118B may be made of one or more of a metal film, an alloy film, a metal oxide film, a semiconductor film, an inorganic insulating film, and an organic insulating film, for example.

[0538] The sacrificial layer 118B can be made of a metal material such as gold, silver, platinum, magnesium, nickel, tungsten, chromium, molybdenum, iron, cobalt, copper, palladium, titanium, aluminum, yttrium, zirconium, and tantalum, or an alloy material containing such a metal material.

[0539] The sacrificial layer 118B can be made of a metal oxide such as In-Ga-Zn oxide, indium oxide, In-Zn oxide, In-Sn oxide, indium titanium oxide (In-Ti oxide), indium tin zinc oxide (In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide), or indium tin oxide containing silicon.

[0540] In addition, instead of the above gallium, an element M (M is one or more elements selected from aluminum, silicon, boron, yttrium, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium) may be used.

[0541] For example, semiconductor materials such as silicon or germanium can be used as materials that are highly compatible with semiconductor manufacturing processes. Alternatively, oxides or nitrides of the above semiconductor materials can be used. Alternatively, non-metallic materials such as carbon or compounds thereof can be used. Alternatively, metals such as titanium, tantalum, tungsten, chromium, and aluminum, or alloys containing one or more of these, can be used. Alternatively, oxides containing the above metals, such as titanium oxide or chromium oxide, or nitrides such as titanium nitride, chromium nitride, or tantalum nitride can be used.

[0542] Furthermore, various inorganic insulating films that can be used for the protective layer 131 can be used for the sacrificial layer 118B. In particular, oxide insulating films are preferable because they have higher adhesion to the film 133Bf than nitride insulating films. For example, inorganic insulating materials such as aluminum oxide, hafnium oxide, and silicon oxide can be used for the sacrificial layer 118B. For example, an aluminum oxide film can be formed as the sacrificial layer 118B using the ALD method. Using the ALD method is preferable because it can reduce damage to the base (particularly the film 133Bf).

[0543] For example, the sacrificial layer 118B can be a stacked structure of an inorganic insulating film (e.g., an aluminum oxide film) formed using the ALD method and an inorganic film (e.g., an In-Ga-Zn oxide film, a silicon film, or a tungsten film) formed using the sputtering method.

[0544] The same inorganic insulating film can be used for both the sacrificial layer 118B and the insulating layer 125 to be formed later. For example, an aluminum oxide film formed using an ALD method can be used for both the sacrificial layer 118B and the insulating layer 125. The same deposition conditions can be applied to the sacrificial layer 118B and the insulating layer 125, or different deposition conditions can be applied. For example, by depositing the sacrificial layer 118B under the same conditions as the insulating layer 125, the sacrificial layer 118B can be an insulating layer with high barrier properties against at least one of water and oxygen. On the other hand, since the sacrificial layer 118B is a layer that is removed mostly or entirely in a later process, it is preferable that it be easily processed. Therefore, the sacrificial layer 118B is preferably deposited under conditions where the substrate temperature during deposition is lower than that of the insulating layer 125.

[0545] An organic material may be used for the sacrificial layer 118B. For example, the organic material may be a material that is soluble in a solvent that is chemically stable with respect to at least the film located at the top of the film 133Bf. In particular, a material that dissolves in water or alcohol is preferably used. When forming a film of such a material, it is preferable to apply the material dissolved in a solvent such as water or alcohol using a wet film formation method, and then perform a heat treatment to evaporate the solvent. In this case, performing the heat treatment under a reduced pressure atmosphere is preferable because it allows the solvent to be removed at a low temperature and in a short time, thereby reducing thermal damage to the film 133Bf.

[0546] The sacrificial layer 118B may be made of an organic resin such as polyvinyl alcohol (PVA), polyvinyl butyral, polyvinylpyrrolidone, polyethylene glycol, polyglycerin, pullulan, water-soluble cellulose, alcohol-soluble polyamide resin, or a fluororesin such as a perfluoropolymer.

[0547] For example, the sacrificial layer 118B can be a laminated structure of an organic film (e.g., a PVA film) formed using either a vapor deposition method or the above-mentioned wet film formation method, and an inorganic film (e.g., a silicon nitride film) formed using a sputtering method.

[0548] Note that in the display device of one embodiment of the present invention, part of the sacrificial film may remain as a sacrificial layer.

[0549] Subsequently, the film 133Bf is processed using the sacrificial layer 118B as a hard mask to form a layer 133B (FIG. 20B).

[0550] 20B, a stacked structure of the layer 133B and the sacrificial layer 118B remains on the pixel electrode 111B. The pixel electrodes 111R and 111G are exposed. In addition, the sacrificial layer 118B remains on the conductive layer 123 in the region corresponding to the connection portion 140.

[0551] The film 133Bf is preferably processed by anisotropic etching, particularly anisotropic dry etching, or wet etching.

[0552] Thereafter, the steps of forming the film 133Bf, the step of forming the sacrificial layer 118B, and the step of forming the layer 133B are repeated at least twice, changing the light-emitting material, to form a layered structure of the layer 133R and the sacrificial layer 118R on the pixel electrode 111R, and a layered structure of the layer 133G and the sacrificial layer 118G on the pixel electrode 111G ( FIG. 20C ). Specifically, the layer 133R is formed to include a light-emitting layer that emits red light, and the layer 133G is formed to include a light-emitting layer that emits green light. The sacrificial layers 118R and 118G can be made of the same material as that used for the sacrificial layer 118B, and may be made of the same material or different materials.

[0553] The side surfaces of the layers 133B, 133G, and 133R are preferably perpendicular or substantially perpendicular to the surface on which they are to be formed. For example, the angle between the surface on which they are to be formed and these side surfaces is preferably 60 degrees or more and 90 degrees or less.

[0554] As described above, the distance between any two adjacent layers of the layers 133B, 133G, and 133R formed using photolithography can be narrowed to 8 μm or less, 5 μm or less, 3 μm or less, 2 μm or less, or 1 μm or less. Here, the distance can be defined, for example, as the distance between the opposing ends of any two adjacent layers of the layers 133B, 133G, and 133R. By narrowing the distance between the island-shaped EL layers in this manner, a display device with high definition and a large aperture ratio can be provided.

[0555] Next, an insulating film 125f, which will later become the insulating layer 125, is formed to cover the pixel electrode, layer 133B, layer 133G, layer 133R, sacrificial layer 118B, sacrificial layer 118G, and sacrificial layer 118R, and an insulating layer 127 is formed on the insulating film 125f (Figure 20D).

[0556] The insulating film 125f is preferably formed to a thickness of 3 nm or more, 5 nm or more, or 10 nm or more, and 200 nm or less, 150 nm or less, 100 nm or less, or 50 nm or less.

[0557] The insulating film 125f is preferably formed by, for example, an ALD method. The ALD method is preferable because it can reduce film formation damage and form a film with high coverage. The insulating film 125f is preferably formed as an aluminum oxide film by, for example, an ALD method.

[0558] Alternatively, the insulating film 125f may be formed by a sputtering method, a CVD method, or a PECVD method, which have a faster film formation rate than an ALD method. This enables a highly reliable display device to be manufactured with high productivity.

[0559] The insulating film that becomes the insulating layer 127 is preferably formed by the aforementioned wet film formation method (e.g., spin coating) using, for example, a photosensitive resin composition containing an acrylic resin. After film formation, it is preferable to remove the solvent contained in the insulating film by performing a heat treatment (also called pre-baking). Next, visible light or ultraviolet light is irradiated onto a portion of the insulating film to expose the portion. Next, development is performed to remove the exposed region of the insulating film. Next, a heat treatment (also called post-baking) is performed. This allows the insulating layer 127 shown in FIG. 20D to be formed. Note that the shape of the insulating layer 127 is not limited to the shape shown in FIG. 20D. For example, the top surface of the insulating layer 127 can have one or more of a convex curved surface, a concave curved surface, and a flat surface. Furthermore, the insulating layer 127 may cover the side surfaces of the end portions of at least one of the insulating layer 125, the sacrificial layer 118B, the sacrificial layer 118G, and the sacrificial layer 118R.

[0560] 20E , an etching process is performed using the insulating layer 127 as a mask to remove the insulating film 125f and portions of the sacrificial layers 118B, 118G, and 118R. As a result, openings are formed in the sacrificial layers 118B, 118G, and 118R, respectively, exposing the top surfaces of the layers 133B, 133G, and 133R, and the conductive layer 123. Note that portions of the sacrificial layers 118B, 118G, and 118R may remain at positions overlapping the insulating layer 127 and the insulating layer 125 (sacrificial layers 119B, 119G, and 119R).

[0561] The etching process can be performed by dry etching or wet etching. Note that if the insulating film 125f is formed using the same material as the sacrificial layers 118B, 118G, and 118R, the etching process can be performed all at once, which is preferable.

[0562] As described above, by providing the insulating layer 127, the insulating layer 125, the sacrificial layer 118B, the sacrificial layer 118G, and the sacrificial layer 118R, it is possible to prevent poor connection between the light-emitting elements in the common layer 134 and the common electrode 135 due to separation and to prevent an increase in electrical resistance due to a locally thin portion of the film thickness. As a result, the display device of one embodiment of the present invention can have improved display quality.

[0563] Subsequently, a common layer 134 and a common electrode 135 are formed in this order on the insulating layer 127, the layer 133B, the layer 133G, and the layer 133R (FIG. 20F).

[0564] The common layer 134 can be formed by a method such as a vapor deposition method (including a vacuum deposition method), a transfer method, a printing method, an inkjet method, or a coating method.

[0565] For example, sputtering or vacuum deposition can be used to form the common electrode 135. Alternatively, a film formed by deposition and a film formed by sputtering may be stacked.

[0566] As described above, in the manufacturing method of a display device according to one embodiment of the present invention, the island-shaped layers 133B, 133G, and 133R are formed by forming a film over the entire surface and then processing it, rather than by using a fine metal mask. This allows the island-shaped layers to be formed with uniform thicknesses. This makes it possible to realize a high-resolution display device or a display device with a high aperture ratio. Furthermore, even when the resolution or aperture ratio is high and the distance between subpixels is extremely short, the layers 133B, 133G, and 133R can be prevented from contacting each other in adjacent subpixels. Therefore, leakage current between subpixels can be suppressed. This prevents crosstalk due to unintended light emission, and a display device with extremely high contrast can be realized.

[0567] Furthermore, by providing the insulating layer 127 having a tapered edge between adjacent island-shaped EL layers, it is possible to suppress the occurrence of a step during the formation of the common electrode 135 and to prevent the formation of a locally thin portion in the common electrode 135. This can suppress the occurrence of a connection failure due to the disconnected portion in the common layer 134 and the common electrode 135 and an increase in electrical resistance due to the locally thin portion. Therefore, the display device of one embodiment of the present invention can achieve both high resolution and high display quality.

[0568] This embodiment mode can be combined with other embodiment modes as appropriate.

[0569] Embodiment 3 In this embodiment, a structural example of a display device to which a semiconductor device of one embodiment of the present invention can be applied will be described.

[0570] Since the semiconductor device of one embodiment of the present invention can be extremely fine, a display device using the semiconductor device of one embodiment of the present invention can be a display device with extremely high resolution. For example, the display device of one embodiment of the present invention can be used in a display portion of a wristwatch-type or bracelet-type information terminal (wearable device), a VR device such as a head-mounted display, and a head-mounted display (HMD) such as a glasses-type AR device.

[0571] 21A shows a perspective view of display module 280. Display module 280 has a display device 200A and an FPC 290. Note that the display panel of display module 280 is not limited to display device 200A, and may be a display device 200B or a display device 200C, which will be described later.

[0572] The display module 280 has a substrate 291 and a substrate 292. The display module 280 has a display unit 281. The display unit 281 is an area for displaying an image.

[0573] 21B is a perspective view schematically illustrating the configuration on the substrate 291 side. A circuit portion 282, a pixel circuit portion 283 on the circuit portion 282, and a pixel portion 284 on the pixel circuit portion 283 are stacked on the substrate 291. A terminal portion 285 for connecting to the FPC 290 is provided in a portion of the substrate 291 that does not overlap with the pixel portion 284. The terminal portion 285 and the circuit portion 282 are electrically connected by a wiring portion 286 composed of a plurality of wirings.

[0574] The pixel section 284 has a plurality of periodically arranged pixels 284a. An enlarged view of one pixel 284a is shown on the right side of Fig. 21B. The pixel 284a has a sub-pixel 11R that emits red light, a sub-pixel 11G that emits green light, and a sub-pixel 11B that emits blue light.

[0575] The pixel circuit portion 283 has a plurality of pixel circuits 283a arranged periodically. Each pixel circuit 283a is a circuit that controls the light emission of three light-emitting devices included in one pixel 284a. One pixel circuit 283a may be configured to have three circuits that control the light emission of one light-emitting device. For example, the pixel circuit 283a may be configured to have at least one selection transistor, one current control transistor (drive transistor), and a capacitor for each light-emitting device. In this case, a gate signal is input to the gate of the selection transistor, and a source signal is input to the source. This realizes an active matrix display panel.

[0576] The circuit portion 282 includes a circuit for driving each pixel circuit 283a of the pixel circuit portion 283. For example, it is preferable that the circuit portion 282 includes one or both of a gate line driver circuit and a source line driver circuit. In addition, the circuit portion 282 may include at least one of an arithmetic circuit, a memory circuit, a power supply circuit, and the like. Furthermore, a transistor provided in the circuit portion 282 may constitute a part of the pixel circuit 283a. That is, the pixel circuit 283a may be composed of a transistor included in the pixel circuit portion 283 and a transistor included in the circuit portion 282.

[0577] The FPC 290 functions as wiring for supplying a video signal, a power supply potential, and the like from the outside to the circuit portion 282. An IC may be mounted on the FPC 290.

[0578] The display module 280 can be configured such that one or both of the pixel circuit unit 283 and the circuit unit 282 are provided overlapping below the pixel unit 284, thereby enabling the aperture ratio (effective display area ratio) of the display unit 281 to be extremely high. For example, the aperture ratio of the display unit 281 can be 40% or more and less than 100%, preferably 50% or more and 95% or less, and more preferably 60% or more and 95% or less. Furthermore, the pixels 284a can be arranged at an extremely high density, enabling the resolution of the display unit 281 to be extremely high. For example, it is preferable that the pixels 284a be arranged in the display unit 281 at a resolution of 2000 ppi or more, preferably 3000 ppi or more, more preferably 5000 ppi or more, and even more preferably 6000 ppi or more, and 20,000 ppi or less, or 30,000 ppi or less.

[0579] Because such a display module 280 has extremely high resolution, it can be suitably used in VR devices such as head-mounted displays, or in glasses-type AR devices. For example, even in a configuration in which the display unit of the display module 280 is viewed through lenses, the display module 280 has an extremely high-resolution display unit 281, so even when the display unit is enlarged with lenses, the pixels are not visible, allowing for a highly immersive display. Furthermore, the display module 280 is not limited to this, and can be suitably used in electronic devices with relatively small display units. For example, it can be suitably used in the display unit of a wearable electronic device such as a wristwatch.

[0580] 22 includes a substrate 331, a light-emitting element 130R, a light-emitting element 130G, a light-emitting element 130B, a capacitor 240, and a transistor 320. The light-emitting element 130R is a display element included in the sub-pixel 11R that emits red light, the light-emitting element 130G is a display element included in the sub-pixel 11G that emits green light, and the light-emitting element 130B is a display element included in the sub-pixel 11B that emits blue light.

[0581] Substrate 331 corresponds to substrate 291 in FIG. 21A.

[0582] The transistor 320 is a vertical channel transistor in which an oxide semiconductor is used for a semiconductor layer in which a channel is formed. Any of the transistors described as examples in Embodiment 1 can be used as the transistor 320.

[0583] An insulating layer 332 is provided over a substrate 331. The insulating layer 332 functions as a barrier layer that prevents impurities such as water or hydrogen from diffusing from the substrate 331 to the transistor 320 and prevents oxygen from being released from the semiconductor layer 108 toward the insulating layer 332. The insulating layer 332 can be, for example, a film through which hydrogen or oxygen is less likely to diffuse than a silicon oxide film, such as an aluminum oxide film, a hafnium oxide film, or a silicon nitride film.

[0584] A conductive layer 112a_1 is provided over the insulating layer 332, and a conductive layer 112a_2 is provided over the conductive layer 112a_1. An insulating layer 110a is provided over the conductive layer 112a_2, a conductive layer 114 is provided over the insulating layer 110a, an insulating layer 110b is provided over the conductive layer 114 and the insulating layer 110a, and a conductive layer 112b is provided over the insulating layer 110b. Openings are provided in the insulating layer 110a, the conductive layer 114, the insulating layer 110b, and the conductive layer 112b, and an insulating layer 110s is provided along the sidewalls of each opening. A semiconductor layer 108 is provided so as to cover a top surface of the conductive layer 112a_2, a sidewall of the insulating layer 110s, and a top surface of the conductive layer 112b. An insulating layer 106 is provided over the semiconductor layer 108, and a conductive layer 104 is provided over the insulating layer 106. An insulating layer 195 is provided over the insulating layer 106, and the conductive layer 104 is provided to fill the openings in the insulating layer 195. In addition, an insulating layer 266 is provided over the insulating layer 195 and the conductive layer 104.

[0585] The insulating layer 266 functions as an interlayer insulating layer. A barrier layer that prevents impurities such as water or hydrogen from diffusing from the insulating layer 195 or the like into the transistor 320 may be provided between the insulating layer 266 and the insulating layer 195. An insulating film similar to the insulating layer 332 can be used as the barrier layer.

[0586] A plug 274 electrically connected to the conductive layer 112b is provided so as to be embedded in the insulating layer 266, the insulating layer 195, and the insulating layer 106. Here, the plug 274 preferably has a conductive layer 274a covering the side surfaces of the openings in the insulating layer 266, the insulating layer 195, and the insulating layer 106 and part of the top surface of the conductive layer 112b, and a conductive layer 274b in contact with the top surface of the conductive layer 274a. In this case, the conductive layer 274a is preferably made of a conductive material through which hydrogen and oxygen do not easily diffuse.

[0587] Furthermore, a capacitor 240 is provided on the insulating layer 266. The capacitor 240 has a conductive layer 241, a conductive layer 245, and an insulating layer 243 located therebetween. The conductive layer 241 functions as one electrode of the capacitor 240, the conductive layer 245 functions as the other electrode of the capacitor 240, and the insulating layer 243 functions as a dielectric of the capacitor 240.

[0588] The conductive layer 241 is provided over the insulating layer 266 and is buried in the insulating layer 254. The conductive layer 241 is electrically connected to the conductive layer 112b of the transistor 320 by a plug 274. The insulating layer 243 is provided to cover the conductive layer 241. The conductive layer 245 is provided in a region overlapping with the conductive layer 241 with the insulating layer 243 interposed therebetween.

[0589] An insulating layer 255a is provided to cover the capacitor 240, an insulating layer 255b is provided over the insulating layer 255a, and an insulating layer 255c is provided over the insulating layer 255b.

[0590] An inorganic insulating film can be preferably used for each of the insulating layers 255a, 255b, and 255c. For example, it is preferable to use a silicon oxide film for the insulating layer 255a and the insulating layer 255c, and a silicon nitride film for the insulating layer 255b. This allows the insulating layer 255b to function as an etching protection film. In this embodiment, an example is shown in which part of the insulating layer 255c is etched to form a recess, but the insulating layer 255c does not necessarily have to have a recess.

[0591] The light emitting elements 130R, 130G, and 130B are provided on the insulating layer 255c.

[0592] The light-emitting element 130R has a pixel electrode 111R, a layer 133R, a common layer 134, and a common electrode 135. The light-emitting element 130G has a pixel electrode 111G, a layer 133G, a common layer 134, and a common electrode 135. The light-emitting element 130B has a pixel electrode 111B, a layer 133B, a common layer 134, and a common electrode 135. The common layer 134 and the common electrode 135 are provided in common to the light-emitting elements 130R, 130G, and 130B.

[0593] Layer 133R of light-emitting element 130R contains a light-emitting organic compound that emits at least red light. Layer 133G of light-emitting element 130G contains a light-emitting organic compound that emits at least green light. Layer 133B of light-emitting element 130B contains a light-emitting organic compound that emits at least blue light. Layer 133R, layer 133G, and layer 133B can also be called EL layers, and each contains at least a layer (light-emitting layer) containing a light-emitting organic compound.

[0594] In the display device 200A, a separate light-emitting device is fabricated for each emitted color, so there is little change in chromaticity between light emitted at low and high luminance. Furthermore, because the layers 133R, 133G, and 133B are spaced apart from one another, crosstalk between adjacent subpixels can be suppressed even in a high-resolution display panel. Therefore, a display panel with high resolution and high display quality can be realized.

[0595] Insulating layers 125, 127, and 128 are provided in the regions between adjacent light-emitting elements.

[0596] The pixel electrodes 111R, 111G, and 111B of the light-emitting element are electrically connected to the conductive layer 112b of the transistor 320 via a plug 256 embedded in the insulating layers 255a, 255b, and 255c, a conductive layer 241 embedded in the insulating layer 254, and a plug 274. The height of the top surface of the insulating layer 255c and the height of the top surface of the plug 256 are the same or approximately the same. Various conductive materials can be used for the plug.

[0597] A protective layer 131 is provided on the light emitting elements 130R, 130G, and 130B. A substrate 170 is attached to the protective layer 131 with an adhesive layer 171.

[0598] There is no insulating layer covering the upper end of each pixel electrode 111 between two adjacent pixel electrodes 111. This allows the distance between adjacent light-emitting elements to be extremely narrow, resulting in a high-definition or high-resolution display device.

[0599] [Display Device 200B] The following describes a display device that has a configuration that is partially different from that described above. Note that parts that are common to the above will be referred to, and descriptions thereof may be omitted.

[0600] 23 shows an example in which a transistor 320A, which is a planar transistor having a semiconductor layer formed on a plane, and a transistor 320B, which is a vertical channel transistor, are stacked. The transistor 320B has a similar configuration to the transistor 320 in the display device 200A.

[0601] The transistor 320A includes a semiconductor layer 351 , an insulating layer 353 , a conductive layer 354 , a pair of conductive layers 355 , an insulating layer 356 , and a conductive layer 357 .

[0602] An insulating layer 352 is provided over the substrate 331. The insulating layer 352 functions as a barrier layer that prevents impurities such as water or hydrogen from diffusing from the substrate 331 to the transistor 320 and prevents oxygen from being released from the semiconductor layer 351 toward the insulating layer 352. The insulating layer 352 can be, for example, a film through which hydrogen or oxygen is less likely to diffuse than a silicon oxide film, such as an aluminum oxide film, a hafnium oxide film, or a silicon nitride film.

[0603] A conductive layer 357 is provided over the insulating layer 352, and an insulating layer 356 is provided to cover the conductive layer 357. The conductive layer 357 functions as a first gate electrode of the transistor 320A, and part of the insulating layer 356 functions as a first gate insulating layer. An oxide insulating film such as a silicon oxide film is preferably used for at least a portion of the insulating layer 356 that is in contact with the semiconductor layer 351. The top surface of the insulating layer 356 is preferably planarized.

[0604] The semiconductor layer 351 is provided over the insulating layer 356. The semiconductor layer 351 preferably includes a metal oxide (also referred to as an oxide semiconductor) film exhibiting semiconductor characteristics. A pair of conductive layers 355 is provided over and in contact with the semiconductor layer 351 and functions as a source electrode and a drain electrode.

[0605] An insulating layer 358 and an insulating layer 350 are provided to cover top surfaces and side surfaces of the pair of conductive layers 355 and side surfaces of the semiconductor layer 351. The insulating layer 358 functions as a barrier layer that prevents impurities such as water or hydrogen from diffusing into the semiconductor layer 351 and prevents oxygen from being released from the semiconductor layer 351. The insulating layer 358 can be formed using an insulating film similar to the insulating layer 352.

[0606] An opening reaching the semiconductor layer 351 is provided in the insulating layer 358 and the insulating layer 350. An insulating layer 353 in contact with a top surface of the semiconductor layer 351 and a conductive layer 354 are buried in the opening. The conductive layer 354 functions as a second gate electrode, and the insulating layer 353 functions as a second gate insulating layer.

[0607] The top surfaces of the conductive layer 354, the insulating layer 353, and the insulating layer 350 are planarized so that their heights are the same or approximately the same, and an insulating layer 359 is provided to cover them. The insulating layer 359 functions as a barrier layer that prevents impurities such as water or hydrogen from diffusing into the transistor 320A. The insulating layer 359 can be formed using an insulating film similar to the insulating layer 352.

[0608] The transistor 320A has a structure in which a semiconductor layer in which a channel is formed is sandwiched between two gates. The two gates may be connected and the transistor may be driven by supplying the same signal to them. Alternatively, the threshold voltage of the transistor may be controlled by applying a potential for controlling the threshold voltage to one of the two gates and a potential for driving to the other.

[0609] [Display Device 200C] A display device 200C shown in FIG. 24 has a stacked structure of a transistor 310 having a channel formed in a semiconductor substrate and a transistor 320B that is a vertical channel transistor.

[0610] The transistor 310 has a channel formation region in a substrate 301. The substrate 301 can be, for example, a semiconductor substrate such as a single crystal silicon substrate. The transistor 310 includes a part of the substrate 301, a conductive layer 311, a low-resistance region 312, an insulating layer 313, and an insulating layer 314. The conductive layer 311 functions as a gate electrode. The insulating layer 313 is located between the substrate 301 and the conductive layer 311 and functions as a gate insulating layer. The low-resistance region 312 is a region in which the substrate 301 is doped with impurities and functions as one of a source and a drain. The insulating layer 314 is provided to cover a side surface of the conductive layer 311.

[0611] Furthermore, an element isolation layer 315 is provided between two adjacent transistors 310 so as to be embedded in the substrate 301 .

[0612] [Configuration Example of Display Device] FIG. 25 shows an example of a configuration applicable to the pixel portion 284 in FIG. 21 or the like.

[0613] One embodiment of the present invention is a display device having a light-emitting element (also referred to as a light-emitting device). The display device has two or more pixels that emit light of different colors. Each pixel has a light-emitting element. Each light-emitting element has a pair of electrodes and an EL layer therebetween. The light-emitting element is preferably an organic EL element (organic electroluminescent element). Two or more light-emitting elements that emit different colors each have an EL layer containing a different light-emitting material. For example, a full-color display device can be realized by having three types of light-emitting elements that emit red (R), green (G), or blue (B) light, respectively.

[0614] When fabricating a display device having multiple light-emitting elements that emit different colors of light, it is necessary to form at least one layer containing a light-emitting material (light-emitting layer) in an island shape. When fabricating a partial or entire EL layer, a method of forming island-shaped organic films by vapor deposition using a shadow mask such as a metal mask is known. However, this method can cause deviations in the shape and position of the island-shaped organic films from the design due to various factors such as the accuracy of the metal mask, misalignment between the metal mask and the substrate, deflection of the metal mask, and spreading of the contours of the deposited film due to vapor scattering, making it difficult to achieve high-definition and high-aperture display devices. Furthermore, during vapor deposition, the contours of the layer can become blurred, resulting in thinning of the edges. In other words, the thickness of the island-shaped light-emitting layer can vary depending on the location. Furthermore, when fabricating large, high-resolution, or high-definition display devices, there is a concern that low dimensional accuracy of the metal mask and deformation due to heat, etc., can reduce manufacturing yield. Therefore, measures have been taken to artificially increase the resolution (also known as pixel density) by adopting special pixel arrangements such as a pentile array.

[0615] In this specification, the term "island-like" refers to a state in which two or more layers formed using the same material in the same process are physically separated. For example, an island-like light-emitting layer refers to a state in which the light-emitting layer is physically separated from an adjacent light-emitting layer.

[0616] In one embodiment of the present invention, an EL layer is processed into a fine pattern by photolithography without using a shadow mask such as a fine metal mask (FMM). This makes it possible to realize a display device with high definition and a large aperture ratio, which have been difficult to achieve until now. Furthermore, since the EL layer can be individually fabricated, a display device with extremely vivid images, high contrast, and high display quality can be realized. Note that, for example, the EL layer may be processed into a fine pattern using both a metal mask and photolithography.

[0617] Furthermore, the EL layer can be partially or entirely separated physically. This can suppress leakage current between adjacent light-emitting elements through a layer shared between the light-emitting elements (also referred to as a common layer). This can prevent crosstalk caused by unintended light emission, thereby realizing a display device with extremely high contrast. In particular, a display device with high current efficiency at low luminance can be realized.

[0618] One embodiment of the present invention can also be a display device that combines a white-emitting light-emitting element and a color filter. In this case, light-emitting elements provided in pixels (subpixels) that emit light of different colors can have the same configuration, and all layers can be common layers. Furthermore, part or all of each EL layer can be separated by photolithography. This suppresses leakage current through the common layer, thereby achieving a display device with high contrast. In particular, in an element having a tandem structure in which multiple light-emitting layers are stacked via a highly conductive intermediate layer, leakage current through the intermediate layer can be effectively prevented, thereby achieving a display device that combines high brightness, high definition, and high contrast.

[0619] When the EL layer is processed by photolithography, a portion of the light-emitting layer may be exposed, which may cause deterioration. Therefore, it is preferable to provide an insulating layer that covers at least the side surfaces of the island-shaped light-emitting layer. The insulating layer may also be configured to cover a portion of the top surface of the island-shaped EL layer. The insulating layer is preferably made of a material that has barrier properties against water and oxygen. For example, an inorganic insulating film that is less likely to diffuse water or oxygen can be used. This suppresses deterioration of the EL layer, thereby achieving a highly reliable display device.

[0620] Furthermore, there is a region (recess) between two adjacent light-emitting elements where the EL layer of either light-emitting element is not provided. When a common electrode, or a common electrode and a common layer, is formed to cover the recess, a phenomenon in which the common electrode is separated by a step at the edge of the EL layer (also called a step discontinuity) may occur, resulting in insulation of the common electrode on the EL layer. Therefore, it is preferable to use a configuration in which the local step located between two adjacent light-emitting elements is filled with a resin layer functioning as a planarization film (also called LFP: Local Filling Planarization). The resin layer functions as a planarization film. This suppresses step discontinuity of the common layer or common electrode, thereby achieving a highly reliable display device.

[0621] A more specific structural example of the display device of one embodiment of the present invention will be described below with reference to the drawings.

[0622] 25A is a schematic top view of a display device 200 of one embodiment of the present invention. The display device 200 includes a plurality of light-emitting elements 130R that emit red light, a plurality of light-emitting elements 130G that emit green light, and a plurality of light-emitting elements 130B that emit blue light over a substrate 101. In FIG. 25A , the symbols R, G, and B are assigned within the light-emitting regions of the light-emitting elements to easily distinguish the light-emitting elements from one another.

[0623] The light emitting elements 130R, 130G, and 130B are arranged in a matrix. Fig. 25A shows a so-called stripe arrangement in which light emitting elements of the same color are arranged in one direction. Note that the arrangement method of the light emitting elements is not limited to this, and arrangement methods such as an S-stripe arrangement, a delta arrangement, a Bayer arrangement, or a zigzag arrangement may also be used, or a pentile arrangement, a diamond arrangement, or the like may also be used.

[0624] 25A also shows a connection electrode 111C that is electrically connected to the common electrode 135. The connection electrode 111C is given a potential (e.g., an anode potential or a cathode potential) to be supplied to the common electrode 135. The connection electrode 111C is provided outside the display area where the light-emitting elements 130R and the like are arranged.

[0625] The connection electrode 111C can be provided along the periphery of the display area. For example, it may be provided along one side of the periphery of the display area, or it may be provided over two or more sides of the periphery of the display area. That is, when the top surface shape of the display area is rectangular, the top surface shape of the connection electrode 111C can be a strip shape (rectangle), an L-shape, a U-shape (square bracket shape), a square shape, or the like.

[0626] 25B and 25C are schematic cross-sectional views corresponding to dashed dotted lines A1-A2 and A3-A4 in Fig. 25A, respectively. Fig. 25B shows a schematic cross-sectional view of light-emitting element 130R, light-emitting element 130G, and light-emitting element 130B, and Fig. 25C shows a schematic cross-sectional view of connection portion 140 where connection electrode 111C and common electrode 135 are connected.

[0627] The light-emitting element 130R has a pixel electrode 111R, a layer 133R, a common layer 134, and a common electrode 135. The light-emitting element 130G has a pixel electrode 111G, a layer 133G, a common layer 134, and a common electrode 135. The light-emitting element 130B has a pixel electrode 111B, a layer 133B, a common layer 134, and a common electrode 135.

[0628] The layer 133 and the common layer 134 can each independently include one or more of an electron injection layer, an electron transport layer, a hole injection layer, and a hole transport layer. For example, the layer 133 can have a stacked structure of a hole injection layer, a hole transport layer, a light-emitting layer, and an electron transport layer from the pixel electrode 111 side, and the common layer 134 can have an electron injection layer.

[0629] A protective layer 131 is provided on the common electrode 135 to cover the light emitting elements 130R, 130G, and 130B. The protective layer 131 has a function of preventing impurities such as water from diffusing from above into each light emitting element.

[0630] The edge of the pixel electrode 111 preferably has a tapered shape. When the edge of the pixel electrode 111 has a tapered shape, the layer 133 provided along the edge of the pixel electrode 111 can also have a tapered shape. By tapering the edge of the pixel electrode 111, the coverage of the layer 133 provided over the edge of the pixel electrode 111 can be improved. Furthermore, by tapering the side surface of the pixel electrode 111, foreign matter (for example, also referred to as dust or particles) during the manufacturing process can be easily removed by a process such as cleaning, which is preferable.

[0631] Layer 133 is processed into an island shape by photolithography. Therefore, the angle between the top surface and the side surface of layer 133 at its edge may be close to 90 degrees. On the other hand, an organic film formed using FMM (Fine Metal Mask) or the like tends to become gradually thinner toward the edge. For example, the top surface may be formed in a sloped shape over a range of 1 μm to 10 μm, resulting in a shape in which it is difficult to distinguish between the top surface and the side surface.

[0632] Between two adjacent light emitting elements, there are an insulating layer 125, an insulating layer 127, and a sacrificial layer (sacrificial layers 119B, 119G, 119R).

[0633] Between two adjacent light-emitting elements, the side surfaces of the layers 133 face each other with the insulating layer 127 interposed therebetween. The insulating layer 127 is located between the two adjacent light-emitting elements and is provided so as to fill the ends of each layer 133 and the region between the two layers 133. The insulating layer 127 has a smooth, convex upper surface, and a common layer 134 and a common electrode 135 are provided to cover the upper surface of the insulating layer 127.

[0634] The insulating layer 125 is provided in contact with the side surface of the layer 133. The insulating layer 125 is also provided to cover the upper end portion of the layer 133. A part of the insulating layer 125 is provided in contact with the upper surface of the substrate 101.

[0635] The insulating layer 125 is located between the insulating layer 127 and the layer 133 and functions as a protective film to prevent the insulating layer 127 from contacting the layer 133 .

[0636] 25C shows a connection portion 140 where the connection electrode 111C and the common electrode 135 are electrically connected. In the connection portion 140, an opening is provided in the insulating layer 125 and the insulating layer 127 above the connection electrode 111C. The connection electrode 111C and the common electrode 135 are electrically connected through the opening.

[0637] 25C shows the connection portion 140 where the connection electrode 111C and the common electrode 135 are electrically connected, but the common electrode 135 may be provided on the connection electrode 111C via the common layer 134. In particular, when a carrier injection layer is used for the common layer 134, the electrical resistivity of the material used for the common layer 134 is sufficiently low and the common layer 134 can be formed thin, so there are many cases where no problem occurs even if the common layer 134 is located at the connection portion 140. This allows the common electrode 135 and the common layer 134 to be formed using the same shielding mask, thereby reducing manufacturing costs.

[0638] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0639] Embodiment 4 In this embodiment, a circuit, a layout, and the like that can be applied to a display device of one embodiment of the present invention will be described.

[0640] 26 is a block diagram illustrating the display device 200. The display device 200 has a display unit 435, a first drive circuit unit 431, and a second drive circuit unit 432.

[0641] The display unit 435 has a plurality of pixels 230 arranged in a matrix of m rows (m is an integer of 1 or more) and n columns (n ​​is an integer of 1 or more). The plurality of pixels 230 can function as sub-pixels corresponding to different colors. For example, the plurality of pixels 230 are classified into pixels 230a, 230b, and 230c shown in FIG. 30A (to be described later) and the like.

[0642] The display unit 435 corresponds to, for example, the display unit 168 in FIG. 14, and the pixels 230a, 230b, 230c, and 440 correspond to, for example, the sub-pixels 11R, 11G, 11B, and 210 in FIG. 14, respectively.

[0643] 21, and the pixels 230a, 230b, 230c, and 440 correspond to the sub-pixels 11R, 11G, 11B, and 284a in FIG. 21, respectively.

[0644] 26, the pixel 230 in the first row and nth column is indicated as pixel 230[1,n], the pixel 230 in the mth row and first column is indicated as pixel 230[m,1], and the pixel 230 in the mth row and nth column is indicated as pixel 230[m,n]. Also, any pixel 230 included in the display unit 435 may be indicated as pixel 230[r,s]. r is an integer greater than or equal to 1 and less than or equal to m, and s is an integer greater than or equal to 1 and less than or equal to n.

[0645] The circuit included in the first drive circuit unit 431 functions as, for example, a scanning line drive circuit. The circuit included in the second drive circuit unit 432 functions as, for example, a signal line drive circuit. Note that some kind of circuit may be provided at a position facing the first drive circuit unit 431 across the display unit 435. Note that some kind of circuit may be provided at a position facing the second drive circuit unit 432 across the display unit 435. Note that the circuits included in the first drive circuit unit 431 and the second drive circuit unit 432 are collectively referred to as a peripheral drive circuit 433.

[0646] The peripheral driver circuit 433 can include various circuits such as a shift register circuit, a level shifter circuit, an inverter circuit, a latch circuit, an analog switch circuit, a multiplexer circuit, a demultiplexer circuit, and a logic circuit. The transistor 100 according to one embodiment of the present invention or the like can be used for the peripheral driver circuit 433. Note that the transistor included in the peripheral driver circuit and the transistor included in the pixel 230 may be formed in the same process.

[0647] The display device 200 also has m wires 436 that are arranged approximately in parallel and whose potential is controlled by a circuit included in the first drive circuit unit 431, and n wires 437 that are arranged approximately in parallel and whose potential is controlled by a circuit included in the second drive circuit unit 432.

[0648] 26 illustrates an example in which the wiring 436 and the wiring 437 are connected to the pixel 230. However, the wiring 436 and the wiring 437 are just an example, and the wirings connected to the pixel 230 are not limited to the wiring 436 and the wiring 437.

[0649] 27A to 27D, 28A to 28D, 29A, and 29B show configuration examples of a pixel 230. The pixel 230 includes a pixel circuit 51 (pixel circuit 51A, pixel circuit 51B, pixel circuit 51C, pixel circuit 51D, pixel circuit 51E, pixel circuit 51F, pixel circuit 51G, pixel circuit 51H, pixel circuit 51I, or pixel circuit 51J) and a light-emitting element 61.

[0650] The light-emitting element (also referred to as a light-emitting device) described in this embodiment and the like refers to a self-luminous display element such as an organic EL element (also referred to as an OLED (organic light-emitting diode)). Note that the light-emitting element electrically connected to the pixel circuit can be a self-luminous light-emitting element such as an LED (light-emitting diode), a micro LED, a QLED (quantum-dot light-emitting diode), or a semiconductor laser.

[0651] The pixel circuit 51A shown in FIG. 27A is a 2Tr1C type pixel circuit having a transistor 52A, a transistor 52B, and a capacitor 53.

[0652] One of the source and drain of the transistor 52A is electrically connected to the wiring SL, and the gate of the transistor 52A is electrically connected to the wiring GL. One of the source and drain of the transistor 52A is electrically connected to the gate of the transistor 52B and one terminal of the capacitor 53. One of the source and drain of the transistor 52B is electrically connected to the wiring ANO. The other of the source and drain of the transistor 52B is electrically connected to the other terminal of the capacitor 53 and the anode of the light-emitting element 61. The cathode of the light-emitting element 61 is electrically connected to the wiring VCOM. A region where the other of the source and drain of the transistor 52A, the gate of the transistor 52B, and one terminal of the capacitor 53 are electrically connected functions as a node ND.

[0653] The wiring GL corresponds to the wiring 436, and the wiring SL corresponds to the wiring 437. The wiring VCOM is a wiring that applies a potential for supplying current to the light-emitting element 61. The transistor 52A has a function of controlling the conduction or non-conduction state between the wiring SL and the gate of the transistor 52B based on the potential of the wiring GL. For example, VDD is supplied to the wiring ANO, and VSS is supplied to the wiring VCOM.

[0654] By turning on the transistor 52A, an image signal is supplied from the wiring SL to the node ND. Then, by turning off the transistor 52A, the image signal is held in the node ND. In order to reliably hold the image signal supplied to the node ND, it is preferable to use a transistor with low off-state current as the transistor 52A. For example, it is preferable to use an OS transistor as the transistor 52A.

[0655] The transistor 52B has a function of controlling the amount of current flowing through the light-emitting element 61. The capacitor 53 has a function of holding the gate potential of the transistor 52B. The intensity of light emitted by the light-emitting element 61 is controlled in response to an image signal supplied to the gate (node ​​ND) of the transistor 52B.

[0656] In the pixel circuit 51A shown in FIG. 27A , the transistors 52A and 52B have back gates. A signal line or a power supply line can be electrically connected to the back gates to apply any potential. The back gates may also be electrically connected to a wiring that supplies a ground potential. The back gates may also be electrically connected to the gates. The back gates may als...

Claims

1. A semiconductor layer comprising a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, a first insulating layer, and a second insulating layer, The second conductive layer has a region located above the first conductive layer, The second conductive layer has a first opening that overlaps with the first conductive layer, The third conductive layer has a region located above the second conductive layer, The third conductive layer has a second opening that overlaps with the first opening, The first insulating layer has a region in contact with the side wall of the second conductive layer at the first opening. The semiconductor layer has a region in contact with the upper surface of the first conductive layer, a region facing the side wall of the second conductive layer via the first insulating layer, and a region in contact with the upper surface of the third conductive layer. The second insulating layer has a region located above the semiconductor layer, The semiconductor device has a fourth conductive layer having a region facing the first conductive layer via the second insulating layer and the semiconductor layer, and a region facing the side wall of the second conductive layer via the second insulating layer, the semiconductor layer, and the first insulating layer.

2. In claim 1, The semiconductor device has a region in the second opening that is in contact with the side wall of the third conductive layer.

3. In claim 1, The first conductive layer functions as either the source or the drain of the transistor. The third conductive layer functions as the other of the source and drain of the transistor. The second conductive layer functions as the first gate of the transistor. The fourth conductive layer is a semiconductor device having the function of a second gate of the transistor.

4. In claim 1, The first conductive layer functions as either the source or the drain of the transistor. The third conductive layer functions as the other of the source and drain of the transistor. The fourth conductive layer functions as the first gate of the transistor. The second conductive layer is a semiconductor device electrically connected to the first conductive layer.

5. A semiconductor layer comprising a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, a first insulating layer, a second insulating layer, a third insulating layer, and a fourth insulating layer, The third insulating layer has a region located above the first conductive layer, The third insulating layer has a first opening that overlaps with the first conductive layer, The second conductive layer has a region located above the third insulating layer, The second conductive layer has a second opening that overlaps with the first opening, The fourth insulating layer has a region located above the second conductive layer, The fourth insulating layer has a third opening that overlaps with the first opening, The third conductive layer has a region located above the fourth insulating layer, The third conductive layer has a fourth opening that overlaps with the first opening, The first insulating layer has a region in contact with the side wall of the third insulating layer at the first opening, a region in contact with the side wall of the second conductive layer at the second opening, and a region in contact with the side wall of the fourth insulating layer at the third opening. The semiconductor layer has a region in contact with the upper surface of the first conductive layer, a region facing the side wall of the second conductive layer via the first insulating layer, and a region in contact with the upper surface of the third conductive layer. The second insulating layer has a region located above the semiconductor layer, The semiconductor device has a fourth conductive layer having a region facing the first conductive layer via the second insulating layer and the semiconductor layer, and a region facing the side wall of the second conductive layer via the second insulating layer, the semiconductor layer, and the first insulating layer.

6. In claim 5, The third insulating layer comprises a first layer and a second layer having a region located above the first layer. The first layer is a semiconductor device having a region with a higher film density than the second layer.

7. In claim 5, The fourth insulating layer comprises a third layer and a fourth layer having a region located above the third layer. The fourth layer is a semiconductor device having a region with a higher film density than the third layer.

8. In claim 5, The first insulating layer comprises a fifth layer and a sixth layer having a region located above the fifth layer. The fifth layer has a region with a higher film density than the sixth layer. The fifth layer has a region in contact with the side wall of the third insulating layer in the first opening, a region in contact with the side wall of the second conductive layer in the second opening, and a region in contact with the side wall of the fourth insulating layer in the third opening. The sixth layer is a semiconductor device having a region in contact with the semiconductor layer.

9. A first conductive film is formed, A first conductive layer is formed by removing a portion of the first conductive film. A first insulating film is formed having a region positioned above the first conductive layer. A second conductive film is formed having a region positioned above the first insulating film. A second conductive layer is formed by removing a portion of the second conductive film. A second insulating film is formed having a region positioned above the second conductive layer. A third conductive film is formed having a region positioned above the second insulating film. Using photolithography, a resist mask having a region positioned above the third conductive film is formed. In the third conductive film, the region that does not overlap with the resist mask is removed by etching to provide a first opening. In the second insulating film, a region that does not overlap with the resist mask is removed by etching to provide a second opening. In the second conductive layer, a region that does not overlap with the resist mask is removed by etching to provide a third opening. In the first insulating film, the region that does not overlap with the resist mask is removed by etching to provide a fourth opening and expose the upper surface of the first conductive layer. A third insulating film is formed so as to cover the upper surface of the third conductive film, the exposed upper surface of the first conductive layer, the side wall of the third conductive film at the first opening, the side wall of the second insulating film at the second opening, the side wall of the second conductive layer at the third opening, and the side wall of the first insulating film at the fourth opening. A method for manufacturing a semiconductor device, comprising processing the third insulating film by anisotropic etching to form a sidewall insulating layer that covers the sidewall of the second conductive layer in the third opening.

10. In claim 9, A method for manufacturing a semiconductor device, wherein the sidewall insulating layer covers the sidewall of the first insulating film at the fourth opening and the sidewall of the second insulating film at the second opening.

11. In claim 9, A method for manufacturing a semiconductor device, wherein the sidewall insulating layer covers the sidewall of the first insulating film at the fourth opening, the sidewall of the second insulating film at the second opening, and the sidewall of the third conductive film at the first opening.