Semiconductor device

Abstract

This semiconductor device comprises a wiring layer, a semiconductor element, an insulating layer, a sealing resin, and a metal film. The semiconductor element has a plurality of electrodes facing the wiring layer and conductively joined to the wiring layer. The insulating layer covers the wiring layer. The sealing resin is positioned on the side opposite to the wiring layer in a first direction with the insulating layer used as a reference and surrounds at least the periphery of the semiconductor element when viewed in the first direction. The metal film covers the semiconductor element and includes a portion positioned between the insulating layer and the sealing resin. A portion of the insulating layer is positioned between the wiring layer and the semiconductor element. The sealing resin has a first side surface facing the direction orthogonal to the first direction. The insulating layer is exposed to the outside from the first side surface.

Description

Semiconductor Devices

[0001] The present disclosure relates to semiconductor devices.

[0002] Patent Document 1 discloses an example of a semiconductor device including a lateral-structure semiconductor element (HEMT). The semiconductor element has a first electrode and a second electrode. In this semiconductor device, the semiconductor element is bonded to a die pad. The first electrode and the second electrode are electrically connected to a plurality of terminal leads located around the die pad via wires.

[0003] In the semiconductor device disclosed in Patent Document 1, transmission of high-frequency electrical signals is sometimes required to achieve more efficient power conversion. To achieve this, it is necessary to reduce external noise that affects the operation of semiconductor elements while meeting the demand for miniaturization of conventional semiconductor devices. Furthermore, noise generated during operation of the semiconductor elements may affect external peripheral devices. Therefore, it is necessary to reduce both external noise and noise generated during operation of the semiconductor elements.

[0004] Japanese Patent Application Laid-Open No. 2020-188085

[0005] An object of the present disclosure is to provide a semiconductor device that is improved over conventional devices. In particular, in view of the above-mentioned circumstances, an object of the present disclosure is to provide a semiconductor device that can reduce noise while achieving device miniaturization.

[0006] A semiconductor device provided by a first aspect of the present disclosure includes a wiring layer, a semiconductor element having a plurality of electrodes facing the wiring layer, the plurality of electrodes being conductively connected to the wiring layer, an insulating layer covering the wiring layer, a sealing resin located on the opposite side of the insulating layer in a first direction from the wiring layer and surrounding at least the semiconductor element as viewed in the first direction, and a metal film covering the semiconductor element and including a portion located between the insulating layer and the sealing resin. A portion of the insulating layer is located between the wiring layer and the semiconductor element. The sealing resin has a first side surface facing a direction perpendicular to the first direction. The insulating layer is exposed to the outside from the first side surface.

[0007] According to the above configuration, it is possible to reduce noise while also miniaturizing the semiconductor device.

[0008] Other features and advantages of the present disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

[0009] FIG. 1 is a plan view of a semiconductor device according to a first embodiment of the present disclosure, seen through a sealing resin. FIG. 2 is a plan view corresponding to FIG. 1, further showing a semiconductor element, an insulating layer, and a metal film. FIG. 3 is a bottom view of the semiconductor device shown in FIG. 1. FIG. 4 is a cross-sectional view taken along line IV-IV in FIG. 2. FIG. 5 is a cross-sectional view taken along line V-V in FIG. 2. FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. 2. FIG. 7 is a partially enlarged view of FIG. 4. FIG. 8 is a partially enlarged view of FIG. 5. FIG. 9 is a cross-sectional view illustrating a manufacturing process of the semiconductor device shown in FIG. 1. FIG. 10 is a cross-sectional view illustrating a manufacturing process of the semiconductor device shown in FIG. 1. FIG. 11 is a cross-sectional view illustrating a manufacturing process of the semiconductor device shown in FIG. 1. FIG. 12 is a cross-sectional view illustrating a manufacturing process of the semiconductor device shown in FIG. 1. FIG. 13 is a cross-sectional view illustrating a manufacturing process of the semiconductor device shown in FIG. 1. FIG. 14 is a cross-sectional view illustrating a manufacturing process of the semiconductor device shown in FIG. 1. FIG. 15 is a cross-sectional view illustrating a manufacturing process of the semiconductor device shown in FIG. 1. FIG. 16 is a cross-sectional view illustrating a manufacturing process of the semiconductor device shown in FIG. 1. FIG. 17 is a cross-sectional view illustrating a manufacturing process of the semiconductor device shown in FIG. 1 . FIG. 18 is a cross-sectional view illustrating a manufacturing process of the semiconductor device shown in FIG. 1 . FIG. 19 is a cross-sectional view illustrating a manufacturing process of the semiconductor device shown in FIG. 1 . FIG. 20 is a cross-sectional view illustrating a manufacturing process of the semiconductor device shown in FIG. 1 . FIG. 21 is a cross-sectional view illustrating a manufacturing process of the semiconductor device shown in FIG. 1 . FIG. 22 is a cross-sectional view illustrating a manufacturing process of the semiconductor device shown in FIG. 1 . FIG. 23 is a cross-sectional view of a semiconductor device according to a modified example of the first embodiment of the present disclosure. FIG. 24 is a plan view of a semiconductor device according to a second embodiment of the present disclosure. FIG. 25 is a cross-sectional view taken along line XXV-XXV of FIG. 24 . FIG. 26 is a cross-sectional view taken along line XXVI-XXVI of FIG. 24 . FIG. 27 is a plan view of a semiconductor device according to a third embodiment of the present disclosure, seen through the sealing resin. FIG. 28 is a plan view corresponding to FIG. 27 , further showing the semiconductor element, the insulating layer, and the metal film. FIG. 29 is a cross-sectional view taken along line XXIX-XXIX of FIG. 28 . Fig. 30 is a cross-sectional view taken along line XXX-XXX in Fig. 28. Fig. 31 is a cross-sectional view taken along line XXXI-XXXI in Fig. 28.

[0010] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present disclosure will be described with reference to the accompanying drawings.

[0011] First Embodiment: A semiconductor device A10 according to a first embodiment of the present disclosure will be described with reference to FIGS. 1 to 8 . The semiconductor device A10 includes a substrate 10, multiple wiring layers 21, multiple terminals 22, a heat dissipation layer 23, multiple dummy terminals 24, a semiconductor element 30, multiple bonding layers 39, an insulating layer 41, a metal film 42, a sealing resin 50, and multiple coating layers 60. The semiconductor device A10 is a resin package that is surface-mounted on a wiring board. The resin package is a QFN (quad flat non-leaded package) in which multiple leads do not protrude from the sealing resin 50. For ease of understanding, FIG. 1 shows the sealing resin 50 in a perspective view. For ease of understanding, FIG. 2 shows the semiconductor element 30, the insulating layer 41, and the metal film 42 in a perspective view, compared to FIG. 1 . In FIG. 1 , the transparent sealing resin 50 is shown with an imaginary line (two-dot chain line). In FIG. 2 , the transparent semiconductor element 30 and the transparent sealing resin 50 are each shown with an imaginary line. Furthermore, in FIG. 2, the line IV-IV and the line V-V are indicated by dashed lines.

[0012] In describing the semiconductor device A10, for convenience, the normal direction to the main surface 11 of the substrate 10 (described later) will be referred to as the "first direction z." One direction perpendicular to the first direction z will be referred to as the "second direction x." A direction perpendicular to the first direction z and the second direction x will be referred to as the "third direction y." As shown in FIG. 1 , the semiconductor device A10 is rectangular when viewed in the first direction z (in a plan view).

[0013] As shown in FIGS. 4 to 6 , the substrate 10 supports a plurality of wiring layers 21. The substrate 10 is electrically insulating. The substrate 10 is made of a material containing black epoxy resin. The substrate 10 has a main surface 11, a back surface 12, and a plurality of second side surfaces 13. The main surface 11 and the back surface 12 face opposite each other in the first direction z. The main surface 11 faces the plurality of wiring layers 21. The back surface 12 is exposed to the outside. When the semiconductor device A10 is mounted on a wiring board, the back surface 12 faces the wiring board. The plurality of second side surfaces 13 face in a direction perpendicular to the first direction z. The plurality of second side surfaces 13 are connected to the main surface 11 and the back surface 12. The plurality of second side surfaces 13 include two second side surfaces 13 facing in the second direction x and two second side surfaces 13 facing in the third direction y.

[0014] 4 to 6, the plurality of wiring layers 21 are supported on the main surface 11 of the base material 10. The plurality of wiring layers 21, together with the plurality of terminals 22, form conductive paths between the semiconductor element 30 and a wiring board on which the semiconductor device A10 is mounted. The composition of the plurality of wiring layers 21 includes titanium (Ti) and copper (Cu).

[0015] 4 and 5 , each of the wiring layers 21 has an end face 211. The end face 211 faces a direction perpendicular to the first direction z. The end face 211 is exposed from the insulating layer 41.

[0016] The multiple wiring layers 21 include a ground wiring 21A. The ground wiring 21A functions as the ground (GND) of the semiconductor device A10. The ground wiring 21A has an exposed surface 212 that faces the same side as the main surface 11 of the base material 10 in the first direction z. The exposed surface 212 is exposed from the insulating layer 41.

[0017] 4 to 6, the plurality of terminals 22 are housed in the substrate 10. Each of the plurality of terminals 22 is connected to one of the plurality of wiring layers 21. The composition of the plurality of terminals 22 includes copper.

[0018] 3 to 5 , each of the multiple terminals 22 has a first exposed surface 221 and a second exposed surface 222. The first exposed surface 221 faces the same side as the back surface 12 of the base material 10 in the first direction z. The first exposed surface 221 is exposed from the back surface 12. The second exposed surface 222 faces a direction perpendicular to the first direction z. The second exposed surface 222 is exposed from one of the multiple second side surfaces 13 of the base material 10. The second exposed surface 222 is flush with the end surfaces 211 of any of the multiple wiring layers 21.

[0019] 2 and 3 , the heat dissipation layer 23 overlaps the semiconductor element 30 when viewed in the first direction z. As shown in FIGS. 4 and 5 , the heat dissipation layer 23 is housed in the base material 10. The heat dissipation layer 23 is connected to any one of the multiple wiring layers 21. The composition of the heat dissipation layer 23 is the same as the composition of the multiple terminals 22.

[0020] 3 to 5 , the heat dissipation layer 23 has a third exposed surface 231. The third exposed surface 231 faces the same side as the rear surface 12 of the base material 10 in the first direction z. The third exposed surface 231 is exposed from the rear surface 12.

[0021] 2 and 3, the multiple dummy terminals 24 are located at the four corners of the substrate 10 when viewed in the first direction z. As shown in Fig. 6, the multiple dummy terminals 24 are housed in the substrate 10. The multiple dummy terminals 24 are located away from the multiple wiring layers 21, the multiple terminals 22, and the multiple heat dissipation layers 23. The composition of the multiple dummy terminals 24 is the same as the composition of the multiple terminals 22.

[0022] 3 and 6 , each of the multiple dummy terminals 24 has a fourth exposed surface 241 and a fifth exposed surface 242. The fourth exposed surface 241 faces the same side as the back surface 12 of the base material 10 in the first direction z. The fourth exposed surface 241 is exposed from the back surface 12. The fifth exposed surface 242 faces a direction perpendicular to the first direction z. The fifth exposed surface 242 is exposed from one of the multiple second side surfaces 13 of the base material 10.

[0023] As shown in FIGS. 3 to 5 , each of the multiple bonding layers 39 is disposed on one of the multiple wiring layers 21 and connected to one of the multiple wiring layers 21. The multiple bonding layers 39 are conductors. As shown in FIG. 8 , each of the multiple bonding layers 39 has a seat portion 391 and a bonding portion 392. The seat portion 391 is connected to one of the multiple wiring layers 21. The composition of the seat portion 391 includes nickel (Ni). The bonding portion 392 is located on the seat portion 391. The composition of the bonding portion 392 includes tin (Sn) and silver (Ag). Alternatively, the composition of the bonding portion 392 may include tin and antimony (Sb).

[0024] 4 and 5, the semiconductor element 30 is conductively bonded to the plurality of wiring layers 21 via the plurality of bonding layers 39. As shown in Fig. 8, the semiconductor element 30 has a peripheral surface 301, a main body 31, a plurality of electrodes 32, and a passivation film 33.

[0025] As shown in Figures 4 and 5, the peripheral surface 301 faces a direction perpendicular to the first direction z. The main body portion 31 and the passivation film 33 include the peripheral surface 301. As shown in Figures 4 and 5, the main body portion 31 is located on the opposite side of the multiple wiring layers 21 in the first direction z with respect to the multiple electrodes 32. The main body portion 31 includes a semiconductor substrate, a semiconductor layer stacked on the semiconductor substrate, and a rewiring layer electrically connected to the semiconductor layer. Various circuits are configured in the semiconductor layer. The main body portion 31 has an upper surface 311. The upper surface 311 faces the same side as the main surface 11 of the base material 10 in the first direction z.

[0026] As shown in Figures 4 and 5, the multiple electrodes 32 face the multiple wiring layers 21. As shown in Figure 8, each of the multiple electrodes 32 has a base 321 and a columnar portion 322. The base 321 is connected to the main body 31. The columnar portion 322 protrudes from the base 321 toward the multiple wiring layers 21. The columnar portion 322 contains copper. The columnar portion 322 of each of the multiple electrodes 32 is individually conductively bonded to each of the bonding portions 392 of the multiple bonding layers 39. In this way, the multiple electrodes 32 are conductively bonded to the multiple wiring layers 21.

[0027] 8 , the passivation film 33 covers the surface of the main body 31 facing away from the upper surface 311 in the first direction z. The passivation film 33 has electrical insulation properties. A plurality of openings 331 are provided in the passivation film 33. The bases 321 of the plurality of electrodes 32 are individually housed in the plurality of openings 331. The passivation film 33 is made of a material containing polyimide.

[0028] As shown in FIG. 1 and FIGS. 4 to 6 , the insulating layer 41 covers the multiple wiring layers 21. The insulating layer 41 is made of a material containing a black, soft resin. An example of the material for the insulating layer 41 is a resin material used for underfill. A portion of the insulating layer 41 is located between the multiple wiring layers 21 and the semiconductor element 30 in the first direction z. The insulating layer 41 is in contact with the main surface 11 of the base material 10. The insulating layer 41 is in contact with each of the columnar portions 322 of the multiple electrodes 32 of the semiconductor element 30 and with the peripheral surface 301 of the semiconductor element 30. As shown in FIG. 8 , the insulating layer 41 is also in contact with the upper surface 311 of the main body portion 31 of the semiconductor element 30.

[0029] 1, 4, and 5, the metal film 42 covers the semiconductor element 30. The metal film 42 includes a portion located between the insulating layer 41 and the sealing resin 50. As shown in FIG. 8, the metal film 42 is separated from the semiconductor element 30 via the insulating layer 41. The metal film 42 contacts the exposed surface 212 of the ground wiring 21A among the multiple wiring layers 21. This allows the metal film 42 to be electrically connected to the ground wiring 21A. Therefore, the potential of the metal film 42 is equivalent to the potential of the ground wiring 21A.

[0030] 8, the metal film 42 has a first film 421 and a second film 422. The first film 421 is in contact with the insulating layer 41. In the semiconductor device A10, the first film 421 is in contact with the semiconductor element 30. The first film 421 contains titanium. The second film 422 is stacked on the first film 421. The second film 422 contains copper.

[0031] 4 and 5 , the sealing resin 50 is located on the opposite side of the insulating layer 41 from the plurality of wiring layers 21 in the first direction z. As shown in FIGS. 1 , 4 and 5 , the sealing resin 50 surrounds at least the semiconductor element 30 when viewed in the first direction z. In the semiconductor device A10, the sealing resin 50 overlaps the semiconductor element 30 when viewed in the first direction z. The base material 10 is made of a material containing a black epoxy resin.

[0032] As shown in FIGS. 4 to 6 , the sealing resin 50 has a top surface 51 and a plurality of first side surfaces 52. The top surface 51 faces the same side as the main surface 11 of the base material 10 in the first direction z. The plurality of first side surfaces 52 are connected to the top surface 51. Each of the plurality of first side surfaces 52 includes a first region 521 and a second region 522. The first region 521 is connected to the top surface 51 and faces a direction perpendicular to the first direction z. The second region 522 is located on the opposite side of the top surface 51 in the first direction z with respect to the first region 521, and is connected to the first region 521. When viewed in the first direction z, the first region 521 overlaps the top surface 51.

[0033] As shown in FIGS. 4 to 6, the maximum dimension of the insulating layer 41 in the first direction z is smaller than the maximum dimension of the sealing resin 50 in the first direction z.

[0034] 7 , the insulating layer 41 and the first film 421 of the metal film 42 are exposed to the outside from second regions 522 of the multiple first side surfaces 52. A cavity 53 is provided between the first film 421 and the sealing resin 50 in the first direction z. The cavity 53 is open to the outside.

[0035] The thermal conductivity of the insulating layer 41 is lower than that of the sealing resin 50. Furthermore, the insulating layer 41 contains a first filler. The sealing resin 50 contains a second filler. The weight percentage (wt %) of the first filler in the insulating layer 41 is lower than the weight percentage of the second filler in the sealing resin 50.

[0036] The multiple covering layers 60 are exposed to the outside as shown in Figures 2 and 3. As shown in Figures 3 to 5, some of the multiple covering layers 60 individually cover the first exposed surface 221 and the second exposed surface 222 of each of the multiple terminals 22 and the end surface 211 of each of the multiple wiring layers 21. One of the multiple covering layers 60 individually covers the third exposed surface 231 of the heat dissipation layer 23. Furthermore, four of the multiple covering layers 60 individually cover the fourth exposed surface 241 and the fifth exposed surface 242 of each of the multiple dummy terminals 24.

[0037] The multiple coating layers 60 are conductors. The multiple coating layers 60 are conductively bonded to the wiring board via solder, thereby mounting the semiconductor device A10 on the wiring board. Each of the multiple coating layers 60 includes multiple metal layers. The multiple metal layers are stacked in the order of a nickel layer and a gold (Au) layer, starting from the side closest to one of the multiple terminals 22. Alternatively, the multiple metal layers may be stacked in the order of a nickel layer, a palladium (Pd) layer, and a gold layer, starting from the side closest to one of the multiple terminals 22. Therefore, the composition of the multiple coating layers 60 includes gold.

[0038] Next, an example of a method for manufacturing the semiconductor device A10 will be described with reference to Figures 9 to 22. The cross-sectional positions of Figures 9 to 22 are the same as the cross-sectional position of Figure 4.

[0039] 9 , an intermediate layer 82 is formed to cover one side of the support member 81 in the first direction z. The intermediate layer 82 is made of a metal thin film made of titanium that is in contact with the support member 81, and a metal thin film made of copper that is laminated on the metal thin film. The intermediate layer 82 is formed by depositing these metal thin films by sputtering.

[0040] Next, as shown in FIG. 10 , a plurality of conductive layers 83 are formed protruding from the intermediate layer 82 in the first direction z. A portion of each of the plurality of conductive layers 83 becomes either a plurality of terminals 22 or a heat dissipation layer 23 provided in the semiconductor device A10. To form the plurality of conductive layers 83, first, lithographic patterning is applied to the intermediate layer 82. Next, the plurality of conductive layers 83 are deposited by electrolytic plating using the intermediate layer 82 as a conductive path. Finally, the mask layer used for lithographic patterning is removed. In this manner, the plurality of conductive layers 83 are formed.

[0041] 11 , a first resin layer 84 is formed to cover the plurality of conductive layers 83. A portion of the first resin layer 84 becomes the base material 10 of the semiconductor device A10. The first resin layer 84 is made of a material containing black epoxy resin. The first resin layer 84 is formed by compression molding. At this time, the first resin layer 84 is formed so as to be in contact with the intermediate layer 82 and to entirely cover the plurality of conductive layers 83.

[0042] 12 , a portion of each of the plurality of conductive layers 83 and a portion of the first resin layer 84 are removed by grinding. These portions to be removed are portions located on the opposite side of the first direction z from the side facing the intermediate layer 82. As a result, the plurality of conductive layers 83 are exposed from the surface of the first resin layer 84 facing the first direction z.

[0043] Next, as shown in FIG. 13 , a plurality of wiring layers 21 are formed in contact with the surface of the first resin layer 84 facing the first direction z, and each wiring layer 21 is connected to one or more of the plurality of conductive layers 83. To form the plurality of wiring layers 21, first, a base layer (not shown) is formed to entirely cover the plurality of conductive layers 83 located on the side opposite the side facing the intermediate layer 82 in the first direction z, and each portion of the first resin layer 84. The base layer has the same composition as the aforementioned intermediate layer 82. The base layer is formed by sputtering. Next, lithographic patterning is performed on the base layer. Next, the plurality of wiring layers 21 are deposited by electrolytic plating using the base layer as a conductive path. Finally, the mask layer used for lithographic patterning is removed. In this manner, the plurality of wiring layers 21 are formed.

[0044] Next, as shown in FIG. 14 , multiple bonding layers 39 are formed, each connected to one of the multiple wiring layers 21. To form the multiple bonding layers 39, lithographic patterning is performed on the aforementioned base layer and the multiple wiring layers 21. Next, multiple nickel layers are deposited by electrolytic plating using the base layer and the multiple wiring layers 21 as conductive paths. Each of the multiple nickel layers corresponds to a seat 391 of each of the multiple bonding layers 39 shown in FIG. 8 . Next, multiple alloy layers containing tin are individually deposited on the multiple nickel layers by electrolytic plating using the base layer, the multiple wiring layers 21, and the multiple nickel layers as conductive paths. Each of the multiple alloy layers corresponds to a joint 392 of each of the multiple bonding layers 39 shown in FIG. 8 . Next, the mask layer used for lithographic patterning is removed. Finally, the base layer is removed by wet etching using a mixed solution of sulfuric acid (H2SO4) and hydrogen peroxide (H2O2). In this manner, the multiple bonding layers 39 are formed.

[0045] Next, as shown in FIG. 15 , the semiconductor element 30 is conductively bonded to the plurality of wiring layers 21. The semiconductor element 30 is conductively bonded to the plurality of wiring layers 21 by flip-chip bonding. First, the plurality of electrodes 32 of the semiconductor element 30 are individually temporarily attached to the plurality of bonding layers 39. Next, the bonding portions 392 (see FIG. 8 ) of each of the plurality of bonding layers 39 are melted by reflow. Finally, the melted bonding portions 392 are solidified by cooling. This completes the conductive bonding of the semiconductor element 30 to the plurality of wiring layers 21.

[0046] 16, an insulating layer 41 is formed to cover the multiple wiring layers 21. To increase the fluidity of the molten insulating layer 41, the weight percentage of the first filler described above in the insulating layer 41 is set lower than the weight percentage of the filler (corresponding to the second filler contained in the sealing resin 50 described above) in the second resin layer 85 described below. At this time, the insulating layer 41 is set to penetrate between the multiple wiring layers 21 and the semiconductor element 30 in the first direction z. Furthermore, an exposed surface 212 is set to appear in the ground wiring 21A of the multiple wiring layers 21.

[0047] 17, a metal film 42 is formed to cover the semiconductor element 30 and the insulating layer 41. To form the metal film 42, first, a first film 421 (see FIG. 8) made of titanium is formed by sputtering. The first film 421 is formed so as to be in contact with the semiconductor element 30 and the insulating layer 41. Next, a second film 422 (see FIG. 8) made of copper is formed by sputtering. The second film 422 is formed so as to cover the entire first film 421.

[0048] 18, a second resin layer 85 is formed to cover the metal film 42. A portion of the second resin layer 85 becomes the sealing resin 50 of the semiconductor device A10. The second resin layer 85 is made of a material including a black epoxy resin containing a filler (the second filler contained in the sealing resin 50 described above). The second resin layer 85 is formed by compression molding. In this case, the second resin layer 85 is formed so as to surround at least the periphery of the semiconductor element 30 when viewed in the first direction z.

[0049] Next, the support member 81 and the intermediate layer 82 are removed by grinding, along with a portion of each of the plurality of conductive layers 83 and a portion of the first resin layer 84.

[0050] 20 , tape 88 is attached to the surface of the second resin layer 85 facing the first direction z. The tape 88 is dicing tape. Next, a first blade 891 having a width b1 is used to remove a portion of each of the plurality of conductive layers 83, a portion of the first resin layer 84, a portion of each of the plurality of wiring layers 21, and a portion of each of the insulating layer 41, the metal film 42, and the second resin layer 85, thereby forming a plurality of grooves 851 recessed in the first direction z. The plurality of grooves 851 are formed in a lattice pattern along each of the second direction x and the third direction y.

[0051] Next, wet etching is performed to smooth the surfaces of the multiple conductive layers 83 exposed to the outside from the first resin layer 84. At this time, the cavity 53 shown in FIG. 7 is formed. The cavity 53 is formed because a portion of the second film 422 of the metal film 42 exposed to the outside from the insulating layer 41 is removed by wet etching. Through this process, each of the multiple conductive layers 83 becomes one of the multiple terminals 22 provided in the semiconductor device A10 or the heat dissipation layer 23 provided in the semiconductor device A10. The first resin layer 84 becomes the base material 10 provided in the semiconductor device A10. The surface of the base material 10 facing the first direction z and exposed to the outside is the back surface 12 of the base material 10.

[0052] 21 , a plurality of covering layers 60 are formed to individually cover the surfaces of the plurality of terminals 22 exposed to the outside from the base material 10 and the heat dissipation layer 23. The plurality of covering layers 60 are formed by electroless plating.

[0053] 22, the second resin layer 85 is cut using a second blade 892 having a width b2. The width b2 is smaller than the width b1 of the first blade 891. To cut the second resin layer 85, the second blade 892 is passed through each of the multiple grooves 851 and then moved in the first direction z until the second blade 892 contacts the tape 88. Through this process, the second resin layer 85 becomes the sealing resin 50 that the semiconductor device A10 is provided with. Through the above processes, the semiconductor device A10 is obtained.

[0054] Modification of First Embodiment Next, a semiconductor device A11, which is a modification of the semiconductor device A10, will be described with reference to Fig. 23. The cross-sectional position of Fig. 23 is the same as the cross-sectional position of Fig. 4.

[0055] 23 , in the semiconductor device A11, the insulating layer 41 is in contact with the entire peripheral surface 301 of the semiconductor element 30. Furthermore, the insulating layer 41 is in contact with the entire upper surface 311 of the main body 31 of the semiconductor element 30. The dimension in the first direction z of the portion of the insulating layer 41 in contact with the entire upper surface 311 is larger than the dimension in the first direction z of the corresponding portion in the semiconductor device A10.

[0056] Next, the effects of the semiconductor device A10 will be described.

[0057] The semiconductor device A10 includes an insulating layer 41 covering the wiring layer 21, a sealing resin 50 surrounding at least the semiconductor element 30 as viewed in the first direction z, and a metal film 42 covering the semiconductor element 30 and including a portion located between the insulating layer 41 and the sealing resin 50. A portion of the insulating layer 41 is located between the wiring layer 21 and the sealing resin 50. This configuration electrically insulates the wiring layer 21 from the metal film 42, while reducing both noise emitted from the semiconductor element 30 and noise entering the semiconductor device A10 from the outside. This is because the metal film 42 blocks most of the electromagnetic waves. Furthermore, the insulating layer 41 is exposed to the outside from a first side surface 52 of the sealing resin 50. This configuration allows the metal film 42 to be provided over the entire semiconductor device A10 as viewed in the first direction z, even when the semiconductor device A10 is miniaturized. This allows the metal film 42 to exhibit a noise reduction effect. Therefore, with this configuration, in the semiconductor device A10, it is possible to reduce noise while also miniaturizing the semiconductor device A10.

[0058] The maximum dimension of the insulating layer 41 in the first direction z is smaller than the maximum dimension of the sealing resin 50 in the first direction z. This configuration allows the metal film 42 to overlap the peripheral surface 301 of the semiconductor element 30 when viewed in a direction perpendicular to the first direction z, while providing electrical insulation between the wiring layer 21 and the metal film 42. This further improves the noise reduction effect in the semiconductor device A10.

[0059] The plurality of electrodes 32 of the semiconductor element 30, which are conductively bonded to the wiring layer 21, have a base 321 and a columnar portion 322 that protrudes from the base 321 toward the wiring layer 21. The columnar portion 322 is conductively bonded to the wiring layer 21 and is in contact with the insulating layer 41. This configuration makes it possible to more reliably fill the insulating layer 41 between the wiring layer 21 and the semiconductor element 30 in the first direction z. This makes it possible to prevent short circuits between the metal film 42 and the plurality of electrodes 32.

[0060] In the above case, if the thermal conductivity of the insulating layer 41 is set higher than the thermal conductivity of the sealing resin 50, heat generated by the semiconductor element 30 is more easily conducted from the columnar portions 322 of the multiple electrodes 32 to the insulating layer 41. Furthermore, since the insulating layer 41 is exposed to the outside from the first side surface 52 of the sealing resin 50, the heat dissipation properties of the semiconductor device A10 can be improved.

[0061] The insulating layer 41 contains a first filler. The sealing resin 50 contains a second filler. The weight percentage of the first filler in the insulating layer 41 is lower than the weight percentage in the sealing resin 50. This configuration relatively improves the fluidity of the molten insulating layer 41. As a result, in the process of forming the insulating layer 41 shown in FIG. 16 during the manufacturing process of the semiconductor device A10, the insulating layer 41 can be smoothly filled between the wiring layer 21 and the semiconductor element 30 in the first direction z.

[0062] The insulating layer 41 is in contact with the peripheral surface 301 of the semiconductor element 30. This configuration can prevent electrical conduction between the metal film 42 and a circuit formed in a semiconductor layer included in the main body 31 of the semiconductor element 30.

[0063] The metal film 42 is separated from the semiconductor element 30 via the insulating layer 41. By adopting this configuration, it is possible to suppress a decrease in the dielectric strength voltage of the semiconductor device A11 due to the provision of the metal film 42.

[0064] The semiconductor device A10 further includes a substrate 10 that supports the wiring layer 21, and terminals 22 that are housed in the substrate 10 and connected to the wiring layer 21. The terminals 22 are exposed from the rear surface 12 of the substrate 10. In this case, the semiconductor device A10 further includes a coating layer 60 that covers the portions of the terminals 22 that are exposed from the substrate 10. The coating layer 60 is conductive. The coating layer 60 contains gold. This configuration improves the wettability of molten solder to the coating layer 60 when the semiconductor device A10 is mounted on a wiring board. This prevents a reduction in the bonding area of ​​the coating layer 60 to the solder.

[0065] In the above case, the terminals 22 are also exposed from the second side surface 13 of the substrate 10. The covering layer 60 also covers the portions of the terminals 22 exposed from the second side surface 13. With this configuration, when the semiconductor device A10 is mounted on a wiring board, the molten solder easily creeps up the covering layer 60 in the first direction z. This promotes the formation of solder fillets. Therefore, the bonding strength of the semiconductor device A10 to the wiring board can be improved. After the semiconductor device A10 is mounted on the wiring board, the solder fillets are exposed to the outside, so the mounting state of the semiconductor device A10 on the wiring board can be easily confirmed visually by external inspection.

[0066] The semiconductor device A10 further includes a heat dissipation layer 23 housed in the base material 10. The heat dissipation layer 23 is connected to the wiring layer 21. The heat dissipation layer 23 is exposed to the outside from the rear surface 12 of the base material 10. With this configuration, heat generated from the semiconductor element 30 is conducted to the heat dissipation layer 23 via the multiple electrodes 32 and the wiring layer 21. This can improve the heat dissipation performance of the semiconductor device A10.

[0067] The metal film 42 contains titanium. This configuration can prevent the metal film 42 from peeling off from the insulating layer 41, even if the insulating layer 41 contains resin. Furthermore, a cavity 53 is provided between the metal film 42 and the sealing resin 50 in the first direction z. The cavity 53 is open to the outside. This configuration can suppress a decrease in the dielectric strength voltage of the semiconductor device A10 due to the inclusion of the metal film 42.

[0068] The semiconductor device A10 further includes a plurality of dummy terminals 24 arranged at the four corners of the substrate 10 as viewed in the first direction z. Here, in the semiconductor device A10 mounted on a wiring substrate, thermal stress acts on the terminals 22. This thermal stress tends to concentrate at the four corners of the semiconductor device A10 as viewed in the first direction z. Therefore, by adopting this configuration, the thermal stress can be concentrated on the plurality of dummy terminals 24, thereby reducing the thermal stress acting on the terminals 22. This makes it less likely for cracks to occur in the solder that electrically connects the wiring substrate and the terminals 22, thereby more effectively preventing conduction interruptions of the terminals 22 to the wiring substrate.

[0069] Second Embodiment: A semiconductor device A20 according to a second embodiment of the present disclosure will be described with reference to Figures 24 to 26. In these figures, elements that are the same as or similar to those in the semiconductor device A10 described above are designated by the same reference numerals, and duplicated descriptions will be omitted. Here, in Figure 24, the lines XXV-XXV and XXVI-XXVI are indicated by dashed lines, respectively.

[0070] In the semiconductor device A20, the configurations of the metal film 42 and the sealing resin 50 are different from those of the semiconductor device A10.

[0071] 24 to 26 , the sealing resin 50 has an opening 54 that opens from the top surface 51. When viewed in the first direction z, the entire semiconductor element 30 is enclosed in the opening 54. The metal film 42 is exposed to the outside from the opening 54. Therefore, the metal film 42 is exposed to the outside from the top surface 51.

[0072] 25 and 26 , in semiconductor device A20, the region of metal film 42 exposed from top surface 51 of sealing resin 50 is located away from top surface 51 in first direction z. Alternatively, this region may be flush with top surface 51.

[0073] Next, the effects of the semiconductor device A20 will be described.

[0074] The semiconductor device A20 includes an insulating layer 41 that covers the wiring layer 21, a sealing resin 50 that surrounds at least the semiconductor element 30 as viewed in the first direction z, and a metal film 42 that covers the semiconductor element 30 and includes a portion that is located between the insulating layer 41 and the sealing resin 50. A portion of the insulating layer 41 is located between the wiring layer 21 and the sealing resin 50. Furthermore, the insulating layer 41 is exposed to the outside from a first side surface 52 of the sealing resin 50. Therefore, with this configuration, the semiconductor device A20 can also be miniaturized while reducing noise. Furthermore, by having a configuration common to the semiconductor device A10, the semiconductor device A20 achieves the same effects as the semiconductor device A10.

[0075] In the semiconductor device A20, the metal film 42 is exposed to the outside from the top surface 51 of the sealing resin 50. With this configuration, heat generated from the semiconductor element 30 is dissipated to the outside via the metal film 42 in addition to the heat dissipation layer 23. Therefore, the heat dissipation performance of the semiconductor device A20 can be further improved.

[0076] Third Embodiment: A semiconductor device A30 according to a third embodiment of the present disclosure will be described with reference to FIGS. 27 to 31. In these figures, elements that are the same as or similar to those in the semiconductor device A10 described above are given the same reference numerals, and redundant description will be omitted. Here, for ease of understanding, FIG. 27 shows a perspective view through the sealing resin 50. For ease of understanding, FIG. 28 shows a perspective view of the semiconductor element 30, insulating layer 41, and metal film 42, which are further perspective views than FIG. 27. In FIG. 27, the perspective view of the sealing resin 50 is shown with imaginary lines. In FIG. 28, the perspective view of the semiconductor element 30 and sealing resin 50 is shown with imaginary lines. Furthermore, in FIG. 28, the XXIX-XXIX line and the XXX-XXX line are shown with dashed dotted lines, respectively.

[0077] The semiconductor device A30 differs from the semiconductor device A10 in that it further includes a plurality of protruding layers 25.

[0078] 29 to 31 , the plurality of protruding layers 25 are located on the opposite side of the plurality of terminals 22 with respect to the plurality of wiring layers 21 in the first direction z. Each of the plurality of protruding layers 25 is connected to one of the plurality of wiring layers 21. The plurality of protruding layers 25 are conductors. The composition of the plurality of protruding layers 25 includes copper.

[0079] As shown in Fig. 28 , when viewed in the first direction z, the multiple protruding layers 25 individually overlap the multiple terminals 22. As shown in Figs. 29 to 31 , the insulating layer 41 is located between the multiple protruding layers 25 and the metal film 42 in the first direction z. Therefore, the metal film 42 is separated from the multiple protruding layers 25 via the insulating layer 41.

[0080] 29 to 31 , each of the multiple protruding layers 25 has a sixth exposed surface 251. The sixth exposed surface 251 faces a direction perpendicular to the first direction z. The sixth exposed surface 251 is exposed from the first side surface 52 of the sealing resin 50. The sixth exposed surface 251 is flush with the end surface 211 of any of the multiple wiring layers 21. The sixth exposed surface 251, together with the second exposed surface 222 of any of the multiple terminals 22 and the end surface 211 of any of the multiple wiring layers 21, is covered by any of the multiple covering layers 60.

[0081] Next, the effects of the semiconductor device A30 will be described.

[0082] The semiconductor device A30 includes an insulating layer 41 that covers the wiring layer 21, a sealing resin 50 that surrounds at least the semiconductor element 30 as viewed in the first direction z, and a metal film 42 that covers the semiconductor element 30 and includes a portion that is located between the insulating layer 41 and the sealing resin 50. A portion of the insulating layer 41 is located between the wiring layer 21 and the sealing resin 50. Furthermore, the insulating layer 41 is exposed to the outside from a first side surface 52 of the sealing resin 50. Therefore, with this configuration, the semiconductor device A30 can also be miniaturized while reducing noise. Furthermore, by having a configuration common to the semiconductor device A10, the semiconductor device A30 achieves the same effects as the semiconductor device A10.

[0083] The semiconductor device A30 further includes a protruding layer 25, which is a conductor. The protruding layer 25 is located on the opposite side of the wiring layer 21 from the terminal 22 in the first direction z. As viewed in the first direction z, the protruding layer 25 overlaps the terminal 22. An insulating layer 41 is located between the protruding layer 25 and the metal film 42. The protruding layer 25 is exposed from a first side surface 52 of the sealing resin 50. The portion of the protruding layer 25 exposed from the first side surface 52 is covered by a coating layer 60. This configuration provides electrical insulation between the protruding layer 25 and the metal film 42 while allowing the dimension of the coating layer 60 to be further enlarged in the first direction z. As a result, when the semiconductor device A30 is mounted on a wiring board, the dimension of the solder fillet formed in contact with the coating layer 60 in the first direction z is further enlarged, thereby increasing the volume of the solder fillet. This further improves the bonding strength of the semiconductor device A30 to the wiring board.

[0084] The present disclosure is not limited to the above-described embodiment, and the specific configuration of each part of the present disclosure can be freely modified in various ways.

[0085] The present disclosure includes embodiments described in the following supplementary notes. Supplementary note 1. A semiconductor device comprising: a wiring layer; a semiconductor element having a plurality of electrodes facing the wiring layer, the plurality of electrodes being conductively connected to the wiring layer; an insulating layer covering the wiring layer; a sealing resin located on the opposite side of the insulating layer in a first direction from the wiring layer and surrounding at least the semiconductor element as viewed in the first direction; and a metal film covering the semiconductor element and including a portion located between the insulating layer and the sealing resin, wherein a portion of the insulating layer is located between the wiring layer and the semiconductor element, the sealing resin has a first side surface facing in a direction perpendicular to the first direction, and the insulating layer is exposed to the outside from the first side surface. Supplementary note 2. The semiconductor device according to Supplementary note 1, wherein a maximum dimension of the insulating layer in the first direction is smaller than a maximum dimension of the sealing resin in the first direction. Supplementary note 3. The semiconductor device according to Appendix 2, wherein the plurality of electrodes have a base and a columnar portion protruding from the base toward the wiring layer, and the columnar portion is conductively joined to the wiring layer and in contact with the insulating layer. Appendix 4. The semiconductor device according to Appendix 2 or 3, wherein the insulating layer contains a first filler, the sealing resin contains a second filler, and the weight percentage of the first filler in the insulating layer is lower than the weight percentage of the second filler in the sealing resin. Appendix 5. The semiconductor device according to any of Appendix 2 to 4, wherein the thermal conductivity of the insulating layer is higher than the thermal conductivity of the sealing resin. Appendix 6. The semiconductor device according to any of Appendix 2 to 5, wherein the semiconductor element has a peripheral surface facing in a direction perpendicular to the first direction, and the insulating layer is in contact with the peripheral surface. Appendix 7. The semiconductor device according to Appendix 6, wherein the semiconductor element has a top surface facing the side opposite to the side facing the wiring layer in the first direction, and the insulating layer is in contact with the top surface. Appendix 8. The semiconductor device according to Appendix 6 or 7, wherein the sealing resin has a top surface facing the same side as the upper surface in the first direction, and the metal film is exposed to the outside from the top surface.Appendix 9. The semiconductor device according to any one of Appendixes 2 to 8, wherein the metal film has a composition including copper. Appendix 10. The semiconductor device according to Appendix 9, wherein the metal film has a composition including titanium, and wherein the metal film is exposed to the outside from the first side surface. Appendix 11. The semiconductor device according to Appendix 10, wherein a cavity is provided between the metal film and the sealing resin in the first direction, and wherein the cavity is open to the outside. Appendix 12. The semiconductor device according to any one of Appendixes 1 to 11, further comprising a base material that supports the wiring layer, and wherein the insulating layer is in contact with the base material. Appendix 13. The semiconductor device according to Appendix 12, further comprising a terminal housed in the base material and connected to the wiring layer, the base material having a back surface facing away from the side facing the wiring layer in the first direction, and the terminal being exposed from the back surface. Appendix 14. The semiconductor device according to Appendix 13, wherein the base material has a second side surface facing in a direction perpendicular to the first direction, and the terminal being exposed from the second side surface. Appendix 15. The semiconductor device according to Appendix 14, further comprising a covering layer covering a portion of the terminal exposed from the base material, the covering layer being a conductor, and the composition of the covering layer including gold. Appendix 16. The semiconductor device according to Appendix 15, further comprising a protruding layer located on the opposite side of the terminal with respect to the wiring layer in the first direction, the protruding layer being a conductor, the protruding layer overlapping the terminal as viewed in the first direction, the insulating layer being located between the protruding layer and the metal film, the protruding layer being exposed from the first side surface, and the portion of the protruding layer exposed from the first side surface being covered by the covering layer. Appendix 17. The semiconductor device according to any of Appendixes 13 to 16, further comprising a heat dissipation layer housed in the base material, the heat dissipation layer being connected to the wiring layer, and the heat dissipation layer being exposed from the back surface.

[0086] A10, A20, A30: semiconductor device 10: substrate 11: main surface 12: back surface 13: second side surface 21: wiring layer 21A: ground wiring 211: end surface 212: exposed surface 22: terminal 221: first exposed surface 222: second exposed surface 23: heat dissipation layer 231: third exposed surface 24: dummy terminal 241: fourth exposed surface 242: fifth exposed surface 25: protruding layer 251: sixth exposed surface 30: semiconductor element 301: peripheral surface 31: main body portion 311: upper surface 32: electrode 321: base portion 322: columnar portion 33: passivation film 331: opening 39: bonding layer 391: seat portion 392: bonding portion 41: insulating layer 42: metal film 421: first film 422: Second film 50: Sealing resin 51: Top surface 52: First side surface 521: First region 522: Second region 53: Cavity 54: Opening 60: Covering layer 81: Support member 82: Intermediate layer 83: Conductive layer 84: First resin layer 85: Second resin layer 851: Groove 88: Tape 891: First blade 892: Second blade z: First direction x: Second direction y: Third direction

Claims

1. A wiring layer; a semiconductor element having a plurality of electrodes facing the wiring layer, the plurality of electrodes being conductively connected to the wiring layer; an insulating layer covering the wiring layer; a sealing resin located on an opposite side of the wiring layer with respect to the insulating layer in a first direction and surrounding at least the semiconductor element as viewed in the first direction; a metal film covering the semiconductor element and including a portion located between the insulating layer and the sealing resin; a portion of the insulating layer is located between the wiring layer and the semiconductor element; the sealing resin has a first side surface facing a direction perpendicular to the first direction, The insulating layer is exposed to the outside from the first side surface.

2. The semiconductor device according to claim 1 , wherein a maximum dimension of said insulating layer in said first direction is smaller than a maximum dimension of said sealing resin in said first direction.

3. the plurality of electrodes each have a base and a columnar portion protruding from the base toward the wiring layer; The semiconductor device according to claim 2 , wherein said pillar-shaped portion is conductively joined to said wiring layer and is in contact with said insulating layer.

4. The insulating layer contains a first filler, The sealing resin contains a second filler, The semiconductor device according to claim 2 , wherein a weight percentage of the first filler in the insulating layer is lower than a weight percentage of the second filler in the sealing resin.

5. The semiconductor device according to claim 2 , wherein the thermal conductivity of the insulating layer is higher than the thermal conductivity of the sealing resin.

6. the semiconductor element has a peripheral surface facing a direction perpendicular to the first direction, The semiconductor device according to claim 2 , wherein the insulating layer is in contact with the peripheral surface.

7. the semiconductor element has an upper surface facing a side opposite to a side facing the wiring layer in the first direction; The semiconductor device according to claim 6 , wherein the insulating layer is in contact with the upper surface.

8. the sealing resin has a top surface facing the same side as the upper surface in the first direction, The semiconductor device according to claim 7 , wherein said metal film is exposed to the outside from said top surface.

9. The semiconductor device according to claim 2 , wherein the metal film has a composition containing copper.

10. The composition of the metal film includes titanium, The semiconductor device according to claim 9 , wherein the metal film is exposed to the outside from the first side surface.

11. a cavity is provided between the metal film and the sealing resin in the first direction, The semiconductor device according to claim 10 , wherein the cavity is in communication with the outside.

12. Further comprising a base material supporting the wiring layer, The semiconductor device according to claim 1 , wherein the insulating layer is in contact with the base material.

13. A terminal is further provided that is housed in the base material and connected to the wiring layer. the base material has a back surface facing a side opposite to a side facing the wiring layer in the first direction, The semiconductor device according to claim 12 , wherein the terminal is exposed from the back surface.

14. The substrate has a second side surface facing in a direction perpendicular to the first direction, The semiconductor device according to claim 13 , wherein the terminal is exposed from the second side surface.

15. a covering layer for covering a portion of the terminal exposed from the base material; The coating layer is an electrical conductor, The semiconductor device according to claim 14 , wherein the coating layer has a composition including gold.

16. a protruding layer that is a conductor and is located on the opposite side of the terminal with respect to the wiring layer in the first direction, When viewed in the first direction, the protruding layer overlaps the terminal, The insulating layer is located between the protruding layer and the metal film, the protruding layer is exposed from the first side surface, The semiconductor device according to claim 15 , wherein a portion of the protruding layer exposed from the first side surface is covered with the covering layer.

17. Further comprising a heat dissipation layer housed in the base material, the heat dissipation layer is connected to the wiring layer, The semiconductor device according to claim 13 , wherein the heat dissipation layer is exposed from the back surface.