Semiconductor device

Abstract

This semiconductor device comprises a support layer, a conductive layer, a semiconductor element bonded to the conductive layer, a first coating layer, a second coating layer, and a bonding layer. The bonding layer has a base layer, a third coating layer, and a fourth coating layer. A solid phase bonding layer is formed between the first coating layer and the third coating layer, and between the second coating layer and the fourth coating layer. The Vickers hardness of the base layer is lower than the Vickers hardness of each of the support layer and the conductive layer. The third coating layer and the fourth coating layer each have a first layer, a second layer, and a third layer. The degree of diffusion of the second layer into each of the third layer, the first coating layer, and the second coating layer is greater than the degree of diffusion of the first layer into each of the third layer, the first coating layer, and the second coating layer.

Description

Semiconductor Devices

[0001] The present disclosure relates to semiconductor devices.

[0002] Patent Document 1 discloses an example of a semiconductor device including a circuit layer and a semiconductor element conductively bonded to the circuit layer. The circuit layer includes a first layer and a second layer bonded to the first layer by solid-state bonding. The first layer is bonded to a ceramic substrate. This configuration allows the overall thickness of the circuit layer to be increased while maintaining a good bond between the first and second layers, even when the first layer is a component of an insulating heat dissipation substrate. This facilitates heat conduction in the circuit layer in a direction perpendicular to the stacking direction of the second layer relative to the first layer, thereby improving the efficiency of heat conduction from the circuit layer to the ceramic substrate. This improves the heat dissipation performance of the semiconductor device.

[0003] Here, in order to further improve the heat dissipation performance of the semiconductor device disclosed in Patent Document 1, it is necessary to improve the efficiency of heat conduction at the interface between the first and second layers, which requires strengthening the metallurgical bond at the interface between the first and second layers that occurs through solid-state bonding.

[0004] Japanese Patent Application Laid-Open No. 2017-174927

[0005] An object of the present disclosure is to provide an improved semiconductor device compared to conventional semiconductor devices. In particular, in view of the above circumstances, an object of the present disclosure is to provide a semiconductor device that can improve the heat dissipation performance of the device by strengthening the bond between the support layer and the conductive layer.

[0006] A semiconductor device according to one aspect of the present disclosure includes a support layer, a conductive layer bonded to the support layer, a semiconductor element located on the opposite side of the conductive layer from the support layer and bonded to the conductive layer, a first coating layer located between the support layer and the conductive layer and covering the support layer, a second coating layer located between the first coating layer and the conductive layer and covering the conductive layer, and a bonding layer bonding the first coating layer to the second coating layer. The bonding layer includes a base layer, a third coating layer located between the base layer and the first coating layer, and a fourth coating layer located between the base layer and the second coating layer. A solid-state bonding layer is formed between the first coating layer and the third coating layer and between the second coating layer and the fourth coating layer. The Vickers hardness of the base layer is lower than the Vickers hardness of each of the support layer and the conductive layer. Each of the third coating layer and the fourth coating layer has a first layer covering the base layer, a second layer covering the first layer, and a third layer covering the second layer, and the degree of diffusion of the second layer into each of the third layer, the first coating layer, and the second coating layer is greater than the degree of diffusion of the first layer into each of the third layer, the first coating layer, and the second coating layer.

[0007] According to the above configuration, the bonding state between the support layer and the conductive layer becomes stronger, so that it is possible to improve the heat dissipation properties of the semiconductor device.

[0008] Other features and advantages of the present disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

[0009] FIG. 1 is a perspective view of a semiconductor device according to a first embodiment of the present disclosure. FIG. 2 is a plan view of the semiconductor device shown in FIG. 1. FIG. 3 is a plan view corresponding to FIG. 2, seen through the sealing resin. FIG. 4 is a partial enlarged view of FIG. 3. FIG. 5 is a plan view corresponding to FIG. 2, seen through the first conductive member, and omitting the sealing resin and the second conductive member. FIG. 6 is a right side view of the semiconductor device shown in FIG. 1. FIG. 7 is a bottom view of the semiconductor device shown in FIG. 1. FIG. 8 is a cross-sectional view taken along line VIII-VIII in FIG. 3. FIG. 9 is a cross-sectional view taken along line IX-IX in FIG. 3. FIG. 10 is a partial enlarged view of the first element and its periphery shown in FIG. 9. FIG. 11 is a partial enlarged view of the second element and its periphery shown in FIG. 9. FIG. 12 is a cross-sectional view taken along line XII-XII in FIG. 3. FIG. 13 is a cross-sectional view taken along line XIII-XIII in FIG. 3. FIG. 14 is a partial enlarged view of FIG. 10. FIG. 15 is a partially enlarged cross-sectional view of a semiconductor device according to a second embodiment of the present disclosure. FIG. 16 is a plan view of a semiconductor device according to a third embodiment of the present disclosure, showing a first conductive member and omitting the sealing resin and the second conductive member. FIG. 17 is a cross-sectional view taken along line XVII-XVII in FIG. 16. FIG. 18 is a cross-sectional view taken along line XVIII-XVIII in FIG. 16. FIG. 19 is a cross-sectional view taken along line XIX-XIX in FIG. 16. FIG. 20 is a plan view of a semiconductor device according to a fourth embodiment of the present disclosure, showing a first conductive member and omitting the sealing resin and the second conductive member. FIG. 21 is a cross-sectional view taken along line XXI-XXI in FIG. 20. FIG. 22 is a cross-sectional view taken along line XXII-XXII in FIG. 20. FIG. 23 is a cross-sectional view taken along line XXIII-XXIII in FIG. 20.

[0010] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present disclosure will be described with reference to the accompanying drawings.

[0011] First Embodiment: A semiconductor device A10 according to a first embodiment of the present disclosure will be described with reference to FIGS. 1 to 14 . The semiconductor device A10 includes a substrate 11, two conductive layers 12, two first coating layers 71, two second coating layers 72, two bonding layers 73, a first input terminal 13, an output terminal 14, a second input terminal 15, a plurality of semiconductor elements 21, a first conductive member 31, a second conductive member 32, and a sealing resin 50. The semiconductor device A10 further includes a first signal terminal 161, a second signal terminal 162, a third signal terminal 171, a fourth signal terminal 172, two fifth signal terminals 181, two sixth signal terminals 182, a seventh signal terminal 19, two thermistors 22, and two control wirings 60. For ease of understanding, FIGS. 3 and 4 show the sealing resin 50 in a perspective view. In FIG. 3 , the transparent sealing resin 50 is indicated by an imaginary line (double-dashed line). 5, for ease of understanding, the first conductive member 31 is shown in a perspective view, and the second conductive member 32 and the sealing resin 50 are omitted. In FIG. 5, the first conductive member 31 is shown in a perspective view by imaginary lines.

[0012] For convenience in describing the present disclosure, an example of the normal direction to each of the main surfaces 121 of the two conductive layers 12 described below will be referred to as the "first direction z." An example of a direction perpendicular to the first direction z will be referred to as the "second direction x." An example of a direction perpendicular to the first direction z and the second direction x will be referred to as the "third direction y." In the present disclosure, "as viewed in the first direction z" corresponds to "in a planar view."

[0013] The semiconductor device A10 converts a DC power supply voltage applied to the first input terminal 13 and the second input terminal 15 into AC power using the semiconductor element 21. The converted AC power is input from the output terminal 14 to a power supply target such as a motor.

[0014] As shown in FIGS. 9 to 11 , the substrate 11 is located on the opposite side of the semiconductor elements 21 from the two conductive layers 12 in the first direction z. The substrate 11 supports the two conductive layers 12. The substrate 11 is obtained, for example, from a DBC (Direct Bonded Copper) substrate. As shown in FIGS. 9 to 11 , the substrate 11 includes an insulating layer 111, two support layers 112, and a heat dissipation layer 113. The substrate 11 is covered with a sealing resin 50 except for a portion of the heat dissipation layer 113.

[0015] As shown in FIGS. 9 to 11 , the insulating layer 111 is located on the opposite side of the two conductive layers 12 in the first direction z with respect to the two support layers 112. The insulating layer 111 is made of a material with high thermal conductivity. The insulating layer 111 is, for example, a ceramic plate containing aluminum nitride (AlN). In addition to a ceramic plate, the insulating layer 111 may also be an insulating resin sheet containing a filler with high thermal conductivity. The thickness of the insulating layer 111 is smaller than the thickness of each of the two conductive layers 12. In the present disclosure, the dimension in the first direction z is referred to as the "thickness."

[0016] 9 to 11 , the two support layers 112 are located between the insulating layer 111 and the two conductive layers 12. The two support layers 112 are spaced apart from each other in the second direction x. The two support layers 112 are bonded to the insulating layer 111. The two support layers 112 contain copper (Cu). As shown in FIG. 5 , when viewed in the first direction z, each of the two support layers 112 is surrounded by a periphery 111A of the insulating layer 111.

[0017] As shown in FIGS. 9 to 11 , the heat dissipation layer 113 is located on the opposite side of the insulating layer 111 from the two support layers 112. The heat dissipation layer 113 is bonded to the insulating layer 111. The heat dissipation layer 113 contains copper. As shown in FIG. 7 , the heat dissipation layer 113 is exposed to the outside from the sealing resin 50. The thickness of the heat dissipation layer 113 is greater than the thickness of the insulating layer 111. Furthermore, the thickness of the heat dissipation layer 113 is equal to or greater than the thickness of each of the two support layers 112. When viewed in the first direction z, the heat dissipation layer 113 is surrounded by the periphery 111A of the insulating layer 111 and overlaps the entirety of each of the two support layers 112.

[0018] As shown in FIGS. 9 to 11 , the two conductive layers 12 are individually bonded to two support layers 112. The two conductive layers 12 include a first conductive layer 12A and a second conductive layer 12B that are spaced apart from each other in the second direction x. The two conductive layers 12 contain copper. The thickness of each of the two conductive layers 12 is greater than the thickness of each of the two support layers 112. As shown in FIG. 5 , the two conductive layers 12 are individually surrounded by the peripheries 112A of the two support layers 112 when viewed in the first direction z.

[0019] 8 and 9 , each of the two conductive layers 12 has a main surface 121 and a back surface 122 that face opposite each other in the first direction z. The main surface 121 faces one of the multiple semiconductor elements 21. The back surface 122 faces one of the two support layers 112. When viewed in the first direction z, the back surface 122 is surrounded by the periphery 112A of one of the two support layers 112. In each of the two conductive layers 12, the area of ​​the back surface 122 is equal to the area of ​​the main surface 121.

[0020] As shown in Figures 10 and 11, the two first coating layers 71 are located between the two support layers 112 and the two conductive layers 12, and individually cover the two support layers 112. The two first coating layers 71 contain either silver (Ag) or gold (Au). When each of the two first coating layers 71 contains silver, the thermal conductivity of each of the two first coating layers 71 is higher than the thermal conductivity of each of the two support layers 112 and the two conductive layers 12. The two first coating layers 71 can be formed, for example, by forming a thin metal film by sputtering that individually covers the two support layers 112.

[0021] As shown in Figures 10 and 11, the two second coating layers 72 are located between the two first coating layers 71 and the two conductive layers 12, and individually cover the back surfaces 122 of the two conductive layers 12. The two second coating layers 72 contain either silver or gold. When each of the two second coating layers 72 contains silver, the thermal conductivity of each of the two second coating layers 72 is higher than the thermal conductivity of each of the two support layers 112 and the two conductive layers 12. The two second coating layers 72 can be formed, for example, by depositing a thin metal film by sputtering that individually covers the two support layers 112.

[0022] 10 and 11 , the two bonding layers 73 individually bond the two first coating layers 71 and the two second coating layers 72. Therefore, the two bonding layers 73 are individually sandwiched between the two first coating layers 71 and the two second coating layers 72.

[0023] As shown in FIG. 14 , each of the two bonding layers 73 includes a base layer 731, a third coating layer 732, and a fourth coating layer 733. The base layer 731 is sandwiched between the third coating layer 732 and the fourth coating layer 733. The Vickers hardness of the base layer 731 is lower than the Vickers hardness of each of the two support layers 112 and the two conductive layers 12. The base layer 731 contains aluminum (Al). The third coating layer 732 is located between the base layer 731 and one of the two first coating layers 71. The fourth coating layer 733 is located between the base layer 731 and one of the two second coating layers 72.

[0024] In the semiconductor device A10, two second coating layers 72 are individually bonded to two first coating layers 71 by solid-state bonding via two bonding layers 73. Solid-state bonding is performed under relatively high temperature and pressure conditions. As a result, a solid-state bonding layer 74 (see FIG. 14 ) is formed between one of the two first coating layers 71 and one of the two second coating layers 72 bonded thereto via one of the two bonding layers 73. The solid-state bonding layer 74 is a metallic bonding layer located at the interface of two adjacent metal layers that are bonded together by solid-state bonding. The solid-state bonding layer 74 does not necessarily exist as a metallic bonding layer with a definite thickness. The solid-state bonding layer 74 may be identified as a region where impurities or voids introduced during solid-state bonding remain along the interface of the two metal layers.

[0025] 14 , the solid-state bonding layer 74 includes a first bonding layer 74A and a second bonding layer 74B. The first bonding layer 74A is located between one of the two first coating layers 71 and the third coating layer 732 of one of the two bonding layers 73 facing it. The second bonding layer 74B is located between one of the two second coating layers 72 and the fourth coating layer 733 of one of the two bonding layers 73 facing it.

[0026] As shown in FIG. 14 , in each of the two bonding layers 73, the third coating layer 732 and the fourth coating layer 733 each have a first layer 751, a second layer 752, and a third layer 753. The first layer 751 covers the base layer 731. The first layer 751 contains nickel (Ni). The second layer 752 covers the first layer 751. The second layer 752 contains copper. That is, the second layer 752 contains the metals contained in the two support layers 112 and the two conductive layers 12. Therefore, the Vickers hardness of the first layer 751 is greater than the Vickers hardness of the second layer 752. The third layer 753 covers the second layer 752. The third layer 753 faces either one of the two first coating layers 71 or the two second coating layers 72. When the two first coating layers 71 and the two second coating layers 72 each contain silver, the third layer 753 contains either silver or gold. When the two first coating layers 71 and the two second coating layers 72 each contain gold, the third layer 753 contains silver. When the third layer 753 contains silver, the thermal conductivity of the third layer 753 is higher than the thermal conductivity of the second layer 752.

[0027] 14 , the first bonding layer 74A is located at the interface between one of the two first coating layers 71 and the opposing third layer 753 of the third coating layer 732. The second bonding layer 74B is located at the interface between one of the two second coating layers 72 and the opposing third layer 753 of the fourth coating layer 733.

[0028] As the solid-phase bonding layer 74 is formed, a portion of the metal constituting the second layer 752 diffuses mainly into the third layer 753. The degree of diffusion of the second layer 752 into the third layer 753, each of the two first coating layers 71, and each of the two second coating layers is greater than the degree of diffusion of the first layer 751 into the third layer 753, each of the two first coating layers 71, and each of the two second coating layers. The third coating layer 732 and the fourth coating layer 733, each of which has the first layer 751, the second layer 752, and the third layer 753, can be formed, for example, by depositing and stacking a plurality of metal thin films on both sides of the base layer 731 in the first direction z by a sputtering method.

[0029] As shown in FIGS. 5 and 9 , each of the multiple semiconductor elements 21 is mounted on either the first conductive layer 12A or the second conductive layer 12B. The semiconductor element 21 is, for example, a metal-oxide-semiconductor field-effect transistor (MOSFET). Alternatively, the semiconductor element 21 may be a switching element such as an insulated gate bipolar transistor (IGBT), or a diode. In the description of the semiconductor device A10, the semiconductor element 21 is an n-channel MOSFET with a vertical structure. The semiconductor element 21 includes a compound semiconductor substrate. The compound semiconductor substrate contains silicon carbide (SiC).

[0030] 5, in the semiconductor device A10, the multiple semiconductor elements 21 include multiple first elements 21A and multiple second elements 21B. The structure of each of the multiple second elements 21B is the same as the structure of each of the multiple first elements 21A. The multiple first elements 21A are mounted on the main surface 121 of the first conductive layer 12A. The multiple first elements 21A are arranged along the third direction y. The multiple second elements 21B are mounted on the main surface 121 of the second conductive layer 12B. The multiple second elements 21B are arranged along the third direction y.

[0031] As shown in FIGS. 5, 10 and 11, the plurality of semiconductor elements 21 have a first electrode 211, a second electrode 212, a third electrode 213 and a fourth electrode 214.

[0032] 10 and 11 , the first electrode 211 faces either the first conductive layer 12A or the second conductive layer 12B. A current corresponding to the power before being converted by the semiconductor element 21 flows through the first electrode 211. In other words, the first electrode 211 corresponds to the drain electrode of the semiconductor element 21.

[0033] 10 and 11 , the second electrode 212 is located on the opposite side of the first electrode 211 in the first direction z. A current corresponding to the power converted by the semiconductor element 21 flows through the second electrode 212. In other words, the second electrode 212 corresponds to the source electrode of the semiconductor element 21.

[0034] 10 and 11 , the third electrode 213 is located on the same side as the second electrode 212 in the first direction z. A gate voltage for driving the semiconductor element 21 is applied to the third electrode 213. That is, the third electrode 213 corresponds to the gate electrode of the semiconductor element 21. As shown in FIG. 5 , the area of ​​the third electrode 213 is smaller than the area of ​​the second electrode 212 when viewed in the first direction z.

[0035] 5 , the fourth electrode 214 is located on the same side as the second electrode 212 in the first direction z and is located next to the third electrode 213 in the third direction y. The potential of the fourth electrode 214 is equal to the potential of the second electrode 212.

[0036] As shown in FIGS. 10 and 11 , the conductive bonding layer 29 is interposed between either the first conductive layer 12A or the second conductive layer 12B and the first electrode 211 of one of the multiple semiconductor elements 21. The conductive bonding layer 29 is, for example, solder. Alternatively, the conductive bonding layer 29 may include a sintered body of metal particles. The first electrodes 211 of the multiple first elements 21A are conductively bonded to the main surface 121 of the first conductive layer 12A via the conductive bonding layer 29. As a result, the first electrodes 211 of the multiple first elements 21A are electrically connected to the first conductive layer 12A. The first electrodes 211 of the multiple second elements 21B are conductively bonded to the main surface 121 of the second conductive layer 12B via the conductive bonding layer 29. As a result, the first electrodes 211 of the multiple second elements 21B are electrically connected to the second conductive layer 12B.

[0037] As shown in FIGS. 3 and 9 , the first input terminal 13 is located on the opposite side of the second conductive layer 12B in the second direction x, sandwiching the first conductive layer 12A therebetween, and is connected to the first conductive layer 12A. This allows the first input terminal 13 to be electrically connected to the first electrodes 211 of the multiple first elements 21A via the first conductive layer 12A. The first input terminal 13 is a P terminal (positive electrode) to which a DC power supply voltage to be converted is applied. The first input terminal 13 extends from the first conductive layer 12A in the second direction x. The first input terminal 13 has a covering portion 13A and an exposed portion 13B. As shown in FIG. 9 , the covering portion 13A is connected to the first conductive layer 12A and is covered with a sealing resin 50. The covering portion 13A is flush with the main surface 121 of the first conductive layer 12A. The exposed portion 13B extends from the covered portion 13A in the second direction x and is exposed from the sealing resin 50 .

[0038] As shown in FIGS. 3 and 8 , the output terminal 14 is located on the opposite side of the first conductive layer 12A in the second direction x, with the second conductive layer 12B sandwiched therebetween, and is connected to the second conductive layer 12B. This allows the output terminal 14 to be electrically connected to the first electrodes 211 of the plurality of second elements 21B via the second conductive layer 12B. The output terminal 14 outputs AC power converted by the semiconductor elements 21. In the semiconductor device A10, the output terminal 14 includes two regions spaced apart from each other in the third direction y. Alternatively, the output terminal 14 may have a single structure without two regions. The output terminal 14 includes a covering portion 14A and an exposed portion 14B. As shown in FIG. 8 , the covering portion 14A is connected to the second conductive layer 12B and covered with a sealing resin 50. The covering portion 14A is flush with the main surface 121 of the second conductive layer 12B. The exposed portion 14B extends from the covered portion 14A in the second direction x and is exposed from the sealing resin 50.

[0039] As shown in FIGS. 3 and 8 , the second input terminal 15 is located on the same side as the first input terminal 13 with respect to the first conductive layer 12A and the second conductive layer 12B in the second direction x, but is spaced apart from the first conductive layer 12A and the second conductive layer 12B. The second input terminal 15 is electrically connected to the second electrodes 212 of the plurality of second elements 21B. The second input terminal 15 is an N terminal (negative electrode) to which a DC power supply voltage to be converted is applied. The second input terminal 15 includes two regions spaced apart from each other in the third direction y. The first input terminal 13 is located between the two regions in the third direction y. The second input terminal 15 has a covering portion 15A and an exposed portion 15B. As shown in FIG. 8 , the covering portion 15A is spaced apart from the first conductive layer 12A and is covered with sealing resin 50. The exposed portion 15B extends from the covering portion 15A in the second direction x and is exposed from the sealing resin 50.

[0040] The two control wirings 60 constitute part of the conductive paths between the first signal terminal 161, the second signal terminal 162, the third signal terminal 171, the fourth signal terminal 172, the two fifth signal terminals 181, and the two sixth signal terminals 182 and the plurality of semiconductor elements 21. As shown in FIGS. 3 to 5 , the two control wirings 60 include a first wiring 601 and a second wiring 602. In the second direction x, the first wiring 601 is located between the plurality of first elements 21A and the first input terminal 13 and the second input terminal 15. The first wiring 601 is bonded to the main surface 121 of the first conductive layer 12A. The first wiring 601 also constitutes part of the conductive path between the seventh signal terminal 19 and the first conductive layer 12A. In the second direction x, the second wiring 602 is located between the plurality of second elements 21B and the output terminal 14. The second wiring 602 is bonded to the main surface 121 of the second conductive layer 12B. As shown in Figures 10 and 11 , the two control wirings 60 have an insulating layer 61, multiple wiring layers 62, an intermediate layer 63, and multiple sleeves 64. The two control wirings 60 are covered with the sealing resin 50 except for a portion of each of the multiple sleeves 64.

[0041] 10 and 11 , the insulating layer 61 includes a portion interposed between the plurality of wiring layers 62 and the intermediate layer 63 in the first direction z. The insulating layer 61 is made of, for example, ceramics. The insulating layer 61 may be made of an insulating resin sheet instead of ceramics.

[0042] 10 and 11 , the multiple wiring layers 62 are located on one side of the insulating layer 61 in the first direction z. The multiple wiring layers 62 contain copper. As shown in Fig. 5 , the multiple wiring layers 62 include a first wiring layer 621, a second wiring layer 622, two third wiring layers 623, a fourth wiring layer 624, and a fifth wiring layer 625. The two third wiring layers 623 are adjacent to each other in the third direction y.

[0043] 10 and 11 , the intermediate layer 63 is located on the opposite side of the multiple wiring layers 62 in the first direction z, with the insulating layer 61 sandwiched therebetween. The intermediate layer 63 contains copper. The intermediate layer 63 of the first wiring 601 is bonded to the main surface 121 of the first conductive layer 12A by a first bonding layer 68. The intermediate layer 63 of the second wiring 602 is bonded to the main surface 121 of the second conductive layer 12B by a first bonding layer 68. The first bonding layer 68 is made of a material that may or may not be conductive. The first bonding layer 68 is, for example, solder.

[0044] As shown in FIGS. 10 and 11 , each of the multiple sleeves 64 is bonded to one of the multiple wiring layers 62 by a second bonding layer 69. The multiple sleeves 64 are made of a conductive material such as metal. Each of the multiple sleeves 64 has a cylindrical shape extending along the first direction z. One end of the multiple sleeves 64 is conductively bonded to one of the multiple wiring layers 62. As shown in FIGS. 2 and 9 , an end surface 641 corresponding to the other end of each of the multiple sleeves 64 is exposed from the top surface 51 of the sealing resin 50, which will be described later. The second bonding layer 69 is conductive. The second bonding layer 69 is, for example, solder.

[0045] As shown in FIG. 4 , one of the two thermistors 22 is conductively joined to two third wiring layers 623 of the first wiring 601. As shown in FIG. 4 , the other of the two thermistors 22 is conductively joined to two third wiring layers 623 of the second wiring 602. The two thermistors 22 are, for example, NTC (Negative Temperature Coefficient) thermistors. NTC thermistors have the characteristic of gradually decreasing resistance as temperature increases. The two thermistors 22 are used as temperature detection sensors for the semiconductor device A10.

[0046] As shown in FIG. 1 , the first signal terminal 161, the second signal terminal 162, the third signal terminal 171, the fourth signal terminal 172, the two fifth signal terminals 181, the two sixth signal terminals 182, and the seventh signal terminal 19 are formed as metal pins extending in the first direction z. These terminals protrude from the top surface 51 of the sealing resin 50, which will be described later. Furthermore, these terminals are individually press-fitted into the multiple sleeves 64 of the two control wires 60. As a result, each of these terminals is supported by one of the multiple sleeves 64 and is electrically connected to one of the multiple wiring layers 62.

[0047] 5 and 10 , the first signal terminal 161 is press-fitted into one of the multiple sleeves 64 of the two control wires 60 that is joined to the first wiring layer 621 of the first wire 601. As a result, the first signal terminal 161 is supported by the sleeve 64 and is electrically connected to the first wiring layer 621 of the first wire 601. Furthermore, the first signal terminal 161 is electrically connected to the third electrodes 213 of the multiple first elements 21A. A gate voltage for driving the multiple first elements 21A is applied to the first signal terminal 161.

[0048] 5 and 11 , the second signal terminal 162 is press-fitted into one of the multiple sleeves 64 of the two control wires 60 that is joined to the first wiring layer 621 of the second wire 602. As a result, the second signal terminal 162 is supported by the sleeve 64 and is electrically connected to the first wiring layer 621 of the second wire 602. Furthermore, the second signal terminal 162 is electrically connected to the third electrodes 213 of the multiple second elements 21B. A gate voltage for driving the multiple second elements 21B is applied to the second signal terminal 162.

[0049] As shown in Fig. 2 , the third signal terminal 171 is located next to the first signal terminal 161 in the third direction y. As shown in Fig. 5 , the third signal terminal 171 is press-fitted into one of the multiple sleeves 64 of the two control wires 60 that is joined to the second wiring layer 622 of the first wire 601. As a result, the third signal terminal 171 is supported by the sleeve 64 and is electrically connected to the second wiring layer 622 of the first wire 601. Furthermore, the third signal terminal 171 is electrically connected to the fourth electrodes 214 of the multiple first elements 21A. A voltage corresponding to the maximum current among the currents flowing through the fourth electrodes 214 of the multiple first elements 21A is applied to the third signal terminal 171.

[0050] As shown in FIG. 2 , the fourth signal terminal 172 is located next to the second signal terminal 162 in the third direction y. As shown in FIG. 5 , the fourth signal terminal 172 is press-fitted into one of the multiple sleeves 64 of the two control wires 60 that is joined to the second wiring layer 622 of the second wire 602. As a result, the fourth signal terminal 172 is supported by the sleeve 64 and is electrically connected to the second wiring layer 622 of the second wire 602. Furthermore, the fourth signal terminal 172 is electrically connected to the fourth electrodes 214 of the multiple second elements 21B. A voltage corresponding to the maximum current among the currents flowing through the fourth electrodes 214 of the multiple second elements 21B is applied to the fourth signal terminal 172.

[0051] As shown in FIG. 2 , the two fifth signal terminals 181 are located on the opposite side of the third signal terminal 171 in the third direction y, with the first signal terminal 161 sandwiched between them. The two fifth signal terminals 181 are adjacent to each other in the third direction y. As shown in FIG. 5 , the two fifth signal terminals 181 are individually press-fitted into two of the multiple sleeves 64 of the two control wires 60 that are joined to the two third wiring layers 623 of the first wire 601. As a result, the two fifth signal terminals 181 are supported by the two sleeves 64 and are electrically connected to the two third wiring layers 623 of the first wire 601. Furthermore, the two fifth signal terminals 181 are electrically connected to the thermistors 22 that are electrically connected to the two third wiring layers 623 of the first wire 601, out of the two thermistors 22.

[0052] As shown in FIG. 2 , the two sixth signal terminals 182 are located on the opposite side of the fourth signal terminal 172 in the third direction y, with the second signal terminal 162 sandwiched therebetween. The two sixth signal terminals 182 are adjacent to each other in the third direction y. As shown in FIG. 5 , the two sixth signal terminals 182 are individually press-fitted into two of the sleeves 64 of the two control wires 60 that are joined to the two third wiring layers 623 of the second wire 602. As a result, the two sixth signal terminals 182 are supported by the two sleeves 64 and are electrically connected to the two third wiring layers 623 of the second wire 602. Furthermore, the two sixth signal terminals 182 are electrically connected to the thermistors 22 that are electrically connected to the two third wiring layers 623 of the second wire 602, out of the two thermistors 22.

[0053] As shown in Fig. 2 , the seventh signal terminal 19 is located on the opposite side of the first signal terminal 161 in the third direction y, with the third signal terminal 171 sandwiched therebetween. As shown in Fig. 5 , the seventh signal terminal 19 is press-fitted into one of the multiple sleeves 64 of the two control wires 60 that is joined to the fifth wiring layer 625 of the first wire 601. As a result, the seventh signal terminal 19 is supported by the sleeve 64 and is electrically connected to the fifth wiring layer 625 of the first wire 601. Furthermore, the seventh signal terminal 19 is electrically connected to the first conductive layer 12A. A voltage equivalent to the DC power input to the first input terminal 13 and the second input terminal 15 is applied to the seventh signal terminal 19.

[0054] As shown in FIG. 5 , the multiple first wires 41 are conductively bonded to the third electrodes 213 of the multiple first elements 21A and the fourth wiring layer 624 of the first wiring 601. As shown in FIG. 5 , the multiple third wires 43 are conductively bonded to the fourth wiring layer 624 of the first wiring 601 and the first wiring layer 621 of the first wiring 601. This allows the first signal terminal 161 to be electrically connected to the third electrodes 213 of the multiple first elements 21A. The multiple first wires 41 and the multiple third wires 43 contain gold. Alternatively, the multiple first wires 41 and the multiple third wires 43 may contain copper or aluminum.

[0055] 5, the plurality of first wires 41 are conductively joined to the third electrodes 213 of the plurality of second elements 21B and the fourth wiring layer 624 of the second wiring 602. Furthermore, the plurality of third wires 43 are conductively joined to the fourth wiring layer 624 of the second wiring 602 and the first wiring layer 621 of the second wiring 602. As a result, the second signal terminal 162 is electrically connected to the third electrodes 213 of the plurality of second elements 21B.

[0056] As shown in FIG. 5 , the multiple second wires 42 are conductively bonded to the fourth electrodes 214 of the multiple first elements 21A and the second wiring layer 622 of the first wiring 601. As a result, the third signal terminal 171 is electrically connected to the fourth electrodes 214 of the multiple first elements 21A. Furthermore, as shown in FIG. 5 , the multiple second wires 42 are conductively bonded to the fourth electrodes 214 of the multiple second elements 21B and the second wiring layer 622 of the second wiring 602. As a result, the fourth signal terminal 172 is electrically connected to the fourth electrodes 214 of the multiple second elements 21B. The composition of the multiple second wires 42 includes gold. Alternatively, the composition of the multiple second wires 42 may include copper or aluminum.

[0057] 5, the fourth wire 44 is conductively bonded to the fifth wiring layer 625 of the first wiring 601 and the main surface 121 of the first conductive layer 12A. This allows the seventh signal terminal 19 to be electrically connected to the first conductive layer 12A. The composition of the fourth wire 44 includes gold. Alternatively, the composition of the fourth wire 44 may include copper or aluminum.

[0058] As shown in Figures 5 and 10, the first conductive member 31 is conductively bonded to the second electrodes 212 of the multiple first elements 21A and the main surface 121 of the second conductive layer 12B. This allows the second electrodes 212 of the multiple first elements 21A to be electrically connected to the second conductive layer 12B. The first conductive member 31 contains copper. The first conductive member 31 is a metal clip. As shown in Figure 5, the first conductive member 31 has a main body 311, multiple first joint portions 312, multiple first connecting portions 313, second joint portions 314, and second connecting portions 315.

[0059] The main body portion 311 forms a main portion of the first conductive member 31. As shown in Fig. 5 , the main body portion 311 extends in the third direction y. As shown in Fig. 9 , the main body portion 311 straddles between the first conductive layer 12A and the second conductive layer 12B.

[0060] 10, the multiple first bonding portions 312 are individually bonded to the second electrodes 212 of the multiple first elements 21A. Each of the multiple first bonding portions 312 faces the second electrode 212 of one of the multiple first elements 21A.

[0061] 5, the plurality of first coupling portions 313 are connected to the main body portion 311 and the plurality of first bonding portions 312. The plurality of first coupling portions 313 are spaced apart from one another in the third direction y. As shown in Fig. 9, when viewed in the third direction y, the plurality of first coupling portions 313 are inclined in a direction away from the main surface 121 of the first conductive layer 12A as they extend from the plurality of first bonding portions 312 toward the main body portion 311.

[0062] 5 and 9 , the second bonding portion 314 is bonded to the main surface 121 of the second conductive layer 12B. The second bonding portion 314 faces the main surface 121. The second bonding portion 314 extends in the third direction y. The dimension of the second bonding portion 314 in the third direction y is equal to the dimension of the main body portion 311 in the third direction y.

[0063] 5 and 9 , the second connecting portion 315 is connected to the main body portion 311 and the second bonding portion 314. When viewed in the third direction y, the second connecting portion 315 is inclined in a direction away from the main surface 121 of the second conductive layer 12B as it extends from the second bonding portion 314 toward the main body portion 311. The dimension of the second connecting portion 315 in the third direction y is equal to the dimension of the main body portion 311 in the third direction y.

[0064] 9, 10, and 13, the semiconductor device A10 further includes a first conductive bonding layer 33. The first conductive bonding layer 33 is interposed between the second electrodes 212 of the plurality of first elements 21A and the plurality of first bonding portions 312. The first conductive bonding layer 33 conductively bonds the second electrodes 212 of the plurality of first elements 21A to the plurality of first bonding portions 312. The first conductive bonding layer 33 is, for example, solder. Alternatively, the first conductive bonding layer 33 may include a sintered body of metal particles.

[0065] 9, the semiconductor device A10 further includes a second conductive bonding layer 34. The second conductive bonding layer 34 is interposed between the main surface 121 of the second conductive layer 12B and the second bonding portion 314. The second conductive bonding layer 34 conductively bonds the main surface 121 and the second bonding portion 314. The second conductive bonding layer 34 is, for example, solder. Alternatively, the second conductive bonding layer 34 may include a sintered body of metal particles.

[0066] As shown in FIGS. 4 and 11 , the second conductive member 32 is conductively joined to the second electrodes 212 of the plurality of second elements 21B and the coating portion 15A of the second input terminal 15. This electrically connects the second electrodes 212 of the plurality of second elements 21B to the second input terminal 15. The second conductive member 32 contains copper. The second conductive member 32 is a metal clip. As shown in FIG. 4 , the second conductive member 32 has two main body portions 321, a plurality of third joint portions 322, a plurality of third connecting portions 323, two fourth joint portions 324, two fourth connecting portions 325, a plurality of intermediate portions 326, and a plurality of cross beam portions 327.

[0067] As shown in Fig. 4, the two main bodies 321 are spaced apart from each other in the third direction y. The two main bodies 321 extend in the second direction x. As shown in Fig. 8, the two main bodies 321 are arranged parallel to the main surface 121 of the first conductive layer 12A and the main surface 121 of the second conductive layer 12B. The two main bodies 321 are spaced apart from each other from the main surface 121 and the main surface 121 relative to the main body 311 of the first conductive member 31.

[0068] 4 , the intermediate portions 326 are spaced apart from one another in the third direction y and are located between the two main body portions 321 in the third direction y. The intermediate portions 326 extend in the second direction x. The dimension of each of the intermediate portions 326 in the second direction x is smaller than the dimension of each of the two main body portions 321 in the second direction x.

[0069] 11 , the plurality of third joints 322 are individually joined to the second electrodes 212 of the plurality of second elements 21B. Each of the plurality of third joints 322 faces the second electrode 212 of one of the plurality of second elements 21B.

[0070] 4 and 12 , the multiple third connecting portions 323 are connected to both sides of the multiple third joint portions 322 in the third direction y. Furthermore, the multiple third connecting portions 323 are connected to either of the two main body portions 321 and the multiple intermediate portions 326. When viewed in the second direction x, each of the multiple third connecting portions 323 is inclined in a direction away from the main surface 121 of the second conductive layer 12B as it moves from either of the multiple third joint portions 322 to either of the two main body portions 321 or the multiple intermediate portions 326.

[0071] 4 and 8, the two fourth joint portions 324 are joined to the covering portion 15A of the second input terminal 15. The two fourth joint portions 324 face the covering portion 15A.

[0072] 4 and 8 , the two fourth connecting portions 325 are connected to the two main body portions 321 and the two fourth joint portions 324. When viewed in the third direction y, the two fourth connecting portions 325 are inclined in a direction away from the main surface 121 of the first conductive layer 12A as they move from the two fourth joint portions 324 toward the two main body portions 321.

[0073] As shown in FIGS. 4 and 13 , the multiple cross beam portions 327 are arranged along the third direction y. As viewed in the first direction z, the multiple cross beam portions 327 include regions that individually overlap the multiple first joint portions 312 of the first conductive member 31. Of the multiple cross beam portions 327, the cross beam portion 327 located at the center in the third direction y is connected to the multiple intermediate portions 326 on both sides in the third direction y. Of the multiple cross beam portions 327, the remaining two cross beam portions 327 are connected to one of the two main body portions 321 and one of the multiple intermediate portions 326 on both sides in the third direction y. As viewed in the second direction x, the multiple cross beam portions 327 are convex in the first direction z toward the main surface 121 of the first conductive layer 12A.

[0074] 9, 11, and 12, the semiconductor device A10 further includes a third conductive bonding layer 35. The third conductive bonding layer 35 is interposed between the second electrodes 212 of the plurality of second elements 21B and the plurality of third bonding portions 322. The third conductive bonding layer 35 conductively bonds the second electrodes 212 of the plurality of second elements 21B to the plurality of third bonding portions 322. The third conductive bonding layer 35 is, for example, solder. Alternatively, the third conductive bonding layer 35 may include a sintered body of metal particles.

[0075] 8, the semiconductor device A10 further includes a fourth conductive bonding layer 36. The fourth conductive bonding layer 36 is interposed between the covering portion 15A of the second input terminal 15 and the two fourth bonding portions 324. The fourth conductive bonding layer 36 conductively bonds the covering portion 15A to the two fourth bonding portions 324. The fourth conductive bonding layer 36 is, for example, solder. Alternatively, the fourth conductive bonding layer 36 may include a sintered body of metal particles.

[0076] As shown in FIGS. 8 , 9 , 12 , and 13 , the sealing resin 50 covers the two support layers 112, the two conductive layers 12, the plurality of semiconductor elements 21, the first conductive member 31, and the second conductive member 32. The sealing resin 50 also covers a portion of each of the first input terminal 13, the output terminal 14, and the second input terminal 15. The sealing resin 50 has electrical insulation properties. The sealing resin 50 is made of a material containing, for example, black epoxy resin. As shown in FIGS. 2 and 6 to 9 , the sealing resin 50 has a top surface 51, a bottom surface 52, two first side surfaces 53, two second side surfaces 54, and two recesses 55.

[0077] 8 and 9 , the top surface 51 faces the same side as the main surfaces 121 of the two conductive layers 12 in the first direction z. As shown in Fig. 8 and 9 , the bottom surface 52 faces the opposite side to the top surface 51 in the first direction z. As shown in Fig. 7 , the heat dissipation layer 113 is exposed to the outside from the bottom surface 52.

[0078] 2 and 6 , the two first side surfaces 53 are spaced apart from each other in the second direction x. The two first side surfaces 53 face the second direction x and extend in the third direction y. The two first side surfaces 53 are connected to the top surface 51. An exposed portion 13B of the first input terminal 13 and an exposed portion 15B of the second input terminal 15 are exposed from one of the two first side surfaces 53. An exposed portion 14B of the output terminal 14 is exposed from the other of the two first side surfaces 53.

[0079] 2 and 7 , the two second side surfaces 54 are spaced apart from each other in the third direction y. The two second side surfaces 54 face opposite each other in the third direction y and extend in the second direction x. The two second side surfaces 54 are connected to the top surface 51 and the bottom surface 52.

[0080] 2 and 7 , the two recesses 55 are recessed in the second direction x from the first side surfaces 53 on which the exposed portion 13B of the first input terminal 13 and the exposed portion 15B of the second input terminal 15 are exposed. The two recesses 55 extend from the top surface 51 to the bottom surface 52 in the first direction z. The two recesses 55 are located on both sides of the first input terminal 13 in the third direction y.

[0081] Next, the effects of the semiconductor device A10 will be described.

[0082] The semiconductor device A10 includes a support layer 112, a conductive layer 12, a semiconductor element 21 bonded to the conductive layer 12, a first coating layer 71 covering the support layer 112, a second coating layer 72 covering the conductive layer 12, and a bonding layer 73 bonding the first coating layer 71 and the second coating layer 72. The bonding layer 73 has a base layer 731, a third coating layer 732, and a fourth coating layer 733. A solid-state bonding layer 74 is formed between the first coating layer 71 and the third coating layer 732 and between the second coating layer 72 and the fourth coating layer 733. The Vickers hardness of the base layer 731 is lower than the Vickers hardness of each of the support layer 112 and the conductive layer 12. With this configuration, when the conductive layer 12 is joined to the support layer 112 by solid-state welding via the joining layer 73, the deformability of the base layer 731 is greater than the deformability of each of the support layer 112 and the conductive layer 12, so the contact area of ​​the joining layer 73 with each of the first coating layer 71 and the second coating layer 72, i.e., the bonding area in the solid-state joining layer 74, becomes larger. This makes the metal bonding in the solid-state joining layer 74 stronger.

[0083] Furthermore, in semiconductor device A10, third coating layer 732 and fourth coating layer 733 of bonding layer 73 each have a first layer 751, a second layer 752, and a third layer 753. The degree of diffusion of second layer 752 into third layer 753, first coating layer 71, and second coating layer 72 is greater than the degree of diffusion of first layer 751 into third layer 753, first coating layer 71, and second coating layer 72. With this configuration, solid-phase bonding layer 74 is formed at the interface between first coating layer 71 and third coating layer 732 and at the interface between second coating layer 72 and fourth coating layer 733. Furthermore, because the first layer 751 functions as a barrier layer that restricts the diffusion of the second layer 752, the diffusion of the second layer 752 into each of the third layer 753, the first covering layer 71, and the second covering layer 72 is further promoted, thereby further strengthening the metal bond in the solid-phase bonding layer 74. Therefore, with the above configuration, in the semiconductor device A10, the bonding state between the support layer 112 and the conductive layer 12 is stronger, and the heat dissipation performance of the semiconductor device A10 can be improved.

[0084] Each of the first coating layer 71, the second coating layer 72, the third layer 753 of the third coating layer 732, and the third layer 753 of the fourth coating layer 733 preferably contains either silver or gold. Silver and gold each have a higher plastic flow rate than copper. Therefore, this configuration facilitates the formation of the solid-phase bonding layer 74.

[0085] In each of the third coating layer 732 and the fourth coating layer 733, the Vickers hardness of the first layer 751 is greater than the Vickers hardness of the second layer 752. With this configuration, when the conductive layer 12 is joined to the support layer 112 by solid-state welding via the joining layer 73, bending acting on each of the second layer 752 and the third layer 753 around a direction perpendicular to the first direction z is reduced. This makes the distribution of compressive stress acting on the solid-state joining layer 74 more uniform. This contributes to strengthening the metallic bond in the solid-state joining layer 74.

[0086] The thickness of the conductive layer 12 is greater than the thickness of the support layer 112. With this configuration, heat is more easily conducted in the conductive layer 12 in a direction perpendicular to the first direction z, thereby improving the efficiency of heat conduction from the conductive layer 12 to the support layer 112.

[0087] The semiconductor device A10 further includes an insulating layer 111 located on the opposite side of the conductive layer 12 with respect to the support layer 112. The support layer 112 is bonded to the insulating layer 111. This configuration allows the heat dissipation layer 113 located on the opposite side of the support layer 112 with respect to the insulating layer 111 to be bonded to the insulating layer 111. This ensures electrical insulation of the heat dissipation layer 113 from the conductive layer 12 while further improving the heat dissipation performance of the semiconductor device A10.

[0088] As viewed in the first direction z, the conductive layer 12 is surrounded by a periphery 112A of the support layer 112. With this configuration, when the conductive layer 12 is joined to the support layer 112 by solid-state welding via the joining layer 73, the concentration of stress acting on the insulating layer 111 due to bending of the end portion of the conductive layer 12 in a direction perpendicular to the first direction z is reduced. This makes it possible to suppress the occurrence of cracks in the insulating layer 111.

[0089] The thickness of the heat dissipation layer 113 is greater than the thickness of the support layer 112. This configuration can reduce thermal stress acting on the insulating layer 111 when the conductive layer 12 is joined to the support layer 112 by solid-state welding via the joining layer 73. Furthermore, the bending rigidity of the entire substrate 11 including the insulating layer 111, the support layer 112, and the heat dissipation layer 113 is improved, so warping of the substrate 11 can be suppressed.

[0090] Second Embodiment: A semiconductor device A20 according to a second embodiment of the present disclosure will be described with reference to Figure 15. In this figure, elements that are the same as or similar to those in the semiconductor device A10 described above are designated by the same reference numerals, and duplicated explanations will be omitted. Here, the cross-sectional position in Figure 15 is the same as the cross-sectional position in Figure 14 showing the semiconductor device A10.

[0091] In the semiconductor device A20, the configurations of the two first covering layers 71 and the two second covering layers 72 are different from those of the semiconductor device A10.

[0092] 15 , each of the two first coating layers 71 has a fourth layer 754, a fifth layer 755, and a sixth layer 756. The fourth layer 754 covers the support layer 112. The fourth layer 754 contains nickel. Therefore, the metal contained in the fourth layer 754 is the same as the metal contained in the first layer 751 of the third coating layer 732 of one of the two bonding layers 73. The fifth layer 755 covers the fourth layer 754. The fifth layer 755 contains copper. Therefore, the metal contained in the fifth layer 755 is the same as the metal contained in the second layer 752 of the third coating layer 732. The sixth layer 756 covers the fifth layer 755. If the third layer 753 of the third coating layer 732 contains silver, the sixth layer 756 contains either silver or gold. If the third layer 753 of the third coating layer 732 contains gold, the sixth layer 756 contains silver. Therefore, the degree of diffusion of the fifth layer 755 into the sixth layer 756 is greater than the degree of diffusion of the fourth layer 754 into the sixth layer 756.

[0093] 15 , the first bonding layer 74A of the solid-phase bonding layer 74 is located at the interface between the sixth layer 756 and the third layer 753 of the third coating layer 732. The first coating layer 71 having the fourth layer 754, the fifth layer 755, and the sixth layer 756 can be formed by depositing and stacking a plurality of thin metal films by sputtering, for example.

[0094] 15 , each of the two second coating layers 72 includes a seventh layer 757, an eighth layer 758, and a ninth layer 759. The seventh layer 757 covers the back surface 122 of one of the two conductive layers 12. The seventh layer 757 contains nickel. Therefore, the metal contained in the seventh layer 757 is the same as the metal contained in the first layer 751 of the fourth coating layer 733 of one of the two bonding layers 73. The eighth layer 758 covers the seventh layer 757. The eighth layer 758 contains copper. Therefore, the metal contained in the eighth layer 758 is the same as the metal contained in the second layer 752 of the fourth coating layer 733. The ninth layer 759 covers the eighth layer 758. The ninth layer 759 faces the third layer 753 of the fourth coating layer 733. If the third layer 753 of the fourth coating layer 733 contains silver, the ninth layer 759 contains either silver or gold. If the third layer 753 of the fourth coating layer 733 contains gold, the ninth layer 759 contains silver. Therefore, the degree of diffusion of the eighth layer 758 into the ninth layer 759 is greater than the degree of diffusion of the seventh layer 757 into the ninth layer 759.

[0095] 15 , the second bonding layer 74B of the solid-phase bonding layer 74 is located at the interface between the ninth layer 759 and the third layer 753 of the fourth coating layer 733. The second coating layer 72 having the seventh layer 757, the eighth layer 758, and the ninth layer 759 can be formed, for example, by depositing and stacking a plurality of thin metal films by a sputtering method.

[0096] Next, the effects of the semiconductor device A20 will be described.

[0097] The semiconductor device A20 includes a support layer 112, a conductive layer 12, a semiconductor element 21 bonded to the conductive layer 12, a first coating layer 71 covering the support layer 112, a second coating layer 72 covering the conductive layer 12, and a bonding layer 73 bonding the first coating layer 71 and the second coating layer 72. The bonding layer 73 includes a base layer 731, a third coating layer 732, and a fourth coating layer 733. A solid-state bonding layer 74 is formed between the first coating layer 71 and the third coating layer 732 and between the second coating layer 72 and the fourth coating layer 733. The Vickers hardness of the base layer 731 is lower than the Vickers hardness of each of the support layer 112 and the conductive layer 12.

[0098] Furthermore, in the semiconductor device A20, the third coating layer 732 and the fourth coating layer 733 of the bonding layer 73 each include a first layer 751, a second layer 752, and a third layer 753. The degree of diffusion of the second layer 752 into the third layer 753, the first coating layer 71, and the second coating layer 72 is greater than the degree of diffusion of the first layer 751 into the third layer 753, the first coating layer 71, and the second coating layer 72. Therefore, with the above configuration, the bonding between the support layer 112 and the conductive layer 12 is stronger in the semiconductor device A20 as well, thereby improving the heat dissipation performance of the semiconductor device A20. Furthermore, by having a configuration common to the semiconductor device A10, the semiconductor device A20 achieves the same effects as the semiconductor device A10.

[0099] In the semiconductor device A20, the first coating layer 71 has a fourth layer 754, a fifth layer 755, and a sixth layer 756. The metal contained in the fourth layer 754 is the same as the metal contained in the first layer 751 of the third coating layer 732 of the bonding layer 73. The metal contained in the fifth layer 755 is the same as the metal contained in the second layer 752 of the third coating layer 732. The degree of diffusion of the fifth layer 755 into the sixth layer 756 is greater than the degree of diffusion of the fourth layer 754 into the sixth layer 756. This configuration promotes diffusion of the fifth layer 755 into the sixth layer 756 and into the third layer 753 of the third coating layer 732 when the conductive layer 12 is bonded to the support layer 112 by solid-state bonding via the bonding layer 73. This further strengthens the metal bonding in the first bonding layer 74A of the solid-state bonding layer 74.

[0100] In the semiconductor device A20, the second coating layer 72 has a seventh layer 757, an eighth layer 758, and a ninth layer 759. The metal contained in the seventh layer 757 is the same as the metal contained in the first layer 751 of the fourth coating layer 733 of the bonding layer 73. The metal contained in the eighth layer 758 is the same as the metal contained in the second layer 752 of the fourth coating layer 733. The degree of diffusion of the eighth layer 758 into the ninth layer 759 is greater than the degree of diffusion of the seventh layer 757 into the ninth layer 759. This configuration promotes diffusion of the eighth layer 758 into the ninth layer 759 and the third layer 753 of the fourth coating layer 733 when the conductive layer 12 is bonded to the support layer 112 by solid-state bonding via the bonding layer 73. This further strengthens the metallurgical bond in the second bonding layer 74B of the solid-state bonding layer 74.

[0101] Third Embodiment: A semiconductor device A30 according to a third embodiment of the present disclosure will be described with reference to Figures 16 to 19. In these figures, elements that are the same as or similar to those in the semiconductor device A10 described above are given the same reference numerals, and duplicated descriptions will be omitted. For ease of understanding, Figure 16 shows the first conductive member 31 in a perspective view, and omits the second conductive member 32 and the sealing resin 50. In Figure 16, the first conductive member 31 is shown in phantom lines.

[0102] In the semiconductor device A30, the configuration of the two conductive layers 12 is different from that of the semiconductor device A10.

[0103] 16 to 19 , in each of the two conductive layers 12, the area of ​​the main surface 121 is larger than the area of ​​the back surface 122. As viewed in the first direction z, the back surfaces 122 of the two conductive layers 12 are individually surrounded by the peripheries 112A of the two support layers 112. As viewed in the first direction z, the main surface 121 of either of the two conductive layers 12 extends outward beyond the peripheries 112A of either of the two support layers 112 to which that conductive layer 12 is to be joined. As viewed in the first direction z, the two conductive layers 12 are surrounded by the peripheries 111A of the insulating layers 111.

[0104] Next, the effects of the semiconductor device A30 will be described.

[0105] The semiconductor device A30 includes a support layer 112, a conductive layer 12, a semiconductor element 21 bonded to the conductive layer 12, a first coating layer 71 covering the support layer 112, a second coating layer 72 covering the conductive layer 12, and a bonding layer 73 bonding the first coating layer 71 and the second coating layer 72. The bonding layer 73 has a base layer 731, a third coating layer 732, and a fourth coating layer 733. A solid-state bonding layer 74 is formed between the first coating layer 71 and the third coating layer 732 and between the second coating layer 72 and the fourth coating layer 733. The Vickers hardness of the base layer 731 is lower than the Vickers hardness of each of the support layer 112 and the conductive layer 12.

[0106] Furthermore, in semiconductor device A30, third coating layer 732 and fourth coating layer 733 of bonding layer 73 each include first layer 751, second layer 752, and third layer 753. The degree of diffusion of second layer 752 into third layer 753, first coating layer 71, and second coating layer 72 is greater than the degree of diffusion of first layer 751 into third layer 753, first coating layer 71, and second coating layer 72. Therefore, with the above configuration, the bonding between support layer 112 and conductive layer 12 is stronger in semiconductor device A30 as well, thereby improving the heat dissipation performance of semiconductor device A30. Furthermore, by having a configuration common to semiconductor device A10, semiconductor device A30 achieves the same effects as semiconductor device A10.

[0107] As viewed in the first direction z, the back surface 122 of the conductive layer 12 is surrounded by the periphery 112A of the support layer 112. The conductive layer 12 has a main surface 121 facing the semiconductor element 21. The area of ​​the main surface 121 is larger than the area of ​​the back surface 122 of the conductive layer 12. With this configuration, when the conductive layer 12 is joined to the support layer 112 by solid-state welding via the joining layer 73, the area of ​​the main surface 121 can be further enlarged while reducing the concentration of stress acting on the insulating layer 111 due to bending of the end portion of the conductive layer 12 in a direction perpendicular to the first direction z. This increases the degree of freedom in the joining position of the semiconductor element 21 relative to the main surface 121.

[0108] Fourth Embodiment: A semiconductor device A40 according to a fourth embodiment of the present disclosure will be described with reference to Figures 20 to 23. In these figures, elements that are the same as or similar to those in the semiconductor device A10 described above are given the same reference numerals, and duplicated descriptions will be omitted. For ease of understanding, Figure 20 shows the first conductive member 31 in a perspective view, and omits the second conductive member 32 and the sealing resin 50. In Figure 20, the first conductive member 31 is shown in a perspective view with imaginary lines.

[0109] In the semiconductor device A40, the configuration of the two conductive layers 12 differs from that of the semiconductor device A10.

[0110] 20 to 23 , as viewed in the first direction z, the main surface 121 and the back surface 122 of each of the two conductive layers 12 extend outward beyond the peripheral edges 112A of the two support layers 112 to which the conductive layer 12 is to be joined. In each of the two conductive layers 12, the area of ​​the back surface 122 is equal to the area of ​​the main surface 121. As viewed in the first direction z, the two conductive layers 12 are surrounded by the peripheral edge 111A of the insulating layer 111.

[0111] Next, the effects of the semiconductor device A40 will be described.

[0112] The semiconductor device A40 includes a support layer 112, a conductive layer 12, a semiconductor element 21 bonded to the conductive layer 12, a first coating layer 71 covering the support layer 112, a second coating layer 72 covering the conductive layer 12, and a bonding layer 73 bonding the first coating layer 71 and the second coating layer 72. The bonding layer 73 includes a base layer 731, a third coating layer 732, and a fourth coating layer 733. A solid-state bonding layer 74 is formed between the first coating layer 71 and the third coating layer 732 and between the second coating layer 72 and the fourth coating layer 733. The Vickers hardness of the base layer 731 is lower than the Vickers hardness of each of the support layer 112 and the conductive layer 12.

[0113] Furthermore, in semiconductor device A40, third coating layer 732 and fourth coating layer 733 of bonding layer 73 each include first layer 751, second layer 752, and third layer 753. The degree of diffusion of second layer 752 into third layer 753, first coating layer 71, and second coating layer 72 is greater than the degree of diffusion of first layer 751 into third layer 753, first coating layer 71, and second coating layer 72. Therefore, with the above configuration, the bonding between support layer 112 and conductive layer 12 is stronger in semiconductor device A40 as well, thereby improving the heat dissipation performance of semiconductor device A40. Furthermore, by having a configuration common to semiconductor device A10, semiconductor device A40 achieves the same effects as semiconductor device A10.

[0114] The present disclosure is not limited to the above-described embodiment, and the specific configuration of each part of the present disclosure can be freely modified in various ways.

[0115] The present disclosure includes embodiments described in the following supplementary notes. Supplementary note 1. A semiconductor device comprising: a support layer; a conductive layer bonded to the support layer; a semiconductor element located on the opposite side of the conductive layer from the support layer and bonded to the conductive layer; a first coating layer located between the support layer and the conductive layer and covering the support layer; a second coating layer located between the first coating layer and the conductive layer and covering the conductive layer; and a bonding layer bonding the first coating layer and the second coating layer, wherein the bonding layer has a base layer, a third coating layer located between the base layer and the first coating layer, and a fourth coating layer located between the base layer and the second coating layer, wherein a solid-state bonding layer is formed between the first coating layer and the third coating layer and between the second coating layer and the fourth coating layer, and the Vickers hardness of the base layer is lower than the Vickers hardness of each of the support layer and the conductive layer, The semiconductor device, wherein each of the third coating layer and the fourth coating layer has a first layer covering the base layer, a second layer covering the first layer, and a third layer covering the second layer, and wherein a degree of diffusion of the second layer into each of the third layer, the first coating layer, and the second coating layer is greater than a degree of diffusion of the first layer into each of the third layer, the first coating layer, and the second coating layer. Appendix 2. The semiconductor device of Appendix 1, wherein the second layer contains a metal contained in each of the support layer and the conductive layer. Appendix 3. The semiconductor device of Appendix 2, wherein the support layer, the conductive layer, and the second layer each contain copper. Appendix 4. The semiconductor device of Appendix 2 or 3, wherein the first coating layer, the second coating layer, and the third layer each contain either silver or gold. Appendix 5. The semiconductor device of any of Appendix 2 to 4, wherein the base layer contains aluminum. Appendix 6. The semiconductor device of any of Appendix 2 to 5, wherein the Vickers hardness of the first layer is greater than the Vickers hardness of the second layer. Appendix 7. The semiconductor device according to Appendix 6, wherein the first layer contains nickel.Appendix 8. The semiconductor device according to Appendix 6 or 7, wherein the first covering layer has a fourth layer covering the support layer, a fifth layer covering the fourth layer, and a sixth layer covering the fifth layer, wherein the metal contained in the fourth layer is the same as the metal contained in the first layer, the metal contained in the fifth layer is the same as the metal contained in the second layer, and the degree of diffusion of the fifth layer into the sixth layer is greater than the degree of diffusion of the fourth layer into the sixth layer. Appendix 9. The semiconductor device according to Appendix 6, further comprising an insulating layer located on the opposite side of the support layer to the conductive layer, wherein the support layer is bonded to the insulating layer. Appendix 10. The semiconductor device according to Appendix 9, wherein the semiconductor element has a first electrode facing the conductive layer, and the first electrode is conductively bonded to the conductive layer. Appendix 11. The semiconductor device according to Appendix 10, wherein the thickness of the conductive layer is greater than the thickness of the support layer. Appendix 12. The semiconductor device according to Appendix 11, wherein, in a plan view, the conductive layer is surrounded by a periphery of the support layer. Appendix 13. The semiconductor device according to Appendix 11, wherein the conductive layer has a back surface covered with the second covering layer, and wherein, in a plan view, the back surface is surrounded by a periphery of the support layer. Appendix 14. The semiconductor device according to Appendix 13, wherein the conductive layer has a main surface facing the first electrode, and an area of ​​the main surface is larger than an area of ​​the back surface. Appendix 15. The semiconductor device according to any of Appendixes 9 to 14, further comprising a heat dissipation layer located on the opposite side of the insulating layer from the support layer, and the heat dissipation layer is bonded to the insulating layer. Appendix 16. The semiconductor device according to Appendix 15, wherein a thickness of the heat dissipation layer is larger than a thickness of the support layer. Appendix 17. The semiconductor device according to Appendix 15 or 16, further comprising a sealing resin covering the support layer, the conductive layer, and the semiconductor element, and wherein the heat dissipation layer is exposed to the outside from the sealing resin.

[0116] <h2 style=";text-align:left;direction:ltr">1 ...A40: semiconductor device 11: base material 111: insulating layer 111A: periphery 112: support layer 112A: periphery 113: heat dissipation layer 12: conductive layer 12A: first conductive layer 12B: second conductive layer 121: main surface 122: back surface 13: first input terminal 13A: covering portion 13B: exposed portion 14: output terminal 14A: covering portion 14B: exposed portion 15: second input terminal 15A: covering portion 15B: exposed portion 161: first signal terminal 162: second signal terminal 171: third signal terminal 172: fourth signal terminal 181: fifth signal terminal 182: sixth signal terminal 19: seventh signal terminal 21: semiconductor element 21A: first element 21B: second element 211: first electrode 212: Second electrode 213: Third electrode 214: Fourth electrode 22: Thermistor 29: Conductive bonding layer 31: First conductive member 311: Main body 312: First bonding portion 313: First connecting portion 314: Second bonding portion 315: Second connecting portion 32: Second conductive member 321: Main body 322: Third bonding portion 323: Third connecting portion 324: Fourth bonding portion 325: Fourth connecting portion 326: Middle portion 327: Cross beam portion 33: First conductive bonding layer 34: Second conductive bonding layer 35: Third conductive bonding layer 36: Fourth conductive bonding layer 41: First wire 42: Second wire 43: Third wire 44: Fourth wire 50: Sealing resin 51: Top surface 52: Bottom surface 53: First side surface 54: Second side surface 55: Recess 60: Control wiring 601: First wiring 602: Second wiring 61: Insulating layer 62: Wiring layer 621: First wiring layer 622: Second wiring layer 623: Third wiring layer 624: Fourth wiring layer 625: Fifth wiring layer 63: Intermediate layer 64: Sleeve 641: End surface 68: First bonding layer 69: Second bonding layer 71: First covering layer 72: Second covering layer 73: Bonding layer 731: Base layer 732: Third covering layer 733: Fourth covering layer 74: Solid-state bonding layer 74A: First bonding layer 74B: Second bonding layer 751: First layer 752: Second layer 753: Third layer 754: Fourth layer 755: Fifth layer 756: Sixth layer 757: 7th layer 758: 8th layer 759: 9th layer z: first direction x: second direction y: third direction,

Claims

1. The support base and a conductive layer bonded to the support layer; a semiconductor element located on the opposite side of the conductive layer from the support layer and bonded to the conductive layer; a first coating layer located between the support layer and the conductive layer and covering the support layer; a second coating layer located between the first coating layer and the conductive layer and covering the conductive layer; A bonding layer that bonds the first coating layer and the second coating layer, The bonding layer includes a base layer, a third coating layer located between the base layer and the first coating layer, and a fourth coating layer located between the base layer and the second coating layer, a solid-phase bonding layer is formed between the first coating layer and the third coating layer and between the second coating layer and the fourth coating layer, the base layer has a Vickers hardness lower than a Vickers hardness of each of the support layer and the conductive layer; each of the third coating layer and the fourth coating layer includes a first layer covering the base layer, a second layer covering the first layer, and a third layer covering the second layer; A semiconductor device, wherein a degree of diffusion of the second layer into each of the third layer, the first coating layer, and the second coating layer is greater than a degree of diffusion of the first layer into each of the third layer, the first coating layer, and the second coating layer.

2. The semiconductor device according to claim 1 , wherein said second layer includes a metal contained in said supporting layer and said conductive layer.

3. The semiconductor device according to claim 2 , wherein each of said supporting layer, said conductive layer and said second layer contains copper.

4. The semiconductor device according to claim 2 , wherein each of the first coating layer, the second coating layer and the third layer contains either silver or gold.

5. The semiconductor device according to claim 2 , wherein the base layer contains aluminum.

6. 6. The semiconductor device according to claim 2, wherein the first layer has a Vickers hardness greater than a Vickers hardness of the second layer.

7. The semiconductor device according to claim 6 , wherein the first layer contains nickel.

8. the first coating layer has a fourth layer covering the support layer, a fifth layer covering the fourth layer, and a sixth layer covering the fifth layer, the metal contained in the fourth layer is the same as the metal contained in the first layer; the metal contained in the fifth layer is the same as the metal contained in the second layer; 7. The semiconductor device according to claim 6, wherein a degree of diffusion of said fifth layer into said sixth layer is greater than a degree of diffusion of said fourth layer into said sixth layer.

9. The insulating layer is located on the opposite side of the conductive layer with respect to the support layer, 6. The semiconductor device according to claim 1, wherein the support layer is bonded to the insulating layer.

10. the semiconductor element has a first electrode facing the conductive layer; The semiconductor device according to claim 9 , wherein the first electrode is conductively connected to the conductive layer.

11. The semiconductor device according to claim 10 , wherein the conductive layer has a thickness greater than a thickness of the support layer.

12. The semiconductor device according to claim 11 , wherein the conductive layer is surrounded by a periphery of the support layer in a plan view.

13. the conductive layer has a back surface covered with the second coating layer, The semiconductor device according to claim 11 , wherein the back surface is surrounded by a periphery of the support layer in a plan view.

14. the conductive layer has a main surface facing the first electrode, The semiconductor device according to claim 13 , wherein an area of ​​said main surface is larger than an area of ​​said back surface.

15. a heat dissipation layer located on the opposite side of the insulating layer from the support layer, The semiconductor device according to claim 9 , wherein the heat dissipation layer is bonded to the insulating layer.

16. The semiconductor device according to claim 15 , wherein the heat dissipation layer has a thickness greater than a thickness of the support layer.

17. a sealing resin that covers the support layer, the conductive layer, and the semiconductor element, The semiconductor device according to claim 15 , wherein the heat dissipation layer is exposed to the outside from the sealing resin.

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