Shift register

Abstract

The present invention provides a novel signal output circuit. The present invention provides a shift register which has a signal output circuit that comprises a vertical channel transistor. The present invention enables the achievement of a signal output circuit which occupies a small area by using one of the gate-source parasitic capacitance and the gate-drain parasitic capacitance of the vertical channel transistor, the one having a higher capacitance, for a bootstrap capacitor. The present invention is capable of shortening the channel length by using an oxide semiconductor for a semiconductor layer of the vertical channel transistor, thereby enhancing the withstand voltage between the source and the drain. The present invention also enables a stable operation in a high temperature environment.

Description

Shift Register

[0001] One aspect of the invention disclosed in this specification relates to an object, a method, or a manufacturing method. Alternatively, one aspect of the invention disclosed in this specification relates to a process, a machine, a manufacture, or a composition of matter.

[0002] One embodiment of the present invention is not limited to the above technical field. Examples of the technical field of one embodiment of the present invention disclosed in this specification and the like include a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, an electronic device, a lighting device, an input device (for example, a touch sensor), an input / output device (for example, a touch panel), a driving method thereof, or a manufacturing method thereof.

[0003] In this specification, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. It also refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component that houses a chip in a package are examples of semiconductor devices. Furthermore, memory devices, display devices, light-emitting devices, lighting devices, electronic devices, etc. may themselves be semiconductor devices and each may have a semiconductor device.

[0004] In recent years, with the trend toward smaller and lighter electronic devices, there has been an increasing demand for integrated circuits with high density integration of transistors, etc. As one means of integrating transistors at high density, progress has been made in miniaturizing transistors and reducing their occupied area.

[0005] As a semiconductor material applicable to transistors, oxide semiconductors using metal oxides have attracted attention. For example, Patent Literature 1 discloses a semiconductor device in which a plurality of oxide semiconductor layers are stacked, and an oxide semiconductor layer serving as a channel contains indium and gallium, and the proportion of indium is made larger than the proportion of gallium, thereby increasing field-effect mobility (sometimes simply referred to as mobility or μFE).

[0006] JP 2014-7399 A

[0007] An object of one embodiment of the present invention is to provide a semiconductor device that occupies a small area, consumes low power, has high reliability, or provides a novel semiconductor device.

[0008] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Note that problems other than these will become apparent from the description of the specification, drawings, claims, etc., and it is possible to extract other problems from the description of the specification, drawings, claims, etc.

[0009] One aspect of the present invention is a shift register having a plurality of signal output circuits, at least one of which has a first transistor, and which has a function of outputting a first signal via the first transistor, the shift register including: a first conductive layer having a region that functions as one of a source electrode or a drain electrode of the first transistor; a first insulating layer having a region disposed on the first conductive layer; and a second conductive layer having a region that functions as the other of the source electrode or the drain electrode of the first transistor and disposed on the first insulating layer. a first opening penetrating the first insulating layer and the second conductive layer and overlapping the first conductive layer; a first semiconductor layer having a region in contact with the first insulating layer, a region in contact with the first conductive layer, and a region in contact with the second conductive layer; a third conductive layer having a region that functions as a gate electrode of the first transistor; and a second insulating layer having a region that functions as a gate insulating film of the first transistor and that is sandwiched by the first semiconductor layer and the third conductive layer in the first opening, wherein a first signal is input to one of the source electrode or the drain electrode of the first transistor.

[0010] For example, the third conductive layer has a region that overlaps with the first conductive layer in the first opening and a region that overlaps with the second conductive layer on the first insulating layer.

[0011] At least one of the plurality of signal output circuits may include a second transistor. For example, the signal output circuit may include: a fourth conductive layer having a region functioning as one of the source electrode or drain electrode of the second transistor; a first insulating layer having a region disposed on the fourth conductive layer; a fifth conductive layer having a region functioning as the other of the source electrode or drain electrode of the first transistor and having a region disposed on the first insulating layer; a second opening penetrating the first insulating layer and the fifth conductive layer and overlapping the fourth conductive layer; a second semiconductor layer having a region contacting the first insulating layer, a region contacting the fourth conductive layer, and a region contacting the fifth conductive layer; a sixth conductive layer having a region functioning as the gate electrode of the second transistor and disposed on the second insulating layer; and a second insulating layer having a region functioning as the gate insulating film of the second transistor and sandwiched between the second semiconductor layer and the sixth conductive layer at the second opening. Preferably, the fourth conductive layer and the third conductive layer are electrically connected to each other.

[0012] In addition, when the bottom surface of the fourth conductive layer is used as a reference, the height of the top surface of the fourth conductive layer may differ from the height of the bottom surface of the sixth conductive layer. The first semiconductor layer preferably includes an oxide semiconductor. The second semiconductor layer preferably includes an oxide semiconductor.

[0013] According to one embodiment of the present invention, a semiconductor device with a small occupation area, low power consumption, high reliability, or a novel semiconductor device can be provided.

[0014] Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. Note that effects other than these will become apparent from the description in the specification, drawings, claims, etc., and it is possible to extract other effects from the description in the specification, drawings, claims, etc.

[0015] FIG. 1A is a diagram showing an example of a shift register. FIGS. 1B and 1C are diagrams showing an example of a signal output circuit. FIG. 2 is a diagram showing an example of a signal output circuit. FIG. 3 is a diagram showing an example of a signal output circuit. FIG. 4 is a diagram showing an example of a signal output circuit. FIG. 5 is a diagram showing an example of a signal output circuit. FIG. 6 is a diagram showing an example of a signal output circuit. FIG. 7 is a diagram showing an example of a signal output circuit. FIG. 8 is a diagram showing an example of a signal output circuit. FIG. 9 is a diagram showing an example of a signal output circuit. FIG. 10 is a diagram showing an example of a signal output circuit. FIG. 11A is a plan view of a transistor. FIG. 11B is a cross-sectional view of a transistor. FIG. 11C is a perspective view of a transistor. FIG. 11D is an equivalent circuit diagram of a transistor. FIGS. 12A and 12B are cross-sectional views of a transistor. FIGS. 12C to 12F are plan views of openings. FIGS. 13A and 13B are plan views of a transistor. FIG. 14A is a cross-sectional view of a transistor. FIG. 14B is an equivalent circuit diagram of a transistor. FIG. 15A is a plan view of a transistor. FIG. 15B is a cross-sectional view of a transistor. FIG. 15C is a perspective view of a transistor. FIG. 15D is an equivalent circuit diagram of a transistor. FIG. 16A is a plan view of a transistor. FIG. 16B is a cross-sectional view of a transistor. FIG. 16C is a perspective view of a transistor. FIG. 16D is an equivalent circuit diagram of a transistor. FIG. 17 is a plan view of a signal output circuit. FIG. 18 is a plan view of a signal output circuit. FIGS. 19A and 19B are cross-sectional views of the signal output circuit. FIGS. 20A and 20B are cross-sectional views of the signal output circuit. FIGS. 21A and 21B are cross-sectional views of the signal output circuit. FIG. 22 is a diagram showing an example of a signal output circuit. FIG. 23 is a timing chart for explaining an example of operation of the signal output circuit. FIG. 24 is a circuit diagram for explaining an example of operation of the signal output circuit. FIG. 25 is a circuit diagram for explaining an example of operation of the signal output circuit. FIG. 26 is a circuit diagram for explaining an example of operation of the signal output circuit. FIG. 27 is a circuit diagram for explaining an example of operation of the signal output circuit. 28 and 29 are circuit diagrams for explaining an example of the operation of the signal output circuit.FIG. 30 is a circuit diagram for explaining an example of the operation of a signal output circuit. FIG. 31 is a diagram showing an example of a signal output circuit. FIG. 32 is a diagram showing an example of a signal output circuit. FIG. 33 is a timing chart for explaining an example of the operation of a shift register. FIG. 34A is a perspective view of a display device. FIG. 34B is a block diagram of a display device. FIGS. 35A to 35D are circuit diagrams of pixel circuits. FIGS. 36A to 36D are circuit diagrams of pixel circuits. FIGS. 37A and 37B are circuit diagrams of pixel circuits. FIGS. 38A and 38B are circuit diagrams of pixel circuits. FIGS. 39A and 39B are diagrams for explaining an example of the configuration of a drive circuit. FIGS. 40A to 40G are diagrams for an example of a pixel. FIGS. 41A to 41K are diagrams for an example of a pixel. FIGS. 42A to 42F are diagrams for explaining an example of the configuration of a light-emitting device. FIGS. 43A to 43C are diagrams for explaining an example of the configuration of a light-emitting element. FIGS. 44A to 44D are diagrams for explaining an example of the configuration of a light-emitting element. Figs. 45A to 45D are diagrams showing configuration examples of light-emitting elements. Figs. 46A to 46C are diagrams explaining configuration examples of light-emitting elements. Figs. 47A to 47F are diagrams showing an example of an electronic device. Figs. 48A to 48F are diagrams showing an example of an electronic device. Figs. 49A1 and 49A2 are schematic cross-sectional views of transistors. Figs. 49B1 and 49B2 are diagrams showing Id-Vg characteristics of transistors. Figs. 49C1 and 49C2 are diagrams showing Id-Vd characteristics of transistors.

[0016] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be readily understood by those skilled in the art that various modifications in form and detail can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below. In the configuration of the invention described below, the same reference numerals will be used in common between different drawings for the same parts or parts having similar functions, and repeated explanations may be omitted.

[0017] Furthermore, the position, size, range, etc. of each component shown in the drawings may not represent the actual position, size, range, etc. in order to facilitate understanding of the invention. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings, etc. For example, in the actual manufacturing process, layers and resist masks may be unintentionally eroded by processes such as etching, but this may be omitted from the description to facilitate understanding of the invention.

[0018] Furthermore, in this specification and the like, when a resist mask is formed by photolithography and then an etching step (removal step) is performed, the resist mask is removed after the etching step is completed, unless otherwise specified.

[0019] In order to make the invention easier to understand, particularly in plan views (also called "top views") and perspective views, some components may be omitted from the drawings. Also, some hidden lines may be omitted from the drawings.

[0020] In this specification, ordinal numbers such as "first" and "second" are used to avoid confusion between components, and do not indicate any order or ranking, such as the order of processes or stacking. Furthermore, even if a term does not have an ordinal number in this specification, ordinal numbers may be used in the claims to avoid confusion between components. Furthermore, the ordinal numbers used in this specification may differ from those used in the claims. Furthermore, even if a term has an ordinal number in this specification, ordinal numbers may be omitted in the claims.

[0021] Furthermore, the terms "electrode," "wiring," and "terminal" used in this specification do not limit the functionality of these components. For example, "electrode" may be used as part of "wiring," and vice versa. Furthermore, the terms "electrode" and "wiring" include cases where multiple "electrodes" and "wiring" are integrated together. Furthermore, for example, "terminal" may be used as part of "wiring" or "electrode," and vice versa. Furthermore, the term "terminal" includes cases where multiple "electrodes," "wiring," "terminals," etc. are integrated together. Therefore, for example, an "electrode" can be part of a "wiring" or "terminal," and a "terminal" can be part of a "wiring" or "electrode." Furthermore, terms such as "electrode," "wiring," and "terminal" may be interchangeable with terms such as "region" in some cases.

[0022] Furthermore, in this specification and the like, supplying a signal refers to supplying a predetermined potential to a wiring or the like. Therefore, the term "signal" may be replaced with a term such as "potential." Furthermore, the term "potential" may be replaced with "signal." Furthermore, the "signal" may be a variable potential or a fixed potential. For example, it may be a power supply potential.

[0023] It should be noted that the terms "film" and "layer" can be interchangeable in some cases or depending on the situation. For example, the term "conductive layer" can be changed to the term "conductive film." Or, for example, the term "insulating film" can be changed to the term "insulating layer."

[0024] Furthermore, in this specification, a "capacitive element" can refer to, for example, a circuit element having a capacitance value higher than 0 F, a region of wiring having a capacitance value higher than 0 F, a parasitic capacitance, or a gate capacitance of a transistor. The terms "capacitive element," "parasitic capacitance," and "gate capacitance" can sometimes be replaced with the term "capacitance." Conversely, the term "capacitance" can sometimes be replaced with the terms "capacitive element," "parasitic capacitance," and "gate capacitance." A "capacitance" (including a "capacitance" with three or more terminals) includes an insulator and a pair of conductive layers sandwiching the insulator. Therefore, the term "pair of conductive layers" in a "capacitance" can be replaced with "pair of electrodes," "pair of conductive regions," "pair of regions," or "pair of terminals." The term "one of the pair of terminals" can sometimes be referred to as "one terminal" or "first terminal." The term "the other of the pair of terminals" can sometimes be referred to as "the other terminal" or "second terminal." The capacitance value can be, for example, 0.05 fF or more and 10 pF or less. Alternatively, it may be set to, for example, 1 pF or more and 10 μF or less.

[0025] The functions of the "source" and "drain" of a transistor may be interchanged when transistors of different polarities are used, or when the direction of current flow changes during circuit operation, etc. For this reason, the terms "source" and "drain" may be used interchangeably in this specification and the like.

[0026] In this specification and elsewhere, the term "gate" refers to a gate electrode and a part or all of a gate wiring. The gate wiring refers to a wiring for electrically connecting the gate electrode of at least one transistor to another electrode or another wiring.

[0027] In this specification and elsewhere, the term "source" refers to a source region, a source electrode, and part or all of a source wiring. The source region refers to a region of a semiconductor layer whose resistivity is equal to or less than a certain value. The source electrode refers to a conductive layer including a portion connected to the source region. The source wiring refers to wiring for electrically connecting the source electrode of at least one transistor to another electrode or another wiring.

[0028] In this specification and elsewhere, "drain" refers to a drain region, a drain electrode, and part or all of a drain wiring. A drain region refers to a region of a semiconductor layer whose resistivity is equal to or less than a certain value. A drain electrode refers to a conductive layer that includes a portion connected to the drain region. A drain wiring refers to wiring that electrically connects the drain electrode of at least one transistor to another electrode or another wiring.

[0029] Unless otherwise specified, the transistors described in this specification and the like are enhancement-type (normally-off) field-effect transistors. Furthermore, if the transistors described in this specification and the like are n-channel transistors, the threshold voltage (also referred to as "Vth") of the transistors is greater than 0 V unless otherwise specified. Furthermore, if the transistors described in this specification and the like are p-channel transistors, the threshold voltage (also referred to as "Vth") of the transistors is less than or equal to 0 V unless otherwise specified. Furthermore, unless otherwise specified, the Vth of multiple transistors of the same conductivity type is the same.

[0030] In this specification and the like, unless otherwise specified, off-state current refers to a current (also referred to as a "drain current" or "Id") that flows between the source and drain when the transistor is in an off state (also referred to as a "non-conducting state" or "cut-off state"). Unless otherwise specified, the off-state refers to a state in which the potential difference between the gate and the source (also referred to as a "gate voltage" or "Vg") with respect to the source is lower than the threshold voltage in an n-channel transistor, and a state in which Vg is higher than the threshold voltage in a p-channel transistor. For example, the off-state current of an n-channel transistor may refer to the drain current when Vg is lower than Vth.

[0031] In this specification, the term "leakage current" may be used to mean the same thing as "off-state current." In this specification, the term "off-state current" may refer to, for example, a current that flows between the source and drain of a transistor when the transistor is in an off state.

[0032] In this specification and the like, unless otherwise specified, the on-state current refers to Id when a transistor is in an on state (also referred to as a "conducting state"). Unless otherwise specified, the on state refers to a state in which Vg is equal to or greater than Vth for an n-channel transistor, and a state in which Vg is equal to or less than Vth for a p-channel transistor. For example, the on-state current of an n-channel transistor may refer to the drain current when Vg is equal to or greater than Vth.

[0033] In this specification and the like, a high power supply potential VDD (hereinafter also simply referred to as "VDD" or "potential H") refers to a power supply potential that is higher than a low power supply potential VSS. A low power supply potential VSS (hereinafter also simply referred to as "VSS" or "potential L") refers to a power supply potential that is lower than a high power supply potential VDD. A ground potential GND (hereinafter also simply referred to as "GND") can also be used as VDD or VSS. For example, when VDD is GND, VSS is a potential lower than GND, and when VSS is GND, VDD is a potential higher than GND. In this specification and the like, VSS is the reference potential unless otherwise specified.

[0034] In general, "voltage" often refers to the potential difference between a certain potential and a reference potential (for example, ground potential or source potential). Furthermore, "potential" is relative, and the potential applied to wiring, etc., may change depending on the reference potential. Therefore, "voltage" and "potential" can sometimes be used interchangeably.

[0035] In this specification, terms indicating position, such as "above," "below," "upward," or "below" may be used for convenience in describing the positional relationship between components with reference to the drawings. Furthermore, the positional relationship between components may change as appropriate depending on the direction in which each configuration is depicted. Therefore, the terms are not limited to those described in the specification, and may be rephrased appropriately depending on the situation. For example, the expression "an insulating layer located above a conductive layer" can be rephrased as "an insulating layer located below the conductive layer" by rotating the orientation of the drawing 180 degrees. For example, the expression "an insulating layer located above an opening" may include "an insulating layer located on the side of the opening."

[0036] Furthermore, the terms "above" and "below" do not limit the positional relationship of components to being directly above or below and in direct contact with each other. For example, the expression "electrode B on insulating layer A" does not require that electrode B be formed on insulating layer A in direct contact with it, and does not exclude the inclusion of other components between insulating layer A and electrode B.

[0037] In this specification, terms such as "overlap" do not limit the state of the stacking order of components, etc. For example, the expression "electrode B overlapping insulating layer A" does not limit the state in which electrode B is formed on insulating layer A, but does not exclude the state in which electrode B is formed under insulating layer A or the state in which electrode B is formed on the right (or left) side of insulating layer A, etc.

[0038] In this specification, the terms "adjacent" and "close to" do not necessarily mean that components are in direct contact with each other. For example, the expression "electrode B adjacent to insulating layer A" does not require that insulating layer A and electrode B are formed in direct contact with each other, and does not exclude the inclusion of other components between insulating layer A and electrode B.

[0039] In this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it also includes cases where the angle is -5° or more and 5° or less. Furthermore, "substantially parallel" or "roughly parallel" refers to a state in which two straight lines are arranged at an angle of -30° or more and 30° or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes cases where the angle is 85° or more and 95° or less. Furthermore, "substantially perpendicular" or "approximately perpendicular" refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

[0040] In this specification and elsewhere, when referring to counting values ​​and measurement values, terms such as "identical," "same," "equal," or "uniform" (including synonyms thereof) are used, unless otherwise specified, and include an error of plus or minus 20%.

[0041] In this specification, the term "tapered end of an object" means that the angle between the surface to be formed (bottom surface) and the side surface (surface) in the end region is greater than 0 degrees and less than 90 degrees, and the cross-sectional shape has a continuously increasing thickness from the end. Also, the taper angle refers to the angle between the bottom surface (surface to be formed) and the side surface (surface) at the end of the object.

[0042] In addition, in drawings and the like relating to this specification, arrows indicating the X direction, Y direction, and Z direction may be used. In this specification and the like, the "X direction" refers to the direction along the X axis, and the forward direction and the reverse direction may not be distinguished unless explicitly stated. The same applies to the "Y direction" and the "Z direction." The X direction, Y direction, and Z direction are directions that intersect with each other. More specifically, the X direction, Y direction, and Z direction are directions that are perpendicular to each other. In this specification and the like, one of the X direction, Y direction, and Z direction may be referred to as the "first direction" or "first direction." The other may be referred to as the "second direction" or "second direction." The remaining one may be referred to as the "third direction" or "third direction."

[0043] In this specification and the like, when the same reference numeral is used for multiple elements, and particularly when it is necessary to distinguish between them, an identification symbol such as "A", "b", "_1", "[n]", or "[m, n]" may be added to the reference numeral. For example, the EL layer 172 may be shown divided into an EL layer 172R, an EL layer 172G, an EL layer 172B, and an EL layer 172W.

[0044] Embodiment Mode 1 In this embodiment mode, an example of a signal output circuit, which is a type of semiconductor device, and a shift register including the signal output circuit will be described with reference to the drawings.

[0045] 1A has n (n is an integer equal to or greater than 1) signal output circuits 110. In this specification and the like, the first-stage (first) signal output circuit 110 may be referred to as signal output circuit 110[1], and the n-th stage (n-th) signal output circuit 110 may be referred to as signal output circuit 110[n].

[0046] Furthermore, the signal output circuit 110 in the i-th stage (i is an integer between 1 and n) may be referred to as signal output circuit 110[i]. Note that an arbitrary stage number is represented as i+α, and when α is positive, i+α does not exceed n. Also, an arbitrary stage number is represented as i-α, and when α is positive, i-α does not fall below 1.

[0047] The shift register 100 also has two signal output circuits 110 (signal output circuit 110[n+1] and signal output circuit 110[n+2]) which are dummy circuits.

[0048] The terminals and input / output signals of the signal output circuit 110 may also be referred to in the same manner as above. For example, the signal OUT of the signal output circuit 110[i] may be referred to as the signal OUT[i].

[0049] The shift register 100 also includes wirings 101 to 104 to which four signals CLK (signals CLK_1 to CLK_4) that are clock signals are supplied, and wirings 105 to 108 to which four signals PWC (signals PWC_1 to PWC_4) are supplied. The signal CLK_1 is supplied to the wiring 101, the signal CLK_2 is supplied to the wiring 102, the signal CLK_3 is supplied to the wiring 103, and the signal CLK_4 is supplied to the wiring 104. The signal PWC_1 is supplied to the wiring 105, the signal PWC_2 is supplied to the wiring 106, the signal PWC_3 is supplied to the wiring 107, and the signal PWC_4 is supplied to the wiring 108.

[0050] The signal output circuit 110 has terminals 111 to 118 (see FIG. 1B ). The terminals 111, 112, and 113 are each electrically connected to different wirings among the wirings 101 to 104. For example, in FIG. 1A , in the first-stage signal output circuit 110[1], the terminal 111 is electrically connected to the wiring 101, the terminal 112 is electrically connected to the wiring 102, and the terminal 113 is electrically connected to the wiring 103. That is, a signal CLK_1 is supplied to the terminal 111, a signal CLK_2 is supplied to the terminal 112, and a signal CLK_3 is supplied to the terminal 113.

[0051] In addition, in the second-stage signal output circuit 110[2], the terminal 111 is electrically connected to the wiring 102, the terminal 112 is electrically connected to the wiring 103, and the terminal 113 is electrically connected to the wiring 104. That is, the signal CLK_2 is supplied to the terminal 111, the signal CLK_3 is supplied to the terminal 112, and the signal CLK_4 is supplied to the terminal 113.

[0052] That is, a signal CLK_k is supplied to a terminal 111[i] of a signal output circuit 110[i] (see FIG. 1C ). Here, k is an integer between 1 and 4, and when i is 4 or less, k is equal to i, and when i is 5 or more, k is equal to i−4×g, where g is the quotient obtained by dividing i by 4.

[0053] Furthermore, a signal CLK_k+1 is supplied to a terminal 112[i] of a signal output circuit 110[i], where k is an integer between 1 and 4, and when k+1 is 5, k is set to 1. When i is 3 or less, k is equal to i, and when i is 4 or more, k is equal to i-4×g.

[0054] Furthermore, a signal CLK_k+2 is supplied to a terminal 113[i] of a signal output circuit 110[i]. Here, k+1 is an integer between 1 and 4, and when k+2 is 5, k+2 is set to 1, and when k+2 is 6, k+2 is set to 2. When i is 2 or less, k is equal to i, and when i is 3 or more, k is equal to i-4×g.

[0055] Furthermore, terminal 114[i] is electrically connected to terminal 117[i+1] (not shown) of the next-stage signal output circuit 110[i+1] (not shown). Therefore, terminal 117[i] is electrically connected to terminal 114[i-1]. For example, terminal 114 of signal output circuit 110[1] is electrically connected to terminal 117 of signal output circuit 110[2]. Furthermore, a start pulse SP is supplied to terminal 117 of signal output circuit 110[1].

[0056] Furthermore, terminal 115[i] is electrically connected to terminal 114[i+2] (not shown) of signal output circuit 110[i+2] (not shown) two stages later. For example, terminal 115 of signal output circuit 110[1] is electrically connected to terminal 114 of signal output circuit 110[3], and terminal 115 of signal output circuit 110[2] is electrically connected to terminal 114 of signal output circuit 110[4]. Therefore, terminal 115 of signal output circuit 110[n-1] is electrically connected to terminal 114 of signal output circuit 110[n+1], and terminal 115 of signal output circuit 110[n] is electrically connected to terminal 114 of signal output circuit 110[n+2]. Note that signal output circuit 110[n+1] and signal output circuit 110[n+2] do not necessarily have terminal 115.

[0057] Furthermore, the terminal 118[i] is electrically connected to any of the wirings 105 to 108. For example, the terminal 118 of the signal output circuit 110[1] is electrically connected to the wiring 105, and the terminal 118 of the signal output circuit 110[2] is electrically connected to the wiring 106. In other words, a signal PWC_k is supplied to the terminal 118[i] of the signal output circuit 110[i]. Here, k is an integer greater than or equal to 1 and less than or equal to 4. When i is 4 or less, k is equal to i, and when i is 5 or more, k is equal to i-4×g.

[0058] Furthermore, a signal OUT[i] is output from a terminal 116[i]. For example, a signal OUT[1] is output from a terminal 116 of a signal output circuit 110[1]. Furthermore, a signal OUT[n] is output from a terminal 116 of an n-th stage signal output circuit 110[n]. Note that "a signal OUT[i] is output from a terminal 116[i]" can be read as "a signal OUT[i] is supplied to a terminal 116[i]."

[0059] Furthermore, a signal SROUT[i] is supplied to the terminal 114[i]. In other words, the signal SROUT[i] is output from the terminal 114[i]. For example, the signal SROUT[1] is output from the terminal 114 of the signal output circuit 110[1]. Furthermore, the signal SROUT[n] is output from the terminal 114 of the n-th stage signal output circuit 110[n]. Note that "The signal SROUT[i] is output from the terminal 114[i]" can be read as "The signal SROUT[i] is supplied to the terminal 114[i]."

[0060] [Configuration Example of Signal Output Circuit 110] Next, a configuration of a signal output circuit 110a that can be used for the signal output circuit 110 will be described (see FIG. 2). The signal output circuit 110a includes transistors 10[1] to 10

[11] and capacitors 20[1] to 20[3].

[0061] The gate of transistor 10[1] is electrically connected to terminal 117 and the gate of transistor 10[6]. The source of transistor 10[1] is electrically connected to the drain of transistor 10[2], and the drain of transistor 10[1] is electrically connected to wiring 131. The gate of transistor 10[2] is electrically connected to one terminal of capacitor 20[1]. The source of transistor 10[2] is electrically connected to the other terminal of capacitor 20[1], the source of transistor 10[6], and wiring 132.

[0062] The gate of the transistor 10[3] is electrically connected to the terminal 113, the drain of the transistor 10[3] is electrically connected to the wiring 131, and the source of the transistor 10[3] is electrically connected to the drain of the transistor 10[4]. The gate of the transistor 10[4] is electrically connected to the terminal 112, and the drain of the transistor 10[4] is electrically connected to the source of the transistor 10[3]. The source of the transistor 10[4] is electrically connected to the gates of the transistors 10[2], 10[9], and 10

[11] and one terminal of the capacitor 20[1].

[0063] In this specification, a region where the gates of the transistors 10[2], 10[9], and 10

[11] , the source of the transistor 10[4], and one terminal of the capacitor 20[1] are electrically connected is referred to as a node ND[1]. The capacitor 20[1] has a function of suppressing a potential fluctuation of the node ND[1] when the node ND[1] is in a floating state and maintaining the potential of the node ND[1].

[0064] The gate of the transistor 10[5] is electrically connected to the terminal 115, and the drain of the transistor 10[5] is electrically connected to the wiring 131. The source of the transistor 10[5] is electrically connected to the gate of the transistor 10[2], the gate of the transistor 10[9], the gate of the transistor 10

[11] , and the drain of the transistor 10[6].

[0065] The gate of the transistor 10[7] is electrically connected to the wiring 131, and one of the source and drain of the transistor 10[7] is electrically connected to the source of the transistor 10[1] and the drain of the transistor 10[2]. The other of the source and drain of the transistor 10[7] is electrically connected to the gate of the transistor 10[8], one terminal of the capacitor 20[2], the gate of the transistor 10

[10] , and one terminal of the capacitor 20[3].

[0066] In this specification, a region where the source or drain of the transistor 10[7], the source of the transistor 10[1], and the drain of the transistor 10[2] are electrically connected is referred to as a node ND[2]. Also, in this specification, a region where the source or drain of the transistor 10[7], the gate of the transistor 10[8], one terminal of the capacitor 20[2], the gate of the transistor 10

[10] , and one terminal of the capacitor 20[3] are electrically connected is referred to as a node ND[3].

[0067] The drain of transistor 10[8] is electrically connected to terminal 111. The source of transistor 10[8] is electrically connected to the other terminal of capacitor 20[2], terminal 114, and the drain of transistor 10[9]. The drain of transistor 10

[10] is electrically connected to terminal 118. The source of transistor 10

[10] is electrically connected to the other terminal of capacitor 20[3], terminal 116, and the drain of transistor 10

[11] .

[0068] The source of the transistor 10[9] and the source of the transistor 10

[11] are electrically connected to the wiring 132.

[0069] The drain of transistor 10[1], the drain of transistor 10[3], the drain of transistor 10[5], and the gate of transistor 10[7] may be electrically connected to different wirings. The sources of transistor 10[6], the sources of transistor 10[9], and the sources of transistor 10

[11] may be electrically connected to different wirings.

[0070] 3, the drain of transistor 10[1] may be electrically connected to wiring 131[1], the drain of transistor 10[3] may be electrically connected to wiring 131[2], the drain of transistor 10[5] may be electrically connected to wiring 131[3], and the gate of transistor 10[7] may be electrically connected to wiring 131[4]. Alternatively, the source of transistor 10[6] may be electrically connected to wiring 132[1], the source of transistor 10[9] may be electrically connected to wiring 132[2], and the source of transistor 10

[11] may be electrically connected to wiring 132[3]. Note that, as shown in FIG. 4, when the capacitance value of capacitor 20[3] can be sufficiently secured, the formation of capacitor 20[2] may be omitted.

[0071] A signal RIN is supplied to a terminal 115, a signal LIN is supplied to a terminal 117, a signal SROUT is supplied to a terminal 114, and a signal OUT is supplied to a terminal 116. In the first-stage signal output circuit 110a, a signal CLK_1 is supplied to a terminal 111, a signal CLK_2 is supplied to a terminal 112, a signal CLK_3 is supplied to a terminal 113, and a signal PWC_1 is supplied to a terminal 118.

[0072] In the second-stage signal output circuit 110 a , the signal CLK_ 2 is supplied to the terminal 111 , the signal CLK_ 3 is supplied to the terminal 112 , the signal CLK_ 4 is supplied to the terminal 113 , and the signal PWC_ 2 is supplied to the terminal 118 .

[0073] [Variation 1] Alternatively, either the transistor 10[3] or the transistor 10[4] may be omitted. FIG. 5 shows a circuit diagram of a signal output circuit 110b, which is a variation of the signal output circuit 110a. The signal output circuit 110b has a configuration in which the transistor 10[4] is removed from the signal output circuit 110a. The source of the transistor 10[3] is electrically connected to the node ND[1]. By omitting either the transistor 10[3] or the transistor 10[4], the signal output circuit 110b can be realized with a small occupancy area.

[0074] [Variation 2] Figure 6 shows a circuit diagram of a signal output circuit 110c, which is a variation of the signal output circuit 110a. Each of the transistors 10[2] and 10[6] may be a multi-gate transistor. Figure 6 shows an example in which each of the transistors 10[2] and 10[6] is a double-gate transistor, which is a type of multi-gate transistor.

[0075] The source of transistor 10[2]a is electrically connected to the drain of transistor 10[2]b, and the drain of transistor 10[2]a is electrically connected to the source of transistor 10[1] and one of the source and drain of transistor 10[7]. The source of transistor 10[2]b is electrically connected to the other terminal of capacitor 20[1], the source of transistor 10[6]b, and wiring 132. The gate of transistor 10[2]a and the gate of transistor 10[2]b are electrically connected. That is, transistor 10[2]a and transistor 10[2]b are connected in series and function as one transistor 10[2]. The gate of transistor 10[2]a and the gate of transistor 10[2]b are electrically connected to node ND[1]. Transistor 10[2] may be a multi-gate transistor configured by connecting three or more transistors in series.

[0076] The source of transistor 10[6]a is electrically connected to the drain of transistor 10[6]b, and the drain of transistor 10[6]a is electrically connected to node ND[1]. The source of transistor 10[6]b is electrically connected to the other terminal of capacitor 20[1], the source of transistor 10[2]b, and wiring 132. The gate of transistor 10[6]a and the gate of transistor 10[6]b are electrically connected. That is, transistors 10[6]a and 10[6]b are connected in series and function as one transistor 10[6]. The gates of transistors 10[6]a and 10[6]b are electrically connected to the gate of transistor 10[1] and terminal 117. Transistor 10[6] may be a multi-gate transistor formed by connecting three or more transistors in series.

[0077] A multi-gate transistor has a high breakdown voltage between the source and drain. Therefore, the reliability of a circuit using a multi-gate transistor can be improved. Therefore, the reliability of a semiconductor device including the circuit can be improved. A multi-gate transistor may be applied to transistors other than the transistor 10[2] and the transistor 10[6].

[0078] 7 shows a circuit diagram of a signal output circuit 110d, which is a modification of the signal output circuit 110c. Note that the signal output circuit 110d is also a modification of the signal output circuit 110a. The signal output circuit 110d includes a transistor 10

[12] . The source of the transistor 10

[12] is electrically connected to the node ND[1], and the drain is electrically connected to the wiring 131. The gate of the transistor 10

[12] is electrically connected to the terminal 119.

[0079] A signal INIRES is supplied to the terminal 119. The signal INIRES functions as a reset signal, and while a potential H is supplied to the terminal 119 as the signal INIRES, the signal OUT and the signal SROUT become a potential L. Specifically, when a potential H is supplied to the terminal 119 as the signal INIRES, the transistor 10

[12] is turned on, and the potential of the node ND1 becomes a potential H. When the potential of the node ND1 becomes a potential H, the transistor 10[9] is turned on, and a potential L is supplied to the terminal 114. Furthermore, the transistor 10

[11] is turned on, and a potential L is supplied to the terminal 116.

[0080] By providing the transistor 10

[12] , the operation of the signal output circuit 110d can be stopped at any timing.

[0081] 8 shows a circuit diagram of a signal output circuit 110e, which is a modification of the signal output circuit 110a. The signal output circuit 110e uses transistors having back gates as the transistors 10[2], 10[6], 10[9], and 10

[11] . The back gates of the transistors 10[2], 10[6], 10[9], and 10

[11] are electrically connected to the terminal 121 via the wiring 133.

[0082] A signal SEL is supplied to the terminal 121. The signal SEL may be a fixed potential or a variable potential. When the signal SEL is a fixed potential, it may be the potential L (VSS) or a potential lower than the potential L.

[0083] Here, the reliability of a transistor will be explained. One of the indicators for evaluating the reliability of a transistor is a gate bias temperature stress (GBTS) test, in which the transistor is held in a state in which an electric field is applied to the gate. Among these tests, a test in which a positive potential (positive bias) is applied to the gate relative to the source potential and drain potential and the transistor is held at a high temperature is called a positive bias temperature stress (PBTS) test, and a test in which a negative potential (negative bias) is applied to the gate and the transistor is held at a high temperature is called a negative bias temperature stress (NBTS) test. The PBTS test and the NBTS test performed under light irradiation are called a PBTIS (Positive Bias Temperature Illumination Stress) test and a NBTIS (Negative Bias Temperature Illumination Stress) test, respectively.

[0084] In an n-type transistor, a positive potential is applied to the gate when the transistor is turned on, so the amount of change in threshold voltage in the PBTS test is one important item to note as an index of transistor reliability. In a p-type transistor, a negative potential is applied to the gate when the transistor is turned on, so the amount of change in threshold voltage in the NBTS test is one important item to note as an index of transistor reliability. The smaller the amount of change in threshold voltage before and after the GBTS test, the higher the reliability of the transistor.

[0085] During the operation of the shift register 100, a potential H (VDD) is maintained at the node ND[1] of the signal output circuit 110 (such as the signal output circuit 110a) for a long period of time. Therefore, PBTS is applied to the transistors 10[2], 10[9], and 10

[11] for a long period of time. NBTS is also applied to the transistor 10[6] for a long period of time. By using transistors with back gates for the transistors 10[2], 10[6], 10[9], and 10

[11] , degradation of the transistor characteristics due to NBTS and PBTS is suppressed.

[0086] Furthermore, even if the threshold voltage of the transistor changes in the negative direction (normally on) due to degradation of the transistor characteristics, the transistor can be reliably turned off by supplying a potential lower than the potential L to the back gate. This ensures that the potential of the node ND[1] is maintained. This stabilizes the operation of the signal output circuit 110, thereby improving the reliability of the semiconductor device including the signal output circuit 110.

[0087] Furthermore, when the operating speed of the shift register 100 is slow (the driving frequency is low), the period during which the nodes ND[1] and the like are in a floating state becomes longer. Even under such circumstances, the potential of the nodes ND[1] and the like can be reliably maintained by supplying a potential lower than the potential L to the back gate. This stabilizes the operation of the signal output circuit 110, thereby improving the reliability of the semiconductor device including the signal output circuit 110.

[0088] As described above, PBTS is applied to transistors 10[2], 10[9], and 10

[11] for a long period of time, and NBTS is applied to transistor 10[6] for a long period of time. Therefore, there is a possibility that the degradation of the transistor characteristics may differ between transistors 10[2], 10[9], and 10

[11] and transistor 10[6].

[0089] 9 , the back gates of the transistor 10[2], the transistor 10[9], and the transistor 10

[11] may be electrically connected to the terminal 121 through a wiring 133, and the back gate of the transistor 10[6] may be electrically connected to the terminal 122 through a wiring 134. In this case, the signal SEL_A is supplied to the terminal 121 as the signal SEL, and the signal SEL_B is supplied to the terminal 122 as the signal SEL. The potentials of the signal SEL_A and the signal SEL_B may be the same or different. For example, the potentials of the signal SEL_A and the signal SEL_B may be different from each other to make the transistor characteristics of the transistor 10[2], the transistor 10[9], and the transistor 10

[11] different from the transistor characteristics of the transistor 10[6].

[0090] The signal SEL_A may be synchronized with the signal RIN. For example, when the signal RIN is at a potential H, the signal SEL_A may be set to a potential H. When the signal RIN is at a potential L, the signal SEL_A may be set to a potential L or a potential lower than the potential L. When both the signal SEL_A and the signal RIN are at a potential H, the operating speed of the transistor 10[2], the transistor 10[9], and the transistor 10

[11] can be increased.

[0091] The signal SEL_B may be synchronized with the signal LIN. For example, when the signal LIN is at a potential H, the signal SEL_B may be set to a potential H. When the signal LIN is at a potential L, the signal SEL_B may be set to a potential L or a potential lower than the potential L. When both the signal SEL_B and the signal LIN are at a potential H, the operating speed of the transistor 10[6] can be increased.

[0092] 10 shows a circuit diagram of a signal output circuit 110f, which is a modification of the signal output circuit 110c. The signal output circuit 110f has a configuration in which a transistor 10

[13] and a transistor 10

[14] are added to the signal output circuit 110c.

[0093] The gate of the transistor 10

[13] is electrically connected to the source of the transistor 10[1], the drain of the transistor 10[2]a, and one of the source and drain of the transistor 10[7]. The source of the transistor 10

[13] is electrically connected to the source of the transistor 10[2]a and the drain of the transistor 10[2]b. The drain of the transistor 10

[13] is electrically connected to the wiring 135.

[0094] The gate of the transistor 10

[14] is electrically connected to the node ND[1]. The source of the transistor 10

[14] is electrically connected to the source of the transistor 10[6]a and the drain of the transistor 10[6]b. The drain of the transistor 10

[14] is electrically connected to the wiring 136.

[0095] A potential SMP is supplied to the wiring 135 and the wiring 136. The potential SMP is preferably higher than the potential L+Vth, and more preferably higher than the potential L+2×Vth.

[0096] When a potential H (more precisely, a potential H-Vth) is supplied to node ND[2], transistor 10

[13] is turned on, and a potential SMP is supplied to the source of transistor 10[2]a. When a potential H is supplied to node ND[1], transistor 10

[14] is turned on, and a potential SMP is supplied to the source of transistor 10[6]a. While a fixed potential is preferred, potential SMP may also be a variable potential.

[0097] By setting the potential SMP to a potential higher than the potential L, when the potential L is supplied to the gates of the transistors 10

[13] and 10

[14] , the potential difference between the source and the gate becomes negative with respect to the source potential, thereby more reliably turning off the transistors 10

[13] and 10

[14] .

[0098] The signal output circuit 110 (the signal output circuit 110a, the signal output circuit 110c, and the signal output circuit 110d) according to one embodiment of the present invention is a unipolar circuit configured using transistors of the same conductivity type (n-channel type). Because it is not necessary to use transistors of different conductivity types (p-channel type), manufacturing costs can be reduced, and a signal output circuit with high productivity can be realized. Furthermore, because a process for forming transistors of different conductivity types is not required, the manufacturing period can be shortened and the yield can be improved.

[0099] Note that p-channel transistors may be used in part of the signal output circuit 110 as needed. That is, transistors of different conductivity types may be used in part of the signal output circuit 110. For example, the signal output circuit 110 may have a CMOS (Complementary Metal-Oxide-Semiconductor) circuit including n-channel transistors and p-channel transistors. Note that, although an example in which the signal output circuit 110 is configured entirely with n-channel transistors is shown in this embodiment, it is also possible to replace all of these transistors with p-channel transistors.

[0100] [Transistor Configuration Example] A configuration example of a transistor that can be used for the transistor 10 will be described. FIG. 11A is a plan view of the transistor 10. FIG. 11B is a cross-sectional view of the portion indicated by the dashed dotted line A1-A2 in FIG. 11A. FIG. 11C is a perspective view of the transistor 10. FIG. 11D is an equivalent circuit diagram of the transistor 10. To facilitate understanding of the configuration of the transistor 10, some of the components of the transistor 10 are omitted in FIGS. 11A and 11C. For example, the insulating layer 164 shown in FIG. 11B and the like are omitted in FIGS. 11A and 11C.

[0101] 12A and 12B are enlarged views of the transistor 10 shown in Fig. 11B. Fig. 12C is a view of the opening 159 as seen from the Z direction.

[0102] The transistor 10 includes an insulating layer 154 over a substrate 153 and a conductive layer 155 over the insulating layer 154. The transistor 10 also includes an insulating layer 156 over the conductive layer 155, an insulating layer 157 over the insulating layer 156, and an insulating layer 158 over the insulating layer 157. The transistor 10 also includes a conductive layer 160 over the insulating layer 158. In this specification and other documents, the insulating layer 156, the insulating layer 157, and the insulating layer 158 may be collectively referred to as the insulating layer 145.

[0103] Furthermore, an opening 159 is provided in the conductive layer 160, the insulating layer 158, the insulating layer 157, and the insulating layer 156 in a region overlapping with a portion of the conductive layer 155 (see FIGS. 11B and 12A ). The opening 159 also includes a semiconductor layer 161. The semiconductor layer 161 has a region overlapping with a bottom of the opening 159 and a region overlapping with a side surface of the opening 159. The semiconductor layer 161 has a region in contact with the insulating layer 145 in the opening 159. Specifically, the semiconductor layer 161 has a region in contact with a side surface of the insulating layer 158, a region in contact with a side surface of the insulating layer 157, and a region in contact with a side surface of the insulating layer 156. Furthermore, in the opening 159, a portion of the semiconductor layer 161 is in contact with the conductive layer 160, and another portion of the semiconductor layer 161 is in contact with the conductive layer 155. That is, a part of the semiconductor layer 161 is electrically connected to the conductive layer 160 , and another part of the semiconductor layer 161 is electrically connected to the conductive layer 155 .

[0104] The insulating layer 162 is provided over the insulating layer 158, the conductive layer 160, and the semiconductor layer 161, and the conductive layer 163 is provided over the insulating layer 162. The insulating layer 164 is provided over the insulating layer 162 and the conductive layer 163. The insulating layer 162 has a region that overlaps with the side surface of the opening 159 with the semiconductor layer 161 interposed therebetween. The conductive layer 163 is provided to cover the semiconductor layer 161. Therefore, the conductive layer 163 has a region that extends beyond the end of the semiconductor layer 161. The conductive layer 163 also has a region that overlaps with the side surface of the opening 159 with the insulating layer 162 and the semiconductor layer 161 interposed therebetween.

[0105] The conductive layer 155 has a region functioning as one of the source electrode and the drain electrode of the transistor 10. The conductive layer 160 has a region functioning as the other of the source electrode and the drain electrode of the transistor 10. For example, when the conductive layer 155 functions as the drain electrode of the transistor 10, the conductive layer 160 functions as the source electrode of the transistor 10.

[0106] The semiconductor layer 161 has a region that functions as a semiconductor layer in which a channel of the transistor 10 is formed, the insulating layer 162 has a region that functions as a gate insulating layer, and the conductive layer 163 has a region that functions as a gate electrode. The transistor 10 is provided in a region that includes the opening 159.

[0107] The source electrode and drain electrode of the transistor 10 are arranged in the Z direction. Therefore, the source and drain of the transistor 10 are arranged at different positions in the Z direction. For example, when the top surface of the substrate 153 is used as a reference, the source and drain of the transistor 10 are arranged at different distances from the top surface of the substrate 153, which is the reference. Note that being arranged at different positions in the Z direction is also referred to as being "arranged at different heights." Such a transistor is also referred to as a "vertical channel transistor," "vertical channel transistor," "vertical transistor," or "VFET (Vertical Field Effect Transistor)." In a vertical channel transistor, the flow direction of Id includes a component in the Z direction (vertical direction). For example, in transistor 10, which is a vertical channel transistor, when a cross section passing through the center (or center of gravity) of opening 159 as viewed from the Z direction is viewed from the X direction or the Y direction, the angle θ (see FIG. 12A ) formed by the formation surface of semiconductor layer 161 on conductive layer 155 and the direction in which Id flows is 5 degrees or more and 110 degrees or less, or 10 degrees or more and 90 degrees or less, or 30 degrees or more and 90 degrees or less, or 60 degrees or more and 90 degrees or less.

[0108] Furthermore, as described above, the semiconductor layer 161 has a region in contact with the side surface of the insulating layer 157. Therefore, Id flows along the side surface of the insulating layer 157. Therefore, the angle θ formed by the formation surface of the semiconductor layer 161 on the conductive layer 155 and the direction in which Id flows can be interpreted as the angle θ formed by the formation surface of the semiconductor layer 161 on the conductive layer 155 and the side surface of the insulating layer 157.

[0109] In a vertical channel transistor, the source electrode and the drain electrode are arranged in the Z direction, so that the area occupied by the transistor can be reduced. By using a vertical channel transistor in a semiconductor device, the area occupied by the semiconductor device can be significantly reduced.

[0110] Here, examples of materials that can be used for the transistor 10 or the semiconductor device according to one embodiment of the present invention will be described.

[0111] [Substrate] There are no significant limitations on the materials used for the substrate 153 and the substrates 148 and 152 described below. The materials may be determined depending on the purpose, taking into consideration the presence or absence of light transmission and heat resistance sufficient to withstand heat treatment. For example, insulating substrates such as glass substrates made of barium borosilicate glass or aluminoborosilicate glass, ceramic substrates, quartz substrates, and sapphire substrates may be used. Alternatively, semiconductor substrates, flexible substrates, laminated films, base films, etc. may also be used.

[0112] Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. The semiconductor substrate may be a single-crystal semiconductor or a polycrystalline semiconductor.

[0113] When the transistor 10 according to one embodiment of the present invention or the like is used in a display device, a large-area glass substrate such as a sixth-generation (1500 mm × 1850 mm), seventh-generation (1870 mm × 2200 mm), eighth-generation (2200 mm × 2400 mm), ninth-generation (2400 mm × 2800 mm), or tenth-generation (2950 mm × 3400 mm) glass substrate can be used as the substrate. This allows a large display device to be manufactured. Furthermore, by increasing the size of the substrate, more display devices can be produced from one substrate, thereby reducing production costs.

[0114] Examples of materials that can be used for flexible substrates, laminated films, base films, etc. include polyesters such as polyethylene terephthalate (PET) and polyethylene naphthalate (PEN), polyacrylonitrile, acrylic resin, polyimide, polymethyl methacrylate, polycarbonate (PC), polyethersulfone (PES), polyamide (nylon, aramid, etc.), polysiloxane, cycloolefin resin, polystyrene, polyamideimide, polyurethane, polyvinyl chloride, polyvinylidene chloride, polypropylene, polytetrafluoroethylene (PTFE), ABS resin, and cellulose nanofiber.

[0115] By using the above materials for the substrate, it is possible to provide a lightweight semiconductor device including the transistor 10. Furthermore, by using the above materials for the substrate, it is possible to provide a semiconductor device that is resistant to shocks. Furthermore, by using the above materials for the substrate, it is possible to provide a semiconductor device that is less likely to break.

[0116] The lower the coefficient of linear expansion of the flexible substrate used for the substrate, the more preferable it is, since deformation due to the environment is suppressed. −３ / K or less, 5×10 −５ / K or less, or 1 × 10 −５ In particular, aramid has a low coefficient of linear expansion and is therefore suitable for a flexible substrate.

[0117] [Conductive Layer] As a conductive material used for the conductive layers of not only the gate electrode, source electrode, and drain electrode of the transistor 10 but also various wirings and electrodes constituting the semiconductor device, metal elements selected from aluminum (Al), chromium (Cr), copper (Cu), silver (Ag), gold (Au), platinum (Pt), tantalum (Ta), nickel (Ni), titanium (Ti), molybdenum (Mo), tungsten (W), hafnium (Hf), vanadium (V), niobium (Nb), manganese (Mn), magnesium (Mg), zirconium (Zr), beryllium (Be), etc., alloys containing the above metal elements, or alloys combining the above metal elements, etc. Also, semiconductors such as polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide may be used. The method for forming the conductive material is not particularly limited, and various methods such as vapor deposition, atomic layer deposition (ALD), chemical vapor deposition (CVD), sputtering, and spin coating can be used.

[0118] Alternatively, a Cu-X alloy (where X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti) may be used as the conductive material. A layer formed of a Cu-X alloy can be processed by a wet etching process, thereby reducing manufacturing costs. Alternatively, an aluminum alloy containing one or more elements selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium may be used as the conductive material.

[0119] In addition, conductive materials that can be used for the conductive layer include conductive materials containing oxygen, such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide to which silicon oxide has been added. Furthermore, conductive materials containing nitrogen, such as titanium nitride, tantalum nitride, and tungsten nitride, can also be used. The conductive layer can also have a stacked structure in which a conductive material containing oxygen, a conductive material containing nitrogen, and a material containing the above-mentioned metal element are appropriately combined.

[0120] For example, the conductive layer may have a single-layer structure of an aluminum layer containing silicon, a two-layer structure in which a titanium layer is stacked on an aluminum layer, a two-layer structure in which a titanium layer is stacked on a titanium nitride layer, a two-layer structure in which a tungsten layer is stacked on a titanium nitride layer, a two-layer structure in which a tungsten layer is stacked on a tantalum nitride layer, or a three-layer structure in which a titanium layer, an aluminum layer is stacked on the titanium layer, and a titanium layer is further stacked on the aluminum layer.

[0121] Furthermore, a plurality of conductive layers formed from the above-described conductive materials may be stacked. For example, the conductive layer may have a stacked structure in which the above-described material containing a metal element and a conductive material containing oxygen are combined. Alternatively, the conductive layer may have a stacked structure in which the above-described material containing a metal element and a conductive material containing nitrogen are combined. Alternatively, the conductive layer may have a stacked structure in which the above-described material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen are combined.

[0122] For example, the conductive layer may have a three-layer structure in which a conductive layer containing at least one of indium and zinc and oxygen is stacked on a conductive layer containing copper, and a conductive layer containing at least one of indium and zinc and oxygen is further stacked on top of that. In this case, it is preferable that the side surface of the conductive layer containing copper is also covered with a conductive layer containing at least one of indium and zinc and oxygen. Furthermore, for example, a plurality of conductive layers containing at least one of indium and zinc and oxygen may be stacked as the conductive layer.

[0123] [Insulating Layer] Each insulating layer is made of a single layer or a stack of insulating materials selected from aluminum nitride, aluminum oxide, aluminum nitride oxide, aluminum oxynitride, magnesium oxide, silicon nitride, silicon oxide, silicon nitride oxide, silicon oxynitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, aluminum silicate, etc. Alternatively, a mixture of two or more materials selected from oxide materials, nitride materials, oxynitride materials, and nitride oxide materials may be used.

[0124] The method for forming the insulating material is not particularly limited, and various methods such as vapor deposition, ALD, CVD, sputtering, and spin coating can be used.

[0125] In this specification and elsewhere, a nitride oxide refers to a material containing more nitrogen than oxygen. An oxynitride refers to a material containing more oxygen than nitrogen. The content of each element can be measured, for example, by Rutherford backscattering spectrometry (RBS).

[0126] For example, the insulating layer 154 and the insulating layer 164 are preferably formed using an insulating material that is impermeable to impurities. For example, an insulating material containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum may be used in a single layer or a stacked layer. Examples of insulating materials that are impermeable to impurities include aluminum oxide, aluminum nitride, aluminum oxynitride, aluminum nitride oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, and silicon nitride.

[0127] By using an insulating material that is impervious to impurities for the insulating layer 154, it is possible to suppress the diffusion of impurities from the substrate 153 side and improve the reliability of the transistor 10. That is, it is possible to improve the reliability of a semiconductor device including the transistor 10. By using an insulating material that is impervious to impurities for the insulating layer 164, it is possible to suppress the diffusion of impurities from above the insulating layer 164 and improve the reliability of the transistor 10. That is, it is possible to improve the reliability of a semiconductor device including the transistor 10.

[0128] The insulating layer may also be an insulating layer that can function as a planarizing layer. Examples of materials for the insulating layer that can function as a planarizing layer include acrylic resin, polyimide, epoxy resin, polyamide, polyimideamide, siloxane resin, benzocyclobutene resin, phenolic resin, and precursors thereof. In addition to the organic materials listed above, low-dielectric-constant materials (low-k materials), siloxane resin, PSG (phosphorus glass), BPSG (borophosphorus glass), and the like can also be used. Note that multiple insulating layers made of these materials may be stacked.

[0129] The siloxane resin corresponds to a resin containing Si-O-Si bonds formed using a siloxane-based material as a starting material. The siloxane resin may have an organic group (e.g., an alkyl group or an aryl group) or a fluoro group as a substituent. The organic group may also have a fluoro group.

[0130] Furthermore, CMP treatment may be performed on the surface of the insulating layer, etc. By performing CMP treatment, unevenness on the surface of the insulating layer, etc. can be reduced, and the coverage of the insulating layer and conductive layer to be formed subsequently can be improved.

[0131] [Semiconductor Layer] For the semiconductor layer 161, a single crystal semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, an amorphous semiconductor, or the like can be used alone or in combination. As the semiconductor material, for example, a semiconductor material having a band gap (a semiconductor material that is not a zero-gap semiconductor), such as silicon or germanium, can be used. For example, a semiconductor of an element, a compound semiconductor, or a layered material (also referred to as an atomic layer material, a two-dimensional material, or the like) can be preferably used as the semiconductor material. Furthermore, as the compound semiconductor, an organic material having semiconductor properties or a metal oxide having semiconductor properties (also referred to as an oxide semiconductor) can be used. Note that these semiconductor materials may contain impurities as dopants.

[0132] For example, single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon may be used for the semiconductor layer 161. As the polycrystalline silicon, for example, low temperature polysilicon (LTPS) may be used.

[0133] A transistor using amorphous silicon for the semiconductor layer 161 can be formed over a large glass substrate and manufactured at low cost. A transistor using polycrystalline silicon for the semiconductor layer 161 has high field-effect mobility and can operate at high speed. A transistor using microcrystalline silicon for the semiconductor layer 161 has higher field-effect mobility and can operate at high speed than a transistor using amorphous silicon.

[0134] Compound semiconductors that can be used for the semiconductor material include silicon carbide, silicon germanium, gallium arsenide, indium phosphide, boron nitride, and boron arsenide. Boron nitride that can be used for the semiconductor layer preferably has an amorphous structure. Boron arsenide that can be used for the semiconductor layer preferably has a cubic crystal structure.

[0135] The semiconductor layer 161 may include a layered material that functions as a semiconductor. A layered material is a general term for a group of materials that have a layered crystal structure. A layered crystal structure is a structure in which layers formed by covalent bonds or ionic bonds are stacked via bonds weaker than covalent bonds or ionic bonds, such as van der Waals forces. A layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-state current can be provided.

[0136] Examples of layered materials include graphene, silicene, boron carbonitride, and chalcogenides. Boron carbonitride, a layered material, has carbon atoms, nitrogen atoms, and boron atoms arranged in a hexagonal lattice structure on a plane. Chalcogenides are compounds containing chalcogen. Chalcogen is a general term for elements belonging to Group 16, including oxygen, sulfur, selenium, tellurium, polonium, and livermorium. Examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides. Specific examples of transition metal chalcogenides applicable to the semiconductor layer of a transistor include molybdenum sulfide (typically MoS ２ ), molybdenum selenide (typically MoSe ２ ), molybdenum telluride (typically MoTe ２ ), tungsten sulfide (typically WS ２ ), tungsten selenide (typically WSe ２ ), tungsten tellurium (typically WTe ２ ), hafnium sulfide (typically HfS ２ ), hafnium selenide (typically HfSe ２ ), zirconium sulfide (typically ZrS ２ ), zirconium selenide (typically ZrSe ２ By applying the above-mentioned transition metal chalcogenide to a semiconductor layer, a memory device with a large on-current can be provided.

[0137] Furthermore, since an oxide semiconductor has a band gap of 2 eV or more, a transistor (also referred to as an "OS transistor") using an oxide semiconductor, which is a type of metal oxide, for a semiconductor layer in which a channel is formed has an extremely low off-state current. Therefore, the power consumption of a semiconductor device including an OS transistor can be reduced. Furthermore, an OS transistor operates stably even in a high-temperature environment and exhibits little fluctuation in its characteristics. For example, the off-state current hardly increases even in a high-temperature environment. Specifically, the off-state current hardly increases even in an ambient temperature range from room temperature to 200° C. Furthermore, the on-state current is unlikely to decrease even in a high-temperature environment. Therefore, a semiconductor device including an OS transistor operates stably even in a high-temperature environment and has high reliability.

[0138] Note that in this embodiment and the like, an OS transistor is preferably used as the transistor 10. Since an OS transistor has a high withstand voltage between the source and drain, its channel length can be shortened. Therefore, its on-state current can be increased. An OS transistor is suitable for a vertical channel transistor.

[0139] For example, the channel length can be 5 nm or more, 7 nm or more, or 10 nm or more, and less than 3 μm, 2.5 μm or less, 2 μm or less, 1.5 μm or less, 1.2 μm or less, 1 μm or less, 500 nm or less, 300 nm or less, 200 nm or less, 100 nm or less, 50 nm or less, 30 nm or less, or 20 nm or less. For example, the channel length L can be 100 nm or more and 1 μm or less.

[0140] Examples of metal oxides that can be used for the semiconductor layer of an OS transistor include indium oxide, gallium oxide, and zinc oxide. The metal oxide preferably contains at least indium (In) or zinc (Zn). The metal oxide preferably contains two or three elements selected from indium, an element M, and zinc. The element M is a metal element or a metalloid element that has a high bond energy with oxygen, for example, a metal element or a metalloid element that has a higher bond energy with oxygen than indium.

[0141] Specific examples of the element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M contained in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and even more preferably gallium. In this specification and the like, metal elements and metalloid elements may be collectively referred to as "metal elements," and the "metal elements" described in this specification and the like may include metalloid elements.

[0142] For example, indium zinc oxide (In-Zn oxide), indium tin oxide (In-Sn oxide), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide), gallium zinc oxide (Ga-Zn oxide, also referred to as GZO), aluminum zinc oxide (Al-Zn oxide, also referred to as AZO), indium aluminum zinc oxide Examples of usable materials include In-Al-Zn oxide (IAZO), indium tin zinc oxide (In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (IGZO), indium gallium tin zinc oxide (IGZTO), and indium gallium aluminum zinc oxide (IGAZO or IAGZO). Alternatively, silicon-containing indium tin oxide, gallium tin oxide (Ga-Sn oxide), and aluminum tin oxide (Al-Sn oxide) can be used.

[0143] By increasing the ratio of the number of indium atoms to the total number of atoms of all metal elements contained in the metal oxide, the field-effect mobility of the transistor can be increased.

[0144] Note that the metal oxide may contain one or more metal elements with a larger periodic number instead of or in addition to indium. The greater the overlap of the orbitals of the metal elements, the greater the carrier conduction in the metal oxide. Therefore, including a metal element with a larger periodic number may improve the field-effect mobility of a transistor. Examples of metal elements with a larger periodic number include metal elements belonging to the fifth period and the sixth period. Specific examples of such metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Note that lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

[0145] The metal oxide may also contain one or more nonmetallic elements, which may increase the field-effect mobility of the transistor. Examples of nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0146] Furthermore, by increasing the ratio of the number of zinc atoms to the total number of atoms of the metal elements among the main component elements contained in the metal oxide, the metal oxide can be made highly crystalline, and the diffusion of impurities in the metal oxide can be suppressed, thereby suppressing fluctuations in the electrical characteristics of the transistor and improving its reliability.

[0147] Furthermore, by increasing the ratio of the number of atoms of element M to the sum of the number of atoms of metal elements among the main component elements contained in the metal oxide, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, carrier generation due to oxygen vacancies can be suppressed, and a transistor with a small off-state current can be obtained. Furthermore, fluctuations in the electrical characteristics of the transistor can be suppressed, and reliability can be improved.

[0148] The electrical characteristics and reliability of a transistor vary depending on the composition of the metal oxide used in the semiconductor layer. Therefore, by varying the composition of the metal oxide depending on the electrical characteristics and reliability required of the transistor, a semiconductor device that has both excellent electrical characteristics and high reliability can be realized.

[0149] When an In-Zn oxide is used for a semiconductor layer of an OS transistor, a metal oxide in which the atomic ratio of indium is equal to or greater than the atomic ratio of zinc is preferably used. For example, a metal oxide in which the atomic ratio of metal elements is In:Zn=1:1, In:Zn=2:1, In:Zn=3:1, In:Zn=4:1, In:Zn=5:1, In:Zn=7:1, In:Zn=10:1, or a metal oxide in a range thereof can be used.

[0150] When an In—Sn oxide is used for a semiconductor layer of an OS transistor, a metal oxide in which the atomic ratio of indium is equal to or greater than that of tin is preferably used. For example, a metal oxide in which the atomic ratio of metal elements is In:Sn=1:1, In:Sn=2:1, In:Sn=3:1, In:Sn=4:1, In:Sn=5:1, In:Sn=7:1, In:Sn=10:1, or a ratio thereof close to these values ​​can be used.

[0151] When an In-Sn-Zn oxide is used for a semiconductor layer of an OS transistor, a metal oxide in which the atomic ratio of indium is higher than that of tin can be used. Furthermore, a metal oxide in which the atomic ratio of zinc is higher than that of tin can be used. For example, the atomic ratios of metal elements may be In:Sn:Zn=2:1:3, In:Sn:Zn=3:1:2, In:Sn:Zn=4:2:3, In:Sn:Zn=4:2:4.1, In:Sn:Zn=5:1:3, In:Sn:Zn=5:1:6, In:Sn:Zn=5:1:7, In:Sn:Zn=5:1:8, In:Sn:Zn=6:1:6, In :Sn:Zn=10:1:3, In:Sn:Zn=10:1:6, In:Sn:Zn=10:1:7, In:Sn:Zn=10:1:8, In:Sn:Zn=5:2:5, In:Sn:Zn=10:1:10, In:Sn:Zn=20:1:10, In:Sn:Zn=40:1:10, or metal oxides thereof having a ratio close to these can be used.

[0152] When an In-Al-Zn oxide is used for a semiconductor layer of an OS transistor, a metal oxide in which the atomic ratio of indium is higher than that of aluminum can be used. Furthermore, a metal oxide in which the atomic ratio of zinc is higher than that of aluminum can be used. For example, the atomic ratios of metal elements may be In:Al:Zn=2:1:3, In:Al:Zn=3:1:2, In:Al:Zn=4:2:3, In:Al:Zn=4:2:4.1, In:Al:Zn=5:1:3, In:Al:Zn=5:1:6, In:Al:Zn=5:1:7, In:Al:Zn=5:1:8, In:Al:Zn=6:1:6, In In:Al:Zn=10:1:3, In:Al:Zn=10:1:6, In:Al:Zn=10:1:7, In:Al:Zn=10:1:8, In:Al:Zn=5:2:5, In:Al:Zn=10:1:10, In:Al:Zn=20:1:10, In:Al:Zn=40:1:10, or metal oxides thereof having a similar ratio can be used.

[0153] When an In—Ga—Zn oxide is used for a semiconductor layer of an OS transistor, a metal oxide in which the atomic ratio of indium to the number of atoms of the metal element is higher than the atomic ratio of gallium can be used. Furthermore, it is more preferable to use a metal oxide in which the atomic ratio of zinc to the number of atoms of gallium is higher. For example, the atomic ratios of the metal elements are as follows: In:Ga:Zn=2:1:3, In:Ga:Zn=3:1:2, In:Ga:Zn=4:2:3, In:Ga:Zn=4:2:4.1, In:Ga:Zn=5:1:3, In:Ga:Zn=5:1:6, In:Ga:Zn=5:1:7, In:Ga:Zn=5:1:8, In:Ga:Zn=6:1:6, In :Ga:Zn=10:1:3, In:Ga:Zn=10:1:6, In:Ga:Zn=10:1:7, In:Ga:Zn=10:1:8, In:Ga:Zn=5:2:5, In:Ga:Zn=10:1:10, In:Ga:Zn=20:1:10, In:Ga:Zn=40:1:10, or metal oxides thereof can be used.

[0154] When an In-M-Zn oxide is used for a semiconductor layer of an OS transistor, a metal oxide in which the atomic ratio of indium to the number of atoms of the metal element is higher than the atomic ratio of the element M can be used. Furthermore, it is more preferable to use a metal oxide in which the atomic ratio of zinc is higher than the atomic ratio of the element M. For example, the atomic ratios of the metal elements are In:M:Zn=2:1:3, In:M:Zn=3:1:2, In:M:Zn=4:2:3, In:M:Zn=4:2:4.1, In:M:Zn=5:1:3, In:M:Zn=5:1:6, In:M:Zn=5:1:7, In:M:Zn=5:1:8, In:M:Zn=6:1:6, In In:M:Zn=10:1:3, In:M:Zn=10:1:6, In:M:Zn=10:1:7, In:M:Zn=10:1:8, In:M:Zn=5:2:5, In:M:Zn=10:1:10, In:M:Zn=20:1:10, In:M:Zn=40:1:10, or metal oxides thereof having a similar ratio can be used.

[0155] When a plurality of metal elements are contained as the element M, the sum of the atomic ratios of the metal elements can be taken as the atomic ratio of the element M. For example, in the case of an In-Ga-Al-Zn oxide having gallium and aluminum as the element M, the sum of the atomic ratio of gallium and the atomic ratio of aluminum can be taken as the atomic ratio of the element M. Furthermore, it is preferable that the atomic ratios of indium, the element M, and zinc are within the above-mentioned ranges.

[0156] It is preferable to use a metal oxide in which the ratio of the number of indium atoms to the total number of atoms of the metal elements among the main component elements contained in the metal oxide is 30 atomic % or more and 100 atomic % or less, preferably 30 atomic % or more and 95 atomic % or less, more preferably 35 atomic % or more and 95 atomic % or less, more preferably 35 atomic % or more and 90 atomic % or less, more preferably 40 atomic % or more and 90 atomic % or less, more preferably 45 atomic % or more and 90 atomic % or less, more preferably 50 atomic % or more and 80 atomic % or less, more preferably 60 atomic % or more and 80 atomic % or less, and more preferably 70 atomic % or more and 80 atomic % or less. For example, when an In-M-Zn oxide is used for the semiconductor layer, it is preferable that the ratio of the number of indium atoms to the total number of atoms of indium, element M, and zinc is in the above-mentioned range.

[0157] As described above, the field-effect mobility of a transistor can be increased by increasing the ratio of the number of indium atoms to the sum of the number of atoms of the metal elements among the main component elements contained in the metal oxide. By using the transistor, a circuit capable of high-speed operation can be manufactured. Furthermore, the area occupied by the circuit can be reduced. For example, when the transistor is applied to a large display device or a high-resolution display device, even if the number of wirings is increased, signal delay in each wiring can be reduced, thereby suppressing display unevenness. Furthermore, since the area occupied by the circuit can be reduced, the frame of the display device can be narrowed.

[0158] The composition of the metal oxide can be analyzed by, for example, energy dispersive X-ray spectroscopy (EDX), X-ray photoelectron spectroscopy (XPS), inductively coupled plasma mass spectrometry (ICP-MS), or inductively coupled plasma atomic emission spectrometry (ICP-AES). Alternatively, a combination of these techniques may be used for the analysis. For elements with low content, the actual content may differ from the content obtained by analysis due to the influence of analytical accuracy. For example, when the content of element M is low, the content of element M obtained by analysis may be lower than the actual content.

[0159] The metal oxide is preferably formed by a sputtering method or an ALD method. When forming a metal oxide by a sputtering method, the atomic ratio of the target may differ from the atomic ratio of the metal oxide. In particular, the atomic ratio of zinc in the metal oxide may be smaller than the atomic ratio of the target. Specifically, the atomic ratio of zinc in the metal oxide may be about 40% to 90% of the atomic ratio of zinc contained in the target.

[0160] By using a metal oxide that does not contain gallium or has a low gallium content in the semiconductor layer, a transistor with high reliability against positive bias application can be obtained. That is, a transistor with a small amount of threshold voltage fluctuation in a PBTS test can be obtained. Furthermore, when using a metal oxide that contains gallium, it is preferable to make the gallium content lower than the indium content. This allows for a highly reliable transistor to be realized.

[0161] One of the factors that causes the threshold voltage to fluctuate in the PBTS test is defect levels at or near the interface between the semiconductor layer and the gate insulating layer. The higher the defect level density, the more significant the degradation in the PBTS test. By reducing the gallium content in the region of the semiconductor layer that contacts the gate insulating layer, the generation of the defect levels can be suppressed.

[0162] The following is a possible reason why using a metal oxide containing no gallium or with a low gallium content for the semiconductor layer can suppress fluctuations in threshold voltage in the PBTS test. Gallium contained in the metal oxide has the property of attracting oxygen more easily than other metal elements (e.g., indium or zinc). Therefore, it is presumed that gallium combines with excess oxygen in the gate insulating layer at the interface between the gallium-rich metal oxide and the gate insulating layer, making it easier to generate carrier (here, electron) trap sites. Therefore, when a positive potential is applied to the gate, carriers are trapped at the interface between the semiconductor layer and the gate insulating layer, which is thought to cause fluctuations in threshold voltage.

[0163] More specifically, when an In-Ga-Zn oxide is used for the semiconductor layer, a metal oxide in which the atomic ratio of indium is higher than that of gallium can be used for the semiconductor layer. It is more preferable to use a metal oxide in which the atomic ratio of zinc is higher than that of gallium. In other words, it is preferable to use a metal oxide in which the atomic ratios of metal elements satisfy In > Ga and Zn > Ga for the semiconductor layer.

[0164] For example, the semiconductor layer of the OS transistor may contain metal elements having an atomic ratio of In:Ga:Zn=2:1:3, In:Ga:Zn=3:1:2, In:Ga:Zn=4:2:3, In:Ga:Zn=4:2:4.1, In:Ga:Zn=5:1:3, In:Ga:Zn=5:1:6, In:Ga:Zn=5:1:7, In:Ga:Zn=5:1:8, In:Ga:Zn= Examples of the composition include In:Ga:Zn=6:1:6, In:Ga:Zn=10:1:3, In:Ga:Zn=10:1:6, In:Ga:Zn=10:1:7, In:Ga:Zn=10:1:8, In:Ga:Zn=5:2:5, In:Ga:Zn=10:1:10, In:Ga:Zn=20:1:10, In:Ga:Zn=40:1:10, and metal oxides thereof having similar ratios can be used.

[0165] The semiconductor layer of an OS transistor preferably uses a metal oxide in which the ratio of the number of gallium atoms to the number of atoms of the metal elements contained therein is greater than 0 atomic % and less than or equal to 50 atomic %, preferably 0.1 atomic % to 40 atomic %, more preferably 0.1 atomic % to 35 atomic %, more preferably 0.1 atomic % to 30 atomic %, more preferably 0.1 atomic % to 25 atomic %, more preferably 0.1 atomic % to 20 atomic %, more preferably 0.1 atomic % to 15 atomic %, and more preferably 0.1 atomic % to 10 atomic %. By lowering the ratio of the number of gallium atoms to the number of atoms of the metal elements contained in the semiconductor layer, a transistor with high resistance to a PBTS test can be obtained. Note that by including gallium in the metal oxide, oxygen deficiency (V Ｏ This has the effect of making oxygen vacancy less likely to occur.

[0166] A metal oxide containing no gallium may be used for the semiconductor layer of an OS transistor. For example, In—Zn oxide may be used for the semiconductor layer. In this case, increasing the atomic ratio of indium to the atomic number of metal elements contained in the metal oxide can increase the field-effect mobility of the transistor. On the other hand, increasing the atomic ratio of zinc to the atomic number of metal elements contained in the metal oxide can result in a metal oxide with high crystallinity, thereby suppressing fluctuations in the electrical characteristics of the transistor and improving its reliability. Furthermore, a metal oxide containing no gallium or zinc, such as indium oxide, may be used for the semiconductor layer. The use of a metal oxide containing no gallium can significantly reduce fluctuations in threshold voltage, particularly in a PBTS test.

[0167] For example, the semiconductor layer can be made of an oxide containing indium and zinc, in which the atomic ratio of the metal elements is, for example, In:Zn=2:3, In:Zn=4:1, or a ratio close to these values.

[0168] Although gallium has been used as a representative example in the description, the present invention can also be applied to a case where element M is used instead of gallium. For the semiconductor layer, it is preferable to use a metal oxide in which the atomic ratio of indium is higher than the atomic ratio of element M. It is also preferable to use a metal oxide in which the atomic ratio of zinc is higher than the atomic ratio of element M.

[0169] A transistor having high reliability against application of a positive bias can be realized by using a metal oxide having a low content of element M in a semiconductor layer. By applying the transistor to a transistor that requires high reliability against application of a positive bias, a highly reliable semiconductor device can be realized.

[0170] Next, the reliability of the transistor against light will be described.

[0171] Light incident on a transistor may cause fluctuations in the electrical characteristics of the transistor. In particular, it is preferable that a transistor applied to a region where light may be incident exhibits small fluctuations in electrical characteristics under light irradiation and has high reliability against light. The reliability against light can be evaluated, for example, by the amount of fluctuation in threshold voltage in an NBTIS test.

[0172] Increasing the content of element M in the metal oxide used in the semiconductor layer can result in a transistor with high reliability against light. That is, a transistor with a small variation in threshold voltage in an NBTIS test can be obtained. Specifically, a metal oxide in which the atomic ratio of element M is equal to or greater than the atomic ratio of indium has a larger band gap, and can reduce the variation in threshold voltage of the transistor in an NBTIS test. The band gap of the metal oxide in the semiconductor layer is preferably 2.0 eV or more, more preferably 2.5 eV or more, even more preferably 3.0 eV or more, still more preferably 3.2 eV or more, even more preferably 3.3 eV or more, still more preferably 3.4 eV or more, and even more preferably 3.5 eV or more.

[0173] For example, the semiconductor layer can be made of a metal oxide having an atomic ratio of metal elements of In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=1:3:2, In:M:Zn=1:3:3, In:M:Zn=1:3:4, or a ratio close to these.

[0174] In particular, a metal oxide in which the ratio of the number of atoms of element M to the number of atoms of the contained metal element is 20 atomic % or more and 70 atomic % or less, preferably 30 atomic % or more and 70 atomic % or less, more preferably 30 atomic % or more and 60 atomic % or less, more preferably 40 atomic % or more and 60 atomic % or less, and more preferably 50 atomic % or more and 60 atomic % or less is suitable as the semiconductor layer.

[0175] When an In—Ga—Zn oxide is used for the semiconductor layer, a metal oxide having an atomic ratio of indium to gallium equal to or less than that of gallium can be used. For example, metal oxides having an atomic ratio of metal elements of In:Ga:Zn=1:1:1, In:Ga:Zn=1:1:1.2, In:Ga:Zn=1:3:2, In:Ga:Zn=1:3:3, In:Ga:Zn=1:3:4, or similar can be used.

[0176] As the semiconductor layer, a metal oxide in which the ratio of the number of gallium atoms to the number of atoms of the contained metal element is 20 atomic % or more and 60 atomic % or less, preferably 20 atomic % or more and 50 atomic % or less, more preferably 30 atomic % or more and 50 atomic % or less, more preferably 40 atomic % or more and 60 atomic % or less, and more preferably 50 atomic % or more and 60 atomic % or less is particularly suitable.

[0177] A transistor with high reliability against light can be obtained by using a metal oxide having a high content of element M in a semiconductor layer. By using the transistor as a transistor that is required to have high reliability against light, a highly reliable semiconductor device can be obtained.

[0178] The semiconductor layer may have a stacked structure including two or more metal oxide layers. The two or more metal oxide layers included in the semiconductor layer may have the same or substantially the same composition. By using a stacked structure of metal oxide layers having the same composition, for example, the same sputtering target can be used for formation, thereby reducing manufacturing costs.

[0179] The two or more metal oxide layers included in the semiconductor layer may have different compositions. For example, a two-layer stack structure may be used, including a first metal oxide layer having an atomic ratio of In:M:Zn=1:3:4 or a similar composition, and a second metal oxide layer having an atomic ratio of In:M:Zn=1:1:1 or a similar composition, overlapping the first metal oxide layer. It is particularly preferable to use gallium or aluminum as the element M. For example, a stack structure may be used, including any one selected from indium oxide, indium gallium oxide, and IGZO, and any one selected from IAZO, IAGZO, and ITZO (registered trademark).

[0180] Alternatively, for example, a stacked structure may be used, which includes a first metal oxide layer having an atomic ratio of In:M:Zn=1:1:1 or a composition close thereto, and a second metal oxide layer having an atomic ratio of In:Zn=4:1 or a composition close thereto, which is provided on the first metal oxide layer.

[0181] Alternatively, for example, a three-layer stacked structure may be used, in which a first semiconductor layer has an atomic ratio of metal elements of In:Ga:Zn = 1:1:1, a second semiconductor layer has an atomic ratio of metal elements of In:Zn = 4:1, and a third semiconductor layer has an atomic ratio of metal elements of In:Ga:Zn = 1:1:1. It is preferable that the band gaps of the first and third semiconductor layers are larger than the band gap of the second semiconductor layer. This configuration allows the main current path to be the second layer, resulting in a so-called buried channel structure.

[0182] The semiconductor layer is preferably a crystalline metal oxide layer. For example, a metal oxide layer having a c-axis aligned crystal (CAAC) structure, a polycrystalline structure, a nanocrystalline (nc) structure, or the like can be used. By using a crystalline metal oxide layer for the semiconductor layer, the density of defect states in the semiconductor layer can be reduced, and a highly reliable display device can be realized.

[0183] The higher the crystallinity of a metal oxide layer used in a semiconductor layer, the more the density of defect states in the semiconductor layer can be reduced.On the other hand, by using a metal oxide layer with low crystallinity, a transistor capable of passing a large current can be realized.

[0184] When a metal oxide layer is formed by a sputtering method, the higher the substrate temperature (stage temperature) during formation, the higher the crystallinity of the formed metal oxide layer.Furthermore, the higher the ratio of the flow rate of oxygen gas to the total film formation gas used during formation (hereinafter also referred to as the oxygen flow rate ratio), the higher the crystallinity of the formed metal oxide layer.

[0185] The semiconductor layer of the OS transistor may have a stacked structure of two or more metal oxide layers with different crystallinity. For example, the semiconductor layer may have a stacked structure of a first metal oxide layer and a second metal oxide layer provided over the first metal oxide layer, where the second metal oxide layer has a region with higher crystallinity than the first metal oxide layer. Alternatively, the second metal oxide layer may have a region with lower crystallinity than the first metal oxide layer. The two or more metal oxide layers included in the semiconductor layer may have the same or approximately the same composition. The stacked structure of metal oxide layers with the same composition can be formed using the same sputtering target, for example, which reduces manufacturing costs. For example, the stacked structure of two or more metal oxide layers with different crystallinity can be formed by using the same sputtering target and varying the oxygen flow rate. Note that the two or more metal oxide layers included in the semiconductor layer may have different compositions.

[0186] In the transistor 10 described in this embodiment, the channel length L is determined by the thickness of the insulating layer provided between the conductive layer 160 and the conductive layer 155. Therefore, a transistor with a short channel length L can be manufactured with high accuracy. Furthermore, the variation in characteristics among the plurality of transistors 10 is reduced. Therefore, the operation of a semiconductor device including the transistor 10 can be stabilized, and the reliability can be improved. Furthermore, the reduced variation in characteristics increases the degree of freedom in circuit design of the semiconductor device, and the operating voltage can also be reduced. Therefore, the power consumption of the semiconductor device can be reduced.

[0187] When an oxide semiconductor is used for the semiconductor layer 161, it is preferable to use a material containing hydrogen for the insulating layers 156 and 158. When the insulating layer containing hydrogen is in contact with the oxide semiconductor, the oxide semiconductor in the region in contact with the insulating layer becomes n-type and can function as a source region or a drain region. For example, a material containing silicon, nitrogen, and hydrogen may be used for the insulating layer. Specifically, silicon nitride containing hydrogen or silicon nitride oxide containing hydrogen may be used.

[0188] When an oxide semiconductor is used for the semiconductor layer 161, the conductive layer 155 in contact with the semiconductor layer 161 and the conductive layer 160 in contact with the semiconductor layer 161 are preferably formed using a conductive material that makes the oxide semiconductor n-type. For example, a conductive material containing nitrogen may be used. For example, a conductive material containing titanium or tantalum and nitrogen may be used. Alternatively, another conductive material may be provided over the conductive material containing nitrogen.

[0189] On the other hand, it is preferable to use a material containing oxygen and having reduced hydrogen for the insulating layer 157. For example, a material containing silicon and oxygen may be used. Specifically, silicon oxide, silicon oxynitride, or the like may be used. Because hydrogen is an impurity element in an oxide semiconductor, contact between the semiconductor layer 161, which is an oxide semiconductor, and the insulating layer 157, which has reduced hydrogen, makes it difficult for the semiconductor layer 161 to become n-type. Furthermore, contact between the semiconductor layer 161, which is an oxide semiconductor, and the insulating layer 157 containing oxygen reduces oxygen vacancies in the semiconductor layer 161, thereby stabilizing the characteristics of the transistor 10 and improving its reliability.

[0190] When an oxide semiconductor is used for the semiconductor layer 161, the insulating layer 157 preferably contains excess oxygen. In this specification and the like, "excess oxygen" refers to oxygen that is released by heating. When a material containing excess oxygen is used for the insulating layer 157, a material that is impermeable to oxygen is preferably used for the insulating layers 156 and 158. Examples of the material that is impermeable to oxygen include an oxide containing one or both of aluminum and hafnium, and a nitride of silicon. By using a material that is impermeable to oxygen for the insulating layers 156 and 158, the excess oxygen contained in the insulating layer 157 is less likely to be released to the lower or upper layer. Therefore, sufficient oxygen can be supplied to the oxide semiconductor. For example, a structure may be used in which an insulating layer containing silicon and oxygen (the insulating layer 157) is provided between two insulating layers containing silicon and nitrogen (the insulating layer 156 and the insulating layer 158).

[0191] When an oxide semiconductor is used for the semiconductor layer 161 and a material containing hydrogen is used for the insulating layers 156 and 158, a region of the semiconductor layer 161 in contact with the conductive layer 160 and a region of the semiconductor layer 161 in contact with the insulating layer 158 function as one of a source (source region) and a drain (drain region). A region of the semiconductor layer 161 in contact with the conductive layer 155 and a region of the semiconductor layer 161 in contact with the insulating layer 156 function as the other of a source (source region) and a drain (drain region). Therefore, the channel length L of the transistor 10 is determined by the thickness t of the insulating layer 157 (see FIG. 12A ).

[0192] Alternatively, the insulating layers 156 and 158 may be formed using a material that does not contain hydrogen or contains very little hydrogen. For example, silicon nitride or silicon nitride oxide containing very little hydrogen may be used. In this case, the region of the semiconductor layer 161 in contact with the insulating layer 156 and the region of the semiconductor layer 161 in contact with the insulating layer 158 are not made n-type. Therefore, the region of the semiconductor layer 161 in contact with the conductive layer 160 functions as either the source (source region) or the drain (drain region). The region of the semiconductor layer 161 in contact with the conductive layer 155 functions as the other of the source (source region) or the drain (drain region). In this case, the total thickness ts of the insulating layers 156, 157, and 158 corresponds to the channel length L of the transistor 10 (see FIG. 12A ).

[0193] The channel length L can be controlled by adjusting the thicknesses of the insulating layers 156, 157, and 158. For example, the channel length L can be set to 5 nm or more, 7 nm or more, or 10 nm or more, and less than 3 μm, 2.5 μm or less, 2 μm or less, 1.5 μm or less, 1.2 μm or less, 1 μm or less, 500 nm or less, 300 nm or less, 200 nm or less, 100 nm or less, 50 nm or less, 30 nm or less, or 20 nm or less. For example, the channel length L can be set to 100 nm or more and 1 μm or less.

[0194] Although this embodiment shows a structure in which three insulating layers (insulating layer 156, insulating layer 157, and insulating layer 158) are provided between the conductive layer 155 and the conductive layer 160, the number of insulating layers between the conductive layer 155 and the conductive layer 160 is not limited to this. The number of insulating layers between the conductive layer 155 and the conductive layer 160 may be one, two, or four or more.

[0195] Furthermore, because the semiconductor layer 161 is provided in the opening 159, the perimeter p of the opening 159 is the channel width W of the transistor 10 (see FIG. 12C ). The perimeter p may be determined, for example, at a position that is half the thickness t (t / 2) or half the thickness ts (ts / 2) of the insulating layer 157. Note that the perimeter at any position of the opening 159 may be the channel width W as needed. For example, the perimeter p at the bottom of the opening 159 may be the channel width W, or the perimeter p at the top of the opening 159 may be the channel width W.

[0196] In addition, although the outline (planar shape) of the opening 159 as viewed from the Z direction is shown as a circle in Fig. 12C, this is not limiting. For example, the outline of the opening 159 as viewed from the Z direction may be an ellipse (see Fig. 12D) or a rectangle (see Fig. 12E). Note that Fig. 12E shows a rectangle with rounded corners. In addition, for example, the outline of the opening 159 as viewed from the Z direction may have a shape including one or both of straight and curved portions (see Fig. 12F).

[0197] In the transistor 10 according to one embodiment of the present invention, the parasitic capacitance generated between the gate and the source is different from the parasitic capacitance generated between the gate and the drain. Specifically, the capacitance C1 is larger than the capacitance C2 generated in a region where the conductive layer 160 and the conductive layer 163 overlap over the insulating layer 145 (see FIGS. 11D and 12B ).

[0198] 13A and 13B show plan views similar to those of FIG. 11A. When the transistor 10 according to one embodiment of the present invention is viewed from the Z direction, the conductive layer 163 overlaps the conductive layer 160 around the periphery of the opening 159 so as to surround the opening 159, and overlaps the conductive layer 160 at the bottom of the opening 159.

[0199] 13A, the region that functions as capacitance C1 when viewed from the Z direction is hatched. The region where conductive layer 160 and conductive layer 163 overlap each other on insulating layer 145 with semiconductor layer 161 and insulating layer 162 interposed therebetween functions as capacitance C1 (see FIGS. 12B and 13A). Note that illustration of insulating layer 145 and insulating layer 162 is omitted in FIG. 13A.

[0200] 13B, the region that functions as capacitance C2 when viewed from the Z direction is hatched. At the bottom of opening 159, the region where conductive layer 155 and conductive layer 163 overlap with semiconductor layer 161 and insulating layer 162 interposed therebetween functions as capacitance C2 (see FIGS. 12B and 13B). Note that insulating layer 145 and insulating layer 162 are omitted from FIG. 13B.

[0201] 13A and 13B, it can be seen that the area of ​​the region functioning as capacitance C1 is larger than the area of ​​the region functioning as capacitance C2. By making the area of ​​the region functioning as capacitance C1 larger than the area of ​​the region functioning as capacitance C2, the capacitance value of capacitance C1 becomes larger than that of capacitance C2.

[0202] Furthermore, changing the overlapping area of ​​conductive layer 155 and conductive layer 163 to change the capacitance value of capacitor C2 requires changing the shape of opening 159, which changes the perimeter p of opening 159. Because the change in perimeter p directly affects the electrical characteristics of transistor 10, it is difficult to adjust the capacitance value of capacitor C2.

[0203] On the other hand, the overlapping area between the conductive layer 163 and the conductive layer 160 can be easily adjusted and is unlikely to affect the electrical characteristics of the transistor 10. For example, by increasing the overlapping area between the conductive layer 163 and the conductive layer 160, the capacitance value of the capacitor C1 can be increased.

[0204] 14A , a conductive layer 166 may be provided in the insulating layer 157 so as to be adjacent to the semiconductor layer 161. The conductive layer 166 is provided without contacting the semiconductor layer 161. The conductive layer 166 is preferably provided to surround the semiconductor layer 161. By providing the conductive layer 166 adjacent to the semiconductor layer 161 without contacting the semiconductor layer 161, the conductive layer 166 can function as a back gate electrode of the transistor 10. Therefore, the transistor 10 shown in FIG. 14A functions as a transistor having a back gate electrode. Note that FIG. 14B is an equivalent circuit diagram of the transistor 10 shown in FIG. 14A .

[0205] Here, the back gate electrode will be explained. Generally, the back gate electrode is formed of a conductive layer and is disposed so that the gate electrode and the back gate electrode sandwich the channel formation region of the semiconductor layer. Therefore, the back gate electrode can function in the same manner as the gate electrode. The potential of the back gate electrode may be the same as that of the gate electrode, or may be the GND potential or any other potential. By electrically connecting the gate electrode and the back gate electrode, the on-current of the transistor can be increased. Furthermore, by changing the potential of the back gate electrode independently of the gate electrode, the threshold voltage of the transistor can be changed.

[0206] Furthermore, since the gate electrode and the back gate electrode are formed of conductive layers, they have the function of preventing an electric field generated outside the transistor from acting on the channel formation region of the semiconductor layer (particularly, an electric field shielding function against static electricity, etc.). As a result, the characteristic variations among transistors are reduced. Furthermore, the degradation of transistor characteristics due to the GBTS test is suppressed. For example, the presence of a back gate electrode can suppress the variation in threshold voltage before and after the GBTS test. Furthermore, the variation in threshold voltage before and after the GBTS test is smaller in a transistor having a back gate electrode than in a transistor without a back gate electrode.

[0207] The GBTS (NBTS and PBTS) test is a type of accelerated test that can quickly evaluate changes in transistor characteristics (aging) that occur over long periods of use. In particular, the amount of change in the threshold voltage of a transistor before and after the GBTS test is an important indicator for examining reliability. The smaller the amount of change in threshold voltage before and after the GBTS test, the more reliable the transistor.

[0208] Furthermore, when light is incident from the back gate electrode side, forming the back gate electrode from a conductive film having a light-shielding property can prevent the light from entering the semiconductor layer from the back gate electrode side. Similarly, forming the gate electrode from a conductive film having a light-shielding property can prevent the light from entering the semiconductor layer from the gate electrode side. Forming one or both of the gate electrode and the back gate electrode from a conductive film having a light-shielding property can prevent light degradation of the semiconductor layer and deterioration of electrical characteristics such as a shift in the threshold voltage of the transistor.

[0209] Furthermore, the gate electrode and the back gate electrode can block the electric field generated by the drain electrode from acting on the semiconductor layer. This can suppress fluctuations in the on-current rise voltage caused by fluctuations in the drain voltage. This effect is particularly noticeable when a potential is supplied to the gate electrode and the back gate electrode.

[0210] Connecting multiple transistors 10 in parallel increases the apparent channel width W of each transistor 10. Increasing the channel width W reduces the resistance between the source and drain when the transistor 10 is in the on state, thereby increasing Id when in the on state.

[0211] FIG. 15A is a plan view of a transistor 10 including a transistor 10a and a transistor 10b. FIG. 15B is a cross-sectional view of the portion indicated by the dashed dotted line A1-A2 in FIG. 15A. FIG. 15C is a perspective view of a transistor 10 including a transistor 10a and a transistor 10b. FIG. 15D is an equivalent circuit diagram of a transistor 10 including a transistor 10a and a transistor 10b. To facilitate understanding of the configuration of the transistor 10, some of the components of the transistor 10 are omitted in FIGS. 15A and 15C.

[0212] The transistors 10a and 10b have the same configuration as the transistor 10 described with reference to Figures 11 and 12. The transistor 10a is provided in a region including an opening 159a, and the transistor 10b is provided in a region including an opening 159b. The openings 159a and 159b can be formed in the same manner as the opening 159.

[0213] A part of the conductive layer 155 functions as one of the source and drain electrodes of the transistor 10a, and another part of the conductive layer 155 functions as one of the source and drain electrodes of the transistor 10b. A part of the conductive layer 160 functions as the other of the source and drain electrodes of the transistor 10a, and another part of the conductive layer 160 functions as the other of the source and drain electrodes of the transistor 10b. A part of the conductive layer 163 functions as the gate electrode of the transistor 10a, and another part of the conductive layer 163 functions as the gate electrode of the transistor 10b.

[0214] 15D, one of the source or drain of transistor 10a is electrically connected to one of the source or drain of transistor 10b, and the other of the source or drain of transistor 10a is electrically connected to the other of the source or drain of transistor 10b. Furthermore, the gate of transistor 10a is electrically connected to the gate of transistor 10b. Therefore, transistors 10a and 10b are simultaneously switched between on and off states and function as a single transistor 10.

[0215] By connecting multiple transistors 10 (here, transistors 10a and 10b) in series, it is possible to increase the apparent channel length L of each transistor 10. Increasing the channel length L allows the saturation characteristics of the transistor 10 to be improved.

[0216] FIG. 16A is a plan view of a transistor 10 including a transistor 10a and a transistor 10b. FIG. 16B is a cross-sectional view of the portion indicated by the dashed dotted line A1-A2 in FIG. 16A. FIG. 16C is a perspective view of a transistor 10 including a transistor 10a and a transistor 10b. FIG. 16D is an equivalent circuit diagram of a transistor 10 including a transistor 10a and a transistor 10b. To facilitate understanding of the configuration of the transistor 10, some of the components of the transistor 10 are omitted in FIGS. 16A and 16C.

[0217] The transistors 10a and 10b have a similar configuration to the transistor 10 described with reference to FIG. 15, but differ in that the conductive layer 155 is separated into conductive layers 155a and 155b.

[0218] The conductive layer 155a functions as one of the source electrode and the drain electrode of the transistor 10a, and part of the conductive layer 160 functions as the other of the source electrode and the drain electrode of the transistor 10a. Another part of the conductive layer 160 functions as one of the source electrode and the drain electrode of the transistor 10b, and the conductive layer 155b functions as the other of the source electrode and the drain electrode of the transistor 10b. Similarly to the transistor 10 described with reference to FIG. 15 , part of the conductive layer 163 functions as the gate electrode of the transistor 10a, and another part of the conductive layer 163 functions as the gate electrode of the transistor 10b.

[0219] 16D, the other of the source or the drain of the transistor 10a is electrically connected to the one of the source or the drain of the transistor 10b, and the gate of the transistor 10a is electrically connected to the gate of the transistor 10b. Thus, the transistors 10a and 10b are simultaneously switched between on and off and function as a single transistor 10.

[0220] [Planar and Cross-Sectional Configuration Examples of Signal Output Circuit 110] Next, examples of planar and cross-sectional configurations of the signal output circuit 110 will be described with reference to the drawings. In this embodiment, examples of planar and cross-sectional configurations of the signal output circuit 110a shown in FIG. 2 will be described.

[0221] FIG. 17 is a diagram showing an example of the planar configuration of the signal output circuit 110a. FIG. 18 is an enlarged plan view of a region including transistors 10[7] to 10

[11] in FIG. 17. FIG. 19A is a diagram showing an example of the cross-sectional configuration of a portion indicated by a dashed line passing through A1-A2 in FIG. 17. FIG. 19B is a diagram showing an example of the cross-sectional configuration of a portion indicated by a dashed line passing through A2-A3 in FIG. 17. FIG. 20A is a diagram showing an example of the cross-sectional configuration of a portion indicated by a dashed line passing through A4-A5 in FIG. 17. FIG. 20B is a diagram showing an example of the cross-sectional configuration of a portion indicated by a dashed line passing through A6-A7 in FIG. 17. FIG. 21A is a diagram showing an example of the cross-sectional configuration of a portion indicated by a dashed line passing through A8-A9 in FIG. 18. FIG. 21B is a diagram showing an example of the cross-sectional configuration of a portion indicated by a dashed line passing through A9-A10 in FIG. 18.

[0222] In this embodiment, a configuration example will be described in which the above-mentioned VFET is used as the transistor 10 of the signal output circuit 110a. The signal output circuit 110a has an insulating layer 154 on a substrate 148, and a conductive layer 155 (e.g., conductive layer 155[1] and conductive layer 155[3] in FIG. 19A, conductive layer 155[3] and conductive layer 155[4] in FIG. 19B, and conductive layer 155

[10] and conductive layer 155

[11] in FIG. 20) on the insulating layer 154.

[0223] The stacked structure of the signal output circuit 110a using the above-described VFET as the transistor 10 has some common parts with the above-described example configuration of the transistor 10. Therefore, the following mainly describes the parts that are different from the above-described example configuration of the transistor 10.

[0224] In this specification and the like, the reference numerals of components related to the transistor 10[1] may be denoted by the reference numeral [1] for identification. For example, the conductive layer 163 functioning as the gate electrode of the transistor 10[1] may be referred to as the conductive layer 163[1]. Note that the reference numerals of components common to multiple transistors 10 may be denoted by the reference numeral [1] for identification of one of the multiple transistors 10. For example, the conductive layer 163 functioning as the gate electrode of each of the transistors 10[2], 10[9], and 10

[11] may be referred to as the conductive layer 163[2].

[0225] For example, the opening 159 and the semiconductor layer 161 of the transistor 10[3] may be referred to as the opening 159[3] and the semiconductor layer 161[3]. For example, the opening 159 and the semiconductor layer 161 of the transistor 10[4] may be referred to as the opening 159[4] and the semiconductor layer 161[4]. For example, the opening 159 and the semiconductor layer 161 of the transistor 10[7] may be referred to as the opening 159[7] and the semiconductor layer 161[7]. For example, the opening 159 and the semiconductor layer 161 of the transistor 10[8] may be referred to as the opening 159[8] and the semiconductor layer 161[8]. For example, the opening 159 and the semiconductor layer 161 of the transistor 10

[10] may be referred to as the opening 159

[10] and the semiconductor layer 161

[10] .

[0226] The signal output circuit 110a includes conductive layers 181[1] to 181[4] over the insulating layer 158 (see FIG. 17 and FIG. 20A). The conductive layers 181 (the conductive layers 181[1] to 181[4]) can be formed using a material and a method similar to those of the conductive layer 160. The conductive layer 181 can be formed simultaneously with the conductive layer 160.

[0227] The signal output circuit 110a also has an insulating layer 187 on the insulating layer 164. The insulating layer 187 preferably functions as a planarizing layer that reduces steps caused by transistors, capacitors, wiring, and the like formed in the underlying layers. An organic insulating film is suitable as a material that functions as a planarizing layer. After the insulating layer 187 is formed using an inorganic or organic material, the insulating layer 187 may be subjected to planarization treatment using a chemical mechanical polishing (CMP) method or the like.

[0228] The signal output circuit 110a also includes conductive layers 191 to 199, a wiring 131, and a wiring 132 over the insulating layer 187 (see FIGS. 17, 19A, 19B, and 20A). The conductive layers 191 to 199, the wiring 131, and the wiring 132 can be formed using the same materials and methods as the other conductive layers. The conductive layer 191 functions as the terminal 111, the conductive layer 192 functions as the terminal 112, the conductive layer 193 functions as the terminal 113, the conductive layer 194 functions as the terminal 114, the conductive layer 195 functions as the terminal 115, the conductive layer 196 functions as the terminal 116, the conductive layer 197 functions as the terminal 117, and the conductive layer 198 functions as the terminal 118.

[0229] In addition, the signal output circuit 110a has openings that penetrate the insulating layer 162, the insulating layer 164, and the insulating layer 187 on the conductive layer 160[2], the conductive layer 160[3], the conductive layer 181[1], the conductive layer 181[2], the conductive layer 181[3], and the conductive layer 181[4], respectively.

[0230] The wiring 132 and the conductive layer 160[2] are electrically connected to each other through an opening provided in the conductive layer 160[2]. More specifically, the wiring 132 and the conductive layer 160[2] are electrically connected to each other at the bottom of the opening provided in the conductive layer 160[2].

[0231] Two openings are provided over the conductive layer 160[3]. The wiring 131 and the conductive layer 160[3] are electrically connected through one of the two openings. The conductive layer 199 and the conductive layer 160[3] are electrically connected through the other opening.

[0232] In addition, the conductive layer 191 and the conductive layer 181[1] are electrically connected in an opening provided over the conductive layer 181[1]. In addition, the conductive layer 194 and the conductive layer 181[2] are electrically connected in an opening provided over the conductive layer 181[3]. In addition, the conductive layer 198 and the conductive layer 181[3] are electrically connected in an opening provided over the conductive layer 181[4]. In addition, the conductive layer 196 and the conductive layer 181[4] are electrically connected in an opening provided over the conductive layer 181[4].

[0233] In addition, the signal output circuit 110a has openings that penetrate the insulating layer 164 and the insulating layer 187 on each of the conductive layers 163[1], 163[3], 163[4], 163[5], and 163[7].

[0234] In an opening provided on the conductive layer 163[1], the conductive layer 197 and the conductive layer 163[1] are electrically connected. In an opening provided on the conductive layer 163[3], the conductive layer 193 and the conductive layer 163[3] are electrically connected. In an opening provided on the conductive layer 163[4], the conductive layer 192 and the conductive layer 163[4] are electrically connected. In an opening provided on the conductive layer 163[5], the conductive layer 195 and the conductive layer 163[5] are electrically connected. In an opening provided on the conductive layer 163[7], the conductive layer 199 and the conductive layer 163[7] are electrically connected. The conductive layer 160[3] and the conductive layer 163[7] are electrically connected through the conductive layer 199.

[0235] In addition, the signal output circuit 110a has openings that penetrate insulating layers 156, 157, and 158 on each of conductive layer 155[1], conductive layer 155[2], conductive layer 155[3], conductive layer 155[4], conductive layer 155[8], conductive layer 155[9], conductive layer 155

[10] , and conductive layer 155

[11] .

[0236] The conductive layer 160[3] and the conductive layer 155[1] are electrically connected to each other through an opening provided over the conductive layer 155[1]. The conductive layer 160[1] and the conductive layer 155[2] are electrically connected to each other through an opening provided over the conductive layer 155[2]. The conductive layer 160[4] and the conductive layer 155[3] are electrically connected to each other through an opening provided over the conductive layer 155[3].

[0237] In addition, the conductive layer 181[1] and the conductive layer 155[8] are electrically connected to each other through an opening provided over the conductive layer 155[8]. In addition, the conductive layer 181[3] and the conductive layer 155

[10] are electrically connected to each other through an opening provided over the conductive layer 155

[10] .

[0238] Two openings are provided on the conductive layer 155[9]. In one of the two openings, the conductive layer 160[8] and the conductive layer 155[9] are electrically connected. In the other of the two openings, the conductive layer 181[2] and the conductive layer 155[9] are electrically connected.

[0239] Two openings are provided on the conductive layer 155

[11] . In one of the two openings, the conductive layer 160

[10] and the conductive layer 155

[11] are electrically connected. In the other of the two openings, the conductive layer 181[4] and the conductive layer 155

[11] are electrically connected.

[0240] Furthermore, in the signal output circuit 110a, openings penetrating the insulating layers 156, 157, and 158 are provided on the conductive layers 155[4] and 155[7], respectively.

[0241] The conductive layer 163[2] and the conductive layer 155[4] are electrically connected through an opening provided on the conductive layer 155[4] (see FIG. 20B). The conductive layer 163[8] and the conductive layer 155[7] are electrically connected through an opening provided on the conductive layer 155[7] (see FIGS. 21A and 21B).

[0242] The conductive layer 155[4] also functions as the conductive layer 155[5] and the conductive layer 155[6]. The conductive layer 160[1] also functions as the conductive layer 160[7]. The conductive layer 160[2] also functions as the conductive layer 160[6], the conductive layer 160[9], and the conductive layer 160

[11] . The conductive layer 160[3] also functions as the conductive layer 160[5]. The conductive layer 163[1] also functions as the conductive layer 163[6]. The conductive layer 163[2] also functions as the conductive layer 163[9] and the conductive layer 163

[11] . The conductive layer 163[8] also functions as the conductive layer 163

[10] .

[0243] The region where the conductive layer 155[4] and the conductive layer 160[6] overlap with the insulating layer 156, the insulating layer 157, and the insulating layer 158 interposed therebetween functions as the capacitor 20[1].

[0244] Furthermore, by electrically connecting the conductive layer 160[8] and the conductive layer 155[9], the capacitance C1 of the transistor 10[8] can be used as the capacitance 20[2]. By using the capacitance C1 of the transistor 10[8] as the capacitance 20[2], it is not necessary to separately provide the capacitance 20[2], and therefore a semiconductor device with a small occupation area can be realized (see FIG. 17). Therefore, it is preferable to use a VFET according to one embodiment of the present invention as the transistor 10[8].

[0245] Furthermore, by electrically connecting the conductive layer 160

[10] and the conductive layer 155

[11] , the capacitance C1 of the transistor 10

[10] can be used as the capacitance 20[3]. By using the capacitance C1 of the transistor 10

[10] as the capacitance 20[3], it is not necessary to separately provide the capacitance 20[3], and therefore a semiconductor device with a small occupation area can be realized (see FIGS. 17 and 20A). Therefore, it is preferable to use a VFET according to one embodiment of the present invention as the transistor 10

[10] .

[0246] FIG. 22 shows a circuit diagram of a signal output circuit 110a in which the capacitance C1 of the transistor 10[8] is used as the capacitance 20[2] and the capacitance C1 of the transistor 10

[10] is used as the capacitance 20[3].

[0247] The transistors other than the transistor 10

[10] and the transistor 10

[10] may be transistors other than VFETs. However, in order to realize a semiconductor device with a reduced occupation area, it is preferable to use many transistors according to one embodiment of the present invention in the signal output circuit 110a. Therefore, it is preferable to use transistors according to one embodiment of the present invention for all the transistors included in the signal output circuit 110a.

[0248] [Example of Operation of Signal Output Circuit] Next, an example of operation of the signal output circuit 110 will be described with reference to the drawings. In this embodiment, an example of operation of the signal output circuit 110a shown in FIG. 2 among the signal output circuits 110 will be described.

[0249] Fig. 23 is a timing chart for explaining an example of the operation of the signal output circuit 110a[i]. Fig. 24 to Fig. 30 are circuit diagrams for explaining an example of the operation of the signal output circuit 110a[i].

[0250] In addition, in drawings and the like, to indicate the potential of a wiring or the like, "H" indicating a potential H or "L" indicating a potential L may be written adjacent to the wiring or the like. Also, "H" or "L" may be enclosed in letters next to an electrode or the like in which a potential change occurs. Furthermore, when a transistor is in an off state, an "x" symbol may be written over the transistor.

[0251] A potential H (VDD) is supplied to the wiring 131, and a potential L (VSS) is supplied to the wiring 132. A signal CLK_1 is supplied to the terminal 111, a signal CLK_2 is supplied to the terminal 112, a signal CLK_3 is supplied to the terminal 113, and a signal PWC_1 is supplied to the terminal 118.

[0252] Also, immediately before the period T1, the signal CLK_1 is at a potential L, the signal CLK_2 is at a potential H, the signal CLK_3 is at a potential H, the signal PWC_1 is at a potential L, and the signal LIN is at a potential L. Also, the transistors 10[2], 10[3], 10[4], 10[9], and 10

[11] are assumed to be in an on state. Also, the transistors 10[1], 10[5], 10[6], 10[7], 10[8], and 10

[10] are assumed to be in an off state.

[0253] Furthermore, the signal CLK_4 and the signals PWC_2 to PWC_4 are assumed to be at a potential L. However, the signal CLK_4 and the signals PWC_2 to PWC_4 are not related to the operation of the signal output circuit 110a[i] described here, and therefore are not used in describing the operation of the signal output circuit 110a[i].

[0254] In the period T1, the signal CLK_2 is at a potential L, and the signal LIN is at a potential H (see FIGS. 23 and 24). This causes the transistors 10[1] and 10[6] to be turned on. This causes the potential of the node ND[1] to be at a potential L, and the transistors 10[2], 10[9], and 10

[11] to be turned off.

[0255] Furthermore, the potentials of the nodes ND[2] and ND[3] become a potential (potential H-Vth) that is lower than the potential H by the Vth of the transistor 10[1]. Here, the value of the potential H-Vth is set to be equal to or higher than the Vth of the transistor. Therefore, the transistors 10[8] and 10

[10] are turned on. The potential L is output from the terminal 116 as the signal OUT, and the potential L is output from the terminal 114 as the signal SROUT.

[0256] During the period T2, the signal CLK_1 is at a potential H, the signal CLK_3 is at a potential L, and the signal PWC_1 is at a potential H. This causes the transistor 10[3] to be turned off. At time T2a (see FIGS. 23 and 25 ) at the start of the period T2, the potential of the node ND[3] is at a potential H−Vth, so the potential of the terminal 114 is at a potential H−Vth−Vth, and the potential of the terminal 116 is at a potential H−Vth−Vth.

[0257] On the other hand, the terminal 114 and the node ND[3] are connected (capacitively coupled) through a capacitor 20[2]. The terminal 116 and the node ND[3] are connected through a capacitor 20[3]. The capacitors 20[2] and 20[3] function as bootstrap capacitors. Therefore, as the potentials of the terminals 114 and 116 increase, the potential of the node ND[3] also increases.

[0258] At this time, the potential of the node ND[2] also rises, but the moment the potential of the node ND[2] exceeds the potential H-Vth, the transistors 10[1] and 10[7] are turned off, and the nodes ND[2] and ND[3] are placed in a floating state. The potential of the node ND[3] also rises to the potential H-Vth+potential H (2×potential H-Vth) (time T2b; see FIGS. 23 and 26). Because this potential is higher than the potential H+Vth, the potentials of the terminals 114 and 116 can be set to the potential H.

[0259] If the signal output circuit 110a did not include the transistor 10[7], a voltage of 2× potential H−Vth−Vss would be applied to the drain of the transistor 10[2]. Because Vss is applied to the source of the transistor 10[2], an excessive voltage (2× potential H−Vth−Vss) would be applied between the source and drain of the transistor 10[2]. As a result, the characteristics of the transistor 10[2] would be easily deteriorated or damaged.

[0260] By having transistor 10[7] between the drain of transistor 10[2] and node ND[3], the potential of node ND[2] (the drain of transistor 10[2]) does not rise even when the potential of node ND[3] becomes 2× potential H-Vth, thereby preventing deterioration of the characteristics and damage of transistor 10[2].

[0261] In the period T3, the signal CLK_2 is at a potential H, the signal PWC_1 is at a potential L, and the signal LIN is at a potential L (see FIGS. 23 and 27). This causes the transistor 10[4] to be turned on. The potential of the terminal 116 is set to a potential L. The transistor 10[6] is turned off, and the nodes ND[1] and ND[2] are set to a floating state.

[0262] In the period T4, the signal CLK_1 is at a potential L, the signal CLK_3 is at a potential H, and the signal RIN is at a potential H (see FIGS. 23 and 28). Then, the transistors 10[3] and 10[5] are turned on, and the potential of the node ND[1] is at a potential H. When the potential of the node ND[1] is at a potential H, the transistors 10[2], 10[9], and 10

[11] are turned on.

[0263] When the transistor 10[2] is turned on, the potential of the node ND[2] becomes the potential L. Then, the transistor 10[7] is turned on, and the potential of the node ND[3] also becomes the potential L. Therefore, the transistors 10[8] and 10

[10] are turned off. Furthermore, when the transistors 10[9] and 10

[11] are turned on, the potential L is supplied to the terminal 114, and the potential of the terminal 116 (potential L) is maintained.

[0264] 18 , 21A, and 21B, in the signal output circuit 110a according to one embodiment of the present invention, the conductive layer 163[8] and the conductive layer 155[7] are electrically connected to each other. The conductive layer 163[8] functions as the gate electrodes of the transistor 10[8] and the transistor 10

[10] . The conductive layer 155[7] functions as the drain electrode (or source electrode) of the transistor 10[7]. The conductive layer 155[7] functions as the node ND[3]. The conductive layer 160[1] functions as the source electrode (or drain electrode) of the transistor 10[7]. The conductive layer 160[1] functions as the node ND[2].

[0265] As will be described in the examples below, when the conductive layer 155[7] is used as a drain (drain electrode), the on-state current of the transistor 10[7] can be increased more than when the conductive layer 155[7] is used as a source (source electrode).

[0266] When one or both of the capacitors 20[2] and 20[3] are connected to the node ND[3], the charge and discharge times required to change the potential of the node ND[3] become longer. The charge and discharge times required to change the potential of the node ND[3] become shorter as the on-current of the transistor 10[7] increases.

[0267] By electrically connecting the conductive layer 163[8] and the conductive layer 155[7], the conductive layer 155[7] functions as a drain and the conductive layer 160[1] functions as a source in the period T3. Therefore, when the transistor 10[7] is turned on in the period T4, the potential of the node ND[3] can be quickly set to potential L. This can increase the operating speed of the signal output circuit 110a. Furthermore, the operating speed of a semiconductor device using the signal output circuit 110a can be increased.

[0268] Furthermore, if the potential of the node ND[3] is not reliably set to potential L after the period T4, a through current may flow between the terminal 118 and the wiring 132. Similarly, a through current may flow between the terminal 111 and the wiring 132. By electrically connecting the conductive layer 163[8] and the conductive layer 155[7], the potential of the node ND[3] can be reliably set to potential L in the period T4. Therefore, the power consumption of the signal output circuit 110a can be reduced. Furthermore, the power consumption of a semiconductor device using the signal output circuit 110a can be reduced.

[0269] Furthermore, by electrically connecting the conductive layer 163[8] and the conductive layer 160[1] (conductive layer 160[7]), the conductive layer 155[7] functions as a source and the conductive layer 160[1] functions as a drain in the period immediately before the period T1. Therefore, the time required for the potential of the node ND[3] to change can be shortened in the period T1. That is, the potential of the node ND[3] can be quickly set to the potential H-Vth. Therefore, the operating speed of the signal output circuit 110a can be increased. Furthermore, the operating speed of a semiconductor device using the signal output circuit 110a can be increased.

[0270] On the other hand, when the conductive layer 155[7] functions as the source of the transistor 10[7] and the conductive layer 160[1] functions as the drain of the transistor 10[7], it is difficult to obtain a reduction effect in power consumption. Therefore, it is preferable that the conductive layer 155[7] functions as the drain of the transistor 10[7] and the conductive layer 160[1] functions as the source of the transistor 10[7]. It is preferable that the conductive layer 163[8] and the conductive layer 155[7] are electrically connected to each other.

[0271] In the period T5, the signal CLK_2 is set to the potential L (see FIGS. 23 and 29). As a result, the transistor 10[4] is turned off.

[0272] In the period T6, the signal CLK_3 and the signal RIN are set to the potential L (see FIGS. 23 and 30). As a result, the transistor 10[3] and the transistor 10[5] are turned off. When the transistor 10[5] is turned off, the node ND[1] is brought into a floating state.

[0273] Thereafter, the potential L is supplied to the terminal 114 and the terminal 116 until the potential H is supplied as the signal LIN to the terminal 117. That is, the potential L is output as the signal OUT and the signal SROUT until the potential H is supplied as the signal LIN to the terminal 117.

[0274] In this way, the signal output circuit [i] can output pulse signals from the terminals 114 and 116 in synchronization with a specific combination of signals. The pulse width (the time during which the potential H is output) of the signal SROUT, which is the pulse signal output from the terminal 114, is linked to the signal CLK. The pulse width (the time during which the potential H is output) of the signal OUT, which is the pulse signal output from the terminal 116, is linked to the signal PWC.

[0275] The signal output circuit [i] according to one embodiment of the present invention includes a capacitor that functions as a bootstrap capacitance, and thus can reliably output a power supply potential (potential H) from the terminal 114 and the terminal 116. Therefore, the signal output circuit [i] according to one embodiment of the present invention has low output impedance and can reliably supply the potential H to a load such as a circuit connected to the terminal 114 or the terminal 116. Therefore, the operation of a semiconductor device including the signal output circuit [i] according to one embodiment of the present invention is stabilized, and the reliability of the semiconductor device can be improved.

[0276] The capacitance C1 of the transistor 10[1] is preferably formed between the node ND[1] and the gate of the transistor 10[1]. The capacitance C2 of the transistor 10[1] is preferably formed between the wiring 131 to which a power supply potential is supplied and the gate of the transistor 10[1] (see FIG. 31).

[0277] The node ND[1] is in a floating state except during the period when both the signal CLK_2 and the signal CLK_3 are at the H potential. To suppress the potential fluctuation of the node ND[1] during this period and ensure more stable operation of the signal output circuit [i] according to one embodiment of the present invention, a capacitor C1 is preferably formed between the gate and a wiring 132 to which a power supply potential is supplied in each of the transistors 10[2], 10[6], 10[9], and 10

[11] . Specifically, the conductive layer 160[2] is preferably electrically connected to the wiring 132 (see FIG. 17 ). The conductive layer 160[2] functions as a source electrode of each of the transistors 10[2], 10[6], 10[9], and 10

[11] .

[0278] By forming the capacitance C1 of each of the transistors 10[2], 10[9], and 10

[11] between the wiring 132 and the gate, the capacitance C1 of each of the transistors is connected in parallel to the capacitance 20[1]. This can enhance the effect of suppressing the potential fluctuation of the node ND[1] (see FIG. 31).

[0279] Furthermore, by forming the capacitance C2 of the transistor 10[6] between the node ND[1] and the gate of the transistor 10[6], the influence of the potential fluctuation of the signal input to the gate of the transistor 10[6] on the node ND[1] can be reduced more than when the capacitance C1 is formed between the node ND[1] and the gate of the transistor 10[6].

[0280] To suppress potential fluctuations at the node ND[1] and ensure more stable operation of the signal output circuit [i] according to one embodiment of the present invention, the capacitor C2 of each of the transistors 10[4] and 10[5] is preferably formed between the node ND[1] and the gate. The capacitor C1 of the transistor 10[5] is preferably formed between the gate and a wiring 131 to which a power supply potential is supplied. Specifically, the conductive layer 160[3] is preferably electrically connected to the wiring 131 (see FIG. 17). The conductive layer 160[3] functions as a drain electrode of the transistor 10[5].

[0281] The capacitor C1 of the transistor 10[4] is preferably formed between the drain and gate of the transistor 10[4]. The capacitor C1 of the transistor 10[3] is preferably formed between the wiring 131 and the gate of the transistor 10[3]. Specifically, the conductive layer 160[3] is preferably electrically connected to the wiring 131 (see FIG. 17). The conductive layer 160[3] functions as the drain electrode of the transistor 10[3]. The capacitor C2 of the transistor 10[3] is preferably formed between the source and gate of the transistor 10[3].

[0282] In order to ensure more stable operation of the signal output circuit [i] according to one embodiment of the present invention, the capacitance value of the parasitic capacitance generated between the node ND[3] and the gate of the transistor 10[7] is preferably smaller than the capacitance values ​​of the capacitors 20[2] and 20[3]. Therefore, in the transistor 10[7], it is preferable that the capacitance C1 be generated between the gate and one of the source or the drain of the transistor 10[7], and the capacitance C2 be generated between the gate and the other of the source or the drain of the transistor 10[7] (see FIG. 31).

[0283] 10 includes a transistor 10

[13] and a transistor 10

[14] . The capacitance C1 of the transistor 10

[13] is preferably formed between the wiring 135 and the gate of the transistor 10

[13] (see FIG. 32). That is, it is preferably formed between the drain and gate of the transistor 10

[13] . Therefore, the capacitance C2 of the transistor 10

[13] is preferably formed between the source and gate of the transistor 10

[13] .

[0284] The potential SMP supplied to the wiring 135 is a fixed potential, and the gate of the transistor 10

[13] is electrically connected to the node ND[2]. By forming a capacitance C1 between the wiring 135 and the gate of the transistor 10

[13] , it is possible to enhance the effect of suppressing the potential fluctuation of the node ND[2] when the node ND[2] is in a floating state.

[0285] The capacitance C1 of the transistor 10

[14] is preferably formed between the wiring 136 and the gate of the transistor 10

[14] . That is, it is preferably formed between the drain and gate of the transistor 10

[14] (see FIG. 32). Therefore, the capacitance C2 of the transistor 10

[14] is preferably formed between the source and gate of the transistor 10

[14] .

[0286] The potential SMP supplied to the wiring 136 is a fixed potential, and the gate of the transistor 10

[14] is electrically connected to the node ND[1]. By forming a capacitance C1 between the wiring 136 and the gate of the transistor 10

[14] , it is possible to enhance the effect of suppressing the potential fluctuation of the node ND[1] when the node ND[1] is in a floating state.

[0287] <Operation Example of Shift Register 100> Next, an operation example of the shift register 100 shown in Fig. 1A will be described with reference to Fig. 33. Fig. 33 is a timing chart illustrating an operation example of the shift register 100. Fig. 33 illustrates potential changes of signals CLK_1 to CLK_4, which are clock signals, signals PWC_1 to PWC_4, which determine the pulse width of the signal OUT, signal LIN[1] input to the signal output circuit 110[1], signals OUT[1] to OUT[4] output from the signal output circuits 110[1] to 110[4], signal OUT[n] output from the signal output circuit 110[n], signal OUT[n+1] output from the signal output circuit 110[n+1], and signal OUT[n+2] output from the signal output circuit 110[n+2].

[0288] First, in a period T51, the signal output circuit 110[1] is supplied with a signal LIN[1] of a potential H. In a period T52, a signal OUT[1] of a potential H is output in synchronization with the signal LIN[1], the signal CLK_1, the signal CLK_4, and the signal PWC_1.

[0289] Subsequently, in a period T53, a potential L is output as the signal OUT[1]. Furthermore, a potential H is output as the signal OUT[2] in synchronization with the signals CLK_1, CLK_2, and PWC_2.

[0290] Subsequently, in a period T54, a potential L is output as the signal OUT[2]. Furthermore, a potential H is output as the signal OUT[3] in synchronization with the signals CLK_3, CLK_4, and PWC_3.

[0291] Subsequently, in a period T55, a potential L is output as the signal OUT[3]. Furthermore, a potential H is output as the signal OUT[4] in synchronization with the signals CLK_3, CLK_4, and PWC_4. In this manner, the potential H is output as the signal OUT in order from the first stage to the (n+2)th stage.

[0292] Thereafter, a potential H is again supplied to the signal output circuit 110[1] as the signal LIN[1], thereby causing the shift register 100 to repeat the above operation. Note that the period from when the potential H is input to the signal output circuit 110[1] as the signal LIN[1] until the potential H is again input as the signal LIN[1] may be referred to as a frame period 176. Also, the signal LIN input to the signal output circuit 110[1] may be referred to as a "start pulse SP."

[0293] Note that as a transistor used in a semiconductor device such as a signal output circuit according to one embodiment of the present invention, a transistor having a structure other than a VFET, such as a planar transistor or a staggered transistor, may be used. Alternatively, a VFET and a transistor having a structure other than a VFET may be used in combination.

[0294] The signal output circuit 110 used in the shift register 100 is not limited to the configuration disclosed in this specification etc. Various circuit configurations can be used as the signal output circuit 110 used in the shift register 100.

[0295] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments.

[0296] Embodiment 2 In this embodiment, a metal oxide (hereinafter also referred to as an oxide semiconductor) that can be used for the OS transistor described in the above embodiment will be described.

[0297] The metal oxide used in the OS transistor preferably contains at least indium or zinc, and more preferably contains indium and zinc. For example, the metal oxide preferably contains indium, M (M is one or more selected from gallium, aluminum, yttrium, tin, silicon, boron, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and cobalt), and zinc. In particular, M is preferably one or more selected from gallium, aluminum, yttrium, antimony, and tin, and more preferably gallium.

[0298] The metal oxide can be formed by a sputtering method, a CVD method such as a metal organic chemical vapor deposition (MOCVD) method, or an ALD method.

[0299] The ALD method allows atoms to be deposited layer by layer, and therefore has the advantages of enabling ultrathin film formation, film formation on structures with high aspect ratios, film formation with fewer defects such as pinholes, film formation with excellent coverage, and film formation at low temperatures. The ALD method also includes thermal ALD, a film formation method that utilizes heat, and plasma-enhanced ALD (PEALD), a film formation method that utilizes plasma. The use of plasma may enable film formation at lower temperatures, which may be preferable. Note that some precursors used in the ALD method contain elements such as carbon or chlorine. Therefore, films formed by the ALD method may contain more elements such as carbon or chlorine than films formed by other film formation methods. The amounts of these elements can be determined by XPS or secondary ion mass spectrometry (SIMS).

[0300] Unlike film formation methods in which particles emitted from a target or the like are deposited, the ALD method is a film formation method in which a film is formed by a reaction on the surface of a workpiece. Therefore, it is a film formation method that is less affected by the shape of the workpiece and has good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surface of an opening with a high aspect ratio.

[0301] Hereinafter, an oxide containing indium (In), gallium (Ga), and zinc (Zn) will be described as an example of a metal oxide. Note that an oxide containing indium (In), gallium (Ga), and zinc (Zn) may be referred to as an In—Ga—Zn oxide.

[0302] <Classification of Crystal Structure> Examples of the crystal structure of an oxide semiconductor include amorphous (including completely amorphous), c-axis-aligned crystalline line (CAAC), nanocrystalline line (nc), cloud-aligned composite (CAC), single crystal, and polycrystalline.

[0303] The crystalline structure of a film or substrate can be evaluated using an X-ray diffraction (XRD) spectrum. For example, it can be evaluated using an XRD spectrum obtained by GIXD (Grazing-Incident XRD) measurement. The GIXD method is also called the thin film method or the Seemann-Bohlin method. In the following, the XRD spectrum obtained by GIXD measurement may be simply referred to as the XRD spectrum.

[0304] For example, in the case of a quartz glass substrate, the peak shape of the XRD spectrum is almost symmetrical. On the other hand, in the case of an In-Ga-Zn oxide film having a crystalline structure, the peak shape of the XRD spectrum is asymmetrical. The asymmetrical peak shape of the XRD spectrum clearly indicates the presence of crystals in the film or substrate. In other words, if the peak shape of the XRD spectrum is not symmetrical, the film or substrate cannot be said to be in an amorphous state.

[0305] The crystalline structure of a film or substrate can be evaluated by a diffraction pattern (also called a nanobeam electron diffraction pattern) observed by nanobeam electron diffraction (NBED). For example, a halo is observed in the diffraction pattern of a quartz glass substrate, confirming that the quartz glass is in an amorphous state. Furthermore, a spot-like pattern is observed in the diffraction pattern of an In—Ga—Zn oxide film formed at room temperature, rather than a halo. For this reason, it is estimated that the In—Ga—Zn oxide formed at room temperature is neither single crystal nor polycrystalline, nor in an amorphous state, but is in an intermediate state, and it cannot be concluded that it is in an amorphous state.

[0306] [Structure of Oxide Semiconductor] Note that oxide semiconductors may be classified differently from the above when focusing on their structure. For example, oxide semiconductors are divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include the above-mentioned CAAC-OS and nc-OS. Non-single-crystal oxide semiconductors include polycrystalline oxide semiconductors, pseudo-amorphous-like oxide semiconductors (a-like OSs), amorphous oxide semiconductors, and the like.

[0307] Here, the above-mentioned CAAC-OS, nc-OS, and a-like OS will be described in detail.

[0308] [CAAC-OS] A CAAC-OS is an oxide semiconductor having multiple crystalline regions, each with its c-axis aligned in a specific direction. The specific direction refers to the thickness direction of the CAAC-OS film, the normal direction to the surface where the CAAC-OS film is formed, or the normal direction to the surface of the CAAC-OS film. A crystalline region is a region having periodic atomic arrangement. If the atomic arrangement is considered as a lattice arrangement, a crystalline region is also a region with a uniform lattice arrangement. Furthermore, a CAAC-OS has a region where multiple crystalline regions are connected in the a-b plane direction, and the region may have distortion. Note that distortion refers to a portion where the lattice arrangement changes between a region with a uniform lattice arrangement and a region with another uniform lattice arrangement in a region where multiple crystalline regions are connected. In other words, a CAAC-OS is an oxide semiconductor whose c-axes are aligned and whose orientation is not clearly aligned in the a-b plane direction.

[0309] Each of the multiple crystalline regions is composed of one or more minute crystals (crystals with a maximum diameter of less than 10 nm). When a crystalline region is composed of one minute crystal, the maximum diameter of the crystalline region is less than 10 nm. When a crystalline region is composed of many minute crystals, the maximum diameter of the crystalline region may be several tens of nanometers.

[0310] In an In—Ga—Zn oxide, CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium (In) and oxygen (hereinafter referred to as an In layer) and a layer containing gallium (Ga), zinc (Zn), and oxygen (hereinafter referred to as a (Ga, Zn) layer) are stacked. Note that indium and gallium are mutually substituted. Therefore, the (Ga, Zn) layer may contain indium. The In layer may contain gallium. The In layer may contain zinc. The layered structure is observed as a lattice image in a high-resolution transmission electron microscope (TEM) image, for example.

[0311] When a CAAC-OS film is subjected to structural analysis using an XRD apparatus, for example, a peak indicating c-axis orientation is detected at or near 2θ = 31° in out-of-plane XRD measurement using θ / 2θ scanning. Note that the position of the peak indicating c-axis orientation (the value of 2θ) may vary depending on the type, composition, and the like of the metal elements constituting the CAAC-OS.

[0312] For example, multiple bright spots are observed in the electron diffraction pattern of a CAAC-OS film, and the observed spots are at positions that are point-symmetric with respect to a spot of an incident electron beam that has passed through the sample (also referred to as a direct spot).

[0313] When a crystalline region is observed from the specific direction, the lattice arrangement in the crystalline region is basically a hexagonal lattice, but the unit cell is not necessarily a regular hexagon and may be a non-regular hexagon. The distortion may have a pentagonal, heptagonal, or other lattice arrangement. In the CAAC-OS, no clear grain boundary can be identified even near the distortion. This indicates that the distortion in the lattice arrangement suppresses the formation of grain boundaries. This is thought to be because the CAAC-OS can tolerate distortion due to the lack of close-packed arrangement of oxygen atoms in the a-b plane and the change in interatomic bond distance caused by metal atom substitution.

[0314] Note that a crystal structure in which clear grain boundaries are observed is called polycrystalline. The grain boundaries act as recombination centers, and are likely to trap carriers, resulting in a decrease in the on-state current of a transistor and a decrease in field-effect mobility. Therefore, CAAC-OS, in which clear grain boundaries are not observed, is one of the crystalline oxides having a crystal structure suitable for a semiconductor layer of a transistor. Note that a structure containing Zn is preferable for forming a CAAC-OS. For example, In—Zn oxide and In—Ga—Zn oxide are suitable because they can suppress the generation of grain boundaries more effectively than In oxide.

[0315] CAAC-OS is an oxide semiconductor with high crystallinity and no clear crystal grain boundaries. Therefore, it can be said that the CAAC-OS is less susceptible to a decrease in electron mobility due to crystal grain boundaries. Furthermore, since the crystallinity of an oxide semiconductor can be reduced by the inclusion of impurities and / or the generation of defects, the CAAC-OS can also be said to be an oxide semiconductor with few impurities and defects (oxygen vacancies, etc.). Therefore, an oxide semiconductor having a CAAC-OS has stable physical properties. Therefore, an oxide semiconductor having a CAAC-OS is heat-resistant and highly reliable. Furthermore, the CAAC-OS is stable even against high temperatures (so-called thermal budget) in the manufacturing process. Therefore, using a CAAC-OS for an OS transistor can increase the flexibility of the manufacturing process.

[0316] [nc-OS] The nc-OS has periodic atomic arrangement in a microscopic region (e.g., a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In other words, the nc-OS has microcrystals. Note that the size of the microcrystals is, for example, 1 nm to 10 nm, particularly 1 nm to 3 nm, and therefore the microcrystals are also called nanocrystals. Furthermore, the nc-OS does not exhibit regularity in the crystal orientation between different nanocrystals. Therefore, no orientation is observed throughout the film. Therefore, depending on the analysis method, the nc-OS may be indistinguishable from an a-like OS and an amorphous oxide semiconductor. For example, when a structural analysis of an nc-OS film is performed using an XRD apparatus, no peak indicating crystallinity is detected in out-of-plane XRD measurement using θ / 2θ scanning. When an nc-OS film is subjected to electron diffraction (also referred to as selected-area electron diffraction) using an electron beam with a probe diameter larger than that of a nanocrystal (e.g., 50 nm or more), a diffraction pattern resembling a halo pattern is observed. On the other hand, when an nc-OS film is subjected to electron diffraction (also referred to as nanobeam electron diffraction) using an electron beam with a probe diameter close to or smaller than that of a nanocrystal (e.g., 1 nm to 30 nm), an electron diffraction pattern in which multiple spots are observed within a ring-shaped region centered on a direct spot may be obtained.

[0317] [a-Like OS] The a-like OS is an oxide semiconductor having a structure between the nc-OS and an amorphous oxide semiconductor. The a-like OS has pores or low-density regions. That is, the a-like OS has lower crystallinity than the nc-OS and CAAC-OS. Furthermore, the a-like OS has a higher hydrogen concentration in the film than the nc-OS and CAAC-OS.

[0318] [Structure of Oxide Semiconductor] Next, the above-described CAC-OS will be described in detail. Note that the CAC-OS relates to a material structure.

[0319] [CAC-OS] CAC-OS is, for example, a material in which elements constituting a metal oxide are unevenly distributed in a size of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or in the vicinity thereof. Note that hereinafter, a state in which one or more metal elements are unevenly distributed in a metal oxide and regions containing the metal elements are mixed in a size of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or in the vicinity thereof, is also referred to as a mosaic or patch state.

[0320] Furthermore, the CAC-OS has a mosaic structure in which a material is separated into a first region and a second region, and the first region is distributed throughout the film (hereinafter also referred to as a cloud structure). That is, the CAC-OS is a composite metal oxide having a structure in which the first region and the second region are mixed.

[0321] Here, the atomic ratios of In, Ga, and Zn to the metal elements constituting the CAC-OS in the In—Ga—Zn oxide are denoted as [In], [Ga], and [Zn], respectively. For example, in the CAC-OS in the In—Ga—Zn oxide, the first region is a region where [In] is larger than [In] in the composition of the CAC-OS film. The second region is a region where [Ga] is larger than [Ga] in the composition of the CAC-OS film. Alternatively, for example, the first region is a region where [In] is larger than [In] in the second region and [Ga] is smaller than [Ga] in the second region. The second region is a region where [Ga] is larger than [Ga] in the first region and [In] is smaller than [In] in the first region.

[0322] Specifically, the first region is a region whose main component is indium oxide, indium zinc oxide, or the like. The second region is a region whose main component is gallium oxide, gallium zinc oxide, or the like. In other words, the first region can be rephrased as a region whose main component is In. The second region can be rephrased as a region whose main component is Ga.

[0323] It should be noted that there are cases where a clear boundary between the first region and the second region cannot be observed.

[0324] Furthermore, CAC-OS in In—Ga—Zn oxide refers to a structure in which a mosaic of regions containing Ga as the main component and regions containing In as the main component are randomly arranged in a material composition containing In, Ga, Zn, and O. Therefore, it is presumed that CAC-OS has a structure in which metal elements are distributed nonuniformly.

[0325] The CAC-OS can be formed by sputtering, for example, without intentionally heating the substrate. When forming the CAC-OS by sputtering, any one or more of an inert gas (typically argon), oxygen gas, and nitrogen gas may be used as the deposition gas. The lower the flow rate of oxygen gas relative to the total flow rate of deposition gas during deposition, the more preferable it is. For example, the flow rate of oxygen gas relative to the total flow rate of deposition gas during deposition is set to 0% or more and less than 30%, preferably 0% or more and 10% or less.

[0326] Furthermore, for example, in the case of CAC-OS in an In—Ga—Zn oxide, EDX mapping obtained using energy dispersive X-ray spectroscopy (EDX) can confirm that the CAC-OS has a structure in which a region containing In as a main component (first region) and a region containing Ga as a main component (second region) are unevenly distributed and mixed.

[0327] Here, the first region has higher conductivity than the second region. That is, the flow of carriers through the first region causes the metal oxide to exhibit conductivity. Therefore, the first region is distributed in a cloud-like manner in the metal oxide, thereby achieving a high field-effect mobility (μ).

[0328] On the other hand, the second region has higher insulating properties than the first region. That is, the second region is distributed in the metal oxide, thereby suppressing leakage current.

[0329] Therefore, when a CAC-OS is used in a transistor, the conductivity due to the first region and the insulating property due to the second region act complementarily, thereby providing the CAC-OS with a switching function (a function of turning on / off). That is, a CAC-OS has a conductive function in a part of the material and an insulating function in a part of the material, and functions as a semiconductor as a whole. By separating the conductive function and the insulating function, both functions can be maximized. Therefore, by using a CAC-OS in a transistor, a high on-current (I ｏｎ), high field-effect mobility (μ), and good switching behavior can be achieved.

[0330] Furthermore, a transistor using the CAC-OS has high reliability, and therefore, the CAC-OS is ideal for various semiconductor devices such as display devices.

[0331] Oxide semiconductors have a variety of structures, each of which has different characteristics. The oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, a CAC-OS, an nc-OS, and a CAAC-OS.

[0332] <Transistor Having Oxide Semiconductor> Next, a case where the oxide semiconductor is used for a transistor will be described.

[0333] By using the oxide semiconductor for a transistor, a transistor with high field-effect mobility and high reliability can be realized.

[0334] In particular, it is preferable to use an oxide containing indium (In), gallium (Ga), and zinc (Zn) (also referred to as "IGZO") as the semiconductor layer in which the channel is formed. Alternatively, an oxide containing indium (In), aluminum (Al), and zinc (Zn) (also referred to as "IAZO") may be used as the semiconductor layer. Alternatively, an oxide containing indium (In), aluminum (Al), gallium (Ga), and zinc (Zn) (also referred to as "IAGZO") may be used as the semiconductor layer.

[0335] For the transistor, an oxide semiconductor having a low carrier concentration is preferably used. For example, the carrier concentration of the oxide semiconductor is 1×10 １７ cm −３ Below 1 × 10, preferably １５ cm −３ More preferably, 1×10 １３ cm −３ Less than 1×10, more preferably 1×10 １１ cm −３ More preferably, 1×10 １０ cm −３is less than 1×10 −９ cm −３ That is all. Note that in order to reduce the carrier concentration of an oxide semiconductor film, the impurity concentration in the oxide semiconductor film may be reduced to reduce the density of defect states. In this specification and the like, a semiconductor having a low impurity concentration and a low density of defect states is referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor. Note that an oxide semiconductor having a low carrier concentration may also be referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor.

[0336] A highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states, and therefore, the density of trap states may also be low.

[0337] Charges trapped in the trap states of an oxide semiconductor take a long time to dissipate and may behave like fixed charges. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high density of trap states may have unstable electrical characteristics.

[0338] Therefore, reducing the impurity concentration in the oxide semiconductor is effective for stabilizing the electrical characteristics of a transistor. Furthermore, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in adjacent films. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon. Note that the term "impurity" in an oxide semiconductor refers to, for example, any element other than the main component constituting the oxide semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity.

[0339] <Impurities> Here, the influence of each impurity in an oxide semiconductor will be described.

[0340] When an oxide semiconductor contains silicon or carbon, which is one of the Group 14 elements, defect levels are formed in the oxide semiconductor. Therefore, the carbon concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1×10 ２０ atoms / cm ３ Below 5 × 10, preferably １９ atoms / cm ３ Less than or equal to 3×10 １９atoms / cm ３ Less than 1×10, more preferably 1×10 １９ atoms / cm ３ Less than or equal to 3×10 １８ atoms / cm ３ More preferably, 1×10 １８ atoms / cm ３ The silicon concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1×10 ２０ atoms / cm ３ Below 5 × 10, preferably １９ atoms / cm ３ Less than or equal to 3×10 １９ atoms / cm ３ Less than 1×10, more preferably 1×10 １９ atoms / cm ３ Less than or equal to 3×10 １８ atoms / cm ３ More preferably, 1×10 １８ atoms / cm ３ The following applies.

[0341] When an oxide semiconductor contains an alkali metal or an alkaline earth metal, defect levels may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal is likely to have normally-on characteristics. Therefore, when the concentration of the alkali metal or the alkaline earth metal in the channel formation region of the oxide semiconductor obtained by SIMS is set to 1×10 １８ atoms / cm ３ Below 2 × 10, preferably １６ atoms / cm ３ Do the following:

[0342] When nitrogen is contained in an oxide semiconductor, electrons serving as carriers are generated, the carrier concentration increases, and the oxide semiconductor is likely to become n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor tends to have normally-on characteristics. Alternatively, when nitrogen is contained in an oxide semiconductor, trap states may be formed. As a result, the electrical characteristics of the transistor may become unstable. Therefore, the nitrogen concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1×10 ２０ atoms / cm ３ Below 5 × 10, preferably １９ atoms / cm ３ Less than 1×10, more preferably 1×10 １９ atoms / cm ３ Less than or equal to 5 × 10, more preferably １８ atoms / cm ３ Less than 1×10, more preferably 1×10 １８ atoms / cm ３ or less, more preferably 5 × 10 １７ atoms / cm ３ The following applies.

[0343] Hydrogen contained in an oxide semiconductor reacts with oxygen bonded to a metal atom to form water, which may form an oxygen vacancy. Hydrogen entering the oxygen vacancy may generate electrons as carriers. Furthermore, some of the hydrogen may bond with oxygen bonded to a metal atom to generate electrons as carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen is likely to have normally-on characteristics. Therefore, it is preferable to reduce hydrogen as much as possible in the channel formation region of the oxide semiconductor. Specifically, the hydrogen concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1×10 ２０ atoms / cm ３ Below 5 × 10, preferably １９ atoms / cm ３ Less than 1×10, more preferably 1×10 １９ atoms / cm ３ Less than or equal to 5 × 10, more preferably １８ atoms / cm ３ Less than 1×10, more preferably 1×10１８ atoms / cm ３ or less, more preferably 5 × 10 １７ atoms / cm ３ The following applies.

[0344] When an oxide semiconductor with sufficiently reduced impurities is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0345] <Microwave Treatment> After an oxide semiconductor is formed, the impurity concentration of the oxide semiconductor can be reduced by performing microwave treatment in an atmosphere containing oxygen. The microwave treatment refers to treatment using, for example, an apparatus having a power source that generates high-density plasma using microwaves.

[0346] By performing microwave treatment in an atmosphere containing oxygen, oxygen gas can be converted into plasma using microwaves or high-frequency waves such as RF, and the oxygen plasma can be used. Oxygen acting on an oxide semiconductor can take various forms, such as oxygen atoms, oxygen molecules, oxygen ions, and oxygen radicals (atoms, molecules, or ions having an unpaired electron, also referred to as O radicals). The oxygen acting on an oxide semiconductor may take one or more of the above forms, and oxygen radicals are particularly preferred.

[0347] Furthermore, when the microwave treatment is performed in the oxygen-containing atmosphere, the substrate is preferably heated to a temperature of 100° C. to 650° C., preferably 200° C. to 600° C., and more preferably 300° C. to 450° C., because the impurity concentration in the oxide semiconductor can be further reduced by heating the substrate.

[0348] By heating the substrate during the microwave treatment in the above-described oxygen-containing atmosphere, the carbon concentration of the oxide semiconductor obtained by SIMS was increased to 1×10 ２０ atoms / cm ３ Below 1 × 10, preferably １９ atoms / cm ３ More preferably, 1×10 １８ atoms / cm ３ It can be as follows:

[0349] Although the above example illustrates a configuration in which microwave treatment is performed on an oxide semiconductor in an atmosphere containing oxygen, the present invention is not limited to this. For example, an insulating layer located near an oxide semiconductor, specifically a silicon oxide layer, may be subjected to microwave treatment in an atmosphere containing oxygen. By performing microwave treatment on a silicon oxide layer in an atmosphere containing oxygen, hydrogen contained in the silicon oxide layer can be converted to H ２ The hydrogen can be released to the outside as O. By releasing hydrogen from the silicon oxide layer located near the oxide semiconductor, the reliability of a transistor including an oxide semiconductor as a semiconductor layer can be improved. Thus, a highly reliable semiconductor device can be provided.

[0350] Furthermore, the microwave treatment may promote crystallization of the oxide semiconductor. That is, the microwave treatment on the oxide semiconductor or an insulating layer located in the vicinity of the oxide semiconductor can increase the crystallinity of the oxide semiconductor.

[0351] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments.

[0352] Embodiment 3 In this embodiment, a structural example of a display device 200 in which the transistor 10, the shift register 100, the signal output circuit 110, and the like according to one embodiment of the present invention can be used will be described.

[0353] Fig. 34A shows a perspective view of display device 200. Display device 200 has a configuration in which substrate 152 and substrate 148 are bonded together. In Fig. 34A, substrate 152 is indicated by a dashed line.

[0354] Display device 200 has a display unit 235, a connection unit 140, a first drive circuit unit 231, a second drive circuit unit 232, wiring 165, etc. Fig. 34A shows an example in which an IC 178 and an FPC 179 are mounted on display device 200. Therefore, the configuration shown in Fig. 34A can also be said to be a display module having display device 200, an IC (integrated circuit), and an FPC.

[0355] The connection portion 140 is provided on the outside of the display portion 235. The connection portion 140 can be provided along one side or multiple sides of the display portion 235. The number of connection portions 140 may be single or multiple. Fig. 34A shows an example in which the connection portion 140 is provided so as to surround the four sides of the display portion. The connection portion 140 electrically connects the common electrode of the light-emitting device and the conductive layer, and can supply a potential to the common electrode.

[0356] The wiring 165 has a function of supplying signals and power to the display unit 235, the first drive circuit unit 231, and the second drive circuit unit 232. The signals and power are input to the wiring 165 from the outside via the FPC 179 or are input to the wiring 165 from the IC 178.

[0357] 34A shows an example in which an IC 178 is provided on a substrate 148 by a chip-on-glass (COG) method, a chip-on-film (COF) method, or the like. The IC 178 may include, for example, a scanning line driver circuit or a signal line driver circuit. Note that the display device 200 and the display module may not include an IC. Alternatively, the IC may be mounted on an FPC by a COF method or the like.

[0358] The display unit 235 has a plurality of pixels 230 arranged in a matrix of m rows (m is an integer of 1 or more) and n columns (n ​​is an integer of 1 or more). The plurality of pixels 230 are further classified into, for example, pixels 230a, 230b, and 230c. The pixels 230a, 230b, and 230c each have the function of emitting light of a different color. For example, the pixel 230a may have the function of emitting red (R) light, the pixel 230b may have the function of emitting green (G) light, and the pixel 230c may have the function of emitting blue (B) light. Alternatively, for example, the pixel 230a may have the function of emitting yellow (Y) light, the pixel 230b may have the function of emitting cyan (C) light, and the pixel 230c may have the function of emitting magenta (M) light.

[0359] A full-color display can be achieved by configuring one pixel 240 with one pixel 230a, one pixel 230b, and one pixel 230c. Therefore, the pixel 230 functions as a sub-pixel. The display device 200 shown in FIG. 34A illustrates an example in which the pixels 230 functioning as sub-pixels are arranged in a stripe array. The number of sub-pixels constituting one pixel 240 is not limited to three, and may be four or more. For example, the pixel 240 may have four sub-pixels that emit R, G, B, and white (W) light. Alternatively, the pixel 240 may have four sub-pixels that emit R, G, B, and Y light.

[0360] FIG. 34B is a block diagram illustrating the display device 200. The display device 200 has a display unit 235, a first drive circuit unit 231, and a second drive circuit unit 232. In FIG. 34B, the pixel 230 in the first row and nth column is indicated as pixel 230[1, n], the pixel 230 in the mth row and first column is indicated as pixel 230[m, 1], and the pixel 230 in the mth row and nth column is indicated as pixel 230[m, n]. In addition, any pixel 230 included in the display unit 235 may be indicated as pixel 230[r, s]. r is an integer greater than or equal to 1 and less than or equal to m, and s is an integer greater than or equal to 1 and less than or equal to n.

[0361] The circuit included in the first drive circuit unit 231 functions as, for example, a scanning line drive circuit. The circuit included in the second drive circuit unit 232 functions as, for example, a signal line drive circuit. Note that some kind of circuit may be provided at a position facing the first drive circuit unit 231 across the display unit 235. Note that some kind of circuit may be provided at a position facing the second drive circuit unit 232 across the display unit 235. Note that the circuits included in the first drive circuit unit 231 and the second drive circuit unit 232 are collectively referred to as a peripheral drive circuit 233.

[0362] The first drive circuit unit 231, which functions as a scanning line drive circuit, has a function of selecting the pixels 230 row by row. The first drive circuit unit 231 sequentially selects the pixels 230 arranged in the first row to the pixels 230 arranged in the mth row, and writes image signals supplied from the second drive circuit unit 232 to the selected pixels 230, thereby rewriting the image displayed on the display unit 235.

[0363] The period from when the first drive circuit unit 231 selects the pixels 230 in the first row to when it selects the pixels 230 in the mth row is called a "frame period." Therefore, a frame period is the period required to rewrite an image displayed on the display unit 235 once. The number of times an image is rewritten per second is called a "frame frequency." The frame frequency is equivalent to the reciprocal of the frame period. The "frame frequency" may also be called a "drive frequency."

[0364] A high frame frequency is preferable when displaying moving images on the display device 200. Specifically, the frame frequency should be 60 Hz or higher, preferably 120 Hz or higher, and more preferably 240 Hz or higher. On the other hand, as the frame frequency increases, the power consumption of the display device 200 increases.

[0365] The peripheral drive circuit 233 can be implemented using various circuits such as a shift register circuit, a level shifter circuit, an inverter circuit, a latch circuit, an analog switch circuit, a multiplexer circuit, a demultiplexer circuit, and a logic circuit.

[0366] The peripheral driver circuit 233 can include the transistor 10 according to one embodiment of the present invention or the like. The shift register circuit can include the shift register 100, the signal output circuit 110, or the like according to one embodiment of the present invention. Note that the transistors included in the peripheral driver circuit and the transistors included in the pixel 230 may be formed in the same process. By using the transistor 10 according to one embodiment of the present invention or the like for the peripheral driver circuit 233, the area occupied by the peripheral driver circuit 233 can be reduced.

[0367] The display device 200 also has m wires 236 that are arranged approximately in parallel and whose potential is controlled by a circuit included in the first drive circuit unit 231, and n wires 237 that are arranged approximately in parallel and whose potential is controlled by a circuit included in the second drive circuit unit 232.

[0368] 34B shows an example in which the wiring 236 and the wiring 237 are connected to the pixel 230. However, the wiring 236 and the wiring 237 are just an example, and the wirings connected to the pixel 230 are not limited to the wiring 236 and the wiring 237.

[0369] <Display Element> The display device 200 can be of various forms or can have various display elements. Examples of display elements include EL (electroluminescence) elements (organic EL elements, inorganic EL elements, or EL elements including organic and inorganic materials), LEDs (white LEDs, red LEDs, green LEDs, blue LEDs, etc.), transistors (transistors that emit light in response to current), electron-emitting elements, liquid crystal elements, electronic ink, electrophoretic elements, grating light valves (GLVs), display elements using MEMS (microelectromechanical systems), digital micromirror devices (DMDs), digital microshutters (DMSs), MIRASOL (registered trademark), IMOD (interferometric modulation) elements, shutter-type MEMS display elements, optical interference-type MEMS display elements, electrowetting elements, piezoelectric ceramic displays, and display elements using carbon nanotubes. Quantum dots may also be used as display elements.

[0370] An example of a display device using an EL element is an EL display. An example of a display device using an electron-emitting element is a field emission display (FED) or an SED-type flat panel display (SED: Surface-conduction Electron-emitter Display). An example of a display device using quantum dots is a quantum dot display. An example of a display device using a liquid crystal element is a liquid crystal display (transmissive liquid crystal display, semi-transmissive liquid crystal display, reflective liquid crystal display, direct-view liquid crystal display, projection liquid crystal display). An example of a display device using electronic ink, electronic liquid powder (registered trademark), or electrophoretic elements is electronic paper. The display device may be a plasma display panel (PDP).

[0371] To realize a transflective or reflective LCD, some or all of the pixel electrodes may be made to function as reflective electrodes. For example, some or all of the pixel electrodes may be made of aluminum, silver, or the like. In this case, a memory circuit such as an SRAM may be provided below the reflective electrodes. This further reduces power consumption.

[0372] When an LED is used, graphene or graphite may be disposed under the electrode or nitride semiconductor of the LED. A multilayer film may be formed by stacking multiple layers of graphene or graphite. By providing graphene or graphite in this manner, a nitride semiconductor, such as an n-type GaN semiconductor layer having crystals, can be easily formed thereon. Furthermore, an LED can be constructed by providing a p-type GaN semiconductor layer having crystals thereon. An AlN layer may be provided between the graphene or graphite and the n-type GaN semiconductor layer having crystals. The GaN semiconductor layer of the LED may be formed by MOCVD. However, by providing graphene, the GaN semiconductor layer of the LED can also be formed by sputtering.

[0373] 35A to 35D, 36A to 36D, 37A, 37B, 38A, and 38B show configuration examples of a pixel 230. The pixel 230 has a pixel circuit 51 (pixel circuit 51A, pixel circuit 51B, pixel circuit 51C, pixel circuit 51D, pixel circuit 51E, pixel circuit 51F, pixel circuit 51G, pixel circuit 51H, pixel circuit 51I, pixel circuit 51J, pixel circuit 51K, or pixel circuit 51L) and a light-emitting element 61.

[0374] The light-emitting element (also referred to as a light-emitting device) described in this embodiment and the like refers to a self-luminous display element such as an organic EL element (also referred to as an OLED (organic light-emitting diode)). Note that the light-emitting element electrically connected to the pixel circuit can be a self-luminous light-emitting element such as an LED (light-emitting diode), a micro LED, a QLED (quantum-dot light-emitting diode), or a semiconductor laser.

[0375] A pixel circuit 51A shown in FIG. 35A is a 2Tr1C type pixel circuit having a transistor 52A, a transistor 52B, and a capacitor 53.

[0376] One of the source and drain of the transistor 52A is electrically connected to the wiring SL, and the gate of the transistor 52A is electrically connected to the wiring GL. One of the source and drain of the transistor 52A is electrically connected to the gate of the transistor 52B and one terminal of the capacitor 53. One of the source and drain of the transistor 52B is electrically connected to the wiring ANO. The other of the source and drain of the transistor 52B is electrically connected to the other terminal of the capacitor 53 and the anode of the light-emitting element 61. The cathode of the light-emitting element 61 is electrically connected to the wiring VCOM. A region where the other of the source and drain of the transistor 52A, the gate of the transistor 52B, and one terminal of the capacitor 53 are electrically connected functions as a node ND.

[0377] The wiring GL corresponds to the wiring 236, and the wiring SL corresponds to the wiring 237. The wiring VCOM is a wiring that applies a potential for supplying a current to the light-emitting element 61. The transistor 52A has a function of controlling the conduction or non-conduction state between the wiring SL and the gate of the transistor 52B based on the potential of the wiring GL. For example, VDD is supplied to the wiring ANO, and VSS is supplied to the wiring VCOM.

[0378] By turning on the transistor 52A, an image signal is supplied from the wiring SL to the node ND. Then, by turning off the transistor 52A, the image signal is held in the node ND. In order to reliably hold the image signal supplied to the node ND, it is preferable to use a transistor with low off-state current as the transistor 52A. For example, it is preferable to use an OS transistor as the transistor 52A.

[0379] By using an OS transistor for the transistor 52A, image display on the display portion 235 can be maintained even when the frame frequency is significantly reduced (for example, 1 Hz or less). Furthermore, for example, when displaying a still image that does not need to be rewritten every frame, the image display can be continued even if the operation of the peripheral driver circuit 233 is stopped. Such a driving method of stopping the operation of the peripheral driver circuit 233 while displaying a still image is also called "idling stop driving." By performing idling stop driving, the power consumption of the display device can be reduced.

[0380] The transistor 52B has a function of controlling the amount of current flowing through the light-emitting element 61. The capacitor 53 has a function of holding the gate potential of the transistor 52B. The intensity of light emitted by the light-emitting element 61 is controlled in response to an image signal supplied to the gate (node ​​ND) of the transistor 52B.

[0381] 35B is a 3Tr1C type pixel circuit having transistors 52A, 52B, and 52C, and a capacitor 53. The pixel circuit 51B shown in Fig. 35B has a configuration in which a transistor 52C is added to the pixel circuit 51A shown in Fig. 35A.

[0382] The source or the drain of the transistor 52C is electrically connected to the other of the source or the drain of the transistor 52B. The gate of the transistor 52C is electrically connected to a wiring GL. The other of the source or the drain of the transistor 52C is electrically connected to a wiring V0. For example, a reference potential is supplied to the wiring V0.

[0383] The transistor 52C has a function of controlling conduction or non-conduction between the other of the source and the drain of the transistor 52B and the wiring V0 based on the potential of the wiring GL. The wiring V0 is a wiring for applying a reference potential. When an n-channel transistor is used as the transistor 52B, the reference potential of the wiring V0 applied via the transistor 52C can suppress variations in the gate-source potential of the transistor 52B.

[0384] Furthermore, the wiring V0 can be used to obtain a current value that can be used to set pixel parameters. More specifically, the wiring V0 can function as a monitor line for outputting the current flowing through the transistor 52B or the current flowing through the light-emitting element 61 to the outside. The current output to the wiring V0 can be converted into a voltage by a source follower circuit or the like and output to the outside. Alternatively, it can be converted into a digital signal by an A-D converter or the like and output to the outside.

[0385] A pixel circuit 51C shown in FIG. 35C is an example in which transistors having back gates electrically connected to the gates are used as the transistors 52A and 52B of the pixel circuit 51A. A pixel circuit 51D shown in FIG. 35D is an example in which the same transistors are used in the pixel circuit 51B. This allows the current that can flow through the transistors to be increased. Note that, although all transistors here have their gates and back gates electrically connected, this is not a limitation. Alternatively, a transistor having a gate and a back gate, which are electrically connected to different wirings, may be used. For example, reliability can be improved by using a transistor in which one of the gate or the back gate is electrically connected to the source.

[0386] Pixel circuit 51E shown in Fig. 36A has a configuration in which transistor 52D is added to pixel circuit 51B shown in Fig. 35B. Pixel circuit 51E shown in Fig. 36A is a 4Tr1C type pixel circuit having transistors 52A, 52B, 52C, 52D, and a capacitor 53.

[0387] One of the source and the drain of the transistor 52D is electrically connected to the node ND, and the other is electrically connected to the wiring V0.

[0388] The pixel circuit 51E is electrically connected to wirings GL1, GL2, and GL3. The wiring GL1 is electrically connected to the gate of the transistor 52A, the wiring GL2 is electrically connected to the gate of the transistor 52C, and the wiring GL3 is electrically connected to the gate of the transistor 52D. Note that in this embodiment and the like, the wirings GL1, GL2, and GL3 may be collectively referred to as wirings GL. Therefore, the number of wirings GL is not limited to one, and there may be multiple wirings GL.

[0389] By simultaneously turning on the transistors 52C and 52D, the source and gate of the transistor 52B have the same potential, and the transistor 52B can be turned off. This makes it possible to forcibly cut off the current flowing through the light-emitting element 61. Such a pixel circuit is suitable for use in a display method in which display periods and off periods are alternately provided.

[0390] The pixel circuit 51F shown in Fig. 36B is an example in which a capacitor 53A is added to the pixel circuit 51E. The capacitor 53A functions as a storage capacitor. The pixel circuit 51E shown in Fig. 36A is a 4Tr1C type pixel circuit. The pixel circuit 51F shown in Fig. 36B is a 4Tr2C type pixel circuit.

[0391] 36C and 36D are examples in which a transistor having a back gate is applied to the pixel circuit 51E or the pixel circuit 51F, respectively. Transistors 52A, 52C, and 52D are transistors in which the gate and the back gate are electrically connected, and transistor 52B is a transistor in which one of the gate or the back gate is electrically connected to the source.

[0392] The pixel circuit 51I shown in FIG. 37A is a 6Tr1C type pixel circuit having a transistor 52A, a transistor 52B, a transistor 52C, a transistor 52D, a transistor 52E, a transistor 52F, and a capacitor 53.

[0393] One of the source and drain of the transistor 52A is electrically connected to the wiring SL, and the gate of the transistor 52A is electrically connected to the wiring GL1. One of the source and drain of the transistor 52D is electrically connected to the wiring ANO, and the gate of the transistor 52D is electrically connected to the wiring GL2. The other of the source and drain of the transistor 52D is electrically connected to one of the source and drain of the transistor 52B. The other of the source and drain of the transistor 52B is electrically connected to the other of the source and drain of the transistor 52A and one of the source and drain of the transistor 52F. The gate of the transistor 52F is electrically connected to the wiring GL3.

[0394] One of the source and the drain of the transistor 52E is electrically connected to the other of the source and the drain of the transistor 52D and one of the source and the drain of the transistor 52B. The other of the source and the drain of the transistor 52E is electrically connected to the gate of the transistor 52B and one terminal of the capacitor 53. The other terminal of the capacitor 53 is electrically connected to the other of the source and the drain of the transistor 52F, the anode of the light-emitting element 61, and one of the source and the drain of the transistor 52C.

[0395] The gate of the transistor 52E and the gate of the transistor 52C are electrically connected to a wiring GL4. The other of the source and the drain of the transistor 52C is electrically connected to a wiring V0. A region where the other of the source and the drain of the transistor 52E, the gate of the transistor 52B, and one terminal of the capacitor 53 are electrically connected functions as a node ND. In the pixel circuit 51I, it is preferable to use an OS transistor, particularly for the transistor 52E.

[0396] 37B , a transistor having a back gate may be used as a transistor included in a pixel circuit 51J. The transistors 52A, 52C, 52D, 52E, and 52F are transistors whose gates and back gates are electrically connected to each other, and the transistor 52B is a transistor whose back gate is electrically connected to the other of the source and the drain.

[0397] The transistor 10 according to one embodiment of the present invention can be used as the transistor 52A, the transistor 52C, the transistor 52D, the transistor 52E, and the transistor 52F.

[0398] A pixel 230 shown in FIG. 38A includes a pixel circuit 51K and a liquid crystal element 62. The pixel circuit 51K also includes a transistor 52A and a capacitor 53. In FIG. 38A , one of the source and the drain of the transistor 52A is electrically connected to a wiring SL, and the gate of the transistor 52A is electrically connected to a wiring GL. The other of the source and the drain of the transistor 52A is electrically connected to one terminal of the capacitor 53 and the liquid crystal element 62. The other terminal of the capacitor 53 is electrically connected to a wiring VCOM. A region electrically connecting the other of the source and the drain of the transistor 52A, the one terminal of the capacitor 53, and the liquid crystal element 62 functions as a node ND. The orientation state of the liquid crystal element 62 is set by data written to the node ND.

[0399] The display device including the liquid crystal element 62 can be driven in, for example, a twisted nematic (TN) mode, a super twisted nematic (STN) mode, a VA mode, an axially symmetric aligned micro-cell (ASM) mode, an optically compensated birefringence (OCB) mode, a ferroelectric liquid crystal (FLC) mode, an antiferroelectric liquid crystal (AFLC) mode, an MVA mode, a patterned vertical alignment (PVA) mode, an IPS mode, an FFS mode, or a transverse alignment (TBA) mode. In addition to the above-described driving methods, other driving methods for the display device include an ECB (Electrically Controlled Birefringence) mode, a PDLC (Polymer Dispersed Liquid Crystal) mode, a PNLC (Polymer Network Liquid Crystal) mode, and a guest-host mode. However, the present invention is not limited to these, and various liquid crystal elements and driving methods thereof can be used.

[0400] When a liquid crystal element is used as a display element, it is possible to use thermotropic liquid crystal, low molecular weight liquid crystal, polymer liquid crystal, polymer dispersed liquid crystal, ferroelectric liquid crystal, antiferroelectric liquid crystal, etc. These liquid crystal materials exhibit a cholesteric phase, a smectic phase, a cubic phase, a chiral nematic phase, an isotropic phase, etc. depending on the conditions.

[0401] Alternatively, liquid crystals exhibiting a blue phase without an alignment layer may be used. The blue phase is a type of liquid crystal phase that appears immediately before the transition from the cholesteric phase to the isotropic phase when cholesteric liquid crystals are heated. Because the blue phase appears only within a narrow temperature range, a liquid crystal composition containing 5% by weight or more of a chiral dopant is used in the liquid crystal layer to improve the temperature range. Liquid crystal compositions containing liquid crystals exhibiting a blue phase and a chiral dopant have a short response time of 1 msec or less, are optically isotropic, do not require alignment treatment, and have low viewing angle dependence. Furthermore, since no alignment layer is required, rubbing treatment is also unnecessary, which prevents electrostatic breakdown caused by rubbing treatment and reduces defects and damage to liquid crystal display devices during the manufacturing process. This allows for improved productivity of liquid crystal display devices.

[0402] Alternatively, a method known as multi-domaining or multi-domain design can be used, in which a pixel is divided into several regions (sub-pixels) and the molecules are tilted in different directions in each region.

[0403] The specific resistance of the liquid crystal material is 1×10 ９ Ω cm or more, preferably 1×10 １１ Ω cm or more, and more preferably 1×10 １２ The specific resistance value in this specification is a value measured at 20°C.

[0404] 38B, the pixel 230 may include a pixel circuit 51L instead of the pixel circuit 51K. The pixel circuit 51L includes a transistor 52A having a back gate. The transistor 52A shown in FIG. 38B has a gate electrically connected to the back gate. Therefore, the gate and back gate are always at the same potential.

[0405] By using the transistor 10 according to one embodiment of the present invention in a pixel circuit of a display device, the area occupied by the pixel circuit can be reduced. Therefore, the resolution of the display device can be improved. For example, a display device having a resolution of 1000 ppi or more, preferably 2000 ppi or more, more preferably 3000 ppi or more, further preferably 4000 ppi or more, further preferably 5000 ppi or more, and further preferably 6000 ppi or more, and 10000 ppi or less, 9000 ppi or less, or 8000 ppi or less can be realized.

[0406] Furthermore, by reducing the area occupied by the pixel circuit, it is possible to increase the number of pixels (resolution) of the display device, and to realize display devices with extremely high resolutions such as HD (1280 x 720 pixels), FHD (1920 x 1080 pixels), WQHD (2560 x 1440 pixels), WQXGA (2560 x 1600 pixels), 4K2K (3840 x 2160 pixels), or 8K4K (7680 x 4320 pixels).

[0407] Therefore, by using the transistor 10 according to one embodiment of the present invention in a pixel circuit of a display device, the display quality of the display device can be improved. Furthermore, in a bottom-emission display device using an EL element, the aperture ratio of the pixel can be increased. A pixel with a high aperture ratio can emit light with the same luminance as a pixel with a low aperture ratio, but with a lower current density than a pixel with a low aperture ratio. Therefore, the reliability of the display device can be improved.

[0408] [Configuration Example of Peripheral Circuits] Figure 39A shows a configuration example of the second drive circuit unit 232. The second drive circuit unit 232 has a shift register 512, a latch circuit 513, and a buffer 514. Also, as the wiring 237, wiring 237[1], wiring 237[2], wiring 237[3], and wiring 237[n] are shown. Also, Figure 39B shows a configuration example of the first drive circuit unit 231. The first drive circuit unit 231 has a shift register 522 and a buffer 523. Also, as the wiring 236, wiring 236[1], wiring 236[2], wiring 236[3], and wiring 236[n] are shown.

[0409] A start pulse SP, a signal CLK, and the like are input to the shift register 512 and the shift register 522. As the shift register 512 and the shift register 522, the shift register 100 disclosed in the above embodiment can be used.

[0410] 40A to 40G and 41A to 41K, pixel layouts different from those in FIG. 34A will be mainly described. There are no particular limitations on the arrangement of sub-pixels, and various pixel layouts can be applied. Examples of sub-pixel arrangements include a stripe arrangement, an S-stripe arrangement, a matrix arrangement, a delta arrangement, a Bayer arrangement, and a pentile arrangement.

[0411] The planar shapes of the sub-pixels shown in FIG. 34A, FIGS. 40A to 40G, and FIGS. 41A to 41K correspond to the planar shapes of the light-emitting regions.

[0412] The planar shape of the subpixel may be, for example, a triangle, a quadrangle (including a rectangle and a square), a polygon such as a pentagon, a polygon with rounded corners, an ellipse, or a circle.

[0413] The pixel circuit 51 included in the sub-pixel (pixel 230) may be disposed so as to overlap the light-emitting region, or may be disposed outside the light-emitting region.

[0414] An S-stripe arrangement is applied to the pixel 240 shown in Fig. 40A. The pixel 240 shown in Fig. 40A is made up of three types of sub-pixels: a pixel 230a, a pixel 230b, and a pixel 230c.

[0415] The pixel 240 shown in Figure 40B includes a pixel 230a having a generally trapezoidal planar shape with rounded corners, a pixel 230b having a generally triangular planar shape with rounded corners, and a pixel 230c having a generally rectangular or hexagonal planar shape with rounded corners. Furthermore, pixel 230a has a larger light-emitting area than pixel 230b. In this manner, the shape and size of each subpixel can be determined independently. For example, the more reliable the light-emitting device, the smaller the size of the subpixel can be.

[0416] The Pentile arrangement is applied to pixels 240A and 240B shown in Fig. 40C. Fig. 40C shows an example in which pixel 240A having pixels 230a and 230b and pixel 240B having pixels 230b and 230c are arranged alternately.

[0417] Pixels 240A and 240B shown in Figures 40D to 40F are arranged in a delta configuration. Pixel 240A has two subpixels (pixels 230a and 230b) in the top row (first row) and one subpixel (pixel 230c) in the bottom row (second row). Pixel 240B has one subpixel (pixel 230c) in the top row (first row) and two subpixels (pixels 230a and 230b) in the bottom row (second row).

[0418] Figure 40D is an example in which each sub-pixel has a roughly rectangular planar shape with rounded corners, Figure 40E is an example in which each sub-pixel has a circular planar shape, and Figure 40F is an example in which each sub-pixel has a roughly hexagonal planar shape with rounded corners.

[0419] In Figure 40F, each subpixel is arranged inside a closely packed hexagonal region. When focusing on one subpixel, it is surrounded by six other subpixels. Furthermore, subpixels that emit light of the same color are arranged so that they are not adjacent to each other. For example, when focusing on pixel 230a, three pixels 230b and three pixels 230c are arranged alternately to surround pixel 230a.

[0420] 40G shows an example in which subpixels of each color are arranged in a zigzag pattern. Specifically, the positions of the top edges of two subpixels aligned in the column direction (for example, pixels 230a and 230b, or pixels 230b and 230c) are misaligned in a plan view.

[0421] 40A to 40G, it is preferable that pixel 230a be a subpixel R that emits red light, pixel 230b be a subpixel G that emits green light, and pixel 230c be a subpixel B that emits blue light. Note that the configuration of the subpixels is not limited to this, and the colors that the subpixels emit and their order of arrangement can be determined appropriately. For example, pixel 230b may be a subpixel R that emits red light, and pixel 230a may be a subpixel G that emits green light.

[0422] In photolithography, the finer the pattern to be processed, the more significant the effect of light diffraction becomes. This reduces the fidelity of the photomask pattern when it is transferred by exposure, making it difficult to process the resist mask into the desired shape. Therefore, even if the photomask pattern is rectangular, it is likely to have rounded corners. As a result, the planar shape of the subpixel may become a polygon with rounded corners, an ellipse, a circle, or the like.

[0423] Furthermore, when processing the EL layer into islands using a resist mask, the resist film formed on the EL layer must be cured at a temperature lower than the heat resistance temperature of the EL layer. Therefore, depending on the heat resistance temperature of the EL layer material and the curing temperature of the resist material, the resist film may not be cured sufficiently. An insufficiently cured resist film may take a shape that deviates from the desired shape during processing. As a result, the planar shape of the EL layer may become a polygon with rounded corners, an ellipse, a circle, or the like. For example, when attempting to form a resist mask with a square planar shape, a resist mask with a circular planar shape may be formed, resulting in a circular planar shape of the EL layer.

[0424] In order to make the planar shape of the EL layer into a desired shape, a technique for correcting the mask pattern in advance (OPC (Optical Proximity Correction) technique) may be used so that the design pattern and the transfer pattern coincide with each other. Specifically, the OPC technique adds a correction pattern to the corners of figures on the mask pattern.

[0425] As shown in Figures 41A to 41I, a pixel can be configured to have four types of sub-pixels.

[0426] The pixel 240 shown in FIGS. 41A to 41C is configured in a stripe arrangement.

[0427] Figure 41A is an example in which each subpixel has a rectangular planar shape, Figure 41B is an example in which each subpixel has a planar shape that combines two semicircles and a rectangle, and Figure 41C is an example in which each subpixel has an elliptical planar shape.

[0428] The pixels 240 shown in FIGS. 41D to 41F are arranged in a matrix.

[0429] Figure 41D is an example in which each sub-pixel has a square planar shape, Figure 41E is an example in which each sub-pixel has an approximately square planar shape with rounded corners, and Figure 41F is an example in which each sub-pixel has a circular planar shape.

[0430] 41G and 41H show an example in which one pixel 240 is made up of sub-pixels arranged in two rows and three columns.

[0431] 41G has three subpixels (pixel 230a, pixel 230b, and pixel 230c) in the top row (first row) and one subpixel (pixel 230d) in the bottom row (second row) of the pixel 240. In other words, the pixel 240 has pixel 230a in the left column (first column), pixel 230b in the center column (second column), pixel 230c in the right column (third column), and further has pixel 230d across these three columns.

[0432] The pixel 240 shown in FIG. 41H has three subpixels (pixel 230a, pixel 230b, and pixel 230c) in the top row (first row) and three subpixels 230d in the bottom row (second row). In other words, pixel 240 has pixel 230a and pixel 230d in the left column (first column) of pixel 240, pixel 230b and pixel 230d in the center column (second column), and pixel 230c and pixel 230d in the right column (third column). As shown in FIG. 41H, by aligning the subpixels in the top row and bottom row, it is possible to efficiently remove dust and other particles that may occur during the manufacturing process. Therefore, a display device with high display quality can be provided.

[0433] FIG. 41I shows an example in which one pixel 240 is made up of sub-pixels arranged in three rows and two columns.

[0434] 41I has pixel 230a in the top row (first row), pixel 230b in the middle row (second row), pixel 230c across the first and second rows, and one subpixel (pixel 230d) in the bottom row (third row). In other words, pixel 240 has pixel 230a and pixel 230b in the left column (first column) of pixel 240, pixel 230c in the right column (second column), and pixel 230d across these two columns.

[0435] The pixel 240 shown in FIGS. 41A to 41I is composed of four sub-pixels: a pixel 230a, a pixel 230b, a pixel 230c, and a pixel 230d.

[0436] The pixels 230a, 230b, 230c, and 230d may each have a light-emitting device that emits a different light color, such as sub-pixels of four colors R, G, B, and white (W), sub-pixels of four colors R, G, B, and Y, or sub-pixels of R, G, B, and infrared (IR).

[0437] In each pixel 240 shown in Figures 41A to 41I, for example, pixel 230a may be a subpixel R that emits red light, pixel 230b may be a subpixel G that emits green light, pixel 230c may be a subpixel B that emits blue light, and pixel 230d may be a subpixel W that emits white light, a subpixel that emits yellow light, or a subpixel that emits near-infrared light. With such a configuration, the pixel 240 shown in Figures 41G and 41H has a stripe layout of R, G, and B, which can improve display quality. Furthermore, the pixel 240 shown in Figure 41I has a so-called S-stripe layout of R, G, and B, which can improve display quality.

[0438] The pixel 240 may have a sub-pixel having a light receiving element (also called a light receiving device).

[0439] In each pixel 240 shown in FIGS. 41A to 41I, any one of the pixels 230a to 230d may be a sub-pixel having a light-receiving device.

[0440] 41A to 41I, for example, pixel 230a may be a subpixel R that emits red light, pixel 230b may be a subpixel G that emits green light, pixel 230c may be a subpixel B that emits blue light, and pixel 230d may be a subpixel S that has a light-receiving device. In such a configuration, the pixel 240 shown in FIGS. 41G and 41H has a stripe layout of R, G, and B, which can improve display quality. Furthermore, the pixel 240 shown in FIG. 41I has a so-called S-stripe layout of R, G, and B, which can improve display quality.

[0441] The wavelength of light detected by the subpixel S having the light receiving device is not particularly limited. The subpixel S can be configured to detect either or both of visible light and infrared light.

[0442] As shown in FIGS. 41J and 41K, one pixel 240 may have five types of sub-pixels.

[0443] FIG. 41J shows an example in which one pixel 240 is made up of sub-pixels arranged in two rows and three columns.

[0444] 41J has three subpixels (pixel 230a, pixel 230b, and pixel 230c) in the top row (first row) of the pixel 240, and two subpixels (pixel 230d and pixel 230e) in the bottom row (second row). In other words, the pixel 240 has pixel 230a and pixel 230d in the left column (first column) of the pixel 240, pixel 230b in the center column (second column), pixel 230c in the right column (third column), and further has pixel 230e spanning from the second column to the third column.

[0445] FIG. 41K shows an example in which one pixel 240 is made up of sub-pixels arranged in three rows and two columns.

[0446] 41K has pixel 230a in the top row (first row), pixel 230b in the middle row (second row), pixel 230c across the first and second rows, and two subpixels (pixel 230d and pixel 230e) in the bottom row (third row). In other words, pixel 240 has pixel 230a, pixel 230b, and pixel 230d in the left column (first column), and pixel 230c and pixel 230e in the right column (second column).

[0447] 41J and 41K, it is preferable that pixel 230a be a subpixel R that emits red light, pixel 230b be a subpixel G that emits green light, and pixel 230c be a subpixel B that emits blue light. With this configuration, the pixel 240 shown in FIG. 41J has a stripe-shaped layout of subpixels, which can improve display quality. Furthermore, the pixel 240 shown in FIG. 41K has a so-called S-stripe-shaped layout of subpixels, which can improve display quality.

[0448] 41J and 41K, for example, a subpixel S having a light receiving device may be applied to at least one of pixel 230d and pixel 230e. When a light receiving device is used in both pixel 230d and pixel 230e, the configurations of the light receiving devices may be different from each other. For example, at least a part of the wavelength range of light detected may be different from each other. Specifically, one of pixel 230d and pixel 230e may have a light receiving device that mainly detects visible light, and the other may have a light receiving device that mainly detects infrared light.

[0449] 41J and 41K, for example, one of pixel 230d and pixel 230e may be a subpixel S having a light-receiving device, and the other may be a subpixel having a light-emitting device that can be used as a light source. For example, one of pixel 230d and pixel 230e may be a subpixel IR (not shown) that emits infrared light, and the other may be a subpixel S (not shown) having a light-receiving device that detects infrared light.

[0450] In a pixel having sub-pixels R, G, B, IR, and S, an image is displayed using the sub-pixels R, G, and B, and the sub-pixel IR is used as a light source, allowing the sub-pixel S to detect reflected infrared light emitted by the sub-pixel IR.

[0451] As described above, in the display device of one embodiment of the present invention, various layouts of subpixels (pixels 230) can be applied to the pixel 240. Furthermore, a structure including both a light-emitting device and a light-receiving device may be applied to the pixel 240. In this case, various layouts can also be applied.

[0452] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments.

[0453] Embodiment 4 In this embodiment, a light-emitting device that can be used as the light-emitting element 61 will be described.

[0454] 42A, the light-emitting device has an EL layer 763 between a pair of electrodes (a lower electrode 761 and an upper electrode 762). The EL layer 763 can be composed of multiple layers, such as a layer 780, a light-emitting layer 771, and a layer 790.

[0455] The light-emitting layer 771 contains at least a light-emitting substance (also referred to as a light-emitting material).

[0456] When the lower electrode 761 is an anode and the upper electrode 762 is a cathode, the layer 780 includes one or more of a layer containing a substance with high hole-injecting properties (hole-injecting layer), a layer containing a substance with high hole-transporting properties (hole-transporting layer), and a layer containing a substance with high electron-blocking properties (electron-blocking layer). The layer 790 also includes one or more of a layer containing a substance with high electron-injecting properties (electron-injecting layer), a layer containing a substance with high electron-transporting properties (electron-transporting layer), and a layer containing a substance with high hole-blocking properties (hole-blocking layer). When the lower electrode 761 is a cathode and the upper electrode 762 is an anode, the layers 780 and 790 have the opposite structures to those described above.

[0457] A structure having the layer 780, the light-emitting layer 771, and the layer 790 provided between a pair of electrodes can function as a single light-emitting unit, and the structure of FIG. 42A is referred to as a single structure in this specification.

[0458] Fig. 42B shows a modified example of the EL layer 763 included in the light-emitting device shown in Fig. 42A. Specifically, the light-emitting device shown in Fig. 42B has a layer 781 on a lower electrode 761, a layer 782 on the layer 781, a light-emitting layer 771 on the layer 782, a layer 791 on the light-emitting layer 771, a layer 792 on the layer 791, and an upper electrode 762 on the layer 792.

[0459] When the lower electrode 761 is an anode and the upper electrode 762 is a cathode, for example, the layer 781 can be a hole injection layer, the layer 782 can be a hole transport layer, the layer 791 can be an electron transport layer, and the layer 792 can be an electron injection layer. When the lower electrode 761 is a cathode and the upper electrode 762 is an anode, the layer 781 can be an electron injection layer, the layer 782 can be an electron transport layer, the layer 791 can be a hole transport layer, and the layer 792 can be a hole injection layer. Such a layer structure allows carriers to be efficiently injected into the light-emitting layer 771, and the efficiency of carrier recombination in the light-emitting layer 771 can be increased.

[0460] As shown in Figures 42C and 42D, a variation of the single structure is a configuration in which multiple light-emitting layers (light-emitting layers 771, 772, and 773) are provided between layer 780 and layer 790. While Figures 42C and 42D show an example having three light-emitting layers, the number of light-emitting layers in a single-structure light-emitting device may be two, four, or more. A single-structure light-emitting device may also have a buffer layer between the two light-emitting layers. For example, a carrier transport layer (a hole transport layer and an electron transport layer) may be used as the buffer layer.

[0461] As shown in Figures 42E and 42F, a configuration in which multiple light-emitting units (light-emitting unit 763a and light-emitting unit 763b) are connected in series via a charge generation layer 785 (also referred to as an intermediate layer) is referred to as a tandem structure in this specification. Note that the tandem structure may also be referred to as a stack structure. By using a tandem structure, a light-emitting device capable of emitting high-luminance light can be obtained. Furthermore, compared to a single structure, the tandem structure can reduce the current required to obtain the same luminance, thereby improving reliability.

[0462] 42D and 42F are examples of display devices having a layer 764 overlapping with the light-emitting device. Fig. 42D is an example in which the layer 764 overlaps with the light-emitting device shown in Fig. 42C, and Fig. 42F is an example in which the layer 764 overlaps with the light-emitting device shown in Fig. 42E. In Fig. 42D and 42F, a conductive film that transmits visible light is used for the upper electrode 762 in order to extract light to the upper electrode 762 side.

[0463] The layer 764 can be a color conversion layer and / or a color filter (coloring layer).

[0464] In Figures 42C and 42D, the light-emitting layers 771, 772, and 773 may be made of light-emitting materials that emit light of the same color, or even the same light-emitting material. For example, the light-emitting layers 771, 772, and 773 may be made of a light-emitting material that emits blue light. In the subpixels that emit blue light, blue light emitted by the light-emitting device can be extracted. Furthermore, in the subpixels that emit red light and the subpixels that emit green light, a color conversion layer can be provided as the layer 764 shown in Figure 42D to convert the blue light emitted by the light-emitting device into light with a longer wavelength, thereby extracting red or green light. Furthermore, it is preferable that the layer 764 includes both a color conversion layer and a colored layer. A portion of the light emitted by the light-emitting device may be transmitted directly without being converted by the color conversion layer. By extracting the light that has passed through the color conversion layer through the colored layer, light other than the desired color can be absorbed by the colored layer, thereby improving the color purity of the light emitted by the subpixels.

[0465] 42C and 42D , light-emitting layers 771, 772, and 773 may each contain light-emitting materials with different emission colors. When the lights emitted by light-emitting layers 771, 772, and 773 are complementary in color, white light can be obtained. For example, a single-structure light-emitting device preferably has a light-emitting layer containing a light-emitting material that emits blue light and a light-emitting layer containing a light-emitting material that emits visible light with a wavelength longer than blue.

[0466] A color filter may be provided as layer 764 shown in Figure 42D. When white light passes through the color filter, light of a desired color can be obtained.

[0467] For example, when a light-emitting device with a single structure has three light-emitting layers, it preferably has a light-emitting layer containing a light-emitting material that emits red (R) light, a light-emitting layer containing a light-emitting material that emits green (G) light, and a light-emitting layer containing a light-emitting material that emits blue (B) light. The stacking order of the light-emitting layers can be R, G, B from the anode side, or R, B, G from the anode side, etc. In this case, a buffer layer may be provided between R and G or B.

[0468] For example, when a light-emitting device with a single structure has two light-emitting layers, a structure having one light-emitting layer containing a light-emitting substance that emits blue (B) light and another light-emitting layer containing a light-emitting substance that emits yellow (Y) light is preferred. This structure is sometimes referred to as a light-emitting device with a BY single structure.

[0469] A light-emitting device that emits white light preferably contains two or more types of light-emitting materials. To obtain white light emission, light-emitting materials can be selected so that the light emitted from each of the two or more light-emitting materials has a complementary color relationship. For example, by making the emission color of the first light-emitting layer and the emission color of the second light-emitting layer complementary to each other, a light-emitting device that emits white light as a whole can be obtained. The same applies to a light-emitting device having three or more light-emitting layers.

[0470] 42C and 42D, the layer 780 and the layer 790 may each independently have a laminated structure made up of two or more layers, as shown in FIG. 42B.

[0471] 42E and 42F , the light-emitting layers 771 and 772 may be made of light-emitting materials that emit light of the same color, or even the same light-emitting material. For example, in a light-emitting device having subpixels that emit light of each color, the light-emitting layers 771 and 772 may each be made of a light-emitting material that emits blue light. In the subpixel that emits blue light, the blue light emitted by the light-emitting device can be extracted. In the subpixel that emits red light and the subpixel that emits green light, a color conversion layer can be provided as the layer 764 shown in FIG. 42F to convert the blue light emitted by the light-emitting device into light with a longer wavelength, thereby allowing red or green light to be extracted. Furthermore, it is preferable that the layer 764 include both a color conversion layer and a coloring layer.

[0472] When the light-emitting devices having the configurations shown in FIG. 42E or 42F are used for the subpixels emitting light of each color, different light-emitting materials may be used for each subpixel. Specifically, in a light-emitting device included in a subpixel emitting red light, light-emitting materials that emit red light may be used for the light-emitting layers 771 and 772, respectively. Similarly, in a light-emitting device included in a subpixel emitting green light, light-emitting materials that emit green light may be used for the light-emitting layers 771 and 772, respectively. In a light-emitting device included in a subpixel emitting blue light, light-emitting materials that emit blue light may be used for the light-emitting layers 771 and 772, respectively. A display device having such a configuration employs a tandem-structure light-emitting device and can be said to have an SBS (Side By Side) structure. Therefore, it can have the advantages of both the tandem structure and the SBS structure. This allows for a highly reliable light-emitting device capable of emitting high-brightness light.

[0473] 42E and 42F, light-emitting layers 771 and 772 may be made of light-emitting materials that emit light of different colors. When the light emitted by light-emitting layer 771 and the light emitted by light-emitting layer 772 are complementary colors, white light can be obtained. A color filter may be provided as layer 764 shown in FIG. 42F. When white light passes through the color filter, light of a desired color can be obtained.

[0474] 42E and 42F show an example in which the light-emitting unit 763a has one light-emitting layer 771 and the light-emitting unit 763b has one light-emitting layer 772, but this is not limiting. Each of the light-emitting unit 763a and the light-emitting unit 763b may have two or more light-emitting layers.

[0475] 42E and 42F illustrate examples of light-emitting devices having two light-emitting units, but the present invention is not limited to this. The light-emitting device may have three or more light-emitting units. Note that a configuration having two light-emitting units may be referred to as a two-tiered tandem structure, and a configuration having three light-emitting units may be referred to as a three-tiered tandem structure.

[0476] In Figures 42E and 42F, light-emitting unit 763a includes layer 780a, light-emitting layer 771, and layer 790a, and light-emitting unit 763b includes layer 780b, light-emitting layer 772, and layer 790b.

[0477] When the lower electrode 761 is an anode and the upper electrode 762 is a cathode, the layers 780a and 780b each have one or more of a hole injection layer, a hole transport layer, and an electron blocking layer. The layers 790a and 790b each have one or more of an electron injection layer, an electron transport layer, and a hole blocking layer. When the lower electrode 761 is a cathode and the upper electrode 762 is an anode, the layers 780a and 790a have the opposite structures to those described above, and the layers 780b and 790b also have the opposite structures to those described above.

[0478] When the lower electrode 761 is an anode and the upper electrode 762 is a cathode, for example, the layer 780a may have a hole injection layer, a hole transport layer on the hole injection layer, and an electron blocking layer on the hole transport layer. The layer 790a may have an electron transport layer and a hole blocking layer between the light-emitting layer 771 and the electron transport layer. The layer 780b may have a hole transport layer and an electron blocking layer on the hole transport layer. The layer 790b may have an electron transport layer, an electron injection layer on the electron transport layer, and a hole blocking layer between the light-emitting layer 772 and the electron transport layer. When the lower electrode 761 is a cathode and the upper electrode 762 is an anode, for example, the layer 780a may have an electron injection layer, an electron transport layer on the electron injection layer, and an electron blocking layer on the electron transport layer. Layer 790a may have a hole transport layer and may further have an electron blocking layer between light-emitting layer 771 and the hole transport layer. Layer 780b may have an electron transport layer and may further have a hole blocking layer on the electron transport layer. Layer 790b may have a hole transport layer and a hole injection layer on the hole transport layer and may further have an electron blocking layer between light-emitting layer 772 and the hole transport layer.

[0479] When a light-emitting device with a tandem structure is fabricated, two light-emitting units are stacked via a charge generation layer 785. The charge generation layer 785 has at least a charge generation region. The charge generation layer 785 has a function of injecting electrons into one of the two light-emitting units and injecting holes into the other when a voltage is applied between a pair of electrodes.

[0480] An example of a light emitting device with a tandem structure is shown in FIGS. 43A to 43C.

[0481] 43A shows a configuration having three light-emitting units. In FIG. 43A, multiple light-emitting units (light-emitting unit 763a, light-emitting unit 763b, and light-emitting unit 763c) are connected in series via charge generation layers 785. Light-emitting unit 763a includes layer 780a, light-emitting layer 771, and layer 790a. Light-emitting unit 763b includes layer 780b, light-emitting layer 772, and layer 790b. Light-emitting unit 763c includes layer 780c, light-emitting layer 773, and layer 790c. Layer 780c can have a structure applicable to layers 780a and 780b, and layer 790c can have a structure applicable to layers 790a and 790b.

[0482] 43A , it is preferable that the light-emitting layers 771, 772, and 773 contain light-emitting materials that emit light of the same color. Specifically, the light-emitting layers 771, 772, and 773 may each contain a red (R) light-emitting material (a so-called R\R\R three-stage tandem structure), the light-emitting layers 771, 772, and 773 may each contain a green (G) light-emitting material (a so-called G\G\G three-stage tandem structure), or the light-emitting layers 771, 772, and 773 may each contain a blue (B) light-emitting material (a so-called B\B\B three-stage tandem structure). Note that "a\b" means that a light-emitting unit containing a light-emitting material that emits light of b is provided on a light-emitting unit containing a light-emitting material that emits light of a, via a charge-generating layer, and a and b represent colors.

[0483] 43A , light-emitting materials with different emission colors may be used for some or all of light-emitting layer 771, light-emitting layer 772, and light-emitting layer 773. Examples of combinations of emission colors of light-emitting layer 771, light-emitting layer 772, and light-emitting layer 773 include a configuration in which two of them are blue (B) and the remaining one is yellow (Y), and a configuration in which one of them is red (R), the other one is green (G), and the remaining one is blue (B).

[0484] Note that the light-emitting materials that emit light of the same color are not limited to the above configuration. For example, as shown in FIG. 43B , a tandem light-emitting device may be used in which light-emitting units having multiple light-emitting layers are stacked. FIG. 43B shows a configuration in which two light-emitting units (light-emitting unit 763a and light-emitting unit 763b) are connected in series via charge generation layer 785. Furthermore, light-emitting unit 763a includes layer 780a, light-emitting layer 771a, light-emitting layer 771b, light-emitting layer 771c, and layer 790a. Light-emitting unit 763b includes layer 780b, light-emitting layer 772a, light-emitting layer 772b, light-emitting layer 772c, and layer 790b.

[0485] In FIG. 43B , light-emitting materials having complementary colors are selected for the light-emitting layers 771a, 771b, and 771c, and the light-emitting unit 763a is configured to emit white light (W). Light-emitting materials having complementary colors are also selected for the light-emitting layers 772a, 772b, and 772c, and the light-emitting unit 763b is configured to emit white light (W). That is, the configuration shown in FIG. 43B is a two-tiered W / W tandem structure. There are no particular limitations on the stacking order of the light-emitting materials having complementary colors. The implementer can select the optimal stacking order as appropriate. Although not shown, a three-tiered W / W / W tandem structure or a four-tiered or more tandem structure may also be used.

[0486] When a light-emitting device with a tandem structure is used, there are used a two-stage tandem structure of B\Y or Y\B having a light-emitting unit that emits yellow (Y) light and a light-emitting unit that emits blue (B) light, a two-stage tandem structure of R·G\B or B\R·G having a light-emitting unit that emits red (R) and green (G) light and a light-emitting unit that emits blue (B) light, a light-emitting unit that emits yellow (Y) light and a light-emitting unit that emits blue (B) light, and a two-stage tandem structure of R·G\B or B\R·G having a light-emitting unit that emits blue (B) light, a light-emitting unit that emits yellow (Y) light and a light-emitting unit that emits blue (B) light. Examples of such a tandem structure include a B\Y\B three-stage tandem structure having a light-emitting unit that emits blue (B) light, a light-emitting unit that emits yellow-green (YG) light, and a light-emitting unit that emits blue (B) light, in that order, a B\YG\B three-stage tandem structure having a light-emitting unit that emits blue (B) light, a light-emitting unit that emits green (G) light, and a light-emitting unit that emits blue (B) light, in that order, and a B\G\B three-stage tandem structure having a light-emitting unit that emits blue (B) light, a light-emitting unit that emits green (G) light, and a light-emitting unit that emits blue (B) light, in that order. Note that "a·b" means that one light-emitting unit has a light-emitting substance that emits light of a and a light-emitting substance that emits light of b.

[0487] As shown in FIG. 43C, a light-emitting unit having one light-emitting layer and a light-emitting unit having multiple light-emitting layers may be combined.

[0488] 43C , a plurality of light-emitting units (light-emitting unit 763a, light-emitting unit 763b, and light-emitting unit 763c) are connected in series via charge generation layer 785. Light-emitting unit 763a includes layer 780a, light-emitting layer 771, and layer 790a, light-emitting unit 763b includes layer 780b, light-emitting layer 772a, light-emitting layer 772b, light-emitting layer 772c, and layer 790b, and light-emitting unit 763c includes layer 780c, light-emitting layer 773, and layer 790c.

[0489] For example, in the configuration shown in Figure 43C, a three-stage tandem structure of B\R·G·YG\B can be applied, in which light-emitting unit 763a is a light-emitting unit that emits blue (B) light, light-emitting unit 763b is a light-emitting unit that emits red (R), green (G), and yellow-green (YG) light, and light-emitting unit 763c is a light-emitting unit that emits blue (B) light.

[0490] For example, the number of layers of the light-emitting units and the order of colors can be, from the anode side, a two-layer structure of B and Y, a two-layer structure of B and light-emitting unit X, a three-layer structure of B, Y, and B, and the number of layers of the light-emitting layers in light-emitting unit X and the order of colors can be, from the anode side, a two-layer structure of R and Y, a two-layer structure of R and G, a two-layer structure of G and R, a three-layer structure of G, R, and G, or a three-layer structure of R, G, and R. Furthermore, another layer can be provided between the two light-emitting layers.

[0491] Next, materials that can be used in light-emitting devices will be described.

[0492] Of the lower electrode 761 and the upper electrode 762, a conductive film that transmits visible light is used for the electrode from which light is extracted. It is preferable to use a conductive film that reflects visible light for the electrode from which light is not extracted. When the display device has a light-emitting device that emits infrared light, it is preferable to use a conductive film that transmits visible light and infrared light for the electrode from which light is extracted, and a conductive film that reflects visible light and infrared light for the electrode from which light is not extracted.

[0493] A conductive film that transmits visible light may also be used for the electrode on the side from which light is not extracted. In this case, the electrode is preferably disposed between the reflective layer and the EL layer 763. That is, light emitted from the EL layer 763 may be reflected by the reflective layer and extracted from the display device.

[0494] Materials for forming the pair of electrodes of a light-emitting device can include metals, alloys, electrically conductive compounds, and mixtures thereof. Specific examples of such materials include metals such as aluminum, magnesium, titanium, chromium, manganese, iron, cobalt, nickel, copper, gallium, zinc, indium, tin, molybdenum, tantalum, tungsten, palladium, gold, platinum, silver, yttrium, and neodymium, as well as alloys containing these metals in combination. Other examples of such materials include indium tin oxide (In-Sn oxide, also referred to as ITO), In-Si-Sn oxide (also referred to as ITSO), indium zinc oxide (In-Zn oxide), and In-W-Zn oxide. Other examples of such materials include aluminum alloys, such as aluminum-nickel-lanthanum alloys (Al-Ni-La), silver-magnesium alloys, and silver-palladium-copper alloys (Ag-Pd-Cu, also referred to as APC). Other examples of the material include elements belonging to Group 1 or 2 of the periodic table (e.g., lithium, cesium, calcium, and strontium) that are not listed above as examples, rare earth metals such as europium and ytterbium, alloys containing appropriate combinations of these, and graphene.

[0495] The light-emitting device preferably has a micro-optical resonator (microcavity) structure. Therefore, one of a pair of electrodes of the light-emitting device is preferably an electrode that is transparent and reflective to visible light (semi-transmissive / semi-reflective electrode), and the other is preferably an electrode that is reflective to visible light (reflective electrode). By having the light-emitting device have a microcavity structure, light emitted from the light-emitting layer can be resonated between the two electrodes, thereby intensifying the light emitted from the light-emitting device.

[0496] The light transmittance of an electrode that is transparent to visible light is 40% or more. For example, when an electrode that is transparent to visible light is used in a light-emitting device, it is preferable to use an electrode that has a transmittance of 40% or more for visible light (light with a wavelength of 400 nm or more and less than 750 nm). The visible light reflectance of a semi-transparent / semi-reflective electrode is 10% or more and 95% or less, preferably 30% or more and 80% or less. The visible light reflectance of a reflective electrode is 40% or more and 100% or less, preferably 70% or more and 100% or less. Furthermore, the resistivity of these electrodes is 1×10 −２ Preferably, it is Ωcm or less.

[0497] The light-emitting device has at least a light-emitting layer. The light-emitting device may further include a layer other than the light-emitting layer, such as a layer containing a substance with high hole-injection properties, a substance with high hole-transport properties, a hole-blocking material, a substance with high electron-transport properties, an electron-blocking material, a substance with high electron-injection properties, or a bipolar substance (a substance with high electron-transport properties and high hole-transport properties). For example, the light-emitting device may have, in addition to the light-emitting layer, one or more layers selected from a hole-injection layer, a hole-transport layer, a hole-blocking layer, a charge-generating layer, an electron-blocking layer, an electron-transport layer, and an electron-injection layer.

[0498] The light-emitting device can be made of either a low-molecular-weight compound or a high-molecular-weight compound, and may contain an inorganic compound. The layers constituting the light-emitting device can be formed by a method such as vapor deposition (including vacuum vapor deposition), transfer, printing, inkjet printing, or coating.

[0499] The light-emitting layer contains one or more light-emitting materials. As the light-emitting material, a material that emits light of blue, purple, blue-purple, green, yellow-green, yellow, orange, red, or the like is appropriately used. Furthermore, as the light-emitting material, a material that emits near-infrared light can also be used.

[0500] The light-emitting material may include a fluorescent material, a phosphorescent material, a TADF material, and a quantum dot material.

[0501] Examples of fluorescent materials include pyrene derivatives, anthracene derivatives, triphenylene derivatives, fluorene derivatives, carbazole derivatives, dibenzothiophene derivatives, dibenzofuran derivatives, dibenzoquinoxaline derivatives, quinoxaline derivatives, pyridine derivatives, pyrimidine derivatives, phenanthrene derivatives, and naphthalene derivatives.

[0502] Examples of phosphorescent materials include organometallic complexes (particularly iridium complexes) having a 4H-triazole skeleton, a 1H-triazole skeleton, an imidazole skeleton, a pyrimidine skeleton, a pyrazine skeleton, or a pyridine skeleton; organometallic complexes (particularly iridium complexes) having a phenylpyridine derivative having an electron-withdrawing group as a ligand; platinum complexes; and rare earth metal complexes.

[0503] The light-emitting layer may contain one or more organic compounds (host material, assist material, etc.) in addition to the light-emitting substance (guest material). As the one or more organic compounds, one or both of a substance with high hole-transporting properties (hole-transporting material) and a substance with high electron-transporting properties (electron-transporting material) can be used. As the hole-transporting material, a material with high hole-transporting properties that can be used for the hole-transporting layer, which will be described later, can be used. As the electron-transporting material, a material with high electron-transporting properties that can be used for the electron-transporting layer, which will be described later, can be used. Furthermore, as the one or more organic compounds, a bipolar material or a TADF material may be used.

[0504] The light-emitting layer preferably includes, for example, a phosphorescent material and a hole-transporting material and an electron-transporting material that are a combination that easily forms an exciplex. This configuration allows for efficient emission using Exciplex-Triple Energy Transfer (ExTET), which is energy transfer from the exciplex to the light-emitting material (phosphorescent material). By selecting a combination that forms an exciplex that emits light that overlaps with the wavelength of the lowest-energy absorption band of the light-emitting material, energy transfer becomes smooth, allowing for efficient emission. This configuration simultaneously enables high efficiency, low-voltage operation, and long life of the light-emitting device.

[0505] The hole injection layer is a layer that injects holes from the anode into the hole transport layer and contains a material with high hole injection properties, such as an aromatic amine compound and a composite material containing a hole transport material and an acceptor material (electron acceptor material).

[0506] As the hole transporting material, a material having high hole transporting properties that can be used for the hole transport layer, which will be described later, can be used.

[0507] The acceptor material can be, for example, an oxide of a metal belonging to Groups 4 to 8 of the periodic table. Specific examples include molybdenum oxide, vanadium oxide, niobium oxide, tantalum oxide, chromium oxide, tungsten oxide, manganese oxide, and rhenium oxide. Among these, molybdenum oxide is particularly preferred because it is stable in the air, has low hygroscopicity, and is easy to handle. Alternatively, an organic acceptor material containing fluorine can be used. Alternatively, an organic acceptor material such as a quinodimethane derivative, a chloranil derivative, or a hexaazatriphenylene derivative can be used.

[0508] For example, as a material with high hole injection properties, a material containing a hole transporting material and an oxide of a metal belonging to Groups 4 to 8 of the periodic table (typically, molybdenum oxide) may be used.

[0509] The hole transport layer is a layer that transports holes injected from the anode by the hole injection layer to the light emitting layer. The hole transport layer is a layer that contains a hole transport material. The hole transport material is 1×10 −６ cm ２ A substance having a hole mobility of 1 / Vs or more is preferred. Note that other substances can also be used as long as they have a higher hole transporting property than electron transporting property. As the hole transporting material, a material having a high hole transporting property, such as a π-electron-rich heteroaromatic compound (e.g., a carbazole derivative, a thiophene derivative, a furan derivative, etc.) or an aromatic amine (a compound having an aromatic amine skeleton), is preferred.

[0510] The electron blocking layer is provided in contact with the light-emitting layer. The electron blocking layer is a layer containing a material that has hole transport properties and can block electrons. The electron blocking layer can be made of a material that has electron blocking properties among the hole transport materials described above.

[0511] The electron blocking layer has hole transport properties and can therefore also be called a hole transport layer. Furthermore, a layer of the hole transport layer that has electron blocking properties can also be called an electron blocking layer.

[0512] The electron transport layer is a layer that transports electrons injected from the cathode by the electron injection layer to the light emitting layer. The electron transport layer is a layer that contains an electron transporting material. The electron transporting material has a concentration of 1×10 −６ cm ２ / Vs or more is preferred. Note that other materials can also be used as long as they have a higher electron transporting property than holes. As the electron-transporting material, materials with high electron transporting properties can be used, such as metal complexes having a quinoline skeleton, metal complexes having a benzoquinoline skeleton, metal complexes having an oxazole skeleton, and metal complexes having a thiazole skeleton, as well as oxadiazole derivatives, triazole derivatives, imidazole derivatives, oxazole derivatives, thiazole derivatives, phenanthroline derivatives, quinoline derivatives having a quinoline ligand, benzoquinoline derivatives, quinoxaline derivatives, dibenzoquinoxaline derivatives, pyridine derivatives, bipyridine derivatives, pyrimidine derivatives, and other π-electron-deficient heteroaromatic compounds including nitrogen-containing heteroaromatic compounds.

[0513] The hole-blocking layer is provided in contact with the light-emitting layer. The hole-blocking layer is a layer containing a material that has electron transport properties and can block holes. The hole-blocking layer can be made of a material that has hole-blocking properties and is selected from the above electron-transporting materials.

[0514] The hole blocking layer has electron transport properties and can therefore also be called an electron transport layer. Furthermore, a layer of the electron transport layer that has hole blocking properties can also be called a hole blocking layer.

[0515] The electron injection layer is a layer that injects electrons from the cathode to the electron transport layer and contains a material with high electron injection properties. Examples of the material with high electron injection properties include alkali metals, alkaline earth metals, and compounds thereof. Examples of the material with high electron injection properties include a composite material containing an electron transport material and a donor material (electron donor material).

[0516] It is preferable that the lowest unoccupied molecular orbital (LUMO) level of a material with high electron injection properties has a small difference (specifically, 0.5 eV or less) from the work function value of the material used for the cathode.

[0517] The electron injection layer may contain, for example, lithium, cesium, ytterbium, lithium fluoride (LiF), cesium fluoride (CsF), calcium fluoride (CaF ｘ , where X is an arbitrary number), 8-(quinolinolato)lithium (abbreviation: Liq), 2-(2-pyridyl)phenolatolithium (abbreviation: LiPP), 2-(2-pyridyl)-3-pyridinolatolithium (abbreviation: LiPPy), 4-phenyl-2-(2-pyridyl)phenolatolithium (abbreviation: LiPPP), lithium oxide (LiO ｘ ), alkali metals such as cesium carbonate, alkaline earth metals, or compounds thereof can be used. The electron injection layer may have a stacked structure of two or more layers. For example, the stacked structure may include a structure in which lithium fluoride is used as a first layer and ytterbium is provided as a second layer.

[0518] The electron injection layer may include an electron transporting material. For example, a compound having an unshared electron pair and an electron-deficient heteroaromatic ring can be used as the electron transporting material. Specifically, a compound having at least one of a pyridine ring, a diazine ring (pyrimidine ring, pyrazine ring, pyridazine ring), and a triazine ring can be used.

[0519] The LUMO level of an organic compound having an unshared electron pair is preferably −3.6 eV or more and −2.3 eV or less. Generally, the highest occupied molecular orbital (HOMO) level and the LUMO level of an organic compound can be estimated by CV (cyclic voltammetry), photoelectron spectroscopy, optical absorption spectroscopy, inverse photoelectron spectroscopy, or the like.

[0520] For example, 4,7-diphenyl-1,10-phenanthroline (abbreviation: BPhen), 2,9-di(naphthalen-2-yl)-4,7-diphenyl-1,10-phenanthroline (abbreviation: NBPhen), 2,2′-(1,3-phenylene)bis(9-phenyl-1,10-phenanthroline) (abbreviation: mPPhen2P), diquinoxalino[2,3-a:2′,3′-c]phenazine (abbreviation: HATNA), 2,4,6-tris[3′-(pyridin-3-yl)biphenyl-3-yl]-1,3,5-triazine (abbreviation: TmPPPyTz), etc. can be used as the organic compound having an unshared electron pair. Note that NBPhen has a higher glass transition point (Tg) and is superior in heat resistance compared to BPhen.

[0521] As described above, the charge generation layer has at least a charge generation region. The charge generation region preferably contains an acceptor material, for example, a hole transport material and an acceptor material applicable to the hole injection layer.

[0522] The charge generation layer preferably has a layer containing a material with high electron injection properties. This layer may also be called an electron injection buffer layer. The electron injection buffer layer is preferably provided between the charge generation region and the electron transport layer. By providing the electron injection buffer layer, the injection barrier between the charge generation region and the electron transport layer can be alleviated, so that electrons generated in the charge generation region can be easily injected into the electron transport layer.

[0523] The electron injection buffer layer preferably contains an alkali metal or an alkaline earth metal, and may contain, for example, an alkali metal compound or an alkaline earth metal compound. Specifically, the electron injection buffer layer preferably contains an inorganic compound containing an alkali metal and oxygen, or an inorganic compound containing an alkaline earth metal and oxygen, and may contain an inorganic compound containing lithium and oxygen (lithium oxide (Li ２ In addition, the electron injection buffer layer is preferably made of the above-mentioned materials applicable to the electron injection layer.

[0524] The charge generation layer preferably has a layer containing a material with high electron transport properties. This layer can also be called an electron relay layer. The electron relay layer is preferably provided between the charge generation region and the electron injection buffer layer. When the charge generation layer does not have an electron injection buffer layer, the electron relay layer is preferably provided between the charge generation region and the electron transport layer. The electron relay layer has the function of preventing interaction between the charge generation region and the electron injection buffer layer (or the electron transport layer) and smoothly transferring electrons.

[0525] The electron relay layer is preferably made of a phthalocyanine material such as copper (II) phthalocyanine (abbreviated as CuPc) or a metal complex having a metal-oxygen bond and an aromatic ligand.

[0526] It should be noted that the charge generation region, electron injection buffer layer, and electron relay layer may not be clearly distinguishable from one another depending on their cross-sectional shapes or characteristics.

[0527] The charge generation layer may have a donor material instead of an acceptor material. For example, the charge generation layer may have a layer containing an electron transport material and a donor material that can be used for the electron injection layer.

[0528] When light-emitting units are stacked, an increase in driving voltage can be suppressed by providing a charge generating layer between two light-emitting units.

[0529] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments.

[0530] Embodiment 5 In this embodiment, an example of a method for forming a light emitting element 61 will be described.

[0531] FIG. 44A shows a schematic plan view of a light-emitting element 61. The light-emitting element 61 includes a plurality of light-emitting elements 61R that emit red light, a plurality of light-emitting elements 61G that emit green light, and a plurality of light-emitting elements 61B that emit blue light. In FIG. 44A, the symbols R, G, and B are assigned within the light-emitting region of each light-emitting element to easily distinguish between the light-emitting elements. Also, while FIG. 44A illustrates a configuration having three emitted light colors, red (R), green (G), and blue (B), this is not limiting. For example, a configuration having four or more colors may also be used.

[0532] The light emitting elements 61R, 61G, and 61B are arranged in a matrix. Fig. 44A shows a so-called stripe arrangement in which light emitting elements of the same color are arranged in one direction, but the arrangement of the light emitting elements is not limited to this.

[0533] As the light-emitting element 61R, the light-emitting element 61G, and the light-emitting element 61B, it is preferable to use an organic EL device such as an OLED (organic light-emitting diode) or a QOLED (quantum-dot organic light-emitting diode). Examples of the light-emitting substance contained in the EL element include a substance that emits fluorescence (fluorescent material), a substance that emits phosphorescence (phosphorescent material), and a substance that exhibits thermally activated delayed fluorescence (thermally activated delayed fluorescence (TADF) material). As the light-emitting substance contained in the EL element, not only organic compounds but also inorganic compounds (such as quantum dot materials) can be used.

[0534] FIG. 44B is a schematic cross-sectional view corresponding to the dashed-dotted line A1-A2 in FIG. 44A . FIG. 44B shows cross sections of the light-emitting elements 61R, 61G, and 61B. The light-emitting elements 61R, 61G, and 61B are each provided on an insulator 363 and include a conductor 171 functioning as a pixel electrode and a conductor 173 functioning as a common electrode. The insulator 363 can be an inorganic insulating film or an organic insulating film, or both. It is preferable to use an inorganic insulating film as the insulator 363. Examples of inorganic insulating films include oxide insulating films and nitride insulating films such as a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, a silicon nitride film, an aluminum oxide film, an aluminum oxynitride film, and a hafnium oxide film.

[0535] The light-emitting element 61R has an EL layer 172R between a conductor 171 functioning as a pixel electrode and a conductor 173 functioning as a common electrode. The EL layer 172R contains a light-emitting organic compound that emits light having a peak in at least the red wavelength range. The EL layer 172G of the light-emitting element 61G contains a light-emitting organic compound that emits light having a peak in at least the green wavelength range. The EL layer 172B of the light-emitting element 61B contains a light-emitting organic compound that emits light having a peak in at least the blue wavelength range.

[0536] The EL layer 172R, the EL layer 172G, and the EL layer 172B may each have one or more of an electron injection layer, an electron transport layer, a hole injection layer, and a hole transport layer in addition to a layer containing a light-emitting substance (light-emitting layer).

[0537] The conductor 171 functioning as a pixel electrode is provided for each light-emitting element. The conductor 173 functioning as a common electrode is provided as a continuous layer common to each light-emitting element. A conductive film that is transparent to visible light is used for either the conductor 171 functioning as a pixel electrode or the conductor 173 functioning as a common electrode, and a conductive film that is reflective is used for the other. By making the conductor 171 functioning as a pixel electrode transparent and the conductor 173 functioning as a common electrode reflective, a bottom-emission display device can be obtained. Conversely, by making the conductor 171 functioning as a pixel electrode reflective and the conductor 173 functioning as a common electrode transparent, a top-emission display device can be obtained. Note that by making both the conductor 171 functioning as a pixel electrode and the conductor 173 functioning as a common electrode light-transmitting, a dual-emission display device can also be obtained.

[0538] For example, when the light-emitting element 61R is a top-emission type, the light 175R emitted from the light-emitting element 61R is emitted toward the conductor 173. When the light-emitting element 61G is a top-emission type, the light 175G emitted from the light-emitting element 61G is emitted toward the conductor 173. When the light-emitting element 61B is a top-emission type, the light 175B emitted from the light-emitting element 61B is emitted toward the conductor 173.

[0539] An insulator 272 is provided to cover an end portion of the conductor 171 functioning as a pixel electrode. The end portion of the insulator 272 preferably has a tapered shape. The insulator 272 can be made of a material similar to that of the insulator 363.

[0540] The insulator 272 is provided to prevent erroneous light emission due to unintentional electrical short circuit between adjacent light-emitting elements 61. In addition, when a metal mask is used to form the EL layer 172, the insulator 272 also functions to prevent the metal mask from coming into contact with the conductor 171.

[0541] The EL layer 172R, the EL layer 172G, and the EL layer 172B each have a region in contact with the plane of the conductor 171 that functions as a pixel electrode, and a region in contact with the surface of the insulator 272. Ends of the EL layer 172R, the EL layer 172G, and the EL layer 172B are located on the insulator 272.

[0542] As shown in Figure 44B, a gap is provided between two EL layers between light-emitting elements that emit different colors. In this manner, it is preferable that the EL layers 172R, 172G, and 172B are arranged so as not to be in contact with each other. This prevents current from flowing through two adjacent EL layers, which could result in unintended light emission (also known as crosstalk). This allows for increased contrast and a display device with high display quality to be realized.

[0543] The EL layers 172R, 172G, and 172B can be separately fabricated by vacuum deposition using a shadow mask such as a metal mask. Alternatively, they may be separately fabricated by photolithography. By using photolithography, a high-definition display device can be realized, which is difficult to achieve using a metal mask. Furthermore, since leakage current between adjacent EL layers is reduced, a display device with extremely vivid images, high contrast, and high display quality can be realized.

[0544] For example, in a formation method using a metal mask, it is difficult to make the distance between adjacent light-emitting elements 61 less than 10 μm, but by using a photolithography method, it is possible to narrow the distance to 8 μm or less, 3 μm or less, 2 μm or less, or 1 μm or less. Here, the distance between adjacent light-emitting elements 61 can be defined as the distance from the edge to the edge of two adjacent pixel electrodes. Alternatively, the distance between adjacent light-emitting elements 61 can be defined as the distance from the edge to the edge of two adjacent EL layers.

[0545] In this specification, etc., a device fabricated using a metal mask or an FMM (fine metal mask, high-resolution metal mask) may be referred to as a device with an MM (metal mask) structure. In addition, in this specification, etc., a device fabricated without using a metal mask or an FMM may be referred to as a device with an MML (metal maskless) structure.

[0546] By reducing the distance between adjacent light-emitting elements 61 as described above, the area of ​​the non-light-emitting region that may exist between two light-emitting elements can be significantly reduced, and the aperture ratio can be made close to 100%. For example, the aperture ratio can be 50% or more, 60% or more, 70% or more, 80% or more, or even 90% or more, and can even be less than 100%.

[0547] Furthermore, the pattern of the EL layer itself (also known as the processing size) can be made much smaller than when a metal mask is used. For example, when a metal mask is used to separately fabricate an EL layer, thickness variations occur between the center and edges of the EL layer, resulting in a smaller effective area that can be used as the light-emitting region relative to the area of ​​the EL layer. On the other hand, with the above-described fabrication method, the EL layer is formed by processing a film deposited to a uniform thickness, so the thickness can be made uniform within the EL layer, and even with a fine pattern, almost the entire area can be used as the light-emitting region. Therefore, the above-described fabrication method can achieve both high definition and a high aperture ratio.

[0548] Organic films formed using FMM often have an extremely small taper angle (e.g., greater than 0 degrees and less than 30 degrees), with the thickness decreasing toward the edge. Therefore, organic films formed using FMM have a continuous connection between their side surfaces and the flat surface, making it difficult to clearly identify the side surfaces. On the other hand, EL layers processed without using FMM have clear side surfaces. The side surfaces of the EL layer preferably have portions with a taper angle of 30 degrees or more and 120 degrees or less, preferably 60 degrees or more and 120 degrees or less.

[0549] A protective layer 271 is provided on the conductor 173, which functions as a common electrode, to cover the light-emitting elements 61R, 61G, and 61B. The protective layer 271 has a function of preventing impurities such as water from diffusing from above into each light-emitting element.

[0550] The protective layer 271 may have, for example, a single-layer structure or a stacked structure including at least an inorganic insulating film. Examples of inorganic insulating films include oxide films or nitride films such as silicon oxide films, silicon oxynitride films, silicon nitride oxide films, silicon nitride films, aluminum oxide films, aluminum oxynitride films, and hafnium oxide films. Alternatively, semiconductor materials such as indium gallium oxide and indium gallium zinc oxide (IGZO) may be used for the protective layer 271. Note that the protective layer 271 may be formed using an ALD method, a CVD method, or a sputtering method. Note that, although the protective layer 271 includes an inorganic insulating film, this is not limiting. For example, the protective layer 271 may have a stacked structure including an inorganic insulating film and an organic insulating film.

[0551] In this specification, "nitride oxide" refers to a compound containing more nitrogen than oxygen. "oxynitride" refers to a compound containing more oxygen than nitrogen. The content of each element can be measured, for example, by Rutherford backscattering spectrometry (RBS).

[0552] When indium gallium zinc oxide is used as the protective layer 271, it can be processed by wet etching or dry etching. For example, when IGZO is used as the protective layer 271, a chemical solution such as oxalic acid, phosphoric acid, or a mixed chemical solution (for example, a mixed chemical solution of phosphoric acid, acetic acid, nitric acid, and water (also referred to as a mixed acid aluminum etching solution)) can be used. Note that the mixed acid aluminum etching solution can have a volume ratio of phosphoric acid:acetic acid:nitric acid:water=53.3:6.7:3.3:36.7 or a similar ratio.

[0553] The structure shown in FIG. 44B may be called an SBS structure.

[0554] Fig. 44C shows a different example from the above. Specifically, Fig. 44C shows a light-emitting element 61W that emits white light. The light-emitting element 61W has an EL layer 172W that emits white light between a conductor 171 that functions as a pixel electrode and a conductor 173 that functions as a common electrode.

[0555] The EL layer 172W may be configured by stacking two or more light-emitting layers selected so that the emitted light colors are complementary to each other. Alternatively, a stacked EL layer may be used in which a charge generating layer is sandwiched between the light-emitting layers.

[0556] Figure 44C shows three light-emitting elements 61W lined up. A colored layer 264R is provided on the top of the left light-emitting element 61W. The colored layer 264R functions as a bandpass filter that transmits red light. Similarly, a colored layer 264G that transmits green light is provided on the top of the center light-emitting element 61W, and a colored layer 264B that transmits blue light is provided on the top of the right light-emitting element 61W. This allows the display device to display color images.

[0557] Here, the EL layer 172W and the conductor 173 functioning as a common electrode are separated between two adjacent light-emitting elements 61W. This prevents unintended light emission due to current flowing through the EL layer 172W between the two adjacent light-emitting elements 61W. In particular, when a stacked EL layer in which a charge generation layer is provided between two light-emitting layers is used as the EL layer 172W, the higher the resolution, i.e., the smaller the distance between adjacent pixels, the more pronounced the effect of crosstalk becomes, resulting in a decrease in contrast. Therefore, by using this configuration, a display device that combines high resolution and high contrast can be realized.

[0558] The separation of the EL layer 172W and the conductor 173 functioning as a common electrode is preferably performed by photolithography, which allows the spacing between the light-emitting elements to be narrowed, thereby achieving a display device with a higher aperture ratio than when a shadow mask such as a metal mask is used.

[0559] In the case of a bottom-emission light-emitting element, a colored layer may be provided between the conductor 171 functioning as a pixel electrode and the insulator 363 .

[0560] FIG. 44D shows an example different from the above. Specifically, FIG. 44D shows a configuration in which an insulator 272 is not provided between the light-emitting element 61R, the light-emitting element 61G, and the light-emitting element 61B. This configuration allows a display device with a high aperture ratio. Furthermore, by not providing the insulator 272, the unevenness of the light-emitting element 61 is reduced, thereby improving the viewing angle of the display device. Specifically, the viewing angle can be set to 150 degrees or more and less than 180 degrees, preferably 160 degrees or more and less than 180 degrees.

[0561] Furthermore, the protective layer 271 covers the side surfaces of the EL layer 172R, the EL layer 172G, and the EL layer 172B. This configuration can suppress impurities (typically, water, etc.) that can enter from the side surfaces of the EL layer 172R, the EL layer 172G, and the EL layer 172B. Furthermore, since leakage current between adjacent light-emitting elements 61 is reduced, the color saturation and contrast ratio are improved and power consumption is reduced.

[0562] 44D , the planar shapes of the conductor 171, the EL layer 172R, and the conductor 173 are generally the same. This structure can be formed all at once using a resist mask or the like after the conductor 171, the EL layer 172R, and the conductor 173 are formed. This process can also be called self-aligned patterning, because the EL layer 172R and the conductor 173 are processed using the conductor 173 as a mask. Note that although the EL layer 172R has been described here, the EL layer 172G and the EL layer 172B can also have a similar configuration.

[0563] 44D shows a structure in which a protective layer 273 is further provided on the protective layer 271. For example, the protective layer 271 may be formed using an apparatus (typically, an ALD apparatus) capable of depositing a film with high coverage, and the protective layer 273 may be formed using an apparatus (typically, a sputtering apparatus) capable of depositing a film with lower coverage than the protective layer 271, thereby providing a region 275 between the protective layer 271 and the protective layer 273. In other words, the region 275 is located between the EL layer 172R and the EL layer 172G, and between the EL layer 172G and the EL layer 172B.

[0564] The region 275 contains, for example, one or more elements selected from air, nitrogen, oxygen, carbon dioxide, and Group 18 elements (typically, helium, neon, argon, xenon, krypton, etc.). The region 275 may also contain, for example, a gas used when forming the protective layer 273. For example, when the protective layer 273 is formed by sputtering, the region 275 may contain one or more of the above Group 18 elements. When the region 275 contains a gas, the gas can be identified by gas chromatography or the like. When the protective layer 273 is formed by sputtering, the gas used during sputtering may also be contained in the protective layer 273. In this case, elements such as argon may be detected when the protective layer 273 is analyzed by energy dispersive X-ray analysis (EDX analysis) or the like.

[0565] Furthermore, if the refractive index of region 275 is lower than the refractive index of protective layer 271, light emitted from EL layer 172R, EL layer 172G, or EL layer 172B is reflected at the interface between protective layer 271 and region 275. This may prevent light emitted from EL layer 172R, EL layer 172G, or EL layer 172B from entering adjacent pixels. This prevents light of different colors from being mixed in with neighboring pixels, thereby improving the display quality of the display device.

[0566] 44D , the area between light-emitting element 61R and light-emitting element 61G or the area between light-emitting element 61G and light-emitting element 61B (hereinafter simply referred to as the distance between the light-emitting elements) can be narrowed. Specifically, the distance between the light-emitting elements can be set to 1 μm or less, preferably 500 nm or less, and more preferably 200 nm or less, 100 nm or less, 90 nm or less, 70 nm or less, 50 nm or less, 30 nm or less, 20 nm or less, 15 nm or less, or 10 nm or less. In other words, the distance between the side surface of EL layer 172R and the side surface of EL layer 172G or the distance between the side surface of EL layer 172G and the side surface of EL layer 172B has an area of ​​1 μm or less, preferably an area of ​​0.5 μm (500 nm) or less, and more preferably an area of ​​100 nm or less.

[0567] Furthermore, for example, when the region 275 contains gas, it is possible to isolate the light emitting elements while suppressing color mixing or crosstalk of light from each light emitting element.

[0568] The region 275 may be empty or filled with a filler. Examples of the filler include epoxy resin, acrylic resin, silicone resin, phenolic resin, polyimide, PVC (polyvinyl chloride) resin, PVB (polyvinyl butyral) resin, and EVA (ethylene vinyl acetate) resin. Photoresist may also be used as the filler. The photoresist used as the filler may be a positive photoresist or a negative photoresist.

[0569] FIG. 45A shows a different example from the above. Specifically, the configuration shown in FIG. 45A differs from the configuration shown in FIG. 44D in the configuration of the insulator 363. The insulator 363 has a recess formed by removing a portion of its flat surface during processing of the light-emitting elements 61R, 61G, and 61B. A protective layer 271 is formed in the recess. In other words, the insulator 363 has a region where the lower surface of the protective layer 271 is located lower than the lower surface of the conductor 171 in a cross-sectional view. By providing this region, impurities (typically, water, etc.) that may enter the light-emitting elements 61R, 61G, and 61B from below can be suppressed. The recess can be formed when impurities (also referred to as residue) that may adhere to the side surfaces of the light-emitting elements 61R, 61G, and 61B are removed by wet etching or the like during processing. After removing the residue, the side surfaces of the light-emitting elements are covered with the protective layer 271, resulting in a highly reliable display device.

[0570] FIG. 45B also shows a different example. Specifically, the configuration shown in FIG. 45B includes an insulator 276 and a microlens array 277 in addition to the configuration shown in FIG. 45A . The insulator 276 functions as an adhesive layer. When the refractive index of the insulator 276 is lower than that of the microlens array 277, the microlens array 277 can focus the light emitted from the light-emitting elements 61R, 61G, and 61B. This improves the light extraction efficiency of the display device. This is particularly advantageous because it allows a bright image to be viewed when a user views the display surface from directly in front of the display surface. The insulator 276 can be made of various curable adhesives, such as a photo-curable adhesive (e.g., an ultraviolet-curable adhesive), a reactive-curable adhesive, a thermosetting adhesive, or an anaerobic adhesive. Examples of such adhesives include epoxy resin, acrylic resin, silicone resin, phenolic resin, polyimide, PVC (polyvinyl chloride) resin, PVB (polyvinyl butyral) resin, and EVA (ethylene vinyl acetate) resin. In particular, materials with low moisture permeability, such as epoxy resin, are preferred. Two-component resins may also be used. Adhesive sheets may also be used.

[0571] FIG. 45C also shows an example different from the above. Specifically, the configuration shown in FIG. 45C has three light-emitting elements 61W instead of the light-emitting elements 61R, 61G, and 61B in the configuration shown in FIG. 45A. An insulator 276 is provided above the three light-emitting elements 61W, and coloring layers 264R, 264G, and 264B are provided above the insulator 276. Specifically, a coloring layer 264R that transmits red light is provided at a position overlapping the left light-emitting element 61W, a coloring layer 264G that transmits green light is provided at a position overlapping the center light-emitting element 61W, and a coloring layer 264B that transmits blue light is provided at a position overlapping the right light-emitting element 61W. This allows the semiconductor device to display a color image. The configuration shown in FIG. 45C is also a variation of the configuration shown in FIG. 44C.

[0572] Fig. 45D shows an example different from the above. Specifically, in the configuration shown in Fig. 45D, protective layer 271 is provided adjacent to the side surfaces of conductor 171 and EL layer 172. Conductor 173 is provided as a continuous layer common to each light-emitting element. In the configuration shown in Fig. 45D, region 275 is preferably filled with a filler material.

[0573] The color purity of the emitted color can be increased by providing a micro-optical resonator (microcavity) structure to the light-emitting element 61. To provide the light-emitting element 61 with a microcavity structure, the product (optical path) of the distance d between the conductors 171 and 173 and the refractive index n of the EL layer 172 should be configured to be m times half the wavelength λ (m is an integer of 1 or greater). The distance d can be calculated using Equation 1.

[0574] d = m × λ / (2 × n)... Equation 1.

[0575] According to Equation 1, the distance d of the light-emitting element 61 having the microcavity structure is determined according to the wavelength (emission color) of the emitted light. The distance d corresponds to the thickness of the EL layer 172. Therefore, the EL layer 172G may be provided thicker than the EL layer 172B, and the EL layer 172R may be provided thicker than the EL layer 172G.

[0576] Strictly speaking, the distance d is the distance from the reflective region of the conductor 171, which functions as a reflective electrode, to the reflective region of the conductor 173, which functions as an electrode (semi-transmissive / semi-reflective electrode) that is transparent and reflective to the emitted light. For example, if the conductor 171 is a laminate of silver and a transparent conductive film, ITO (Indium Tin Oxide), and the ITO is on the EL layer 172 side, the distance d can be set according to the emitted color by adjusting the film thickness of the ITO. In other words, even if the thicknesses of the EL layers 172R, 172G, and 172B are the same, the distance d appropriate for the emitted color can be obtained by changing the thickness of the ITO.

[0577] However, it may be difficult to precisely determine the positions of the reflection regions in the conductors 171 and 173. In this case, it is assumed that the microcavity effect can be fully obtained by assuming that any position in the conductors 171 and 173 is the reflection region.

[0578] The light-emitting element 61 is composed of a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, an electron injection layer, etc. Detailed configuration examples of the light-emitting element 61 will be described in other embodiments. In order to increase the light extraction efficiency in the microcavity structure, it is preferable to set the optical distance from the conductor 171 functioning as a reflective electrode to the light-emitting layer to an odd multiple of λ / 4. To achieve this optical distance, it is preferable to appropriately adjust the thickness of each layer constituting the light-emitting element 61.

[0579] Furthermore, when light is emitted toward the conductor 173, it is preferable that the reflectance of the conductor 173 be greater than the transmittance. The light transmittance of the conductor 173 is preferably 2% or more and 50% or less, more preferably 2% or more and 30% or less, and even more preferably 2% or more and 10% or less. By reducing the transmittance of the conductor 173 (increasing the reflectance), the effect of the microcavity can be enhanced.

[0580] Fig. 46A shows an example different from the above. Specifically, in the configuration shown in Fig. 46A, the EL layer 172 extends beyond the end of the conductor 171 in each of the light-emitting element 61R, the light-emitting element 61G, and the light-emitting element 61B. For example, in the light-emitting element 61R, the EL layer 172R extends beyond the end of the conductor 171. Furthermore, in the light-emitting element 61G, the EL layer 172G extends beyond the end of the conductor 171. In the light-emitting element 61B, the EL layer 172B extends beyond the end of the conductor 171.

[0581] In each of the light-emitting elements 61R, 61G, and 61B, the EL layer 172 and the protective layer 271 have an overlapping region with the insulator 270 interposed therebetween. In addition, in the region between adjacent light-emitting elements 61, an insulator 278 is provided on the protective layer 271.

[0582] Examples of the insulator 278 include epoxy resin, acrylic resin, silicone resin, phenol resin, polyimide, PVC (polyvinyl chloride) resin, PVB (polyvinyl butyral) resin, and EVA (ethylene vinyl acetate) resin. Photoresist may also be used as the insulator 278. The photoresist used as the insulator 278 may be a positive photoresist or a negative photoresist.

[0583] Furthermore, a common layer 174 is provided on the light-emitting elements 61R, 61G, and 61B and the insulator 278, and a conductor 173 is provided on the common layer 174. The common layer 174 has a region in contact with the EL layer 172R, a region in contact with the EL layer 172G, and a region in contact with the EL layer 172B. The common layer 174 is shared by the light-emitting elements 61R, 61G, and 61B.

[0584] The common layer 174 may be one or more of a hole injection layer, a hole transport layer, a hole blocking layer, an electron blocking layer, an electron transport layer, and an electron injection layer. For example, the common layer 174 may be a carrier injection layer (hole injection layer or electron injection layer). The common layer 174 can also be said to be a part of the EL layer 172. Note that the common layer 174 may be provided as needed. When the common layer 174 is provided, it is not necessary to provide a layer having the same function as the common layer 174 among the layers included in the EL layer 172.

[0585] In addition, a protective layer 273 is provided over the conductor 173 , and an insulator 276 is provided over the protective layer 273 .

[0586] FIG. 46B also shows an example different from the above. Specifically, the configuration shown in FIG. 46B has three light-emitting elements 61W instead of the light-emitting elements 61R, 61G, and 61B in the configuration shown in FIG. 46A. An insulator 276 is provided above the three light-emitting elements 61W, and coloring layers 264R, 264G, and 264B are provided above the insulator 276. Specifically, a coloring layer 264R that transmits red light is provided at a position overlapping the left light-emitting element 61W, a coloring layer 264G that transmits green light is provided at a position overlapping the center light-emitting element 61W, and a coloring layer 264B that transmits blue light is provided at a position overlapping the right light-emitting element 61W. This allows the semiconductor device to display a color image. The configuration shown in FIG. 46B is also a variation of the configuration shown in FIG. 45C.

[0587] 46C, a light-emitting element 61R, a light-emitting element 61G, and a light-receiving element 71 may be provided on an insulator 363. The light-receiving element 71 shown in FIG. 46C can be realized by replacing the EL layer 172 of the light-emitting element 61 with an active layer 182 (also referred to as a "light-receiving layer") that functions as a photoelectric conversion layer. The active layer 182 has a function of changing its resistance value depending on the wavelength and intensity of incident light. The active layer 182 can be formed of an organic compound, similar to the EL layer 172. Note that the active layer 182 may also be made of an inorganic material such as silicon.

[0588] The light receiving element 71 has a function of detecting light DLin incident from outside the display device through the protective layer 273, the conductor 173, and the common layer 174. A colored layer that transmits light in a desired wavelength range may be provided on the incident side of the light receiving element 71, overlapping the light receiving element 71.

[0589] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments.

[0590] Embodiment 6 In this embodiment, electronic devices to which the display device according to one embodiment of the present invention described in the above embodiment can be applied will be described.

[0591] A display device according to one embodiment of the present invention can be applied to a display portion of an electronic device. Therefore, an electronic device with high display quality, extremely high resolution, or high reliability can be realized.

[0592] Examples of electronic devices using the display device, the shift register, the signal output circuit, or the like according to one embodiment of the present invention include display devices such as televisions and monitors, lighting devices, desktop or notebook personal computers, word processors, and DVD (Digital Versatile Examples of such devices include image playback devices that play back still images or videos stored on recording media such as a CD or DVD, portable CD players, radios, tape recorders, headphone stereos, stereos, table clocks, wall clocks, cordless telephone handsets, transceivers, car phones, mobile phones, personal digital assistants, tablet terminals, portable game machines, fixed game machines such as pachinko machines, calculators, electronic organizers, e-book terminals, electronic translators, voice input devices, video cameras, digital still cameras, electric shavers, high-frequency heating devices such as microwave ovens, air conditioning equipment such as electric rice cookers, electric washing machines, electric vacuum cleaners, hot water heaters, electric fans, hair dryers, air conditioners, humidifiers, and dehumidifiers, dishwashers, dish dryers, clothes dryers, futon dryers, electric refrigerators, electric freezers, electric refrigerator-freezers, DNA storage freezers, flashlights, tools such as chainsaws, smoke detectors, and medical equipment such as dialysis machines. Further examples include industrial equipment such as emergency lights, traffic lights, conveyor belts, elevators, escalators, industrial robots, power storage systems, and power storage devices for power leveling and smart grids. Mobile bodies propelled by fuel-powered engines or electric motors powered by power from power storage devices may also be included in the category of electronic devices. Examples of such mobile bodies include electric vehicles (EVs), hybrid vehicles (HVs) that combine internal combustion engines and electric motors, plug-in hybrid vehicles (PHVs), tracked vehicles in which the tires and wheels of these vehicles are replaced with tracks, mopeds including electrically assisted bicycles, motorcycles, electric wheelchairs, golf carts, small or large ships, submarines, helicopters, aircraft, rockets, artificial satellites, space probes, planetary probes, and spaceships.

[0593] The electronic device may have a secondary battery, and it is preferable that the secondary battery can be charged using contactless power transmission.

[0594] Examples of secondary batteries include lithium ion secondary batteries, nickel-metal hydride batteries, nickel-cadmium batteries, organic radical batteries, lead-acid batteries, air secondary batteries, nickel-zinc batteries, and silver-zinc batteries.

[0595] The electronic device may have an antenna. By receiving a signal through the antenna, images, information, etc. can be displayed on the display unit. Furthermore, if the electronic device has an antenna and a secondary battery, the antenna may be used for contactless power transmission.

[0596] The electronic device may have sensors (including the ability to sense, detect, or measure force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemicals, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared).

[0597] An electronic device including a display device, a shift register, a signal output circuit, or the like according to one embodiment of the present invention can have various functions, such as a function of displaying various information (still images, videos, text images, etc.) on a display portion, a touch panel function, a function of displaying a calendar, date, time, etc., a function of executing various software (programs), a wireless communication function, a function of reading programs or data recorded on a recording medium, etc.

[0598] Furthermore, electronic devices having multiple display units can have a function of mainly displaying image information on one part of the display units and mainly displaying text information on another part, or a function of displaying a stereoscopic image by displaying an image taking into account parallax on the multiple display units. Furthermore, electronic devices having an image receiving unit can have a function of capturing a still image or a video, a function of automatically or manually correcting the captured image, a function of storing the captured image in a recording medium (external or built in the electronic device), a function of displaying the captured image on the display unit, etc. Note that the functions of the electronic device of one embodiment of the present invention are not limited to these, and can have various functions. ...

Claims

1. It has multiple signal output circuits, At least one of the plurality of signal output circuits has a first transistor, At least one of the plurality of signal output circuits is a shift register having the function of outputting a first signal via the first transistor, A first conductive layer having a region that functions as either the source electrode or the drain electrode of the first transistor, A first insulating layer having a region disposed on the first conductive layer, A second conductive layer having a region that functions as the other of the source electrode or drain electrode of the first transistor and having a region disposed on the first insulating layer, A first opening that penetrates the first insulating layer and the second conductive layer and overlaps the first conductive layer, A first semiconductor layer having a region in contact with the first insulating layer, a region in contact with the first conductive layer, and a region in contact with the second conductive layer, A third conductive layer having a region that functions as the gate electrode of the first transistor, The first transistor has a region that functions as a gate insulating film, and a second insulating layer having a region sandwiched between the first semiconductor layer and the third conductive layer at a first opening, The first signal is input to a shift register, either the source electrode or the drain electrode of the first transistor.

2. In claim 1, The third conductive layer is, In the first opening, the region overlapping with the first conductive layer, A shift register having a region on the first insulating layer that overlaps with the second conductive layer.

3. In claim 1 or claim 2, At least one of the plurality of signal output circuits is a shift register having a second transistor, A fourth conductive layer having a region that functions as either the source electrode or the drain electrode of the second transistor, The first insulating layer having a region disposed on the fourth conductive layer, A fifth conductive layer having a region that functions as the other of the source electrode or drain electrode of the first transistor and having a region disposed on the first insulating layer, A second opening penetrates the first insulating layer and the fifth conductive layer and overlaps with the fourth conductive layer, A second semiconductor layer having a region in contact with the first insulating layer, a region in contact with the fourth conductive layer, and a region in contact with the fifth conductive layer, A sixth conductive layer having a region that functions as the gate electrode of the second transistor and a region disposed on the second insulating layer, The second insulating layer has a region that functions as a gate insulating film of the second transistor, and a region that is sandwiched between the second semiconductor layer and the sixth conductive layer at the second opening, A shift register in which the fourth conductive layer and the third conductive layer are electrically connected to each other.

4. In claim 3, A shift register in which the height of the top surface of the fourth conductive layer and the height of the bottom surface of the sixth conductive layer are different when the bottom surface of the fourth conductive layer is used as a reference.

5. In claim 1 or claim 2, The first semiconductor layer is a shift register containing an oxide semiconductor.

6. In claim 3, The second semiconductor layer is a shift register containing an oxide semiconductor.

7. In claim 4, The second semiconductor layer is a shift register containing an oxide semiconductor.