Light-emitting element drive device

Abstract

This light-emitting element drive device (1) comprises: an input terminal (ADIM terminal); a smoothing circuit (4); a frequency monitor circuit (3) configured to switch whether an input signal (Din) inputted by the input terminal is inputted to the smoothing circuit or bypasses the output of the smoothing circuit in accordance with whether the frequency of the input signal is higher than a prescribed frequency threshold value; and a current driver (9) configured to generate, on the basis of the output from the smoothing circuit, a light-emitting element current (ILED) to be channeled to a light-emitting element (10).

Description

Light emitting element driving device

[0001] The present disclosure relates to a light emitting element driving device.

[0002] Conventionally, light emitting diodes (LEDs) have been known as an example of light emitting elements, and LEDs, which consume little power and have a long life, are used for a variety of purposes. A conventional example of an LED driving device for driving an LED is disclosed in Patent Document 1.

[0003] The LED driving device of Patent Document 1 includes an LED terminal configured to be connectable to a cathode of an LED, and a constant current driver connected to the LED terminal. The constant current driver causes a constant current to flow through the LED.

[0004] JP 2013-21117 A

[0005] Some LED driving devices have a DC dimming function that allows a DC (direct current) voltage to be input from an external source and controls the brightness of the LED by passing an LED current proportional to the input DC voltage through the LED. However, in some systems, it is not possible to input a DC voltage to the LED driving device from an external source, and a pulse signal must be input instead. Therefore, there is a demand for DC dimming even in such cases.

[0006] In view of the above circumstances, an object of the present disclosure is to provide a light-emitting element driving device that is capable of performing DC dimming with an effective configuration based on a DC voltage or pulse signal input from an external source.

[0007] For example, a light-emitting element driving device according to the present disclosure is configured to include an input terminal, a smoothing circuit, a frequency monitor circuit configured to switch between inputting the input signal to the input terminal to the smoothing circuit or bypassing the input signal to the output of the smoothing circuit depending on whether the frequency of the input signal is higher than a predetermined frequency threshold, and a current driver configured to generate a light-emitting element current to be passed through the light-emitting element based on the output of the smoothing circuit.

[0008] According to the light-emitting element driving device of the present disclosure, it is possible to perform DC dimming with an effective configuration based on a DC voltage or pulse signal input from the outside.

[0009] FIG. 1 is a diagram illustrating a configuration of an LED driver according to an exemplary embodiment of the present disclosure. FIG. 2 is a timing chart illustrating an example of operation when the input signal Din is a pulse signal. FIG. 3 is a timing chart illustrating an example of operation when the input signal Din has a low frequency. FIG. 4 is a timing chart illustrating another example of operation when the input signal Din has a low frequency. FIG. 5 is a diagram illustrating a configuration of a frequency monitor circuit according to a first modified example. FIG. 6 is a diagram illustrating a partial configuration of an LED driver according to a second modified example. FIG. 7 is a diagram illustrating a partial configuration of an LED driver according to a third modified example. FIG. 8 is a diagram illustrating a configuration of an LED driver according to a fourth modified example. FIG. 9 is a diagram illustrating a configuration of an LED driver according to a fifth modified example. FIG. 10 is a block diagram illustrating a configuration of an LED driving system according to a first comparative example. FIG. 11 is a block diagram illustrating a configuration of an LED driving system according to a second comparative example. FIG. 12 is a block diagram illustrating a configuration of an LED driving system according to a third comparative example. FIG. 13 is a block diagram illustrating a configuration of an LED driving system according to a fourth comparative example. FIG. 14 is a diagram illustrating a configuration of an LED driver according to the fourth comparative example. FIG. 15 is a diagram illustrating an example of a configuration of a current driver.

[0010] A system for driving an LED as an example of a light-emitting element will be described below. Therefore, the LED driver described below is an example of a light-emitting element driving device.

[0011] <Comparative Example> Before describing an exemplary embodiment according to the present disclosure, a comparative example will be described for comparison. By describing such a comparative example, the problem will become more apparent.

[0012] Fig. 10 is a block diagram showing the configuration of an LED driving system 401 according to a first comparative example. The LED driving system 401 shown in Fig. 10 includes a microcomputer 101, an LED driver 201, and a substrate 301. The microcomputer 101 and the LED driver 201 are mounted on the same substrate 301.

[0013] The microcomputer 101 has a DA (digital-analog) conversion function and is capable of outputting a DC voltage Vdc. The DC voltage Vdc is a voltage for dimming. The DC voltage Vdc output from the microcomputer 101 is input to an LED driver 201. The LED driver 201 is an integrated circuit (IC) capable of driving an LED (not shown). The LED driver 201 generates an LED current proportional to the input DC voltage Vdc and passes the generated LED current through the LED. This allows the LED to be driven at a brightness corresponding to the DC voltage Vdc, thereby implementing DC dimming.

[0014] Some microcomputers do not have a DA conversion function, and in such cases, an LED driving system 402 according to a second comparative example as shown in Fig. 11 can be used. The LED driving system 402 shown in Fig. 11 includes a microcomputer 102, an LED driver 202, a smoothing circuit 250, and a substrate 302. The microcomputer 102, the LED driver 202, and the smoothing circuit 250 are mounted on the same substrate 302. The LED driver 202 has the same configuration as the LED driver 201 according to the first comparative example (Fig. 10) described above.

[0015] Because the microcomputer 102 does not have a DA conversion function, it cannot output a DC voltage, but instead outputs a pulse signal (pulse voltage) Vpls for dimming. The pulse signal Vpls is input to a smoothing circuit 250, where it is smoothed and converted into a DC voltage Vdc. The generated DC voltage Vdc is input to an LED driver 202. The LED driver 202 generates an LED current proportional to the input DC voltage Vdc and passes the generated LED current through the LED. This allows DC dimming to be performed even by a microcomputer 102 that does not have a DA conversion function.

[0016] However, in the configuration according to the second comparative example, there is a problem in that an external smoothing circuit 250 is required for the LED driver 202.

[0017] In order to solve the above-mentioned problems, an improved embodiment according to a comparative example, which will be described below, is implemented. Fig. 12 is a block diagram showing the configuration of an LED driving system 403 according to a third comparative example. The LED driving system 403 shown in Fig. 12 includes a microcomputer 103, an LED driver 203, and a substrate 303. The microcomputer 103 and the LED driver 203 are mounted on the same substrate 303.

[0018] Since the microcomputer 103 does not have a DA conversion function, it cannot output a DC voltage, but instead outputs a pulse signal Vpls for dimming. The pulse signal Vpls is input to an LED driver 203. The LED driver 203 has a built-in smoothing circuit 203A. The pulse signal Vpls input to the LED driver 203 is smoothed by the smoothing circuit 203A and converted into a DC voltage. The LED driver 203 generates an LED current proportional to the generated DC voltage and passes the generated LED current through an LED (not shown). This allows DC dimming based on the pulse signal Vpls to be performed.

[0019] With the configuration shown in FIG. 12, the smoothing circuit externally attached to the LED driver 203 becomes unnecessary.

[0020] FIG. 13 is a block diagram showing the configuration of an LED driving system 404 according to a fourth comparative example. The LED driving system 404 shown in FIG. 13 differs from the configuration shown in FIG. 12 in that it includes separate boards 304A and 304B. The microcomputer 104 is mounted on board 304A, and the LED driver 204 is mounted on board 304B. Because the microcomputer 104 and the LED driver 204 are mounted on separate boards 304A and 304B, a potential difference in ground potential may occur between boards 304A and 304B. However, the configuration of the LED driver 204, which will be described later, makes it possible to suppress the effect of this potential difference in ground potential on LED dimming.

[0021] 14 is a diagram showing the configuration of an LED driver 204 according to a fourth comparative example. As shown in FIG. 14, the LED driver 204 is an IC having a level shifter LS, a smoothing circuit 204A, a constant current circuit 204B, a current mirror 204C, and a current driver 204D integrated on a single chip. The LED driver 204 also has an ADIM_P terminal (pulse input terminal), an ADIM terminal (DC input terminal), an ISET terminal (resistor connection terminal), and an LED terminal (LED connection terminal) as external terminals for establishing electrical connection with the outside.

[0022] An external pulse signal Vpls is input to the ADIM_P terminal. The pulse signal Vpls is composed of high and low levels and has a duty (the ratio of the high level to one cycle). As will be described later, DC dimming is performed based on this duty.

[0023] The level shifter LS includes a Schmitt buffer SB and a level shift circuit LSA. The Schmitt buffer SB converts the pulse signal Vpls input to the ADIM_P terminal into a level-shifted pulse signal PLA that is binarized with a high level being Vreg (internal voltage) and a low level being ground potential, and outputs the binarized signal. The Schmitt buffer SB sets the pulse signal PLA to a high level if the level of the pulse signal Vpls is higher than a predetermined threshold voltage, and sets the pulse signal PLA to a low level if not. A hysteresis characteristic is imparted to the threshold voltage.

[0024] A level shift circuit LSA is provided in the subsequent stage of the Schmitt buffer SB. When the input pulse signal PLA is at a high level, the level shift circuit LSA outputs a pulse signal PLB at the reference voltage Vref, and when the pulse signal PLA is at a low level, the level shift circuit LSA outputs a pulse signal PLB at the ground potential. In other words, a pulse signal PLB is generated whose high level is the reference voltage Vref and whose low level is the ground potential.

[0025] In this way, the level shifter LS level-shifts the input pulse signal Vpls to the pulse signal PLB. The pulse signal PLB is input to the smoothing circuit 204A. The smoothing circuit 204A is configured as an RC filter made up of a resistor R1 and a capacitor C1. The smoothing circuit 204A smooths the input pulse signal PLB and converts it into a DC voltage Vdc. When the high level of the pulse signal PLB is equal to the reference voltage Vref, the DC voltage Vdc is expressed as follows: Vdc = Vref × Duty where Duty: duty [%] of the pulse signal Vpls (= duty of the pulse signal PLB)

[0026] In this way, the pulse signal Vpls input to the ADIM_P terminal is converted by the Schmitt buffer SB into the pulse signal PLA, and then converted by the level shift circuit LSA into the pulse signal PLB. Therefore, the pulse signal Vpls is level-shifted by the level shifter LS to the pulse signal PLB, where the high level is Vref and the low level is ground potential. As a result, even if a potential difference occurs between the ground potentials of the boards 304A and 304B when the microcomputer 104 and the LED driver 204 are mounted on separate boards 304A and 304B as shown in FIG. 13 , the pulse signal Vpls is converted into the pulse signal PLB based on the ground potential of the board 304B on which the LED driver 204 is mounted, thereby minimizing the effect on dimming.

[0027] The DC voltage Vdc is input to the constant current circuit 204B. The constant current circuit 204B has an error amplifier EA and a transistor Tr. The non-inverting input terminal (+) of the error amplifier EA is connected to the output terminal of the smoothing circuit 204A. That is, the DC voltage Vdc is input to the non-inverting input terminal (+) of the error amplifier EA. The output terminal of the error amplifier EA is connected to the gate of a transistor Tr configured by an N-channel metal-oxide-semiconductor field-effect transistor (MOSFET). The source of the transistor Tr, together with the inverting input terminal (-) of the error amplifier EA, is connected to the ISET terminal. A setting resistor Reset is externally connected to the ISET terminal.

[0028] Such a constant current circuit 204B controls the voltage VA of the source (ISET terminal) of the transistor Tr to match the DC voltage Vdc, and a constant current IA determined by the voltage VA and the resistance value of the setting resistor Reset flows through the transistor Tr.

[0029] The constant current IA is mirrored by the current mirror 204C to form a constant current IB, which is supplied to the current driver 204D. FIG. 15 shows the configuration of the current driver 204D. The current driver 204D includes resistors Ra and Rb and an error amplifier Ap. One end of the resistor Ra is connected to the output terminal of the current mirror 204C at node Nb. The other end of the resistor Ra is connected to a terminal to which a ground potential is applied. Node Nb is connected to the non-inverting input terminal (+) of the error amplifier Ap. The output terminal of the error amplifier Ap is connected to the gate of a transistor M, which is an N-channel MOSFET. The source of the transistor M is connected to the inverting input terminal (-) of the error amplifier Ap and to one end of the resistor Rb. The other end of the resistor Rb is connected to a terminal to which a ground potential is applied. The drain of the transistor M is connected to an LED terminal. The cathode of the LED 504 is externally connected to the LED terminal.

[0030] With this configuration of the current driver 204D, the constant current IB output from the current mirror 204C is converted into a voltage VB at the node Nb by the resistor Ra. The voltage VC at the node Nc, where the source of the transistor M and one end of the resistor Rb are connected, is controlled to match the voltage VB. Therefore, the LED current I, which is determined by VC (=VB) and the resistance value of the resistor Rb, ＬＥＤ flows through the LED 504 via the LED terminal.

[0031] In this way, the LED driver 204 generates an LED current I according to the duty of the pulse signal Vpls. ＬＥＤ is generated, thereby adjusting the brightness of the LED 504. Here, in the LED driver 204, the ADIM terminal is connected to the non-inverting input terminal of the error amplifier EA. By inputting a DC voltage Vdc to the ADIM terminal, it is also possible to perform DC dimming of the LED 504 using the DC voltage Vdc.

[0032] However, when DC dimming is performed using PWM (pulse width modulation) with the pulse signal Vpls, the ADIM_P terminal is connected by wire bonding to a lead frame provided in a package (not shown) that encapsulates the LED driver 204, but the ADIM terminal is not connected by wire bonding. On the other hand, when DC dimming using the ADIM terminal is performed, the ADIM terminal is connected by wire bonding to the lead frame, but the ADIM_P terminal is not connected by wire bonding. Thus, the LED driver 204 requires two terminals, the ADIM_P terminal and the ADIM terminal, to perform DC dimming using two input methods. Furthermore, changing the wire bonding is required to switch the DC dimming input method, so only one input method can be used in one product.

[0033] <Embodiments of the Present Disclosure> In consideration of the above-described problems, the following embodiments of the present disclosure are implemented. Fig. 1 is a diagram showing the configuration of an LED driver 1 according to an exemplary embodiment of the present disclosure. The LED driver 1 has a level shifter 2, a frequency monitor circuit 3, a smoothing circuit 4, a selector 5, a voltage divider circuit 6, a constant current circuit 7, a current mirror 8, and a current driver 9 integrated on a single chip. The LED driver 1 also has external terminals, including an ADIM terminal (input terminal), an ISET terminal, and an LED terminal.

[0034] An input signal Din can be input to the ADIM terminal from the outside. As will be described later, the input signal Din can be a DC voltage with a relatively low frequency, or a pulse signal with a relatively high frequency.

[0035] The level shifter 2 has a comparator 21 and a level shift circuit 22. The non-inverting input terminal (+) of the comparator 21 is connected to the ADIM terminal. The inverting input terminal (-) of the comparator 21 is connected to an application terminal of a reference voltage Vref. The comparator 21 compares the input signal Din input to the ADIM terminal with the reference voltage Vref, and outputs a comparison signal Cpout as the comparison result. It is desirable that the comparator 21 be configured as a hysteresis comparator.

[0036] The level shift circuit 22 includes inverters IV1 and IV2, switches SW1 and SW2, and an amplifier A1. The switch SW1 is switched on and off by a switch control signal SC1 obtained by inverting the comparison signal Cpout using the inverter IV1. The switch SW2 is switched on and off by a switch control signal SC2 obtained by inverting the switch control signal SC1 using the inverter IV2.

[0037] The amplifier A1 forms a voltage follower. A reference voltage Vref application terminal is connected to the non-inverting input terminal (+) of the amplifier A1. The switch SW2 switches whether or not to output the output of the amplifier A1. The switch SW1 switches whether or not to output an output at ground potential. A level shift signal Lsout is generated as the output of the switches SW1 and SW2. The switches SW1 and SW2 are turned on when the switch control signals SC1 and SC2 are at high level, and turned off when they are at low level. Therefore, when the comparison signal Cpout is at high level, the switch SW2 is turned on and the switch SW1 is turned off, and the level shift signal Lsout is at the reference voltage Vref. When the comparison signal Cpout is at low level, the switch SW1 is turned on and the switch SW2 is turned off, and the level shift signal Lsout is at ground potential. That is, when the comparison signal Cpout is a pulse signal, a level shift signal Lsout is generated, which is a pulse signal with the reference voltage Vref at a high level and the ground potential at a low level.

[0038] In this way, when the input signal Din input to the ADIM terminal is a pulse signal, the level shifter 2 shifts the level of the input signal Din to the level-shifted signal Lsout.

[0039] The frequency monitor circuit 3 monitors the frequency of the input signal Din input to the ADIM terminal and includes a D flip-flop 31, an inverter 32, an NMOS transistor 33, a capacitor 34, a current mirror 35, a constant current source 36, inverters 37 and 38, and switches 39A and 39B.

[0040] The comparison signal Cpout is input to the clock terminal of the D flip-flop 31. The Q output terminal of the D flip-flop 31 is connected to the input terminal of the inverter 32. The output terminal of the inverter 32 is connected to the D terminal of the D flip-flop 31 and the gate of the NMOS transistor 33. The NMOS transistor 33 is configured as an N-channel MOSFET.

[0041] The source of the NMOS transistor 33 is connected to a terminal to which a ground potential is applied. The drain of the NMOS transistor 33 is connected to one end of a capacitor 34, and the source of the NMOS transistor 33 is connected to the other end of the capacitor 34. The current mirror 35 has an input transistor 35A and an output transistor 35B, both of which are P-channel MOSFETs. The drain of the input transistor 35A is connected to a constant current source 36. The drain of the output transistor 35B is connected to one end of the capacitor 34. The constant current from the constant current source 36 is mirrored by the current mirror 35 and used to charge the capacitor 34. The NMOS transistor 33 is used to discharge the capacitor 34.

[0042] One end of the capacitor 34 is connected to the input end of the inverter 37. The switch 39A is provided between the application end of the level shift signal Lsout (the output end of the level shifter 2) and the smoothing circuit 4, and is switched on and off according to the output level of the inverter 37. The inverter 38 is provided in the subsequent stage of the inverter 37. The switch 39B is provided between the ADIM terminal and the output end of the smoothing circuit 4, and is switched on and off according to the output level of the inverter 38.

[0043] When the output of the inverter 37 is at a low level, the switch 39A is in an off state, and at this time the output of the inverter 38 is at a high level, so the switch 39B is in an on state. On the other hand, when the output of the inverter 37 is at a high level, the switch 39A is in an on state, and at this time the output of the inverter 38 is at a low level, so the switch 39B is in an off state. The frequency monitor circuit 3 switches the on / off states of the switches 39A and 39B in accordance with the monitoring result of the frequency of the input signal Din (comparison signal Cpout).

[0044] The smoothing circuit 4 is configured as an RC filter made up of a resistor R1 and a capacitor C1. When the switch 39A is in the on state, the smoothing circuit 4 smoothes the level-shifted signal Lsout input via the switch 39A and converts it into the dimming output signal ADIM_OUT. When the high level of the level-shifted signal Lsout is equal to the reference voltage Vref, the dimming output signal ADIM_OUT is expressed as follows: ADIM_OUT = Vref x Dadim, where Dadim is the duty [%] of the input signal Din (= the duty of the level-shifted signal Lsout).

[0045] When the switch 39B is in the ON state, the input signal Din input to the ADIM terminal becomes the dimming output signal ADIM_OUT as it is. That is, the input signal Din is bypassed to the output of the smoothing circuit 4.

[0046] The dimming output signal ADIM_OUT is input to a first input terminal of the selector 5. The voltage divider circuit 6 has voltage-dividing resistors Rd1 and Rd2, and divides the reference voltage Vref to generate a reference voltage Vref', which is input to a second input terminal of the selector 5. The selector 5 selects the lower of the dimming output signal ADIM_OUT and the reference voltage Vref', and outputs the selection result to the constant current circuit 7. The configurations of the constant current circuit 7, the current mirror 8, and the current driver 9 are similar to those of 204B, 204C, and 204D in the LED driver 204 (FIG. 14) according to the comparative example, and therefore will not be described in detail.

[0047] The operation of the LED driver 1 according to this embodiment will now be described. Fig. 2 is a timing chart showing an example of operation when the input signal Din is a pulse signal. Fig. 2 (and Figs. 3 and 4, which will be described later) shows, from top to bottom, example waveforms of the input signal Din, the comparison signal Cpout, the voltage V1 of the output signal of the inverter 32 (the gate voltage of the NMOS transistor 33), the voltage V2 of the capacitor 34, the voltage V3 of the output signal of the inverter 38 (the control voltage of the switch 39B), and the dimming output signal ADIM_OUT.

[0048] In FIG. 2 , the high level of the input signal Din is higher than the reference voltage Vref. As a result, at timing t1 when the input signal Din rises from low to high during startup, the comparison signal Cpout also rises from low to high, and the D flip-flop 31 operates to cause the voltage V1 to rise from low to high. This causes the NMOS transistor 33 to turn on, and the voltage V2 to remain low. Therefore, the voltage V3 also remains low, and the switch 39A remains on and the switch 39B remains off. This causes the level-shift signal Lsout to be smoothed by the smoothing circuit 4 via the switch 39A and input to the selector 5 as the dimming signal ADIM_OUT. The dimming signal ADIM_OUT rises from 0 V when the input signal Din rises.

[0049] Thereafter, at timing t2 when the input signal Din falls from high to low, the comparison signal Cpout also falls from high to low, and the D flip-flop 31 operates to maintain the voltage V1 at a high level and the voltage V2 at a low level. Therefore, the voltage V3 also remains at a low level, the switch 39A remains on, and the switch 39B remains off. This causes the level-shift signal Lsout to be smoothed by the smoothing circuit 4 via the switch 39A and output as the dimming signal ADIM_OUT. The dimming signal ADIM_OUT decreases as the input signal Din falls.

[0050] Thereafter, at timing t3 when the input signal Din rises from low to high, the comparison signal Cpout also rises from low to high, and the D flip-flop 31 operates to cause the voltage V1 to fall from high to low. This turns the NMOS transistor 33 off, charging of the capacitor 34 with a constant current begins, and the voltage V2 rises. Thereafter, at timing t4 when the input signal Din falls from high to low, the comparison signal Cpout also rises from high to low, and the D flip-flop 31 operates to cause the voltage V1 to remain low. This keeps the NMOS transistor 33 off, charging of the capacitor 34 continues, and the voltage V2 continues to rise.

[0051] Thereafter, at timing t5 when the input signal Din rises from low to high, the comparison signal Cpout also rises from low to high, and the D flip-flop 31 operates to cause the voltage V1 to rise from low to high. This turns on the NMOS transistor 33, discharges the capacitor 34, and causes the voltage V2 to fall to 0 V. Because the voltage V2 has not yet reached the threshold Vgs of the inverter 37 at timing t5, the voltage V3 remains low, and the switch 39A remains on and the switch 39B remains off. The threshold Vgs is the gate-source voltage threshold of the lower NMOS transistor in the CMOS structure that constitutes the inverter 37.

[0052] Thereafter, by repeating the same operation, the switch 39A is maintained in the on state, and the level shift signal Lsout is smoothed by the smoothing circuit 4 to become the dimming signal ADIM_OUT. As a result, the dimming signal ADIM_OUT rises to Vref×Dadim and is stabilized. Therefore, in the case of FIG. 2, DC dimming is performed by the PWM input method of the input signal Din.

[0053] Here, when ADIM_OUT is lower than the reference voltage Vref′, the LED current I ＬＥＤ is generated, but when ADIM_OUT is higher than the reference voltage Vref′, the selector 5 selects the reference voltage Vref′, and the LED current I ＬＥＤ is limited to a current value according to the reference voltage Vref'. Therefore, it is possible to provide a dead zone for dimming in which the luminance does not change even if Dadim is increased.

[0054] FIG. 3 is a timing chart showing an example of operation when the frequency of the input signal Din is low (in the case of DC input). In FIG. 3, at timing t11 during startup, the input signal Din rises from low level but does not reach the reference voltage Vref. In this case, the comparison signal Cpout remains low, and the voltage V1 remains low. This causes the NMOS transistor 33 to remain off, and the constant current source 36 begins to supply a constant current, which starts charging the capacitor 34. Therefore, the voltage V2 begins to rise. While the voltage V2 does not reach the threshold Vgs, the voltage V3 remains low, and the dimming signal ADIM_OUT is at 0 V due to the on state of the switch 39A.

[0055] Thereafter, the level of the input signal Din is maintained, and when the voltage V2 reaches the threshold Vgs at timing t12, the voltage V3 rises from low to high. This switches the switch 39B to the on state, and the input signal Din remains as the dimming signal ADIM_OUT. After that, as shown in FIG. 3, even if the input signal Din decreases, the input signal Din remains as the dimming signal ADIM_OUT. Therefore, in the case of FIG. 3, DC dimming is performed using the input signal Din as a DC voltage.

[0056] FIG. 4 is a timing chart showing another example of operation when the frequency of the input signal Din is low. In FIG. 4, at timing t21 during startup, the input signal Din rises from low level and exceeds the reference voltage Vref. In this case, the comparison signal Cpout rises from low level to high level. As a result, the D flip-flop 31 operates to cause the voltage V1 to rise from low level to high level, while the voltage V2 remains at 0 V. As a result, the voltage V3 remains at low level, and the switch 39A remains on. Therefore, the rising edge of the comparison signal Cpout causes the dimming signal ADIM_OUT, which is obtained by smoothing the level shift signal Lsout using the smoothing circuit 4, to rise. Thereafter, as the level of the input signal Din is maintained, the dimming signal ADIM_OUT reaches the reference voltage Vref and stabilizes. Therefore, in the case of FIG. 4, since Vref>Vref', the selector 5 selects the LED current I corresponding to the reference voltage Vref'. ＬＥＤ is generated.

[0057] The dimming signal ADIM_OUT may be input to the constant current circuit 7 without providing the selector 5 .

[0058] As described above, in this embodiment, when the frequency threshold value fth is set to I / (C·Vgs) (where C is the capacitance of the capacitor 34 and I is the constant current value for charging the capacitor 34), if the frequency of the input signal Din is greater than fth, the frequency monitor circuit 3 keeps the switch 39A on, and DC dimming is performed using the PWM input method of the input signal Din, as shown in the example of Fig. 2. On the other hand, if the frequency of Din is less than fth, the frequency monitor circuit 3 turns the switch 39B on, and the input signal Din is bypassed to the output of the smoothing circuit 4, as shown in the example of Fig. 3, and DC dimming is performed using the DC input method of the input signal Din.

[0059] Therefore, in this embodiment, one input terminal (ADIM terminal) can accommodate two input methods, and there is no need to change the wire bonding as in the comparative example.

[0060] <Frequency Division of Comparison Signal> In the configuration shown in Fig. 1 described above, when the input signal Din is a pulse signal, the comparison signal Cpout is divided by 2 to generate the voltage V1 as shown in Fig. 2. However, the division is not limited to 2, and division by 4, 8, or the like may also be used. For example, as shown in Fig. 5, by providing two unit stages in the frequency monitor circuit 3, each of which includes a D flip-flop 31A and an inverter 32A and another unit stage including a D flip-flop 31B and an inverter 32B, the comparison signal Cpout can be divided by 4 to generate the voltage V1. Note that the unit stages may be three or more (Fig. 1 shows a single unit stage).

[0061] By increasing the frequency division ratio, the discharge time of the capacitor 34 can be extended, and the discharge can be performed more reliably. If the discharge is not reliable, charge may remain in the capacitor 34, and the voltage V2 may exceed the threshold Vgs when the capacitor 34 is charged.

[0062] <Countermeasures against Coupling> In the configuration shown in FIG. 1, when the input signal Din is a pulse signal, the switch 39A is in the ON state, and the switch 39B is in the OFF state, the input signal Din input to the ADIM terminal may affect the dimming signal ADIM_OUT, which is the output of the smoothing circuit 4, due to coupling caused by the parasitic capacitance of the switch 39B, and fluctuations may occur in the dimming signal ADIM_OUT.

[0063] 6, a filter 391 may be provided after the switch 39B in the bypass path to the output of the smoothing circuit 4. This makes it possible to suppress the influence of the input signal Din on the dimming signal ADIM_OUT due to coupling.

[0064] Alternatively, as shown in FIG. 7, one or more switches 39C may be connected in series to the rear stage of switch 39B, and multiple stages of switches 39B may be provided that are on / off controlled by the output of inverter 38.

[0065] <Schmitt Trigger> As in the configuration of the LED driver 1 according to the modified example shown in FIG. 8 , a Schmitt buffer 23 may be used instead of the comparator 21. The Schmitt buffer 23 outputs a high-level signal if the level of the input signal Din is higher than a predetermined threshold voltage, and outputs a low-level signal otherwise. A hysteresis characteristic is imparted to the threshold voltage. However, using the comparator 21 makes it easier to set the threshold voltage for the input signal Din with high accuracy.

[0066] 1, some parts of the frequency monitor circuit 3 (the NMOS transistor 33, the capacitor 34, the current mirror 35, and the constant current source 36) are configured using analog circuits, but a digital circuit 30 may be provided in the frequency monitor circuit 3 as shown in Fig. 9. The digital circuit 30 compares the frequency of the comparison signal Cpout with a predetermined frequency, and switches on and off the switches 39A and 39B according to the comparison result.

[0067] <Others> Although exemplary embodiments have been described above, the embodiments can be modified in various ways within the scope of the spirit of the present invention.

[0068] <Additional Notes> As described above, for example, a light-emitting element driving device (1) according to one aspect of the present disclosure includes an input terminal (ADIM terminal), a smoothing circuit (4), a frequency monitor circuit (3) configured to switch between inputting an input signal (Din) to the input terminal to the smoothing circuit or bypassing the input signal to an output of the smoothing circuit depending on whether the frequency of the input signal is higher than a predetermined frequency threshold, and a light-emitting element current (I) to be passed through a light-emitting element (10) based on the output of the smoothing circuit. ＬＥＤ and a current driver (9) configured to generate a current (first configuration).

[0069] In addition, in the first configuration, the frequency monitor circuit (3) may have a first switch (39A) arranged in a stage preceding the smoothing circuit (4) and a second switch (39B) arranged in a path bypassing from the input terminal (ADIM terminal) to the output of the smoothing circuit, and when the frequency of the input signal (Din) is higher than the frequency threshold, the first switch is controlled to an on state and the second switch is controlled to an off state, and when the frequency of the input signal is lower than the frequency threshold, the first switch is controlled to an off state and the second switch is controlled to an on state (second configuration).

[0070] Moreover, in the second configuration, the light-emitting element driving device (1) further includes an output unit (21) configured to output a binary signal (Cpout) of high level or low level according to a comparison between the input signal (Din) and a threshold voltage (Vref), and the frequency monitor circuit (3) includes at least one unit configuration having a D flip-flop (31) including a clock terminal, a D terminal, and an output terminal, and an inverter (32) including an input terminal connected to the output terminal and an output terminal connected to the D terminal, a transistor (33) including a control terminal, a first terminal, and a second terminal, a capacitor (34) connected between the first terminal and the second terminal of the transistor, and constant current supply units (35, 36) configured to supply a constant current to the capacitor, and the clock terminal of the D flip-flop in the unit configuration at the front stage is configured to receive the binary signal (Cpout), The output terminal of the inverter in the unit configuration at the rearmost stage may be connected to the control terminal, and the first switch (39A) and the second switch (39B) may be configured to be controlled to be turned on and off in accordance with the voltage of the capacitor (third configuration).

[0071] In the third configuration, the output section may have a comparator (21) (fourth configuration).

[0072] In the third configuration, the output section may have a Schmitt buffer (23) (fifth configuration).

[0073] In addition, in any of the third to fifth configurations, the light-emitting element driving device (1) may further include a level shifter (2) having the output section (21) and a level shift circuit (22) arranged in a stage subsequent to the output section, and the high level of the level shift signal (Lsout) output from the level shift circuit may be configured to be the same voltage as the threshold voltage (Vref) (sixth configuration).

[0074] In any of the third to sixth configurations, the unit structures may be arranged in a plurality of stages (seventh configuration).

[0075] In addition, in the second configuration, the frequency monitor circuit (3) may have a digital circuit (30) configured to control the on / off of the first switch (39A) and the second switch (39B) depending on a comparison result between the frequency of a signal based on the input signal (Din) and the frequency threshold value (eighth configuration).

[0076] In addition, any one of the second to eighth configurations may further include a filter (391) arranged in the subsequent stage of the second switch (39B) (ninth configuration).

[0077] In addition, any one of the second to eighth configurations may be configured to further include a plurality of stages of switches (39B, 39C) including the second switch (39B) (tenth configuration).

[0078] In addition, in any of the first to tenth configurations, the light-emitting element driving device (1) may further include a level shifter (2) arranged between the input terminal (ADIM terminal) and the smoothing circuit (4), and the signal output from the level shifter may have two values, high level and low level, the high level being a reference voltage (Vref), and the low level being a ground potential (eleventh configuration).

[0079] In addition, in the above-mentioned eleventh configuration, the level shifter (2) may be configured to have an output section (21) configured to output a binary signal of high level or low level according to a comparison between the input signal (Din) and a threshold voltage, and a level shift circuit (22) arranged in a stage subsequent to the output section (twelfth configuration).

[0080] In the twelfth configuration, the output section may have a hysteresis comparator (21) (thirteenth configuration).

[0081] In the twelfth configuration, the output section may have a Schmitt buffer (23) (fourteenth configuration).

[0082] Furthermore, in any of the above configurations 11 to 14, the light-emitting element driving device (1) may further include a voltage divider circuit (6) configured to divide the reference voltage (Vref), and a selector (5) configured to select the lower of the output of the smoothing circuit (4) and the voltage (Vref') after division by the voltage divider circuit, and the current driver (9) may be configured to generate the light-emitting element current based on the output of the selector (configuration 15).

[0083] The present disclosure can be used, for example, as a means for driving LEDs for various applications.

[0084] 1 LED driver 2 Level shifter 3 Frequency monitor circuit 4 Smoothing circuit 5 Selector 6 Voltage divider circuit 7 Constant current circuit 8 Current mirror 9 Current driver 21 Comparator 22 Level shift circuit 23 Schmitt buffer 30 Digital circuit 31 D flip-flop 31A, 31B D flip-flop 32 Inverter 33 NMOS transistor 34 Capacitor 35 Current mirror 35A Input side transistor 35B Output side transistor 36 Constant current source 37, 38 Inverter 39A, 39B, 39C Switch 101 to 104 Microcomputer 201 to 204 LED driver 203A Smoothing circuit 204A Smoothing circuit 204B Constant current circuit 204C Current mirror 204D Current driver 250 Smoothing circuit 301 to 303 Board 304A, 304B Board 391 Filter 401 to 404 LED drive system 504 LED A1 Amplifier Ap Error amplifier C1 Capacitor EA Error amplifier IV1, IV2 Inverter LS Level shifter LSA Level shift circuit M Transistor R1 Resistor Ra, Rb Resistor Rd1, Rd2 Voltage dividing resistor Reset Setting resistor SB Schmitt buffer SW1, SW2 Switch Tr Transistor

Claims

1. An input terminal; A smoothing circuit; a frequency monitor circuit configured to switch between inputting the input signal to the input terminal to the smoothing circuit or bypassing the input signal to an output of the smoothing circuit depending on whether the frequency of the input signal is higher than a predetermined frequency threshold; a current driver configured to generate a light emitting element current to be applied to a light emitting element based on an output of the smoothing circuit; A light-emitting element driving device comprising:

2. the frequency monitor circuit has a first switch arranged in a stage preceding the smoothing circuit, and a second switch arranged in a bypass path from the input terminal to an output of the smoothing circuit, When the frequency of the input signal is higher than the frequency threshold, the first switch is controlled to be in an on state and the second switch is controlled to be in an off state; The light-emitting element driving device according to claim 1 , wherein, when the frequency of the input signal is lower than the frequency threshold, the first switch is controlled to be in an off state and the second switch is controlled to be in an on state.

3. The light emitting element driving device further includes an output unit configured to output a binary signal of a high level or a low level in response to a comparison between the input signal and a threshold voltage; The frequency monitor circuit includes: At least one unit configuration having a D flip-flop including a clock terminal, a D terminal, and an output terminal, and an inverter including an input terminal connected to the output terminal and an output terminal connected to the D terminal; a transistor including a control end, a first end, and a second end; a capacitor connected between the first terminal and the second terminal of the transistor; a constant current supply configured to supply a constant current to the capacitor; having the clock terminal of the D flip-flop in the unit configuration at the frontmost stage is configured to receive the binary signal; The output terminal of the inverter in the most rear stage unit configuration is connected to the control terminal, The light-emitting element driving device according to claim 2 , wherein the first switch and the second switch are configured to be controlled to be turned on and off in response to a voltage of the capacitor.

4. The light emitting element driving device according to claim 3 , wherein the output section includes a comparator.

5. The light emitting element driving device according to claim 3 , wherein the output section includes a Schmitt buffer.

6. The light emitting element driving device further includes a level shifter having the output section and a level shift circuit arranged in a subsequent stage of the output section, 4. The light-emitting element driving device according to claim 3, wherein a high level of the level shift signal output from said level shift circuit is the same voltage as said threshold voltage.

7. The light emitting element driving device according to claim 3 , wherein the unit components are provided in a plurality of stages.

8. 3. The light-emitting element driving device according to claim 2, wherein the frequency monitor circuit has a digital circuit configured to control the first switch and the second switch to be turned on and off depending on a result of comparing a frequency of a signal based on the input signal with the frequency threshold value.

9. The light-emitting element driving device according to claim 2 , further comprising a filter disposed in a stage following the second switch.

10. The light-emitting element driving device according to claim 2 , further comprising a plurality of stages of switches including the second switch.

11. The light emitting element driving device further includes a level shifter disposed between the input terminal and the smoothing circuit, 2. The light-emitting element driving device according to claim 1, wherein the signal output from said level shifter has two values, a high level and a low level, said high level being a reference voltage and said low level being a ground potential.

12. The level shifter includes: an output section configured to output a binary signal of high level or low level in response to a comparison between the input signal and a threshold voltage; a level shift circuit disposed downstream of the output unit; The light emitting element driving device according to claim 11 ,

13. The light-emitting element driving device according to claim 12 , wherein the output section includes a hysteresis comparator.

14. The light emitting element driving device according to claim 12 , wherein the output section includes a Schmitt buffer.

15. The light emitting element driving device a voltage divider circuit configured to divide the reference voltage; a selector configured to select the lower of the output of the smoothing circuit and the voltage after voltage division by the voltage divider circuit; Further equipped with The light-emitting element driving device according to claim 11 , wherein the current driver is configured to generate the light-emitting element current based on an output of the selector.