Power conversion device and control method for power conversion device

Abstract

This power conversion device is provided with an arm unit and a control device that controls the arm unit. The arm unit includes a plurality of cells connected in series. The plurality of cells include a pair of connection terminals, a plurality of semiconductor switch elements, a power storage element connected in parallel to the plurality of semiconductor switch elements, and a voltage detector for detecting the voltage of the power storage element. The control device can switch, in a manner corresponding to each of the plurality of cells, the states of a plurality of semiconductor switch elements included in a corresponding cell so as to be in any of states including at least a state in which the connection terminals of the corresponding cell output at least one of a positive and a negative voltage and a state in which the connection terminals are electrically connected to each other. For each instance of a predetermined timing, the control device selects any one of the plurality of cells for switching of the states thereof on the basis of the voltages of the power storage elements of each of the plurality of cells and the durations of the states of the plurality of cells, then switches the states of the plurality of semiconductor switch elements included in the selected cell.

Description

Power conversion device and control method for power conversion device

[0001] The present disclosure relates to a power conversion device connected to a power grid.

[0002] Power conversion equipment is connected to power grids to adjust the voltage and power factor and improve stability. Power conversion equipment controls multiple semiconductor switches to input and output active and reactive power to and from the power grid, thereby helping to stabilize the frequency and voltage of the grid.

[0003] There are various configurations of power conversion devices, but in recent years, there has been an increasing number of cases where power conversion devices, each consisting of multiple connected structural units called cells, are connected to a grid. Control of such power conversion devices with multiple cells requires not only control that directly contributes to the grid, but also equalizing the capacitor voltages of the cells, and selecting, for each time period, which cell's capacitor to discharge power from, which cell's capacitor to charge power to, or neither. Cell selection and operation instructions are then given to semiconductor switches in the cells, which switch between ON and OFF states to operate according to the control output (see Patent Document 1).

[0004] Japanese Patent Application Laid-Open No. 2022-99845

[0005] Due to the electrical characteristics of the semiconductor switches in the cells, if they are switched to the ON state once and then switched back to the OFF state in an extremely short time, there is a risk of surge generation or destruction of the semiconductor switches. In the configuration of Patent Document 1, the time it takes for the cells to switch back to the OFF state after being switched to the ON state is not guaranteed, and there is a risk that the same cell will switch switching states in an extremely short time. In other words, it is not possible to prevent surge generation or destruction of the semiconductor switches.

[0006] The present disclosure is intended to solve the above-mentioned problems, and has an object to provide a power conversion device and a control method thereof that can prevent the occurrence of surges and breakdowns.

[0007] A power conversion device according to one embodiment includes an arm unit and a control device that controls the arm unit. The arm unit includes a plurality of cells connected in series. The plurality of cells include a pair of connection terminals, a plurality of semiconductor switch elements, energy storage elements connected in parallel to the plurality of semiconductor switch elements, and a voltage detector that detects the voltage of the energy storage elements. The control device is capable of switching the states of a plurality of semiconductor switches included in each of the plurality of cells so that the corresponding cell is in one of two states, including at least a state in which the connection terminal of the corresponding cell outputs at least one of a positive and a negative voltage, and a state in which the connection terminals are electrically connected. At predetermined timings, the control device selects one of the plurality of cells whose state is to be switched based on the voltage of the energy storage element included in each of the plurality of cells and the duration of the state of the plurality of cells, and switches the states of the plurality of semiconductor switches included in the selected cell.

[0008] A control method for a power conversion device according to an embodiment is a control method for a power conversion device including an arm unit, wherein the arm unit includes a plurality of cells connected in series, each of the plurality of cells including a pair of connection terminals, a plurality of semiconductor switch elements, a storage element connected in parallel to the plurality of semiconductor switch elements, and a voltage detector that detects a voltage of the storage element. The control method includes the steps of: selecting, at each predetermined timing, one of a plurality of cells whose state is to be switched based on the voltage of the storage element included in each of the plurality of cells and a duration of each state of the plurality of cells; and switching the states of a plurality of semiconductor switches included in the selected cell to one of the states including at least a state in which the connection terminal of the cell outputs at least one of a positive and a negative voltage and a state in which the connection terminals are electrically connected.

[0009] The power conversion device and the control method thereof according to the present disclosure can prevent the occurrence of surges and breakdowns.

[0010] FIG. 1 is a diagram illustrating a configuration of power conversion device 1 according to a first embodiment. FIG. 2 is a diagram illustrating a configuration of cell 10 according to the first embodiment. FIG. 3 is a diagram illustrating a function of control circuit 50 according to the first embodiment. FIG. 4 is a diagram illustrating a state of cell 10 according to the first embodiment. FIG. 5 is a diagram illustrating combinations of conduction states of semiconductor switch elements Q1 to Q4 according to the first embodiment. FIG. 6 is a diagram illustrating timing for switching the state of cell 10 according to the first embodiment. FIG. 7 is a diagram illustrating states of cells 10A and 10B according to a comparative example. FIG. 8 is a diagram illustrating states of cells 10A and 10B according to the first embodiment. FIG. 9 is a flowchart illustrating cell selection processing by control circuit 50 according to the first embodiment. FIG. 10 is a diagram illustrating function of control circuit 51 according to a second embodiment. FIG. 11 is a diagram illustrating a cell switching procedure. FIG. 12 is a flowchart illustrating cell selection processing by control circuit 50 according to the second embodiment. FIG. 13 is a flowchart illustrating cell classification according to the second embodiment. FIG. 14 is a flowchart illustrating cell classification according to the third embodiment. FIG. 15 is a diagram illustrating capacitor voltages of cells according to a comparative example and the third embodiment.

[0011] First Embodiment Fig. 1 is a diagram illustrating a configuration of a power conversion device 1 according to a first embodiment.

[0012] 1, an example of a power conversion device 1 according to the first embodiment is provided with arm units 2A to 2C (hereinafter also collectively referred to as arm unit 2) for each of the three phases of a power transmission line 3, and a control circuit 50 that controls arm units 2A to 2C. The configuration of arm unit 2 for each phase is similar, so detailed description thereof will not be repeated. In this example, the configuration of arm unit 2A will be described as an example. Also, a case where control circuit 50 controls arm unit 2A will be described as an example.

[0013] The arm section 2A includes a plurality of cells 10A to 10C (collectively referred to as cells 10) and an interconnection reactor 11.

[0014] The plurality of cells 10A to 10C are connected in series to each other and to an interconnection reactor 11.

[0015] The configuration of each cell 10 is similar. Fig. 2 is a diagram illustrating the configuration of cell 10 according to the first embodiment.

[0016] Referring to FIG. 2, cell 10 includes a plurality of semiconductor switch elements Q1 to Q4, diodes Q1A to Q4A connected in parallel in the opposite directions corresponding to the plurality of semiconductor switch elements Q1 to Q4, a capacitor 101 which is a storage element, and a voltage detector 104 which detects the voltage of capacitor 101.

[0017] Semiconductor switch elements Q1 and Q2 are connected in series between nodes N1 and N2. Semiconductor switch elements Q3 and Q4 are connected in series between nodes N1 and N2. Semiconductor switch elements Q1 and Q2, semiconductor switch elements Q3 and Q4, and capacitor 101 are connected in parallel between nodes N1 and N2. In addition, voltage detector 104 that detects the voltage of capacitor 101 is connected between nodes N1 and N2.

[0018] A node Np, which is a connection node between the semiconductor switch elements Q1 and Q2, is connected to a node Nn of another cell 10 on the upstream side connected in series.

[0019] A node Nn, which is a connection node between the semiconductor switch element Q3 and the semiconductor switch element Q4, is connected to a node Np of another downstream cell 10 connected in series.

[0020] The node Np of the most upstream cell 10 is connected to an interconnection reactor 11. This configuration is sometimes called an MMC (Modular Multilevel Converter), and requires balance control to equalize the voltages of the capacitors of each cell in addition to control for exchanging power with the power grid.

[0021] 3 is a diagram illustrating the function of control circuit 50 according to embodiment 1. Referring to FIG. 3, control circuit 50 includes a switching control unit 200 that controls ON / OFF of semiconductor switch elements Q1 to Q4 of cells 10A to 10C, a capacitor voltage acquisition unit 201 that acquires the capacitor voltages of cells 10A to 10C, and a state duration counting unit 202 that counts the duration of each state of cells 10A to 10C.

[0022] The capacitor voltage acquisition unit 201 acquires the voltage value of the capacitor 101 from the voltage detector 104 provided in each cell 10 .

[0023] When the state of each of the cells 10A to 10C changes, the state duration counting unit 202 counts the time that the changed state continues.

[0024] The switching control unit 200 controls the ON / OFF of the semiconductor switch elements Q1 to Q4 of the cells 10A to 10C at predetermined timings, as will be described later.

[0025] Specifically, the switching control unit 200 performs PWM control to control the ON / OFF of the semiconductor switch elements Q1 to Q4 of the cells 10A to 10C based on the capacitor voltage of each cell 10A to 10C acquired by the capacitor voltage acquisition unit 201, the time that the state of each cell 10A to 10C continues in the state duration counting unit 202, and the magnitude relationship between the command value and the carrier.

[0026] Fig. 4 is a diagram illustrating states of cell 10 according to the first embodiment. Fig. 5 is a diagram illustrating combinations of the conduction states of semiconductor switch elements Q1 to Q4 according to the first embodiment.

[0027] Referring to Figures 4 and 5, when semiconductor switch elements Q1 and Q4 are ON (conducting) and semiconductor switch elements Q2 and Q3 are OFF (non-conducting), cell 10 is in a positive output state in which the positive voltage of capacitor 101 is applied to the output terminal of the cell.

[0028] Furthermore, when the semiconductor switch elements Q1 and Q3 are ON (conducting) and the semiconductor switch elements Q2 and Q4 are OFF (non-conducting), the cell 10 is in a zero output state (first) in which it outputs zero voltage.

[0029] When the semiconductor switch elements Q2 and Q4 are ON (conducting) and the semiconductor switch elements Q1 and Q3 are OFF (non-conducting), the cell 10 is in a zero output state (part 2) in which it outputs zero voltage.

[0030] When the semiconductor switch elements Q2 and Q3 are ON (conducting) and the semiconductor switch elements Q1 and Q4 are OFF (non-conducting), the cell 10 is in a negative output state where a negative voltage is applied.

[0031] As shown in FIG. 4, by switching the semiconductor switch elements Q1 to Q4 ON ​​and OFF according to FIG. 5, it is possible to sequentially switch between a positive output state, a negative output state, and a zero output state in which zero voltage is output.

[0032] 4, there are two types of zero output states in which zero voltage is output. In the following description, when simply referring to a zero output state, it can refer to either of the two types of states.

[0033] FIG. 6 is a diagram illustrating timing for switching the state of cell 10 according to the first embodiment.

[0034] A case where level-shift PWM control is applied will be described with reference to FIG. 6 . Specifically, referring to FIG. 6A , the switching control unit 200 performs PWM control based on the magnitude relationship between the command value and the carrier. Specifically, the timing for switching the state of the cells 10 is determined by the magnitude relationship between multiple triangular wave carriers and the command value, as shown on the horizontal axis and the vertical axis, which represents time and voltage or a dimensionless quantity, respectively. That is, when the command value calculated based on the output current or capacitor voltage is positive, the switching control unit 200 determines to switch the number of cells 10 that exceed the carrier value to the positive output state. On the other hand, when the command value is negative, the switching control unit 200 determines to switch the number of cells 10 that fall below the carrier value to the negative output state. Then, depending on the capacitor voltage, the positive or negative command value, and the direction of the current, it determines which cells 10 should be placed in the output state or the zero output state. In this example, of the carriers CA to CD, carriers CA and CB are located on the positive side, and carriers CC and CD are located on the negative side. Carriers CA and CB are always in the range of 0 or more, and carriers CC and CD are always in the range of 0 or less.

[0035] The waveforms of carriers CA to CD in this example are merely an example and may be other waveforms. Also, carriers CC and CD may have waveforms that are line-symmetrical to carriers CA and CB with respect to the 0 line.

[0036] Referring to FIG. 6B, the cell output state based on the relationship between the command value and the carrier will be described.

[0037] When the command value is greater than carrier CA, two cells in a positive output state are selected from among cells 10A to 10C. When the command value is between carrier CA and carrier CB, one cell in a positive output state is selected from among cells 10A to 10C. When the command value is between carrier CB and carrier CC, all cells 10A to 10C are set to the zero state. When the command value is between carrier CC and carrier CD, one cell in a negative output state is selected from among cells 10A to 10C. When the command value is less than carrier CD, two cells in a negative output state are selected from among cells 10A to 10C.

[0038] In order to make the voltages of the capacitors 101 of the cells 10 as uniform as possible, there is a method of selecting the cells whose states are to be switched depending on the magnitude of the voltage of the capacitors 101.

[0039] This method is sometimes called a sorting method. For example, if a current flows to discharge the capacitor 101 when the cell 10 is switched from a zero output state to a positive output state, the switching control unit 200 can switch the multiple cells 10 to positive output in order, starting with the cell 10 with the highest capacitor voltage, thereby achieving a good balance of the capacitor voltages of the cells 10.

[0040] When a current flows to charge the capacitor 101 when the cell 10 is switched from a zero output state to a positive output state, the switching control unit 200 switches the cells 10 to positive output in order starting with the cell 10 with the lowest capacitor voltage, thereby achieving a good balance of the capacitor voltages of each cell 10.

[0041] When switching the cells 10 from a positive output state to a zero output state while current is flowing in a discharging state, the switching control unit 200 switches the cells 10 to the zero output state in order starting with the cell with the lowest capacitor voltage, thereby achieving a good balance of the capacitor voltages of each cell 10.

[0042] When switching the cells 10 from a positive output state to a zero output state while current is flowing in the charging direction, the switching control unit 200 switches the cells 10 to the zero output state in order starting with the cells 10 with the highest capacitor voltage, thereby achieving a good balance of the capacitor voltages of the cells 10.

[0043] Similarly, when switching between the zero output state and the negative output state, the cells 10 can be selected in descending or ascending order according to the magnitude of the capacitor voltage.

[0044] Next, we will explain this in detail using an example. Consider a case in which multiple cells 10A to 10C are connected in series in a certain phase in Figure 1, and the relationship between the magnitude of the carrier and the command value causes the state to fluctuate between "all cells are in a zero output state" and "only one cell is in a positive output state."

[0045] At this time, considering the positive / negative command value and the direction of the current, we consider the case where the capacitor voltage of cell 10 in the positive output state is discharged, and explain the case where the capacitor voltage of cell 10A in the first stage is the highest and the capacitor voltage of cell 10B in the second stage is the next highest.

[0046] 7A and 7B are diagrams illustrating the states of cells 10A and 10B according to a comparative example, and show the relationship between the triangular wave carrier and the command value.

[0047] Here, if the time period during which "all cells are in the zero output state" is very short, cell 10A is switched to the zero output state for only a very short time.

[0048] FIG. 7B is a diagram illustrating the ON / OFF states of the semiconductor switch elements Q1 to Q4 according to the comparative example.

[0049] Referring to Figure 7(B), the ON and OFF states of each semiconductor switch element Q1 to Q4 of the first-stage cell 10A are shown when the state of the cell 10A changes, but the semiconductor switch elements Q2 and Q3 are in the ON state for only a very short time.

[0050] In this regard, bipolar semiconductor switching elements such as IGBTs switch between ON and OFF states by injecting or discharging minority carriers, but if the ON state is maintained for too short a time, i.e., if the amount of minority carriers injected is too small, the discharge of minority carriers will be completed instantaneously when the element is next switched to the OFF state. This will cause the electric field layer inside the semiconductor switching element to expand rapidly, resulting in a large voltage oscillation phenomenon and possibly damaging the element.

[0051] Therefore, the semiconductor switch elements Q2 and Q3 may not be in the ON state for a sufficient time, which may result in destruction of the semiconductor switch elements Q2 and Q3. The minimum value of the sufficient time that the semiconductor switch elements must be in the ON state is sometimes called the minimum ON time. The minimum ON time is determined based on, for example, the withstand voltage of the semiconductor switch elements or the upper limit of the switching frequency.

[0052] In the method according to the first embodiment, the cell 10 whose state is to be switched is selected based not only on the capacitor voltage but also on the duration of each state of each cell 10. That is, if a predetermined time has not elapsed since the first-stage cell 10A entered the zero-output state, switching of the state of the first-stage cell 10A is prohibited. Then, from among the cells excluding the first-stage cell 10A, the cell 10 whose state is to be switched is selected based on the magnitude of the capacitor voltage. Here, the predetermined time is a time determined based on the characteristics of the semiconductor switch elements constituting the cell (e.g., voltage rating, current rating, upper limit of switching frequency, etc.), and is, for example, several microseconds to several tens of microseconds. The predetermined time is longer than the minimum on-time and may be set to any value by the designer. After a predetermined time has elapsed since the first-stage cell 10A entered the zero-output state, the first-stage cell 10A again becomes a candidate for selection.

[0053] 8A and 8B are diagrams illustrating the states of cells 10A and 10B according to embodiment 1. Referring to Fig. 8A, the relationship between the triangular wave carrier and the command value is shown.

[0054] Here, consider the case where all cells go back and forth between a zero output state and only one cell goes back and forth between a positive output state and a zero output state.

[0055] As explained in the comparative example, cell 10A may be switched to the zero output state for a very short period of time, but if sufficient time has not passed since cell 10A in the first stage was in the zero output state, cell 10B in the second stage, which is the next best candidate, is switched to the positive output state.

[0056] After a predetermined time has elapsed, the first-stage cell 10A becomes a candidate for selection again, and in FIG. 8, the first-stage cell 10A is again switched to the positive output state.

[0057] FIG. 8B is a diagram illustrating the ON / OFF states of semiconductor switch elements Q1 to Q4 according to the first embodiment.

[0058] Referring to FIG. 8B, which shows the ON and OFF states of the semiconductor switches of the first-stage cells, it can be seen that the ON state can be avoided for only a very short time.

[0059] FIG. 9 is a flowchart illustrating a cell selection process by control circuit 50 according to the first embodiment.

[0060] Referring to FIG. 9, switching control unit 200 performs a process of comparing the carrier with the command value (step S1).

[0061] The switching control unit 200 calculates the number of cells whose states are to be changed according to the comparison process (step S2).

[0062] Next, the voltage of the capacitor 101 of each cell 10 is acquired (step S3). Specifically, the capacitor voltage acquisition unit 201 acquires the voltage of the capacitor 101 of each cell 10 and outputs it to the switching control unit 200.

[0063] The switching control unit 200 extracts candidates for cells that change state according to the acquired voltage of the capacitor 101 (step S4). Specifically, the switching control unit 200 extracts the cells 10 with high capacitor voltages as candidates.

[0064] Next, the duration of the state is acquired (step S5). Specifically, the state duration counting unit 202 counts the time that the state of each cell 10 continues, and outputs the count to the switching control unit 200.

[0065] Next, the switching control unit 200 determines the cell whose state is to be changed (step S6). Specifically, as described above, if a predetermined time has elapsed since the state was changed, the cell 10 with the highest priority from among the extracted cell candidates is determined. On the other hand, if a predetermined time has not elapsed since the state was changed, the cell with the next highest priority is determined as the cell whose state is to be changed. For the determined cell, the ON / OFF states of the semiconductor switch elements Q1 to Q4 are controlled according to the states described in FIGS. 4 and 5.

[0066] Next, it is determined whether the processing has been completed (step S7). If it is determined in step S7 that the processing has been completed (YES in step S7), the processing is terminated (END).

[0067] On the other hand, if it is determined in step S7 that the process has not been completed (NO in step S7), the process returns to step S1 and the above process is repeated. This process is executed at predetermined intervals.

[0068] Although an example of the operation of the present invention has been described above, the number of cells and their states are not limited. While the circuit diagram in FIG. 1 shows a star-type connection, a delta-type connection is also possible, as is a double-star connection in which two star-type connections are connected. Furthermore, the system may be configured with a single cell instead of multiple cells, and switching of the states of all cells may be prohibited until the cell state duration has elapsed for a predetermined time. Furthermore, a transformer may be installed instead of the interconnection reactor 11.

[0069] Although the configuration of the cell 10 in FIG. 2 is described as a case where the cell is configured in a full-bridge configuration, a half-bridge configuration in which the number of semiconductor switch elements is reduced may also be used, and the semiconductor switch elements may be configured using not only IGBTs but also other conceivable elements such as GCTs and MOSFETs.

[0070] Also, a storage battery may be installed instead of the capacitor 101. Also, regarding the level shift PWM control in Figure 6, the carrier is level shifted, but the method is not limited to this. All figures are examples and do not limit the configuration, components, or method.

[0071] Second Embodiment Fig. 10 is a diagram illustrating the function of a control circuit 51 according to a second embodiment.

[0072] 10, control circuit 51 further includes a state switching number counting unit 203 and a classification unit 204 in comparison with control circuit 50.

[0073] The state switching counting unit 203 counts the number of times the state is switched for each cell 10 .

[0074] The classification unit 204 classifies the plurality of cells into groups for which state switching is to be performed preferentially based on the number of state switching times counted by the state switching number counting unit 203 .

[0075] In the second embodiment, a case will be described in which some of the cells among a plurality of cells have different characteristics.

[0076] If the characteristics of the cells are different, the loss of the cells will increase, and the cells will generate heat and become hotter, which may shorten the lifespan of the cells.

[0077] For example, consider a case where an arm section 2 corresponding to a certain phase has a plurality of cells 10 and the capacitance of the capacitor 101 of the cell 10 in the first stage is smaller than the capacitors 101 of the other cells 10.

[0078] In this case, since the capacitance of the capacitor 101 of the first-stage cell 10 is small, even if the same current flows through the capacitor 101, the capacitor voltage of the first-stage cell changes more than the capacitor voltages of the other cells 10. Therefore, the number of times the first-stage cell 10 is selected increases in order to equalize the capacitor voltages.

[0079] That is, the number of times that the semiconductor switch element of the first-stage cell 10 switches between the ON state and the OFF state increases, which increases switching loss.

[0080] This may cause the first-stage cells 10 to become hot, shortening their lifespan. The cells whose states are switched are selected mainly in descending or ascending order of the cell capacitor voltages, but the method according to the second embodiment suppresses an increase in the number of switching times of some of the cells 10.

[0081] Specifically, the cells 10 whose states are to be switched are selected not only based on the magnitude of the capacitor voltage but also on the number of times the states of each cell 10 are switched. That is, the number of times the states of each cell are switched is counted at each predetermined cycle, and cells that have switched the states a predetermined number of times or more are prioritized for selection.

[0082] A specific example will be given below, taking the case where there are four cells 10A to 10D in a certain phase as an example.

[0083] 11 is a diagram illustrating the cell switching procedure, which will be described below with reference to the case where, for example, a current flows so as to be discharged from a capacitor when switching from a zero output state to a positive output state.

[0084] 11A, in the switching order according to the comparative example, the cell 10A is selected in order from the cell with the highest capacitor voltage and switched to the positive output state. In this case, the number of switching times of the cell 10A is not taken into consideration, and the cell 10 to be switched to the positive output state is determined simply by the magnitude of the capacitor voltage. Therefore, there is a possibility that some cells 10 will be switched more times than other cells 10.

[0085] 11B, the switching order according to the second embodiment counts the number of switching times of the cells at predetermined time intervals, and prioritizes the cells with a relatively large number of switching times. In this case, the case where the number of switching times of cells 10B and 10C is greater than that of cells 10A and 10D and therefore the cells are prioritized in the selection order will be described.

[0086] Here, cells 10B and 10C are called a subordinate group because they are subordinated in selection, while cells 10A and 10D are called a priority group.

[0087] First, cells 10 are selected from the priority group in descending order of capacitor voltage and switched to the positive output state. After that, if more cells 10 are needed to be switched to the positive output state, cells 10 are selected from the subordinate group in descending order of capacitor voltage. In this way, cells 10B and 10C, which have a relatively high number of switching times, are not preferentially selected regardless of the magnitude of their capacitor voltages, thereby reducing the number of switching times.

[0088] It is effective to compare the number of switching times with a threshold value in order to classify the cells into the priority group and the subordinate group. Fig. 12 is a flow diagram illustrating the cell selection process of control circuit 50 according to the second embodiment.

[0089] Referring to FIG. 12, the flow differs from that of FIG. 9 in that step S4 is replaced with step S4A.

[0090] Specifically, the switching control unit 200 extracts candidates for cells whose states are to be changed from the priority group according to the acquired voltage of the capacitor 101 (step S4A). Specifically, the cell 10 with a high capacitor voltage is extracted as a candidate from the pre-classified priority group. If a candidate cannot be extracted from the priority group, the cell 10 is extracted from the subordinate group.

[0091] The subsequent processing is the same as that described in the flowchart of FIG. 9, and therefore detailed description thereof will not be repeated.

[0092] 13 is a flow diagram illustrating cell classification according to embodiment 2. Referring to FIG. 13, state switching counting unit 203 counts the number of state switching times N1 to Nk of the first to kth cells (step S10). Next, classification unit 204 determines whether a predetermined period has elapsed (step S11).

[0093] In step S11, if the classification unit 204 determines that the predetermined period has not elapsed (NO in step S11), the process returns to step S10 and the counting continues.

[0094] On the other hand, if the classification unit 204 determines in step S11 that the predetermined period has elapsed (YES in step S11), it calculates the average value Navr of the number of state switching times N1 to Nk (step S12). Specifically, the classification unit 204 calculates the average value Navr of the number of state switching times N1 to Nk counted by the number of state switching times counting unit 203.

[0095] Next, the classification unit 204 calculates a threshold value Nth (step S13). The threshold value Nth is calculated by Nvar×α (α>1).

[0096] Next, the classification unit 204 sets an initial value i = 1. Next, the classification unit 204 determines whether the number of state switching times Ni is greater than a threshold value Nth (step S15).

[0097] In step S15, if the classification unit 204 determines that the number of state switching times Ni is greater than the threshold value Nth, it sets the i-th cell to the subordinate group (step S16).

[0098] Next, the classification unit 204 sets i=i+1 (step S18). On the other hand, if the classification unit 204 determines in step S15 that the number of state switching times Ni is smaller than the threshold value Nth, it sets the i-th cell to the priority group (step S16).

[0099] Next, the classification unit 204 proceeds to step S18. Next, the classification unit 204 determines whether the condition i>k is satisfied (step S19).

[0100] In step S19, if the classification unit 204 determines that the condition i>k is satisfied (YES in step S19), the process proceeds to the next step S20.

[0101] In step S20, the classification unit 204 instructs the state switching count unit 203 to reset the count, and the process returns to step S10.

[0102] On the other hand, if the classification unit 204 determines in step S19 that the condition i>k is not satisfied (NO in step S19), the process returns to step S15 and the above processing is repeated.

[0103] Through this process, the classification unit 204 sets cells with a state switching count exceeding the threshold to a subordinate group, and sets cells with a state switching count below the threshold to a prioritized group.

[0104] The above cell is determined according to the priority group and the subordinate group. The above operation is repeated at predetermined intervals.

[0105] As described above, in the case of a cell that would be switched over relatively frequently in the conventional method, the number of times of switching can be reduced by lowering the selection order in the present disclosure.

[0106] In the second embodiment, the cell selection order was explained taking into account the number of switching times, but using this method may make it difficult to balance the capacitor voltages. In the third embodiment, a method for classifying cells into a priority group and a subordinate group that further balances the capacitor voltages will be explained.

[0107] Fig. 14 is a flow diagram illustrating cell classification according to embodiment 3. Referring to Fig. 14, classification unit 204 detects capacitor voltages Vdc1 to Vdck of the cells and calculates an average value Vavr (step S30).

[0108] Next, the first threshold value Vthu (=Vavr×(1+β)) and the second threshold value Vthl (=Vavr×(1−β)) are calculated (step S31). (1>β>0) Next, the classification unit 204 sets an initial value j=1.

[0109] Next, the classification unit 204 determines whether the capacitor voltage Vdcj is between the first threshold value Vthu and the second threshold value Vthl (step S33).

[0110] If the classification unit 204 determines in step S33 that the capacitor voltage Vdcj is between the first threshold value Vthu and the second threshold value Vthl (YES in step S33), the jth cell maintains the current group (step S34). That is, if the jth cell is in the inferior group, the jth cell maintains the inferior group. If the jth cell is in the priority group, the jth cell maintains the priority group.

[0111] Next, the classification unit 204 sets j=j+1 (step S35). On the other hand, if the classification unit 204 determines in step S33 that the capacitor voltage Vdcj is not between the first threshold value Vthu and the second threshold value Vthl (NO in step S33), it sets the j-th cell to the priority group (step S36). Then, the process proceeds to step S35.

[0112] Next, the classification unit 204 determines whether the condition j>k is satisfied (step S37). If the classification unit 204 determines that the condition j>k is satisfied (YES in step S37), the processing ends (END).

[0113] On the other hand, if the classification unit 204 determines in step S37 that the condition j>k is not satisfied (NO in step S37), the process returns to step S33 and the above processing is repeated.

[0114] This process enables the sorting unit 204 to re-sort cells that have been sorted according to their capacitor voltages.

[0115] The classification unit 204 executes the process at predetermined time intervals. Specifically, the classification unit 204 repeatedly executes the process at a timing earlier than the initial classification.

[0116] If the capacitor voltage is within the range of Vthl to Vthu, the group to which it belongs remains the same. That is, the cells in the priority group are classified into the priority group, and the cells in the inferior group are classified into the inferior group. The above operation is repeated at predetermined intervals.

[0117] As described above, by allowing only cells whose capacitor voltages are within a predetermined range to be classified into the inferior group, it is possible to balance the capacitor voltages and equalize the number of switching times.

[0118] FIG. 15 is a diagram illustrating the capacitor voltage of the cell according to the comparative example and the third embodiment.

[0119] Referring to FIG. 15A, the capacitor voltage of the cell according to the comparative example shows a case where variations occur.

[0120] On the other hand, referring to FIG. 15B, variations in the capacitor voltages of the cells according to the third embodiment are suppressed.

[0121] The embodiments disclosed herein should be considered to be illustrative in all respects and not restrictive. Furthermore, it goes without saying that there is no problem in suitably combining a plurality of embodiments, and it is desirable to enhance the effects of each embodiment for efficient and economical use.

[0122] The scope of the present disclosure is defined by the claims, rather than the above description, and is intended to include all modifications within the meaning and scope of the claims.

[0123] 1 Power conversion device, 2, 2A to 2C Arm section, 3 Transmission line, 10, 10A, 10B, 10C, 10D Cell, 11 Interconnection reactor, 50, 51 Control circuit, 101 Capacitor, 104 Voltage detector, 200 Switching control section, 201 Capacitor voltage acquisition section, 202 State duration counting section, 203 State switching counting section, 204 Classification section.

Claims

1. An arm portion; a control device for controlling the arm unit, the arm portion includes a plurality of cells connected in series, The plurality of cells include: A pair of connection terminals; a plurality of semiconductor switch elements; a storage element connected in parallel to the plurality of semiconductor switch elements; a voltage detector for detecting a voltage of the storage element; The control device corresponding to each of the plurality of cells, the states of the plurality of semiconductor switch elements included in the corresponding cell can be switched to one of the states including at least a state in which the connection terminal of the corresponding cell outputs at least one of a positive and a negative voltage, and a state in which the connection terminals are electrically connected; At each predetermined timing, one of the plurality of cells is selected to switch states based on the voltages of the storage elements of the plurality of cells and the durations of the states of the plurality of cells; switching the states of the plurality of semiconductor switch elements included in the selected cell; A power conversion device that selects, at each predetermined timing, one of the plurality of cells to switch states based on the voltage of the storage element that each of the plurality of cells has, the duration of the states of the plurality of cells, and the number of times the states of the plurality of cells are switched.

2. The power conversion device according to claim 1 , wherein the control device prohibits the selected cell from switching to another state until a predetermined time has elapsed since the state of the selected cell was switched.

3. The control device Count the number of times each cell switches states for each predetermined period, classifying the cells among the plurality of cells whose number of state switching times is equal to or less than a predetermined value into a first cell group, and the cells among the plurality of cells whose number of state switching times is greater than a predetermined value into a second cell group; The power conversion device according to claim 1 , wherein the cells that switch states at the predetermined timing are preferentially selected from the first cell group.

4. 4. The power conversion device according to claim 3, wherein the control device classifies, among the plurality of cells, cells whose state has been switched a number of times exceeding a predetermined value and whose storage element voltage is within a predetermined range into a second cell group.

5. A control method for a power conversion device including an arm section, comprising: the arm portion includes a plurality of cells connected in series, each of the plurality of cells including a pair of connection terminals, a plurality of semiconductor switch elements, a storage element connected in parallel to the plurality of semiconductor switch elements, and a voltage detector that detects a voltage of the storage element; At each predetermined timing, selecting one of the plurality of cells to switch states based on the voltage of a storage element of each of the plurality of cells and the duration of the states of the plurality of cells; switching the states of the plurality of semiconductor switch elements included in the selected cell to one of the states including at least a state in which the connection terminals of the cell output at least one of a positive and a negative voltage, and a state in which the connection terminals are electrically connected; A control method for a power conversion device, comprising a step of selecting, at each predetermined timing, one of the plurality of cells to switch states based on the voltage of a storage element possessed by each of the plurality of cells, the duration of the states of the plurality of cells, and the number of times the states of the plurality of cells are switched.