Detection apparatus and wearable device

Abstract

Provided are a detection apparatus and a wearable device, which are capable of suppressing periodic body movement noise when acquiring biometric information. First frequency domain data for each pixel is generated on the basis of detection values for a plurality of pixels acquired in time series. The maximum intensity among the signal intensities corresponding to the respective frequencies of the first frequency domain data is defined as a first signal intensity for each pixel. A domain in which the first signal intensity is equal to or greater than a prescribed value within a sensor domain is defined as a first domain. On the basis of the first frequency domain data in the pixels in the outer peripheral portion of the first domain, second frequency domain data, in which a prescribed frequency range of the first frequency domain data in all the pixels in the first domain is masked, is generated. The maximum intensity among the signal intensities corresponding to the respective frequencies of the second frequency domain data is defined as a second signal intensity for each pixel. When the area of a second domain, in which the second signal intensity is equal to or greater than a prescribed value, is not less than a prescribed value, the biometric information is acquired on the basis of the second frequency domain data. When the area of the second domain is less than the prescribed value, the biometric information is acquired on the basis of the first frequency domain data.

Description

Detection apparatus and wearable device

[0001] The present invention relates to a detection apparatus and a wearable device.

[0002] Patent Document 1 describes an optical sensor in which a plurality of photoelectric conversion elements such as photodiodes are arranged on a semiconductor substrate. The optical sensor can detect biological information by detecting changes in the signal output from the photoelectric conversion elements depending on the amount of light irradiated.

[0003] US Patent Application Publication No. 2018 / 0012069

[0004] When a detection device is attached to a human body to acquire a pulse wave, periodic body movement noise generated by human body movement such as walking may be erroneously determined as a pulse wave.

[0005] The present disclosure aims to provide a detection apparatus and a wearable device that can suppress periodic body movement noise when acquiring biological information.

[0006] A detection device according to one aspect of the present disclosure includes a sensor area having a plurality of pixels arranged in a plane, a light source that irradiates the sensor area with light, and a detection circuit that acquires periodically fluctuating biological information of a subject based on data acquired from the sensor area, wherein the detection circuit converts detection values ​​for each of the plurality of pixels acquired in time series into signal intensities for each frequency to generate first frequency domain data for each of the pixels, defines a maximum intensity of the signal intensities corresponding to each frequency of the first frequency domain data as a first signal intensity for each pixel, and defines an area within the sensor area where the first signal intensity is equal to or greater than a predetermined value as a first area. Based on first frequency domain data for pixels on the periphery of the first region, second frequency domain data is generated by masking a predetermined frequency range of the first frequency domain data for all pixels in the first region, the maximum strength of the signal strengths corresponding to each frequency of the second frequency domain data is set as the second signal strength for each pixel, and a region within the sensor region where the second signal strength is equal to or greater than a predetermined value is set as a second region, and if the area of ​​the second region is equal to or greater than the predetermined value, biometric information is acquired based on the second frequency domain data, and if the area of ​​the second region is less than the predetermined value, biometric information is acquired based on the first frequency domain data.

[0007] A wearable device according to one aspect of the present disclosure includes the above-described detection device and has a ring-like shape that can be attached to and detached from the human body.

[0008] FIG. 1 is a plan view showing a detection device according to an embodiment. FIG. 2 is a block diagram showing an example of the configuration of the detection device according to an embodiment. FIG. 3 is a circuit diagram showing the detection device according to an embodiment. FIG. 4 is a circuit diagram showing a plurality of pixels. FIG. 5 is a schematic partial cross-sectional view of a photosensor according to an embodiment. FIG. 6 is a timing waveform diagram showing an example of operation of the detection device according to an embodiment in one frame period. FIG. 7 is a timing waveform diagram showing an example of operation of the detection device according to an embodiment in a reset period. FIG. 8 is a timing waveform diagram showing an example of operation of the detection device according to an embodiment in a readout period. FIG. 9 is a timing waveform diagram showing an example of operation of a drive period of one gate line included in the readout period in FIG. 6. FIG. 10 is an explanatory diagram illustrating the relationship between driving of a sensor region of the detection device according to an embodiment and the lighting operation of a light source. FIG. 11 is a schematic diagram showing a first application example of the detection device according to an embodiment. FIG. 12 is a schematic diagram showing a second application example of the detection device according to an embodiment. FIG. 13 is a flowchart showing an example of a detection process flow in the detection device according to an embodiment. FIG. 14 is a sub-flowchart showing an example of a raw data acquisition process. FIG. 15 is a diagram showing detection values ​​for F frames at each pixel in a detection region. FIG. 16 is a sub-flowchart showing an example of a first image generation process. FIG. 17 is a sub-flowchart showing an example of a first signal intensity extraction process. FIG. 18 is a diagram showing an example of time domain data. FIG. 19 is a diagram showing an example of frequency domain data. FIG. 20 is a sub-flowchart showing an example of a binarization process in the first image generation process. FIG. 21 is a diagram showing a specific example of an image obtained by visualizing a first binary value for each pixel. FIG. 22 is a sub-flowchart showing an example of a filter generation process. FIG. 23 is a sub-flowchart showing an example of an edge extraction process. FIG. 24 is a diagram showing a specific example of an image obtained by visualizing a second binary value for each pixel. FIG. 25 is a sub-flowchart showing an example of an averaging process. FIG. 26 is a diagram showing an example of an average value of signal intensities of multiple pixels in the image shown in FIG. 24. FIG. 27 is a diagram showing an example of a filter value. FIG. 28 is a sub-flowchart showing an example of a second image generation process. FIG. 29 is a sub-flowchart showing an example of a second signal intensity calculation process.FIG. 30 is a diagram showing an example of second frequency domain data. FIG. 31 is a schematic diagram showing the positional relationship between a pulse wave component detection region and a body movement noise component detection region in a sensor region. FIG. 32 is a sub-flowchart showing an example of binarization processing in the second image generation processing. FIG. 33 is a diagram showing a specific example of an image obtained by visualizing third binary values ​​for each pixel. FIG. 34 is a sub-flowchart showing an example of pulse wave generation processing. FIG. 35 is a sub-flowchart showing an example of first pulse wave generation processing. FIG. 36 is a sub-flowchart showing an example of second pulse wave generation processing. FIG. 37 is a diagram showing an example of first frequency domain data when the time domain data does not contain a periodic noise component such as body movement noise. FIG. 38 is a diagram showing an example of second frequency domain data when the time domain data does not contain a periodic noise component such as body movement noise.

[0009] Modes (embodiments) for carrying out the present invention will be described in detail with reference to the drawings. Note that the present invention is not limited to the contents described in the following embodiments. Furthermore, the components described below include those that can be easily imagined by a person skilled in the art and those that are substantially identical. Furthermore, the components described below can be combined as appropriate. Furthermore, the disclosure is merely an example, and appropriate modifications that a person skilled in the art can easily conceive while maintaining the gist of the invention are naturally included within the scope of the present invention. Furthermore, for clarity of explanation, the drawings may show the width, thickness, shape, etc. of each part schematically compared to the actual embodiment. However, these are merely examples and are not intended to limit the interpretation of the present invention. Furthermore, in this specification and each figure, elements similar to those described above with reference to the previous figures may be designated by the same reference numerals, and detailed descriptions may be omitted as appropriate.

[0010] 1 is a plan view showing a detection device according to an embodiment. In the present disclosure, the detection device 1 is configured as a detection device that is worn on, for example, a finger or wrist of a subject and detects the subject's pulse wave as biological information.

[0011] As shown in FIG. 1, the detection device 1 includes a sensor substrate 21, a sensor region 10, a gate line driving circuit 15, a signal line selection circuit 16, an AFE (Analog Front End) circuit 48, a control circuit 122, a power supply circuit 123, a first light source 61, and a second light source 62.

[0012] The detection device 1 is electrically connected to a host. The host is, for example, a higher-level control device of an apparatus (not shown) to which the detection device 1 is applied. The detection device 1 according to the first embodiment transmits acquired biological information to the host via the output circuit 126.

[0013] A control board 121 is electrically connected to the sensor substrate 21 via a flexible printed circuit board 71. The flexible printed circuit board 71 is provided with an AFE circuit 48. The control board 121 is provided with a control circuit 122, a power supply circuit 123, and an output circuit 126.

[0014] The control circuit 122 is, for example, a control integrated circuit (IC) that outputs a logic control signal, or may be, for example, a programmable logic device (PLD) such as a field programmable gate array (FPGA).

[0015] The control circuit 122 supplies control signals to the sensor area 10, the gate line driving circuit 15, and the signal line selection circuit 16 to control the detection operation of the sensor area 10. The control circuit 122 also supplies control signals to the first light source 61 and the second light source 62 to control whether the first light source 61 and the second light source 62 are turned on or off.

[0016] The power supply circuit 123 supplies voltage signals such as a sensor power supply potential VDDSNS (see FIG. 4) to the sensor region 10, the gate line driving circuit 15, and the signal line selection circuit 16. The power supply circuit 123 also supplies a power supply voltage to the first light source 61 and the second light source 62.

[0017] The output circuit 126 is, for example, a USB controller IC, and controls communication between the control circuit 122 and the host.

[0018] The sensor substrate 21 has a detection area AA and a peripheral area GA. The detection area AA is an area in which a plurality of optical sensors PD (see FIG. 4 ) included in the sensor area 10 are arranged in a matrix. The peripheral area GA is an area between the outer periphery of the detection area AA and the edge of the sensor substrate 21, and is an area in which no optical sensors PD are provided.

[0019] The gate line driving circuit 15 and the signal line selection circuit 16 are provided in the peripheral area GA. Specifically, the gate line driving circuit 15 is provided in a region of the peripheral area GA extending along the second direction Dy. The signal line selection circuit 16 is provided in a region of the peripheral area GA extending along the first direction Dx, and is provided between the sensor area 10 and the AFE circuit 48.

[0020] The first direction Dx is a direction in a plane parallel to the sensor substrate 21. The second direction Dy is a direction in a plane parallel to the sensor substrate 21 and is a direction perpendicular to the first direction Dx. The second direction Dy may intersect with the first direction Dx without being perpendicular to it. The third direction Dz is a direction perpendicular to the first direction Dx and the second direction Dy and is a normal direction of the sensor substrate 21.

[0021] The plurality of first light sources 61 are provided on the first light source substrate 51 and arranged along the second direction Dy. The plurality of second light sources 62 are provided on the second light source substrate 52 and arranged along the second direction Dy. The first light source substrate 51 and the second light source substrate 52 are electrically connected to the control circuit 122 and the power supply circuit 123 via terminals 124 and 125 provided on the control board 121, respectively.

[0022] The plurality of first light sources 61 and the plurality of second light sources 62 may be, for example, inorganic light emitting diodes (LEDs) or organic light emitting diodes (OLEDs).

[0023] The first light source 61 and the second light source 62 emit at least one of visible light, near-infrared light, and infrared light. The first light source 61 and the second light source 62 may emit light of different wavelengths or may emit light of the same wavelength. Specifically, for example, in a configuration including at least the first light source 61 (or the second light source 62), the first light emitted by the first light source 61 (or the second light source 62) may be red light or infrared light, or may be blue light or green light. Alternatively, for example, in a configuration including the first light source 61 and the second light source 62, the first light emitted by the first light source 61 may be red light, and the second light emitted by the second light source 62 may be infrared light. The present disclosure is not limited by the emission colors of the first light source 61 and the second light source 62.

[0024] In the present disclosure, light emitted from the first light source 61 and the second light source 62 is reflected by or transmitted through the surface or interior of, for example, the subject's finger or wrist, and then enters the sensor area 10. This allows the sensor area 10 to detect the subject's pulse wave.

[0025] 2 is a block diagram showing an example of the configuration of the detection device according to the embodiment. As shown in FIG. 2, the detection device 1 further includes a detection control circuit 11 and a detection circuit 40.

[0026] The sensor region 10 has a plurality of optical sensors PD. The optical sensors PD of the sensor region 10 are organic photodiodes (OPDs), and output an electrical signal corresponding to irradiated light as a detection signal Vdet to the signal line selection circuit 16. The sensor region 10 also performs detection in accordance with a gate drive signal Vgcl supplied from the gate line drive circuit 15.

[0027] The detection control circuit 11 is a circuit that supplies control signals to the gate line drive circuit 15, the signal line selection circuit 16, and the detection circuit 40, respectively, and controls their operations. The detection control circuit 11 supplies various control signals, such as a start signal STV, a clock signal CK, and a reset signal RST1, to the gate line drive circuit 15. The detection control circuit 11 also supplies various control signals, such as a selection signal ASW, to the signal line selection circuit 16. The detection control circuit 11 also supplies various control signals to the first light source 61 and the second light source 62, and controls the lighting and non-lighting of each light source.

[0028] The gate line driving circuit 15 is a circuit that drives a plurality of gate lines GCL (see FIG. 3) based on various control signals. The gate line driving circuit 15 sequentially or simultaneously selects the plurality of gate lines GCL and supplies a gate driving signal Vgcl to the selected gate lines GCL. In this way, the gate line driving circuit 15 selects a plurality of photosensors PD connected to the gate lines GCL.

[0029] The signal line selection circuit 16 is a switch circuit that sequentially or simultaneously selects multiple signal lines SGL (see FIG. 3 ). The signal line selection circuit 16 is, for example, a multiplexer. The signal line selection circuit 16 electrically connects the selected signal line SGL to the AFE circuit 48 based on a selection signal ASW supplied from the detection control circuit 11. As a result, the signal line selection circuit 16 outputs a detection signal Vdet of the photosensor PD to the detection circuit 40.

[0030] The detection circuit 40 includes an AFE circuit 48, a signal processing circuit 44, a memory circuit 46, and a detection timing control circuit 47. The detection timing control circuit 47 controls the AFE circuit 48 and the signal processing circuit 44 to operate in synchronization with each other based on a control signal supplied from the detection control circuit 11.

[0031] The AFE circuit 48 detects, in time series, the detection signals of the optical sensors PD output from the sensor area 10. The AFE circuit 48 is, for example, an analog front-end IC.

[0032] The AFE circuit 48 is a signal processing circuit that has at least the functions of the detection signal amplifier circuit 42 and the A / D conversion circuit 43. The detection signal amplifier circuit 42 amplifies the detection signal Vdet. The A / D conversion circuit 43 converts the analog signal output from the detection signal amplifier circuit 42 into a digital signal at a predetermined sampling period.

[0033] In the present disclosure, the signal processing circuit 44 and the memory circuit 46 are included in the control circuit 122 .

[0034] The signal processing circuit 44 acquires the pulse wave of the subject based on the detection values ​​of the optical sensors PD output from the AFE circuit 48 .

[0035] The memory circuitry 46 temporarily stores the signals processed by the signal processing circuitry 44. The memory circuitry 46 may include, for example, a random access memory (RAM), a read-only memory (ROM), an electrically erasable programmable read-only memory (EEPROM), etc. The memory circuitry 46 may also be a register circuit, etc.

[0036] Next, an example of the circuit configuration of the detection device 1 will be described. Fig. 3 is a circuit diagram showing the detection device according to the embodiment. As shown in Fig. 3, the sensor area 10 has a plurality of pixels PAA arranged in a planar shape.

[0037] Specifically, the plurality of pixels PAA are arranged in a matrix, for example, aligned in the first direction Dx and the second direction Dy. However, the present invention is not limited to this, and the plurality of pixels PAA may be arranged in a staggered pattern in the detection area AA.

[0038] Each of the pixels PAA is provided with an optical sensor PD, which outputs an electric signal (electric potential) in response to light incident thereon.

[0039] The gate line GCL extends in a first direction Dx and is connected to a plurality of pixels PAA arranged in the first direction Dx. Furthermore, a plurality of gate lines GCL(1), GCL(2), ..., GCL(8) are arranged in a second direction Dy and are each connected to a gate line driving circuit 15. In the following description, when it is not necessary to distinguish between the plurality of gate lines GCL(1), GCL(2), ..., GCL(8), they will simply be referred to as gate lines GCL. Although FIG. 3 shows eight gate lines GCL for ease of explanation, this is merely an example, and M gate lines GCL (M is a natural number, for example, M=256) may also be arranged.

[0040] The signal line SGL extends in the second direction Dy and is connected to the photosensors PD of the plurality of pixels PAA arranged in the second direction Dy. The plurality of signal lines SGL(1), SGL(2), ..., SGL(12) are arranged in the first direction Dx and are each connected to the signal line selection circuit 16 and the reset circuit 17. In the following description, when it is not necessary to distinguish between the plurality of signal lines SGL(1), SGL(2), ..., SGL(12), they will simply be referred to as signal lines SGL.

[0041] For ease of understanding, 12 signal lines SGL are shown, but this is merely an example, and N signal lines SGL (N is a natural number, for example, N=252) may be arranged. In addition, in Fig. 3, the sensor region 10 is provided between the signal line selection circuit 16 and the reset circuit 17. However, the present invention is not limited to this, and the signal line selection circuit 16 and the reset circuit 17 may be connected to ends of the signal lines SGL in the same direction.

[0042] The gate line driving circuit 15 receives various control signals, such as a start signal STV, a clock signal CK, and a reset signal RST1, from the control circuit 122 (see FIG. 1 ). Based on the various control signals, the gate line driving circuit 15 sequentially selects multiple gate lines GCL(1), GCL(2), ..., GCL(8) in a time-division manner. The gate line driving circuit 15 supplies a gate driving signal Vgcl to the selected gate line GCL. As a result, the gate driving signal Vgcl is supplied to multiple first switching elements Tr connected to the gate line GCL, and multiple pixels PAA arranged in the first direction Dx are selected as detection targets.

[0043] The signal line selection circuit 16 has a plurality of selection signal lines Lsel, a plurality of output signal lines Lout, and a third switching element TrS. The plurality of third switching elements TrS are provided corresponding to the plurality of signal lines SGL, respectively. The six signal lines SGL(1), SGL(2), ..., SGL(6) are connected to a common output signal line Lout1. The six signal lines SGL(7), SGL(8), ..., SGL(12) are connected to a common output signal line Lout2. The output signal lines Lout1 and Lout2 are each connected to the AFE circuit 48.

[0044] Here, the signal lines SGL(1), SGL(2), ..., SGL(6) are defined as a first signal line block, and the signal lines SGL(7), SGL(8), ..., SGL(12) are defined as a second signal line block. The multiple selection signal lines Lsel are connected to the gates of the third switching elements TrS included in one signal line block. Furthermore, one selection signal line Lsel is connected to the gates of the third switching elements TrS of multiple signal line blocks.

[0045] Specifically, the selection signal lines Lsel1, Lsel2, ..., Lsel6 are connected to the third switching elements TrS corresponding to the signal lines SGL(1), SGL(2), ..., SGL(6), respectively. The selection signal line Lsel1 is connected to the third switching element TrS corresponding to the signal line SGL(1) and the third switching element TrS corresponding to the signal line SGL(7). The selection signal line Lsel2 is connected to the third switching element TrS corresponding to the signal line SGL(2) and the third switching element TrS corresponding to the signal line SGL(8).

[0046] The control circuit 122 (see FIG. 1) sequentially supplies the selection signal ASW to the selection signal line Lsel. As a result, the signal line selection circuit 16 sequentially selects the signal lines SGL in one signal line block in a time-division manner through the operation of the third switching element TrS. The signal line selection circuit 16 also selects one signal line SGL from each of the multiple signal line blocks. This configuration allows the detection device 1 to reduce the number of integrated circuits (ICs) including the AFE circuit 48 or the number of IC terminals.

[0047] 3, the reset circuit 17 has a reference signal line Lvr, a reset signal line Lrst, and fourth switching elements TrR. The fourth switching elements TrR are provided corresponding to the multiple signal lines SGL. The reference signal line Lvr is connected to one of the sources or drains of the multiple fourth switching elements TrR. The reset signal line Lrst is connected to the gates of the multiple fourth switching elements TrR.

[0048] The control circuit 122 supplies a reset signal RST2 to the reset signal line Lrst. This turns on the multiple fourth switching elements TrR, and the multiple signal lines SGL are electrically connected to the reference signal line Lvr. The power supply circuit 123 supplies a reference signal COM to the reference signal line Lvr. This causes the reference signal COM to be supplied to the capacitive elements Ca (see FIG. 4) included in the multiple pixels PAA.

[0049] FIG. 4 is a circuit diagram showing multiple pixels of a detection device according to an embodiment. FIG. 4 also shows the circuit configuration of an AFE circuit 48. As shown in FIG. 4, pixel PAA includes a photosensor PD, a capacitive element Ca, and a first switching element Tr1. The capacitive element Ca is a capacitance (sensor capacitance) formed in the photosensor PD and is equivalently connected in parallel with the photosensor PD. Furthermore, signal line capacitance Cc is a parasitic capacitance formed in the signal line SGL and is equivalently formed between the signal line SGL and one end of the capacitive element Ca and the anode of the photosensor PD.

[0050] 4 shows two gate lines GCL(m) and GCL(m+1) aligned in the second direction Dy among the multiple gate lines GCL. Also, two signal lines SGL(n) and SGL(n+1) aligned in the first direction Dx among the multiple signal lines SGL. The pixel PAA is an area surrounded by the gate lines GCL and the signal lines SGL.

[0051] The first switching element Tr is provided corresponding to the optical sensor PD. The first switching element Tr is configured by a thin film transistor, and in this example, is configured by an n-channel MOS (Metal Oxide Semiconductor) TFT (Thin Film Transistor).

[0052] The gates of the first switching elements Tr belonging to the pixels PAA aligned in the first direction Dx are connected to the gate line GCL, the sources of the first switching elements Tr belonging to the pixels PAA aligned in the second direction Dy are connected to the signal line SGL, and the drains of the first switching elements Tr are connected to the cathodes of the photosensors PD and the capacitive elements Ca.

[0053] A sensor power supply signal (potential) VDDSNS is supplied to the anode of the optical sensor PD from the power supply circuit 123. In addition, a reference signal COM, which becomes the initial potential of the signal line SGL and the capacitive element Ca, is supplied to the cathode of the optical sensor PD from the power supply circuit 123.

[0054] When light is irradiated onto pixel PAA, a current corresponding to the amount of light flows through photosensor PD, causing charge corresponding to the amount of light to accumulate in capacitance element Ca. When first switching element Tr is turned on, a current corresponding to the charge accumulated in capacitance element Ca flows through signal line SGL. Signal line SGL is connected to AFE circuit 48 via third switching element TrS of signal line selection circuit 16. This allows detection device 1 to detect a signal corresponding to the amount of light irradiated onto photosensor PD for each pixel PAA.

[0055] In the AFE circuit 48, the switch SSW is turned on during the readout period Pdet (see FIG. 6 ), and the AFE circuit 48 is connected to the signal line SGL. The detection signal amplifier circuit 42 of the AFE circuit 48 converts the current supplied from the signal line SGL into a voltage and amplifies it. A reference potential (Vref) having a fixed potential is input to the non-inverting input terminal (+) of the detection signal amplifier circuit 42, and the signal line SGL is connected to the inverting input terminal (−). In this embodiment, a signal identical to the reference signal COM is input as the reference potential (Vref) voltage. The detection signal amplifier circuit 42 also has a capacitance element Cb and a reset switch RSW. During the reset period Prst (see FIG. 6 ), the reset switch RSW is turned on, and the charge of the capacitance element Cb is reset.

[0056] Next, the configuration of the optical sensor PD will be described. Fig. 5 is a schematic partial cross-sectional view of the optical sensor according to the embodiment. The sensor region 10 of the detection device 1 includes a sensor substrate 21, a sensor structure 22, and a protective film 23. The sensor substrate 21 is an insulating substrate formed of, for example, a film-like resin.

[0057] The sensor structure 22 includes a TFT layer 221 , an anode electrode (lower electrode) 222 , a photosensor PD, and a cathode electrode (upper electrode) 226 .

[0058] Various wirings such as gate lines GCL and signal lines SGL are provided on the TFT layer 221. The sensor substrate 21 and the TFT layer 221 form a drive circuit that drives the sensor, and are also called a backplane.

[0059] The photosensor PD has an active layer 224, an electron transport layer (lower buffer layer) 223 provided between the active layer 224 and an anode electrode (lower electrode) 222, and a hole transport layer (upper buffer layer) 225 provided between the active layer 224 and a cathode electrode (upper electrode) 226. In other words, the electron transport layer (lower buffer layer) 223, the active layer 224, and the hole transport layer (upper buffer layer) 225 of the photosensor PD are stacked in this order in a direction perpendicular to the sensor substrate 21.

[0060] The characteristics (for example, voltage-current characteristics and resistance value) of the active layer 224 change depending on the light irradiated thereto. An organic material is used as the material of the active layer 224. Specifically, the active layer 224 has a bulk heterostructure in which a p-type organic semiconductor and an n-type organic semiconductor, an n-type fullerene derivative (PCBM), are mixed. For example, a low-molecular organic material, C ６０ (fullerene), PCBM (phenyl C61-butyric acid methyl ester), CuPc (copper phthalocyanine), F １６ CuPc (fluorinated copper phthalocyanine), rubrene (5,6,11,12-tetraphenyltetracene), PDI (a derivative of perylene), or the like can be used.

[0061] The active layer 224 can be formed by a vapor deposition (dry process) using these low molecular weight organic materials. In this case, the active layer 224 is formed by a vapor deposition (dry process) using, for example, CuPc and F １６ CuPc laminated film or rubrene and C ６０The active layer 224 may be a laminated film of the above-mentioned low molecular weight organic material and high molecular weight organic material. The active layer 224 may also be formed by a wet process. In this case, the active layer 224 is made of a material that combines the above-mentioned low molecular weight organic material and high molecular weight organic material. Examples of high molecular weight organic materials that can be used include P3HT (poly(3-hexylthiophene)) and F8BT (F8-alt-benzothiadiazole). The active layer 224 may be a film in which P3HT and PCBM are mixed, or a film in which F8BT and PDI are mixed.

[0062] The electron transport layer (lower buffer layer) 223 and the hole transport layer (upper buffer layer) 225 are provided to facilitate the electrons and holes generated in the active layer 224 reaching the anode electrode (lower electrode) 222 or the cathode electrode (upper electrode) 226. The electron transport layer (lower buffer layer) 223 is in direct contact with the anode electrode (lower electrode) 222. The active layer 224 is in direct contact with the electron transport layer (lower buffer layer) 223. The electron transport layer (lower buffer layer) 223 is made of ethoxylated polyethyleneimine (PEIE).

[0063] The hole transport layer (upper buffer layer) 225 is in direct contact with the active layer 224, and the cathode electrode (upper electrode) 226 is in direct contact with the hole transport layer (upper buffer layer) 225. The hole transport layer (upper buffer layer) 225 is a metal oxide layer. The metal oxide layer is made of tungsten oxide (WO ３ ), molybdenum oxide, etc. are used.

[0064] The materials and manufacturing methods of the electron transport layer (lower buffer layer) 223, the active layer 224, and the hole transport layer (upper buffer layer) 225 are merely examples, and other materials and manufacturing methods may be used.

[0065] The anode electrode (lower electrode) 222 and the cathode electrode (upper electrode) 226 face each other with the photosensor PD interposed therebetween. The cathode electrode (upper electrode) 226 is made of a light-transmitting conductive material such as indium tin oxide (ITO). The anode electrode (lower electrode) 222 is made of a metal material such as silver (Ag) or aluminum (Al). Alternatively, the anode electrode (lower electrode) 222 may be made of an alloy material containing at least one of these metal materials.

[0066] By controlling the film thickness of the anode electrode (lower electrode) 222, the anode electrode (lower electrode) 222 can be formed as a semi-transparent electrode having light transmittance. For example, the anode electrode (lower electrode) 222 can be formed of a 10 nm thick Ag thin film to have a light transmittance of about 60%. In this case, the photosensor PD can detect the first light LD irradiated from the first surface FD side, for example.

[0067] The protective film 23 is provided on the second surface FU to cover the cathode electrode (upper electrode) 226. The protective film 23 is a passivation film, and is provided to protect the photosensor PD.

[0068] 4 illustrates a configuration in which the sensor power supply signal VDDSNS is supplied from the power supply circuit 123 to the anode of the photosensor PD, and the reference signal COM, which serves as the initial potential of the signal line SGL and the capacitance element Ca, is supplied from the power supply circuit 123 to the cathode of the photosensor PD, but, for example, a configuration in which the sensor power supply signal VDDSNS is supplied from the power supply circuit 123 to the cathode of the photosensor PD, and the reference signal COM, which serves as the initial potential of the signal line SGL and the capacitance element Ca, is supplied from the power supply circuit 123 to the anode of the photosensor PD, may also be used. In this case, unlike the configuration described above, the photosensor PD has an active layer 224, a hole transport layer (lower buffer layer) 223 provided between the active layer 224 and the cathode electrode (lower electrode) 222, and an electron transport layer (upper buffer layer) 225 provided between the active layer 224 and the anode electrode (upper electrode) 226. In other words, the hole transport layer (lower buffer layer) 223 , the active layer 224 , and the electron transport layer (upper buffer layer) 225 of the photosensor PD are stacked in this order in a direction perpendicular to the sensor substrate 21 .

[0069] In addition, in the present disclosure, the photosensor PD is not limited to an organic photodiode (OPD), and may be, for example, a silicon photodiode (SiPD).

[0070] Next, an example of operation of the detection device 1 will be described. Fig. 6 is a timing waveform diagram showing an example of operation in one frame period of the detection device according to the embodiment. Fig. 7 is a timing waveform diagram showing an example of operation in the reset period in Fig. 6. Fig. 8 is a timing waveform diagram showing an example of operation in the readout period in Fig. 6. Fig. 9 is a timing waveform diagram showing an example of operation in the drive period of one gate line included in the row readout period VR in Fig. 6. Fig. 10 is an explanatory diagram for explaining the relationship between driving of the sensor region of the detection device according to the embodiment and the lighting operation of the light source.

[0071] As shown in FIG. 6, the detection device 1 has a reset period Prst, an exposure period Pex, and a readout period Pdet. The power supply circuit 123 supplies a sensor power supply signal VDDSNS to the anode of the photosensor PD throughout the reset period Prst, the exposure period Pex, and the readout period Pdet. The sensor power supply signal VDDSNS is a signal that applies a reverse bias between the anode and cathode of the photosensor PD. For example, a reference signal COM of substantially 0.75 V is applied to the cathode of the photosensor PD, but by applying a sensor power supply signal VDDSNS of substantially -1.25 V to the anode, the anode-cathode is reverse biased at substantially 2.0 V. After setting the reset signal RST2 to "H," the control circuit 122 supplies a start signal STV and a clock signal CK to the gate line drive circuit 15, starting the reset period Prst. During the reset period Prst, the control circuit 122 supplies the reference signal COM to the reset circuit 17 and turns on the fourth switching element TrR for supplying a reset voltage by the reset signal RST2. As a result, the reference signal COM is supplied as a reset voltage to each signal line SGL. The reference signal COM is set to, for example, 0.75 V.

[0072] During the reset period Prst, the gate line driving circuit 15 sequentially selects gate lines GCL based on a start signal STV, a clock signal CK, and a reset signal RST1. The gate line driving circuit 15 sequentially supplies gate driving signals Vgcl {Vgcl(1) to Vgcl(M)} to the gate lines GCL. The gate driving signal Vgcl has a pulse waveform including a power supply voltage VDD, which is a high-level voltage, and a power supply voltage VSS, which is a low-level voltage. In FIG. 6 , M (e.g., M=256) gate lines GCL are provided, and gate driving signals Vgcl(1), ..., Vgcl(M) are sequentially supplied to each gate line GCL, causing the multiple first switching elements Tr to be sequentially turned on row by row and a reset voltage to be supplied. For example, the voltage of 0.75 V of the reference signal COM is supplied as the reset voltage.

[0073] Specifically, as shown in FIG. 7 , the gate line drive circuit 15 supplies a gate drive signal Vgcl(1) of a high-level voltage (power supply voltage VDD) to the gate line GCL(1) during a period V(1). The control circuit 122 supplies at least one of selection signals ASW1, ..., ASW6 (selection signal ASW1 in FIG. 7 ) to the signal line selection circuit 16 during the period when the gate drive signal Vgcl(1) is at a high-level voltage (power supply voltage VDD). This connects the signal line SGL of the pixel PAA selected by the selection signal ASW1 to the AFE circuit 48. As a result, the reset voltage (reference signal COM) is also supplied to the connection wiring between the third switching element TrS and the AFE circuit 48.

[0074] Similarly, the gate line driving circuit 15 supplies high-level voltage gate driving signals Vgcl(2), ..., Vgcl(M-1), Vgcl(M) to the gate lines GCL(2), ..., GCL(M-1), GCL(M), respectively, during periods V(2), ..., V(M-1), V(M).

[0075] As a result, during the reset period Prst, the capacitance elements Ca of all pixels PAA are sequentially electrically connected to the signal line SGL and the reference signal COM is supplied. As a result, the capacitance of the capacitance elements Ca is reset. Note that it is also possible to reset the capacitance of some of the capacitance elements Ca of the pixels PAA by partially selecting the gate lines and signal lines SGL.

[0076] Examples of exposure timing include a gate line non-selection exposure control method and a constant exposure control method. In the gate line non-selection exposure control method, gate drive signals {Vgcl(1) to (M)} are sequentially supplied to all gate lines GCL connected to the photosensors PD to be detected, and a reset voltage is supplied to all photosensors PD to be detected. Subsequently, when all gate lines GCL connected to the photosensors PD to be detected are at a low voltage (the first switching element Tr is off), exposure begins, and exposure is performed during the exposure period Pex. After exposure is completed, as described above, gate drive signals {Vgcl(1) to (M)} are sequentially supplied to the gate lines GCL connected to the photosensors PD to be detected, and readout is performed during the readout period Pdet. In the constant exposure control method, it is also possible to control exposure during the reset period Prst and the readout period Pdet (constant exposure control). In this case, the exposure period Pex(1) begins after the gate drive signal Vgcl(1) is supplied to the gate line GCL during the reset period Prst. Here, the exposure period Pex{(1)...(M)} is the actual exposure period, which is the period during which the photosensor PD charges the capacitance element Ca, and does not include periods during which light is irradiated outside of this period. The charge stored in the capacitance element Ca during the reset period Prst flows as a reverse current (from the cathode to the anode) through the photosensor PD due to light irradiation, reducing the potential difference across the capacitance element Ca. The actual exposure periods Pex(1),..., Pex(M) for the pixel PAA corresponding to each gate line GCL have different start and end times. Each exposure period Pex(1),..., Pex(M) begins when the gate drive signal Vgcl changes from the high-level power supply voltage VDD to the low-level power supply voltage VSS during the reset period Prst. Furthermore, the exposure periods Pex(1), ..., Pex(M) each end when the gate drive signal Vgcl changes from the power supply voltage VSS to the power supply voltage VDD during the readout period Pdet. The exposure times of the exposure periods Pex(1), ..., Pex(M) are equal in length.

[0077] During the exposure periods Pex {(1)...(M)}, a current flows in each pixel PAA in response to light irradiated onto the photosensor PD, and as a result, charge is accumulated in each capacitance element Ca.

[0078] Before the readout period Pdet starts, the control circuit 122 sets the reset signal RST2 to a low-level voltage. This stops the operation of the reset circuit 17. The reset signal may be set to a high-level voltage only during the reset period Prst. During the readout period Pdet, as in the reset period Prst, the gate line drive circuit 15 sequentially supplies gate drive signals Vgcl(1), ..., Vgcl(M) to the gate lines GCL.

[0079] 8 , the gate line driving circuit 15 supplies a gate driving signal Vgcl(1) of a high-level voltage (power supply voltage VDD) to the gate line GCL(1) during a row readout period VR(1). The control circuit 122 sequentially supplies selection signals ASW1, ..., ASW6 to the signal line selection circuit 16 during the period when the gate driving signal Vgcl(1) is at a high-level voltage (power supply voltage VDD). As a result, the signal lines SGL of the pixels PAA selected by the gate driving signal Vgcl(1) are sequentially connected to the AFE circuit 48. As a result, the detection signal Vdet is supplied to the AFE circuit 48 for each pixel PAA.

[0080] Similarly, the gate line driving circuit 15 supplies high-level voltage gate driving signals Vgcl(2), ..., Vgcl(M-1), and Vgcl(M) to the gate lines GCL(2), ..., GCL(M-1), and GCL(M), respectively, during row readout periods VR(2), ..., VR(M-1), and VR(M). That is, the gate line driving circuit 15 supplies the gate driving signal Vgcl to the gate line GCL for each row readout period VR(1), VR(2), ..., VR(M-1), and VR(M). For each period in which each gate driving signal Vgcl is at a high-level voltage, the signal line selection circuit 16 sequentially or simultaneously selects the signal lines SGL based on the selection signal ASW. The signal line selection circuit 16 sequentially or simultaneously connects each signal line SGL to one AFE circuit 48. This allows the detection device 1 to output the detection signals Vdet of all the pixels PAA to the AFE circuit 48 during the readout period Pdet.

[0081] An example of operation during a row readout period VR, which is the supply period of one gate drive signal Vgcl(j) in Fig. 6, will be described below with reference to Fig. 9. In Fig. 6, the first gate drive signal Vgcl(1) is labeled with the row readout period VR, but the same applies to the other gate drive signals Vgcl(2), ..., Vgcl(M). j is a natural number from 1 to M.

[0082] As shown in FIGS. 9 and 4 , the output (Vout) of the third switching element TrS is reset to a reference potential (Vref) voltage. The reference potential (Vref) voltage is a reset voltage, e.g., 0.75 V. Next, the gate drive signal Vgcl(j) goes high, turning on the first switching element Tr of the corresponding row, and the signal line SGL of each row goes to a voltage corresponding to the charge accumulated in the capacitance (capacitor element Ca) of the corresponding pixel PAA. After a period t1 has elapsed since the rising edge of the gate drive signal Vgcl(j), a period t2 occurs during which the selection signal ASW(k) goes high. When the selection signal ASW(k) goes high and the third switching element TrS turns on, the AFE circuit 48 and the capacitance (capacitor element Ca) of the pixel PAA are electrically connected via the third switching element TrS. As a result, the output (Vout) of the third switching element TrS (see FIG. 4) changes to a voltage corresponding to the charge accumulated in the capacitance (capacitor element Ca) of the pixel PAA (period t3). In the example of FIG. 9, this voltage drops from the reset voltage as shown in period t3. Thereafter, when the switch SSW is turned on (period t4 when the SSW signal is at a high level), the charge accumulated in the capacitance (capacitor element Ca) of the pixel PAA moves to the capacitance (capacitor element Cb) of the detection signal amplifier circuit 42 of the AFE circuit 48, and the output voltage of the detection signal amplifier circuit 42 becomes a voltage corresponding to the charge accumulated in the capacitor element Cb. At this time, the inverting input of the detection signal amplifier circuit 42 becomes the imaginary short potential of the operational amplifier, and therefore becomes the reference potential (Vref). The output voltage of the detection signal amplifier circuit 42 is read by the A / D conversion circuit 43. 9, the waveforms of the selection signals ASW(k), ASW(k+1), ... corresponding to the signal lines SGL of each column become high to sequentially turn on the third switching elements TrS, and similar operations are sequentially performed to sequentially read out the charges accumulated in the capacitances (capacitance elements Ca) of the pixels PAA connected to the corresponding gate lines GCL. Note that ASW(k), ASW(k+1), ... in FIG. 9 are, for example, any of ASW1 to ASW6 in FIG.

[0083] Specifically, when a period t4 occurs during which the switch SSW is turned on, charge transfers from the capacitance (capacitor Ca) of pixel PAA to the capacitance (capacitor Cb) of the detection signal amplifier circuit 42 of the AFE circuit 48. At this time, the non-inverting input (+) of the detection signal amplifier circuit 42 is biased to a reference potential (Vref) voltage (e.g., 0.75 V). Therefore, an imaginary short circuit between the inputs of the detection signal amplifier circuit 42 causes the output (Vout) of the third switching element TrS to also become the reference potential (Vref). Furthermore, the voltage of the capacitor Cb becomes a voltage corresponding to the charge accumulated in the capacitance (capacitor Ca) of pixel PAA at the location where the third switching element TrS is turned on in response to the selection signal ASW(k). After the output (Vout) of the third switching element TrS becomes the reference potential (Vref) voltage due to the imaginary short circuit, the output of the detection signal amplifier circuit 42 becomes a voltage corresponding to the capacitance of the capacitor Cb. The output voltage of the detection signal amplifier circuit 42 is read by the A / D conversion circuit 43. The voltage of the capacitance element Cb is, for example, the voltage between two electrodes provided in the capacitor that constitutes the capacitance element Cb.

[0084] 10 , the detection device 1 executes the above-described reset period Prst, exposure period Pex{(1)...(M)}, and readout period Pdet during each of periods t(1), t(2), t(3), and t(4). During the reset period Prst and readout period Pdet, the gate line driving circuit 15 sequentially scans the gate lines GCL(1) to GCL(M). In the following description, detection during periods t(1), t(2), t(3), and t(4), i.e., scanning the gate lines GCL(1) to GCL(M) during the reset period Prst and readout period Pdet and acquiring the detection signal Vdet from the signal line SGL of each column, is referred to as detection of one frame.

[0085] The control circuit 122 can control the lighting and non-lighting of the light sources depending on the detection target. Fig. 10 shows an example in which the first light source 61 is turned on during periods t(1) and t(3), and the second light source 62 is turned on during periods t(2) and t(4). That is, in the first example shown in Fig. 10, the control circuit 122 alternately turns on and off the first light source 61 and the second light source 62 for each frame detection. However, the present invention is not limited to this. For example, the control circuit 122 may alternately turn on and off the first light source 61 and the second light source 62 every predetermined period, or may keep one of them continuously lit.

[0086] Next, application examples of the detection device 1 according to the first embodiment will be described. Fig. 11 is a schematic diagram showing a first application example of the detection device according to the embodiment. Fig. 12 is a schematic diagram showing a second application example of the detection device according to the embodiment.

[0087] 11 , the detection device 1 is a ring-shaped wearable device 200 that can be attached to or detached from the human body and is worn on a finger Fg of a subject. The finger Fg includes the thumb, index finger, middle finger, ring finger, little finger, etc. In the first application example shown in FIG. 11 , the detection device 1 according to the present disclosure acquires a pulse wave from the finger Fg on which it is worn.

[0088] 12 , the detection device 1 is a ring-shaped wearable device 200a such as a smartwatch, a wristwatch, or a wristband, and is worn on the human body HB of a subject. The human body HB includes the subject's wrist, arm, leg, etc. In the second application example shown in FIG. 12 , the detection device 1 acquires a pulse wave from the human body HB (e.g., the subject's arm) on which it is worn.

[0089] When acquiring a pulse wave by wearing a wearable device 200, 200a (see Figures 11 and 12) that employs the detection device 1 having the above-described configuration, periodic body movement noise generated by human body movement such as walking may be mistakenly identified as a pulse wave.

[0090] A specific example of a process capable of suppressing periodic body movement noise when acquiring biological information will be described below.

[0091] 13 is a flowchart showing an example of a detection process flow in the detection device according to the embodiment. The processes shown in FIG. 13 are mainly executed by the signal processing circuit 44 of the detection circuit 40.

[0092] In the following description, X<n,m> denotes a variable for pixel PAA in column n and row m. The variable X<n,m> includes coordinate information for pixel PAA from which the variable X<n,m> was obtained. Furthermore, X(f)<n,m> denotes the variable X<n,m> for the fth frame.

[0093] In the detection process flow shown in Fig. 13, first, the signal processing circuit 44 executes the raw data acquisition process shown in Fig. 14 to acquire detection values ​​Raw(f)<n, m> for multiple frames for each pixel PAA in the sensor area 10 (Fig. 13, step S100). Fig. 14 is a sub-flowchart showing an example of the raw data acquisition process.

[0094] The number of frames F when acquiring detection values ​​Raw(f)<n,m> for multiple frames is set to a number that allows multiple (e.g., approximately 10) pulse wave peaks to be acquired. The number of frames F is defined by the following equation (1), where P is the acquisition period for the detection values ​​Raw(f)<n,m> and t is the sampling period. The acquisition period P for the detection values ​​Raw(f)<n,m> is set to, for example, 10 to 20 seconds. The number of frames F is stored in, for example, the memory circuitry 46.

[0095] F=P / t...(1)

[0096] 14, the signal processing circuit 44 sets the initial frame f to 1 (f=1) (step S101), sets n=1 and m=1 (step S102), acquires the detection value Raw(f)<n,m> (step S103), and stores the acquired detection value Raw(f)<n,m> in the memory circuit 46 (step S104). Fig. 15 is a diagram showing the detection values ​​for F frames at each pixel in the detection area.

[0097] Next, the signal processing circuit 44 sets n=n+1 (step S105) and determines whether n is N (n=N) (step S106). If n is less than N (n<N) (step S106; No), the process returns to step S103.

[0098] When n becomes N (n=N) (step S106; Yes), the signal processing circuit 44 then sets m=m+1 (step S107) and determines whether m is M (m=M) (step S108). If m is less than M (m<M) (step S108; No), the process returns to step S103.

[0099] When m becomes M (m=M) (step S108; Yes), the signal processing circuit 44 then sets f=f+1 (step S109) and determines whether f is F (f=F) (step S110). If f is less than F (f<F) (step S110; No), the process returns to step S102.

[0100] By repeating the processes from step S102 to step S110 F times, the detection values ​​Raw(f)<n, m> for F frames at each pixel PAA are stored in the memory circuit 46.

[0101] When f becomes F (f=F) (step S110; Yes), the process returns to the detection process flow shown in Fig. 13, and the signal processing circuit 44 then executes the first image generation process shown in Fig. 16 (Fig. 13, step S200). Fig. 16 is a sub-flowchart showing an example of the first image generation process.

[0102] In the first image generation process shown in Fig. 16, first, the signal processing circuit 44 executes a first signal intensity extraction process (Fig. 16, step S210). Fig. 17 is a sub-flowchart showing an example of the first signal intensity extraction process.

[0103] 17, the signal processing circuit 44 sets n=1 and m=1 (step S211), sets the initial frame f to 1 (f=1) (step S212), and reads the detection value Raw(f)<n,m> from the storage circuit 46 (step S213). Furthermore, the signal processing circuit 44 sets f=f+1 (step S214) and determines whether f is F (f=F) (step S215). If f is less than F (f<F) (step S215; No), the process returns to step S213.

[0104] By the processing from step S213 to step S215, the detection value Raw(f)<n, m> for F frames at pixel PAA in the nth column and mth row is read out.

[0105] When f becomes F (f = F) (step S215; Yes), the signal processing circuit 44 performs Fourier transform processing (here, FFT (Fast Fourier Transform) processing) on ​​the detection values ​​Raw(f)<n, m> for F frames read from the memory circuit 46 as time domain data, and generates frequency domain data Sdet(i)<m, n> (step S216).

[0106] 18 is a diagram showing an example of time domain data, in which the horizontal axis represents frame f (time) and the vertical axis represents the detection value Raw(f)<n, m> corresponding to each frame f.

[0107] 19 is a diagram showing an example of frequency domain data. In FIG. 19, the horizontal axis represents frequency line i, and the vertical axis represents signal strength Sdet(i)<n, m> corresponding to each frequency line i. The number I of frequency lines included in the frequency domain data is defined by the following equation (2).

[0108] I=1 / (F×t)...(2)

[0109] 19 to a frequency range equal to or greater than the first frequency line i1 and less than the second frequency line i2, stores the data in the memory circuitry 46 as first frequency domain data (signal strength Sdet1(i)<n,m>) (step S217), and extracts a peak value from the first frequency domain data (signal strength Sdet1(i)<n,m>) (step S218). The frequency corresponding to the first frequency line i1 is set to, for example, 0.5 Hz, and the frequency corresponding to the second frequency line i2 is set to, for example, 4 Hz. The first frequency domain data (signal strength Sdet1(i)<n,m>) is stored in the memory circuitry 46.

[0110] The signal processing circuit 44 stores the peak value extracted in step S218 in the memory circuit 46 as the first signal intensity Peak1<n,m> for the pixel PAA in the nth column and mth row (step S219).

[0111] 19, the signal component around 0.75 Hz is the body movement component, and the signal component around 1.3 Hz is the pulse wave component. Here, the signal strength of the frequency line corresponding to the body movement component is extracted as the first signal strength Peak1<n,m>.

[0112] Then, the signal processing circuit 44 sets n=n+1 (step S220) and determines whether n is N (n=N) (step S221). If n is less than N (n<N) (step S221; No), the process returns to step S212.

[0113] When n becomes N (n=N) (step S221; Yes), the signal processing circuit 44 then sets m=m+1 (step S222) and determines whether m is M (m=M) (step S223). If m is less than M (m<M) (step S223; No), the process returns to step S212.

[0114] By repeating the processing from step S212 to step S223 N×M times, the first frequency domain data (signal intensity Sdet1(i)<n,m>) and first signal intensity Peak1<n,m> for each pixel PAA are stored in the memory circuit 46.

[0115] When m becomes M (m=M) (step S223; Yes), the process returns to the first image generation process shown in Fig. 16, and the signal processing circuit 44 then executes the binarization process shown in Fig. 20 (Fig. 16, step S230). Fig. 20 is a sub-flowchart showing an example of the binarization process in the first image generation process.

[0116] In the binarization process shown in Figure 20, the signal processing circuit 44 sets n = 1 and m = 1 (step S231), reads the first signal strength Peak1<n, m> from the memory circuit 46 (step S232), and determines whether the read first signal strength Peak1<n, m> is greater than or equal to a predetermined threshold Sig1th (Speak1<n, m> ≧ Sig1th) (step S233).

[0117] If the first signal strength Peak1<n,m> is greater than or equal to the threshold value Sig1th (step S233; Yes), the first binary value Bin1<n,m> at pixel PAA in the nth column and mth row is set to "1" (Bin1<n,m> = 1, step S234) and stored in the memory circuit 46 (step S236).

[0118] If the first signal strength Peak1<n,m> is less than the threshold value Sig1th (step S233; No), the first binary value Bin1<n,m> at pixel PAA in the nth column and mth row is set to "0" (Bin1<n,m> = 0, step S235) and stored in the memory circuit 46 (step S236).

[0119] Then, the signal processing circuit 44 sets n=n+1 (step S237) and determines whether n is N (n=N) (step S238). If n is less than N (n<N) (step S238; No), the process returns to step S232.

[0120] When n becomes N (n=N) (step S238; Yes), the signal processing circuit 44 then sets m=m+1 (step S239) and determines whether m is M (m=M) (step S240). If m is less than M (m<M) (step S240; No), the process returns to step S232.

[0121] By repeating the processes from step S232 to step S240 N×M times, the first binary value Bin1<n,m> for each pixel PAA is stored in the memory circuit 46. By applying the first binary value Bin1<n,m> for each pixel PAA to the sensor area 10, the image shown in FIG.

[0122] 21 is a diagram showing a specific example of an image obtained by visualizing the first binary values ​​for each pixel. In this example, the first binary value Bin1<n,m>, the first binary value Bin1<n+1,m>, and the first binary value Bin1<n,m+1> are all "1," and the first binary value Bin1<n,m-1> and the first binary value Bin1<n-1,m> are all "0."

[0123] In the present disclosure, the region in which the first binary value Bin1 is "1" is defined as the "first region" in the image shown in Fig. 21. In other words, the first region indicates the region in which the first signal strength Peak1<n, m> is equal to or greater than the threshold value Sig1th in the image shown in Fig. 21.

[0124] When m becomes M (m=M) (step S240; Yes), the process returns from the first image generation process shown in Fig. 16 to the detection process flow shown in Fig. 13, and then the signal processing circuit 44 executes the filter generation process shown in Fig. 22 (step S300 in Fig. 13). Fig. 22 is a sub-flowchart showing an example of the filter generation process.

[0125] In the filter generation process shown in Fig. 22, first, the signal processing circuit 44 executes edge extraction processing (Fig. 22, step S310). Fig. 23 is a sub-flowchart showing an example of the edge extraction processing.

[0126] In the edge extraction process shown in FIG. 23, the signal processing circuit 44 sets n=1 and m=1 (step S311), reads the first binary value Bin1<n, m> from the memory circuit 46 (step S312), and determines whether the first binary value Bin1<n, m> is “1” (Bin1<n, m>=1) (step S313).

[0127] If the first binary value Bin1<n,m> is "1" (step S313; Yes), the signal processing circuit 44 then reads the first binary value Bin1<n,m-1> from the memory circuit 46 (step S314) and determines whether the first binary value Bin1<n,m-1> is "1" (Bin1<n,m-1> = 1) (step S315).

[0128] If the first binary value Bin1<n,m-1> is "1" (step S315; Yes), the signal processing circuit 44 then reads the first binary value Bin1<n-1,m> from the memory circuit 46 (step S316) and determines whether the first binary value Bin1<n-1,m> is "1" (Bin1<n-1,m> = 1) (step S317).

[0129] If the first binary value Bin1<n-1,m> is "1" (step S317; Yes), the signal processing circuit 44 then reads the first binary value Bin1<n+1,m> from the memory circuit 46 (step S318) and determines whether the first binary value Bin1<n+1,m> is "1" (Bin1<n+1,m>=1) (step S319).

[0130] If the first binary value Bin1<n+1,m> is "1" (step S319; Yes), the signal processing circuit 44 then reads the first binary value Bin1<n,m+1> from the memory circuit 46 (step S320) and determines whether the first binary value Bin1<n,m+1> is "1" (Bin1<n,m+1> = 1) (step S321).

[0131] If the first binary value Bin1<n,m> is "1" (step S313; Yes), or if the first binary value Bin1<n,m-1> is "0" (step S315; No), or if the first binary value Bin1<n-1,m> is "0" (step S317; No), or if the first binary value Bin1<n+1,m> is "0" (step S319; No), or if the first binary value Bin1<n,m+1> is "0" (step S321; No), the signal processing circuit 44 sets the second binary value Bin2<n,m> in the pixel PAA in the nth column and mth row to "1" (Bin2<n,m> = 1, step S322) and stores it in the memory circuit 46 (step S324).

[0132] If the first binary value Bin1<n,m> is "0" (step S313; No), or the first binary value Bin1<n,m> is "1" (step S313; Yes), and the first binary value Bin1<n,m-1> is "1" (step S315; Yes), and the first binary value Bin1<n-1,m> is "1" (step S317; Yes), and the first binary value Bin1<n+1,m> is "1" (step S319; Yes), and the first binary value Bin1<n,m+1> is "1" (step S321; Yes), the signal processing circuit 44 sets the second binary value Bin2<n,m> in the pixel PAA in the nth column and mth row to "0" (Bin2<n,m> = 0, step S323) and stores it in the memory circuit 46 (step S324).

[0133] Then, the signal processing circuit 44 sets n=n+1 (step S325) and determines whether n is N (n=N) (step S326). If n is less than N (n<N) (step S326; No), the process returns to step S312.

[0134] When n becomes N (n=N) (step S326; Yes), the signal processing circuit 44 then sets m=m+1 (step S327) and determines whether m is M (m=M) (step S328). If m is less than M (m<M) (step S328; No), the process returns to step S312.

[0135] By repeating the processes from step S312 to step S328 N×M times, the second binary value Bin2<n,m> for each pixel PAA is stored in the memory circuit 46. By applying the second binary value Bin2<n,m> for each pixel PAA to the sensor area 10, the image shown in FIG.

[0136] 24 is a diagram showing a specific example of an image obtained by visualizing the second binary values ​​for each pixel. In this example, the second binary values ​​Bin2<n,m> and Bin2<n+1,m> are "1," and the second binary values ​​Bin2<n,m-1>, Bin2<n-1,m>, and Bin2<n,m+1> are "0."

[0137] The above-described edge extraction process is merely an example, and it is also possible to use a known contour tracing algorithm to extract pixels PAA located on the periphery of the first region (see FIG. 21).

[0138] When m becomes M (m=M) (step S328; Yes), the process returns to the filter generation process shown in Fig. 22, and the signal processing circuit 44 then executes the averaging process shown in Fig. 25 (Fig. 22, step S330). Fig. 25 is a sub-flowchart showing an example of the averaging process.

[0139] 25, the signal processing circuit 44 sets i=1 (step S331) and determines whether the frequency line i is equal to or greater than the first frequency line i1 (step S332). If the frequency line i is less than the first frequency line i1 (step S332; No), the signal processing circuit 44 increments the frequency line i (i=i+1, step S333) and repeatedly executes the processes of steps S332 and S333 until the frequency line i is equal to or greater than the first frequency line i1 (step S332; Yes).

[0140] When the frequency line i is equal to or greater than the first frequency line i1 (step S332; Yes), the signal processing circuit 44 calculates the average value Ave(i) for each frequency line i of the first frequency domain data (signal intensity Sdet1(i)<n, m>) for all pixels PAA included in the region where the second binary value Bin2 is "1" in the image shown in Figure 24 (step S334). The average value Ave(i) for each frequency line i can be expressed by the following equation (3).

[0141] Ave(i)=ΣSdet1(i)<n,m> / ΣBin2<n,m>...(3)

[0142] Next, the signal processing circuit 44 performs threshold determination processing on the average value Ave(i) calculated in step S334 to generate a filter value Fil(i) corresponding to the frequency line i. Specifically, the signal processing circuit 44 determines whether the average value Ave(i) calculated in step S334 is equal to or greater than a predetermined threshold value Aveth (step S335).

[0143] If the average value Ave(i) is equal to or greater than the threshold value Aveth (step S335; Yes), the signal processing circuit 44 sets the filter value Fil(i) to "0" and stores it in the storage circuit 46 (step S336). If the average value Ave(i) is less than the threshold value Aveth (step S335; No), the signal processing circuit 44 sets the filter value Fil(i) to "1" and stores it in the storage circuit 46 (step S337).

[0144] Then, the signal processing circuit 44 increments the frequency line i (i = i + 1, step S338) and determines whether the frequency line i is equal to or greater than the second frequency line i2 (i ≥ i2) (step S339). If the frequency line i is less than the second frequency line i2 (i < i2) (step S339; No), the process returns to step S334.

[0145] By repeating the processing from step S334 to step S339, the filter value Fil(i) corresponding to the frequency line i where the signal strength Ave(i) after the averaging process is equal to or greater than the threshold value Aveth is stored as "0" in the memory circuit 46, and the filter value Fil(i) corresponding to the frequency line i where the signal strength Ave(i) after the averaging process is less than the threshold value Aveth is stored as "1" in the memory circuit 46.

[0146] When the frequency line i is equal to or greater than the second frequency line i2 (i≧i2) (step S339; Yes), the process returns from the filter generation process shown in FIG. 22 to the detection process flow shown in FIG.

[0147] Fig. 26 is a diagram showing an example of average values ​​of signal intensities of multiple pixels in the image shown in Fig. 24. Fig. 27 is a diagram showing an example of filter values. In Figs. 26 and 27, the horizontal axis represents frequency line i. The vertical axis in Fig. 26 represents the average value Ave(i) corresponding to each frequency line i. The vertical axis in Fig. 27 represents the filter value Fil(i) corresponding to each frequency line i.

[0148] 26 and 27, by the above-described process, the filter value Fil of the frequency line where the average value Ave is equal to or greater than the threshold value Aveth becomes "0." In the example shown in Fig. 26 and 27, the filter value Fil around 0.75 Hz and the filter value Fil around 1.5 Hz become "0."

[0149] In the present disclosure, the process returns from the filter generation process shown in Fig. 22 to the detection process flow shown in Fig. 13, and the second image generation process shown in Fig. 28 is executed (Fig. 13, step S400). In the second signal strength calculation process shown in Fig. 29 (Fig. 28, step S410), the filter value Fil(i) is applied to the first frequency domain data (signal strength Sdet1(i)<n, m>). As a result, the signal strength corresponding to the frequency line where the filter value Fil(i) is "0" is suppressed.

[0150] Fig. 28 is a sub-flowchart showing an example of the second image generation process. Fig. 29 is a sub-flowchart showing an example of the second signal intensity calculation process.

[0151] 29 , the signal processing circuit 44 sets i=1 (step S411) and determines whether the frequency line i is equal to or greater than the first frequency line i1 (step S412). If the frequency line i is less than the first frequency line i1 (step S412; No), the signal processing circuit 44 increments the frequency line i (i=i+1, step S413) and repeatedly executes the processes of steps S412 and S413 until the frequency line i is equal to or greater than the first frequency line i1 (step S412; Yes).

[0152] When the frequency line i is equal to or greater than the first frequency line i1 (step S412; Yes), the signal processing circuit 44 reads out the filter value Fil(i) corresponding to the frequency line i from the storage circuit 46 (step S414).

[0153] Next, the signal processing circuit 44 sets n = 1 and m = 1 (step S415), reads out the first frequency domain data (signal strength Sdet1(i)<n,m>) from the memory circuit 46 (step S416), and multiplies the signal strength Sdet1(i)<n,m> corresponding to the frequency line i of the read out first frequency domain data by the filter value Fil(i) corresponding to the frequency line i to calculate the second frequency domain data (signal strength Sdet2(i)<n,m>), which is stored in the memory circuit 46 (step S417). The second frequency domain data (signal strength Sdet2(i)<n,m>) can be expressed by the following equation (4):

[0154] Sdet2(i)<n,m>=Sdet1(i)<n,m>×Fil(i)...(4)

[0155] FIG. 30 is a diagram showing an example of second frequency domain data. In FIG. 30, the horizontal axis represents frequency line i, and the vertical axis represents signal strength Sdet2(i)<n,m> corresponding to each frequency line i. As shown in FIG. 30, by applying a filter value Fil(i) corresponding to each frequency line i to the first frequency domain data (signal strength Sdet1(i)<n,m>) for each pixel PAA, second frequency domain data (signal strength Sdet2(i)<n,m>) in which the signal strength corresponding to the frequency line where the filter value Fil(i) is "0" is suppressed is obtained. When the frequency corresponding to the frequency line where the filter value Fil(i) is "0" overlaps with the frequency of the body movement component, second frequency domain data (signal strength Sdet2(i)<n,m>) in which the body movement component is suppressed is obtained.

[0156] Fig. 31 is a schematic diagram showing the positional relationship between the pulse wave component detection region and the body movement noise component detection region within the sensor region. In Fig. 31, region A1+A2, which includes regions A1 and A2, indicates a region where the binarized value of the signal strength of the frequency component corresponding to body movement noise is "1." In contrast, region A2, excluding region A1, indicates a region where the binarized value of the signal strength of the frequency component corresponding to the pulse wave component is "1." In other words, of region A1+A2, region A1 indicates a region where the binarized value of the signal strength of the frequency component corresponding to the pulse wave component is "0."

[0157] As shown in FIG. 31 , region A1+A2 is wider than region A2, and region A2 is included within region A1+A2. In the present disclosure, a filter value Fil(i) corresponding to a frequency line where the average value Ave(i) of the first frequency domain data (signal strength Sdet1(i)<n,m>) at the edge portion corresponding to region A1 is equal to or greater than a predetermined threshold Aveth is set to "0," and this filter value is applied to the first frequency domain data (signal strength Sdet1(i)<n,m>) for each pixel PAA in the entire sensor area 10 (detection area AA) to calculate second frequency domain data (signal strength Sdet2(i)<n,m>). This allows second frequency domain data (signal strength Sdet2(i)<n,m>) in which body movement components are suppressed to be obtained. Specifically, the example shown in FIG. 30 illustrates an example in which signal components near 0.75 Hz and signal components near 1.5 Hz are suppressed as body movement components.

[0158] Next, the signal processing circuit 44 extracts the peak value in the second frequency domain data (signal strength Sdet2(i)<n, m>) (step S418) and stores the peak value as the second signal strength Peak2<n, m> in the memory circuit 46 (step S419).

[0159] 30, the signal component near 1.3 Hz is taken as the pulse wave component. Here, the signal strength of the frequency line corresponding to the pulse wave component is extracted as the second signal strength Peak2<n, m>.

[0160] Then, the signal processing circuit 44 sets n=n+1 (step S420) and determines whether n is N (n=N) (step S421). If n is less than N (n<N) (step S421; No), the process returns to step S416.

[0161] When n becomes N (n=N) (step S421; Yes), the signal processing circuit 44 then sets m=m+1 (step S422) and determines whether m is M (m=M) (step S423). If m is less than M (m<M) (step S423; No), the process returns to step S416.

[0162] By repeating the processing from step S416 to step S423 N x M times, the second frequency domain data (signal intensity Sdet2(i)<n,m>) and second signal intensity Peak2<n,m> for each pixel PAA are stored in the memory circuit 46.

[0163] When m becomes M (m=M) (step S423; Yes), the process returns to the second image generation process shown in Fig. 28, and the signal processing circuit 44 then executes the binarization process shown in Fig. 32 (Fig. 28, step S430). Fig. 32 is a sub-flowchart showing an example of the binarization process in the second image generation process.

[0164] In the binarization process shown in Figure 32, the signal processing circuit 44 sets n = 1 and m = 1 (step S431), reads the second signal strength Peak2<n, m> from the memory circuit 46 (step S432), and determines whether the read second signal strength Peak2<n, m> is greater than or equal to a predetermined threshold value Sig2th (Speak1<n, m> ≧ Sigth) (step S433).

[0165] If the second signal strength Peak2<n,m> is greater than or equal to the threshold value Sig2th (step S433; Yes), the third binary value Bin3<n,m> at pixel PAA in the nth column and mth row is set to "1" (Bin3<n,m> = 1, step S434) and stored in the memory circuit 46 (step S436).

[0166] If the second signal strength Peak2<n,m> is less than the threshold value Sig2th (step S433; No), the third binary value Bin3<n,m> at pixel PAA in the nth column and mth row is set to "0" (Bin3<n,m> = 0, step S435) and stored in the memory circuit 46 (step S436).

[0167] Then, the signal processing circuit 44 sets n=n+1 (step S437) and determines whether n is N (n=N) (step S438). If n is less than N (n<N) (step S438; No), the process returns to step S432.

[0168] When n becomes N (n=N) (step S438; Yes), the signal processing circuit 44 then sets m=m+1 (step S439) and determines whether m is M (m=M) (step S440). If m is less than M (m<M) (step S440; No), the process returns to step S432.

[0169] By repeating the processes of steps S432 to S440 N×M times, the third binary value Bin3<n,m> for each pixel PAA is stored in the memory circuit 46. By applying the third binary value Bin3<n,m> for each pixel PAA to the sensor area 10, the image shown in FIG.

[0170] 33 is a diagram showing a specific example of an image obtained by visualizing the third binary values ​​for each pixel. In this example, the third binary values ​​Bin3<n,m>, Bin3<n+1,m>, and Bin3<n,m+1> are all "1," and the third binary values ​​Bin3<n,m-1> and Bin3<n-1,m> are all "0."

[0171] In the present disclosure, the region in which the third binary value Bin3 is "1" in the image shown in Fig. 33 is defined as the "second region." In other words, the second region indicates the region in the image shown in Fig. 33 where the second signal strength Peak2<n, m> is equal to or greater than the threshold value Sig2th.

[0172] When m becomes M (m=M) (step S440; Yes), the process returns from the second image generation process shown in Fig. 28 to the detection process flow shown in Fig. 13, and then the signal processing circuit 44 executes the pulse wave generation process shown in Fig. 34 (Fig. 13, step S500). Fig. 34 is a sub-flowchart showing an example of the pulse wave generation process.

[0173] In the pulse wave generation process shown in Fig. 34, the signal processing circuit 44 calculates the area S2 of the second region (see Fig. 33) (step S501). The area S2 of the second region can be expressed by the following equation (5).

[0174] S2=ΣBin3<n,m>...(5)

[0175] The signal processing circuit 44 determines whether the area S2 of the second region is less than a predetermined threshold value S2th (S2<S2th) (step S502).

[0176] If the area S2 of the second region is less than the threshold value S2th (step S502; Yes), the signal processing circuit 44 selects the first frequency domain data (signal intensity Sdet1(i)<n, m>) (step S503) and executes the first pulse wave generation process ( FIG. 34 , step S510) shown in Fig. 35. Fig. 35 is a sub-flowchart showing an example of the first pulse wave generation process.

[0177] 35 , the signal processing circuit 44 sets i=1 and Avemax=0 (step S511), and determines whether the frequency line i is equal to or greater than the first frequency line i1 (step S512). If the frequency line i is less than the first frequency line i1 (step S512; No), the signal processing circuit 44 increments the frequency line i (i=i+1, step S513) and repeatedly executes the processes of steps S512 and S513 until the frequency line i is equal to or greater than the first frequency line i1 (step S512; Yes).

[0178] When the frequency line i is equal to or greater than the first frequency line i1 (step S512; Yes), the signal processing circuit 44 calculates the average value Ave1(i) for each frequency line i of the first frequency domain data (signal strength Sdet1(i)<n, m>) for all pixels PAA included in the first domain (see FIG. 21) (step S514). The average value Ave1(i) for each frequency line i can be expressed by the following equation (6).

[0179] Ave1(i)=ΣSdet1(i)<n,m> / ΣBin1<n,m>...(6)

[0180] Next, the signal processing circuit 44 executes a process of comparing the average value Ave1(i) calculated in step S514 with Avemax. Specifically, the signal processing circuit 44 determines whether the average value Ave1(i) calculated in step S514 is equal to or less than Avemax (step S515).

[0181] If the average value Ave1(i) is equal to or less than Avemax (step S515; Yes), the process proceeds to step S517. If the average value Ave1(i) exceeds Avemax (step S515; No), the signal processing circuit 44 sets the average value Ave1(i) to Avemax and stores the frequency line i as the frequency line ipw corresponding to the pulse wave component in the memory circuit 46 (Avemax = Ave1(i), ipw = i, step S516), and then proceeds to step S517.

[0182] When the process proceeds to step S517, the signal processing circuit 44 increments the frequency line i (i=i+1, step S517) and determines whether the frequency line i is equal to or greater than the second frequency line i2 (i≧i2) (step S518). If the frequency line i is less than the second frequency line i2 (i<i2) (step S518; No), the process returns to step S514.

[0183] By repeating the processes from step S514 to step S518, the frequency line ipw corresponding to Avemax, which is the peak value of the signal strength Ave1(i) after averaging, is stored in the storage circuit 46.

[0184] If the frequency line i is equal to or greater than the second frequency line i2 (i≧i2) (step S518: Yes), the frequency corresponding to the frequency line ipw is output as the pulse wave frequency to, for example, the host (step S519). Then, the process returns from the pulse wave generation process shown in FIG. 34 to the detection process flow shown in FIG. 13, and the detection process flow ends.

[0185] Returning to step S502 shown in Fig. 34, if the area S2 of the second region is equal to or greater than the threshold value S2th (step S502; No), the signal processing circuit 44 selects the second frequency region data (signal intensity Sdet2(i)<n, m>) (step S504) and executes the first pulse wave generation process (Fig. 34, step S530) shown in Fig. 36. Fig. 36 is a sub-flowchart showing an example of the second pulse wave generation process.

[0186] 36, the signal processing circuit 44 sets i=1 and Avemax=0 (step S531), and determines whether the frequency line i is equal to or greater than the first frequency line i1 (step S532). If the frequency line i is less than the first frequency line i1 (step S532; No), the signal processing circuit 44 increments the frequency line i (i=i+1, step S533) and repeatedly executes the processes of steps S532 and S533 until the frequency line i is equal to or greater than the first frequency line i1 (step S532; Yes).

[0187] When the frequency line i is equal to or greater than the first frequency line i1 (step S532; Yes), the signal processing circuit 44 calculates the average value Ave2(i) for each frequency line i of the second frequency domain data (signal strength Sdet2(i)<n, m>) for all pixels PAA included in the second domain (see FIG. 33) (step S534). The average value Ave2(i) for each frequency line i can be expressed by the following equation (7).

[0188] Ave2(i)=ΣSdet2(i)<n,m> / ΣBin3<n,m>...(7)

[0189] Subsequently, the signal processing circuit 44 executes a process of comparing the average value Ave2(i) calculated in step S534 with Avemax. Specifically, the signal processing circuit 44 determines whether the average value Ave2(i) calculated in step S534 is equal to or less than Avemax (step S535).

[0190] If the average value Ave2(i) is equal to or less than Avemax (step S535; Yes), the process proceeds to step S537. If the average value Ave2(i) is greater than Avemax (step S535; No), the signal processing circuit 44 sets the average value Ave2(i) to Avemax and stores the frequency line i as the frequency line ipw corresponding to the pulse wave component in the memory circuit 46 (Avemax = Ave2(i), ipw = i, step S536), and then proceeds to step S537.

[0191] In step S537, the signal processing circuit 44 increments the frequency line i (i=i+1, step S537) and determines whether the frequency line i is equal to or greater than the second frequency line i2 (i≧i2) (step S538). If the frequency line i is less than the second frequency line i2 (i<i2) (step S538; No), the process returns to step S534.

[0192] By repeating the processes from step S534 to step S538, the frequency line ipw corresponding to Avemax, which is the peak value of the signal strength Ave2(i) after averaging, is stored in the memory circuit 46.

[0193] When the frequency line i is equal to or greater than the second frequency line i2 (i≧i2) (step S538; Yes), the frequency corresponding to the frequency line ipw is output as the pulse wave frequency to, for example, the host (step S539). Then, the process returns from the pulse wave generation process shown in Fig. 34 to the detection process flow shown in Fig. 13, and the detection process flow ends.

[0194] 37 and 38 show examples of first and second frequency domain data in the case where the time domain data does not contain periodic noise components such as body movement noise.

[0195] In the examples shown in Figures 37 and 38, in the first signal strength extraction process (Figure 16, step S210) shown in Figure 17, the pulse wave component of the first frequency domain data (signal strength Sdet1(i)<n,m>) is extracted as the first signal strength Peak1, and as a result, in the second signal strength calculation process (Figure 28, step S410) shown in Figure 29, second frequency domain data (signal strength Sdet2(i)<n,m>) in which the pulse wave component is suppressed is obtained. In this case, in step S433 of the binarization process in the second image generation process shown in Figure 32, the number of pixels PAA in which the second signal strength Peak2<n,m> is equal to or greater than the threshold value Sig2th (step S433; Yes) is drastically reduced, and as a result, the area S2 of the second region (see Figure 33) is reduced.

[0196] In the present disclosure, in the pulse wave generation process shown in Fig. 34, if the area S2 of the second region is less than the threshold value S2th (step S502; Yes), the signal processing circuit 44 selects the first frequency domain data (signal strength Sdet1(i)<n, m>) (step S503) and executes the first pulse wave generation process (Fig. 34, step S510) shown in Fig. 35. This makes it possible to obtain a highly accurate pulse wave component regardless of the presence or absence of periodic noise components such as body movement noise.

[0197] By the above-described processing, periodic body movement noise can be suppressed when acquiring biological information.

[0198] In the above-described embodiment, an example of acquiring a pulse wave as biometric information has been described. However, the scope of application of the detection device 1 according to the present disclosure is not limited to pulse wave frequency, and the device can be widely applied to configurations for acquiring periodically fluctuating biometric information of a subject.

[0199] Although preferred embodiments of the present invention have been described above, the present invention is not limited to such embodiments. The contents disclosed in the embodiments are merely examples, and various modifications are possible without departing from the spirit of the present invention. Appropriate modifications made without departing from the spirit of the present invention naturally fall within the technical scope of the present invention. At least one of various omissions, substitutions, and modifications of components can be made without departing from the gist of each of the above-described embodiments and modifications.

[0200] 1 Detection device 10 Sensor region 11 Detection control circuit 15 Gate line driving circuit 16 Signal line selection circuit 21 Sensor substrate 22 Sensor structure 23 Protective film 40 Detection circuit 42 Detection signal amplification circuit 43 A / D conversion circuit 44 Signal processing circuit 46 Memory circuit 47 Detection timing control circuit 48 AFE circuit 61 First light source (light source) 62 Second light source (light source) 122 Control circuit 123 Power supply circuit 126 Output circuit 200, 200a Wearable device 221 TFT layer 222 Anode electrode (lower electrode) (or cathode electrode (lower electrode)) 223 Electron transport layer (lower buffer layer) (or hole transport layer (lower buffer layer)) 224 Active layer 225 Hole transport layer (upper buffer layer) (or electron transport layer (upper buffer layer)) 226 Cathode electrode (upper electrode) (or anode electrode (upper electrode)) AA Detection area GA Peripheral area GCL Gate line PAA Pixel PD Photosensor Pdet Readout period Pex Exposure period RSW Reset switch SGL Signal line

Claims

1. A sensor area having a plurality of pixels arranged in a planar shape; a light source which irradiates the sensor area with light; and a detection circuit which acquires periodically fluctuating biological information of a subject based on data acquired from the sensor area, wherein the detection circuit: converts a plurality of detection values ​​for each of the pixels acquired in time series into signal strength for each frequency to generate first frequency domain data for each of the pixels; defines a first signal strength for each pixel as a maximum strength of signal strengths corresponding to each frequency of the first frequency domain data; defines a first region within the sensor area where the first signal strength is equal to or greater than a predetermined value; generates second frequency domain data by masking a predetermined frequency range of the first frequency domain data for all pixels in the first region based on the first frequency domain data for pixels on the periphery of the first region; defines a second signal strength for each pixel as a maximum strength of signal strengths corresponding to each frequency of the second frequency domain data; defines a second region within the sensor area where the second signal strength is equal to or greater than a predetermined value; and acquires biological information based on the second frequency domain data when an area of ​​the second region is equal to or greater than a predetermined value. When an area of ​​the second region is less than a predetermined value, the detection device acquires biological information based on the first frequency domain data.

2. The detection device according to claim 1, wherein the detection circuit averages the signal strength for each frequency of the first frequency domain data for a plurality of pixels on the periphery of the first region, generates a filter that masks a predetermined range including the frequency at which the signal strength is maximum among the frequencies of the frequency domain data after the averaging process, and applies the filter to the first frequency domain data for all pixels in the first region to generate the second frequency domain data.

3. The detection device according to claim 2, wherein, when generating the filter, the detection circuit sets a filter value of 0 for frequencies where the signal strength after averaging is equal to or greater than a predetermined threshold, and sets a filter value of 1 for frequencies where the signal strength after averaging is less than a predetermined threshold, and generates the second frequency domain data by multiplying the signal strength of the first frequency domain data by the filter value corresponding to each frequency.

4. The detection device according to claim 1, wherein the detection circuit, when the area of ​​the second region is equal to or greater than a predetermined value, averages the signal intensities of the second frequency domain data of multiple pixels included in the second region, and acquires, as biometric information, a frequency corresponding to a peak value of the signal intensity after the averaging process.

5. The detection device according to claim 1, wherein the detection circuit, when the area of ​​the second region is less than a predetermined value, averages the signal intensities of the first frequency domain data of multiple pixels included in the first region, and obtains the frequency corresponding to the peak value of the signal intensity after the averaging process as biometric information.

6. The detection device according to claim 1, wherein the detection circuit limits the frequency range for acquiring biometric information to 0.5 Hz or more and less than 4 Hz.

7. The detection device according to claim 1, wherein each of the plurality of pixels is provided with a photosensor, the photosensor being an organic photodiode, and comprising: an active layer; an upper electrode provided between the active layer and the upper electrode and an upper buffer layer sandwiched between the active layer and the upper electrode; and a lower electrode provided between the active layer and the lower electrode and a lower buffer layer sandwiched between the active layer and the upper electrode.

8. The detection device according to claim 1, wherein the light source includes a first light source that irradiates at least the sensor area with a first light.

9. The detection device according to claim 8, wherein the first light is red light or infrared light.

10. The detection device according to claim 8, wherein the first light is blue light or green light.

11. The detection device of claim 1, wherein the light source includes: a first light source that irradiates the sensor area with a first light; and a second light source that irradiates the sensor area with a second light.

12. The detection device of claim 11, wherein the first light is red light and the second light is infrared light.

13. A wearable device comprising the detection device according to claim 1, said wearable device having a ring shape that can be attached to and detached from the human body.

14. The wearable device according to claim 13, which is worn on a finger of a human body.

15. The wearable device according to claim 13, which is worn on a wrist or arm of a human body.

16. The wearable device according to claim 13, which is worn on a foot of a human body.

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