Power supply device

Abstract

First through fourth switching elements (M1–M4) are connected in series from a reference node toward a power supply node that receives an input voltage (VIN). A power supply device (1) controls the states of the switching elements to divide the input voltage and steps down an intermediate voltage (VMID) obtained by the division to generate an output voltage (VOUT). The states of the first through fourth switching elements are switched between first through third states on the basis of information about the output voltage and current information about an inductor (L1). In the first state, the second and fourth switching elements are on and the first and third switching elements are off. In the second state, the second and fourth switching elements are off and the first and third switching elements are on. In the third state, all of the first through fourth switching elements are off.

Description

power supply

[0001] The present disclosure relates to a power supply device.

[0002] 2. Description of the Related Art Power supply devices that use multiple switching techniques to step down an input voltage to generate a desired output voltage are widely used.

[0003] Japanese Patent Application Laid-Open No. 2020-89043

[0004] [Summary] Improving efficiency is important in power supply devices.

[0005] A power supply device according to the present disclosure includes a first switching element provided between a reference node having a potential lower than an input voltage and a first node, a second switching element provided between the first node and a second node, a third switching element provided between the second node and a third node, and a fourth switching element provided between the third node and a power supply node receiving the input voltage, and is configured to generate an output voltage by dividing the input voltage and stepping down an intermediate voltage obtained by voltage division through controlling the states of the switching elements, and further includes a control circuit for controlling information on the output voltage and a voltage between the first node and an output node to which the output voltage is applied. and current information of an inductor provided between the first switching element and the fourth switching element, wherein in the first state, the second switching element and the fourth switching element are on and the first switching element and the third switching element are off, in the second state, the second switching element and the fourth switching element are off and the first switching element and the third switching element are on, and in the third state, the first switching element to the fourth switching element are all off.

[0006] FIG. 1 is a diagram illustrating the overall configuration of a power supply device according to an embodiment of the present disclosure. FIG. 2 is a diagram illustrating three possible states of four switching elements according to an embodiment of the present disclosure. FIG. 3 is a diagram illustrating the flow of current when switching control is performed in a power supply device according to an embodiment of the present disclosure. FIG. 4 is a diagram illustrating an example of the internal configuration of a control circuit according to an embodiment of the present disclosure. FIG. 5 is a timing chart of a power supply device in a heavy load state according to an embodiment of the present disclosure. FIG. 6 is a diagram illustrating the relationship between a feedback voltage and an output signal of a light load detection circuit according to a first example of an embodiment of the present disclosure. FIG. 7 is a flowchart of a power supply device according to a first example of an embodiment of the present disclosure. FIG. 8 is a timing chart of a power supply device in a light load state according to a first example of an embodiment of the present disclosure. FIG. 9 is a timing chart of a power supply device in a light load state according to a first example of an embodiment of the present disclosure. FIG. 10 is a flowchart of a power supply device according to a second example of an embodiment of the present disclosure.

[0007] [Detailed Description] Hereinafter, examples of embodiments of the present disclosure will be specifically described with reference to the drawings. In each of the drawings referred to, the same parts are designated by the same reference numerals, and duplicate descriptions of the same parts will be omitted as a general rule. In this specification, for the sake of simplicity, symbols or signs referring to information, signals, physical quantities, functional units, circuits, elements, or components may be used, and the names of the information, signals, physical quantities, functional units, circuits, elements, or components corresponding to the symbols or signs may be omitted or abbreviated.

[0008] First, some terms used in describing the embodiments of the present disclosure will be explained. Ground refers to a reference conductive part having a reference potential of 0 V (zero volts) or the 0 V reference potential itself. When a component, electrode, or node is connected to ground, it means that the component, electrode, or node is connected to a reference node having a reference potential of 0 V. The reference node and ground can be read interchangeably.

[0009] A level refers to the level of potential, and for any given signal or voltage, a high level has a higher potential than a low level. For any given signal or voltage, a high level signal or voltage strictly means that the signal or voltage level is high, and a low level signal or voltage strictly means that the signal or voltage level is low. For any given signal or voltage, a transition from a low level to a high level is called a rising edge, and a transition from a high level to a low level is called a falling edge.

[0010] Any switching element can be configured with a transistor. For any transistor configured as a FET (field effect transistor), including a MOSFET, the on state refers to a state in which the drain and source of the transistor are conductive, and the off state refers to a state in which the drain and source of the transistor are non-conductive (cut-off state). The same applies to transistors not classified as FETs. Unless otherwise specified, a MOSFET is understood to be an enhancement-type MOSFET. MOSFET is an abbreviation for "metal-oxide-semiconductor field-effect transistor." Furthermore, unless otherwise specified, the back gate of any MOSFET can be considered to be short-circuited to the source.

[0011] Hereinafter, the on and off states of any switching element (transistor) may be simply referred to as on and off. For any switching element, switching from the off state to the on state is referred to as turning on, and switching from the on state to the off state is referred to as turning off. Furthermore, for any switching element, the period during which the switching element is in the on state is referred to as the on period, and the period during which the switching element is in the off state is referred to as the off period.

[0012] For any signal that takes a high or low signal level, the period during which the signal level is high is referred to as a high-level period, and the period during which the signal level is low is referred to as a low-level period. The same applies to any voltage that takes a high or low voltage level.

[0013] Unless otherwise specified, the connection between a plurality of parts forming a circuit, such as any circuit element, wiring, or node, may be understood to refer to an electrical connection.

[0014] If two arbitrary voltages to be compared are voltages v1 and v2, then "v1>v2" indicates that voltage v1 is higher than voltage v2, and "v1<v2" indicates that voltage v1 is lower than voltage v2. The same applies to other equations that include physical quantities other than voltage.

[0015] 1 shows the overall configuration of a power supply device 1 according to an embodiment of the present disclosure. The power supply device 1 receives a positive input voltage V IN is supplied, and the input voltage V IN By stepping down the voltage, a positive output voltage V OUT Generates an output voltage V OUT is the input voltage V IN The power supply 1 has an output voltage V OUT That is, in a steady state, the output voltage V OUT The target voltage is substantially equal to the target voltage. Hereinafter, the target voltage is referred to as "V TG In the power supply device 1, the intermediate voltage V MID is generated. The output voltage V OUT is the intermediate voltage V MID Also, in the steady state, the intermediate voltage V MID is essentially the input voltage V IN Therefore, "V IN >2 x V OUT " is true. "V IN >2 x V OUT As long as " is true, the input voltage V IN and output voltage V OUT The value of "V" is arbitrary. IN >2 x V TG As long as " is true, the input voltage VIN and target voltage V TG The value of is arbitrary. For example, the input voltage V IN is 48V, and the target voltage V TG (i.e., the output voltage V OUT ) is 12V or 5V.

[0016] Regarding the power supply device 1, the steady state is when the output voltage V OUT rises from 0V to the target voltage V TG After reaching OUT is the target voltage V TG This refers to a state in which the temperature is stabilized at .

[0017] The power supply device 1 includes switching elements M1 to M4 and a capacitor C FLY , C MID and C OUT , an inductor L1, and a control circuit 30. FLY can be called a flying capacitor. MID can be referred to as the intermediate capacitor. OUT can be referred to as the output capacitor.

[0018] The power supply device 1 includes a buck converter and a stacked converter. The buck converter in the power supply device 1 includes switching elements M1 and M2 and an inductor L1, and outputs an intermediate voltage V MID By lowering the voltage at the output node ND OUT Output voltage V OUT The capacitor C OUT The switching elements M1 and M2 function as a low-side switching element and a high-side switching element in the buck converter. The stacked converter in the power supply device 1 includes the switching elements M3 and M4 and the capacitor C FLY and an input voltage V IN to intermediate voltage V MID The capacitor C MID can be understood to be included in the components of the stacked converter.

[0019] In this embodiment, the switching elements M1 to M4 are each configured by an N-channel MOSFET, and therefore hereinafter may be referred to as transistors M1 to M4.

[0020] The transistors M1 to M4 are connected in series between the ground and a node ND4. The transistor M1 is provided between the ground and the node ND1, the transistor M2 is provided between the nodes ND1 and ND2, the transistor M3 is provided between the nodes ND2 and ND3, and the transistor M4 is provided between the nodes ND3 and ND4. More specifically, the source of the transistor M1 is connected to the ground. The drain of the transistor M1 and the source of the transistor M2 are connected to the node ND1. The drain of the transistor M2 and the source of the transistor M3 are connected to the node ND2. The drain of the transistor M3 and the source of the transistor M4 are connected to the node ND3. The drain of the transistor M4 is connected to the node ND4. The node ND4 is connected to the input voltage V IN That is, the node ND4 is a power supply node that receives the input voltage V IN The signals supplied to the gates of the transistors M1 to M4 are referred to as gate signals G1 to G4, respectively.

[0021] Capacitor C FLY is provided between the nodes ND3 and ND1. That is, the capacitor C FLY The first end of the capacitor C is connected to the node ND3. FLY The second end of the transistor ND1 is connected to the node ND1.

[0022] Capacitor C MID is provided between the node ND2 and the ground. That is, the capacitor C MID The first end of the capacitor C is connected to the node ND2. MID The second end of the capacitor C is connected to ground. MID The first end of the capacitor C MID The voltage at node ND2 corresponds to the positive electrode of the intermediate voltage V MID That is, the capacitor C MID An intermediate voltage V MIDoccurs.

[0023] The inductor L1 is connected between the node ND1 and the output node ND OUT That is, a first end of the inductor L1 is connected to the node ND1, and a second end of the inductor L1 is connected to the output node ND OUT is connected to.

[0024] Capacitor C OUT is the output node ND OUT and ground. That is, the capacitor C OUT The first end of the output node ND OUT and a capacitor C OUT The second end of the capacitor C is connected to ground. OUT The first end of the capacitor C OUT This corresponds to the positive electrode of the output node ND. OUT The voltage at is the output voltage V OUT That is, the capacitor C OUT An output voltage V OUT occurs.

[0025] The control circuit 30 is connected to the gates of the transistors M1 to M4, and controls the states (on / off states) of the transistors M1 to M4 individually by supplying gate signals G1 to G4 to the transistors M1 to M4. By controlling the states of the transistors M1 to M4 with the control circuit 30, the input voltage V IN The lower desired output voltage V OUT is the output node ND OUT The control circuit 30 may be formed of a semiconductor integrated circuit.

[0026] Any of the gate signals G1 to G4 will be referred to as the gate signal Gx. Of the transistors M1 to M4, the transistor that receives the gate signal Gx at its gate will be referred to as the transistor Mx. When the gate signal Gx is at a high level, the transistor Mx is on, and when the gate signal Gx is at a low level, the transistor Mx is off. Therefore, during the high-level period of the gate signal G1, the transistor M1 is on, and during the low-level period of the gate signal G1, the transistor M1 is off. Similarly, during the high-level period of the gate signal G2, the transistor M2 is on, and during the low-level period of the gate signal G2, the transistor M2 is off. The same is true for the transistors M3 and M4. A high-level gate signal Gx has a potential higher than the potential that is higher than the source potential of the transistor Mx by the gate threshold voltage of the transistor Mx. A low-level gate signal Gx may have a potential equivalent to the source potential of the transistor Mx.

[0027] Output node ND OUT is connected to a load (not shown). The load is connected to an output voltage V OUT The output node ND is an arbitrary load that drives the OUT The current supplied to the load from LD The load current I LD corresponds to the output current of the power supply device 1. The current flowing through the inductor L1 is the inductor current I L The node ND1 to the output node ND OUT The inductor current I L has a positive polarity, and the output node ND OUT An inductor current I flows from the node L is assumed to have negative polarity.

[0028] The control circuit 30 can set the states of the transistors M1 to M4 to any of states ST1, ST2, and ST3 shown in FIG. 2. That is, the control circuit 30 can switch the states of the transistors M1 to M4 between states ST1, ST2, and ST3. In state ST1, the transistors M2 and M4 are on and the transistors M1 and M3 are off. In state ST2, the transistors M2 and M4 are off and the transistors M1 and M3 are on. In state ST3, the transistors M1 to M4 are all off.

[0029] The control circuit 30 can perform switching control to alternately switch the states of the transistors M1 to M4 between states ST1 and ST2. The current generated when the switching control is performed will be described with reference to FIG. 3. The capacitor C FLY (i.e., the potential at the node ND1) as a reference. FLY The current that increases the potential at the first end of the capacitor C FLY The reverse current is the charging current of the capacitor C FLY is the discharge current of the capacitor C MID Regarding the intermediate voltage V MID The current that increases the intermediate voltage V MID The current that decreases the capacitance is the discharge current.

[0030] In state ST1, currents 811 and 813 are generated. The current 811 flows through the capacitor C MID from the output node ND through the transistor M2 and the inductor L1. OUT is the current going to the capacitor C MID The current 813 is generated by the discharge of the input voltage V IN The voltage is applied from node ND4 to capacitor C FLY The current 813 flows into the capacitor C FLY is charged.

[0031] In state ST2, currents 812 and 814 are generated. The current 812 flows from ground through transistor M1 and inductor L1 to output node ND. OUT The current 814 flows into the capacitor C FLY through the transistor M3 to the capacitor C MID The current 814 flows through the capacitor C FLY is generated by the discharge of the capacitor C MID contributes to charging.

[0032] In state ST1, transistors M2 and M4 are on, so that capacitor C FLY and C MID For FLY and C MID In the state ST2, the capacitor C FLY and C MID As a result, the transistors M1 to M4 and the capacitor C FLY and C MID Therefore, in the steady state, the capacitor C MID The intermediate voltage V MID is approximately the voltage (V IN / 2) That is, the input voltage V IN The intermediate voltage V corresponds to the divided voltage of MID In this way, the control circuit 30 controls the transistors M1 to M4 and the capacitor C MID and C FLY The circuit having the intermediate voltage V MID Generates.

[0033] Meanwhile, the intermediate voltage V MID Therefore, the power supply device 1 can be called a hybrid buck converter that combines a switched capacitor circuit and a synchronous buck converter.

[0034] The switched capacitor circuit generates an input voltage V IN is reduced to half, and the resulting intermediate voltage V MID High efficiency can be achieved by further stepping down the voltage using a synchronous buck converter.

[0035] For example, if the input voltage V is 48V, IN to 12V output voltage V OUT Consider the case where a 48V input voltage V is generated. As a reference method, a simple synchronous buck converter is used to directly step down 48V to 12V. In the reference method, IN By switching between these, a square wave voltage (a square wave voltage that fluctuates between approximately 0 V and 48 V) is generated, and the square wave voltage is rectified and smoothed to obtain an output voltage of 12 V. In contrast, in the power supply device 1, the voltage (V IN / 2) to generate a square wave voltage (a square wave voltage that fluctuates between approximately 0 V and 24 V), which is then rectified and smoothed to obtain an output voltage of 12 V. Therefore, compared to power supply devices according to the reference method, power supply device 1 can keep switching losses low.

[0036] There are several factors that contribute to the reduction of switching loss, some of which are listed below. In the reference method, the switching duty is relatively small. When the switching duty is relatively small, the effects of losses during periods when the instantaneous value of the square wave voltage rises and falls become relatively large. In contrast, when the power supply device 1 is used, the input voltage to the synchronous buck converter is a voltage (V IN / 2), the switching duty is relatively large compared to the reference method, which leads to an improvement in switching loss. Also, various parasitic capacitances are charged and discharged during the switching process, but in the power supply device 1, the input voltage to the synchronous buck converter is a voltage (V IN / 2), the loss due to charging and discharging of the parasitic capacitance can be kept relatively low compared to the reference method.

[0037] 4 shows a block diagram of the power supply device 1, illustrating an example of the internal configuration of the control circuit 30. FIG. 5 shows a timing chart of the power supply device 1 under heavy load conditions. The load current ILD When is sufficiently large, the signal S LLM The signal S is maintained at a low level. LLM For convenience, the state in which "I" is maintained at a low level is referred to as a heavy load state. L The power supply device 1 operates in a continuous current mode where the signal S LLM When the switch voltage V is maintained at a low level, the switching control is continuously performed. SW , inductor current I L , error voltage V ERR , slope voltage V SLP , signal CLK, CMPOUT, G1, G2, G3, G4, S LLM , S ZX The waveform of the signal S LLM When is maintained at a low level, the signal S ZX The switch voltage V SW is the voltage at node ND1.

[0038] The control circuit 30 includes an error amplifier 31, a ramp circuit 32, a current information acquisition circuit 33, an adder 34, a PWM comparator 35, an oscillation circuit 36, a controller 37, a light load detection circuit 38, a reverse current detection circuit 39, and a clamp circuit 40. The power supply device 1 is also provided with resistors R1 and R2. A first end of the resistor R1 is connected to an output node ND OUT The second end of the resistor R1 is connected to the first end of the resistor R2, and the second end of the resistor R2 is connected to ground. An output voltage V OUT Feedback voltage V according to FB The feedback voltage V FB is the output voltage V OUT Therefore, the output voltage V OUT The resistors R1 and R2 are proportional to the feedback voltage V FB A feedback voltage generating circuit is formed to generate the feedback voltage V FB is supplied to the control circuit 30. However, it may be understood that the feedback voltage generating circuit is included in the components of the control circuit 30. OUT It is the feedback voltage V FBIn any case, the feedback voltage V FB is the output voltage V OUT Information on the output voltage V OUT It contains information indicating the value of

[0039] The error amplifier 31 is a current output type transconductance amplifier. The error amplifier 31 has an inverting input terminal, a non-inverting input terminal, and an output terminal. A feedback voltage V FB A predetermined reference voltage V REF The reference voltage V REF is a DC voltage having a predetermined positive voltage value, and is generated by a reference voltage generating circuit (not shown) in the control circuit 30. The output terminal of the error amplifier 31 is connected to the wiring WR ERR When the power supply device 1 is started, the reference voltage V REF Although a soft start control may be performed to gradually increase the value of from 0 V to a predetermined positive voltage value, the existence of the soft start control will be ignored below.

[0040] The error amplifier 31 outputs a feedback voltage V FB and the reference voltage V REF By outputting a current signal corresponding to the difference between the feedback voltage V FB and the reference voltage V REF Error voltage V according to the difference between ERR Wiring WR ERR Specifically, the error amplifier 31 generates a feedback voltage V FB is the reference voltage V REF When the error voltage V ERR Wiring WR from its own output terminal so that ERR and outputs a current to the feedback voltage V FB is the reference voltage V REF When the error voltage V ERR Wiring WR to reduce ERR The current is drawn from the wiring WR ERR A phase compensation circuit including a capacitor may be connected between the input and ground.

[0041] The ramp circuit 32 generates a predetermined initial voltage V INT The ramp voltage V monotonically increases at a predetermined rate of change from RAMP In the ramp circuit 32, an initial voltage V INT is, for example, 0 V, but may be different from 0 V. During the off period of the transistor M2, the ramp voltage V RAMP is the initial voltage V INT It is fixed in place.

[0042] The current information acquisition circuit 33 acquires current information of the inductor L1 and outputs a sense voltage V IL The current information of the inductor L1 is the inductor current I L This is information indicating the value of the sense voltage V IL is a positive proportional coefficient and the inductor current I L Therefore, the inductor current I L As the sense voltage V IL rises, and the inductor current I L With the decrease in the sense voltage V IL For example, "V IL = k IV ×I L " may be. IV is a predetermined positive coefficient.

[0043] Sense voltage V IL indicates the current information of the inductor L1, the sense voltage V IL The method for generating the inductor current I L By directly detecting the current with a current sensor, the sense voltage V IL The current sensor here may be a shunt resistor (not shown) inserted in series between the inductor L1 and the node ND1. Alternatively, for example, the current flowing through the transistor M2 during the ON period of the transistor M2 (therefore, the inductor current I L ) or by detecting the current flowing through the transistor M1 during the ON period of the transistor M1 (thus the inductor current I L ) is detected, the sense voltage V ILAlternatively, the inductor current I L By detecting the voltage at any point where a voltage corresponding to IL may be generated.

[0044] The adder 34 calculates the lamp voltage V RAMP With respect to the sense voltage V IL By adding these, the slope voltage V SLP That is, "V SLP =V RAMP +V IL "

[0045] The PWM comparator 35 outputs the error voltage V ERR and the slope voltage V SLP The PWM comparator 35 compares the error voltage V ERR is input, and the slope voltage V SLP is input to the PWM comparator 35. SLP <V ERR " is established, a low level signal CMPOUT is output, and "V SLP >V ERR " is established, a high level signal CMPOUT is output. SLP =V ERR When "is established," the signal CMPOUT has a low level or a high level.

[0046] The oscillator circuit 36 ​​generates and outputs a clock signal CLK by oscillating. The clock signal CLK has a predetermined frequency f PWM The clock signal CLK is a rectangular wave signal having a frequency f and alternates between high and low levels. The duty of the clock signal CLK is arbitrary. In this example, the clock signal CLK has a low level in principle and a frequency f PWM The signal S is kept at a high level for a short time at intervals equal to the reciprocal of the time (see FIG. 5). LLM is input, but the signal S LLM The effect of this on the operation of the oscillator circuit 36 ​​will be described later.

[0047] A signal CMPOUT and a clock signal CLK are input to a controller 37. The controller 37 is connected to the gates of the transistors M1 to M4 and supplies gate signals G1 to G4 to the transistors M1 to M4. In the switching control, the controller 37 turns on the transistors M2 and M4 by generating a rising edge in the gate signals G2 and G4 (i.e., by switching the levels of the gate signals G2 and G4 from low to high) in response to a predetermined level change in the clock signal CLK, and turns off the transistors M1 and M3 by generating a falling edge in the gate signals G1 and G3 (i.e., by switching the levels of the gate signals G1 and G3 from high to low). In this example, the predetermined level change in the clock signal CLK is a change from low to high in the clock signal CLK, but it may also be a change from high to low in the clock signal CLK.

[0048] After transistors M2 and M4 are turned on and transistors M1 and M3 are turned off, the slope voltage V SLP After a monotonous rise in SLP <V ERR "From the established state of "V SLP >V ERR In the switching control, when a rising edge occurs in the signal CMPOUT, the controller 37 generates a falling edge in the gate signals G2 and G4 to turn off the transistors M2 and M4, and generates a rising edge in the gate signals G1 and G3 to turn on the transistors M1 and M3. As the transistor M2 turns off, the ramp voltage V RAMP is a sufficiently low initial voltage V INT Since it decreases to "V SLP <V ERR” is established, and a falling edge is quickly generated in the signal CMPOUT. In the switching control, the time from when the transistors M2 and M4 are turned on and the transistors M1 and M3 are turned off to when the transistors M2 and M4 are turned off and the transistors M1 and M3 are turned on is defined as time t ON It is called.

[0049] "V OUT =V TG "When "V FB =V REF "V OUT =V TG Starting from the state where " LD Through the increase of "V OUT <V TG "So, "V FB <V REF " so the error voltage V ERR The error voltage V ERR The increase in the ON period of the transistor M2 causes the inductor current I L increases, resulting in an output voltage V OUT is the target voltage V TG On the other hand, "V OUT =V TG Starting from the state where " LD Through the decrease of "V OUT >V TG "So, "V FB >V REF " so the error voltage V ERR The error voltage V ERR The decrease in the ON period of the transistor M2 reduces the inductor current I L decreases, resulting in the output voltage V OUT is the target voltage V TG In this way, in switching control, the output voltage V OUT and target voltage V TG Control is performed to reduce the difference between the

[0050] The above-mentioned time tON is the error voltage V ERR (and hence the output voltage V OUT ) and the sense voltage V IL (and therefore depends on the current information of the inductor L1). In other words, the controller 37 controls the output voltage V OUT Based on the information on the current of the inductor L1 and the current information of the inductor L2, the controller 37 controls the switching of the transistors M1 to M4 in synchronization with the clock signal CLK. In the switching control, the controller 37 turns on the transistors M2 and M4 and turns off the transistors M1 and M3 in response to a predetermined level change in the clock signal CLK, and then controls the output voltage V OUT and the time t ON After this time has elapsed, transistors M2 and M4 are turned off and transistors M1 and M3 are turned on.

[0051] The controller 37 controls the capacitor C MID An intermediate voltage V MID and generates an intermediate voltage V in a buck converter including transistors M1 and M2 and inductor L1. MID By lowering the voltage at the output node ND OUT Output voltage V OUT Generates.

[0052] The feedback voltage V FB The light load detection circuit 38 detects the feedback voltage V FB Based on the load current I LD and outputs a light load detection signal S LLM The signal S LLM is a binary signal having a low level or a high level. LD When is relatively large, the signal S LLM is maintained at a low level, but the load current I LD When is relatively small, the signal S LLM The light load detection circuit 38 includes at least a comparator 38a.FB and a predetermined light load threshold voltage V LLM Here, the feedback voltage V is input to the non-inverting input terminal of the comparator 38a. FB is input, and the light load threshold voltage V LLM is input. The light load threshold voltage V LLM has a predetermined positive DC voltage value, and the reference voltage V REF The feedback voltage V FB is the light load threshold voltage V LLM and the comparison result is the signal S LLM The feedback voltage V FB When is sufficiently low, the signal S LLM has a low level. The feedback voltage V FB By increasing FB >V LLM " is established, the signal S LLM The signal S has a high level. A detailed example of the operation of the light load detection circuit 38 will be described later. LLM is input to the oscillator circuit 36 ​​and the controller 37 .

[0053] The reverse current detection circuit 39 is connected to the node ND1 and the ground. For example, the reverse current detection circuit 39 detects the switch voltage V SW is compared with the ground potential to detect the presence or absence of a backflow current, and a signal S indicating the detection result is output. ZX Generates a signal S ZX is a binary signal having a low level or a high level. ZX is set to a low level, and when a reverse current is detected, a signal S ZX (i.e., the one-shot pulse is switched to the signal S ZX The reverse current is a current that flows from the node ND1 to the ground via the transistor M1, and is a negative inductor current I L During the on-period of the transistor M1, the inductor current I LThe phenomenon in which the polarity of the signal S is inverted from positive to negative (in other words, the phenomenon in which the potential of the node ND1 is inverted from negative to positive) is also called a zero crossing. ZX can be referred to as a zero crossing detection signal or a backflow detection signal.

[0054] The reverse current detection circuit 39 typically detects the switch voltage V SW By monitoring the polarity of the signal S ZX However, the reverse current detection circuit 39 may generate the switch voltage V SW is compared with a predetermined small positive or negative voltage, the signal S ZX That is, the reverse current detection circuit 39 may generate a voltage between the ground and the node ND1 (i.e., a switching voltage V SW ) based on the inductor current I L determines whether a predetermined backflow condition is satisfied, and based on the determination result, outputs a signal S ZX In principle, the backflow detection circuit 39 generates a signal S ZX The level of the signal S is set to a low level, and only when the backflow condition is met is it determined that a backflow current has been detected and the signal S is output for a predetermined short time. ZX (i.e., the one-shot pulse is switched to the signal S ZX (Include in

[0055] The backflow condition may be the following first, second, or third condition. A backflow detection comparator (not shown) may be provided in the backflow detection circuit 39. The backflow detection comparator detects the switch voltage V SW The (determination voltage) may be compared with a predetermined backflow threshold voltage, and based on the comparison result, it may be determined whether the first, second or third condition is met.

[0056] The first condition is that during the on-period of the transistor M1, the switch voltage V SW In other words, during the on-period of the transistor M1, the inductor current I L When the polarity of V is reversed from positive to negative, the first condition is met. When the first condition is a backflow condition, the backflow detection comparator detects the switch voltage VSW is compared with the reverse threshold voltage of 0 V. The ON period of the transistor M1 coincides with the period during which the states of the transistors M1 to M4 are set to state ST2.

[0057] The second condition is that during the on-period of the transistor M1, the switch voltage V SW After the polarity of V is reversed from negative to positive, SW In other words, during the ON period of the transistor M1, the inductor current I L After the polarity of reverses from positive to negative, the inductor current I L When the magnitude of the reverse current threshold voltage V reaches a predetermined value or more, the second condition is met. When the second condition is a reverse current condition, a positive reverse current threshold voltage (for example, +3 mV) is set as the reverse current threshold voltage, and the reverse current detection comparator detects the switch voltage V SW can be compared with the reverse current threshold voltage.

[0058] The third condition is that during the on-period of the transistor M1, the switch voltage V SW The polarity of the switch voltage V SW In other words, during the on-period of the transistor M1, the inductor current I L When the polarity of the inductor current I L When the magnitude of the reverse current threshold voltage V falls below a predetermined value, the third condition is met. When the third condition is a reverse current condition, a negative reverse current threshold voltage (for example, −3 mV) is set as the reverse current threshold voltage, and the reverse current detection comparator detects the switch voltage V SW can be compared with the reverse current threshold voltage.

[0059] The reverse current threshold voltage may be changeable in the power supply device 1. For example, the reverse current threshold voltage may be variably set according to the value of a resistor externally connected to an external terminal of an electronic component that includes the control circuit 30. Alternatively, the reverse current threshold voltage may be variably set based on a command supplied to the control circuit 30 from a higher-level system (not shown).

[0060] The clamp circuit 40 is connected to the wiring WR ERR and the error voltage V ERRThe error voltage V ERR The significance of providing the clamp circuit 40 will be described later.

[0061] Below, several specific configuration examples, operation examples, application techniques, modified techniques, etc. related to the power supply device 1 will be described in multiple embodiments. The matters described above in this embodiment apply to each of the following embodiments unless otherwise specified and unless there is a contradiction. If there are any matters in each embodiment that contradict the matters described above, the description in that embodiment may take precedence. Furthermore, unless there is a contradiction, the matters described in any of the multiple embodiments shown below can also be applied to any of the other embodiments (i.e., any two or more of the multiple embodiments can be combined).

[0062] First Embodiment A first embodiment will be described. FB and the signal S output from the light load detection circuit 38 LLM The light load detection circuit 38 detects a light load threshold voltage V LLM In addition to the release voltage V CNCL is defined as the release voltage V CNCL is the light load threshold voltage V LLM Here, the reference voltage V REF is the release voltage V CNCL (i.e., "V CNCL =V REF "). However, the release voltage V CNCL is the reference voltage V REF The voltage may be slightly higher or slightly lower than the voltage.

[0063] The light load detection circuit 38 is FB <V CNCL When " is established, the signal S LLM The signal S is fixed to a low level. LLM is at a low level, the feedback voltage V FB As a result, the feedback voltage V FB is the light load threshold voltage V LLM When the load exceeds the threshold, the light load detection circuit 38 outputs a signal S LLM Switches the signal S from low level to high level.LLM After becoming high level, the feedback voltage V FB is the release voltage V CNCL Unless the load drops below 100 kΩ, the light load detection circuit 38 outputs the signal S LLM The signal S is maintained at a high level. LLM After becoming high level, the feedback voltage V FB is the release voltage V CNCL When the load falls below this level, the light load detection circuit 38 outputs a signal S LLM Switch from high level to low level.

[0064] To achieve the above operation, the differential voltage (V LLM -V CNCL In this case, the output signal of the comparator 38a itself may be used as the signal S LLM Alternatively, the feedback voltage V FB is the light load threshold voltage V LLM a first comparator (corresponding to comparator 38a) that compares the feedback voltage V FB release voltage V CNCL and a second comparator for comparing the signal S with the characteristic shown in FIG. 6 based on the comparison results of the comparators. LLM A hysteresis characteristic may be provided to each of the first and second comparators.

[0065] 7 shows a flowchart of the operation of the power supply device 1. The flowchart in FIG. 7 can also be considered a state transition diagram of the power supply device 1 (the same applies to the flowchart in FIG. 10 described later). In step S11, the feedback voltage V FB is low enough, and at least FB <V CNCL " is established, the signal S LLM is at a low level. Then, a transition from step S11 to step S12 occurs. In step S12, the control circuit 30 executes the above-described switching control. The switching control alternates the states of the transistors M1 to M4 between states ST1 and ST2.

[0066] In step S13 following step S12, the control circuit 30FB >V LLM Specifically, in step S13, the signal S LLM In step S13, it is determined whether "V FB >V LLM " is established (i.e., signal S LLM is high), a transition occurs from step S13 to step S14. FB >V LLM If the condition "is not satisfied (i.e., the signal S LLM is at a low level), the process returns from step S13 to step S12, and the switching control continues to be executed.

[0067] In a heavy load state, the transition to step S14 does not occur, and the loop operation consisting of steps S12 and S13 is repeatedly executed. On the other hand, in a light load state, the transition to step S14 occurs. LLM The load current I LD refers to a state where is small.

[0068] 8 and 9 are timing charts of the power supply device 1 in a light load state. Note that the load current I LD is the load current I when the timing chart of FIG. 9 is observed. LD The load current I LD is the load current I in a light load state LD is greater than.

[0069] Therefore, it can be considered as follows: In a heavy load state, the load current I LD is the current value I VAL1 That is, the load current I LD is the current value I VAL1 , the transition to step S14 does not occur and the switching control continues. LD is the current value I VAL2 or I VAL3In the light load state, a transition to step S14 occurs. VAL1 >I VAL2 >I VAL3 >0" is assumed to be true.

[0070] In the case of operating under light load conditions, the load current I LD is a sufficiently small current value I VAL3 In the case where "V FB <V CNCL The backflow condition is met in step S15 before the condition "" is met, and therefore the loop operation via steps S12 to S17 is repeatedly executed. LD is the current value I VAL3 10 is a timing chart showing the timing when the

[0071] In the case of operating under light load conditions, the load current I LD is the current value I VAL2 In the case of FB <V CNCL ” is established, the loop operation consisting of steps S12, S13, S14, S15 and S18 is repeatedly executed. LD is the current value I VAL2 10 is a timing chart showing the timing when the

[0072] The processing from step S14 onwards in Figure 7 will be described in detail. In step S14, the control circuit 30 stops the switching control and sets the state of the transistors M1 to M4 to state ST2 (see Figure 2). After step S14, the process proceeds to step S15. In step S15, the control circuit 30 determines whether the backflow condition is met. During the period in which the switching control is stopped and the state of the transistors M1 to M4 is set to state ST2, the control circuit 30 controls the switch voltage V SW (i.e., based on the voltage between the ground and the node ND1), it can be determined whether the backflow condition is met. The backflow condition here may be any of the first to third conditions described above. Only when the backflow condition is met, the signal S ZXWhen the backflow condition is met in step S15, the controller 37 transitions to step S16. ZX When the signal S goes high, a transition to step S16 occurs. If the backflow condition is not satisfied in step S15, a transition to step S18 occurs. ZX If is maintained at a low level, the controller 37 will cause a transition to step S18.

[0073] In step S16, the control circuit 30 sets the states of the transistors M1 to M4 to state ST3 (see FIG. 2). In step S17 following step S16, the control circuit 30 sets the state of the transistors M1 to M4 to state ST3 (see FIG. 2). FB <V CNCL After the transition to step S16, the success or failure of "V FB <V CNCL Unless "V FB <V CNCL If the condition "is satisfied," the control circuit 30 transitions from step S17 to step S12, and resumes the switching control in step S12. The controller 37 outputs the signal S LLM When the signal is switched from high to low, a transition from step S17 to step S12 occurs. After that, the operations from step S12 onwards are repeated.

[0074] In step S18, the control circuit 30 FB <V CNCL In step S18, it is determined whether "V FB <V CNCL If " is not established, the process returns to step S15, and the determination process of step S15 is executed again. FB <V CNCL If the condition "is satisfied," the control circuit 30 transitions from step S18 to step S12, and resumes the switching control in step S12. The controller 37 outputs the signal S LLMWhen the signal is switched from high to low, a transition from step S18 to step S12 occurs. After that, the operations from step S12 onwards are repeated.

[0075] Referring to FIG. 8, the load current I LD is a sufficiently small current value I VAL3 In the case of FIG. 8, as time progresses, the power supply 1 operates at time t A1 , t A2 , t A3 , t A4 , t A5 However, they will be visited in this order.

[0076] In the case of FIG. 8, at time t A1 It is assumed that switching control is stopped until just before time t A1 In "V FB <V CNCL " is established, and therefore the signal S LLM has a low level. Therefore, at time t A1 The switching control is started at time t A1 The inductor current I L As the voltage increases with fluctuations, the output voltage V OUT and feedback voltage V FB gradually increases. At time t A2 The boundary is "V FB <V LLM "From the established state of "V FB >V LLM " is established, and therefore, at time t A2 Signal S LLM A rising edge occurs.

[0077] Time t A2 Signal S at LLM The transition from step S13 to step S14 occurs at the rising edge of the A2 Signal S at LLM In response to the rising edge of the signal , the switching control is stopped, and the states of the transistors M1 to M4 are set and fixed to the state ST2 (step S14).

[0078] However, time t A2 (Signal S LLM If the states of the transistors M1 to M4 are in state ST1 at time t (the time when a rising edge occurs in the signal CMPOUT), the controller 37 maintains the states of the transistors M1 to M4 in state ST1 until the next rising edge of the signal CMPOUT occurs, and when the rising edge of the signal CMPOUT occurs, the controller 37 switches the states of the transistors M1 to M4 to state ST2, and thereafter fixes the states of the transistors M1 to M4 to state ST2. A2 If the states of the transistors M1 to M4 are in state ST1 at time t, the controller 37 may immediately switch the states of the transistors M1 to M4 from state ST1 to state ST2 without waiting for the next rising edge of the signal CMPOUT, and thereafter fix the states at state ST2. A2 If the states of the transistors M1 to M4 are in state ST2 in step ST1, the controller 37 fixes the states of the transistors M1 to M4 to state ST2.

[0079] In the case of FIG. 8, at time t A2 Signal S at LLM The inductor current I L decreases, and at time t A3 In the case of FIG. 8, the backflow condition is met at time t A2 Hereafter, the output voltage V OUT and feedback voltage V FB Although gradually decreases, at time t A3 So, "V FB >V CNCL In other words, in the case of FIG. 8, after the switching control is stopped (step S14), FB <V CNCL Before " is established, time t A3 The backflow condition is met at time t A3 Signal S ZX is set to a high level for a short time, and the controller 37 outputs a high level signal S ZXIn response to this, the states of the transistors M1 to M4 are switched from state ST2 to state ST3 (step S16). A5 The states of the transistors M1 to M4 are fixed at state ST3 until switching control is resumed at step ST1.

[0080] By fixing the states of the transistors M1 to M4 to the state ST3, the reverse current is suppressed, and loss in a light load state is reduced. A3 The output voltage V OUT and feedback voltage V FB The decrease continues. Then, at time t A4 The boundary is "V FB >V CNCL "From the established state of "V FB <V CNCL " is established, and therefore, at time t A4 Signal S LLM A fall edge occurs.

[0081] The controller 37 A4 Signal S at LLM (i.e., the low level signal S LLM , switching control is resumed by generating a transition from step S17 to step S12. LLM There may be a delay depending on the circuit configuration in the control circuit 30 from the falling edge of time t A4 A time t slightly delayed from A5 That is, at time t A5 At time t, the states of the transistors M1 to M4 are switched from state ST3 to state ST1, and thereafter, the states of the transistors M1 to M4 are alternately switched between states ST1 and ST2. A4 and time t A5 may be the same time.

[0082] Time t A5 So, "V FB <V CNCL " is established, and therefore the signal S LLM has a low level, i.e., at time tA5 The state of the power supply device 1 at time t A1 This is equivalent to the state of the power supply device 1 at time t A5 After that, at time t A1 From time t A5 The same operation as that just before is repeated.

[0083] Referring to FIG. 9, the load current I LD is the current value I VAL3 Larger current value I VAL2 In the case of FIG. 9, as time progresses, the power supply 1 operates at time t B1 , t B2 , t B3 , t B4 However, they will be visited in this order.

[0084] In the case of FIG. 9, at time t B1 It is assumed that switching control is stopped until just before time t B1 In "V FB <V CNCL " is established, and therefore the signal S LLM has a low level. Therefore, at time t B1 The switching control is started at time t B1 The inductor current I L As the voltage increases with fluctuations, the output voltage V OUT and feedback voltage V FB gradually increases. At time t B2 The boundary is "V FB <V LLM "From the established state of "V FB >V LLM " is established, and therefore, at time t B2 Signal S LLM A rising edge occurs.

[0085] Time t B2 Signal S at LLM The transition from step S13 to step S14 occurs at the rising edge of the B2 Signal S at LLMIn response to the rising edge of the signal , the switching control is stopped, and the states of the transistors M1 to M4 are set and fixed to the state ST2 (step S14).

[0086] However, time t B2 (Signal S LLM If the states of the transistors M1 to M4 are in state ST1 at time t (the time when a rising edge occurs in the signal CMPOUT), the controller 37 maintains the states of the transistors M1 to M4 in state ST1 until the next rising edge of the signal CMPOUT occurs, and when the rising edge of the signal CMPOUT occurs, the controller 37 switches the states of the transistors M1 to M4 to state ST2, and thereafter fixes the states of the transistors M1 to M4 to state ST2. B2 If the states of the transistors M1 to M4 are in state ST1 at time t, the controller 37 may immediately switch the states of the transistors M1 to M4 from state ST1 to state ST2 without waiting for the next rising edge of the signal CMPOUT, and thereafter fix the states at state ST2. B2 If the states of the transistors M1 to M4 are in state ST2 in step ST1, the controller 37 fixes the states of the transistors M1 to M4 to state ST2.

[0087] Time t B2 Signal S at LLM The output voltage V OUT and feedback voltage V FB and the inductor current I L However, in the case of FIG. B2 After that, before the backflow condition is met, FB <V CNCL 9, after the switching control is stopped (step S14), the backflow condition is not satisfied and the time t B3 "V" FB >V CNCL "From the established state of "V FB <V CNCL 9, the backflow condition is not satisfied, so the signal S ZXis fixed at a low level, while at time t B3 Signal S LLM A fall edge occurs.

[0088] The controller 37 B3 Signal S at LLM (i.e., the low level signal S LLM , switching control is resumed by generating a transition from step S18 to step S12. LLM There may be a delay depending on the circuit configuration in the control circuit 30 from the falling edge of time t B3 A time t slightly delayed from B4 That is, at time t B4 At time t, the states of the transistors M1 to M4 are switched from state ST2 to state ST1, and thereafter, the states of the transistors M1 to M4 are alternately switched between states ST1 and ST2. B3 and time t B4 may be the same time.

[0089] Time t B4 So, "V FB <V CNCL " is established, and therefore the signal S LLM has a low level, i.e., at time t B4 The state of the power supply device 1 at time t B1 This is equivalent to the state of the power supply device 1 at time t B4 After that, at time t B1 From time t B4 The same operation as that just before is repeated.

[0090] As described above, in the hybrid buck converter (power supply device 1) that combines a switched capacitor circuit and a synchronous buck converter, control is performed to stop switching control and to turn off all of transistors M1 to M4 under light load conditions, thereby suppressing losses under light load conditions and improving the efficiency of the power supply device 1.

[0091] Second Embodiment A second embodiment will be described. In state ST3, the capacitor C MID Although the accumulated charge is maintained, in reality, the intermediate voltage V MID When the switching control is stopped and then resumed, the intermediate voltage V MID If the inductor current I is excessively low, the inductor current I required immediately after the switching control is restarted will be L is not obtained, and the output voltage V OUT The stability of the system may be impaired.

[0092] Taking this into consideration, the control circuit 30 according to the second embodiment sets the states of the transistors M1 to M4 to the state ST3 by the method shown in the first embodiment, and then sets "V FB <V CNCL " and "V MID <V LL " and monitor the success or failure of each "V FB <V CNCL " and "V MID <V LL " is satisfied, the switching control is resumed. LL is the intermediate voltage V MID The lower limit voltage V LL has a positive predetermined DC voltage value. MID <V LL In order to determine whether " MID and the lower limit voltage V LL A lower limit judgment comparator (not shown) for comparing the level of the lower limit with the lower limit may be provided in the control circuit 30 , and the comparison result of the lower limit judgment comparator may be input to the controller 37 .

[0093] FIG. 10 shows a flowchart of the operation of the power supply device 1 according to the second embodiment. The flowchart of FIG. 10 is obtained by replacing step S17 in the flowchart of FIG. 7 with step S17a. Apart from this replacement, the flowcharts of FIG. 7 and FIG. 10 are identical, and the description of the first embodiment also applies to the second embodiment unless there is a contradiction. In this application, the symbol "S17" in the first embodiment is read as "S17a" in the second embodiment.

[0094] In step S16, after the states of the transistors M1 to M4 are set to state ST3, the process proceeds to step S17a in the second embodiment. FB <V CNCL " and "V MID <V LL In the second embodiment, after the transition to step S16, the success or failure of "V FB <V CNCL " and "V MID <V LL " is not satisfied, the control circuit 30 maintains the states of the transistors M1 to M4 in the state ST3. FB <V CNCL " and "V MID <V LL If at least one of the above conditions is satisfied, the control circuit 30 transitions from step S17a to step S12, and resumes the switching control in step S12. The controller 37 receives the signal S LLM is switched from a high level to a low level, or MID <V LL When the signal indicating that the condition "is satisfied" is received from the lower limit judgment comparator, a transition from step S17a to step S12 occurs.

[0095] <<Third Embodiment>> A third embodiment will be described. The operation of the clamp circuit 40 will be described. The load current I LD The decrease in the error voltage V ERR On the other hand, the clamp circuit 40 reduces the error voltage V ERR The error voltage V ERR Therefore, the error voltage V ERR When the value of is equal to the value of the clamp voltage, the load current I LD When the sense voltage V IL As the voltage V decreases, the on-duty of the buck converter consisting of the transistors M1 and M2 (the ratio of the on-period of the transistor M2 to the sum of the on-period and off-period of the transistor M2) increases. OUTThis will promote the rise of "V FB >V LLM " becomes more likely to hold. That is, the control to stop switching control under light load conditions and the control to set all of the transistors M1 to M4 to off become more likely to be performed by providing the clamp circuit 40. This contributes to suppressing losses under light load conditions. However, it is not essential to provide the clamp circuit 40 in the control circuit 30.

[0096] <<Fourth Embodiment>> A fourth embodiment will be described. The oscillator circuit 36 ​​generates a clock signal CLK by oscillating. The oscillator circuit 36 ​​generates a signal S LLM During the low level period of the signal S, the clock signal CLK is generated by an oscillation operation. LLM In this case, the oscillation operation may be stopped during the high level period of the signal S LLM However, when the oscillation operation is stopped and then resumed, it may take a considerable amount of time for the clock signal CLK to be stably generated and output.

[0097] Taking this into consideration, the following may be done: The oscillator circuit 36 ​​generates a signal S LLM During the low level period of the signal S, a clock signal CLK having a first frequency is generated by a first oscillation operation. LLM During the high level period of the first frequency f, the clock signal CLK having the second frequency is generated by the second oscillation operation. PWM The second frequency is lower than the first frequency. LLM The clock signal CLK during the high level period of the signal S does not affect the operation of the controller 37. LLM During the high level period, the states of the transistors M1 to M4 are set to the state ST2 or ST3 according to the method described above.

[0098] Signal S LLM In addition, since the second frequency is lower than the first frequency, the switching control can be resumed quickly. LLMThe power consumption of the oscillation circuit 36 ​​during the high level period of the signal S LLM can be suppressed to be lower than that during the low level period.

[0099] <<Fifth Embodiment>> A fifth embodiment will be described. A modification may be applied in which the adder 34 is removed from the control circuit 30 of FIG. 4 and current information of the inductor L1 is fed back to the error amplifier 31 instead. In this modification, "V SLP =V RAMP " and at the same time, a voltage (V ERR -V IL ) is input to the PWM comparator 35 according to this modification. SLP =V RAMP <V ERR -V IL ", the signal CMPOUT is set to a low level, and "V SLP =V RAMP >V ERR -V IL If "", the signal CMPOUT is set to high level.

[0100] <<Sixth Embodiment>> A sixth embodiment will be described. In the sixth embodiment, modified techniques, applied techniques, supplementary matters, etc. for the above-mentioned items will be described.

[0101] The power supply device 1 according to the present disclosure can be applied to any device or system that requires a stable DC voltage. For example, the power supply device 1 may be applied to a power supply system for a data center. In this case, for example, the output voltage V OUT may be 48V, and the power supply device 1 outputs an output voltage V OUT In recent years, reducing power consumption in data centers has become an important issue, and as part of this effort, there has been a shift from 12V power buses to 48V power buses. It is necessary to supply power from the 48V power bus with high efficiency to server systems or storage devices consisting of semiconductor memories, magnetic disks, etc. Use of the power supply unit 1 enables high-efficiency power supply.

[0102] Alternatively, the power supply device 1 may be applied to a primary power supply in a vehicle such as an automobile. In this case, the power supply device 1 receives an input voltage V IN Directly receives the output voltage V OUT and an output voltage V OUT The power supply device 1 may function as a driving voltage for any system (e.g., a level 3 or higher autonomous driving system) installed in the vehicle. Alternatively, for example, the power supply device 1 may be applied to a power source for a charging system. The charging system may charge the battery of an electric vehicle. Alternatively, for example, the power supply device 1 may be applied to a power source for a base station.

[0103] With respect to any signal or voltage, the relationship between the high level and the low level thereof may be reversed without prejudice to the above-mentioned gist.

[0104] The channel types of the FETs (field effect transistors) shown in each embodiment are merely examples. The channel type of any FET can be changed between P-channel and N-channel without departing from the spirit of the invention. Therefore, for example, the transistors M1 to M4 may be formed of P-channel MOSFETs, or N-channel MOSFETs and P-channel MOSFETs may be mixed among the transistors M1 to M4.

[0105] Any of the transistors described above may be any type of transistor, provided that no disadvantages arise. For example, any of the transistors described above as MOSFETs may be replaced with junction FETs, IGBTs (Insulated Gate Bipolar Transistors), or bipolar transistors, provided that no disadvantages arise. Any of the transistors has a first electrode, a second electrode, and a control electrode. In an FET, one of the first and second electrodes is the drain, the other is the source, and the control electrode is the gate. In an IGBT, one of the first and second electrodes is the collector, the other is the emitter, and the control electrode is the gate. In a bipolar transistor other than an IGBT, one of the first and second electrodes is the collector, the other is the emitter, and the control electrode is the base.

[0106] The embodiments of the present disclosure can be modified in various ways as appropriate within the scope of the technical ideas set forth in the claims. The above-described embodiments are merely examples of the present disclosure, and the meanings of the terms of the present disclosure and each constituent element are not limited to those described in the above-described embodiments. The specific numerical values ​​shown in the above description are merely examples, and as a matter of course, they can be changed to various numerical values.

[0107] <<Supplementary Notes>> Supplementary notes are provided for the present disclosure, the specific configuration examples of which have been shown in the above-described embodiments.

[0108] A power supply device according to one aspect of the present disclosure is IN ), a first switching element (M1) provided between a reference node having a potential lower than V 1 , and a first node, a second switching element (M2) provided between the first node and a second node, a third switching element (M3) provided between the second node and a third node, and a fourth switching element (M4) provided between the third node and a power supply node receiving the input voltage, and divides the input voltage by controlling the state of each switching element, and outputs an intermediate voltage (V MID ) to reduce the output voltage (V OUT ), and includes a control circuit (30) configured to switch states of the first switching element to the fourth switching element among a first state (ST1), a second state (ST2), and a third state (ST3) based on information about the output voltage and information about a current through an inductor (L1) provided between the first node and an output node to which the output voltage is applied, wherein in the first state, the second switching element and the fourth switching element are on and the first switching element and the third switching element are off, in the second state, the second switching element and the fourth switching element are off and the first switching element and the third switching element are on, and in the third state, the first switching element to the fourth switching element are all off (first configuration).

[0109] By adopting a method of dividing the input voltage before stepping it down, highly efficient step-down operation can be achieved. In this case, by enabling control to turn off all of the first through fourth switching elements, loss can be reduced under light loads, etc., and further efficiency improvements can be expected.

[0110] In the power supply device according to the first configuration, an intermediate capacitor (C MID ) and a flying capacitor (C FLY ), and the control circuit may be configured to perform switching control to switch the states of the first switching element to the fourth switching element between the first state and the second state based on information about the output voltage and information about the current of the inductor, thereby generating the intermediate voltage across the intermediate capacitor and generating the output voltage at the output node by stepping down the intermediate voltage (second configuration).

[0111] In the power supply device according to the second configuration, after the start of the switching control, the control circuit is configured to adjust the feedback voltage according to the output voltage to a predetermined light load threshold voltage (V LLM ), the switching control may be stopped and the states of the first to fourth switching elements may be set to the second state (third configuration).

[0112] In the power supply device according to the third configuration, the control circuit may be configured (fourth configuration) such that, after the start of the switching control, when the feedback voltage exceeds the light load threshold voltage, the control circuit stops the switching control and sets the states of the first to fourth switching elements to the second state, and then sets the states of the first to fourth switching elements to the third state or resumes the switching control based on the feedback voltage and the current of the inductor.

[0113] In the power supply device according to the fourth configuration, when the feedback voltage exceeds the light load threshold voltage after the start of the switching control, the control circuit stops the switching control and sets the states of the first to fourth switching elements to the second state, and thereafter, when the feedback voltage reaches a release voltage (V CNCL ), the states of the first to fourth switching elements are set to the third state, and the switching control is resumed if the feedback voltage falls below the release voltage before the current of the inductor satisfies the backflow condition (fifth configuration).

[0114] In the power supply device according to the fifth configuration, the control circuit may be configured (sixth configuration) to set the states of the first to fourth switching elements to the third state, and then resume the switching control when the feedback voltage falls below the release voltage.

[0115] In the power supply device according to the fifth configuration (see FIG. 10), after setting the states of the first to fourth switching elements to the third state, the control circuit LL ) (seventh configuration), the switching control may be resumed.

[0116] In the power supply device according to any of the fifth to seventh configurations, the control circuit may be configured (eighth configuration) to determine whether the backflow condition is met based on the voltage between the first node and the reference node during a period in which the states of the first to fourth switching elements are set to the second state during a period in which the switching control is stopped.

[0117] In the power supply device according to the eighth configuration, the control circuit generates a determination voltage (V SW) and the backflow condition is satisfied when the polarity of the judgment voltage reverses from negative to positive, when the magnitude of the judgment voltage reaches a predetermined value or more after the polarity of the judgment voltage reverses from negative to positive, or when the polarity of the judgment voltage is negative and the magnitude of the judgment voltage decreases to a predetermined value or less (ninth configuration).

[0118] In the power supply device according to any of the second to ninth configurations (see FIG. 5), the control circuit turns on the second switching element and the fourth switching element and turns off the first switching element and the third switching element in response to a predetermined level change in a predetermined clock signal (CLK), and then, for a time (t ON ) has elapsed, the second switching element and the fourth switching element are turned off and the first switching element and the third switching element are turned on (tenth configuration).

[0119] In the power supply device according to any one of the first to tenth configurations, an output capacitor (C OUT ) may be provided (eleventh configuration).

[0120] 1 Power supply device 30 Control circuit M1 to M4 Switching elements (transistors) G1 to G4 Gate signal C FLY Capacitor (Flying Capacitor) C MID Capacitor (intermediate capacitor) C OUT Capacitor (output capacitor) L1 Inductor V IN Input voltage V OUT Output voltage V MID Intermediate voltage ND1 to ND4 Node ND OUT Output node I L Inductor current I LDLoad current 31 Error amplifier 32 Ramp circuit 33 Current information acquisition circuit 34 Adder 35 PWM comparator 36 Oscillator circuit 37 Controller 38 Light load detection circuit 38a Comparator 39 Zero cross detection circuit 40 Clamp circuit R1, R2 Resistor V FB Feedback voltage V REF Reference voltage V ERR Error voltage V RAMP Lamp voltage V IL Sense voltage V SLP Slope voltage V LLM Light load threshold voltage WR ERR Wiring S LLM Signal (light load detection signal) S ZX Signal (zero cross detection signal) CLK Clock signal CMPOUT Signal

Claims

1. A first switching element is provided between a reference node and a first node having a potential lower than the input voltage, A second switching element is provided between the first node and the second node, A third switching element is provided between the second node and the third node, A power supply device comprising a fourth switching element provided between the third node and a power supply node that receives the input voltage, wherein the power supply device is configured to generate an output voltage by controlling the state of each switching element to divide the input voltage and step down the intermediate voltage obtained by the division, The system includes a control circuit configured to switch the state of the first to fourth switching elements between a first state, a second state, and a third state based on the output voltage information and the current information of an inductor provided between the first node and the output node to which the output voltage is applied. In the first state, the second switching element and the fourth switching element are on, and the first switching element and the third switching element are off. In the second state, the second switching element and the fourth switching element are off, and the first switching element and the third switching element are on. In the third state, all of the first to fourth switching elements are off. , power supply.

2. An intermediate capacitor is provided between the second node and the reference node, A flying capacitor provided between the first node and the third node, The control circuit performs switching control to switch the state of the first to fourth switching elements between a first state and a second state based on the output voltage information and the inductor current information, thereby generating the intermediate voltage across the intermediate capacitor and generating the output voltage at the output node through step-down of the intermediate voltage. The power supply device according to claim 1.

3. After the start of the switching control, if the feedback voltage corresponding to the output voltage exceeds a predetermined light load threshold voltage, the control circuit stops the switching control and sets the state of the first to fourth switching elements to the second state. The power supply device according to claim 2.

4. After the start of the switching control, if the feedback voltage exceeds the light load threshold voltage, the control circuit stops the switching control and sets the state of the first to fourth switching elements to the second state, and then sets the state of the first to fourth switching elements to the third state or restarts the switching control based on the feedback voltage and the current of the inductor. The power supply device according to claim 3.

5. The control circuit, after the start of the switching control, stops the switching control and sets the state of the first to fourth switching elements to the second state if the feedback voltage exceeds the light load threshold voltage, and then sets the state of the first to fourth switching elements to the third state if the current of the inductor satisfies a predetermined reverse flow condition without the feedback voltage falling below the release voltage which is less than the light load threshold voltage, and restarts the switching control if the feedback voltage falls below the release voltage before the current of the inductor satisfies the reverse flow condition. The power supply device according to claim 4.

6. The control circuit sets the state of the first to fourth switching elements to the third state, and then restarts the switching control when the feedback voltage falls below the release voltage. The power supply device according to claim 5.

7. The control circuit sets the state of the first to fourth switching elements to the third state, and then restarts the switching control when the intermediate voltage falls below a predetermined lower limit voltage. The power supply device according to claim 5.

8. The control circuit determines whether the reverse current condition is met based on the voltage between the first node and the reference node during the period when the state of the first to fourth switching elements is in the second state, within the stop period of the switching control. or the power supply device according to any one of claims 5 to 7.

9. The control circuit, during the period when the state of the first to fourth switching elements is in the second state within the stop period of the switching control, determines whether the reverse current condition is met based on a determination voltage corresponding to the potential of the first node as seen from the potential of the reference node. When the polarity of the determination voltage reverses from negative to positive, When the polarity of the determination voltage reverses from negative to positive, and the magnitude of the determination voltage reaches a predetermined value or higher, The reverse current condition is met when the polarity of the determination voltage is negative and the magnitude of the determination voltage decreases to or below a predetermined value. The power supply device according to claim 8.

10. In the switching control, the control circuit turns on the second and fourth switching elements and turns off the first and third switching elements when a predetermined level change in a predetermined clock signal occurs, and then, after a time corresponding to the output voltage information and the inductor current information has elapsed, it turns off the second and fourth switching elements and turns on the first and third switching elements. or the power supply device according to any one of claims 2 to 7.

11. An output capacitor is provided between the output node and the reference node. or the power supply device according to any one of claims 1 to 7.