DC-DC converter

Abstract

A DC-DC converter (1) for controlling DC output power by controlling the on and off of a high-side switch (11) is provided with a control unit (2) for adjusting the off-time of the high-side switch (11) in order to control output power. The control unit (2) makes the on-time of the high-side switch (11) inversely proportional to an input output voltage difference (Ei-Eo) which is the difference between an input voltage (E1) to the DC-DC converter (1) and an output voltage (Eo) from the DC-DC converter (1).

Description

DC-DC converter

[0001] The present disclosure relates to DC-DC converters.

[0002] A step-down converter consists of a high-side switch that switches the input voltage at high frequency, a low-side switch that alternates between on and off with the high-side switch, an inductor and output capacitor that average the potential at the junction between the high-side and low-side switches to supply the output voltage to the load, and a controller that controls the switching of the high-side and low-side switches. Note that a diode specialized for rectification is often used instead of the low-side switch. The ratio of the on time of the high-side switch to the switching cycle is called the duty ratio δ, and the following relationship (Equation 1) generally holds between the input voltage Ei and the output voltage Eo.

[0003] Eo=δ・Ei (Formula 1)

[0004] Generally, a step-down converter controls an output voltage Eo by adjusting a duty ratio δ.

[0005] When the duty cycle δ becomes significantly small when the input voltage is high, adjusting the duty cycle δ (on time) becomes difficult. Therefore, Patent Document 1 proposes a control method that fixes the on time of the high-side switch and adjusts the off time. The DC-DC converter in Patent Document 1 generates a modulation signal based on a reference voltage, a feedback voltage from the output voltage, and an extracted inductor ripple current, sets the off time according to the modulation signal, and sets the on time according to a constant on-time control signal. Specifically, the DC-DC converter in Patent Document 1 performs switching control by comparing a signal obtained by adding the modulation signal to the feedback voltage with a reference voltage, or by comparing a signal obtained by subtracting the modulation signal from the reference voltage with the feedback voltage. This control method is called hysteresis control because switching control is performed using the amplitude of the modulation signal as equivalent hysteresis. Patent Document 2 describes an example of hysteresis control that does not fix the on time, but subtracts a modulation signal corresponding to the ripple current from a reference voltage. Generally, with hysteresis control, the greater the hysteresis, the more stable the feedback control system becomes, but regulation tends to deteriorate.

[0006] US Patent No. 10,587,196 JP 2007-89278 A

[0007] However, the DC-DC converter of Patent Document 1 requires a current ripple extractor to extract the ripple current of the inductor, which increases the size of the control unit.The technology of Patent Document 2 does not fix the on-time, so it is difficult to control when the input voltage is high.

[0008] Patent Document 1 also proposes a control method in which the on-time is inversely proportional to the input voltage. This method has the advantage of being able to maintain a constant operating frequency (switching frequency) compared to a method in which the on-time is fixed regardless of input / output conditions, but the amplitude of the ripple current varies depending on the input voltage. In particular, when the input voltage is low, the amplitude of the ripple current becomes smaller, which reduces hysteresis and causes problems such as a deterioration in the stability of the output voltage.

[0009] An object of the present disclosure is to provide a DC-DC converter that can suppress both fluctuations in switching frequency and fluctuations in the amplitude of ripple current.

[0010] A DC-DC converter according to one aspect of the present disclosure is a DC-DC converter that controls DC output power by controlling the on and off of a high-side switch, and includes a control unit that adjusts the off time of the high-side switch to control the output power, and the control unit makes the on time of the high-side switch inversely proportional to an input / output voltage difference, which is the difference between the input voltage to the DC-DC converter and the output voltage from the DC-DC converter.

[0011] These comprehensive or specific aspects may be realized as a system, a method, an integrated circuit, a computer program, or a computer-readable recording medium such as a CD-ROM, or may be realized as any combination of a system, a method, an integrated circuit, a computer program, and a recording medium.

[0012] According to the DC-DC converter of the present disclosure, it is possible to suppress both fluctuations in the switching frequency and fluctuations in the amplitude of the ripple current.

[0013] FIG. 1 is a circuit diagram showing the configuration of a DC-DC converter according to a first embodiment. FIG. 2 is a waveform diagram showing the operation of the DC-DC converter according to the first embodiment. FIG. 3 is a characteristic diagram showing the switching frequency versus the input voltage of a DC-DC converter according to the present disclosure and a conventional DC-DC converter. FIG. 4 is a characteristic diagram showing the amplitude of a ripple current versus the input voltage of a DC-DC converter according to the present disclosure and a conventional DC-DC converter. FIG. 5 is a circuit diagram showing the configuration of a DC-DC converter according to a second embodiment. FIG. 6 is a waveform diagram showing the operation of a DC-DC converter according to the second embodiment. FIG. 7 is a circuit diagram showing the configuration of a DC-DC converter according to a third embodiment. FIG. 8 is a waveform diagram showing the operation of a DC-DC converter according to the third embodiment. FIG. 9 is a circuit diagram showing the configuration of a constant current source according to another embodiment.

[0014] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. Note that each embodiment described below represents a specific example of the present disclosure. The numerical values, shapes, materials, components, component arrangements and connection forms, steps, and step orders shown in the following embodiments are merely examples and do not limit the present disclosure. Furthermore, each figure is not necessarily an exact illustration. In each figure, substantially identical configurations are assigned the same reference numerals, and redundant explanations are omitted or simplified. Furthermore, "connection" means electrical connection, and includes not only cases where two circuit elements are directly connected, but also cases where two circuit elements are indirectly connected with another circuit element inserted between them.

[0015] Furthermore, "proportional" described below may be "approximately proportional," and "inversely proportional" may be "approximately inversely proportional." For example, if the coefficient when y is proportional to x is a, then "approximately proportional" and "approximately inversely proportional" mean that a does not necessarily have to be a fixed value depending on the value of x, and that a may vary somewhat depending on the value of x. For example, the range of variation of a is within ±10% of a representative value (such as the mean, median, or mode) that a can take.

[0016] First Embodiment FIG. 1 is a circuit diagram showing the configuration of a DC-DC converter 1 according to a first embodiment.

[0017] The DC-DC converter 1 controls DC output power by controlling the on and off of a high-side switch 11. In FIG. 1 , the DC-DC converter 1 is a step-down converter that steps down an input voltage Ei from a DC power supply 10, such as a battery, to the DC-DC converter 1 and supplies an output voltage Eo from the DC-DC converter 1 to a load (not shown). The DC-DC converter 1 includes a high-side switch 11, a low-side switch 12, an inductor 13, an output capacitor 14, and a control unit 2. In the DC-DC converter 1, a series configuration of the high-side switch 11 and the low-side switch 12 is connected in parallel to the DC power supply 10, one end of the inductor 13 with an inductance L is connected to a connection point LX between the high-side switch 11 and the low-side switch 12, and the other end of the inductor 13 is connected to an output capacitor 14. The voltage across the output capacitor 14 is output as an output voltage Eo. The high-side switch 11 and the low-side switch 12 are, for example, NMOS (N type Metal Oxide Semiconductor) transistors. The DC-DC converter 1 may include a diode instead of the low-side switch 12.

[0018] The control unit 2 adjusts the off time of the high-side switch 11 to control the output power. For example, the control unit 2 includes a reference voltage source 20 that generates a reference voltage Vref, a current source circuit 21 that receives an input voltage Ei and an output voltage Eo and generates a current proportional to an input-output voltage difference (Ei - Eo) between the input voltage Ei and the output voltage Eo, an on-time setting circuit 22 that receives the current proportional to the input-output voltage difference (Ei - Eo) and outputs a turn-off signal Vdf, an off-time setting circuit 23 that generates a ramp voltage Vr by superimposing a modulation signal on the reference voltage Vref, compares the ramp voltage Vr with a feedback voltage Vfb (described later), and outputs a turn-on signal Vdr, resistors 24 and 25 that form a feedback circuit that divides the output voltage Eo and generates a feedback voltage Vfb corresponding to the output voltage Eo, and a drive circuit 26 that receives the turn-off signal Vdf and the turn-on signal Vdr and outputs a drive signal Vg1 for the high-side switch 11 and a drive signal Vg2 for the low-side switch 12. Although details will be described later, the control unit 2 having such a configuration can make the on-time of the high-side switch 11 inversely proportional to the input / output voltage difference (Ei-Eo).

[0019] Here, if the resistance values ​​of the resistors 24 and 25 are R4 and R5, respectively, and the voltage division ratio is k=R5 / (R4+R5), the feedback voltage Vfb can be expressed as in the following (Equation 2).

[0020] Vfb=Eo・R5 / (R4+R5)=k・Eo (Formula 2)

[0021] To prevent the high-side switch 11 and the low-side switch 12 from being turned on simultaneously, the drive circuit 26 causes the drive signal Vg2 to fall at the rising timing of the turn-on signal Vdr to turn off the low-side switch 12, and then causes the drive signal Vg1 to rise to turn on the high-side switch 11. Then, the drive circuit 26 causes the drive signal Vg1 to fall at the rising timing of the turn-off signal Vdf to turn off the high-side switch 11, and then causes the drive signal Vg2 to rise to turn on the low-side switch 12.

[0022] The current source circuit 21 includes a PMOS (P type Metal Oxide Semiconductor) transistor 210, the source of which is applied with the output voltage Eo, a resistor 211 for causing a current to flow through the PMOS transistor 210, a resistor 212 to which an input voltage Ei is applied, resistors 213 and 214, the other ends of which are connected to the other end of the resistor 212, a PMOS transistor 215, the source of which is connected to the other end of the resistor 213, and a PMOS transistor 216, the source of which is connected to the other end of the resistor 214, and the gate and drain of the PMOS transistor 210, the gate of the PMOS transistor 215, and the gate of the PMOS transistor 216 are connected to one another. With this configuration, the source voltages of the PMOS transistors 215 and 216 are both equal to the output voltage Eo. Let the resistance values ​​of resistors 212, 213, and 214 be R, Ra, and Rb, respectively, and let Ia be the current flowing out from the drain of PMOS transistor 215 via resistor 213, and Ib be the current flowing out from the drain of PMOS transistor 216 via resistor 214. The currents Ia and Ib can be expressed as in the following (Equation 3a) and (Equation 3b).

[0023] Ia=(Ei-Eo) / {Ra+R(1+Ra / Rb)} (Formula 3a) Ib=(Ei-Eo) / {Rb+R(1+Rb / Ra)} (Formula 3b)

[0024] For simplicity, if R=Ra=Rb=r / 3, the currents Ia and Ib can be expressed as in the following (Equation 3).

[0025] Ia=Ib=(Ei-Eo) / r (Formula 3)

[0026] The drain of PMOS transistor 215 is connected to off-time setting circuit 23, and the drain of PMOS transistor 216 is connected to on-time setting circuit 22, and a current Ia proportional to the input / output voltage difference (Ei-Eo) is supplied to each of on-time setting circuit 22 and off-time setting circuit 23.

[0027] The on-time setting circuit 22 includes an on-time setting capacitor 220 connected to the drain of the PMOS transistor 216 and through which current from the current source circuit 21 flows, a switch 221 that shorts both ends of the on-time setting capacitor 220 in response to a drive signal Vg2, and a comparator 222 that compares the voltage Vt of the on-time setting capacitor 220 with a reference voltage Vref1, and outputs a turn-off signal Vdf from the comparator 222. Specifically, the switch 221 is on while the drive signal Vg2 is rising, shorting both ends of the on-time setting capacitor 220 (in other words, discharging the on-time setting capacitor 220). The reference voltage Vref1 may be the same as the reference voltage Vref of the reference voltage source 20, but to avoid confusion in the equations, the reference voltage Vref1 and the reference voltage Vref will be described separately. As will be described in more detail later, the on-time setting circuit 22 is configured in this manner so that it turns off the high-side switch 11 when the amount of change in voltage of the on-time setting capacitor 220 from the time the high-side switch 11 is turned on reaches a predetermined value (e.g., reference voltage Vref1).

[0028] the off-time setting circuit 23 includes an off-time setting capacitor 230 having one end connected to the reference voltage source 20 and outputting a ramp voltage Vr from the other end; a current mirror consisting of an NMOS transistor 231 and an NMOS transistor 232 for drawing in a current the same as the current Ia from the drain of the PMOS transistor 215; a switch 233 for connecting the drain of the NMOS transistor 232 to the other end of the off-time setting capacitor 230 in response to a drive signal Vg1; a constant current source 234 for charging the off-time setting capacitor 230 with a constant current Ir; a switch 235 for connecting the constant current source 234 to the other end of the off-time setting capacitor 230 in response to a drive signal Vg2; a switch 236 for shorting both ends of the off-time setting capacitor 230 in response to a turn-on signal Vdr; a comparator 237 for comparing the ramp voltage Vr with a feedback voltage Vfb; and a trigger circuit 238 for outputting a turn-on signal Vdr as a one-shot pulse in response to the rising edge of the output of the comparator 237.

[0029] Specifically, the switch 233 is on while the drive signal Vg1 is rising, connecting the drain of the NMOS transistor 232 to the other end of the off-time setting capacitor 230 (in other words, discharging the off-time setting capacitor 230). Specifically, the switch 235 is on while the drive signal Vg2 is rising, connecting the constant current source 234 to the other end of the off-time setting capacitor 230 (in other words, charging the off-time setting capacitor 230). Specifically, the switch 236 is on while the turn-on signal Vdr is rising, shorting both ends of the off-time setting capacitor 230 (in other words, making the lamp voltage Vr equal to the reference voltage Vref). Here, for simplicity, it is assumed that the current drawn by the NMOS transistor 232 is set to be equal to the current Ia from the drain of the PMOS transistor 215.

[0030] Although details will be described later, the off-time setting circuit 23 is configured in this manner so that when the high-side switch 11 is turned on, the off-time setting circuit 23 charges the voltage of the off-time setting capacitor 230 to a predetermined voltage (for example, reference voltage Vref), discharges the off-time setting capacitor 230 with current Ia from current source circuit 21 that is proportional to the input / output voltage difference (Ei-Eo) during the on-period of the high-side switch 11, charges the off-time setting capacitor 230 with a predetermined constant current or current Ir that is proportional to the output voltage Eo during the off-period of the high-side switch 11, and turns on the high-side switch 11 when the voltage of the off-time setting capacitor 230 reaches feedback voltage Vfb.

[0031] Next, the operation of the DC-DC converter 1 (specifically, the operation of the control unit 2) will be described in detail with reference to FIG.

[0032] Fig. 2 is a waveform diagram showing the operation of the DC-DC converter 1 according to embodiment 1. Fig. 2 is an operational waveform diagram for each of the main parts of the DC-DC converter 1 according to embodiment 1 shown in Fig. 1, and shows, from the top, the turn-on signal Vdr, the turn-off signal Vdf, the drive signal Vg1, the drive signal Vg2, the LX terminal voltage Vx, the inductor current Ix, the voltage Vt of the on-time setting capacitor 220, and the lamp voltage Vr.

[0033] At time t0, the turn-on signal Vdr rises, the drive signal Vg2 falls, turning off the low-side switch 12, and the drive signal Vg1 rises, turning on the high-side switch 11. This causes the LX terminal voltage Vx to change from zero to the input voltage Ei. The input-output voltage difference (Ei - Eo) is applied to the inductor 13, and the inductor current Ix increases at a slope of (Ei - Eo) / L. Furthermore, the rise of the turn-on signal Vdr turns on the switch 236, and the voltage (ramp voltage Vr) of the off-time setting capacitor 230 is charged to the reference voltage Vref. In the on-time setting circuit 22 of the control unit 2, the fall of the drive signal Vg2 turns off the switch 221, and the on-time setting capacitor 220 is charged at a current Ia = (Ei - Eo) / r, causing the voltage Vt to rise. Meanwhile, in the off-time setting circuit 23, the switch 233 is turned on when the drive signal Vg1 rises, and the switch 235 is turned off when the drive signal Vg2 falls, causing the off-time setting capacitor 230 to discharge with the current Ia, and the lamp voltage Vr drops from the reference voltage Vref.

[0034] At time t1, when the voltage Vt of the on-time setting capacitor 220 reaches the reference voltage Vref1, the turn-off signal Vdf output by the comparator 222 rises, and the drive signal Vg1 falls, turning off the high-side switch 11. Next, the drive signal Vg2 rises, turning on the low-side switch 12.

[0035] Here, the time from time t0 to time t1 is the on-time Ton of the high-side switch 11. If the capacitance of the on-time setting capacitor 220 is Ct, the on-time Ton is given by the following (Equation 4).

[0036] Ton=Ct・Vref1・r / (Ei−Eo) (Formula 4)

[0037] As shown in Equation 4, the on-time Ton is inversely proportional to the input / output voltage difference (Ei-Eo). The increment ΔIx (amplitude of the ripple current) of the inductor current Ix during this on-time Ton is given by Equation 5 below.

[0038] ΔIx=(Ei-Eo)・Ton / L=Ct・Vref1・r / L (Formula 5)

[0039] Furthermore, the drop ΔVr of the lamp voltage Vr is expressed by the following (Equation 6), where Cr is the capacitance of the off-time setting capacitor 230.

[0040] ΔVr=Ia・Ton / Cr=Ct・Vref1 / Cr (Formula 6)

[0041] Equation 5 and Equation 6 show that the increase ΔIx of the inductor current Ix and the decrease ΔVr of the lamp voltage Vr are constant values ​​that do not depend on the input / output voltage.

[0042] After time t1, the high-side switch 11 is turned off and the low-side switch 12 is turned on, causing the LX terminal voltage Vx to reach zero potential, output voltage Eo to be applied to inductor 13, and inductor current Ix to decrease at a slope of Eo / L. In on-time setting circuit 22 of control unit 2, drive signal Vg2 rises, turning on switch 221, causing voltage Vt of on-time setting capacitor 220 to reach zero, and causing turn-off signal Vdf output by comparator 222 to fall. Meanwhile, in off-time setting circuit 23, drive signal Vg1 falls, turning off switch 233, and drive signal Vg2 rises, turning on switch 235. As a result, off-time setting capacitor 230 is charged by a constant current from constant current source 234, and lamp voltage Vr begins to rise.

[0043] At time t2, when the ramp voltage Vr reaches the feedback voltage Vfb, the output of the comparator 237 rises, and a turn-on signal Vdr is output via the trigger circuit 238. At the same time, the rise of the turn-on signal Vdr turns on the switch 236, and the ramp voltage Vr reaches the reference voltage Vref. However, because the turn-on signal Vdr is a one-shot pulse, the switch 236 immediately turns off. The off-time setting capacitor 230 is discharged with the current Ia, and the ramp voltage Vr begins to decrease. When the turn-on signal Vdr causes the drive signal Vg2 to fall, the low-side switch 12 turns off. Next, the drive signal Vg1 rises, turning on the high-side switch 11. The LX terminal voltage Vx changes from zero potential to the input voltage Ei, and the same operation as that from time t0 onwards is repeated.

[0044] Here, the time from time t1 to time t2 is the off time Toff of the high-side switch 11. The decrease in the inductor current Ix during this off time Toff is given by the following (Equation 7).

[0045] ΔIx=Eo・Toff / L (Formula 7)

[0046] In a steady state, this decrease is equal to the increase, and therefore the following relationship (Equation 8) is obtained.

[0047] (Ei-Eo)・Ton=Eo・Toff (Formula 8)

[0048] From (Equation 8), we can obtain (Equation 1), which is an input / output relational expression of the step-down converter: Eo=Ei·Ton / (Ton+Toff)=δ·Ei. Furthermore, from (Equation 4) and (Equation 8), we can obtain the following relationship: (Equation 9).

[0049] Eo・Toff=Ct・Vref1・r (Formula 9)

[0050] On the other hand, when the current value from the constant current source 234 of the off time setting circuit 23 is Ir, the following relationship (Equation 10) is obtained.

[0051] Vfb-Vref+ΔVr=Ir・Toff / Cr (Formula 10)

[0052] Substituting (Equation 6) and (Equation 9) into (Equation 10) and eliminating Toff, the following relationship in (Equation 11) is obtained.

[0053] Vfb-Vref=(Ct / Cr)・Vref1・(r・Ir / Eo-1) (Formula 11)

[0054] From Vfb = k Eo (Equation 2), it can be seen that the output voltage Eo is expressed by a complex design constant and can be stabilized at a desired value. Here, by setting the constant current Ir to Eo / r, that is, by making the off time Toff inversely proportional to the output voltage Eo, Equation 11 can be simplified to the following Equation 12.

[0055] Vfb=Vref (Formula 12)

[0056] Next, the characteristics of the DC-DC converter 1 of the present disclosure, in which the on-time Ton is inversely proportional to the input / output voltage difference (Ei-Eo), will be described in comparison with a conventional DC-DC converter using FIGS. 3A and 3B.

[0057] FIG. 3A is a characteristic diagram showing switching frequency f versus input voltage Ei of the DC-DC converter of the present disclosure and the conventional DC-DC converter.

[0058] 3B is a characteristic diagram showing the amplitude (variation range) ΔIx of the ripple current with respect to the input voltage Ei of the DC-DC converter of the present disclosure and the conventional DC-DC converter. Specifically, FIGS. 3A and 3B show the characteristics of the conventional DC-DC converter when the on-time is fixed (Ton = 0.2 μsec) and when the on-time is inversely proportional to the input voltage Ei (Ton = 4.8 / Ei), while FIGS. 3B show the characteristics of the DC-DC converter 1 of the present disclosure when the on-time is inversely proportional to the input / output voltage difference (Ei - Eo) (Ton = 3.8 / (Ei - Eo)). The input voltage Ei is set to 10 to 50 V, the output voltage Eo is set to 5 V, the inductance of the inductor 13 is set to 100 μH, and the on-time Ton is set to 0.2 μsec when the input voltage Ei is 24 V.

[0059] When the on-time is fixed, both the switching frequency f and the amplitude ΔIx of the ripple current fluctuate significantly. However, when the on-time Ton is inversely proportional to the input voltage Ei, there is no fluctuation in the switching frequency f, and the lower the input voltage Ei, the smaller the amplitude ΔIx of the ripple current. In contrast, when the on-time Ton of the present disclosure is inversely proportional to the input / output voltage difference (Ei - Eo), there is almost no fluctuation in the amplitude ΔIx of the ripple current. On the other hand, the lower the input voltage Ei, the lower the switching frequency f, but the fluctuation in the switching frequency f is suppressed compared to when the on-time is fixed.

[0060] As described above, the DC-DC converter 1 of the present disclosure can suppress both fluctuations in the switching frequency f and fluctuations in the ripple current amplitude ΔIx by making the on-time of the high-side switch 11 inversely proportional to the input-output voltage difference (Ei - Eo). Specifically, fluctuations in the ripple current amplitude ΔIx are almost eliminated while suppressing the switching frequency f, enabling stable operation over a wide input voltage Ei.

[0061] Furthermore, because the current Ia flowing through the on-time setting capacitor 220 is proportional to the input-output voltage difference (Ei - Eo), the time from when the high-side switch 11 is turned on until the amount of change in the voltage of the on-time setting capacitor 220 reaches a predetermined value (e.g., reference voltage Vref1), which corresponds to the on-time of the high-side switch 11, is inversely proportional to the input-output voltage difference (Ei - Eo). Therefore, by providing the control unit 2 with the current source circuit 21 and the on-time setting circuit 22, the on-time of the high-side switch 11 can be made inversely proportional to the input-output voltage difference (Ei - Eo).

[0062] Furthermore, taking into consideration the feedback voltage Vfb corresponding to the output voltage Eo, the time from when the high-side switch 11 is turned off until the voltage of the off-time setting capacitor 230 reaches the feedback voltage Vfb is set, which corresponds to the off-time of the high-side switch 11. Therefore, by providing the control unit 2 with the feedback circuit (resistors 24 and 25) and the off-time setting circuit 23, the off-time of the high-side switch 11 can be set so as to suppress fluctuations in the output voltage Eo, and the output voltage Eo can be stabilized.

[0063] (Embodiment 2) Fig. 4 is a circuit diagram showing the configuration of a DC-DC converter 1A according to embodiment 2. In Fig. 4, the same components as those in the DC-DC converter 1 shown in Fig. 1 are given the same reference numerals, and their description will be omitted or simplified.

[0064] 4 differs from Fig. 1 in the configuration of control unit 2A, which is simplified by reducing the number of components compared to control unit 2 in Fig. 1. Current source circuit 21 in Fig. 4 is replaced by current source circuit 21A, in which resistor 213 and PMOS transistor 215 of current source circuit 21 are deleted and resistors 212 and 214 are replaced with resistor 212A. If the resistance value of resistor 212A is r, current Ia output from the drain of PMOS transistor 216 is given by the following (Equation 13), as in the first embodiment.

[0065] Ia=(Ei-Eo) / r (Formula 13)

[0066] 4 is an off time setting circuit 23A in comparison with off time setting circuit 23 in Fig. 1, in which NMOS transistors 231 and 232 constituting a current mirror, switches 233 and 235, and trigger circuit 238 in off time setting circuit 23 are eliminated, and switch 236 is replaced with switch 236A that shorts out off time setting capacitor 230 in response to drive signal Vg1. Specifically, switch 236A is on while drive signal Vg1 is rising, and shorts out both ends of off time setting capacitor 230 (in other words, switch 236A discharges off time setting capacitor 230 so that lamp voltage Vr becomes reference voltage Vref of reference voltage source 20).

[0067] Although details will be described later, the off-time setting circuit 23A is configured in this manner so that, while the high-side switch 11 is on, the voltage of the off-time setting capacitor 230 is discharged to a predetermined voltage (for example, reference voltage Vref), while the high-side switch 11 is off, the off-time setting capacitor 230 is charged with a predetermined constant current or with a current Ir proportional to the output voltage Eo, and when the voltage of the off-time setting capacitor 230 reaches the feedback voltage Vfb, the high-side switch 11 is turned on.

[0068] Next, the operation of the DC-DC converter 1A (specifically, the operation of the control unit 2A) will be described in detail with reference to FIG.

[0069] Fig. 5 is a waveform diagram showing the operation of the DC-DC converter 1A according to embodiment 2. Fig. 5 is an operational waveform diagram for each of the main parts of the DC-DC converter 1A according to embodiment 2 shown in Fig. 4, and shows, from top to bottom, the turn-on signal Vdr, the turn-off signal Vdf, the drive signal Vg1, the drive signal Vg2, the LX terminal voltage Vx, the inductor current Ix, the voltage Vt of the on-time setting capacitor 220, and the lamp voltage Vr.

[0070] At time t0, the turn-on signal Vdr rises, the drive signal Vg2 falls, turning off the low-side switch 12, and the drive signal Vg1 rises, turning on the high-side switch 11. This causes the LX terminal voltage Vx to change from zero to the input voltage Ei. The input-output voltage difference (Ei - Eo) is applied to the inductor 13, and the inductor current Ix increases at a slope of (Ei - Eo) / L. In the on-time setting circuit 22, the switch 221 is turned off, charging the on-time setting capacitor 220 with a current Ia = (Ei - Eo) / r, increasing the voltage Vt. Meanwhile, in the off-time setting circuit 23A, the drive signal Vg1 rises, turning on the switch 236A, shorting both ends of the off-time setting capacitor 230, and discharging the voltage of the off-time setting capacitor 230 (lamp voltage Vr) to the reference voltage Vref.

[0071] At time t1, when the voltage Vt of the on-time setting capacitor 220 reaches the reference voltage Vref1, the turn-off signal Vdf output by the comparator 222 rises, and the drive signal Vg1 falls, turning off the high-side switch 11. Next, the drive signal Vg2 rises, turning on the low-side switch 12.

[0072] Here, similarly to the first embodiment, the on-time Ton of the high-side switch 11 from time t0 to time t1 is given by the following (Equation 14).

[0073] Ton=Ct・Vref1・r / (Ei−Eo) (Formula 14)

[0074] The increment ΔIx (amplitude of the ripple current) of the inductor current Ix during this on-time Ton is given by the following (Equation 15).

[0075] ΔIx=(Ei-Eo)・Ton / L=Ct・Vref1・r / L (Formula 15)

[0076] As in the first embodiment, the increment ΔIx of the inductor current Ix is a constant value that does not depend on the input / output voltage.

[0077] After time t1, the high-side switch 11 is turned off and the low-side switch 12 is turned on, causing the LX terminal voltage Vx to reach zero potential, output voltage Eo to be applied to inductor 13, and inductor current Ix to decrease at a slope of Eo / L. In on-time setting circuit 22 of control unit 2, drive signal Vg2 rises, turning on switch 221, causing voltage Vt of on-time setting capacitor 220 to reach zero, and causing turn-off signal Vdf output by comparator 222 to fall. Meanwhile, in off-time setting circuit 23A, drive signal Vg1 falls, turning off switch 236A, causing off-time setting capacitor 230 to be charged by a constant current from constant current source 234, and lamp voltage Vr increases.

[0078] At time t2, when the lamp voltage Vr reaches the feedback voltage Vfb, the turn-on signal Vdr, which is the output of the comparator 237, rises. When the turn-on signal Vdr causes the drive signal Vg2 to fall, the low-side switch 12 turns off, then the drive signal Vg1 rises, turning the high-side switch 11 on, and the LX terminal voltage Vx changes from zero potential to the input voltage Ei. When the drive signal Vg1 rises, the switch 236A turns on, shorting both ends of the off-time setting capacitor 230, causing the lamp voltage Vr to become the reference voltage Vref, the comparator 237 is inverted, and the turn-on signal Vdr falls. The same operations as those from time t0 onwards are repeated.

[0079] Here, the time from time t1 to time t2 is the off time Toff of the high-side switch 11. The decrease in the inductor current Ix during this off time Toff is given by the following (Equation 16).

[0080] ΔIx=Eo・Toff / L (Formula 16)

[0081] In a steady state, this decrease is equal to the increase, and therefore the following relationship (Equation 17) is obtained.

[0082] (Ei-Eo)・Ton=Eo・Toff (Formula 17)

[0083] From (Equation 17), we can obtain (Equation 1), which is an input / output relational expression of the step-down converter: Eo=Ei·Ton / (Ton+Toff)=δ·Ei. Furthermore, from (Equation 14) and (Equation 17), we can also obtain the following relationship (Equation 18).

[0084] Eo・Toff=Ct・Vref1・r (Formula 18)

[0085] On the other hand, when the current value from the constant current source 234 of the off time setting circuit 23A is Ir, the following relationship (Equation 19) is obtained.

[0086] Vfb-Vref=Ir・Toff / Cr (Formula 19)

[0087] Substituting (Equation 18) into (Equation 19) and eliminating Toff, the following relationship in (Equation 20) is obtained.

[0088] Vfb-Vref=(Ct / Cr)・Vref1・r・Ir / Eo (Formula 20)

[0089] From Vfb = k Eo (Equation 2), it can be seen that the output voltage Eo is expressed by a complex design constant and can be stabilized at a desired value. Here, by setting the constant current Ir to Eo / r, that is, by making the off time Toff inversely proportional to the output voltage Eo, Equation 20 can be simplified to the following Equation 21.

[0090] Vfb=Vref+(Ct / Cr)・Vref1 (Formula 21)

[0091] In the second embodiment, the on-time is inversely proportional to the input / output voltage difference (Ei-Eo), so there is almost no fluctuation in the amplitude of the ripple current, and fluctuations in the switching frequency are suppressed compared to when the on-time is fixed, which is similar to the first embodiment. The difference from the first embodiment is that the configuration of the control unit 2A is simpler than the configuration of the control unit 2.

[0092] Also in the second embodiment, the feedback voltage Vfb corresponding to the output voltage Eo is taken into consideration when setting the time from when the high-side switch 11 is turned off until the voltage of the off-time setting capacitor 230 reaches the feedback voltage Vfb, which corresponds to the off-time of the high-side switch 11. Therefore, by providing the control unit 2A with the feedback circuit (resistors 24 and 25) and the off-time setting circuit 23A, the off-time of the high-side switch 11 can be set so as to suppress fluctuations in the output voltage Eo, and the output voltage Eo can be stabilized.

[0093] (Embodiment 3) Fig. 6 is a circuit diagram showing the configuration of a DC-DC converter 1B according to embodiment 3. In Fig. 6, the same components as those in the DC-DC converter 1 shown in Fig. 1 are given the same reference numerals, and their description will be omitted or simplified.

[0094] The difference between Fig. 6 and Fig. 1 is the configuration of control unit 2B. Current source circuit 21 in Fig. 1 is replaced with current source circuit 21B in Fig. 6, in which resistor 214 and PMOS transistor 216 of current source circuit 21 are deleted and resistors 212 and 213 are replaced with resistor 212B. If the resistance value of resistor 212B is r, current Ia output from the drain of PMOS transistor 215 is given by the following (Equation 22), as in the first embodiment.

[0095] Ia=(Ei-Eo) / r (Formula 22)

[0096] In FIG. 6, the off-time setting capacitor 230 in FIG. 1 is replaced with a capacitor 27, which functions to set both the off time and the on time. That is, in FIG. 6, the on-time setting capacitor 220 and the off-time setting capacitor 230 are replaced with the capacitor 27. The lamp voltage Vr is the voltage obtained by adding the voltage of the capacitor 27 to the reference voltage Vref. In FIG. 6, the on-time setting circuit 22 in FIG. 1 is replaced with an on-time setting circuit 22B. The negative input terminal of a comparator 222B that outputs a turn-off signal Vdf receives the lamp voltage Vr, and the positive input terminal receives the reference voltage Vref. Furthermore, a reference voltage source 223 that generates a reference voltage Vref1 is added to the reference voltage Vref, and a switch 224 is connected to set the lamp voltage Vr to the reference voltage Vref+Vref1 in response to the turn-on signal Vdr. A current mirror formed by NMOS transistors 225 and 226 draws a current equal to the current Ia from current source circuit 21B into NMOS transistor 226, and capacitor 27 is discharged via switch 227, which operates in response to drive signal Vg1. Meanwhile, off-time setting circuit 23 in FIG. 1 is replaced by off-time setting circuit 23B in FIG. 6, and switch 236 is eliminated from off-time setting circuit 23B. Furthermore, the circuit corresponding to NMOS transistors 231, 232, and switch 233, which discharge lamp voltage Vr during the on-period in FIG. 1, is replaced by NMOS transistors 225, 226, and switch 227 in FIG. 6, as described above, which are components of on-time setting circuit 22B.

[0097] Specifically, the switch 224 is on while the turn-on signal Vdr is rising, and connects the positive terminal of the reference voltage source 223 to the positive input terminal of the comparator 237 (in other words, when the high-side switch 11 is turned on, the voltage of the capacitor 27 is charged to the reference voltage Vref+Vref1). Specifically, the switch 227 is on while the drive signal Vg1 is rising, and connects the drain of the NMOS transistor 226 and the capacitor 27 (in other words, while the high-side switch 11 is on, the capacitor 27 is discharged with a current Ia from the current source circuit 21B that is proportional to the input-output voltage difference (Ei-Eo)).

[0098] Although details will be described later, the on-time setting circuit 22B charges the voltage of the capacitor 27 to a first voltage (reference voltage Vref+Vref1) when the high-side switch 11 is turned on, discharges the capacitor 27 with a current from the current source circuit 21B that is proportional to the input-output voltage difference (Ei-Eo) while the high-side switch 11 is on, and turns off the high-side switch 11 when the voltage of the high-side switch 11 reaches a second voltage (reference voltage Vref) that is lower than the first voltage.

[0099] Although details will be described later, the off-time setting circuit 23B charges the capacitor 27 with a predetermined constant current or a current Ir proportional to the output voltage Eo during the off period of the high-side switch 11, and turns on the high-side switch 11 when the voltage of the capacitor 27 reaches the feedback voltage Vfb.

[0100] Next, the operation of the DC-DC converter 1B (specifically, the operation of the control unit 2B) will be described in detail with reference to FIG.

[0101] Fig. 7 is a waveform diagram showing the operation of DC-DC converter 1B according to embodiment 3. Fig. 7 is an operational waveform diagram for each of the main parts of DC-DC converter 1B according to embodiment 3 shown in Fig. 6, and shows, from top to bottom, turn-on signal Vdr, turn-off signal Vdf, drive signal Vg1, drive signal Vg2, LX terminal voltage Vx, inductor current Ix, and lamp voltage Vr.

[0102] At time t0, the turn-on signal Vdr rises, the drive signal Vg2 falls, turning off the low-side switch 12, and the drive signal Vg1 rises, turning on the high-side switch 11. This causes the LX terminal voltage Vx to change from zero to the input voltage Ei. The input-output voltage difference (Ei - Eo) is applied to the inductor 13, and the inductor current Ix increases at a slope of (Ei - Eo) / L. In the on-time setting circuit 22B, the rising of the turn-on signal Vdr turns on the switch 224, charging the ramp voltage Vr to the reference voltage Vref + Vref1, and turning off the switch 224 as the one-shot pulse turn-on signal Vdr falls. Furthermore, when the drive signal Vg1 rises, the switch 227 turns on, and when the drive signal Vg2 falls, the switch 235 of the off time setting circuit 23B turns off, so that the capacitor 27 is discharged with the current Ia and the lamp voltage Vr drops from the reference voltage Vref+Vref1.

[0103] At time t1, when the ramp voltage Vr drops to the reference voltage Vref, the turn-off signal Vdf rises and the drive signal Vg1 falls, turning off the high-side switch 11. Next, the drive signal Vg2 rises and the low-side switch 12 turns on.

[0104] Here, the time from time t0 to time t1 is the on-time Ton of the high-side switch 11. If the capacitance of the capacitor 27 is Cr, the on-time Ton is given by the following (Equation 23).

[0105] Ton=Cr・Vref1・r / (Ei−Eo) (Formula 23)

[0106] As shown in Equation 23, the on-time Ton is inversely proportional to the input / output voltage difference (Ei-Eo). The increment ΔIx (amplitude of the ripple current) of the inductor current Ix during this on-time Ton is given by Equation 24 below.

[0107] ΔIx=(Ei-Eo)・Ton / L=Ct・Vref1・r / L (Formula 24)

[0108] The decrease in the lamp voltage Vr is Vref1, and both the increase ΔIx in the inductor current Ix and the decrease in the lamp voltage Vr are constant values ​​independent of the input and output voltages.

[0109] After time t1, the high-side switch 11 turns off and the low-side switch 12 turns on, causing the LX terminal voltage Vx to go to zero potential, output voltage Eo to be applied to inductor 13, and inductor current Ix to decrease at a slope of Eo / L. As drive signal Vg1 falls, switch 227 of on-time setting circuit 22B turns off, and as drive signal Vg2 rises, switch 235 of off-time setting circuit 23B turns on, so capacitor 27 is charged by a constant current from constant current source 234. After falling below reference voltage Vref, ramp voltage Vr begins to rise, and turn-off signal Vdf falls.

[0110] At time t2, when the ramp voltage Vr reaches the feedback voltage Vfb, the output of the comparator 237 rises, and a turn-on signal Vdr is output via the trigger circuit 238. At the same time, the rise of the turn-on signal Vdr turns on the switch 224, and the ramp voltage Vr becomes the reference voltage Vref+Vref1. Because the turn-on signal Vdr is a one-shot pulse, the switch 224 immediately turns off, the capacitor 27 discharges with the current Ia, and the ramp voltage Vr begins to decrease. When the turn-on signal Vdr causes the drive signal Vg2 to fall, the low-side switch 12 turns off. Next, the drive signal Vg1 rises, turning on the high-side switch 11. The LX terminal voltage Vx changes from zero potential to the input voltage Ei, and the same operation as that from time t0 onwards is repeated.

[0111] Here, the time from time t1 to time t2 is the off time Toff of the high-side switch 11. The decrease in the inductor current Ix during this off time Toff is given by the following (Equation 25).

[0112] ΔIx=Eo・Toff / L (Formula 25)

[0113] In the steady state, this decrease is equal to the increase, and therefore the following relationship (Equation 26) is obtained.

[0114] (Ei-Eo)・Ton=Eo・Toff (Formula 26)

[0115] From (Equation 26), we can obtain (Equation 1), which is an input / output relational expression of the step-down converter, Eo=Ei·Ton / (Ton+Toff)=δ·Ei. Furthermore, from (Equation 23) and (Equation 26), we can also obtain the following relationship (Equation 27).

[0116] Eo・Toff=Cr・Vref1・r (Formula 27)

[0117] On the other hand, when the current value from the constant current source 234 of the OFF time setting circuit 23B is Ir, the following relationship (Equation 28) is obtained.

[0118] Vfb-Vref=Ir・Toff / Cr (Formula 28)

[0119] When (Equation 27) is substituted into (Equation 28) and Toff is eliminated, the following relationship of (Equation 29) is obtained.

[0120] Vfb-Vref=Vref1・r・Ir / Eo (Formula 29)

[0121] From Vfb = k Eo (Equation 2), it can be seen that the output voltage Eo is expressed by a complex design constant and can be stabilized at a desired value. Here, by setting the constant current Ir to Eo / r, that is, by making the off time Toff inversely proportional to the output voltage Eo, Equation 29 can be simplified to the following Equation 30.

[0122] Vfb=Vref+Vref1 (Formula 30)

[0123] As described above, the current discharged from capacitor 27 is proportional to the input-output voltage difference (Ei - Eo), and therefore the time it takes for the voltage of high-side switch 11 to reach a second voltage (e.g., reference voltage Vref+Vref1) from a first voltage (e.g., reference voltage Vref), which corresponds to the on-time of high-side switch 11, is inversely proportional to the input-output voltage difference (Ei - Eo). Therefore, by providing control unit 2B with current source circuit 21B and on-time setting circuit 22B, the on-time of high-side switch 11 can be made inversely proportional to the input-output voltage difference (Ei - Eo).

[0124] Furthermore, taking into consideration the feedback voltage Vfb corresponding to the output voltage Eo, the time from when the high-side switch 11 is turned off until the voltage of capacitor 27 reaches the feedback voltage Vfb, which corresponds to the off-time of high-side switch 11, is set. Therefore, by including a feedback circuit (resistors 24 and 25) and an off-time setting circuit 23B in control unit 2B, the off-time of high-side switch 11 can be set so as to suppress fluctuations in output voltage Eo, thereby stabilizing output voltage Eo. Furthermore, since capacitor 27 is shared between on-time setting circuit 22B and off-time setting circuit 23B, the DC-DC converter 1B can be made smaller.

[0125] In the third embodiment, the on-time is also inversely proportional to the input / output voltage difference (Ei - Eo), so there is almost no fluctuation in the amplitude of the ripple current, and fluctuations in the switching frequency are suppressed compared to when the on-time is fixed, which is similar to the first embodiment. The differences from the first embodiment are that the configuration of the current source circuit 21B is simplified, that the on-time setting capacitor 220 and the off-time setting capacitor 230 are combined into a single capacitor 27, which simplifies the configuration of the control unit 2B, and that the generation of a surge current due to short-circuiting both ends of capacitor 27 is suppressed, thereby reducing noise.

[0126] (Other Embodiments) While the DC-DC converter according to the present disclosure has been described above based on Embodiments 1 to 3, the present disclosure is not limited to these embodiments. As long as they do not deviate from the spirit of the present disclosure, various modifications that would occur to those skilled in the art to the embodiments and other embodiments constructed by combining some of the components of the embodiments are also included within the scope of the present disclosure.

[0127] For example, in the above-described first to third embodiments, the circuit that generates the constant current Ir that increases the lamp voltage Vr is described as a constant current source 234 for the sake of simplicity, but as noted in the text, this current Ir is assumed to be a current Eo / r that is proportional to the output voltage Eo, and may be generated using the output voltage Eo. Figure 8 shows an example of a circuit that generates a constant current Ir (Eo / r) using the output voltage Eo.

[0128] FIG. 8 is a circuit diagram showing the configuration of a constant current source 234A according to another embodiment. For example, FIG. 8 is a circuit diagram of a constant current source 234A obtained by modifying the constant current source 234 of FIG. 6 so as to flow a current Eo / r. In FIG. 8, a resistor 241 and an NMOS transistor 242 are connected between a node to which an input voltage Ei is applied and a node to which an output voltage Eo is applied. The drain and gate of the NMOS transistor 242 are connected, and the potential thereof is Eo+Vgs. A current mirror of NMOS transistors 244 and 245 is connected to the gate of the NMOS transistor 242 via a resistor 243. Since the output voltage Eo is applied to the resistor 243, when the resistance value of the resistor 243 is set to r, the current flowing to the drains of the NMOS transistors 244 and 245 becomes Eo / r. The current mirror of PMOS transistors 246 and 247 allows the same current as that flowing from the drain of PMOS transistor 246 to flow from the drain of PMOS transistor 247, thereby allowing constant current source 234A to output current Eo / r.

[0129] Furthermore, for example, the current generated by the constant current source 234 does not have to be a current proportional to the output voltage Eo, and may be a predetermined constant current.

[0130] Furthermore, in the above-mentioned embodiments 1 to 3, the ramp voltage to be compared with the feedback voltage is generated by subtracting a modulation signal corresponding to the ripple current from a reference voltage, but as described in the explanation of hysteresis control in the text, it is also possible to configure the feedback voltage to be added with a modulation signal and then compared with the reference voltage.

[0131] In the above-described first to third embodiments, hysteresis control is used as the control method because the control width, or hysteresis width, is constant regardless of the input voltage Ei, thereby improving control stability. However, it goes without saying that the on-time inversely proportional to the input / output voltage difference (Ei - Eo) of the present disclosure can be applied to control methods other than hysteresis control. Furthermore, the ability to constantize the fluctuations in the amplitude of the ripple current of the inductor 13 means that the maximum allowable current value requirement is eliminated when selecting the inductor 13. In the case of a step-down converter, the peak value of the inductor current is the output current plus half the amplitude of the ripple current. If the amplitude of the ripple current is constant, the peak value of the inductor current is also constant regardless of the input voltage Ei. As can be seen from Figure 3B, in the conventional method, the amplitude of the ripple current is maximum when the input voltage Ei is maximum. However, the method of the present disclosure, which maintains a constant amplitude of the ripple current, can substantially reduce the maximum peak value of the inductor current. In other words, this contributes to the miniaturization of the inductor 13.

[0132] In the above-described embodiments, each component (particularly the control unit) included in the DC-DC converter may be configured with dedicated hardware, or may be realized by executing a software program suitable for each component. Each component may be realized by a program execution unit such as a CPU or processor reading and executing a software program recorded on a recording medium such as a hard disk or semiconductor memory.

[0133] Some or all of the functions of the DC-DC converter according to the above embodiments are typically realized as an LSI, which is an integrated circuit. These may be individually implemented as single chips, or some or all of them may be integrated into a single chip. Furthermore, the integrated circuit is not limited to an LSI, and may be realized using a dedicated circuit or a general-purpose processor. It is also possible to use an FPGA (Field Programmable Gate Array) that can be programmed after LSI manufacturing, or a reconfigurable processor that can reconfigure the connections and settings of circuit cells within the LSI.

[0134] Furthermore, if an integrated circuit technology that can replace LSIs emerges due to advances in semiconductor technology or other derivative technologies, it is natural that each component included in the DC-DC converter can be integrated using that technology.

[0135] In addition, this disclosure also includes forms obtained by making various modifications to the embodiments that a person skilled in the art would think of, and forms realized by arbitrarily combining the components and functions in each embodiment within the scope of the present disclosure.

[0136] (Additional Notes) The above description of the embodiments discloses the following techniques.

[0137] (Technology 1) A DC-DC converter that controls DC output power by controlling the on and off of a high-side switch, and that includes a control unit that adjusts the off time of the high-side switch to control the output power, and the control unit makes the on time of the high-side switch inversely proportional to an input / output voltage difference, which is the difference between an input voltage to the DC-DC converter and an output voltage from the DC-DC converter.

[0138] This allows the on-time of the high-side switch to be inversely proportional to the input / output voltage difference, thereby suppressing both fluctuations in the switching frequency and fluctuations in the amplitude of the ripple current. Specifically, this suppresses the switching frequency while almost completely eliminating fluctuations in the amplitude of the ripple current, enabling stable operation over a wide input voltage range.

[0139] (Technology 2) In a DC-DC converter according to Technology 1, the control unit includes a current source circuit that generates a current proportional to the input / output voltage difference, and an on-time setting circuit having an on-time setting capacitor through which current from the current source circuit flows, and the on-time setting circuit turns off the high-side switch when a change in voltage of the on-time setting capacitor from the time the high-side switch was turned on reaches a predetermined value.

[0140] According to this, the current flowing through the on-time setting capacitor is proportional to the input-output voltage difference, and therefore the time from when the high-side switch is turned on until the amount of change in the voltage of the on-time setting capacitor reaches a predetermined value, which corresponds to the on-time of the high-side switch, is inversely proportional to the input-output voltage difference. Therefore, by providing the control unit with a current source circuit and an on-time setting circuit, the on-time of the high-side switch can be made inversely proportional to the input-output voltage difference.

[0141] (Technology 3) A DC-DC converter according to Technology 2, wherein the control unit further includes a feedback circuit that generates a feedback voltage corresponding to the output voltage, and an off-time setting circuit having an off-time setting capacitor, wherein the off-time setting circuit charges the voltage of the off-time setting capacitor to a predetermined voltage when the high-side switch is turned on, discharges the off-time setting capacitor with a current from the current source circuit that is proportional to the input-output voltage difference during an on-period of the high-side switch, charges the off-time setting capacitor with a predetermined constant current or a current that is proportional to the output voltage during an off-period of the high-side switch, and turns on the high-side switch when the voltage of the off-time setting capacitor reaches the feedback voltage.

[0142] According to this, the time from when the high-side switch is turned off until the voltage of the off-time setting capacitor reaches the feedback voltage, which corresponds to the off-time of the high-side switch, is set in consideration of the feedback voltage corresponding to the output voltage. Therefore, by providing the control unit with a feedback circuit and an off-time setting circuit, the off-time of the high-side switch can be set so as to suppress fluctuations in the output voltage, thereby stabilizing the output voltage. Furthermore, since the off-time setting capacitor is gradually discharged by a current from the current source circuit proportional to the input-output voltage difference during the on-time of the high-side switch, the generation of noise can be suppressed more than when the off-time setting capacitor is suddenly discharged.

[0143] (Technology 4) In the DC-DC converter according to Technology 2, the control unit further includes a feedback circuit that generates a feedback voltage corresponding to the output voltage, and an off-time setting circuit having an off-time setting capacitor, wherein the off-time setting circuit discharges the voltage of the off-time setting capacitor to a predetermined voltage during an on-period of the high-side switch, charges the off-time setting capacitor with a predetermined constant current or a current proportional to the output voltage during an off-period of the high-side switch, and turns on the high-side switch when the voltage of the off-time setting capacitor reaches the feedback voltage.

[0144] According to this, the time from when the high-side switch is turned off until the voltage of the off-time setting capacitor reaches the feedback voltage, which corresponds to the off-time of the high-side switch, is set in consideration of the feedback voltage corresponding to the output voltage. Therefore, by providing the control unit with a feedback circuit and an off-time setting circuit, the off-time of the high-side switch can be set so as to suppress fluctuations in the output voltage, and the output voltage can be stabilized.

[0145] (Technology 5) A DC-DC converter according to Technology 1, wherein the control unit includes a current source circuit that generates a current proportional to the input / output voltage difference, a feedback circuit that generates a feedback voltage corresponding to the output voltage, a capacitor, an on-time setting circuit, and an off-time setting circuit, wherein the on-time setting circuit charges the capacitor to a first voltage when the high-side switch is turned on, discharges the capacitor with a current from the current source circuit that is proportional to the input / output voltage difference during an on-period of the high-side switch, and turns off the high-side switch when the voltage of the high-side switch reaches a second voltage that is lower than the first voltage, and the off-time setting circuit charges the capacitor with a predetermined constant current or a current proportional to the output voltage during an off-period of the high-side switch, and turns on the high-side switch when the voltage of the capacitor reaches the feedback voltage.

[0146] According to this, because the current discharged from the capacitor is proportional to the input-output voltage difference, the time it takes for the voltage of the high-side switch to reach the second voltage from the first voltage, which corresponds to the on-time of the high-side switch, is inversely proportional to the input-output voltage difference. Therefore, by including a current source circuit and an on-time setting circuit in the control unit, the on-time of the high-side switch can be made inversely proportional to the input-output voltage difference. Furthermore, taking into account the feedback voltage corresponding to the output voltage, the time from when the high-side switch is turned off until the voltage of the capacitor reaches the feedback voltage, which corresponds to the off-time of the high-side switch, is set. Therefore, by including a feedback circuit and an off-time setting circuit in the control unit, the off-time of the high-side switch can be set to suppress fluctuations in the output voltage, thereby stabilizing the output voltage. Furthermore, because the on-time setting circuit and the off-time setting circuit share a capacitor, the DC-DC converter can be made smaller.

[0147] The DC-DC converter according to the present disclosure can be used as a power supply device that steps down an input DC voltage to obtain a desired output DC voltage.

[0148] 1, 1A, 1B DC-DC converter 2, 2A, 2B control unit 10 DC power supply 11 high-side switch 12 low-side switch 13 inductor 14 output capacitor 20, 223 reference voltage source 21, 21A, 21B current source circuit 22, 22B on-time setting circuit 23, 23A, 23B off-time setting circuit 24, 25, 211, 212, 212A, 212B, 213, 214, 241, 243 resistor 26 drive circuit 27 capacitor 210, 215, 216, 246, 247 PMOS transistor 220 on-time setting capacitor 221, 224, 227, 233, 235, 236, 236A switch 222, 222B, 237 comparator 230 Off time setting capacitors 225, 226, 231, 232, 242, 244, 245 NMOS transistors 234, 234A constant current source 238 trigger circuit

Claims

1. A DC-DC converter that controls the DC output power by controlling the on / off state of the high-side switch, The system includes a control unit that adjusts the off time of the high-side switch in order to control the output power, The control unit makes the on-time of the high-side switch inversely proportional to the input-output voltage difference, which is the difference between the input voltage to the DC-DC converter and the output voltage from the DC-DC converter. The control unit, A current source circuit that generates a current proportional to the input-output voltage difference, An on-time setting circuit having an on-time setting capacitor through which current flows from the current source circuit, A feedback circuit that generates a feedback voltage corresponding to the output voltage, The circuit comprises an off-time setting circuit having an off-time setting capacitor, The on-time setting circuit turns off the high-side switch when the change in the voltage of the on-time setting capacitor from the time the high-side switch is turned on reaches a predetermined value. The aforementioned off-time setting circuit is When the high-side switch is turned on, the voltage of the off-time setting capacitor is charged to a predetermined voltage. During the ON period of the high-side switch, the off-time setting capacitor is discharged by a current from the current source circuit that is proportional to the input / output voltage difference. During the off period of the high-side switch, the off-time setting capacitor is charged with a predetermined constant current or a current proportional to the output voltage. When the voltage of the off-time setting capacitor reaches the feedback voltage, the high-side switch is turned on. DC-DC converter.

2. A DC-DC converter that controls the DC output power by controlling the on and off states of a high-side switch, The system includes a control unit that adjusts the off time of the high-side switch in order to control the output power, The control unit makes the on-time of the high-side switch inversely proportional to the input-output voltage difference, which is the difference between the input voltage to the DC-DC converter and the output voltage from the DC-DC converter. The control unit, A current source circuit that generates a current proportional to the input-output voltage difference, An on-time setting circuit having an on-time setting capacitor through which current flows from the current source circuit, A feedback circuit that generates a feedback voltage corresponding to the output voltage, The circuit comprises an off-time setting circuit having an off-time setting capacitor, The on-time setting circuit turns off the high-side switch when the change in the voltage of the on-time setting capacitor from the time the high-side switch is turned on reaches a predetermined value. The aforementioned off-time setting circuit is During the ON period of the high-side switch, the voltage of the off-time setting capacitor is discharged to a predetermined voltage. During the off period of the high-side switch, the off-time setting capacitor is charged with a predetermined constant current or a current proportional to the output voltage. When the voltage of the off-time setting capacitor reaches the feedback voltage, the high-side switch is turned on. DC-DC converter.

3. A DC-DC converter that controls the DC output power by controlling the on and off states of a high-side switch, The system includes a control unit that adjusts the off time of the high-side switch in order to control the output power, The control unit makes the on-time of the high-side switch inversely proportional to the input-output voltage difference, which is the difference between the input voltage to the DC-DC converter and the output voltage from the DC-DC converter. The control unit, A current source circuit that generates a current proportional to the input-output voltage difference, A feedback circuit that generates a feedback voltage corresponding to the output voltage, Capacitors and, On-time setting circuit, It includes an off-time setting circuit, The aforementioned on-time setting circuit is When the high-side switch is turned on, the voltage of the capacitor is charged to a first voltage. During the ON period of the high-side switch, the capacitor is discharged by a current from the current source circuit that is proportional to the input / output voltage difference. When the voltage of the high-side switch reaches a second voltage lower than the first voltage, the high-side switch is turned off. The aforementioned off-time setting circuit is During the off period of the high-side switch, the capacitor is charged with a predetermined constant current or a current proportional to the output voltage. When the voltage across the capacitor reaches the feedback voltage, the high-side switch is turned on. DC-DC converter.