High thermal conductivity, high modulus structure within a mold material layer of an integrated circuit package

Abstract

An integrated circuit assembly may be formed comprising an electronic substrate, at least one integrated circuit device electrically attached to the electronic substrate, a mold material layer adjacent to the electronic substrate and substantially surrounding at least one integrated circuit, and at least one structure within the mold material layer—at least one structure comprising a material having a thermal conductivity of more than about 10 watts per meter-Kelvin and a modulus of more than about 20 gigapascals.

Description

Technology Field

[0001] The embodiments of this description generally relate to the field of manufacturing molded integrated circuit packages, more specifically, to incorporating high modulus, high thermal conductivity structures into a mold material layer of an integrated circuit package. Background Technology

[0002] The integrated circuit industry continues to strive to produce much faster, smaller, and thinner integrated circuit (IC) devices and packages for use in a wide variety of electronic products, including computer servers and portable devices, such as portable computers, electronic tablets, cellular phones, and digital cameras, but not limited to these.

[0003] One path to achieving these goals is tighter packaging of integrated circuit devices. One such arrangement, known as a stacked composite die, comprises multiple integrated circuit devices attached to an electronic substrate, either passively or actively, and a layer of mold material on the electronic substrate substantially surrounds or encloses the multiple integrated circuit devices. Although such an integrated circuit package may be an effective method for packaging integrated circuit devices, as understood by those skilled in the art, it exhibits higher warping than monolithic silicon because the mold material layer causes temperature fluctuations. This warping can cause delamination and / or cracking of the mold material layer, which can lead to failure of the integrated circuit package. Warping can occur from temperature fluctuations during temperature cycles in manufacturing processes, such as from the operation of the integrated circuit package and / or from the thermal compression bonding of the integrated circuit package to the board.

[0004] In addition, when the substrate is active, for example, an integrated circuit device, it can generate significant heat, which may be difficult to transfer to a heat dissipation device through the mold material layer and multiple integrated circuit devices. This issue can be mitigated by using a thermally conductive mold material to form the mold material layer. However, thermally conductive mold materials generally have high coefficients of thermal expansion, which can exacerbate warping. Brief explanation of the drawing

[0005] The subject matter of the present disclosure is particularly noted and explicitly claimed in the concluding section of the specification. The foregoing and other features of the present disclosure will become more fully apparent from the following description and appended claims, taken together with the accompanying drawings. It is understood that the accompanying drawings illustrate only some embodiments according to the present disclosure and, therefore, should not be considered as limiting the scope thereof. The present disclosure will be further described in specific and detailed manner through the use of the accompanying drawings so that the advantages of the present disclosure may be more easily recognized. FIG. 1 is a side cross-sectional view of an integrated circuit assembly according to one embodiment of the present description. FIGS. 2 to 4 are plan views of an integrated circuit assembly along line 2-2 of FIG. 1 according to embodiments of the present description. FIGS. 5 to 8 are cross-sectional views of a method for manufacturing an integrated circuit assembly according to an embodiment of the present description. FIGS. 9 to 12 are cross-sectional views of other methods for manufacturing an integrated circuit assembly according to one embodiment of the present description. FIG. 13 is a side cross-sectional view of an integrated circuit assembly according to another embodiment of the present description. FIG. 14 is a flowchart of a process for manufacturing an integrated circuit assembly according to an embodiment of the present description. FIG. 15 is an electronic system according to one embodiment of the present description. Specific details for implementing the invention

[0006] In the following detailed description, reference is made to the accompanying drawings, which illustrate, by example, specific embodiments in which the claimed subject matter may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the subject matter. It should be understood that various embodiments, while different, are not necessarily mutually exclusive. For example, specific features, structures, or characteristics described herein in relation to one embodiment may be implemented in other embodiments without departing from the spirit and scope of the claimed subject matter. References to "one embodiment" or "an embodiment" within this specification mean that specific features, structures, or characteristics described in relation to that embodiment are included in at least one implementation encompassed within this description. Accordingly, the use of the phrases "one embodiment" or "in an embodiment" does not necessarily refer to the same embodiment. Furthermore, it should be understood that the location or arrangement of individual elements within each disclosed embodiment may be modified without departing from the spirit and scope of the claimed subject matter. Accordingly, the following detailed description is not to be taken in a limiting sense, and the scope of the subject matter is defined only by the appended claims, as appropriately interpreted, together with equivalents of the full scope to which the appended claims are granted. In the drawings, similar reference numbers refer to identical or similar elements or functions throughout several drawings, and the elements depicted therein are not necessarily scaled to one another; rather, individual elements may be enlarged or reduced to make them easier to understand in the context of this description.

[0007] The terms “over,” “to,” “between,” and “on,” as used herein, may refer to the relative position of one layer with respect to other layers. A layer “over” or “on” another layer, or “to” another layer, may be in direct contact with the other layer or may have one or more interlayers. A layer “between” the layers may be in direct contact with those layers or may have one or more interlayers.

[0008] The term "package" generally refers to a self-contained carrier of one or more dies, which are attached to a package substrate and may be encapsulated for protection by integrated or wire-junction interconnects between the dies and leads, pins, or bumps located on the outer parts of the package substrate. A package may include a single die or multiple dies that provide specific functions. A package is typically mounted on a printed circuit board to interconnect with other packaged integrated circuits and separate components, forming a larger circuit.

[0009] Here, the term "cored" generally refers to a substrate of an integrated circuit package built on a board, card, or wafer comprising a non-flexible rigid material. Typically, a small printed circuit board is used as the core, and integrated circuit devices and separate passive components can be soldered thereon. Typically, the core has vias extending from one side to the other, which allow a circuit on one side of the core to be directly connected to a circuit on the opposite side of the core. The core can also serve as a platform for building layers of conductors and dielectric materials.

[0010] Here, the term "coreless" generally refers to a substrate of an integrated circuit package that does not have a core. Because through-vias have relatively large dimensions and pitches compared to high-density interconnects, the absence of a core allows for high-density package architectures.

[0011] Herein, the term "land side," as used herein, generally refers to the side of the substrate of an integrated circuit package closest to the plane of attachment to a printed circuit board, motherboard, or other package. This is in contrast to the term "die side," which refers to the side of the substrate of an integrated circuit package to which a die or dies are attached.

[0012] Here, the term "dielectric" generally refers to any number of non-electrically conductive materials constituting the structure of the package substrate. For the purposes of this disclosure, the dielectric material may be incorporated into an integrated circuit package as a resin molded onto integrated circuit dies mounted on the substrate or as layers of a laminated film.

[0013] Here, the term "metallization" generally refers to metal layers formed on and through the dielectric material of a package substrate. These metal layers are typically patterned to form metal structures such as traces and junction pads. This metallization of the package substrate may be limited to a single layer or to multiple layers separated by layers of dielectric material.

[0014] Here, the term "bond pad" generally refers to metallized structures that terminate traces and vias integrated in integrated circuit packages and dies. The term "solder pad" may sometimes be used interchangeably with "bond pad" and conveys the same meaning.

[0015] Here, the term "solder bump" generally refers to a solder layer formed on a bonding pad. This solder layer typically has a round shape, and therefore is called a "solder bump."

[0016] Here, the term "substrate" generally refers to a planar platform comprising dielectric and metallized structures. Such a substrate mechanically supports and electrically connects one or more IC dies on a single platform through the encapsulation of one or more IC dies by a moldable dielectric material. Such a substrate generally includes solder bumps as bonding interconnects on both sides. One side of the substrate, generally referred to as the "die side," includes solder bumps for bonding the chip or die. The opposite side of the substrate, generally referred to as the "land side," includes solder bumps for bonding the package to a printed circuit board.

[0017] Here, the term "assembly" generally refers to the grouping of parts into a single functional unit. These parts may be separate or mechanically assembled into a functional unit, where they may be removable. In other cases, these parts may be permanently joined together. In some cases, these parts are integrated together.

[0018] Throughout this specification and in the claims, the term “connected” means a direct connection, such as an electrical, mechanical, or magnetic connection between directly connected things without any intermediary devices.

[0019] The term "coupled" means a direct or indirect connection, such as a direct electrical, mechanical, magnetic, or fluid connection between the connected things, or an indirect connection through one or more passive or active intermediary devices.

[0020] The terms "circuit" or "module" may refer to one or more passive and / or active components arranged to cooperate with one another to provide a desired function. The term "signal" may refer to at least one current signal, voltage signal, magnetic signal, or data / clock signal. The meaning of the singular expressions ("a," "an," and "the") includes plural references. The meaning of "in" includes "in" and "on."

[0021] It is understood that the vertical orientation is in the z-direction, and that the descriptions "top," "bottom," "above," and "below" refer to relative positions in the z-dimension in a general sense. However, it is understood that the embodiments are not necessarily limited to the orientations or configurations illustrated in the drawings.

[0022] The terms "substantially," "close," "approximately," "near," and "about" generally refer to being within + / - 10% of a target value (unless specifically stated otherwise). Unless otherwise stated, the use of ordinal adjectives such as "first," "second," "third," etc., to describe common objects merely indicates different instances of the similar objects being referred to and is not intended to imply that the objects thus described must exist in a given sequence, temporally, spatially, or in any other way.

[0023] For the purposes of this disclosure, the phrases “A and / or B” and “A or B” mean (A), (B), or (A and B). For the purposes of this disclosure, the phrase “A, B, and / or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).

[0024] The diagrams labeled "cross-sectional," "profile," and "plan" correspond to orthogonal planes within the Cartesian coordinate system. Thus, cross-sectional and profile diagrams are taken in the xz plane, and plan diagrams are taken in the xy plane. Typically, profile diagrams in the xz plane are cross-sectional diagrams. Where appropriate, the diagrams are labeled with axes to indicate the orientation of the diagram.

[0025] The embodiments of the present description include methods for manufacturing an integrated circuit package, comprising: an integrated circuit package; an electronic substrate; at least one integrated circuit device electrically attached to the electronic substrate; a mold material layer adjacent to the electronic substrate and substantially surrounding the at least one integrated circuit device; and at least one structure within the mold material layer—the at least one structure comprising a material having a high modulus and high thermal conductivity.

[0026] FIG. 1 illustrates an integrated circuit assembly (100) having an integrated circuit package (110) electrically connected to an electronic board (120). According to one embodiment of the present description, the integrated circuit package (110) may include at least one integrated circuit device (exemplified as a first integrated circuit device (1401), a second integrated circuit device (1402), and a third integrated circuit device (1403)) electrically attached to an electronic board (150) in a configuration generally known as a flip-chip or "C4" (controlled collapse chip connection) configuration.

[0027] The first integrated circuit device (1401), the second integrated circuit device (1402), and the third integrated circuit device (1403) may be any suitable device, including, but not limited to, a microprocessor, a chipset, a graphics device, a wireless device, a memory device, an application-specific integrated circuit, combinations thereof, stacks thereof, etc. As illustrated, the first integrated circuit device (1401), the second integrated circuit device (1402), and the third integrated circuit device (1403) may each have a first surface (142), an opposite second surface (144), and at least one side (146) extending between the first surface (142) and the second surface (144).

[0028] In the embodiment of the description illustrated in FIG. 1, the first integrated circuit device (1401), the second integrated circuit device (1402), and the third integrated circuit device (1403) may be electrically attached to an electronic board (150) by a plurality of device-to-board interconnects (160). These device-to-board interconnects (160) may be any suitable electrically conductive material or structure, including, but not limited to, solder balls, metal bumps or fillers, metal-filled epoxy, or a combination thereof. In one embodiment, the device-to-substrate interconnects (160) may be solder balls formed from tin, lead / tin alloys (e.g., 63% tin / 37% lead solder), and high tin content alloys (e.g., tin / bismuth, eutectic tin / silver, ternary tin / silver / copper, eutectic tin / copper, and similar alloys, with more than 90% tin). In another embodiment, the device-to-substrate interconnects (160) may be copper bumps or fillers. In a further embodiment, the device-to-substrate interconnects (160) may be metal bumps or fillers coated with solder material. The device-to-board interconnects (160) may be electrically communicating with the integrated circuits (not shown) in their respective integrated circuit devices, namely the first integrated circuit device (1401), the second integrated circuit device (1402), and the third integrated circuit device (1403).

[0029] An electrically insulating underfill material (170), such as an epoxy material, may be placed between the first integrated circuit device (1401) and the electronic substrate (150), between the second integrated circuit device (1402) and the electronic substrate (150), and between the third integrated circuit device (1403) and the electronic substrate (150). As understood by those skilled in the art, the underfill material (170) is a viscous liquid and may be administered between the first surface (142) of each of the integrated circuit devices (1401, 1402, 1403) and the electronic substrate (150), and then cured by a curing process. The underfill material (170) may also be a molded underfill material, as is known in the art. As understood by those skilled in the art, the underfill material (170) may provide structural integrity and prevent contamination.

[0030] The electronic board (150) may be any suitable device comprising a passive device, such as an interposer, a circuit board, etc., and / or an active device (e.g., having an integrated circuit), such as a microprocessor, a chipset, a graphics device, a wireless device, a memory device, an application-specific integrated circuit, combinations thereof, stacks thereof, etc. As illustrated, the electronic board (150) may include a first surface (152) and a second surface (154) opposite to it.

[0031] When the electronic substrate (150) is a passive device, it may comprise a plurality of dielectric material layers (not shown) that may include build-up films and / or solder resist layers, and may be composed of suitable dielectric materials including, but not limited to, bismaleimide triazine resin, flame retardant grade 4 material, polyimide material, silica-filled epoxy material, glass-reinforced epoxy material, etc., as well as, but not limited to, carbon-doped dielectrics, fluorine-doped dielectrics, porous dielectrics, organic polymer dielectrics, etc., low-k and ultra-low-k dielectrics (dielectric constants of less than about 3.6). The electronic substrate (150) may further comprise conductive paths or "metallization" (not shown) extending through the electronic substrate (150). As understood by those skilled in the art, the conductive paths may be a combination of conductive traces (not shown) and conductive vias (not shown) extending through multiple dielectric material layers (not shown). These conductive traces and conductive vias are well known in the art and are not shown in FIG. 1 for the sake of clarity. The conductive traces and conductive vias may be made of any suitable conductive material, including, but not limited to, metals such as copper, silver, nickel, gold, aluminum, alloys thereof, etc. As understood by those skilled in the art, the electronic substrate (150) may be a cored substrate or a coreless substrate.

[0032] When the electronic substrate (150) is an active device, it may be any suitable device including, but not limited to, a microprocessor, a chipset, a graphics device, a wireless device, a memory device, an application-specific integrated circuit, combinations thereof, stacks thereof, etc. The first integrated circuit device (1401), the second integrated circuit device (1402), and the third integrated circuit device (1403) may be electrically attached to silicon-through-vias (not shown) on the second surface (154) of the electronic substrate (150) (as active devices). Silicon-through-vias are known in the art and will be discussed or illustrated in this specification for the purposes of clarity and brevity.

[0033] The electronic board (120) may be a passive device and, similar to the passive electronic substrate (150) previously discussed, may comprise a plurality of dielectric material layers (not shown) which may include build-up films and / or solder resist layers, and may be composed of suitable dielectric materials including, but not limited to, bismaleimide triazine resin, flame retardant grade 4 material, polyimide material, silica-filled epoxy material, glass-reinforced epoxy material, etc., as well as, but not limited to, carbon-doped dielectrics, fluorine-doped dielectrics, porous dielectrics, organic polymer dielectrics, etc., low-k and ultra-low-k dielectrics (dielectric constants of less than about 3.6). The electronic board (120) may further comprise conductive paths or "metallization" (128) (shown by dashed lines) extending through the electronic board (120). As understood by those skilled in the art, the conductive paths (128) may be a combination of conductive traces (not shown) and conductive vias (not shown) extending through multiple dielectric material layers (not shown). These conductive traces and conductive vias are well known in the art and are not shown in FIG. 1 for the sake of clarity. The conductive traces and conductive vias may be made of any suitable conductive material, including, but not limited to, metals such as copper, silver, nickel, gold, aluminum, alloys thereof, etc. As understood by those skilled in the art, the electronic board (120) may be a cored substrate or a coreless substrate.

[0034] In an embodiment of the present description, an integrated circuit package (110) may be electrically attached to an electronic board (120) by a plurality of package-to-board interconnects (130). In one embodiment of the present description, the package-to-board interconnects (130) may extend between bonding pads (156) on a first surface (152) of an electronic substrate (150) and bonding pads (124) on a first surface (122) of an electronic board (120). These package-to-board interconnects (130) may be any suitable electrically conductive material or structure, including, but not limited to, solder balls, metal bumps or fillers, metal-filled epoxy, or a combination thereof. In one embodiment, the package-to-board interconnects (130) may be solder balls formed from tin, lead / tin alloys (e.g., 63% tin / 37% lead solder), and high tin content alloys (e.g., tin / bismuth, eutectic tin / silver, ternary tin / silver / copper, eutectic tin / copper, and similar alloys, with more than 90% tin). In another embodiment, the package-to-board interconnects (130) may be copper bumps or fillers. In a further embodiment, the package-to-board interconnects (130) may be metal bumps or fillers coated with solder material.

[0035] Bonding pads (124) on the first surface (122) of the electronic board (120) may be in electrical contact with conductive paths (128). The conductive paths (128) may extend through the electronic board (120) and be electrically connected to external components (not shown).

[0036] As further illustrated in FIG. 1, a mold material layer (180) may be formed on an electronic substrate (150). The mold material layer (180) may be any suitable material, such as epoxy resin. As understood by those skilled in the art, the mold material layer (180) may provide structural integrity and prevent contamination. At least one high thermal conductivity, high modulus structure (190) may be formed within the mold material layer (180). The at least one structure (190) may be made of any suitable high modulus and high thermal conductivity material, including, but not limited to, metal, graphene, sintered paste, etc. In one embodiment, the metal material may include copper, silver, nickel, gold, aluminum, alloys thereof, etc. In another embodiment, the graphene material may include aligned graphene, functionalized graphene, sheet graphene, etc. In another embodiment, the complete or partial sintered paste may comprise silver, silver-coated copper particles, copper / tin intermetallic compounds, tin / antimony alloys in an epoxy or silicon matrix, etc. In one embodiment, at least one structure (190) may comprise a material having a thermal conductivity of more than about 10 watts per meter-Kelvin and a modulus of more than about 20 gigapascals.

[0037] Although three integrated circuit devices (1401, 1402, and 1403) are shown in FIG. 1, the integrated circuit package (110) may have any suitable number of integrated circuit devices, such as the integrated circuit devices (1401 to 1409) shown in FIG. 2. Additionally, at least one structure (190) may have any suitable configuration. In one embodiment of the present description, as shown in FIG. 2, at least one structure (190) may be a single structure surrounding the integrated circuit devices (1401 to 1409), similar to a frame for a picture, e.g., a "picture frame." In another embodiment of the present description, at least one structure (190) may include a plurality of segments, such as L-shaped walls (1901 to 1904) shown in FIG. 3, wall segments (1905 to 1908) shown in FIG. 4.

[0038] FIGS. 5 through 8 illustrate a process for manufacturing an integrated circuit package (110) according to one embodiment of the present description. As shown in FIG. 5, at least one integrated circuit device (1401 to 1403) may be electrically attached to an electronic substrate (150) through a plurality of device-to-substrate interconnects (160), and an underfill material (170) may be disposed between the integrated circuit devices (1401 to 1403) and the electronic substrate (150). As shown in FIG. 6, at least one structure (190) may be formed on the electronic substrate (150). The at least one structure (190) may be formed by any process known in the art, including, but not limited to, plating, deposition, printing, etc. As illustrated in FIG. 7, a mold material layer (180) may be formed on an electronic substrate (150), at least one structure (190), and integrated circuit devices (1401 to 1403). The mold material layer (180) may be formed by dispensing, lamination, the use of a mold chase, etc. The mold material layer (180) may be flattened, such as by chemical-mechanical polishing (CMP), so as to be exposed in a portion of the second surfaces (144) of at least one structure (190) and the integrated circuit devices (1401 to 1403), thereby forming an integrated circuit package (110) as illustrated in FIG. 8.

[0039] FIGS. 9 through 12 illustrate a process for manufacturing an integrated circuit package (110) according to one embodiment of the present description. Starting with a structure illustrated and discussed in relation to FIG. 5, a mold material layer (180) may be formed on an electronic substrate (150) and integrated circuit devices (1401 to 1403), as shown in FIG. 9. As shown in FIG. 10, the mold material layer (180) may be flattened, as previously discussed, to expose second surfaces (144) of the integrated circuit devices (1401 to 1403). As shown in FIG. 11, at least one trench (192) may be formed through the mold material layer (180) to expose a portion of the electronic substrate (150). At least one trench (192) may be formed by any suitable process known in the art, including but not limited to laser drilling, ion ablation, etching, etc. As shown in FIG. 12, at least one structure (190) may be formed on an electronic substrate (150) within at least one trench (192) (see FIG. 11) to form an integrated circuit package (110). At least one structure (190) may be formed by any process known in the art, including but not limited to plating, deposition, printing, etc.

[0040] It is understood that embodiments are not limited to the integrated circuit assembly (100) of FIG. 1 and may be any suitable configuration. In one embodiment illustrated in FIG. 13, the integrated circuit assembly (100) may include a motherboard (194), and an electronic board (120) is electrically attached to the motherboard (194). The motherboard (194) may be a passive device and, similar to the passive electronic board (120) previously discussed, may be composed of a plurality of dielectric material layers (not shown) and conductive paths or "metallization" (198) (shown by dashed lines) extending through the motherboard (194). As understood by those skilled in the art, the conductive paths (198) may be a combination of conductive traces (not shown) and conductive vias (not shown) extending through a plurality of dielectric material layers (not shown). These conductive traces and conductive vias are well known in the art and are not shown in FIG. 13 for the sake of clarity. As understood by those skilled in the art, the motherboard (194) may be a cored substrate or a coreless substrate.

[0041] In an embodiment of the present description, the electronic board (120) may be electrically attached to the motherboard (194) by a plurality of board-to-board interconnects (134). In one embodiment of the present description, the board-to-board interconnects (134) may extend between the bonding pads (132) on the second surface (126) of the electronic board (120) and the bonding pads (136) on the first surface (196) of the motherboard (194). The board-to-board interconnects (134) may have a configuration and composition similar to the package-to-board interconnects (130) previously discussed.

[0042] As further illustrated in FIG. 13, an underfill material (172) may be placed between the integrated circuit package (110) and the electronic board (120). Additionally, bonding pads (136) on the first surface (196) of the motherboard (194) may be in electrical contact with conductive paths (198). The conductive paths (198) may extend through the motherboard (194) and be electrically connected to external components (not illustrated).

[0043] FIG. 14 is a flowchart of a process (200) for manufacturing an integrated circuit assembly according to an embodiment of the present description. As shown in block 210, an electronic substrate may be formed. As shown in block 220, at least one integrated circuit device may be formed. As shown in block 230, at least one integrated circuit device may be electrically attached to the electronic substrate. As shown in block 240, a mold material layer may be formed adjacent to the electronic substrate and substantially surrounding at least one integrated circuit device. As shown in block 250, at least one structure may be formed within the mold material layer, and such at least one structure comprises a material having a thermal conductivity of more than about 10 watts per meter-Kelvin and a modulus of more than about 20 gigapascals.

[0044] FIG. 15 illustrates an electronic or computing device (300) according to one implementation of the present description. The computing device (300) may include a housing (301) having a board (302) disposed inside. A computing device (300) may include, but is not limited to, a number of integrated circuit components including a processor (304), at least one communication chip (306A, 306B), volatile memory (308) (e.g., DRAM), non-volatile memory (310) (e.g., ROM), flash memory (312), a graphics processor or CPU (314), a digital signal processor (not shown), a cryptographic processor (not shown), a chipset (316), an antenna, a display (touchscreen display), a touchscreen controller, a battery, an audio codec (not shown), a video codec (not shown), a power amplifier (AMP), a global positioning system (GPS) device, a compass, an accelerometer (not shown), a gyroscope (not shown), a speaker, a camera, and a mass storage device (not shown) (such as a hard disk drive, a CD (compact disk), a DVD (digital versatile disk), etc.). Any of these integrated circuit components may be physically and electrically connected to the board (302). In some implementations, at least one of these integrated circuit components may be part of the processor (304).

[0045] Communication chips enable wireless communication for the transmission of data to and from computing devices. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc., capable of communicating data through the use of modulated electromagnetic radiation over a non-solid medium. These terms do not imply that the related devices do not include any wiring, although this may not be the case in some embodiments. The communication chip may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, LTE (long term evolution), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, and derivatives thereof, as well as any other wireless protocols designated as 3G, 4G, 5G, and beyond. The computing device may include a number of communication chips. For example, the first communication chip may be dedicated to short-range wireless communication such as Wi-Fi and Bluetooth, and the second communication chip may be dedicated to long-range wireless communication such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

[0046] The term "processor" may refer to any device or part of a device that processes electronic data from registers and / or memory and converts said electronic data into other electronic data that can be stored in registers and / or memory.

[0047] At least one of the integrated circuit components may comprise an integrated circuit assembly comprising: an electronic substrate; at least one integrated circuit device electrically attached to the electronic substrate; a mold material layer adjacent to the electronic substrate and substantially surrounding the at least one integrated circuit device; and at least one structure within the mold material layer—at least one structure comprising a material having a thermal conductivity of more than about 10 watts per meter-Kelvin and a modulus of more than about 20 gigapascals.

[0048] In various implementations, the computing device may be a laptop, netbook, notebook, ultrabook, smartphone, tablet, PDA (personal digital assistant), ultra-mobile PC, mobile phone, desktop computer, server, printer, scanner, monitor, set-top box, entertainment control unit, digital camera, portable music player, or digital video recorder. In additional implementations, the computing device may be any other electronic device that processes data.

[0049] It is understood that the subject matter of this description is not necessarily limited to the specific applications exemplified in FIGS. 1 through 15. As will be understood by those skilled in the art, the subject matter may be applicable to any suitable electronic application, as well as to other integrated circuit devices and assembly applications.

[0050] The following examples relate to additional embodiments, and details in the examples may be used anywhere in one or more embodiments, and Example 1 is an integrated circuit assembly comprising an electronic substrate, at least one integrated circuit device electrically attached to the electronic substrate, a mold material layer adjacent to the electronic substrate and substantially surrounding the at least one integrated circuit device, and at least one structure within the mold material layer—at least one structure comprises a material having a thermal conductivity of more than about 10 watts per meter-Kelvin and a modulus of more than about 20 gigapascals.

[0051] In Example 2, the subject of Example 1 may optionally include at least one material of the structure being selected from the group consisting of metal, graphene, and sintered paste.

[0052] In Example 3, the subject of any of Examples 1 to 2 may optionally include the electronic substrate being an active device.

[0053] In Example 4, the subject of any of Examples 1 to 2 may optionally include the electronic substrate being a passive device.

[0054] In Example 5, the subject of any of Examples 1 through 4 may optionally include at least one structure substantially surrounding at least one integrated circuit device.

[0055] Example 6 is an electronic system comprising a board and an integrated circuit assembly electrically attached to the board, wherein the integrated circuit assembly comprises an electronic substrate, at least one integrated circuit device electrically attached to the electronic substrate, a mold material layer adjacent to the electronic substrate and substantially surrounding at least one integrated circuit device, and at least one structure within the mold material layer—at least one structure comprises a material having a thermal conductivity of more than about 10 watts per meter-Kelvin and a modulus of more than about 20 gigapascals.

[0056] In Example 7, the subject of Example 6 may optionally include at least one material of the structure being selected from the group consisting of metal, graphene, and sintered paste.

[0057] In Example 8, the subject of any of Examples 6 to 7 may optionally include the electronic substrate being an active device.

[0058] In Example 9, the subject of any of Examples 6 to 7 may optionally include the electronic substrate being a passive device.

[0059] In Example 10, the subject of any of Examples 6 through 9 may optionally include at least one structure substantially surrounding at least one integrated circuit device.

[0060] Example 11 is a method for manufacturing an integrated circuit assembly, comprising the steps of forming an electronic substrate, forming at least one integrated circuit device, electrically attaching at least one integrated circuit device to the electronic substrate, forming a mold material layer adjacent to the electronic substrate and substantially surrounding at least one integrated circuit device, and forming at least one structure within the mold material layer—at least one structure comprising a material having a thermal conductivity of greater than about 10 watts per meter-Kelvin and a modulus of greater than about 20 gigapascals.

[0061] In Example 12, the subject of Example 11 may optionally include the electronic substrate being an active device.

[0062] In Example 13, the subject of Example 11 may optionally include the electronic substrate being a passive device.

[0063] In Example 14, the subject of any of Examples 11 to 13 may optionally include a step of forming at least one structure prior to the step of forming a mold material layer.

[0064] In Example 15, the subject of Example 14 may optionally include the step of forming at least one structure from a material of at least one structure selected from the group consisting of metal, graphene, and sintered paste.

[0065] In Example 16, the subject of Example 14 may optionally include a step of flattening a mold material layer to expose a portion of at least one integrated circuit device.

[0066] In Example 17, the subject of any of Examples 11 to 13 may optionally include the step of forming at least one trench in a mold material layer and the step of forming at least one structure in at least one trench.

[0067] In Example 18, the subject of Example 17 may optionally include the step of forming at least one structure from a material of at least one structure selected from the group consisting of metal, graphene, and sintered paste.

[0068] In Example 19, the subject of Example 17 may optionally include a step of flattening a mold material layer to expose a portion of at least one integrated circuit device prior to the step of forming at least one trench.

[0069] In Example 20, the subject of any of Examples 11 through 19 may optionally include at least one structure substantially surrounding at least one integrated circuit device.

[0070] Accordingly, embodiments of the present invention have been described in detail, and it is understood that the present invention, as defined by the appended claims, is not limited by the specific details set forth in the above description, because many obvious variations thereof are possible without departing from the spirit or scope thereof.

Claims

Claim 1 An integrated circuit assembly comprising: an electronic substrate; at least one integrated circuit device electrically attached to the electronic substrate; a mold material layer adjacent to the electronic substrate and surrounding the at least one integrated circuit device; and at least one structure within the mold material layer—the at least one structure comprising a material having a thermal conductivity of greater than 10 watts per meter-Kelvin and a modulus of greater than 20 gigapascals. Claim 2 An integrated circuit assembly according to claim 1, wherein the material of at least one structure is selected from the group consisting of metal, graphene, and sintered paste. Claim 3 In claim 1, the electronic substrate is an integrated circuit assembly that is an active device. Claim 4 In claim 1, the electronic substrate is an integrated circuit assembly that is a passive device. Claim 5 In claim 1, the at least one structure is an integrated circuit assembly surrounding the at least one integrated circuit device. Claim 6 An electronic system comprising: a board; an integrated circuit assembly electrically attached to the board, wherein the integrated circuit assembly comprises: an electronic substrate; at least one integrated circuit device electrically attached to the electronic substrate; a mold material layer adjacent to the electronic substrate and surrounding the at least one integrated circuit device; and at least one structure within the mold material layer—the at least one structure comprising a material having a thermal conductivity of greater than 10 watts per meter-Kelvin and a modulus of greater than 20 gigapascals. Claim 7 In claim 6, the material of the at least one structure is an electronic system selected from the group consisting of metal, graphene, and sintered paste. Claim 8 In paragraph 6, the electronic substrate is an electronic system that is an active device. Claim 9 In paragraph 6, the electronic substrate is an electronic system that is a passive device. Claim 10 In paragraph 6, the above at least one structure is an electronic system surrounding the above at least one integrated circuit device. Claim 11 A method for forming an integrated circuit assembly comprising: forming an electronic substrate; forming at least one integrated circuit device; electrically attaching the at least one integrated circuit device to the electronic substrate; forming a mold material layer adjacent to the electronic substrate and surrounding the at least one integrated circuit device; and forming at least one structure within the mold material layer, wherein the at least one structure comprises a material having a thermal conductivity of greater than 10 watts per meter-Kelvin and a modulus of greater than 20 gigapascals. Claim 12 In claim 11, the step of forming the electronic substrate comprises the step of forming an active device. Claim 13 In claim 11, the step of forming the electronic substrate includes the step of forming a passive device. Claim 14 In claim 11, the step of forming the at least one structure comprises the step of forming the at least one structure prior to the step of forming the mold material layer. Claim 15 In claim 14, the step of forming the at least one structure comprises forming the at least one structure from a material selected from the group consisting of metal, graphene, and sintered paste. Claim 16 A method according to claim 14, further comprising the step of flattening the mold material layer to expose a portion of the at least one integrated circuit device. Claim 17 In claim 11, the step of forming at least one structure comprises the step of forming at least one trench in the mold material layer and the step of forming at least one structure in the at least one trench. Claim 18 In claim 17, the step of forming the at least one structure in the at least one trench comprises the step of forming the at least one structure from a material selected from the group consisting of metal, graphene, and sintered paste. Claim 19 A method according to claim 17, further comprising the step of flattening the mold material layer to expose a portion of the at least one integrated circuit device prior to the step of forming the at least one trench. Claim 20 In claim 11, the step of forming at least one structure comprises the step of forming at least one structure to surround at least one integrated circuit device.

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