Field effect transistor including channel formed of 2D material

Abstract

A field-effect transistor is provided, comprising: a substrate; a source electrode and a drain electrode spaced apart from each other along a first direction on the substrate; a plurality of channel layers, each having two ends in contact with the source electrode and the drain electrode and spaced apart along a second direction away from the substrate, and comprising a two-dimensional semiconductor material; a gate insulating film surrounding each of the plurality of channel layers; and a gate electrode surrounding the gate insulating film.

Description

Technology Field

[0001] The disclosed embodiments relate to a field-effect transistor having a channel made of a 2D material. Background Technology

[0002] Transistors are semiconductor devices that perform the role of electrical switching and are employed in various integrated circuits, including memory, driver ICs, and logic devices. As the integration density of integrated circuits increases, the space occupied by transistors is rapidly shrinking; therefore, research is underway to maintain performance while reducing the size of transistors.

[0003] It is known that as the size of transistors decreases and the channel length shortens, problems caused by the short channel effect are triggered. Examples include phenomena such as threshold voltage variation, carrier velocity saturation, and deterioration of the subthreshold characteristics. Accordingly, methods to overcome the short channel effect and effectively reduce the channel length are being sought. The problem to be solved

[0004] A field-effect transistor having a channel made of a 2D material is provided. means of solving the problem

[0005] According to one type, a field effect transistor is provided, comprising: a substrate; a source electrode and a drain electrode spaced apart from each other along a first direction on the substrate; a plurality of channel layers spaced apart along a second direction away from the substrate, each having two ends in contact with the source electrode and the drain electrode, and comprising a two-dimensional semiconductor material; a gate insulating film surrounding each of the plurality of channel layers; and a gate electrode surrounding the gate insulating film.

[0006] Each of the plurality of channel layers includes two edges extended in a third direction perpendicular to the first direction and the second direction, respectively, and the two edges may contact the source electrode and the drain electrode, respectively.

[0007] Each of the above plurality of channel layers may include two contact regions that are in planar contact with the source electrode and the drain electrode.

[0008] The plurality of channel layers may include a first channel layer and a second channel layer having different lengths in the first direction.

[0009] The first channel layer and the second channel layer may be arranged from the substrate in an order in which the length of the first direction becomes shorter.

[0010] The first channel layer and the second channel layer may have different thicknesses.

[0011] The lengths of the third direction, which is perpendicular to the first direction and the second direction respectively, may differ from each other for the first channel layer and the second channel layer.

[0012] The first channel layer and the second channel layer can be arranged from the substrate in an order in which the length of the third direction becomes shorter.

[0013] The gate insulating film is in contact with the plurality of channel layers and may have a shape that surrounds each of the plurality of channel layers in a closed path with the first direction as an axis.

[0014] The gate electrode is spaced apart from the plurality of channel layers and may have a shape that surrounds each of the plurality of channel layers in a closed path with the first direction as an axis.

[0015] The gate insulating film may have a shape that extends into the region between the gate electrode and the source electrode and between the gate electrode and the drain electrode.

[0016] The above two-dimensional semiconductor material may include graphene, black phosphorus, phosphorene, or transition metal dichalcogenide.

[0017] The above transition metal dichalcogenide may include one metal element selected from the group consisting of Mo, W, Nb, V, Ta, Ti, Zr, Hf, Tc, Re, Cu, Ga, In, Sn, Ge, and Pb, and one chalcogen element selected from the group consisting of S, Se, and Te.

[0018] A predetermined conductive dopant can be doped into the above two-dimensional semiconductor material.

[0019] The above plurality of channel layers may include the same two-dimensional semiconductor material.

[0020] The gate insulating film may include a high-k dielectric material or a ferroelectric material.

[0021] The length of the first direction of the channel layer can be set to a minimum length determined by the thickness of the second direction of the channel layer.

[0022] The thickness of the second direction of the above channel layer may be 5 nm or less.

[0023] The thickness of the second direction of the above channel layer may be 1 nm or less.

[0024] The length of the first direction of the above channel layer may be 3 nm or less. Effects of the invention

[0025] The field-effect transistor described above has a multi-bridge type channel and employs a two-dimensional material for the channel material, thereby effectively reducing the channel length.

[0026] The aforementioned field-effect transistor has an ultra-small size and excellent electrical performance, making it suitable for application in high-density integrated circuit devices. Brief explanation of the drawing

[0027] FIG. 1 is a perspective view showing the schematic structure of a field-effect transistor according to an embodiment. Figure 2 is a cross-sectional view of the field-effect transistor of Figure 1. Figure 3 is a BB cross-sectional view of the field-effect transistor of Figure 1. Figure 4 is a graph conceptually showing that the minimum channel length due to the short channel effect varies depending on the channel thickness. FIGS. 5a to 5e are diagrams schematically illustrating a method for manufacturing a field-effect transistor of FIG. 1. FIG. 6 is a cross-sectional view showing the schematic structure of a field-effect transistor according to another embodiment. Figure 7 is a cross-sectional view of the field-effect transistor of Figure 6 shown in a different cross-section. FIG. 8 is a cross-sectional view showing the schematic structure of a field-effect transistor according to another embodiment. Figure 9 is a cross-sectional view of the field-effect transistor of Figure 8 shown in a different cross-section. FIG. 10 is a cross-sectional view showing the schematic structure of a field-effect transistor according to another embodiment. Figure 11 is a cross-sectional view of the field-effect transistor of Figure 10 shown in a different cross-section. Specific details for implementing the invention

[0028] Hereinafter, embodiments will be described in detail with reference to the attached drawings. The described embodiments are merely illustrative, and various modifications are possible from these embodiments. In the following drawings, the same reference numerals refer to the same components, and the size of each component in the drawings may be exaggerated for clarity and convenience of explanation.

[0029] In the following, terms described as "upper" or "upper" may include not only those directly above in contact, but also those above without contact.

[0030] Terms such as first, second, etc., may be used to describe various components, but are used solely for the purpose of distinguishing one component from another. These terms do not limit the difference in the material or structure of the components.

[0031] A singular expression includes a plural expression unless the context clearly indicates otherwise. Furthermore, when a part is said to "include" a certain component, this means that, unless specifically stated otherwise, it does not exclude other components but may include additional components.

[0032] Additionally, terms such as “...part,” “module,” etc., as described in the specification refer to a unit that processes at least one function or operation, and this may be implemented in hardware or software, or as a combination of hardware and software.

[0033] The use of the term “above” and similar descriptive terms may apply to both the singular and plural forms.

[0034] Unless there is an explicit statement that the steps constituting the method must be performed in the described order, they may be performed in a suitable order. Furthermore, the use of all exemplary terms (e.g., etc.) is merely intended to describe the technical concept in detail and, unless limited by the claims, such terms do not limit the scope of the rights.

[0035] FIG. 1 is a perspective view showing the schematic structure of a field-effect transistor according to an embodiment, FIG. 2 is a cross-sectional view AA of the field-effect transistor of FIG. 1, and FIG. 3 is a cross-sectional view BB of the field-effect transistor of FIG. 1.

[0036] Referring to the drawings, the field-effect transistor (100) includes a plurality of channel layers (121)(122) disposed on a substrate (110), a source electrode (180) and a drain electrode (190) in contact with the channel layers (121)(122), and a gate electrode (160) spaced apart from the channel layers (121)(122).

[0037] The substrate (110) may be an insulating substrate, or a semiconductor substrate having an insulating layer formed on its surface. The semiconductor substrate may include, for example, Si, Ge, SiGe, or III-V group semiconductor materials. The substrate (110) may be, for example, a silicon substrate having silicon oxide formed on its surface, but is not limited thereto.

[0038] On a substrate (110), a source electrode (180) and a drain electrode (190) may be spaced apart along a first direction, and a first channel layer (121) and a second channel layer (122) may be spaced apart along a second direction between the source electrode (180) and the drain electrode (190). The first direction may be the X direction, and the second direction may be the Y direction.

[0039] The gate insulating film (140) is provided in a shape that surrounds each of the first channel layer (121) and the second channel layer (122). The gate electrode (160) is provided in a shape that surrounds the gate insulating film (140).

[0040] As illustrated in FIG. 3, the gate insulating film (140) is in contact with the first channel layer (121) and the second channel layer (122), and may have a shape that surrounds the first channel layer (121) and the second channel layer (122) in a closed path with the first direction (X direction) as the axis. Also, the gate electrode (160) is spaced apart from the first channel layer (121) and the second channel layer (122) with the gate insulating film (140) in between, and may have a shape that surrounds the first channel layer (121) and the second channel layer (122) in a closed path with the first direction (X direction) as the axis.

[0041] The gate insulating film (140) thus insulates the first channel layer (121) and the gate electrode (160) and the second channel layer (122) and the gate electrode (160), and can suppress leakage current. The gate insulating film (140) also extends into the region between the gate electrode (160) and the source electrode (180) and between the gate electrode (160) and the drain electrode (190), thereby insulating the region between the gate electrode (160) and the source electrode (180) and between the gate electrode (160) and the drain electrode (190).

[0042] The contact between the first channel layer (121) and the second channel layer (122), respectively, and the source electrode (180) and drain electrode (190) may have an edge contact form. As shown in FIG. 2, two edges extending in a third direction (Y direction) are provided at both ends of the first channel layer (121), and each of the two edges contacts the source electrode (180) and the drain electrode (190). The second channel layer (122) also contacts the source electrode (180) and the drain electrode (190) in the same form.

[0043] The field-effect transistor (100) according to the embodiment may have a multi-bridge form in which a first channel layer (121) and a second channel layer (122) are stacked spaced apart along a direction away from the substrate (110) and have both ends in contact with the source electrode (180) and the drain electrode (190). This multi-bridge channel form is advantageous for high integration because it can reduce the short channel effect and reduce the area occupied by the source / drain. In addition, it has the advantage of being applicable as a high-speed and high-reliability device because it can maintain a uniform source / drain junction capacitance regardless of the channel position. Although the multi-bridge channel is illustrated with two channel layers, this is exemplary and is not limited thereto, and the field-effect transistor (100) of the embodiment may include a plurality of channel layers stacked in three or more layers.

[0044] The field-effect transistor (100) according to the embodiment may employ a two-dimensional semiconductor material as the material for the first channel layer (121) and the second channel layer (122). The two-dimensional semiconductor material refers to a semiconductor material having a two-dimensional crystal structure and may have a monolayer or multilayer structure. Each layer constituting such a two-dimensional semiconductor material may have an atomic level thickness. The thickness of the first channel layer (121) and the second channel layer (122) may be approximately 10 nm or less. However, it is not limited thereto, and to achieve a short channel length (CL), the thickness of the channel layers (121) (122) may be thinner.

[0045] The field-effect transistor (100) of the embodiment uses a two-dimensional semiconductor material in the first channel layer (121) and the second channel layer (122) to enable a shorter channel length (CL). Here, the channel length (CL) refers to the length of the channel layer (121)(122) between the source electrode (180) and the drain electrode (190), that is, the length in the first direction (X direction) as shown in FIG. 2. The channel length (CL) is related to the thickness of the channel layer (121)(122), and the channel length (CL) can be set to the minimum length determined by the thickness of the channel layer (121)(122). The thickness refers to the thickness in the stacking direction, that is, the thickness in the second direction (Z direction).

[0046] The thickness of the first channel layer (121) and the second channel layer (122) may be 5 nm or less. The thickness of the first channel layer (121) and the second channel layer (122) may be 1 nm or less, and in this case, the channel length (CL) of the first channel layer (121) and the second channel layer (122) may be 3 nm or less.

[0047] Two-dimensional semiconductor materials have excellent electrical properties and can be applied to various devices because they maintain high mobility without their properties changing significantly even when their thickness is reduced to the nanoscale.

[0048] Two-dimensional semiconductor materials may include, for example, at least one of graphene, black phosphorus, and TMD (Transition Metal Dichalcogenide). Graphene is a material in which carbon atoms are bonded two-dimensionally to form a hexagonal honeycomb structure. Compared to silicon (Si), it has high electrical mobility and excellent thermal properties, and has the advantages of being chemically stable and having a large surface area. Black phosphorus is a material in which black phosphorus atoms are bonded two-dimensionally.

[0049] TMDs may include, for example, one transition metal among Mo, W, Nb, V, Ta, Ti, Zr, Hf, Tc, and Re, and one chalcogen element among S, Se, and Te. TMDs can be represented, for example, as MX2, where M represents the transition metal and X represents the chalcogen element. For example, M can be Mo, W, Nb, V, Ta, Ti, Zr, Hf, Tc, Re, etc., and X can be S, Se, Te, etc. Thus, for example, TMDs may include MoS2, MoSe2, MoTe2, WS2, WSe2, WTe2, ZrS2, ZrSe2, HfS2, HfSe2, NbSe2, ReSe2, etc. Alternatively, TMDs may not be represented as MX2. In this case, for example, the TMD may include CuS, which is a compound of the transition metal Cu and the chalcogen element S. Meanwhile, the TMD may be a chalcogenide material containing a non-transition metal. The non-transition metal may include, for example, Ga, In, Sn, Ge, Pb, etc. In this case, the TMD may include a compound of a non-transition metal such as Ga, In, Sn, Ge, Pb, and a chalcogen element such as S, Se, Te. For example, the TMD may include SnSe2, GaS, GaSe, GaTe, GeSe, In2Se3, InSnS2, etc.

[0050] As described above, TMDs may contain one metal element among Mo, W, Nb, V, Ta, Ti, Zr, Hf, Tc, Re, Cu, Ga, In, Sn, Ge, and Pb, and one chalcogen element among S, Se, and Te. However, the materials mentioned above are merely exemplary, and other materials may also be used as TMD materials.

[0051] Two-dimensional semiconductor materials can be doped with p-type dopants or n-type dopants to control mobility. Here, for example, p-type and n-type dopants used in graphene or carbon nanotubes (CNT) can be used as p-type and n-type dopants. The p-type or n-type dopants can be doped by ion implantation or chemical doping.

[0052] The first channel layer (121) and the second channel layer (122) may be made of the same two-dimensional semiconductor material and may have the same thickness. However, they are not limited thereto, and the first channel layer (121) and the second channel layer (122) may include different types of two-dimensional semiconductor materials and may have different thicknesses.

[0053] The source electrode (180) and the drain electrode (190) may comprise a metal material with excellent electrical conductivity. For example, the source electrode (180) and the drain electrode (190) may be made of a metal or an alloy thereof such as magnesium (Mg), aluminum (Al), scandium (Sc), titanium (Ti), vanadium (V), chromium (Cr), manganese (Mn), nickel (Ni), copper (Cu), zinc (Zn), gallium (Ga), zirconium (Zr), niobium (Nb), molybdenum (Mo), lead (Pd), silver (Ag), cadmium (Cd), indium (In), tin (Sn), lanthanum (La), hafnium (Hf), tantalum (Ta), tungsten (W), iridium (Ir), platinum (Pt), gold (Au), bismuth (Bi), etc.

[0054] The gate electrode (160) may include a metal material or a conductive oxide. Here, the metal material may include, for example, at least one selected from the group consisting of Au, Ti, TiN, TaN, W, Mo, WN, Pt, and Ni. The conductive oxide may include, for example, ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), etc. The gate electrode (160) may be made of the same material as the source electrode (180) and the drain electrode (190).

[0055] The gate insulating film (160) may include a high-k dielectric material, which is a material with a high dielectric constant. The gate insulating film (160) may include, for example, aluminum oxide, hafnium oxide, zirconium hafnium oxide, lanthanum oxide, etc. However, it is not limited thereto.

[0056] The gate insulating film (160) may comprise a ferroelectric material. The ferroelectric material has a non-centrosymmetric charge distribution within a unit cell in its crystallized material structure, possessing an electric dipole, that is, spontaneous polarization. Therefore, the ferroelectric material possesses remnant polarization due to the dipole even in the absence of an external electric field. Additionally, the direction of polarization can be switched on a domain-by-domain basis by an external electric field. Such a ferroelectric material may comprise, for example, at least one oxide selected from Hf, Si, Al, Zr, Y, La, Gd, and Sr, but this is exemplary. Additionally, the ferroelectric material may further comprise a dopant as needed.

[0057] When the gate insulating film (160) includes a ferroelectric material, the field-effect transistor (100) can be applied, for example, as a logic device or a memory device. When the gate insulating film (160) includes a ferroelectric material, the subthreshold swing (SS) can be lowered by the negative capacitance effect, so the performance of the field-effect transistor (100) can be improved while reducing its size.

[0058] The gate insulating film (160) may have a multilayer structure including a high-k material and a ferroelectric material. By including a charge trapping layer such as silicon nitride in the gate insulating film (160), the field-effect transistor (100) can operate as a memory transistor having memory characteristics.

[0059] The field effect transistor (100) according to the embodiment employs a two-dimensional semiconductor material as the channel material, thereby reducing the short channel effect and enabling a short channel length.

[0060] The short channel effect refers to performance limitations that occur when the channel length is shortened, such as threshold voltage variation, carrier velocity saturation, and deterioration of the subthreshold characteristics.

[0061] This short channel effect is known to be related to channel thickness. Figure 4 is a graph conceptually showing that the minimum channel length due to the short channel effect varies with channel thickness. As shown in the graph, as the channel thickness decreases, the minimum channel length that can be implemented becomes shorter. Therefore, when attempting to implement ultra-small transistors to increase integration density, the channel length can be effectively reduced by reducing the channel thickness.

[0062] Meanwhile, when reducing the channel thickness using a conventional bulk material, for example, a silicon-based material, if the thickness is reduced to a few nanometers or less, the number of carriers inside the silicon decreases, and consequently, there is a problem in that the electron mobility decreases. In the field-effect transistor (100) of the present embodiment, by forming the channel layer (121)(122) with a two-dimensional semiconductor material, high electron mobility can be maintained even if the thickness of the channel layer (121)(122) is reduced to a few nanometers or less. Therefore, the minimum channel length due to the short channel effect can be formed short, and excellent performance can also be exhibited.

[0063] The graph in FIG. 4 shows the case where silicon material is used in the channel, and the minimum channel length is greater than 10 nm. However, the field-effect transistor (100) of the embodiment uses a two-dimensional semiconductor material in the channel layer (121)(122), so a shorter channel length can be achieved. For example, the channel thickness can be reduced to 1 nm or less, and in this case, the channel length can be reduced to about 3 nm.

[0064] FIGS. 5a to 5e are diagrams schematically illustrating a method for manufacturing a field-effect transistor of FIG. 1.

[0065] Referring to FIG. 5a, first, a support layer (170) and a channel material layer (120) are repeatedly stacked on a substrate (110). As illustrated, the support layer (170) and the channel material layer (120) can be alternately deposited multiple times in that order.

[0066] The support layer (170) supports the channel material layer (120) and is a sacrificial layer that is removed after another structure supporting the channel material layer (120) is formed. The support layer (170) supports the channel material layer (120) and may also be made of a material having an etching ratio different from that of the channel material layer (120) so that it can be selectively removed. The support layer (170) may be formed by a chemical vapor deposition (CVD) method, etc.

[0067] The channel material layer (120) may be made of a two-dimensional semiconductor material and may be formed by, for example, methods such as metal-organic chemical vapor deposition (MOCVD) or atomic layer deposition (ALD). The channel material layer (120) may have a single-layer or multi-layer structure made of a two-dimensional semiconductor material. The thickness of the channel material layer (120) may be 10 nm or less, or 5 nm or less, or 1 nm or less. This thickness may be determined by considering the channel length to be formed.

[0068] The channel material layer (120) may be formed from a two-dimensional semiconductor material doped with a dopant of a predetermined conductivity type. The two-dimensional semiconductor material of the channel material layer (120) may be doped with a p-type dopant or an n-type dopant. Here, for example, the p-type dopant and n-type dopant used in graphene or carbon nanotubes (CNT) may be used as the p-type dopant and n-type dopant. The p-type dopant or n-type dopant may be doped by ion implantation or chemical doping.

[0069] Sources of p-type dopants may include, for example, ionic liquids such as NO2BF4, NOBF4, NO2SbF6, acidic compounds such as HCl, H2PO4, CH3COOH, H2SO4, HNO3, and organic compounds such as dichlorodicyanoquinone (DDQ), oxone, dimyristoylphosphatidylinositol (DMPI), and trifluoromethanesulfoneimide. Alternatively, sources of p-type dopants may include HPtCl4, AuCl3, HAuCl4, AgOTf (silver trifluoromethanesulfonate), AgNO3, H2PdCl6, Pd(OAc)2, Cu(CN)2, etc.

[0070] Sources of n-type dopants may include, for example, a reduction product of a substituted or unsubstituted nicotinamide; a reduction product of a compound which is chemically bound to a substituted or unsubstituted nicotinamide; and a compound comprising at least two pyridinium moieties in which a nitrogen atom of at least one of the pyridinium moieties is reduced. For example, sources of n-type dopants may include NMNH (nicotinamide mononucleotide-H), NADH (nicotinamide adenine dinucleotide-H), NADPH (nicotinamide adenine dinucleotide phosphate-H), or viologen. Alternatively, the source of the n-type dopant may include a polymer such as PEI (polyethylenimine). Alternatively, the n-type dopant may include an alkali metal such as K or Li. Meanwhile, the p-type and n-type dopant materials mentioned above are exemplary, and various other materials may also be used as dopants.

[0071] In this way, after forming a structure in which the support layer (170) and the channel material layer (120) are alternately stacked, the structure can be patterned by a photolithography process.

[0072] Referring to FIG. 5b, a structure having a support layer (170), a first channel layer (121), a support layer (170), a second channel layer (122), and a support layer (170) can be formed by patterning using a photolithography process. Additionally, a source electrode (180) and a drain electrode (190) of a predetermined shape that contact the first channel layer (121) and the second channel layer (122) can be formed.

[0073] Next, the support layer (170) can be removed. To remove the support layer (170), an etching gas that selectively etches only the support layer (170) may be used. The etching process is performed until the first channel layer (121) and the second channel layer (122) are exposed to a predetermined space (H1), and as shown in FIG. 5c, a structure is formed in which the first channel layer (121) and the second channel layer (122) are supported in a bridge form between the source electrode (180) and the drain electrode (190).

[0074] Next, as shown in FIG. 5d, a gate insulating film (140) is formed surrounding the first channel layer (121) and the second channel layer (122). The gate insulating film (140) can be formed by depositing a predetermined insulating material on the surface of the first channel layer (121) and the second channel layer (122) using, for example, Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), Physical Vapor Deposition (PVD), etc. The gate insulating film (140) can be formed in a shape surrounding the second channel layer (121) and the second channel layer (122), for example, as shown in FIG. 3, which is a cross-sectional view in a direction different from FIG. 5d.

[0075] The gate insulating film (140) may also be formed to extend over the surface of the source electrode (180) and the drain electrode (190). The deposition process of the gate insulating film (140) may be carried out to the extent that a predetermined space (H2) remains to form the gate electrode.

[0076] Next, an electrode material is deposited in the space (H2) to form a gate electrode (160) as shown in FIG. 5e. The gate electrode (160) can be formed in a shape that surrounds the gate insulating film (140), for example, as shown in FIG. 3, which is a cross-sectional view in a different direction from FIG. 5e.

[0077] The manufacturing method described in FIGS. 5a to 5e is exemplary and is not limited thereto, and other methods capable of forming the transistor structure illustrated in FIGS. 1 to 3 may be used.

[0078] FIG. 6 is a cross-sectional view showing the schematic structure of a field-effect transistor according to another embodiment, and FIG. 7 is a cross-sectional view showing the field-effect transistor of FIG. 6 from a different cross-section.

[0079] The field-effect transistor (101) includes a first channel layer (125) and a second channel layer (125) stacked vertically spaced apart on a substrate (110), a source electrode (181) and a drain electrode (191) in contact with the first channel layer (125) and the second channel layer (126), and a gate electrode (161) spaced apart from the first channel layer (125) and the second channel layer (125).

[0080] The gate insulating film (141) is provided in a shape that surrounds each of the first channel layer (125) and the second channel layer (125). The gate electrode (161) is provided in a shape that surrounds the gate insulating film (141).

[0081] As illustrated in FIG. 7, the gate insulating film (141) is in contact with the first channel layer (125) and the second channel layer (125), and may have a shape that surrounds the first channel layer (125) and the second channel layer (125) in a closed path with the first direction (X direction) as the axis. Also, the gate electrode (161) is spaced apart from the first channel layer (125) and the second channel layer (125) with the gate insulating film (141) in between, and may have a shape that surrounds the first channel layer (131), the second channel layer (132), and the third channel layer (133) in a closed path with the first direction (X direction) as the axis.

[0082] The field effect transistor (101) of this embodiment differs from the field effect transistor (100) described in FIGS. 1 to 3 in that the channel layer (125)(126) contacts the source electrode (181) and the drain electrode (191).

[0083] The first channel layer (125) includes two contact regions that are in planar contact with the source electrode (181) and the drain electrode (191), and the second channel layer (126) is also in planar contact with the source electrode (181) and the drain electrode (191) in a similar manner.

[0084] As illustrated, the channel length (CL) is defined as the length between the source electrode (181) and the drain electrode (191) in the region of the channel layer (125)(126). The channel length (CL) can be set to a minimum determined by the thickness of the channel layer (125)(126), i.e., the thickness in the stacking direction (Z direction). The thickness of the channel layer (125)(126) may be 10 nm or less, or 5 nm or less, or 1 nm or less. If the thickness of the channel layer (125)(126) is 1 nm or less, the channel length (CL) may be 3 nm or less.

[0085] FIG. 8 is a cross-sectional view showing the schematic structure of a field-effect transistor according to another embodiment, and FIG. 9 is a cross-sectional view showing the field-effect transistor of FIG. 8 from a different cross-section.

[0086] The field-effect transistor (102) includes a first channel layer (131), a second channel layer (132), and a third channel layer (133) stacked vertically spaced apart on a substrate (110), a source electrode (182) and a drain electrode (192) in contact with the first channel layer (131), the second channel layer (132), and the third channel layer (133), and a gate electrode (162) spaced apart from the first channel layer (131), the second channel layer (132), and the third channel layer (133).

[0087] The gate insulating film (142) is provided in a shape that surrounds each of the first channel layer (131), the second channel layer (132), and the third channel layer (133). The gate electrode (162) is provided in a shape that surrounds the gate insulating film (142).

[0088] As illustrated in FIG. 9, the gate insulating film (142) is in contact with the first channel layer (131), the second channel layer (132), and the third channel layer (133), and may have a shape that surrounds each of the first channel layer (131), the second channel layer (132), and the third channel layer (133) in a closed path with the first direction (X direction) as the axis. Also, the gate electrode (162) is spaced apart from the first channel layer (131), the second channel layer (132), and the third channel layer (133) with the gate insulating film (142) in between, and may have a shape that surrounds each of the first channel layer (131), the second channel layer (132), and the third channel layer (133) in a closed path with the first direction (X direction) as the axis.

[0089] In this embodiment, the first channel layer (131), the second channel layer (132), and the third channel layer (133) each have different channel lengths (CL1), (CL2), and (CL3). The first channel layer (131), the second channel layer (132), and the third channel layer (133) can be arranged from the substrate (110) in order of decreasing channel length.

[0090] As described above, the channel length is set to the minimum length that can be implemented according to the thickness of the channel layer, and thus, the first channel layer (131), the second channel layer (132), and the third channel layer (133) may have different thicknesses. For example, the thickness of the first channel layer (131), which has the longest channel length (CL1), may be the thickest, followed by the second channel layer (132) and the third channel layer (133). The thickness of the third channel layer (133), which has the shortest channel length (CL3), may be, for example, 1 nm or less, and the channel length (CL3) may be 3 nm or less. However, this is exemplary, and the thicknesses of the first channel layer (131), the second channel layer (132), and the third channel layer (133) may all be the same.

[0091] Although three channel layers are illustrated in the drawing, they are not limited thereto, and the field-effect transistor (102) may have a plurality of channel layers having two or more different channel lengths.

[0092] FIG. 10 is a cross-sectional view showing the schematic structure of a field-effect transistor according to another embodiment, and FIG. 11 is a cross-sectional view showing the field-effect transistor of FIG. 10 from a different cross-section.

[0093] The field-effect transistor (103) includes a first channel layer (135), a second channel layer (136), and a third channel layer (137) stacked vertically spaced apart on a substrate (110), a source electrode (183) and a drain electrode (193) in contact with the first channel layer (135), the second channel layer (136), and the third channel layer (137), and a gate electrode (163) spaced apart from the first channel layer (135), the second channel layer (136), and the third channel layer (137).

[0094] The gate insulating film (143) is provided in a shape that surrounds each of the first channel layer (135), the second channel layer (136), and the third channel layer (137). The gate electrode (163) is provided in a shape that surrounds the gate insulating film (143).

[0095] The field effect transistor (103) of the present embodiment is similar to the field effect transistor (102) described in FIGS. 8 and 9 in that the first channel layer (135), the second channel layer (136), and the third channel layer (137) have different channel lengths (CL1)(CL2)(CL3), and differs from the field effect transistor (102) in that the width of the third direction (X-direction), which is perpendicular to the channel length direction, is different as shown in FIG. 10.

[0096] The first channel layer (135), the second channel layer (136), and the third channel layer (137) can be arranged from the substrate (110) in order of decreasing width. In FIG. 10, the third-direction widths of the first channel layer (135), the second channel layer (136), and the third channel layer (137) are all shown differently, but this is exemplary and two or more may be different from each other.

[0097] The above-described field-effect transistor (100)(101)(102)(103) can exhibit good electrical performance with a micro-sized structure and can be applied to integrated circuit devices, enabling miniaturization, low power consumption, and high performance.

[0098] The field-effect transistor and its manufacturing method described above have been explained with reference to the embodiments illustrated in the drawings, but this is merely illustrative, and those skilled in the art will understand that various modifications and equivalent alternative embodiments are possible therefrom. Although many details are described in detail in the above description, they should be interpreted as examples of specific embodiments rather than as limiting the scope of the invention. Accordingly, the scope of the invention should not be determined by the described embodiments but by the technical concept described in the claims. Explanation of the symbols

[0099] 100, 101, 102, 103: Field-effect transistors 110: Substrate 120: Channel material layer 121, 122, 125, 126, 131, 132, 133, 135, 136, 137: Channel layer 140, 141, 142, 143: Gate insulating film 101, 161, 162, 163: Gate electrodes 180, 181, 182, 183: Source electrode 190, 191, 192, 193: Drain electrodes 170: Support base

Claims

Claim 1 A field-effect transistor comprising: a substrate; a source electrode and a drain electrode spaced apart from each other along a first direction on the substrate; a plurality of channel layers spaced apart along a second direction away from the substrate, with both ends in contact with the source electrode and the drain electrode, and including a two-dimensional semiconductor material; a gate insulating film surrounding each of the plurality of channel layers; and a gate electrode surrounding the gate insulating film; wherein the two-dimensional semiconductor material includes a transition metal dichalcogenide, the thickness of the channel layer in the second direction is 1 nm or less, the length of the channel layer in the first direction is 3 nm or less, the plurality of channel layers include a first channel layer and a second channel layer having different lengths in the first direction, and the first channel layer and the second channel layer have different lengths in a third direction perpendicular to the first direction and the second direction, respectively. Claim 2 A field-effect transistor according to claim 1, wherein each of the plurality of channel layers includes two edges extended in a third direction perpendicular to the first direction and the second direction, respectively, and the two edges contact the source electrode and the drain electrode, respectively. Claim 3 A field-effect transistor according to claim 1, wherein each of the plurality of channel layers includes two contact regions that are in planar contact with the source electrode and the drain electrode. Claim 4 delete Claim 5 In claim 1, the first channel layer and the second channel layer are arranged from the substrate in an order in which the length of the first direction becomes shorter, forming a field-effect transistor. Claim 6 A field-effect transistor according to claim 1, wherein the first channel layer and the second channel layer have different thicknesses. Claim 7 delete Claim 8 In claim 1, the field effect transistors are arranged such that the first channel layer and the second channel layer are arranged from the substrate in an order in which the length of the third direction becomes shorter. Claim 9 A field-effect transistor according to claim 1, wherein the gate insulating film is in contact with the plurality of channel layers and has a shape that surrounds each of the plurality of channel layers in a closed path with the first direction as an axis. Claim 10 A field-effect transistor according to claim 9, wherein the gate electrode is spaced apart from the plurality of channel layers and has a shape that surrounds each of the plurality of channel layers in a closed path with the first direction as an axis. Claim 11 A field-effect transistor according to claim 9, wherein the gate insulating film has a shape that extends into the region between the gate electrode and the source electrode and between the gate electrode and the drain electrode. Claim 12 delete Claim 13 A field-effect transistor according to claim 1, wherein the transition metal dichalcogenide comprises one metal element selected from the group consisting of Mo, W, Nb, V, Ta, Ti, Zr, Hf, Tc, Re, Cu, Ga, In, Sn, Ge, and Pb, and one chalcogen element selected from the group consisting of S, Se, and Te. Claim 14 A field-effect transistor according to any one of claims 1 to 3, 5, 6, and 8 to 11, wherein a predetermined conductive type dopant is doped into the two-dimensional semiconductor material. Claim 15 A field-effect transistor according to any one of claims 1 to 3, 5, 6, and 8 to 11, wherein the plurality of channel layers comprises the same two-dimensional semiconductor material. Claim 16 A field-effect transistor according to any one of claims 1 to 3, 5, 6, and 8 to 11, wherein the gate insulating film comprises a high-k dielectric material or a ferroelectric material. Claim 17 A field-effect transistor according to any one of claims 1 to 3, 5, 6, and 8 to 11, wherein the length of the first direction of the channel layer is set to a minimum length determined by the thickness of the second direction of the channel layer. Claim 18 delete Claim 19 delete Claim 20 delete

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