Storage system

Abstract

A storage device is provided. The storage device of the present invention includes a memory device comprising a first single-level cell area, a second single-level cell area, and a multi-level cell area, and a storage controller that reads data from the memory device and controls the movement of data between the first single-level cell area, the second single-level cell area, and the multi-level cell area, wherein the data reading speed of the first single-level cell area may be faster than the data reading speed of the second single-level cell area.

Description

Technology Field

[0001] The present invention relates to a storage device including non-volatile memory. Background Technology

[0002] Flash memory stores data by varying the threshold voltage of memory cells and reads data using predetermined read levels. Recently, storage devices containing flash memory, such as Solid State Drives (SSDs) and memory cards, are widely used. This is because flash memory is a non-volatile device with characteristics such as low power consumption and high integration.

[0003] When flash memory stores write data received from a host, it stores it in a memory block of a single-level cell area or a memory block of a multi-level cell area depending on the characteristics of the write data. The problem to be solved

[0004] The technical problem that the present invention aims to solve is to provide a storage controller with improved performance and a method of operation thereof.

[0005] Another technical problem that the present invention aims to solve is to provide a storage device that varies the storage area according to the usage characteristics of the data and a method of operating the same.

[0006] The technical problems of the present invention are not limited to those mentioned above, and other unmentioned technical problems will be clearly understood by those skilled in the art from the description below. means of solving the problem

[0007] A storage device according to some embodiments for achieving the above technical problem includes a memory device comprising a first single-level cell area, a second single-level cell area, and a multi-level cell area, and a storage controller that reads data from the memory device and controls the movement of data between the first single-level cell area, the second single-level cell area, and the multi-level cell area, wherein the data reading speed of the first single-level cell area may be faster than the data reading speed of the second single-level cell area.

[0008] A method of operation of a storage controller according to some embodiments for achieving the above technical problem includes the step of reading data from a single-level cell area of ​​a memory device and the step of moving data to a multi-level cell area of ​​a memory device according to the time order in which the data was written to the single-level cell area, wherein the moving step may retain the data in the single-level cell area without moving it if the number of times the data is read is greater than or equal to a threshold count.

[0009] A storage controller according to some embodiments for achieving the above technical problem includes a control unit that requests to read data stored in any one of a first single-level cell area, a second single-level cell area, and a multi-level cell area included in a memory device, and a movement management unit that changes the storage location within the memory device according to the characteristics of the data, and the data reading speed of the first single-level cell area may be faster than the reading speed of the second single-level cell area.

[0010] Specific details of other embodiments are included in the detailed description and drawings. Brief explanation of the drawing

[0011] FIG. 1 is a simplified block diagram of a host-storage system according to some embodiments. FIG. 2 is a block diagram specifically illustrating the storage controller of FIG. 1 according to some embodiments. FIG. 3 is a block diagram specifically showing the storage device of FIG. 1. FIG. 4 is a block diagram specifically illustrating the storage controller of FIG. 1 according to some embodiments. Figure 5 is a conceptual diagram illustrating the dynamic allocation of the storage device of Figure 3. FIG. 6 is a diagram illustrating the operation of a storage device according to some embodiments. FIG. 7 is a diagram illustrating the operation of a storage device according to some embodiments. FIG. 8 is a flowchart illustrating the operation method of a storage controller according to some embodiments. FIG. 9 is a block diagram showing a storage device according to one embodiment of the present invention. FIG. 10 is an exemplary block diagram showing the memory device of FIG. 1. FIG. 11 is a drawing illustrating a system to which the storage device of FIG. 1 is applied. Specific details for implementing the invention

[0012] Hereinafter, embodiments according to the technical concept of the present invention will be described with reference to the attached drawings.

[0013] FIG. 1 is a simplified block diagram of a storage system according to some embodiments, FIG. 2 is a detailed block diagram of a storage controller of FIG. 1, and

[0014] Referring to FIG. 1, the host-storage system (10) may include a host (100) and a storage device (200). Additionally, the storage device (200) may include a storage controller (210) and a memory device (NVM, 220). Additionally, according to an exemplary embodiment of the present invention, the host (100) may include a host controller (110) and a host memory (120). The host memory (120) may function as a buffer memory for temporarily storing data to be transmitted to the storage device (200) or data transmitted from the storage device (200).

[0015] The storage device (200) may include storage media for storing data in response to a request from the host (100). As an example, the storage device (200) may include at least one of a Solid State Drive (SSD), embedded memory, and removable external memory. If the storage device (200) is an SSD, the storage device (200) may be a device that follows the NVMe (non-volatile memory express) standard. If the storage device (200) is embedded memory or external memory, the storage device (200) may be a device that follows the UFS (universal flash storage) or eMMC (embedded multi-media card) standard. The host (100) and the storage device (200) may each generate and transmit packets according to the adopted standard protocol.

[0016] When the memory device (220) of the storage device (200) includes flash memory, the flash memory may include a 2D NAND memory array or a 3D (or vertical) NAND (VNAND) memory array. As another example, the storage device (200) may include various other types of non-volatile memory. For example, the storage device (200) may include Magnetic RAM (MRAM), Spin-Transfer Torque MRAM, Conductive Bridging RAM (CBRAM), Ferroelectric RAM (FeRAM), Phase RAM (PRAM), Resistive RAM, and various other types of memory.

[0017] According to one embodiment, the host controller (110) and the host memory (120) may be implemented as separate semiconductor chips. Alternatively, in some embodiments, the host controller (110) and the host memory (120) may be integrated on the same semiconductor chip. As an example, the host controller (110) may be any one of a plurality of modules provided in an application processor, and the application processor may be implemented as a System on Chip (SoC). Additionally, the host memory (120) may be an embedded memory provided within the application processor, or a non-volatile memory or memory module placed outside the application processor.

[0018] The host controller (110) can manage the operation of storing data (e.g., written data) of the host memory (120) in the memory device (220) or storing data (e.g., read data) of the memory device (220) in the host memory (120).

[0019] The storage controller (210) may include a host interface (211), a memory interface (212), and a control unit (Control, 213). Additionally, the storage controller (210) may further include a Flash Translation Layer (FTL, 214), a packet manager (215), a buffer memory (216), an ECC (error correction code, 217) engine, an AES (advanced encryption standard, 218) engine, and a movement management unit (300). The storage controller (210) may further include a working memory (not shown) on which the Flash Translation Layer (FTL, 214) is loaded, and data writing and reading operations for the memory device may be controlled by the control unit (213) executing the Flash Translation Layer.

[0020] The host interface (211) can transmit and receive packets with the host (100). The packet transmitted from the host (100) to the host interface (211) may include a command or data to be written to the memory device (220), and the packet transmitted from the host interface (211) to the host (100) may include a response to the command or data read from the memory device (220). The memory interface (212) can transmit data to be written to the memory device (220) to the memory device (220) or receive data read from the memory device (220). This memory interface (212) may be implemented to comply with standard protocols such as Toggle or ONFI.

[0021] The flash conversion layer (214) can perform various functions such as address mapping, wear-leveling, and garbage collection. Address mapping is an operation that converts a logical address received from a host into a physical address used to actually store data within the memory device (220). Wear-leveling is a technique to prevent excessive degradation of a specific block by ensuring that blocks within the memory device (220) are used uniformly, and can be implemented, for example, through firmware technology that balances the erase counts of physical blocks. Garbage collection is a technique to secure usable capacity within the memory device (220) by copying the valid data of a block to a new block and then erasing the existing block.

[0022] The packet manager (215) can generate a packet according to the protocol of the interface agreed upon with the host (100) or parse various information from a packet received from the host (100).

[0023] The buffer memory (216) can temporarily store data to be written to the memory device (220) or data to be read from the memory device (220). The buffer memory (216) may be configured to be located within the storage controller (210), but it may also be placed outside the storage controller (210).

[0024] The ECC engine (217) can perform error detection and correction functions for read data read from the memory device (220). More specifically, the ECC engine (217) can generate parity bits for write data to be written to the memory device (220), and the parity bits thus generated can be stored in the memory device (220) together with the write data. When reading data from the memory device (220), the ECC engine (217) can correct errors in the read data using the parity bits read from the memory device (220) together with the read data, and output the read data with the errors corrected.

[0025] When the storage controller (210) receives data from the memory device (220), the ECC engine (217) performs decoding on the received data to check whether error correction is possible, and if error correction is possible, it checks the number of errors that occurred in the received data and informs the movement management unit (300). If error correction is not possible, the ECC engine (217) informs the control unit (213) that error correction is not possible and can have the data read again from the memory device (220) through the control unit (213). The AES engine (218) can perform at least one of the encryption and decryption operations on the data input to the storage controller (210) using a symmetric-key algorithm.

[0026] The temperature sensor (219) can sense the operating temperature of the memory device (220). That is, it can sense changes in the operating temperature of the memory cell. In some embodiments, the storage controller (210) may not have a temperature sensor and may be implemented as part of the memory device (220).

[0027] The movement management unit (300) can change the storage location of data within the memory device (220) according to the usage characteristics of the data. The movement of the data storage location can be performed during the idle period of operation for the memory device (220). In some embodiments, the idle period may be a period during which background operation of the memory device (220) is performed.

[0028] Referring to FIG. 3, the memory device (220) may include a plurality of regions (401, 402, 403) distinguished according to cell levels. Each region may include a plurality of memory blocks, and each region may be managed in a different way. According to some embodiments, the first region (Region 1, 401) may be managed in a first Single Level cell (SLC) manner, the second region (Region 2, 402) may be managed in a second Single Level cell manner, and the third region (Region 3, 403) may be a region where 2 bits or more of data are stored in a single cell. The third region (403) may also be managed in, for example, a Multi Level Cell (MLC), Triple Level Cell (TLC), or Quad Level Cell (QLC) manner.

[0029] For example, single-level cells (SLC), multi-level cells (MLC), and triple-level cells (TLC) can be distinguished based on the capacity of data that can be stored in a single memory cell. Accordingly, some of the data (metadata) can be programmed in the first area (401) or the second area (402), that is, the single-level cell (SLC) area, and the remaining data excluding the metadata can be programmed in the third area (403).

[0030] For example, the first area (401) and the second area (402) have a faster speed for performing write and read operations compared to the third area (403). Data that changes frequently according to the host's pattern may be stored in the first area (401) or the second area (402), and data that does not change frequently may be stored in the third area (403).

[0031] Additionally, the first area (401) and the second area (402) are both single-level cell areas, but the first area (401) can be configured to perform a reading operation faster than the second area (402). That is, the data reading speed of the first area (401) can be faster than the data reading speed of the second area (402).

[0032] According to some embodiments, the read operation of the first region (401) may be in preset small chunk units, and may be data of a very small capacity, for example, about 4KB or 8KB. According to some embodiments, the read operation of the second region (402) may be performed in multi-page units.

[0033] When the storage controller (210) divides a single-level cell area into at least two areas (e.g., a first area (401), a second area (402)) according to data usage characteristics and performs data reading, the performance of the storage device (200) can be improved by ensuring the reliability of the memory device (220) while performing data reading at a faster speed.

[0034] In this specification, the first region, second region, and third region (401, 402, 403) may be referred to as the first single-level cell region (401), the second single-level cell region (402), and the multi-level cell region (403) according to some embodiments, or as the locality queue region (401), the remaining single-level cell region (402), and the multi-level cell region (403) according to some embodiments. It will be obvious that these designations do not limit the scope of the invention.

[0035] The movement management unit (300) can change the area where data is stored in the memory device (220) according to the usage characteristics of the data for the above-described fast data reading. The usage characteristics of the data may be, for example, at least one of the time the data was written to the memory device (220) (Write time), the last read time (Recent Read time), the number of reads (Read count), and the number of errors (Number of Data Error bit).

[0036] According to some embodiments, the movement management unit (300) may retain data in the first area (401) if the write time is less than the movement threshold time (THw). That is, the movement management unit (300) may move the data in the first area (401) to the second area (402) or the third area (403) if it has been a long time since it was written, and retain the data in the first area (401) if it has not been a long time since it was written.

[0037] According to some embodiments, the movement management unit (300) has, for data in the first area (401), a movement threshold count (TH) of read counts. RCIf the amount is less than ) the data can be moved to the second area (402) or the third area (403). That is, the movement management unit (300) can keep data that is frequently read (has a large number of reads) in the first area (401), and move data that is rarely read from the first area (401) to other areas (402, 403).

[0038] According to some embodiments, the movement management unit (300) may, even if the data is in the second area or the third area (402, 403), have a read count of the movement threshold count (TH RC If it is greater than ) the data can be moved to the first area (401).

[0039] According to some embodiments, the movement management unit (300) may move data from a first area (401) or a second area (402) to a third area (403) in order of the time (Write time) when the data was written to the memory device (220). However, the number of times the data is read is a movement threshold count (TH RC If it exceeds ), since it is currently frequently used data, it can be kept in the first area (401) or the second area (402) without being moved to the third area (403). According to one embodiment, the number of reads among the time written and the number of reads can be considered first.

[0040] According to some embodiments, the number of data reads is a first moving threshold count (TH RC1 If it is greater than ), place it in the first area (401), and the first movement threshold count (TH RC1 Less than ) 2nd moving threshold count (TH RC2 If it is greater than ) it can be placed in the second area (402). At this time, the first movement threshold count may be greater than the second movement threshold count (TH RC1 TH RC2 )

[0041] FIG. 4 is a block diagram specifically illustrating the storage controller of FIG. 1 according to some embodiments, and FIG. 5 is a conceptual diagram for explaining the dynamic allocation of the storage device of FIG. 3. The following description will focus on the differences from FIG. 2, and redundant descriptions will be omitted.

[0042] Referring to FIGS. 4 and 5, the storage controller (210') may further include a block management unit (310). The block management unit (310) may statically or dynamically allocate the sizes of the first area (401), the second area (402), and the third area (403) according to the application method.

[0043] For example, if the size (R1, R2) of the first area (401) or the second area (402) is large, the size (R3) of the third area (403) is reduced accordingly, and the space utilization of the memory device (220) is lowered, thereby reducing the overall data storage capacity. The space utilization may be the ratio of the used area to the total area (R1, R2, R3) of each area.

[0044] Meanwhile, if the size (R1, R2) of the first or second area is small, some of the data stored in the first and second areas (401, 402) is frequently migrated to the third area (403) to secure effective space in the first and second areas (401, 402), which may reduce the performance of the storage device (200). Therefore, the size of each area must be appropriately selected.

[0045] According to some embodiments, the block management unit (310) may dynamically allocate a first area (401), a second area (402), and a third area (403) according to the data access tendency of the storage device (200). Alternatively, according to some embodiments, the block management unit (310) may statically allocate the first area (401), the second area (402), and the third area (403) according to the user settings of the storage device (200).

[0046] FIG. 6 is a diagram illustrating the operation of a storage device according to some embodiments, and FIG. 7 is a diagram illustrating the operation of a storage device according to some embodiments. For convenience of explanation, in FIG. 6 and FIG. 7, the first region is labeled and described as Region 1, the second region as Region 2, and the third region as Region 3.

[0047] Referring to FIG. 6, the memory device (220) can be divided into a single-level cell area including a first area (410) and a second area (402) as described in FIG. 3, and a multi-level cell area corresponding to a third area (403).

[0048] Data can be stored in the single-level cell area in the order of write time, namely SLC1, SLC2, SLC3, SLC4, SLC5. Then, in order of oldest write time, they are moved to the third area (403). For example, SLC1, which has the oldest write time, can be moved to the third area (403).

[0049] However, even if the written time is long, if the data is frequently read by the storage controller (210), the movement management unit (300) may retain the data of the single-level cell in the first area (401) or the second area (402) without moving it to the third area (403). That is, according to some embodiments, the movement management unit (300) may have the number of times the data is read called a movement threshold count (TH RCIf the reading count is greater than ) the data stored in the first region (401) can be maintained by considering the reading count first rather than the written time order. For example, if the data in SLC4 is frequently read, the SLC4 data is maintained in Region 1 even if data continues to arrive after SLC5. According to some embodiments, the movement management unit (300) may move the least recently used data first to the third region (403). For example, the time elapsed from the last read time of the data stored in the first region (401) or the second region (402) is the movement threshold time (TH R If it exceeds ), the movement management unit (300) can move the data from the first area (401) or the second area (402) to the third area (403).

[0050] Referring to FIG. 7, the movement management unit (300) [requires] the number of reads of data stored in the second area (402) to be a movement threshold count (TH RC If it exceeds ), it can be moved back to the first area (401). In the illustrated example, the movement threshold count (TH RC Assuming that ) is 2000, SLC5 reaches the move threshold count with a read count of 2000 and can be moved from the second region (402) to the first region (401). However, SLC6 and TLC have read counts of 100, 1500, and 500, respectively, which are less than the move threshold count, so they can be maintained in their original storage locations (Region 2, Region 3).

[0051] Likewise, although not illustrated, even if the data is stored in the third area (403), the number of reads is the movement threshold count (TH RC If it exceeds ), it can be moved back to the first area (401).

[0052] FIG. 8 is a flowchart illustrating the operation method of a storage controller according to some embodiments.

[0053] Referring to FIG. 8, the storage controller sends a read command to the memory device (S11). When data read from the memory device according to the read command is received, the number of errors is checked after error decoding of the received data (S12).

[0054] According to some embodiments, it is checked whether the storage location of the read data (hereinafter referred to as data) is the first region (Region 1, 401) (S13). If the data is stored in the first region (401), the number of errors in the data is checked (S14).

[0055] If the number of errors in the data exceeds the error threshold (TH ER If it is less than ) (S14), the time at which data was written to the memory device (write time) is checked (S15). The elapsed time from the write time is the move threshold time (TH W If within ) the above data is maintained in the first area (401) (S16).

[0056] If the number of errors in the data exceeds the error threshold (TH ER If the number of reads is greater than or equal to (S14), the read count of the data is checked (S17). Alternatively, even if the data is not stored in the first area (401) (S13, N) but is stored in the second or third area (402, 403), the read count of the data is continuously monitored (S17).

[0057] The number of data reads is the move threshold count (TH RCIf the value exceeds (S17), the data is still in use, so if the data was in the first area, the current storage state is maintained, and if the data was in the second or third area, the data is moved (migrated) to the first area (S18). That is, if the data is frequently read due to frequent current use, the data is maintained in the first area or moved to the first area.

[0058] However, the number of data reads is the move threshold count (TH TC If it is smaller than ), the data is not currently used frequently, so the data is moved to a second area or a third area (S19).

[0059] FIG. 9 is a block diagram illustrating a storage device according to one embodiment of the present invention. Referring to FIG. 9, the storage device (200) may include a memory device (220) and a storage controller (210). The memory device (220) may correspond to one of the non-volatile memory devices (NVM11~NVMmn) that communicate with the storage controller (200) based on one of the plurality of channels (CH1~CHm) of FIG. 10. The storage controller (210) may correspond to the storage controller (200) of FIG. 1.

[0060] The memory device (220) may include first to eighth pins (P11 to P18), a memory interface circuit (221), a control logic circuit (222), and a memory cell array (400).

[0061] The memory interface circuit (221) can receive a chip enable signal (nCE) from the storage controller (210) through the first pin (P11). The memory interface circuit (221) can transmit and receive signals with the storage controller (210) through the second to eighth pins (P12 to P18) according to the chip enable signal (nCE). For example, when the chip enable signal (nCE) is in an enable state (e.g., low level), the memory interface circuit (221) can transmit and receive signals with the storage controller (210) through the second to eighth pins (P12 to P18).

[0062] The memory interface circuit (221) can receive a command latch enable signal (CLE), an address latch enable signal (ALE), and a write enable signal (nWE) from the storage controller (210) through the second to fourth pins (P12 to P14). The memory interface circuit (221) can receive a data signal (DQ) from the storage controller (210) or transmit a data signal (DQ) to the storage controller (210) through the seventh pin (P17). A command (CMD), an address (ADDR), and data (DATA) can be transmitted through the data signal (DQ). For example, the data signal (DQ) can be transmitted through a plurality of data signal lines. In this case, the seventh pin (P17) may include a plurality of pins corresponding to the plurality of data signals.

[0063] The memory interface circuit (221) can obtain a command (CMD) from a data signal (DQ) received during the enable period (e.g., high level state) of a command latch enable signal (CLE) based on the toggle timings of a write enable signal (nWE). The memory interface circuit (221) can obtain an address (ADDR) from a data signal (DQ) received during the enable period (e.g., high level state) of an address latch enable signal (ALE) based on the toggle timings of a write enable signal (nWE).

[0064] In an exemplary embodiment, the write enable signal (nWE) may maintain a static state (e.g., high level or low level) and then toggle between the high level and the low level. For example, the write enable signal (nWE) may toggle during the interval in which a command (CMD) or an address (ADDR) is transmitted. Accordingly, the memory interface circuit (221) may obtain the command (CMD) or the address (ADDR) based on the toggle timings of the write enable signal (nWE).

[0065] The memory interface circuit (221) can receive a read enable signal (nRE) from the storage controller (210) through the fifth pin (P15). The memory interface circuit (221) can receive a data strobe signal (DQS) from the storage controller (210) through the sixth pin (P16) or transmit a data strobe signal (DQS) to the storage controller (210).

[0066] In the data (DATA) output operation of the memory device (220), the memory interface circuit (221) may receive a read enable signal (nRE) that toggles through the fifth pin (P15) before outputting the data (DATA). The memory interface circuit (221) may generate a data strobe signal (DQS) that toggles based on the toggling of the read enable signal (nRE). For example, the memory interface circuit (221) may generate a data strobe signal (DQS) that begins to toggle after a predetermined delay (e.g., tDQSRE) based on the toggling start time of the read enable signal (nRE). The memory interface circuit (221) may transmit a data signal (DQ) containing data (DATA) based on the toggling timing of the data strobe signal (DQS). Accordingly, the data (DATA) can be aligned with the toggle timing of the data strobe signal (DQS) and transmitted to the storage controller (210).

[0067] In the data (DATA) input operation of the memory device (220), when a data signal (DQ) containing data (DATA) is received from the storage controller (210), the memory interface circuit (221) may receive a data strobe signal (DQS) that toggles along with the data (DATA) from the storage controller (210). The memory interface circuit (221) may acquire data (DATA) from the data signal (DQ) based on the toggle timing of the data strobe signal (DQS). For example, the memory interface circuit (221) may acquire data (DATA) by sampling the data signal (DQ) at the rising edge and falling edge of the data strobe signal (DQS).

[0068] The memory interface circuit (221) can transmit a ready / busy output signal (nR / B) to the storage controller (210) via the eighth pin (P18). The memory interface circuit (221) can transmit status information of the memory device (220) to the storage controller (210) via the ready / busy output signal (nR / B). When the memory device (220) is in a busy state (i.e., when internal operations of the memory device (220) are being performed), the memory interface circuit (221) can transmit a ready / busy output signal (nR / B) indicating the busy state to the storage controller (210). When the memory device (220) is in a ready state (i.e., when internal operations of the memory device (220) are not being performed or have been completed), the memory interface circuit (221) can transmit a ready / busy output signal (nR / B) indicating the ready state to the storage controller (210). For example, while the memory device (220) reads data (DATA) from the memory cell array (400) in response to a page read command, the memory interface circuit (221) can transmit a ready / busy output signal (nR / B) indicating a busy state (e.g., low level) to the storage controller (210). For example, while the memory device (220) programs data (DATA) into the memory cell array (400) in response to a program command, the memory interface circuit (221) can transmit a ready / busy output signal (nR / B) indicating a busy state to the storage controller (210).

[0069] The control logic circuit (222) can control various operations of the memory device (220) overall. The control logic circuit (222) can receive a command / address (CMD / ADDR) obtained from the memory interface circuit (221). The control logic circuit (222) can generate control signals to control other components of the memory device (220) according to the received command / address (CMD / ADDR). For example, the control logic circuit (222) can generate various control signals to program data (DATA) into the memory cell array (400) or to read data (DATA) from the memory cell array (400).

[0070] The memory cell array (400) can store data (DATA) obtained from the memory interface circuit (221) under the control of the control logic circuit (222). The memory cell array (400) can output the stored data (DATA) to the memory interface circuit (221) under the control of the control logic circuit (222).

[0071] The memory cell array (400) may include a plurality of memory cells. For example, the plurality of memory cells may be flash memory cells. However, the present invention is not limited thereto, and the memory cells may be RRAM (Resistive Random Access Memory) cells, FRAM (Ferroelectric Random Access Memory) cells, PRAM (Phase Change Random Access Memory) cells, TRAM (Thyristor Random Access Memory) cells, or MRAM (Magnetic Random Access Memory) cells. Hereinafter, embodiments of the present invention will be described with a focus on embodiments in which the memory cells are NAND flash memory cells.

[0072] The storage controller (210) may include first to eighth pins (P21 to P28) and a controller interface circuit (410). The first to eighth pins (P21 to P28) may correspond to the first to eighth pins (P11 to P18) of the memory device (220).

[0073] The controller interface circuit (410) can transmit a chip enable signal (nCE) to the memory device (220) through the first pin (P21). The controller interface circuit (410) can transmit and receive signals to and from the selected memory device (220) through the second to eighth pins (P22~P28) via the chip enable signal (nCE).

[0074] The controller interface circuit (410) can transmit a command latch enable signal (CLE), an address latch enable signal (ALE), and a write enable signal (nWE) to the memory device (220) through the second to fourth pins (P22 to P24). The controller interface circuit (410) can transmit a data signal (DQ) to the memory device (220) or receive a data signal (DQ) from the memory device (220) through the seventh pin (P27).

[0075] The controller interface circuit (410) can transmit a data signal (DQ) containing a command (CMD) or an address (ADDR) to the memory device (220) along with a toggling write enable signal (nWE). The controller interface circuit (410) can transmit a data signal (DQ) containing a command (CMD) to the memory device (220) by transmitting a command latch enable signal (CLE) having an enable state, and can transmit a data signal (DQ) containing an address (ADDR) to the memory device (220) by transmitting an address latch enable signal (ALE) having an enable state.

[0076] The controller interface circuit (410) can transmit a read enable signal (nRE) to the memory device (220) through the fifth pin (P25). The controller interface circuit (410) can receive a data strobe signal (DQS) from the memory device (220) or transmit a data strobe signal (DQS) to the memory device (220) through the sixth pin (P26).

[0077] In the data (DATA) output operation of the memory device (220), the controller interface circuit (410) can generate a toggling read enable signal (nRE) and transmit the read enable signal (nRE) to the memory device (220). For example, the controller interface circuit (410) can generate a read enable signal (nRE) that changes from a fixed state (e.g., high level or low level) to a toggling state before the data (DATA) is output. Accordingly, a toggling data strobe signal (DQS) can be generated in the memory device (220) based on the read enable signal (nRE). The controller interface circuit (410) can receive a data signal (DQ) containing data (DATA) along with the toggling data strobe signal (DQS) from the memory device (220). The controller interface circuit (410) can acquire data (DATA) from the data signal (DQ) based on the toggle timing of the data strobe signal (DQS).

[0078] In the data (DATA) input operation of the memory device (220), the controller interface circuit (410) can generate a toggling data strobe signal (DQS). For example, the controller interface circuit (410) can generate a data strobe signal (DQS) that changes from a fixed state (e.g., high level or low level) to a toggling state before transmitting the data (DATA). Based on the toggling timings of the data strobe signal (DQS), the controller interface circuit (410) can transmit a data signal (DQ) containing the data (DATA) to the memory device (220).

[0079] The controller interface circuit (410) can receive a ready / busy output signal (nR / B) from the memory device (220) through the eighth pin (P28). The controller interface circuit (410) can determine the status information of the memory device (220) based on the ready / busy output signal (nR / B).

[0080] The storage device (200) transmits a read command via the data bus (DQ) and can determine whether the memory device (220) is in a state where it can perform a read operation (Ready) based on the Ready / Busy output signal (nR / B). If the memory device (220) is in a Ready state, the storage device (200) can output data read from the memory cell array via the data bus. That is, the storage device (200) can determine whether the data being read is read from the first area (i.e., the locality queue area) or from the remaining area through the time interval between transmitting the read command and the Ready / Busy output signal (nR / B) and the signal output via the data bus (DQ).

[0081] The storage device (200) can support multiple channels (CH1~CHm), and the memory device (220) and the storage controller (210) can be connected through multiple channels (CH1~CHm). For example, the storage device (200) can be implemented as a storage device such as an SSD (Solid State Drive).

[0082] The memory device (220) may include a plurality of non-volatile memory devices. Each of the non-volatile memory devices may be connected to one of a plurality of channels through a corresponding way. For example, the non-volatile memory devices may be connected to a first channel through ways, and the non-volatile memory devices may be connected to a second channel through ways. In an exemplary embodiment, each of the non-volatile memory devices may be implemented as any memory unit capable of operating according to individual commands from the storage controller (210). For example, each of the non-volatile memory devices may be implemented as a chip or a die, but the present invention is not limited thereto.

[0083] FIG. 10 is an exemplary block diagram illustrating the memory device of FIG. 1. Referring to FIG. 10, the memory device (400) may include a control logic circuit (420), a memory cell array (430), a page buffer section (440), a voltage generator (450), and a row decoder (460). Although not shown in FIG. 12, the memory device (400) may further include a memory interface circuit (410) shown in FIG. 12, and may also further include column logic, a pre-decoder, a temperature sensor, a command decoder, an address decoder, etc.

[0084] The control logic circuit (420) can control various operations within the memory device (400) overall. The control logic circuit (420) can output various control signals in response to a command (CMD) and / or an address (ADDR) from the memory interface circuit (410). For example, the control logic circuit (420) can output a voltage control signal (CTRL_vol), a row address (X-ADDR), and a column address (Y-ADDR).

[0085] The memory cell array (430) may include a plurality of memory blocks (BLK1 to BLKz) (z is a positive integer), and each of the plurality of memory blocks (BLK1 to BLKz) may include a plurality of memory cells. The memory cell array (430) may be connected to a page buffer (440) via bit lines (BL) and may be connected to a row decoder (460) via word lines (WL), string select lines (SSL), and ground select lines (GSL).

[0086] In an exemplary embodiment, the memory cell array (430) may include a three-dimensional memory cell array, and the three-dimensional memory cell array may include a plurality of NAND strings. Each NAND string may include memory cells connected to word lines stacked vertically on a substrate. U.S. Patent Publication No. 7,679,133, U.S. Patent Publication No. 8,553,466, U.S. Patent Publication No. 8,654,587, U.S. Patent Publication No. 8,559,235, and U.S. Patent Application Publication No. 2011 / 0233648 are incorporated herein by reference. In an exemplary embodiment, the memory cell array (430) may include a two-dimensional memory cell array, and the two-dimensional memory cell array may include a plurality of NAND strings arranged along row and column directions.

[0087] The page buffer unit (440) may include a plurality of page buffers (PB1 to PBn) (where n is an integer greater than or equal to 3), and the plurality of page buffers (PB1 to PBn) may each be connected to memory cells through a plurality of bit lines (BL). The page buffer unit (440) may select at least one bit line among the bit lines (BL) in response to a column address (Y-ADDR). The page buffer unit (440) may operate as a write driver or a sense amplifier depending on the operation mode. For example, during a program operation, the page buffer unit (440) may apply a bit line voltage corresponding to the data to be programmed with the selected bit line. During a read operation, the page buffer unit (440) may detect the current or voltage of the selected bit line to detect the data stored in the memory cell.

[0088] The voltage generator (450) can generate various types of voltages to perform program, read, and erase operations based on the voltage control signal (CTRL_vol). For example, the voltage generator (450) can generate a program voltage, a read voltage, a program verification voltage, an erase voltage, etc. as a word line voltage (VWL).

[0089] The row decoder (460) can select one of a plurality of word lines (WL) and one of a plurality of string select lines (SSL) in response to a row address (X-ADDR). For example, during a program operation, the row decoder (460) can apply a program voltage and a program verification voltage to the selected word line, and during a read operation, it can apply a read voltage to the selected word line.

[0090] FIG. 11 is a drawing illustrating a system to which the storage device of FIG. 1 is applied.

[0091] The system (1000) of FIG. 11 may basically be a mobile system such as a portable communication terminal (mobile phone), a smartphone, a tablet PC (tablet personal computer), a wearable device, a healthcare device, or an IoT (Internet of Things) device. However, the system (1000) of FIG. 11 is not necessarily limited to a mobile system and may be a personal computer, a laptop computer, a server, a media player, or an automotive device such as a navigation system.

[0092] Referring to FIG. 11, the system (1000) may include a main processor (1100), memory (1200a, 1200b) and storage devices (1300a, 1300b), and additionally may include one or more of an image capturing device (1410), a user input device (1420), a sensor (1430), a communication device (1440), a display (1450), a speaker (1460), a power supplying device (1470), and a connecting interface (1480).

[0093] The main processor (1100) can control the overall operation of the system (1000), more specifically, the operation of other components that make up the system (1000). Such a main processor (1100) can be implemented as a general-purpose processor, a dedicated processor, or an application processor.

[0094] The main processor (1100) may include one or more control unit cores (1110) and may further include a controller (1120) for controlling memory (1200a, 1200b) and / or storage devices (1300a, 1300b). According to an embodiment, the main processor (1100) may further include an accelerator block (1130), which is a dedicated circuit for high-speed data computation, such as artificial intelligence (AI) data computation. Such an accelerator block (1130) may include a Graphics Processing Unit (GPU), a Neural Processing Unit (NPU), and / or a Data Processing Unit (DPU), and may be implemented as a separate chip physically independent from other components of the main processor (1100).

[0095] The memory (1200a, 1200b) can be used as the main memory of the system (1000) and may include volatile memory such as SRAM and / or DRAM, but may also include non-volatile memory such as flash memory, PRAM and / or RRAM. The memory (1200a, 1200b) may also be implemented within the same package as the main processor (1100).

[0096] The storage device (1300a, 1300b) can function as a non-volatile storage device that stores data regardless of whether power is supplied, and can have a relatively large storage capacity compared to the memory (1200a, 1200b). The storage device (1300a, 1300b) may include a storage controller (1310a, 1310b) and a non-volatile memory (NVM) storage (1320a, 1320b) that stores data under the control of the storage controller (1310a, 1310b). The non-volatile storage (1320a, 1320b) may include V-NAND flash memory with a 2D (2-dimensional) or 3D (3-dimensional) structure, but may also include other types of non-volatile memory such as PRAM and / or RRAM.

[0097] The storage device (1300a, 1300b) may be included in the system (1000) in a state physically separated from the main processor (1100), or it may be implemented within the same package as the main processor (1100). Additionally, the storage device (1300a, 1300b) may have a form such as a memory card and may be detachably coupled to other components of the system (1000) through an interface such as the connection interface (1480) described later. Such storage device (1300a, 1300b) may be a device to which standard protocols such as UFS (universal flash storage) are applied, but it is not necessarily limited thereto.

[0098] The shooting device (1410) can take still images or video and may be a camera, camcorder and / or webcam, etc.

[0099] The user input device (1420) can receive various types of data input from a user of the system (1000) and may be a touch pad, a keypad, a keyboard, a mouse and / or a microphone.

[0100] The sensor (1430) can detect various types of physical quantities that may be obtained from outside the system (1000) and convert the detected physical quantities into electrical signals. Such a sensor (1430) may be a temperature sensor, a pressure sensor, an illuminance sensor, a position sensor, an acceleration sensor, a biosensor and / or a gyroscope, etc.

[0101] The communication device (1440) can transmit and receive signals between other devices outside the system (1000) according to various communication protocols. Such a communication device (1440) may be implemented including an antenna, a transceiver and / or a modem.

[0102] The display (1450) and speaker (1460) can function as output devices that output visual information and auditory information, respectively, to the user of the system (1000).

[0103] The power supply unit (1470) can appropriately convert power supplied from a battery (not shown) and / or an external power source built into the system (1000) and supply it to each component of the system (1000).

[0104] The connection interface (1480) can provide a connection between the system (1000) and an external device connected to the system (1000) that can exchange data with the system (1000). The connection interface (1480) can be implemented in various interface methods such as ATA (Advanced Technology Attachment), SATA (Serial ATA), e-SATA (external SATA), SCSI (Small Computer Small Interface), SAS (Serial Attached SCSI), PCI (Peripheral Component Interconnection), PCIe (PCI express), NVMe (NVM express), IEEE 1394, USB (universal serial bus), SD (secure digital) card, MMC (multi-media card), eMMC (embedded multi-media card), UFS (Universal Flash Storage), eUFS (embedded Universal Flash Storage), CF (compact flash) card interface, etc.

[0105] Although embodiments of the present invention have been described above with reference to the attached drawings, the present invention is not limited to the above embodiments and can be manufactured in various different forms, and those skilled in the art will understand that the present invention can be implemented in other specific forms without changing the technical concept or essential features of the present invention. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. Explanation of the symbols

[0106] 100 : Host 200 : Storage device 210: Storage controller 220, 400: Memory device 300: Movement Management Department 310: Block Management Department 401: 1st single-level cell area, locality queue area 402: The remaining area excluding the second single-level cell area and the locality queue area 403: Multi-level cell area

Claims

Claim 1 A storage device comprising: a first single-level cell area, a second single-level cell area, and a multi-level cell area; and a storage controller that reads data from the memory device and controls the movement of data between the first single-level cell area, the second single-level cell area, and the multi-level cell area, wherein the data reading speed of the first single-level cell area is faster than the data reading speed of the second single-level cell area, and the storage controller controls the movement of data between the first single-level cell area, the second single-level cell area, and the multi-level cell area according to the characteristics of the data, and the characteristics of the data include at least one of a write time programmed into the memory device for the data and the number of reads of the data. Claim 2 delete Claim 3 delete Claim 4 A storage device according to claim 1, wherein the first single-level cell area stores data in which the number of errors in the data is less than an error threshold and the write time is less than a movement threshold time. Claim 5 A storage device according to claim 1, wherein the second single-level cell area or the multi-level cell area stores data in which the number of errors in the data is greater than or equal to an error threshold and the number of reads is less than a move threshold count. Claim 6 A storage device according to claim 1, wherein the storage controller moves to the first single-level cell area when the data is data stored in the second single-level cell area or the multi-level cell area, and maintains the storage state when the data is data in the first single-level cell area, for data where the number of reads is greater than or equal to the movement threshold count. Claim 7 A storage device according to claim 1, wherein the storage controller further comprises a block management unit that dynamically adjusts the size of each of the first single-level cell area, the second single-level cell area, and the multi-level cell area in the memory device according to the data access tendency of the storage controller. Claim 8 A method of operation of a storage controller comprising: a step of reading data from a single-level cell area of ​​a memory device; and a step of moving the data to a multi-level cell area of ​​the memory device according to the time order in which the data was written to the single-level cell area, wherein the moving step is to retain the data in the single-level cell area without moving it if the number of times the data is read is greater than or equal to a threshold count. Claim 9 A method of operation of a storage controller according to claim 8, wherein the single-level cell area further includes a locality queue area that maintains the storage location of the data according to the data characteristics of the data. Claim 10 A method of operation of a storage controller according to claim 9, wherein if the last read time of data stored in the locality queue exceeds a threshold time, the data is moved out of the locality queue area. Claim 11 A method of operation of a storage controller according to claim 9, wherein if the number of reads of data stored in the multi-level cell area exceeds the threshold count, the data is moved from the multi-level cell area to the locality queue area. Claim 12 A method of operation of a storage controller according to claim 9, wherein if the number of reads of data stored in the remaining area excluding the locality queue in the single-level cell area exceeds the threshold count, the data is moved back from the remaining area to the locality queue area. Claim 13 A method of operation of a storage controller according to claim 9, wherein the storage controller dynamically adjusts the size of the locality queue area, the area excluding the locality queue in the single-level cell area, and the multi-level cell area according to the data access tendency. Claim 14 A storage controller comprising: a control unit requesting to read data stored in any one of a first single-level cell area, a second single-level cell area, and a multi-level cell area included in a memory device; and a movement management unit changing a storage location within the memory device according to the characteristics of the data, wherein the data reading speed of the first single-level cell area is faster than the reading speed of the second single-level cell area, and the characteristics of the data include one of the time the data was written, the last read time, the number of reads, and the number of errors. Claim 15 In claim 14, the storage controller further includes an error correction code (ECC) engine that corrects errors in the data received from the memory device and checks the number of errors, and the movement management unit changes the storage location of the data based on the number of errors. Claim 16 delete Claim 17 In paragraph 14, the above-mentioned movement management unit moves the data from the first single-level cell area to the second single-level cell area or the multi-level cell area if the number of reads is less than the movement threshold count, even if the data is in the first single-level cell area, in a storage controller. Claim 18 In paragraph 14, the control unit is a storage controller that requests the memory device to read the data again when the data cannot be error-corrected. Claim 19 A storage controller according to claim 14, wherein the storage location of the data is the first single-level cell area, and if the time at which the data is written is less than the movement threshold time, the storage location of the data is maintained in the first single-level cell area. Claim 20 In paragraph 14, the above-mentioned movement management unit is a storage controller that moves the data to the first single-level cell area even if the storage location of the data is the second single-level cell area or the multi-level cell area, if the number of reads for the data is greater than or equal to the movement threshold counter.

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