Multi-stage selective patterning for stacked device fabrication

Abstract

A microfabrication method comprises the steps of: providing a substrate having an existing pattern of features formed within a first layer; depositing a selective adhesive on the substrate (wherein the selective adhesive is attached to the features and includes a solubility-converting agent); depositing a first resist on the substrate; activating the solubility-converting agent so that a portion of the first resist on the features is dissolved in a first developer; developing the first resist using a first developer to form a relief pattern having an opening that exposes the features of the existing layer; growing a selective growth material on the features and within the opening of the relief pattern to provide a self-aligned selective growth feature; removing the first resist; depositing a fill layer on the substrate; and repeating the steps a predetermined number of times to provide a stacked device having a predetermined number of levels.

Description

Background Technology

[0001] Microfabrication of semiconductor devices involves various steps such as film deposition, pattern formation, and pattern transfer. Materials and films are deposited onto a substrate via spin coating, vapor deposition, and other deposition processes. Pattern formation is typically performed by exposing a photosensitive film, known as photoresist, to a chemical radiation pattern and then developing the photoresist to form a relief pattern. The relief pattern then acts as an etching mask to cover the portions of the substrate that will not be etched when one or more etching processes are applied to the substrate. After the first etching, processing may continue through additional steps such as material deposition, etching, annealing, and photolithography, with various steps repeated until a transistor or integrated circuit is manufactured.

[0002] There are several steps in semiconductor processing where important features must be accurately aligned to the base layer. Generally, different processes can be aligned by aligning different mask layers, correcting their positions, and then etching the layers in place.

[0003] The content of this invention is provided to introduce a selection of concepts further described in the detailed description below. It is not intended to identify the principal or essential features of the claimed subject matter, nor is it intended to help limit the scope of the claimed subject matter.

[0004] In one embodiment, the embodiment disclosed herein relates to a microfabrication method comprising the steps of: (a) providing a substrate having a pre-existing pattern (wherein the upper surface of the substrate has a feature that is not covered and a pre-existing pattern is formed within the first layer such that the first layer is not covered), (b) depositing a selective adhesive on the substrate (wherein the selective adhesive is attached to the feature and comprises a solubility-converting agent), and (c) depositing a first resist on the substrate. Then, the method comprises: (d) activating a solubility-converting agent such that a portion of the first resist on the feature becomes soluble in the first developer, or a portion of the first resist on the first layer between the features becomes insoluble in the first developer; (e) developing the first resist using the first developer to form a relief pattern including an opening (wherein the opening exposes a feature of the existing layer); (f) performing a selective growth process to grow a selective growth material on the feature and within the opening of the relief pattern to provide a self-aligned selective growth feature; (g) removing the first resist; (h) depositing a filling layer on a substrate to provide a filled substrate; and (i) repeating steps (b) through (h) a predetermined number of times to provide a stacked device having a predetermined number of levels.

[0005] In another aspect, an embodiment of the present disclosure relates to a microfabrication method comprising the steps of: receiving a substrate having a feature formed in a first layer such that the upper surface of the substrate has an uncovered feature and an uncovered first layer; depositing a first solubility-converter on the substrate (wherein the first solubility-converter is selected to adhere to the uncovered surface of the feature without the first solubility-converter adhering to the uncovered surface of the first layer); and depositing a second solubility-converter on the substrate (wherein the second solubility-converter is selected to adhere to the uncovered surface of the first layer without the second solubility-converter adhering to the uncovered surface of the feature). Then, the method comprises the steps of: depositing a first photoresist on a substrate; activating a first solubility-converter sufficient to make the first photoresist region on the feature soluble in a specific developer; activating a second solubility-converter so that the second solubility-converter increases the insolubility of the first photoresist on the first layer; developing the first photoresist to create a relief pattern defining an opening that does not cover the feature; and performing a selective growth process to grow a selectively deposited material on the feature and within the defined opening of the relief pattern to create a self-aligned selectively deposited feature.

[0006] Other aspects and advantages of the claimed subject matter will become apparent from the following description and the appended claims. Brief explanation of the drawing

[0007] FIG. 1 is a block flowchart of a method according to one or more embodiments of the present disclosure. FIGS. 2a to 2i are schematic diagrams of a coated substrate at each point of a method according to one or more embodiments of the present disclosure. FIGS. 3a to 3c are schematic diagrams of a substrate for a device according to one or more embodiments of the present disclosure. FIGS. 4a to 4d are schematic diagrams of a coated substrate for constructing an MRAM at each point of a method according to one or more embodiments of the present disclosure. FIGS. 5a to 5c are schematic diagrams of an incomplete CMOS device, a DRAM device, and a 3DNAND device according to one or more embodiments of the present disclosure. Specific details for implementing the invention

[0008] Many advanced semiconductor devices are composed of various three-dimensional (3D) structures on a substrate. For example, 3D NAND memory, dynamic random-access memory (DRAM), and magnetic random-access memory (MRAM) are built as large 3D arrays of vertical features, which are expensive to manufacture using conventional etching-based processes because they are difficult to scale and limited by deep etching capabilities.

[0009] The present disclosure generally relates to a multilayer processing method comprising multiple iterations of self-aligned selective growth on a semiconductor substrate. In this disclosure, the terms “semiconductor substrate” and “substrate” are used interchangeably and may be any semiconductor material, including but not limited to semiconductor wafers, semiconductor material layers, and combinations thereof. In one or more embodiments, the method provides a multilayer device by combining multilayer processing, selective growth, and self-alignment. Since the stack can be provided in a single lithography / patterning step, this method is simpler to implement than conventional etching-based processes. Accordingly, the method disclosed herein allows for both sizing and reachable dimensions that are not achievable with current technology.

[0010] One or more embodiments of the method relying on both chemical processes and diffusion characteristics provide a unique ability to add control features to the input chemistry itself and a process for measuring such chemistry.

[0011] In the microfabrication of devices and nodes, it is desirable for certain features to be fully aligned using selective processing. In selective deposition processes, it is desirable to grow a pre-selected material without defects in a pre-defined location and direction. However, current-directed growth techniques, such as selective atomic layer deposition, suffer from significant drawbacks. Furthermore, these techniques are often insufficient for use in more complex cases, such as selected growth regions extending to the sidewalls of spacers. Current self-aligned growth often has high failure rates, and even small amounts of unintended deposition can cause problems in semiconductor devices.

[0012] As understood by those skilled in the art, the method disclosed herein may be used to provide various self-aligned features, such as, for example, universal self-aligned, fully self-aligned, selective self-aligned, and feature self-aligned. Accordingly, the specific embodiments disclosed herein are not intended to limit the scope of the disclosure. In one or more specific embodiments, a method for universal self-aligned vias is provided.

[0013] A method (100) for multilayer selective patterning according to the present disclosure is illustrated in FIG. 1 and is discussed with reference thereto. Initially, an existing pattern including features within a base layer is provided on a substrate in block (102). In block (104), the substrate, or a portion thereof, is coated with a selective adhesive. The selective adhesive may include a solubility-converting agent. Then, in block (106), the substrate is coated with a first resist. In block (108), the solubility-converting agent may be activated to provide an area of ​​the first resist that is soluble in a first developer. Then, the first resist is developed in block (110) to provide a gap in the first resist that exposes features of the existing pattern on the substrate. In block (112), selective growth on the features is performed. Then, in block (116), the first resist is removed so that only the selectively grown features remain. Then, the selectively grown features are coated in block (118). In some embodiments, prior to coating, the selective growth feature may be treated by a freezing process or the like. In some embodiments, after coating the selective growth feature, the substrate is etched to remove residual coating, such as excess resist. Finally, a fill layer is deposited on the substrate to fill the substrate (120), and the steps indicated in blocks (104 to 120) are repeated to provide a multi-level patterned substrate.

[0014] Schematic diagrams of substrates coated at various points during the method described above are illustrated in FIGS. 2a through 2i. As used herein, "coated substrate" refers to a substrate coated with one or more layers, such as a first resist layer and a second resist layer. FIG. 2a illustrates a substrate containing an existing pattern. FIG. 2b illustrates a substrate containing an overcoat containing a selective adhesive. FIG. 2c illustrates a substrate containing a selective adhesive overcoat laminated with a first resist. FIG. 2d shows a coated substrate after the first resist has been developed so that features of the substrate are exposed. FIG. 2e illustrates a substrate containing a selective growth layer over the first resist and features of the substrate. In FIG. 2f, the first resist is removed, leaving only the selective growth layer. FIG. 2g shows the selective growth feature after processing and coating. FIG. 2h illustrates a substrate including the selective growth feature, the coating, and a filled layer deposited on the substrate. Finally, FIG. 2i illustrates a multi-level stacked device provided by repeating the method steps shown in blocks (104 to 120) three times. The method of FIG. 1 and the coated substrates shown in FIG. 2a to 2i will be described in detail below.

[0015] In FIG. 1, in block (102), a conventional pattern is provided on a substrate that includes an integrated circuit. The conventional pattern may be a large array of hexagonal or linear arrays. For example, the conventional pattern may correspond to the core of a dynamic random access memory (DRAM) device, a magnetoresistive random access memory (MRAM) device, a 3D NAND device, or other 3D devices known in the art. A DRAM device may store data bits in a memory cell comprising a capacitor for storing bits and a transistor for reading and writing bits. An MRAM device may store data bits in a memory cell comprising two ferromagnetic plates forming a magnetic tunnel junction. A 3D NAND device may store memory bits using NOT-AND logic gates. This list of devices is not intended to be limiting, and in practice, the conventional pattern may correspond to any type of integrated circuit. FIGs. 3a through 3c show top views of a conventional pattern suitable for a DRAM device, an MRAM device, and a 3D NAND device, respectively. For example, in an embodiment in which a DRAM device is constructed, the substrate may have a conventional pattern comprising an array of DRAM cells (301) designed such that two adjacent DRAM cells in a row share a single beltline (302) contact to reduce the area of ​​each. Meanwhile, in an embodiment in which an MRAM device is constructed, the substrate (303) may have a basic pattern comprising an array of MRAM cells (304) as shown in FIG. 3b. In particular, the substrate used for manufacturing the MRAM device may be smaller than the substrate used for manufacturing the DRAM device. Alternatively, in an embodiment in which a 3D NAND device is constructed, a terabit cell array transistor (TCAT) (305) may be used as a substrate as shown in FIG. 3c. It will be understood that the substrates shown in FIG. 3a through 3c are exemplary, and that selecting a suitable substrate for constructing the 3D device is within the skill of those skilled in the art.

[0016] FIG. 2a illustrates a cross-sectional view of a substrate (200) including an existing pattern corresponding to a core region of an MRAM device. In FIG. 2a, the existing pattern includes an existing feature (202) formed on a base layer (201). The existing feature (202) may include vias that interconnect multiple layers of the MRAM. The existing feature (202) may also include an N-type region, the substrate (200) may include a P-type substrate, and the existing pattern may include one or more N-type metal oxide semiconductor (NMOS) devices. The existing feature (202) may also include a P-type region, the substrate (200) may include an N-type substrate, and the existing pattern may include one or more P-type metal oxide semiconductor (PMOS) devices. The existing feature (202) may include both NMOS and PMOS devices, which are known as complementary metal oxide semiconductor (CMOS) devices. It will be understood that the existing pattern of the existing feature (202) may include alternative suitable combinations of vias, NMOS devices, PMOS, and CMOS devices without departing from the spirit and scope of the present disclosure. One or more embodiments having NMOS devices, PMOS devices, CMOS devices, and vias will be discussed in more detail below in connection with 5a to 5c. The base layer may be a suitable substrate known in the art. In one or more embodiments, the features formed on the base layer are arranged in a large array. For example, in a square base layer, the features may be arranged at uniform intervals in a 4×4 array, a 5×5 array, a 6×6 array, etc. The shape and size of the array are not particularly limited and may be any shape and size suitable for use in a photolithography track.

[0017] The feature may be manufactured from any material commonly used in the art. In one or more embodiments, the feature comprises a metal, a semimetal, or other conductive structure. As used herein, the term metal includes alloys, stacks, and other combinations of multiple metals. For example, a metal interconnect line may include a barrier layer, a stack of various metals or alloys, etc. Suitable metals and semimetals that may constitute the feature include, but are not limited to, silicon, polysilicon, copper, cobalt, and tungsten. In one or more embodiments, the base layer is an interlayer dielectric. Suitable interlayer dielectrics may include silicon oxide (e.g., silicon dioxide (SiO2)), doped silicon oxide, fluorinated silicon oxide, carbon-doped silicon oxide, various low-k dielectric materials known in the art, and combinations thereof. The existing pattern may be a final feature or an intermediate feature during the patterning process. The substrate may be planarized so that the existing pattern of the feature within the base layer is exposed and accessible. In one or more embodiments, the substrate comprises an etching stop layer or a graphene coating on a metal line.

[0018] Then, in block (104), an optional adhesive is coated onto the substrate, or a part thereof. FIG. 2b illustrates a substrate (200) having an existing pattern having a base layer (201) having existing features (202) coated with an optional adhesive (203). The optional adhesive may be coated onto the substrate by any coating method known in the art. Suitable coating methods include, but are not limited to, vapor phase deposition, liquid phase deposition, vapor deposition, spin-on coating, and Langmuir-Blodgett monolayer coating. The optional adhesive may form a layer thickness corresponding to one molecule known as a self-assembled monolayer that bonds to the surface in an aligned manner due to physical or chemical forces during the deposition process.

[0019] The selective adhesive may be preferentially attached to one material of the existing pattern. In one or more embodiments, the selective adhesive is attached to features of the existing pattern of the substrate. In these embodiments, the selective adhesive may be attached to features of the pattern at a ratio of features to the first layer greater than 1:1. Without limitation, as an example, the selective adhesive may be attached to features of the pattern at a ratio of features to the first layer of about 2:1 to about 10:1 or more.

[0020] In one or more embodiments, the selective adhesive is a chemical functional group that may be further functionalized. Exemplary selective adhesives include, but are not limited to, alcohols, silanols, amines, phosphines, phosphonic acids, and carboxylic acids. A specific selective adhesive coated on an existing pattern may vary depending on the specific chemical used in other components of the method (100). For example, various phosphonic acids and esters may react selectively or at least preferentially with natural or oxidized metal surfaces to form metal phosphonates that are preferentially or even selectively strongly bonded on the surface of a dielectric material (e.g., silicon oxide), and thus can be used as a selective adhesive for features rather than a base layer. A specific example of a suitable phosphonic acid is octadecylphosphonic acid (ODPA). While such surface coatings generally tend to be stable in many organic solvents, they can be removed using weak aqueous acid and base solutions. Phosphines (e.g., organophosphines) may also be used selectively. Other common acids, such as sulfonic acid, sulfinic acid, and carboxylic acid, can also be used selectively.

[0021] Another example of a reaction that is selective or at least preferential toward metal materials compared to dielectric materials, organic polymer materials, or other materials is various metal corrosion inhibitors, such as those used to protect interconnected structures during chemical mechanical polishing. Specific examples include benzotriazoles, other triazole functional groups, other suitable heterocyclic groups (e.g., heterocyclic-based corrosion inhibitors), and other metal corrosion inhibitors known in the art. In addition to triazole groups, other functional groups may be used to provide the desired attraction or reactivity toward the metal. Various metal chelating agents are also potentially suitable. Various amines (e.g., organic amines) are also potentially suitable.

[0022] Another example of a reaction that is selective or at least preferential to metal materials compared to dielectric materials, organic polymer materials, or other materials is various thiols. As another example, 1,2,4-triazoles or similar aromatic heterocyclic compounds can be used to react selectively with metals compared to dielectrics and other specific materials. The selective adhesive may also contain functional groups capable of reacting with the functional groups of the polymer to bind the polymer to the surface. Various other metal-poisoning compounds known in the art may also be potentially used. These are merely a few exemplary examples, and it should be understood that other examples will be obvious to those skilled in the art and may benefit from the present disclosure. The selective adhesive may also comprise a polymer containing any of the aforementioned functional groups capable of selective attachment, wherein the polymer has functional groups along the main chain or as terminal groups, forming a layer of polymer chains attached to the target material.

[0023] In one or more embodiments, the selective adhesive may include a solubility-converter. The composition of the solubility-converter may vary depending on the selective adhesive. As understood by those skilled in the art, any suitable solubility-converter may be included in the selective adhesive provided that the two materials do not react with each other. Generally, the solubility-converter may be any chemical that is activated by light or heat. For example, in some embodiments, the solubility-converter includes an acid or an acid-generating agent. In the case of a TAG, the acid or generated acid must be sufficiently heated to increase the solubility of the first resist polymer in the specific developer to be applied by cleaving the bonds of the acid-degradable groups of the polymer in the surface area of ​​the first resist pattern. The acid or TAG is typically present in the composition in an amount of about 0.01 to 20 weight percent based on the total solid content of the trimming composition.

[0024] Preferred acids are organic acids including non-aromatic and aromatic acids, each of which may optionally have fluorine substitution. Suitable organic acids include, for example: carboxylic acids such as alkanes including formic acid, acetic acid, propionic acid, butyric acid, dichloroacetic acid, trichloroacetic acid, perfluoroacetic acid, perfluorooctanoic acid, oxalic acid, malonic acid, and succinic acid; hydroxyalkanes such as citric acid; aromatic carboxylic acids such as benzoic acid, fluorobenzoic acid, hydroxybenzoic acid, and naphthoic acid; organic phosphoric acids such as dimethyl phosphate and dimethylphosphinic acid; and optionally, sulfonic acids such as fluorinated alkylsulfonic acids including methanesulfonic acid, trifluoromethanesulfonic acid, ethanesulfonic acid, 1-butanesulfonic acid, 1-perfluorobutanesulfonic acid, 1,1,2,2-tetrafluorobutane-1-sulfonic acid, 1,1,2,2-tetrafluoro-4-hydroxybutane-1-sulfonic acid, 1-pentanesulfonic acid, 1-hexanesulfonic acid, and 1-heptanesulfonic acid are included.

[0025] Exemplary fluorine-free aromatic acids include aromatic acids of general formula I:

[0026] [General Formula I]

[0027]

[0028] (wherein: R1 independently or optionally represents a substituted or unsubstituted C1-C20 alkyl group, a substituted or unsubstituted C5-C20 aryl group, or a combination thereof containing one or more groups selected from carbonyl, carbonyloxy, sulfonamido, ether, thioether, substituted or unsubstituted alkylene groups, or combinations thereof; Z1 independently represents a group selected from carboxyl, hydroxy, nitro, cyano, C1 to C5 alkoxy, formyl, and sulfonic acid; a and b are independently integers from 0 to 5; and a+b is 5 or less).

[0029] Exemplary aromatic acids can have general formula II:

[0030] [General Formula II]

[0031]

[0032] (wherein: R2 and R3 each independently represent a substituted or unsubstituted C1-C20 alkyl group, a substituted or unsubstituted C5-C16 aryl group, or a combination thereof, containing one or more groups selected from carbonyl, carbonyloxy, sulfonamido, ether, thioether, substituted or unsubstituted alkylene groups, or combinations thereof; Z2 and Z3 each independently represent a group selected from carboxyl, hydroxy, nitro, cyano, C1 to C5 alkoxy, formyl, and sulfonic acid; c and d are independently integers from 0 to 4; c+d is 4 or less; e and f are independently integers from 0 to 3; and e+f is 3 or less).

[0033] Additional aromatic acids that may be included in the solubility-converting agent include those of the following general formulas III or IV:

[0034] [General Formula III]

[0035]

[0036] (wherein: R4, R5 and R6 each independently represent a substituted or unsubstituted C1-C20 alkyl group, a substituted or unsubstituted C5-C12 aryl group, or a combination thereof, containing one or more groups selected from carbonyl, carbonyloxy, sulfonamido, ether, thioether, substituted or unsubstituted alkylene groups, or combinations thereof; Z4, Z5 and Z6 each independently represent a group selected from carboxyl, hydroxy, nitro, cyano, C1 to C5 alkoxy, formyl, and sulfonic acid; g and h are independently integers from 0 to 4; g+h is 4 or less; i and j are independently integers from 0 to 2; i+j is 2 or less; k and l are independently integers from 0 to 3; k+l is 3 or less);

[0037] [General Formula IV]

[0038]

[0039] (wherein: R4, R5 and R6 each independently represent a substituted or unsubstituted C1-C20 alkyl group, a substituted or unsubstituted C5-C12 aryl group, or a combination thereof, containing one or more groups selected from carbonyl, carbonyloxy, sulfonamido, ether, thioether, substituted or unsubstituted alkylene groups, or combinations thereof; Z4, Z5 and Z6 each independently represent a group selected from carboxyl, hydroxy, nitro, cyano, C1 to C5 alkoxy, formyl, and sulfonic acid; g and h are independently integers from 0 to 4; g+h is 4 or less; i and j are independently integers from 0 to 1; i+j is 1 or less; k and l are independently integers from 0 to 4; k+l is 4 or less).

[0040] Suitable aromatic acids may alternatively have the following general formula V:

[0041] [General Formula V]

[0042]

[0043] (wherein: R7 and R8 each independently represent a substituted or unsubstituted C1-C20 alkyl group, a substituted or unsubstituted C5-C14 aryl group, or a combination thereof, containing one or more groups selected from carboxyl, carbonyl, carbonyloxy, sulfonamido, ether, thioether, substituted or unsubstituted alkylene groups, or combinations thereof; Z7 and Z8 each independently represent a group selected from hydroxy, nitro, cyano, C1-C5 alkoxy, formyl, and sulfonic acid; m and n are independently integers from 0 to 5; m+n is 5 or less; o and p are independently integers from 0 to 4; o+p is 4 or less).

[0044] In addition, exemplary aromatic acids may have the following general formula VI:

[0045] [General Formula VI]

[0046]

[0047] (wherein: X is O or S; R9 is independently or optionally a substituted or unsubstituted C1-C20 alkyl group, a substituted or unsubstituted C5-C20 aryl group, or a combination thereof containing one or more groups selected from carbonyl, carbonyloxy, sulfonamido, ether, thioether, substituted or unsubstituted alkylene groups, or combinations thereof; Z9 independently represents a group selected from carboxyl, hydroxy, nitro, cyano, C1 to C5 alkoxy, formyl, and sulfonic acid; q and r are independently integers from 0 to 3; and q+r is 3 or less).

[0048] In one or more embodiments, the acid is a free acid having fluorine substitution. Suitable free acids having fluorine substitution may be aromatic or non-aromatic. For example, free acids having fluorine substitution that can be used as solubility-converting agents include, but are not limited to, the following:

[0049]

[0050]

[0051]

[0052]

[0053]

[0054] Suitable TAGs include those capable of producing non-polymeric acids as described above. The TAG may be nonionic or ionic. Suitable nonionic thermal acid generators include, for example, cyclohexyl trifluoromethyl sulfonate, methyl trifluoromethyl sulfonate, cyclohexyl p-toluenesulfonate, methyl p-toluenesulfonate, cyclohexyl 2,4,6-triisopropylbenzenesulfonate, nitrobenzyl ester, benzoin tosylate, 2-nitrobenzyl tosylate, tris(2,3-dibromopropyl)-1,3,5-triazine-2,4,6-trione, alkyl esters of organic sulfonic acids, p-toluenesulfonic acid, dodecylbenzenesulfonic acid, oxalic acid, phthalic acid, phosphoric acid, camphorsulfonic acid, 2,4,6-trimethylbenzenesulfonic acid, triisopropylnaphthalenesulfonic acid, 5-nitro-o-toluenesulfonic acid, 5-sulfosalicylic acid, 2,5-dimethylbenzenesulfonic acid. Includes 2-nitrobenzenesulfonic acid, 3-chlorobenzenesulfonic acid, 3-bromobenzenesulfonic acid, 2-fluorocaprylnaphthalenesulfonic acid, dodecylbenzenesulfonic acid, 1-naphthol-5-sulfonic acid, 2-methoxy-4-hydroxy-5-benzoylbenzenesulfonic acid, and salts thereof, and combinations thereof. Suitable ionic thermal acid generators include, for example, dodecylbenzenesulfonic acid triethylamine salt, dodecylbenzenedisulfonic acid triethylamine salt, p-toluenesulfonic acid-ammonium salt, p-toluenesulfonic acid-pyridinium salt, sulfonate salts, such as carbocyclic aryl and heteroaryl sulfonate salts, aliphatic sulfonate salts, and benzenesulfonate salts. Compounds that produce sulfonic acid upon activation are generally suitable. Desirable thermal acid generating agents include ammonium p-toluenesulfonate salts and heteroaryl sulfonate salts.

[0055] Preferably, the TAG is ionic, having a reaction scheme for the production of sulfonic acid as shown below:

[0056]

[0057] (Here, RSO3 - is a TAG anion, and X +is a TAG cation, preferably an organic cation. The cation may be a nitrogen-containing cation of General Formula I:

[0058] [General Formula I]

[0059] (BH) +

[0060] (This is a single-protonated form of a nitrogen-containing base B. Suitable nitrogen-containing base B includes, for example: optionally substituted amines, e.g., ammonia, difluoromethylammonium, C1-20 alkyl amines, and C3-30 aryl amines, e.g., nitrogen-containing heteroaromatic bases, e.g., pyridine or substituted pyridine (e.g., 3-fluoropyridine), pyrimidine, and pyrazine; nitrogen-containing heterocyclic groups, e.g., oxazole, oxazolin, or thiazolin. The nitrogen-containing base B may be optionally substituted with one or more groups selected from, for example, alkyl, aryl, halogen atoms (preferably fluorine), cyano, nitro, and alkoxy. Among these, base B is preferably a heteroaromatic base.

[0061] Base B typically has a pKa of 0 to 5.0, or 0 to 4.0, or 0 to 3.0, or 1.0 to 3.0. As used herein, the term “pKa” is used according to the meaning recognized in the art, namely, pKa is the conjugate acid (BH) of the basic moiety (B) in an aqueous solution at approximately room temperature. + It is the negative logarithm of the dissociation constant (for 10 of the brine). In certain embodiments, base B has a boiling point of less than about 170°C, or less than about 160°C, 150°C, 140°C, 130°C, 120°C, 110°C, 100°C, or 90°C.

[0062] Exemplary suitable nitrogen-containing cation (BH) + is NH4 + , CF2HNH2 + , CF3CH2NH3 + , (CH3)3NH+ , (C2H5)3NH + , (CH3)2(C2H5)NH + and includes the following:

[0063]

[0064] (Here, Y is alkyl, preferably methyl or ethyl).

[0065] In certain embodiments, the solubility-converter may be an acid such as trifluoromethanesulfonic acid, perfluoro-1-butanesulfonic acid, p-toluenesulfonic acid, 4-dodecylbenzenesulfonic acid, 2,4-dinitrobenzenesulfonic acid, and 2-trifluoromethylbenzenesulfonic acid; an acid-generating agent such as triphenylsulfonium antimonate, pyridinium perfluorobutanesulfonate, 3-fluoropyridinium perfluorobutanesulfonate, 4-t-butylphenyltetramethylenesulfonium perfluoro-1-butanesulfonate, 4-t-butylphenyltetramethylenesulfonium 2-trifluoromethylbenzenesulfonate, and 4-t-butylphenyltetramethylenesulfonium 4,4,5,5,6,6-hexafluorodihydro-4H-1,3,2-dithiazine 1,1,3,3-tetraoxide; or a combination thereof.

[0066] Alternatively, the solubility-converter may comprise a base or a base-generating agent. In such embodiments, suitable solubility-converters include, but are not limited to, hydroxides, carboxylates, amines, imines, amides, and mixtures thereof. Specific examples of bases include ammonium carbonate, ammonium hydroxide, ammonium hydrogen phosphate, ammonium phosphate, tetramethylammonium carbonate, tetramethylammonium hydroxide, tetramethylammonium hydrogen phosphate, tetramethylammonium phosphate, tetraethylammonium carbonate, tetraethylammonium hydroxide, tetraethylammonium hydrogen phosphate, tetraethylammonium phosphate, and combinations thereof. Amines include aliphatic amines, cycloaliphatic amines, aromatic amines, and heterocyclic amines. Amines may be primary, secondary, or tertiary amines. Amines may be monoamines, diamines, or polyamines. Suitable amines may include C1-30 organic amines, imines, or amides, or may be C1-30 quaternary ammonium salts of strong bases (e.g., hydroxyides or alkoxides) or weak bases (e.g., carboxylates). Exemplary bases include amines such as tripropylamine, dodecylamine, tris(2-hydroxypropyl)amine, and tetrakis(2-hydroxypropyl)ethylenediamine; The ionic quenching agent comprises arylamines such as diphenylamine, triphenylamine, aminophenol, and 2-(4-aminophenyl)-2-(4-hydroxyphenyl)propane, Troger bases, hindered amines such as diazabicycloundecene (DBU) or diazabicyclononene (DBN), amides such as tert-butyl 1,3-dihydroxy-2-(hydroxymethyl)propane-2-ylcarbamate and tert-butyl 4-hydroxypiperidin-1-carboxylate; or quaternary alkylammonium salts such as tetrabutyl hydroxide (TBAH) or tetrabutylammonium lactate. In another embodiment, the amine is a hydroxyamine.Examples of hydroxyamines include hydroxyamines having one or more hydroxyalkyl groups, such as hydroxymethyl, hydroxyethyl, and hydroxybutyl groups, each having 1 to about 8 carbon atoms and preferably 1 to about 5 carbon atoms. Specific examples of hydroxyamines include mono-, di-, and tri-ethanolamines, 3-amino-1-propanol, 2-amino-2-methyl-1-propanol, 2-amino-2-ethyl-1,3-propanediol, tris(hydroxymethyl)aminomethane, N-methylethanolamine, 2-diethylamino-2-methyl-1-propanol, and triethanolamine.

[0067] Suitable base generators may be thermal base generators. Thermal base generators form a base when heated above a first temperature, typically about 140°C or higher. Thermal base generators may include functional groups such as amides, sulfonamides, imides, imines, O-acyl oximes, benzoyloxycarbonyl derivatives, quaternary ammonium salts, nifedipine, carbamates, and combinations thereof. Exemplary thermobase generators may include o-{(.beta.-(dimethylamino)ethyl)aminocarbonyl}benzoic acid, o-{(.gamma.-(dimethylamino)propyl)aminocarbonyl}benzoic acid, 2,5-bis{(.beta.-(dimethylamino)ethyl)aminocarbonyl}terephthalic acid, 2,5-bis{(.gamma.-(dimethylamino)propyl)aminocarbonyl}terephthalic acid, 2,4-bis{(.beta.-(dimethylamino)ethyl)aminocarbonyl}isophthalic acid, 2,4-bis{(.gamma.-(dimethylamino)propyl)aminocarbonyl}isophthalic acid, and combinations thereof.

[0068] Alternatively, in one or more embodiments, the solubility-converter comprises a crosslinking agent. Suitable crosslinking agents that can be used as the solubility-converter include, but are not limited to, crosslinking agents used for bis-epoxide curing, such as bisphenol A diglycidyl ether, 2,5-bis[(2-oxyranylmethoxy)-methyl]-furan, 2,5-bis[(2-oxyranylmethoxy)methyl]-benzene, melamine, glycuryls such as tetramethoxymethyl glycoluryl and tetrabutoxymethyl glycoluryl, benzoguanamine-based materials such as benzoguanamine, hydroxymethylbenzoguanamine, methylated hydroxymethylbenzoguanamine, ethylated hydroxymethylbenzoguanamine, and urea-based materials.

[0069] In one or more embodiments, the selective adhesive comprises a solvent. The solvent is typically selected from water, organic solvents, and mixtures thereof. In some embodiments, the solvent may comprise an organic solvent system comprising one or more organic solvents. The term “organic” means that the solvent system comprises more than 50 wt% of an organic solvent based on the total solvent of the solubility-converter composition, more typically more than 90 wt%, more than 95 wt%, more than 99 wt%, or more than 100 wt% of an organic solvent based on the total solvent of the solubility-converter composition. The solvent component is typically present in an amount of 90 to 99 wt% based on the solubility-converter composition.

[0070] Organic solvents suitable for the selective adhesive composition are, for example: alkyl esters such as alkyl propionates such as n-butyl propionate, n-pentyl propionate, n-hexyl propionate and n-heptyl propionate, and alkyl butyrates such as n-butyl butyrate, isobutyl butyrate and isobutyl isobutyrate; ketones such as 2,5-dimethyl-4-hexanone and 2,6-dimethyl-4-heptanone; aliphatic hydrocarbons such as n-heptane, n-nonane, n-octane, n-decane, 2-methylheptane, 3-methylheptane, 3,3-dimethylhexane and 2,3,4-trimethylpentane, and fluorinated aliphatic hydrocarbons such as perfluoroheptane; Alcohols, for example, straight-chain, branched, or cyclic C4-C91 alcohols, for example, 1-butanol, 2-butanol, isobutyl alcohol, tert-butyl alcohol, 3-methyl-1-butanol, 1-pentanol, 2-pentanol, 4-methyl-2-pentanol, 1-hexanol, 1-heptanol, 1-octanol, 2-hexanol, 2-heptanol, 2-octanol, 3-hexanol, 3-heptanol, 3-octanol, and 4-octanol; 2,2,3,3,4,4-hexafluoro-1-butanol, 2,2,3,3,4,4,5,5-octafluoro-1-pentanol and 2,2,3,3,4,4,5,5,5,6,6-decafluoro-1-hexanol, and C5-C9 fluorinated diols such as 2,2,3,3,4,4-hexafluoro-1,5-pentanediol, 2,2,3,3,4,4,5,5-octafluoro-1,6-hexanediol and 2,2,3,3,4,4,5,5,6,6,7,7-dodecafluoro-1,8-octanediol; ethers such as isopentyl ether and propylene glycol monomethyl ether; Esters, for example, alkyl esters having a total number of carbon atoms of 4 to 10, for example, propylene glycol monomethyl ether acetate; alkyl propionates, for example, n-butyl propionate, n-pentyl propionate, n-hexyl propionate, and n-heptyl propionate; and alkyl butyrates, for example, n-butyl butyrate, isobutyl butyrate, and isobutyl isobutyrate; ketones, for example, 2,5-dimethyl-4-hexanone and 2,6-dimethyl-4-heptanone;and polyethers such as dipropylene glycol monomethyl ether and tripropylene glycol monomethyl ether; and a mixture containing one or more of these solvents.;

[0071] In some embodiments, after coating the substrate with a selective adhesive, the substrate is pretreated. The substrate is pretreated to ensure adhesion of the selective adhesive to the surface of the feature. The pretreatment may be a soft bake performed for about 30 to 90 seconds at a temperature in the range of 50 to 150°C.

[0072] After the selective adhesive material is attached to the feature, any excess material may be removed. Thus, in one or more embodiments, a selective adhesive is applied to a substrate, optionally pretreated, and then the substrate is cleaned to remove unused material.

[0073] Then, in block (106) of the method (100), a first resist is deposited on a substrate. FIG. 2c illustrates a substrate (200) comprising a base layer (201) and an existing feature (202) coated with an optional adhesive (203) and a first resist (204). Generally, the resist is a chemically amplified photosensitive composition comprising a polymer, a photogenerator, and a solvent. In one or more embodiments, the first resist comprises a polymer. The polymer may be any standard polymer typically used in resist materials, and in particular may be a polymer having acid-unstable groups. The polymer may be a polymer prepared from monomers comprising vinyl aromatic monomers such as styrene and p-hydroxystyrene, acrylates, methacrylates, norbornene, and combinations thereof. For example, the polymer may be a polymer prepared from monomers including styrene, p-hydroxystyrene, acrylates, methacrylates, norbornene, and combinations thereof. Monomers containing reactive functional groups may be present in the polymer in a protected form. For example, the -OH group of p-hydroxystyrene may be protected by a tert-butyloxycarbonyl protecting group. Such protecting groups may alter the reactivity and solubility of the polymer contained in the first resist. As understood by those skilled in the art, various protecting groups may be used for this reason. Acid-unstable groups include, for example: tertiary alkyl ester groups, secondary or tertiary aryl ester groups, secondary or tertiary ester groups having a combination of alkyl and aryl groups, tertiary alkoxy groups, acetal groups, or ketal groups. Acid-unstable groups are also commonly referred to in the industry as "acid-degradable groups," "acid-cutting groups," "acid-cutting protectors," "acid-unstable protectors," "acid-extractable groups," and "acid-sensitive groups."

[0074] The acid-unstable group that forms a carboxylic acid on the polymer upon decomposition is preferably of the formula -C(O)OC(R 1)3 tertiary ester group or chemical formula -C(O)OC(R 2 )2OR 3 The acetal group of (here: R 1 Each is independently a linear C 1-20 Alkyl, branched chain type C 3-20 Alkyl, monocyclic, or polycyclic C 3-20 Cycloalkyl, straight-chain C 2-20 Alkenyl, branched chain type C 3-20 Alkenyl, monocyclic, or polycyclic C 3-20 Cycloalkenyl, monocyclic, or polycyclic C 6-20 Aryl, or monocyclic, or polycyclic C 2-20 Heteroaryl, preferably a straight-chain type C 1-6 Alkyl, branched chain type C 3-6 Alkyl, or monocyclic or polycyclic C 3-10 They are cycloalkyl, each of which is substituted or unsubstituted (each R 1 is optionally included as part of its structure one or more groups selected from -O-, -C(O)-, -C(O)-O-, or -S-, and any two R 1 (Gi selectively forms a ring together); R 2 It independently consists of hydrogen, fluorine, and straight-chain C 1-20 Alkyl, branched chain type C 3-20 Alkyl, monocyclic, or polycyclic C 3-20 Cycloalkyl, straight-chain C 2-20 Alkenyl, branched chain type C 3-20 Alkenyl, monocyclic, or polycyclic C 3-20 Cycloalkenyl, monocyclic, or polycyclic C 6-20 Aryl, or monocyclic, or polycyclic C 2-20 Heteroaryl, preferably hydrogen, straight-chain C 1-6 Alkyl, branched chain type C 3-6 Alkyl, or monocyclic or polycyclic C 3-10 Cycloalkyl (each of these is substituted or not substituted, and each R 2is optionally composed of one or more groups selected from -O-, -C(O)-, -C(O)-O-, or -S- as part of its structure, and R 2 (which selectively forms a ring together) and; R 3 It is a straight chain type C 1-20 Alkyl, branched chain type C 3-20 Alkyl, monocyclic, or polycyclic C 3-20 Cycloalkyl, straight-chain C 2-20 Alkenyl, branched chain type C 3-20 Alkenyl, monocyclic, or polycyclic C 3-20 Cycloalkenyl, monocyclic, or polycyclic C 6-20 Aryl, or monocyclic, or polycyclic C 2-20 Heteroaryl, preferably a straight-chain type C 1-6 Alkyl, branched chain type C 3-6 Alkyl, or monocyclic or polycyclic C 3-10 Cycloalkyl (each of these is substituted or not substituted, and R 3 is optionally composed of one or more groups selected from -O-, -C(O)-, -C(O)-O-, or -S- as part of its structure, and 1 R 2 is R 3 (It selectively forms a ring together with). These monomers are typically vinyl aromatic, (meth)acrylate, or norbornyl monomers. The total content of polymerization units containing acid-degradable groups that form carboxylic acid groups on the polymer is typically 10 to 100 mol%, more typically 10 to 90 mol% or 30 to 70 mol% based on the total polymerization units of the polymer.

[0075] The polymer may further comprise monomers containing polymerized acid-unstable groups, which decompose to form alcohol or fluoroalcohol groups on the polymer. Suitable such groups include, for example, the formula -COC(R 2 )2OR 3It includes an acetal group of - or a carbonate ester group of the formula -OC(O)O-, where R is as defined above. These monomers are typically vinyl aromatic, (meth)acrylate, or norbornyl monomers. When present in the polymer, the total content of polymerization units containing acid-degradable groups (which decompose to form alcohol or fluoroalcohol groups on the polymer) is typically 10 to 90 mol%, more typically 30 to 70 mol%, based on the total polymerization units of the polymer.

[0076] In some embodiments, the first resist has a composition similar to that of a positive tone developed (PTD) resist. In these embodiments, the first resist may comprise a polymer prepared from the monomers described above, wherein one or more monomers containing reactive functional groups are protected. Thus, the PTD-type first resist may be organically soluble.

[0077] In another embodiment where the solubility-converting agent is the crosslinking agent, the first resist is a negative resist. In this embodiment, the first resist may comprise a polymer prepared from the aforementioned monomers, wherein any monomer containing a reactive functional group is not protected. Suitable reactive functional groups include, but are not limited to, alcohols, carboxylic acids, amines, and epoxides. Upon exposure to the crosslinking agent, the polymer is crosslinked, and the polymer becomes insoluble in the developer. Then, the uncrosslinked regions can be removed using a suitable developer.

[0078] In another embodiment, the first resist is a negative tone developing (NTD) resist. Similar to the PTD resist, the NTD resist may comprise a polymer prepared from the monomers described above, wherein one or more monomers containing reactive functional groups are protected. Thus, the NTD first resist may be organically soluble, but instead of developing the solubility-converted regions with a first resist developer that is basic, the solubility-converted regions remain, while the regions containing the protected functional groups are removed using a first resist developer containing an organic solvent. Suitable organic solvents that can be used as the first resist developer include n-butyl acetate (NBA) and 2-heptanone. The tone of the resist ( in other words , PTD vs. Negative vs. NTD) can affect the final pattern placement.

[0079] In one or more embodiments, the first resist is laminated on a substrate to have a thickness of about 300 Å to about 3000 Å.

[0080] In block (108) of the method (100), a solubility-converting agent is activated. In an embodiment where the solubility-converting agent is an acid, an acid-generating agent, a base, or a base-generating agent, the activation of the solubility-converting agent comprises diffusing the solubility-converting agent into the first resist to provide a solubility-converted region of the first resist. The solubility-converted region of the first resist may be determined by the preferential adhesion of an optional adhesive. For example, an optional adhesive that preferentially adheres to features of an existing pattern may provide a solubility-converted region of the first resist over the features. In one or more embodiments, the solubility-converted region of the first resist extends vertically from the surface of the optional adhesive coated on the features to the surface of the first resist. In one or more embodiments, the solubility-converted region extends in an inclined direction. When the solubility-converted region extends in an inclined direction, it may be desirable to prevent the features from merging with each other. To achieve this, the feature thickness can be controlled to become sufficiently thin.

[0081] In one or more embodiments, baking is performed to diffuse the solubility-converter into the first resist. Baking may be performed using a hot plate or an oven. Baking temperature and time may vary depending on the characteristics of the second resist and the desired amount of solubility-converter diffusion into the second resist. Suitable conditions for baking may include a temperature in the range of about 50°C to about 160°C and a time in the range of about 30 seconds to about 90 seconds.

[0082] In an embodiment where the solubility-converter is a crosslinking agent, activation of the solubility-converter includes initiating polymerization of the crosslinking agent into the first resist. Activation of the crosslinking agent may provide a crosslinked region of the first resist. The crosslinked region of the first resist may be determined by the preferential adhesion of a selective adhesive. For example, when the selective adhesive is preferentially attached to a feature of an existing pattern, such as in selective patterning self-alignment, the crosslinked region of the first resist may be on the feature.

[0083] Then, in block (110) of the method (100), the first resist is developed using a specific developer. The specific developer may be any developer commonly used in the field. The composition of the specific developer may vary depending on the tone and solubility characteristics of the first resist. For example, if the first resist is a positive tone developed resist, the specific developer may be a base such as tetramethylammonium hydroxide. Meanwhile, if the first resist is a negative tone developed resist, the specific developer may be a non-polar organic solvent such as n-butyl acetate or 2-heptanone.

[0084] In one or more embodiments, the selective adhesive is preferentially adhered to the base layer (201) rather than the existing feature (202), and the solubility-converted or crosslinked regions are insoluble in the first developer. In these embodiments, after developing the first resist, the solubility-converted or crosslinked regions of the first resist may remain on the substrate. Alternatively, in one or more embodiments, the selective adhesive is preferentially adhered to the existing feature (202) rather than the base layer (201), and the solubility-converted regions become soluble in the first developer. In these embodiments, after developing the first resist, the solubility-converted regions of the first resist are removed from the substrate. This pattern may be referred to as a non-selective pattern because regions of the resist remain on the base layer that is not coated with the selective adhesive.

[0085] It will be understood that FIGS. 2a through 2i illustrate a coated substrate at each point of a method in which a solubility-converter is dissolved in a first developer and selectively attached to existing features (202) so as to preferentially attach to features of an existing pattern. An embodiment is considered in which the solubility-converter is insoluble in the first developer and selectively attached to a base layer (201) between existing features (202). Thus, it will be understood that a coated substrate having exposed existing features can be produced by using a solubility-converter that is dissolved in the first developer or a solubility-converter that is insoluble in the first developer, as exemplified in FIG. 2d as being soluble in the first developer for the solubility-converter.

[0086] In one or more embodiments, the selective adhesive is preferentially attached to the existing feature (202), and the solubility-converted region of the first resist is soluble in the first developer. In these embodiments, the development of the first resist creates a pattern of the first resist that includes a gap exposing the feature of the existing pattern. Thus, the selective adhesive is exposed and accessible for additional coating. FIG. 2d illustrates a coated substrate in which a gap (205) of the first resist (204) exposes the existing feature (202) within the base layer (201) of the existing pattern of the substrate (200). In one or more embodiments, a rinsing procedure removes any remaining selective adhesive before metallization.

[0087] Then, in block (112) of the method (100), selective growth on a feature of an existing pattern is performed. Any suitable selective growth technique known in the art can be used to directly provide a selectively grown feature on a feature of an existing pattern. FIG. 2e shows a substrate (200) comprising an existing feature (202) in a base layer (201), a first resist (204) offset from the existing feature (202), and a selectively grown feature (206) on the existing feature (202).

[0088] In one or more embodiments, the selective growth feature comprises a selective growth material. Various types of selective growth deposition materials known in the art are suitable for the various embodiments disclosed herein. In some embodiments, selective metal-to-metal reactive deposition may be achieved in solution using techniques such as electroless metal deposition and / or electrochemical atomic layer deposition. Examples of metals suitable for such metal-to-metal reactive deposition include, but are not limited to, copper (Cu), nickel (Ni), cobalt (Co), iron (Fe), manganese (Mn), chromium (Cr), titanium (Ti), tantalum (Ta), ruthenium (Ru), palladium (Pd), and various alloys, stacks, or other combinations thereof. Other metals that can be deposited by selective reaction using electroless metal deposition and / or electrochemical atomic layer deposition should also generally be suitable.

[0089] In some embodiments, selective metal-metal reactive deposition may be performed using a homometal diazabutadiene complex [M{N(R)C(H)C(H)N(R')}2]. In the above formula, M may represent a metal atom selected from nickel (Ni), cobalt (Co), iron (Fe), manganese (Mn), or chromium (Cr). Organic functional groups R and R' may represent any of various substituted or unsubstituted alkyl or aryl functional groups. Examples of R and R' include, but are not limited to, 2 to 8 carbon alkyl groups, phenyl groups, etc. Various combinations of complexes (e.g., having various metal atoms) may also be optionally used. Metals (e.g., pure metals or multi-metal alloys or stacks) can be deposited on starting metals and / or metals deposited from these complexes using Chemical Vapor Deposition (CVD), with or without co-reactants (e.g., hydrogen (H2), ammonia (NH3), hydrazine, etc.). Atomic Layer Deposition (ALD) may be used alternatively. Such deposition is generally selective compared to dielectric materials, semiconductor materials, and organic polymer materials.

[0090] In some embodiments, the applied voltage and / or photoelectric effect may be used to promote metal deposition and / or increase the selectivity of metal deposition to the metal compared to other materials (e.g., dielectrics). In some embodiments, a voltage bias may be applied between the wafer or other substrate and the conductive hardware of the metal deposition equipment, for example, between the wafer chuck and the coil on the wafer on the wafer chuck. This voltage bias may be direct current (DC) or alternating current (AC) (e.g., radio frequency AC). The applied voltage bias may tend to generate relatively more electrons (e.g., secondary electrons) from the metal (e.g., interconnect lines or metal material formed on interconnect lines) than other materials (e.g., dielectrics), reduce the energy required to emit them, or provide electrons (e.g., secondary electrons), for example, partly due to the photoelectric effect. In some embodiments, a forward voltage bias may be applied to help accelerate electrons away from the metal. When using a DC voltage bias, there is a possibility that after some electrons are emitted from the metal, the electron emission slows down and, without a conductive path to the metal, it may begin to have a net positive charge. However, applying an AC voltage bias can generally help prevent this by loading electrons into the metal backup between cycles. Electrons can be used to promote metal deposition and / or increase the selectivity of metal deposition on the metal compared to other materials (e.g., dielectrics). Electrons can help provide energy to drive or promote selective metal deposition reactions, such as ALD or CVD deposition of metals or other metal deposition processes that can be facilitated by the generated electrons. In some embodiments, an ultraviolet light source may be used along with the voltage bias to help generate more photoelectrons near the metal.This can additionally help promote metal deposition and metal deposition selectivity.

[0091] In some embodiments, selective dielectric-dielectric reactive deposition may be achieved by solution-phase techniques such as sol-gel processes. Selective dielectric-dielectric reactive deposition may also be achieved by CVD, ALD, MLD, or other vapor-phase techniques. Examples of materials suitable for such dielectric-dielectric reactive deposition include, but are not limited to, silicon oxide (e.g., silicon dioxide (SiO2)), carbon-doped silicon oxide, silicon nitride (e.g., silicon nitride (SiN)), silicon carbide (e.g., silicon carbide (SiC)), silicon carbonitride (e.g., SiCN), aluminum oxide (e.g., aluminum oxide (Al2O3)), titanium oxide (e.g., titanium oxide (TiO2)), zirconium oxide (e.g., zirconium oxide (ZrO2)), hafnium oxide (e.g., hafnium oxide (HfO2)), and combinations thereof. Other dielectric and low-k dielectric materials known in the art are also potentially suitable. Carbosiloxane materials may also be used optionally. Various examples of reactions that selectively or at least preferentially deposit these materials relative to metals using techniques such as sol-gel, ALD, CVD, and MLD are known in the art.

[0092] In some embodiments, one or more of carbon nanotubes, graphene, and graphite may be grown or formed on a metal surface material. The metal surface material may represent a catalytic metal surface material that catalyzes the growth of carbon nanotubes, graphene, and graphite. The catalytic metal surface material may be heated using techniques known in the art and exposed to suitable hydrocarbons and any other co-reactants. An example of a suitable catalytic surface and set of reactants is a cobalt surface exposed to carbon monoxide and hydrogen. The voltage bias approach described above may also potentially be used to help facilitate these reactions.

[0093] In some embodiments, a passivation material or layer may be optionally applied or formed over one of the other surface materials to help increase the selectivity or preferentiality of the reaction toward the other surface material. The use of such a passivation material generally helps to expand the number of possible optional / preferential reactions that can be used to form the layer. The reaction does not necessarily have to be optional / preferential toward one of the surface materials over the other, but nevertheless may be optional toward one of the surface materials relative to the passivation material. For example, to increase the selectivity / preferentiality of a given deposition reaction toward a second surface material relative to the passivation material, the passivation material may be applied to the first surface material but not to the second surface material. Most passivation materials that can operate to be formed optionally toward one of the materials and to operate to increase the selectivity / preferentiality of the reaction should generally be suitable. Such passivation agents may be applied in a vapor phase or a solution phase. Such passivation agents may be applied once or multiple times during the optional deposition process. After forming a layer through a selective / preferential reaction, the passivation material can be removed. For example, the passivation material can be removed through thermal, photodegradative, chemical, or electrochemical treatment. In some embodiments, a different passivation material may be optionally applied to a different surface material, but this is not necessarily required. Again, the use of such optional passivation materials can help expand the number of possible optional or at least preferential chemical reactions that can be used to form the various layers mentioned herein.

[0094] After selective growth is performed, in block (114) of the method (100), the first resist is removed. The first resist may be removed according to any method known in the art, provided that such method does not affect the selective growth feature. Thus, in one or more embodiments, after the removal of the first resist, only the selective growth feature remains. FIG. 2f illustrates a coated substrate from which the first resist has been removed so that the substrate (200) includes the selective growth feature (206) on the existing feature (202) in the base layer (201).

[0095] In one or more embodiments, the first resist is removed by rinsing. In particular, the first resist may be removed from the substrate by cleaning using an organic solvent. The organic solvent may be a solvent used as a first resist developer, such as, for example, n-butyl acetate (NBA) and heptanone, or a solvent used to apply the provided optional adhesive.

[0096] Optionally, if the first resist is removed, the selective growth feature may be coated. In some embodiments, prior to coating, the selective growth feature may be treated by means such as smoothing the surface of the selective growth feature. The selective growth feature may be planarized to provide a uniform surface for applying the coating layer. In one or more embodiments, the selective growth feature is stabilized prior to coating. Various resist stabilization techniques, also known as freezing processes such as ion implantation, UV curing, thermal hardening, thermal curing, and chemical curing, have been proposed. These techniques are described, for example, in US2008 / 0063985A1, US 2008 / 0199814A1, and US 2010 / 0330503A1. After any of these treatments, the selective growth feature may be coated with one or more coating layers. One or more coating layers may be applied to the selective growth feature so that the selective growth feature is completely coated. For example, one or more coating layers may be coated on the top and both sides of the optional growth feature. A substrate (200) comprising a base layer (201), an existing feature (202), and an optional growth feature (206) coated by a coating layer (207) is illustrated in FIG. 2g.

[0097] In some embodiments, after coating the optional growth feature, the substrate is etched to remove any remaining coating, such as excess resist or optional attachment material, from the surface of the base layer. Then, a filling layer is deposited on the substrate to fill the substrate (118). A coated substrate according to block (118) is shown in FIG. 2h. As shown in FIG. 2h, the substrate (200) comprises a base layer (201), an existing feature (202), and an optional growth feature (206) coated by a coating layer (207) separated by a filling layer (208). FIG. 2h illustrates a coating layer over the optional growth feature, which may not be present in all embodiments of the present disclosure. Examples of materials suitable for the packing layer include, but are not limited to, silicon oxide (e.g., silicon dioxide (SiO2)), carbon-doped silicon oxide, silicon nitride (e.g., silicon nitride (SiN)), silicon carbide (e.g., silicon carbide (SiC)), silicon carbonitride (e.g., SiCN), aluminum oxide (e.g., aluminum oxide (Al2O3)), titanium oxide (e.g., titanium oxide (TiO2)), zirconium oxide (e.g., zirconium oxide (ZrO2)), hafnium oxide (e.g., hafnium oxide (HfO2)), and combinations thereof. Subsequently, a chemical-mechanical polishing process may be used to planarize the surface. For example, if silicon dioxide is deposited and an excess portion is provided by this deposition, the excess portion can be removed by chemical-mechanical polishing.

[0098] Finally, in method (100), blocks (104 to 118) are repeated to provide a multi-level patterned substrate. The steps shown in blocks (104 to 118) may be repeated any number of times to provide a stacked device having a suitable number of optionally patterned levels. For example, blocks (104 to 120) may be repeated 1, 2, 3, or even 4 times to provide a 5-level multi-level stacked device. An exemplary multi-level stacked device comprising four distinct optional growth layers is shown in FIG. 2i.

[0099] In each repeating block (104 to 118), the process step (e.g., deposition, coating, etc.) and material (e.g., first resist, selective-adhesion agent, solubility-converting agent, selective-growth material, etc.) are as described above. However, in some embodiments, the material included in each block may be the same or different for each repeat. In particular, the selective growth material may be different for each layer of the multi-level stack. For example, the selective growth material may be a silane-containing monolayer in the first layer of the 3-level stacked device, a phosphonate ester in the second layer, and a triazole in the third layer. Thus, the method (100) can provide a composite multi-level stacked device having a layer having a vertical growth pattern due to constraints applied by the surrounding first resist.

[0100] In one or more embodiments, the method includes a photolithography step. The photolithography step may be used to select a specific feature, a part of a feature, or other area. For example, selective placement and growth may be achieved using a directional growth process as in the method (100) described above. Then, a first resist may be exposed to form a patterned array that exposes the target area and activates the solubility-converter in that area. Then, a heat treatment causes the solubility-converter to diffuse through the resist layer and promotes the solubility-conversion reaction. The solubility-converter (e.g., acid) makes the resist soluble, and the corresponding portion is removed. Then, selective growth on the metal / substrate may be performed. Selective growth may be preceded by an etching step to remove any residual coating of the selective adhesive and / or solubility-converter from the top of the uncovered feature.

[0101] The method according to the present disclosure can provide a unique pattern having high-density features. In one or more embodiments, deposition at the center uses an alternative step for forming local high-density magnetic random access memory (MRAM). An exemplary method for the core region is provided below. The coated substrate is illustrated at each point of the method of FIGS. 4a through 4d. All depositions are preferably nearly collimated. For control, the oxide is preferably formed by atomic layer deposition.

[0102] The method may begin with the same steps as method (100). For example, a substrate (401) having an existing feature (402) may be provided, an optional adhesive may be deposited, and a first resist (403) may be laminated onto the substrate, subsequently developed to provide a relief pattern in which a gap exists over the existing feature of the substrate and the optional adhesive. Then, as shown in FIG. 4a, an optional growth material (404), such as a conductor / metal, for example, is deposited. As shown in FIG. 4b, the optional growth material is etched back to a predetermined depth (before or after placement). As shown in FIG. 4b, the substrate (401) comprises an existing feature (402), a first resist (403) offset from the existing feature (402), and an optional growth material (404) shorter than the first resist (403). In one or more embodiments, the optional growth material is etched back by the depth of the magnetic layer to be deposited. The selective growth material can be etched back to include additional space for deformation. Then, the magnetic layer (405) is deposited as shown in FIG. 4c. As shown in FIG. 4c, the substrate (401) comprises a first resist (403) and a selective growth material (404) coated on the existing feature (402) and the magnetic layer (405). The deposition of the magnetic layer can provide the magnetic layer on top of the selective growth material and the first resist. The magnetic layer may be a magnetoresistance memory device or cap, such as a polarization layer, an insulator, a free layer, a tunnel junction, a synthetic antiferromagnet, for example. Then, as shown in FIG. 4d, the portion of the magnetic layer (405) on top of the first resist (403) is removed so that the magnetic layer (405) remains only on the selective growth material (404) on the feature (402) of the substrate (401). Optionally, a final etching or chemical cleaning step is performed to "clean" or remove the edges of the feature without serious damage.

[0103] The resulting structure is an etch-free implementation of magnetic material. This enables increased density and dramatic cost reduction. Note that the shapes in FIGS. 4a through 4d are depicted as cylindrical but are not limited thereto. Other shapes may be used. Since the selective growth technique is independent of the target, the shapes do not need to be round features.

[0104] FIG. 5a illustrates an incomplete CMOS device (500) according to one or more embodiments. Since the selective growth procedure has not yet been performed on the incomplete CMOS device (500), the incomplete CMOS device (500) is merely a partial transistor and can be regarded as a substrate having an existing pattern as described in block (102) of FIG. 1. The incomplete CMOS device (500) is regarded as a complementary metal oxide semiconductor because it includes both an NMOS portion (501) and a PMOS portion (502). The incomplete CMOS device (500) has a plurality of existing features (504 to 508) as well as a substrate (503). The substrate (503) and the existing features (504 to 508) are each composed of crystalline silicon doped to be converted into a conductive P-type or N-type material.

[0105] Elemental silicon is a semiconductor with four electrons in its outermost shell. The outer electron shell of any semiconductor material is known as the valence band because it can easily jump to the conduction band when excited by an electric current. Since each silicon atom in crystalline silicon forms a perfect covalent bond with four adjacent silicon atoms, it creates a lattice that acts as an insulator and conducts almost no electricity. Therefore, for crystalline silicon to be conductive, it must be doped with impurities.

[0106] P-type materials are silicon bases doped with atoms having three electrons in their outer shells. Boron and / or gallium atoms may be used for this purpose, but are not limited thereto. When crystalline silicon is doped with P-type atoms having only three outer electrons, positive charge carriers are created in the valence bands of adjacent silicon atoms. That is, because the P-type dopant lacks the fourth electron necessary to form a perfect covalent bond with each adjacent silicon atom, there is a single net positive charge known as a positively charged hole for each P-type atom in the silicon lattice. Since the P-type dopant is fixed to the crystal lattice, only positively charged holes can move. For this reason, silicon crystals doped with atoms having only three valence electrons are known as positive-type materials or P-type materials.

[0107] In contrast to P-type materials, there are N-type materials. N-type materials are silicon bases doped with atoms having five electrons in their outer shells. Arsenic and / or phosphorus atoms may be used for this purpose, but are not limited thereto. When crystalline silicon is doped with N-type atoms having five outer electrons, negative charge carriers are generated in the valence bands of adjacent silicon atoms. That is, the N-type dopant has a single net negative charge, which is a negatively charged electron for each N-type atom in the silicon lattice, because it possesses an additional fifth electron in addition to the four electrons that form perfect covalent bonds with each adjacent silicon atom. Since the extra negatively charged electron has nothing to bond with, it conducts electricity and can move freely throughout the lattice. For this reason, silicon crystals doped with atoms having five valence electrons are known as negative-type materials, or N-type materials.

[0108] In FIG. 5a, the brightly shaded portions corresponding to the substrate (503) and terminals (507 to 508) are P-type materials and are doped with boron, gallium, or other elements having three valence electrons. The internally patterned portions corresponding to the terminals (504 to 505) and well (506) are N-type materials and are doped with arsenic, phosphorus, or other elements having five valence electrons. Each portion of the incomplete CMOS device (500) is defined by the doping of the corresponding terminals. Thus, the left side of the CMOS device (500) having N-type terminals (504 to 505) is known as the NMOS portion (501). Likewise, the right side of the incomplete CMOS device (500) having P-type terminals (507 to 508) is known as the PMOS portion (502). The configuration of an incomplete CMOS device (500) combining both an NMOS portion (501) and a PMOS portion (502) may be more desirable than using only a single NMOS portion or a single PMOS portion, because the combined incomplete CMOS device (500) uses less power and is less sensitive to noise interference compared to a single device. As previously mentioned, since the selective growth procedure has not yet been performed on the incomplete CMOS device (500), the incomplete CMOS device (500) is merely a partial transistor and can be regarded as a substrate having an existing pattern as described in block (102) of FIG. 1.

[0109] FIG. 5b illustrates a DRAM device (600) according to one or more embodiments. The DRAM device (600) is similar to an incomplete CMOS device (500) associated with existing features (503 to 508); however, the DRAM device (600) may have undergone the multilayer selective patterning method (100) one or more times to become a complete device. For example, the DRAM device (600) may have undergone one or more iterations of the method (100) for multilayer selective patterning to grow additional features (510 to 512 and 520 to 522) as well as an insulating layer (509). The DRAM device (600) may function as a volatile random access memory, as described in more detail below.

[0110] Additional features (510 to 512 and 520 to 522) may include an NMOS control gate (510) for controlling the current between NMOS terminals (504 and 505) and a PMOS control gate (520) for controlling the current between PMOS terminals (507 and 508), as well as vias (511 to 512 and 521 to 522) that provide an electrical interface to each of the terminals (504 to 505 and 507 to 508). For example, via (511) may provide an electrical connection to terminal (504), via (512) may provide an electrical connection to terminal (505), via (521) may provide an electrical connection to terminal (507), and via (522) may provide an electrical connection to terminal (508). Additional features (510 to 512 and 520 to 522) are shown without shading to show that they may be made of a purely conductive material, such as aluminum or copper, to interface with existing features (504 to 508). An insulating layer (509) is placed on the surface of the substrate (503) and directly above the existing features (504 to 508) to provide electrical insulation between the additional features (510 to 512 and 520 to 522) that interface with the existing features (504 to 508). The insulating layer (509) may be a layer of silicon dioxide grown on the substrate (503) using method (100) or any other suitable method. Once the internal configuration of the DRAM device (600) is complete, it may undergo packaging and wire bonding processes so that it can be integrated into an integrated circuit (IC) of an electronic device. For example, the DRAM device (600) may be packaged and connected to an interactive television, a mobile phone, or a desktop computer. It will be recognized that the DRAM device (600) may be integrated into any number of electronic devices without departing from the spirit and scope of the present disclosure.

[0111] The DRAM device (600) can function as a volatile random access memory by storing data using the interaction between additional features (510 to 512 and 520 to 522) and existing features (504 to 508). For example, the NMOS portion (501) and the PMOS portion (502) can each represent a transistor capable of storing a single bit using the characteristics of electric capacitance. When charged using an excitation voltage, the electric capacitor can store its charge for a certain period. The presence or absence of charge in the capacitor represents 1 bit of data. When the capacitor is charged, the value of the bit is 1, and when the capacitor is discharged, the value of the bit is 0. The NMOS portion (501) and the PMOS portion (502) can store their charges between their respective terminals (504 to 505 and 507 to 508) using direct current (DC) electrical characteristics, as described in more detail below.

[0112] The process of writing data bits to the DRAM device (600) will be described in relation to the NMOS portion (501); however, it will be understood that the same process can be used to write data bits within the PMOS portion (502). Initially, the NMOS portion (501) functions as a field-effect transistor (FET). When the NMOS control gate (510) is off or no voltage is applied, current cannot flow through the terminals (504 and 505). Therefore, when the NMOS control gate (510) is off, the charge value between the terminals (504 and 505) cannot be changed. To store a charge or a value of 1 between the terminals (504 and 505), a charging circuit is used to apply voltage between the terminals (504 and 505) and rapidly turn the NMOS control gate (510) on and off. This process creates capacitance and stores a charge value of 1 between terminals (504 and 505). To store no charge or a value of 0 between terminals (504 and 505), a negative voltage is applied between terminals (504 and 505) using a charging circuit, and the NMOS control gate (510) is quickly switched on and off. This process removes the capacitance and stores a charge value of 0 between terminals (504 and 505).

[0113] Next, the process of reading data bits from the DRAM element (600) will be described in relation to the NMOS portion (501); however, it will be understood that the same process can be used to read data bits within the PMOS portion (502). To read the charge between terminals (504 and 505), the charging circuit applies a zero or floating voltage between terminals (504 and 505), and then the sensing circuit is applied to terminals (504 and 505). Next, the NMOS control gate (510) is quickly switched on and off. Because the charging circuit applied a zero voltage between terminals (504 and 505), when the NMOS control gate (510) is switched on and off, the value of the charge stored between terminals (504 and 505) will drive the sensing circuit to high or low depending on whether a zero or one bit is stored between terminals (504 and 505). If there is a voltage stored between terminals (504 and 505), the detection circuit detects a bit value of 1. If there is no voltage stored between terminals (504 and 505), the detection circuit detects a bit value of 0.

[0114] It will be understood that multiple DRAM elements (600) can be connected in parallel to store a larger amount of data. Additionally, the DRAM elements (600) are particularly suitable for operating as volatile random access memory. For example, because the DRAM elements (600) have a small number of parts and small tolerances, the DRAM elements (600) can transmit data quickly using less power. On the other hand, since the additional features (510 to 512 and 520 to 522) always have a DC connection to the charging and sensing circuit, the charge state between terminals (504 and 505) suffers from slow parasitic drain. Therefore, the charge state between terminals (504 and 505) must be refreshed periodically. Furthermore, if the DRAM element (600) is turned off, all of its stored data bits are lost.

[0115] FIG. 5c illustrates a 3D NAND device (700) according to one or more embodiments. The 3D NAND device (700) is similar to a DRAM device (600) with existing features (503 to 508), an insulating layer (509), and additional features (510 to 512 and 520 to 522); however, the 3D NAND device (700) may also include a floating NMOS gate (513) and a floating PMOS gate (523). The floating NMOS gate (513) and the floating PMOS gate (523) may allow the 3D NAND device (700) to store a charge state for a longer period of time, or even when the 3D NAND device (700) is turned off, as described in more detail below.

[0116] The process of writing data bits to the 3D NAND device (700) will be described in relation to the NMOS portion (501); however, it will be understood that the same process can be used to write data bits within the PMOS portion (502). As with the DRAM device (600), the NMOS portion (501) functions as a field-effect transistor (FET). However, unlike the DRAM device (600), the 3D NAND device (700) has a floating NMOS gate (513) placed within the NMOS portion (501). Since the floating NMOS gate (513) is completely surrounded by an insulating layer (509), it does not have a direct current (DC) electrical connection to the NMOS portion (501). This allows the floating NMOS gate (513) to operate as a perfect capacitor without a tendency to drain, which is an improvement over the temporary stored capacitance of the gates (504 and 505) of the DRAM device (600). However, charging and discharging the floating NMOS gate (513) requires a different process than that provided for the DRAM device (600).

[0117] To store a charge or a value of 1 within the floating NMOS gate (513), a voltage is applied between terminals (504 and 505) using a charging circuit, and the NMOS control gate (510) is turned on. Since there is no DC connection between the NMOS portion (501) and the floating NMOS gate (513), the floating NMOS gate (513) must be charged via tunneling or hot carrier injection. Tunneling and hot carrier injection refer to the process in which electrons and holes gain enough kinetic energy to jump over an insulating barrier. For example, if the insulating layer (509) is composed of silicon dioxide, electrons require approximately 3.2 electron volts (eV) of kinetic energy to be transferred to the floating NMOS gate (513). In order for the NMOS portion (501) to achieve the appropriate kinetic energy to charge the floating NMOS gate (513), the charging circuit must maintain the NMOS control gate (510) at a specific amount of voltage for a specific period depending on the configuration and size of the barrier. The voltage and duration values ​​are typically greater than the values ​​required to charge the DRAM device (600), and the values ​​are calculated in advance according to the design characteristics of the 3D NAND device (700).

[0118] Next, to store a charge or a value of zero within the floating NMOS gate (513), a negative voltage is applied between terminals (504 and 505) using a charging circuit, and the NMOS control gate (510) is turned on. Similar to the charging procedure for the floating NMOS gate (513), the floating NMOS gate (513) must also be discharged via tunneling or hot carrier injection. If the insulating layer (509) is composed of silicon dioxide, about 4.6 eV is required for holes to pass through the floating NMOS gate (513). To achieve the appropriate kinetic energy for the NMOS portion (501) to discharge the floating NMOS gate (513), the charging circuit must also apply a specific negative voltage to the NMOS control gate (510) for a specific period depending on the configuration and size of the barrier. The voltage and duration values ​​are typically greater than what is required to discharge the DRAM device (600), and the values ​​are calculated in advance according to the design characteristics of the 3D NAND device (700).

[0119] Next, the process of reading data bits from the 3D NAND device (700) will be described in relation to the NMOS portion (501); however, it will be understood that the same process can be used to read data bits within the PMOS portion (502). Since tunneling and hot carrier injection are not required to detect the voltage of the floating NMOS gate (513), reading data bits from the 3D NAND device (700) is similar to reading data bits from the DRAM device (600). To read the charge from the floating NMOS gate (513), the charging circuit applies a zero or floating voltage between the terminals (504 and 505), and then the sensing circuit is applied to the terminals (504 and 505). Next, the NMOS control gate (510) is quickly switched on and off. Since the charging circuit has applied a zero voltage between terminals (504 and 505), when the NMOS control gate (510) is switched on or off, the value of the charge stored in the floating NMOS gate (513) is capacitively coupled to the terminals (504 and 505) and will drive the sensing circuit to high or low depending on whether a 0 or 1 bit is stored in the floating NMOS gate (513). If there is a voltage stored in the floating NMOS gate (513), the sensing circuit detects a bit value of 1 at the terminals (504 and 505). If there is no voltage stored in the floating NMOS gate (513), the sensing circuit detects a bit value of 1 at the terminals (504 and 505).

[0120] It will be understood that multiple 3D NAND elements (700) can be connected in parallel to store a larger amount of data. Once the internal configuration of the 3D NAND elements (700) is complete, they may undergo packaging and wire bonding processes so that they can be embedded in an integrated circuit (IC) of an electronic device. For example, the 3D NAND elements (700) can be packaged and connected to an interactive television, a mobile phone, or a desktop computer. It will be understood that the 3D NAND elements (700) can be integrated into any number of electronic devices without departing from the spirit and scope of the present disclosure.

[0121] The 3D NAND device (700) is particularly suitable for operating as long-term non-volatile memory. For example, because the floating NMOS gate (513) and the floating PMOS gate (523) have complete DC electrical isolation, the 3D NAND device (700) can store data for a long period of time even when the 3D NAND device (700) is turned off. Additionally, although the 3D NAND device (700) takes longer to perform write operations than the DRAM device (600), the 3D NAND device (700) performs read operations as quickly as the DRAM device (600). Therefore, it will be understood that switching both the DRAM device (600) and the NAND device (700) to electronic devices provides the benefits of high-speed write operations and long-term data storage. For example, in a desktop computer, a DRAM element (600) can be used to store application data while the computer is turned on, and a 3D NAND element (700) can be used to store long-term data while the computer is turned off.

[0122] Embodiments of the present invention provide at least the following advantages. The method disclosed herein enables much finer pitch features with up to one significant lithography step. Compared to conventional etching / filling methods, the method of the present invention is much more efficient and much cheaper. This may be partly due to the ability of the present method to execute many steps directly on a coater-developer tool (track tool) instead of switching between etching tools. Such a process may be beneficial for some classes of memory devices. Additionally, since some specific materials do not integrate well through deposition, making high aspect ratio or fine pitch devices impossible, the ability to execute steps directly on a track tool may enable the deposition of unique materials. However, using the present technology, high-density devices can be fabricated quickly and inexpensively. For example, memory devices formed using the method described herein can be integrated into logic chips or used separately. This differs from a single-point mechanism due to the addition of iterative application and integration options.

[0123] Although only a few exemplary embodiments have been described in detail above, those skilled in the art will readily understand that many variations from the exemplary embodiments are possible without substantially departing from the invention. Accordingly, all such variations are intended to be included within the scope of the disclosure as defined in the claims below.

Claims

Claim 1 (a) a step of providing a substrate having an existing pattern, wherein the upper surface of the substrate has features that are not covered and the existing pattern is formed within the first layer such that the first layer is not covered; (b) a step of depositing a selective adhesive on the substrate, wherein the selective adhesive is attached to the features and includes a solubility-converting agent; (c) a step of depositing a first resist on the substrate; (d) a step of activating the solubility-converting agent such that a portion of the first resist on the features becomes soluble in the first developer, or a portion of the first resist on the first layer between the features becomes insoluble in the first developer; (e) a step of developing the first resist using the first developer to form a relief pattern including an opening, wherein the opening exposes features of the existing layer; (f) a step of providing self-aligned selective growth features by performing a selective growth process to grow a selective growth material on the features and within the opening of the relief pattern; (g) a step of removing the first resist; (h) a step of depositing a filled layer on the substrate A micromanufacturing method comprising: a step of providing a charged substrate; and (i) a step of repeating steps (b) to (h) a predetermined number of times to provide a stacked device having a predetermined number of levels. Claim 2 A method according to claim 1, wherein the feature formed within the first layer forms an array. Claim 3 A method according to claim 1 or 2, further comprising the step of planarizing the substrate after depositing a filling layer on the substrate. Claim 4 A method according to claim 1 or 2, further comprising the step of coating a selective growth feature after removing the first photoresist. Claim 5 A method according to claim 1 or 2, wherein the selective adhesive comprises a self-assembled monolayer. Claim 6 A method according to claim 1 or 2, wherein the optional adhesive comprises phosphonic acid, phosphonate ester, phosphine, sulfonic acid, sulfinic acid, carboxylic acid, triazole, thiol, or a combination thereof. Claim 7 A method according to claim 1 or 2, wherein the solubility-converting agent comprises an acid-generating agent. Claim 8 In claim 7, the above acid generating agent does not contain fluorine. Claim 9 The method according to claim 7, wherein the acid generating agent is selected from the group consisting of triphenylsulfonium antimonate, pyridinium perfluorobutanesulfonate, 3-fluoropyridinium perfluorobutanesulfonate, 4-t-butylphenyltetramethylenesulfonium perfluoro-1-butanesulfonate, 4-t-butylphenyltetramethylenesulfonium 2-trifluoromethylbenzenesulfonate, 4-t-butylphenyltetramethylenesulfonium 4,4,5,5,6,6-hexafluorodihydro-4H-1,3,2-dithiazine 1,1,3,3-tetraoxide, and combinations thereof. Claim 10 A method according to claim 1 or 2, wherein the solubility-converting agent comprises an acid. Claim 11 In paragraph 10, the above acid does not contain fluorine. Claim 12 In claim 10, the acid is selected from the group consisting of trifluoromethanesulfonic acid, perfluoro-1-butanesulfonic acid, p-toluenesulfonic acid, 4-dodecylbenzenesulfonic acid, 2,4-dinitrobenzenesulfonic acid, 2-trifluoromethylbenzenesulfonic acid, and combinations thereof. Claim 13 A method according to claim 1 or 2, further comprising the step of pre-treating the substrate before depositing the first resist on the substrate. Claim 14 A method according to claim 1 or 2, wherein the feature comprises a conductive material. Claim 15 A method according to claim 1 or 2, wherein the feature comprises a metal or semimetal selected from the group consisting of silicon, polysilicon, copper, cobalt, tungsten, and combinations thereof. Claim 16 A method according to claim 1 or 2, wherein the base layer comprises a dielectric. Claim 17 A method according to claim 1 or 2, wherein the stacked element is a memory element. Claim 18 In paragraph 17, the above memory element is an MRAM element, method. Claim 19 In claim 17, the method wherein the memory element is a 3D NAND element. Claim 20 In paragraph 17, the above memory device is a DRAM device, method. Claim 21 A step of receiving a substrate having a feature formed within a first layer such that the upper surface of the substrate has an uncovered feature and an uncovered first layer; a step of depositing a first solubility-converter on the substrate, wherein the first solubility-converter is selected to adhere to the uncovered surface of the feature without the first solubility-converter adhering to the uncovered surface of the first layer; a step of depositing a second solubility-converter on the substrate, wherein the second solubility-converter is selected to adhere to the uncovered surface of the first layer without the second solubility-converter adhering to the uncovered surface of the feature; a step of depositing a first photoresist on the substrate; a step of activating the first solubility-converter sufficient to make the first photoresist region on the feature soluble in a specific developer; a step of activating the second solubility-converter so that the second solubility-converter increases the insolubility of the first photoresist on the first layer; a step of developing the first photoresist to generate a relief pattern defining an opening that does not cover the feature; A microfabrication method comprising the step of creating self-aligned selectively deposited features by performing a selective growth process to grow a selectively deposited material within a defined opening of a relief pattern above the feature.

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