Deep trench isolation structure for image sensor narrowed by epitaxy growth

Abstract

The problem of forming deep trench isolation (DTI) structures suitable for photodetectors with narrow pitch is solved by a process in which a p-doped epitaxial layer is grown on the sidewalls of trenches formed by etching. The epitaxial layer becomes part of the active region of any adjacent photodetector and narrows the DTI structure formed by the dielectric within the trenches. The epitaxial layer can be allowed to close the trench mouths and grow on the front side. Subsequently, floating diffusion regions, etc., can be formed directly on the DTI structure. Optionally, dislocations within the epitaxial layer are removed by laser annealing. Optionally, the epitaxial layer is planarized after annealing. The trenches can be accessed from the back side by thinning the substrate, and then the trenches can be partially or completely filled with dielectric to form the DTI structure.

Description

Technology Field

[0001] This application claims priority to U.S. Provisional Application No. 63 / 497,498 filed on April 21, 2023, the contents of which are incorporated herein by reference in their entirety. Background Technology

[0002] Integrated circuits (ICs) containing image sensors are used in various modern electronic devices, such as cameras and mobile phones. Complementary metal-oxide semiconductor (CMOS) image sensors (CIS) are gaining popularity. Compared to charge-coupled devices (CCDs), CIS are becoming increasingly preferred due to their low power consumption, small pixel size, fast data processing, and low manufacturing costs. As pixel sizes shrink, manufacturing becomes increasingly difficult, such as limiting crosstalk between pixels. These are ongoing challenges where unique solutions can provide improved performance. Brief explanation of the drawing

[0003] Aspects of the present disclosure are best understood from the detailed description below when read together with the accompanying drawings. In accordance with standard industrial practice, features are not drawn to scale. Additionally, the dimensions of various features within individual drawings may be increased or decreased relative to one another at will to facilitate explanation or to provide emphasis. FIG. 1a illustrates a cross-sectional view of an image sensing device according to some embodiments. FIG. 1b provides an extended view of the area (1B) of FIG. 1a. Figure 1c is a plan view taken along line C-C' of Figure 1a. FIG. 2a illustrates a cross-sectional view of an image sensing device according to some other embodiments. Figure 2b provides an extended view of the area (2B) of Figure 2a. FIG. 3 illustrates a cross-sectional view of an image detection device according to some other embodiments. FIG. 4a illustrates a cross-sectional view of an image sensing device according to some other embodiments. FIG. 4b provides an extended view of the area (4B) of FIG. 4a. FIG. 5 illustrates a cross-sectional view of an image detection device according to some other embodiments. FIG. 6 illustrates a cross-sectional view of an image detection device according to some other embodiments. FIGS. 7 to 22 illustrate a series of cross-sectional views illustrating a method for forming an image sensing device according to some other embodiments. FIGS. 23 to 26 illustrate variations of the method of FIGS. 7 to 22 according to various other embodiments. FIG. 27 provides a flowchart illustrating some embodiments of a method for forming an image sensing device. Specific details for implementing the invention

[0004] The present disclosure provides many different embodiments or examples for implementing different features of the present disclosure. Specific examples of components and arrangements are described below for the sake of brevity of the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following detailed description, the formation of the first feature on or above the second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features so that the first and second features do not come into direct contact.

[0005] Spatially relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to describe the relationship of one component or feature to another component(s) or feature(s) as illustrated in the drawings. These spatially relative terms are intended to encompass different orientations of the device or apparatus in use or operation in addition to the orientations illustrated in the drawings. The device or apparatus may be oriented differently (rotated 90 degrees or oriented in a different way), and the spatially relative terms used herein may be interpreted accordingly. Terms such as “first,” “second,” “third,” “fourth,” etc. are merely general identifiers and thus may be interchanged in various embodiments. For example, in some embodiments, an element (e.g., an opening) may be referred to as the “first” element, but in other embodiments, that element may be referred to as the “second” element.

[0006] Some CIS are designed for back-side illumination (BSI) and include an array of photodetectors within a semiconductor substrate. The photodetectors may be separated by a deep trench isolation (DTI) structure. The DTI structure may be a back-side deep trench isolation (BDTI) structure, which is an isolation structure in which trenches are formed on the back side of the semiconductor substrate and tend to narrow from the back side to the front side, or a front-side deep trench isolation (FDTI) structure, which is a DTI structure in which trenches are formed on the front side of the semiconductor substrate and tend to narrow from the front side to the back side. The DTI structure may be in the form of a grid having segments between adjacent photodetectors.

[0007] As the photodetector pitch decreases, the DTI structure occupies a progressively larger proportion of the image detection area. To counteract this trend, it is desirable to make the DTI structure narrower. Attempts to make the DTI structure narrower are hindered by the aspect ratio limitations inherent in the trench etching process. Additionally, as the trenches become narrower, they become more susceptible to pinching off during backfill. Pinch-off during backfill can disrupt passivating defects on the trench sidewalls.

[0008] According to some aspects of the present disclosure, the problem of forming a DTI structure suitable for photodetectors having a small pitch is solved by a process in which a layer of a p-doped semiconductor is epitaxially grown on the sidewalls of trenches formed in a semiconductor substrate by etching. The epitaxial layer becomes part of the active region of any adjacent photodetectors and the semiconductor body. The epitaxial layer creates trenches, and accordingly, the DTI structure formed within the trenches becomes narrower than the etched trenches. Any defects on the sidewalls of the etched trenches are passivated by p-type doping. The p-type epitaxial layer also contributes to electrical isolation between adjacent pixels. In some embodiments, the epitaxial layer is grounded. In some embodiments, the epitaxial layer is coupled to a bias source to which a bias voltage can be applied to the epitaxial layer. In some embodiments, the DTI structure is an FDTI structure. FDTI structures are formed before any FEOL (front end of line) structures that may be adversely affected by the process conditions of epitaxial growth.

[0009] The epitaxial growth process may continue until the trench mouths close. Depending on the conditions of the epitaxial growth process, dislocations may form near the trench mouths where the sidewalls of the trenches begin to merge. In some embodiments, these dislocations are removed or improved by annealing. In some embodiments, heat for annealing is provided by laser pulses. Annealing may increase surface roughness. In some embodiments, chemical mechanical polishing (CMP) or the like is applied to reduce surface roughness.

[0010] In some embodiments, the epitaxial layer is formed by a non-selective growth process such that the p-doped epitaxial layer extends onto the front side of the semiconductor substrate. In some embodiments, the front side epitaxial layer is incorporated within photodetector structures. In some embodiments, a floating diffusion region having n-type doping is formed within the p-doped front side epitaxial layer. In some embodiments, the p-doped front side epitaxial layer provides a channel for a transfer gate. In some embodiments, the transfer gate is a vertical transfer gate comprising an electrode extending through the p-doped front side epitaxial layer.

[0011] In some embodiments, after forming the FDTI structure and photodetectors, the semiconductor substrate undergoes a back-end-of-line (BEOL) process to form a metal interconnect structure on the front side. A bonding layer may be formed on the metal interconnect structure, thereby allowing the semiconductor substrate to be bonded to a second substrate. Subsequently, the semiconductor substrate may be thinned from the back side. In some embodiments, the thinning process opens trenches from the back side and a dielectric is deposited within the trenches from the back side. The dielectric provides the DTI structure. In some embodiments, the dielectric fills the trenches. In some embodiments, depositing the dielectric from the back side seals the trenches while leaving void regions within the trenches.

[0012] Some aspects of the present disclosure relate to an image sensing device of a type that can be manufactured by the process described above. The semiconductor device comprises a semiconductor substrate having a photodetector array. The semiconductor substrate has sidewalls defining trenches between adjacent photodetectors within the array. The trenches comprise a dielectric of a DTI structure. The sidewalls are provided by an epitaxial layer of a p-doped semiconductor. In some embodiments, the trenches narrow when approaching the front side of the semiconductor substrate, narrow when approaching the rear side of the semiconductor substrate, and are widest between the top and bottom of the trenches. The trenches may narrow when approaching the rear side due to the narrowing of the original trenches etched into the semiconductor substrate from the front side. The trenches may narrow when approaching the front side because the epitaxial layer is formed thicker as it approaches the front side. The trenches are narrower than the trenches formed by etching. In some embodiments, trenches having sidewalls provided by an epitaxial layer have an aspect ratio of about 50:1 or greater.

[0013] FIG. 1a illustrates a cross-sectional view of an image sensing device (100) according to some embodiments. The image sensing device (100) comprises an array of photodetectors (125) within a semiconductor body (101). The semiconductor body (101) has a front side (104) and a rear side (102) and is a composite of an epitaxial layer (114) of a p-doped semiconductor and a bulk semiconductor (112). The epitaxial layer (114) extends into trenches defined by sidewalls (129) of the bulk semiconductor (112). A DTI structure (123) is disposed between the sidewalls (127) provided by the epitaxial layer (114). The DTI structure (123) includes an isolating dielectric (145) and may have voids (149). The voids (149) may have sidewalls (147) provided by the isolation dielectric (145).

[0014] The isolation dielectric (145) may continue on the rear side (102). On the rear side (102), the isolation dielectric (145) may provide an anti-reflective coating. Alternatively, the anti-reflective coating may be provided as a separate layer. A microlens (137) may be positioned to focus light entering the photodetectors (125). A color filter (135) may be positioned between the microlens (137) and the isolation dielectric (145).

[0015] The photodetectors (125) include image sensing elements such as photodiodes (121). Various n-type and p-type dopant injection processes may have been performed to provide regions of n-type doping and p-type doping constituting the photodiodes (121). Nevertheless, in some embodiments, the photodiodes (121) include a PN junction formed between an adjacent region of the bulk semiconductor (112) having n-type doping and an epitaxial layer (114).

[0016] A front-side metal interconnect structure (103) may be disposed on the front side (104) of a semiconductor body (101). The front-side metal interconnect structure (103) may include wires (173) arranged in a stack of metallization layers. Wires (173) within adjacent metallization layers may be connected by vias (169). The wires (173) and vias (169) may be surrounded by an inter-level dielectric (171).

[0017] The image sensing device (100) may be designed for rear illumination. Accordingly, the semiconductor body (101) may be attached to a second substrate (181) that is relatively thin and provides mechanical support. The semiconductor device (179) may be formed on the second substrate (181) so that the second substrate (181) provides additional functionality. In some embodiments, the additional functionality includes providing logic circuits. In some embodiments, the additional functionality includes providing transistors associated with a photodiode (121). These transistors may include, for example, select gates, reset gates, etc.

[0018] A second metal interconnect structure (105) may be disposed on a second substrate (181). The semiconductor body (101) and the second substrate (181) may be bonded together through a first bonding layer (175) on the front metal interconnect structure (103) and a second bonding layer (177) on the second metal interconnect structure (105). Electrical connections between the front metal interconnect structure (103) and the second metal interconnect structure (105) may be provided by first bond pads (151) in the first bonding layer (175) and second bond pads (153) in the second bonding layer (177).

[0019] In some embodiments, the epitaxial layer (114) continues onto the front side (106) of the bulk semiconductor (112) to provide a front-side epitaxial layer (165). In some embodiments, floating diffusion regions (111) are provided by high-concentration n-doped wells disposed within the front-side epitaxial layer (165). In some embodiments, the transfer gates (115) include vertical gate electrodes (117) extending through the front-side epitaxial layer (165). The floating diffusion region (111) may have doping aligned with spacers (113) adjacent to the vertical gate electrodes (117).

[0020] The DTI structure (123) provides isolation between adjacent photodetectors (125) together with the epitaxial layer (114). In some embodiments, this isolation is enhanced by grounding the epitaxial layer (114) or by applying a bias voltage to the epitaxial layer (114). The epitaxial layer (114) may be connected to ground or a bias voltage source (not shown) through the front metal interconnect structure (103). In some embodiments, high-concentration p-doped contact regions (167) are formed on the front side (104) to facilitate this connection.

[0021] FIG. 1b is an enlarged view of the area (1B) in FIG. 1a focusing on the structure of the DTI structure (123) and the semiconductor body (101). The DTI structure (123) is theoretically bounded by the sidewalls (127) of the epitaxial layer (114). The epitaxial layer (114) is disposed within trenches defined by the sidewalls (129) of the bulk semiconductor (112). The trenches defined by the sidewalls (129) have a width (W5) on the front side (106) of the bulk semiconductor (112). In some embodiments, the width (W5) is in the range of about 120 nm to about 300 nm. In some embodiments, the width (W5) is in the range of about 160 nm to about 200 nm. In some embodiments, the trenches defined by the sidewalls (129) are reduced in width from the width (W5) at the front side (106) of the bulk semiconductor (112) to the width (W1) at the rear side (102). The width is reduced due to a process of etching the trenches within the bulk semiconductor (112) from the front side (106). In some embodiments, the width (W1) is about 10 percent to about 80 percent of the width (W5). In some embodiments, the width (W1) is about 20 percent to about 60 percent of the width (W5).

[0022] The DTI structure (123) has a maximum width (W3) occurring at an intermediate position between the front side (106) and the rear side (102) of the bulk semiconductor (112). In some embodiments, the width (W3) is about 100 nm or less. In some embodiments, the width (W3) is about 60 nm or less. In some embodiments, the width (W3) is within the range of about 30 nm to about 50 nm. These widths are related to the DTI structure (123) being narrow enough to maintain a large overall well capacity and wide enough to suppress crosstalk.

[0023] In the first zone (191) located near the rear side (102) and above the intermediate position where the maximum width (W3) occurs, the epitaxial layer (114) has a roughly constant thickness (T2). The thickness (T2) gradually decreases in the direction of the rear side (102) to the extent that it varies in the first zone (191). In some embodiments, the thickness (T2) is in the range of about 30 nm to about 100 nm. In some embodiments, the thickness (T2) is in the range of about 40 nm to about 60 nm.

[0024] The width of the DTI structure (123) gradually decreases through the first section (191) until it reaches the width (W2) at the back (102). This decrease in the width of the DTI structure (123) is related to the decrease in the width of the trenches defined by the side walls (129) of the bulk semiconductor (112). In some embodiments, the width (W2) at the back (102) is about 20% to about 80% of the maximum width (W3). In some embodiments, the width (W2) at the back (102) is about 50% to about 70% of the maximum width (W3), e.g., about 60%.

[0025] In a second zone (193) located near the front side (104) and below the intermediate position where the maximum width (W3) occurs, the DTI structure (123) gradually decreases over the width (W4). The width (W4) may occur at a depth corresponding to the voids (149). In some embodiments, the width decreases over the second zone (193) because the epitaxial layer (114) thickens as it approaches the front side (106) of the bulk semiconductor (112). In some embodiments, the width (W4) is about 20 percent to about 80 percent of the maximum width (W3).

[0026] The DTI structure (123) terminates at a distance (D1) from the front side (106) of the bulk semiconductor (112). The DTI structure (123) has a height (H1) that is smaller than the thickness (T1) of the bulk semiconductor (112) by the distance (D1). In some embodiments, the height (H1) is in the range of about 30 μm to about 50 μm. In some embodiments, the height (H1) is in the range of about 1.5 μm to about 2 μm. The ratio of the height (H1) to the width (W3) is the aspect ratio of the DTI structure (123). In some embodiments, the aspect ratio is greater than about 30:1. In some embodiments, the aspect ratio is in the range of about 50:1 to about 100:1.

[0027] The epitaxial layer (114) continues onto the front side (106) of the bulk semiconductor (112) to provide a front epitaxial layer (165). In some embodiments, the thickness (T3) of the front epitaxial layer (165) is in the range of about 50 nm to about 200 nm. In some embodiments, the thickness (T3) is in the range of about 80 nm to about 150 nm. Providing a suitable thickness for the front epitaxial layer (165) facilitates the formation of devices related to photodetectors (125) within the front epitaxial layer (165).

[0028] Having a DTI structure (123) resized by a distance (D1) below the front side (106) of a bulk semiconductor (112) makes it easier to form semiconductor devices on the front side (104), and in particular makes it easier to form floating diffusion regions (111) immediately below the DTI structure (123). In some embodiments, the distance (D1) is in the range of about 30 nm to about 200 nm. In some embodiments, the distance (D1) is in the range of about 50 nm to about 150 nm.

[0029] The combined distance (D1) and thickness (T3) are sufficiently large to accommodate floating diffusion regions (111) and sufficiently small for dislocations that may result from the epitaxial growth process, so that they are preferably repaired by a laser annealing process. Accordingly, in some embodiments, the combined distance (D1) and thickness (T1) are within the range of about 100 nm to about 300 nm. In some embodiments, the combined distance (D1) and thickness (T1) are within the range of about 150 nm to about 220 nm.

[0030] FIG. 1c provides a top view of an image detection device (100) taken along line C-C' of FIG. 1a. As illustrated in FIG. 1c, trenches defined by the sidewalls (127) of the DTI structure (123) and the epitaxial layer (114) each form a grid having segments that laterally surround and isolate photodetectors (125). Floating diffusion regions (111) that can be shared by up to four photodetectors (125) are located directly above the DTI structure (123) at the intersection between these segments. High-concentration p-doped contact regions (167) to which the epitaxial layer (114) can be grounded may also be located directly above the DTI structure (123) at the intersection between these segments. The photodetectors (125) form an array that may have a small pitch (P1). In some embodiments, the pitch (P1) is in the range of about 0.2 μm to about 0.4 μm. In some embodiments, the pitch (P1) is about 0.3 μm or less. In some embodiments, the pitch (P1) is about 0.25 μm or less.

[0031] FIG. 2a illustrates a cross-sectional view of an image sensing device (200) according to some other embodiments. FIG. 2b is an enlarged view of FIG. 2a with a focus on region (2B). The image sensing device (200) is similar to the image sensing device (100) of FIG. 1a except that the trenches defined by the sidewalls (129) of the bulk semiconductor in the image sensing device (200) have a maximum width (W6) (see FIG. 2b) at a distance (D2) from the front side (106). The trenches defined by the sidewalls (129) of the bulk semiconductor (112) narrow between the point where the maximum width (W6) occurs and the front side (106). This narrowing facilitates the merging of the epitaxial layer (114) at a distance (D1) from the front side (106). If the distance (D1) is kept large, it is easy to form a floating diffusion area (111) directly below the DTI structure (123).

[0032] FIG. 3 illustrates a cross-sectional view of an image sensing device (300) according to some other embodiments. The image sensing device (300) is similar to the image sensing device (100) of FIG. 1a and FIG. 1b except that the DTI structure (123) in the image sensing device (300) has no voids (149) (see FIG. 1a). In the image sensing device (300), the isolation dielectric (145) of the DTI structure (123) fills trenches defined by the sidewalls (127) of the epitaxial layer (114).

[0033] FIG. 4a illustrates a cross-sectional view of an image sensing device (400) according to some other embodiments. FIG. 4b is an enlarged view of FIG. 4a with a focus on region (4B). The image sensing device (400) is similar to the image sensing device (300) of FIG. 3 except that the trenches defined by the sidewalls (129) of the bulk semiconductor (112) in the image sensing device (400) have substantially constant widths. The DTI structure (123) of the image sensing device (400) does not have a bulge in the middle and has a width that increases or remains constant as the DTI structure (123) approaches the rear side (102). This configuration increases the width (W2) of the DTI structure (123) at the rear side (102) but makes it easier to form the DTI structure (123) without a gap (149) (see FIG. 1a).

[0034] FIG. 5 illustrates a cross-sectional view of an image sensing device (500) according to some other embodiments. The image sensing device (500) is similar in many respects to the image sensing device (200) of FIG. 2a and FIG. 2b, except that the epitaxial layer (114) in the image sensing device (500) does not extend onto the front side (106) of the bulk semiconductor (112). The p-doped layer (501) on the front side (104) can provide the functionality of the front epitaxial layer (165) (see FIG. 2a).

[0035] FIG. 6 illustrates a cross-sectional view of an image sensing device (600) according to some other embodiments. The image sensing device (600) is similar to the image sensing device (500) of FIG. 5 except that the floating diffusion region (111) in the image sensing device (500) is laterally offset from the DTI structure (123). Without the front epitaxial layer (165), it may be difficult to form the floating diffusion regions (111) directly below the DTI structure (123).

[0036] FIGS. 7 through 22 provide a series of cross-sectional views (700-2200) illustrating an image sensing integrated circuit device according to the present disclosure at various manufacturing stages according to the process of the present disclosure. Although FIGS. 7 through 22 are described in relation to a series of operations, it should be noted that the order of operations may be changed in some cases and that this series of operations may be applicable to structures other than the structure illustrated. In some embodiments, some of these operations may be omitted in whole or in part. Also, although FIGS. 7 through 22 are described in relation to a series of operations, it should be noted that the structure disclosed in FIGS. 7 through 22 is not limited to the manufacturing method but may instead be constructed independently as a structure separate from the method.

[0037] As illustrated by the cross-sectional view (700) of FIG. 7, the method may begin by providing a bulk semiconductor (112) and injecting an n-type dopant (703) to form a deep n-well (701). The bulk semiconductor (112) may be formed as a single crystal and may be any type of semiconductor, such as silicon (Si), a III-V or some other binary semiconductor, a ternary semiconductor (e.g., AlGaAs), a higher-order semiconductor, etc. In some embodiments, the bulk semiconductor (112) is silicon (Si), etc. or comprises it.

[0038] In some embodiments, the injection process is blanket injection performed without a mask so that a deep n-well (701) extends across the bulk semiconductor (112). In some embodiments, n-type dopants (703) are injected at an energy in the range of about 2000 keV to about 10,000 keV. In some embodiments, n-type dopants (703) are injected at an energy in the range of about 3000 keV to about 6000 keV. In some embodiments, n-type dopants (703) are about 1 × 10⁻⁶ 10 to about 1 × 10 13atoms / cm 2 It is injected in an injection amount within the range. In some embodiments, the deep n-well (701) has a peak dopant concentration of about 2 μm to about 5 μm below the front side (106). The deep n-well (701) may have a depth such that it extends to the rear side (102) (see FIG. 1a) after the bulk semiconductor (112) is thinned. Other dopant injection processes related to the formation of photodiodes (121) (see FIG. 1a), for example, containing shallower n-well implants, may also be performed at this stage of processing with or without a mask.

[0039] As illustrated by the cross-sectional view (800) of FIG. 8, a mask (801) is formed and can be used to etch trenches (803) within the bulk semiconductor (112). The trenches (803) can be etched by any suitable process. In some embodiments, the etching process is dry etching. In some embodiments, the etching process includes a deep reactive ion etching (DRIE) process, etc. In some embodiments, the etching process includes alternating steps of forming a passivation layer that limits exposure to reactive ions and lateral etching. The trenches (803) have a maximum width (W5) at or near the front side (106). The sidewalls (129) may be angled so that the trenches (803) decrease in width while increasing in depth to a width (W1). Maintaining the sidewalls (129) nearly vertical is desirable in terms of keeping the DTI structure (123) (see FIG. 1a) narrow, but it is difficult to increase the verticality of the sidewalls (129) without increasing the energy of the ions used in the etching process. Increasing the energy of the ions increases damage to the bulk semiconductor (112), which can result in dark currents, white pixels, etc. Therefore, in some embodiments, lower energy etching is used. The greater the angle of the sidewalls (129), the lower energy etching is reflected. In some embodiments, the sidewalls (129) are angled so that the width (W1) is 60% or less of the width (W5). In some embodiments, the sidewalls (129) are angled so that the width (W1) is 50% or less of the width (W5).

[0040] The trenches (803) have a depth (D3). In some embodiments, the depth (D3) is in the range of about 1.5 μm to about 5 μm. In some embodiments, the depth (D3) is in the range of about 2 μm to about 3 μm. In some embodiments, the trenches (803) have an aspect ratio in the range of about 10:1 to about 20:20. In some embodiments, the aspect ratio is in the range of about 13:1 to about 16:1.

[0041] As illustrated by the cross-sectional view (900) of FIG. 9, the mask (801) can be removed, and the epitaxial layer (114) can be grown within the trenches (803) and on the front side (106). The epitaxial layer (114) can be any suitable semiconductor. In some embodiments, the epitaxial layer (114) is silicon having p-type doping, etc. The p-type dopant can be boron (B), arsenic (As), etc. The epitaxial layer (114) is combined with the bulk semiconductor (112) to form the front side (104) and the semiconductor body (101).

[0042] Conditions for the epitaxial growth process may include, for example, a temperature in the range of about 700 °C to about 1000 °C and a pressure in the range of about 10 to about 500 torr. The semiconductor source may be a hydride, such as trichlorosilane (TCS), dichlorosilane (DCS), silane (SiH4), etc., or some other suitable gas. The dopant source may also be a hydride, such as diborane (B2H6), arsine (AsH3), etc., or some other suitable gas. In some embodiments, the epitaxial layer (114) is about 1 × 10⁻⁶ 15 to about 1 × 10 18 atoms / cm 3 It is formed with a dopant concentration in the range of. In some embodiments, the epitaxial layer (114) is about 1 × 10 15 to about 2 × 10 15 atoms / cm 3It is formed with a dopant concentration in the range of. In some embodiments, the epitaxial layer (114) is formed with a resistivity in the range of about 0.1 to about 100 Ohm-cm. In some embodiments, the epitaxial layer (114) is formed with a resistivity in the range of about 8 to about 12 Ohm-cm.

[0043] Film formation conditions are selected such that the trenches (803) are closed near their entrances. This closure is desirable in that it increases the substrate area on the front side (104) where semiconductor devices can be formed. Closure near the entrances of the trenches (803) is also desirable in that it leaves the voids (149) to be lined with or filled with a dielectric in a subsequent stage of processing. In some embodiments, the epitaxial growth process continues beyond this point of closure to increase the thickness of the front epitaxial layer (165). In some embodiments, the trenches (803) are closed within 40 nm to 100 nm of the epitaxial growth. In some embodiments, after the trenches (803) are closed, epitaxial growth continues to increase the thickness of the front epitaxial layer (165) by an amount ranging from about 50 nm to about 200 nm.

[0044] In some embodiments, dislocations (901) are formed at which growth from the opposing sidewalls (129) of the trenches (803) begins to merge. It is desirable to maintain these dislocations at a distance (T4) on the front side (104) so ​​that these dislocations can be recovered by a laser annealing process or the like. In some embodiments, the distance (T4) is in the range of about 100 nm to about 400 nm. In some embodiments, the distance (T4) is in the range of about 200 nm to about 300 nm.

[0045] FIGS. 10 and 11 illustrate processing that may be used to remove or improve dislocations (901). In some embodiments, dislocations (901) are avoided by appropriate selection of conditions for the epitaxial growth process, or dislocations (901) are removed when they are formed during the epitaxial growth process. For example, temperature cycling may be performed in conjunction with the epitaxial growth process to provide in-situ annealing. Thus, the processing of FIGS. 10 and 11 is optional.

[0046] As illustrated by the cross-sectional view (1000) of FIG. 10, an annealing process may be performed to remove dislocations (901). The annealing process may be rapid thermal annealing (RAT), furnace annealing, or laser annealing. In some embodiments, the annealing process is to selectively heat the upper layer of the semiconductor body (101). In some embodiments, the annealing process is laser annealing, etc. In some embodiments, annealing is performed with pulsed ultraviolet laser light (1003) that may be provided by an excimer laser. For example, the annealing process may be performed with a 248 nm wavelength KrF excimer laser, etc. In some embodiments, the laser pulses are about 2 ns to about 100 ns, e.g., about 24 ns. In some embodiments, the laser light intensity is about 400 to about 1000 mJ / cm² 2 It is within the range. In some embodiments, the intensity is at least about 700 mJ / cm² 2 The annealing process can roughen the surface on the front side (104).

[0047] As illustrated by the cross-sectional view (1100) of FIG. 11, a planarization process may be performed to smooth the surface on the front side (104). The planarization process may be CMP or some other suitable process. In some embodiments, the CMP process reduces the thickness of the front side epitaxial layer (165) by an amount ranging from about 20 nm to about 100 nm, for example, about 50 nm.

[0048] As illustrated by the cross-sectional view (1200) of FIG. 12a, additional doping may be performed to complete the formation of photodiodes (121) and optionally shallow p-wells (163) (see FIG. 1). The doping process may include masks (not shown). In some embodiments, at least a portion of the PN junction of the photodiodes (121), particularly the portion furthest from the front side (104), has P-doping provided by the epitaxial layer (114). The p-type dopants may remain within the epitaxial layer (114) or diffuse slightly into the bulk semiconductor (112).

[0049] FIG. 12b is an enlarged view of the region (12B) in FIG. 12a, focusing on the PN junction (1203) formed between the p-type dopants of the epitaxial layer (114) and the region of the bulk semiconductor (112) having n-type doping. As illustrated, the bulk semiconductor (112) may have a p-doped region (1201) as a result of the diffusion of p-type dopants from the epitaxial layer (114). When p-type doping is provided exclusively by the epitaxial layer (114), the width (W7) of the region between the sidewall (127) and the PN junction (1203) is kept narrow. Keeping the width (W7) small increases the overall well capacity of the resulting photodiodes (121) (see FIG. 1a). In some embodiments, the thickness (W7) is in the range of about 30 nm to about 110 nm. In some embodiments, the thickness (W7) is about 80 nm or less.

[0050] As illustrated by the cross-sectional view (1300) of FIG. 13, a mask (1301) is formed and can be used to etch trenches (1303) on the front side (104). The trenches (1303) penetrate the front side epitaxial layer (165) and extend into the bulk semiconductor (112). After the etching process, the etching mask (1301) is stripped.

[0051] As illustrated in the cross-sectional view (1400) of FIG. 14, a gate stack (1401) is formed to fill the trenches (1303) after lining them. The gate stack (1401) includes a gate dielectric layer and a gate electrode layer. The gate dielectric layer may be an oxide, a high-k dielectric, etc., or may include the same. The gate dielectric layer may be formed by oxidation, film deposition, etc. The gate electrode layer may be polysilicon, a metal, etc., and is formed by film deposition. The film deposition processes may be atomic layer deposition (ALD), chemical vapor deposition (CVD), or physical vapor deposition (PVD), or may include the same.

[0052] As illustrated by the cross-sectional view (1500) of FIG. 15, a mask (1501) may be formed and used to pattern the gate stack (1401) to define transfer gates (115), etc. As illustrated by the cross-sectional view (1600) of FIG. 16, the mask (1501) may be stripped and spacers (113) may be formed. The spacers (113) may comprise one or more layers of oxides, nitrides, oxycarbides, oxynitrides, etc., or any other suitable material. The spacers (113) may be formed by etching following the deposition of the spacer material.

[0053] As illustrated by the cross-sectional view (1700) of FIG. 17, high-concentration p-doped contact regions (167) and floating diffusion regions (111) may be formed. These regions may be formed by masking and ion implantation. Ion implantation for the floating diffusion regions (111) is at least partially masked by spacers (113) so that the floating diffusion regions (111) have sides aligned with the spacers (113). In some embodiments, the floating diffusion regions (111) are formed directly over trenches defined by sidewalls (129) and lined with an epitaxial layer (114) (see FIG. 1c). In some embodiments, the floating diffusion regions (111) are formed within the front epitaxial layer (165). In some embodiments, high-concentration p-doped contact regions (167) are formed directly above trenches defined by sidewalls (129) and lined with an epitaxial layer (114). In some embodiments, high-concentration p-doped contact regions (167) are formed within a front epitaxial layer (165). This process completes the formation of photodetectors (125) within the semiconductor body (101).

[0054] As illustrated by the cross-sectional view (1800) of FIG. 18, a front metal interconnect structure (103) and a first bonding layer (175) may be formed on the front side (104). These structures may be formed by damascene processes, etc. (e.g., a single damascene process or a dual damascene process). A damascene process may include the steps of forming a layer of inter-level dielectric (171), etching the layer to form via holes and / or trenches, and filling the via holes and / or trenches with a conductive material to form wires (173) or vias (169). The inter-level dielectric layers (171) may be formed by ALD, CVD, PVD, etc., or any other suitable process. The conductive material may be deposited by ALD, CVD, PVD, electroplating, electroless plating, etc., or any other suitable process. The inter-level dielectric (171) may be silicon dioxide (SiO2), a low-k dielectric, etc. The conductive material may be tungsten, copper, aluminum, etc. or may include these. The first bonding layer (175) may be formed by a similar processing.

[0055] As illustrated in the cross-sectional view (1900) of FIG. 19, the semiconductor body (101) can be inverted and bonded to a second substrate (181). A second metal interconnect structure (105) and a second bonding layer (177) can be placed on the second substrate (181). In some embodiments, the second substrate (181) is a support substrate or a handle substrate. In some embodiments, the second substrate (181) comprises a semiconductor material such as silicon, and semiconductor devices (179), such as transistors, are formed on the second substrate (181). The semiconductor body (101) can be bonded to the second substrate (181) through a first bonding layer (175) and a second bonding layer (177). The bonding process may be a hybrid bonding process, or some other suitable bonding process. In some embodiments, the first bonding layer (175) and the second bonding layer (177) form electrical connections between the semiconductor body (101) and the second substrate (181).

[0056] As illustrated by the cross-sectional view (2000) of FIG. 20, after bonding, the semiconductor body (101) can be thinned from the rear side (102). Thinning the semiconductor body (101) allows light to pass more easily to the photodetectors (125). In some embodiments, the thinning process forms openings (2001) within trenches defined by the sidewalls (127). The semiconductor body (101) can be thinned by etching, mechanical grinding, CMP, etc., or any other suitable process. In some embodiments, the semiconductor body (101) is thinned to less than about 5 μm. In some embodiments, the semiconductor body (101) is thinned to about 3 μm or less.

[0057] As illustrated by the cross-sectional view (2100) of FIG. 21, the isolation dielectric (145) may be deposited to line the sidewalls (127) provided by the epitaxial layer (114). The isolation dielectric (145) may also be deposited on the rear side (102). The isolation feature (145) may comprise one or more layers of suitable dielectrics. In some embodiments, at least the base layer of the isolation dielectric (145) is a high-k dielectric deposited by a conformal deposition process such as ALD. Examples of suitable high-k dielectrics include hafnium oxide (HfO), aluminum oxide (AlO), zirconium oxide (ZrO), titanium oxide (TiO), strontium oxide (SrO), barium oxide (BaO), barium titanate (BaTiO3), tantalum oxide (Ta2O3), lanthanum oxide (La2O3), yttrium oxide (Y2O3), etc. In some embodiments, the base layer is hafnium oxide (HfO), aluminum oxide (AlO), etc. Additional layers may be deposited by nonconformal deposition processes so that the isolation dielectric (145) is thicker on the rear side (102) than on the sidewalls (127). The deposition processes may include ALD, PVD, CVD, etc., or any other suitable process. In some embodiments, the additional layers include tantalum oxide (Ta2O3), etc. In some embodiments, the total thickness of the isolation dielectric (145) on the sidewalls (127) is in the range of about 10 nm to about 100 nm.

[0058] In some embodiments, the total thickness of the isolation dielectric (145) on the rear side (102) is within the range of about 50 nm to about 500 nm when the openings (2001) are sealed. In some embodiments, the openings (2001) are sealed, and the voids (149) remain. Additional layers may be added to the isolation dielectric (145). These additional layers may include, for example, layers of silicon dioxide (SiO2). In some embodiments, a layer of tantalum oxide, etc., is formed on the rear side (102) before any silicon dioxide layers. Tantalum oxide has a refractive index intermediate between silicon dioxide and silicon. Having tantalum oxide or a layer between any silicon dioxide layers formed on the bulk semiconductor (112) and the rear side (102) can reduce reflections.

[0059] As illustrated by the cross-sectional view (2200) of FIG. 22, an additional layer (2201) may be added to the isolation dielectric (145) and a rear metal grid (133) may be formed. The rear metal grid (133) may be formed by etching trenches within the additional layer (2201) and filling the trenches with metal. The rear metal grid (133) may reduce crosstalk between adjacent photodetectors (125). Color filters (135) and microlenses (137) may be formed on the structure illustrated by the cross-sectional view (2200) of FIG. 22 to create the image sensing device (100) of FIG. 1a.

[0060] The cross-sectional view (2300) of FIG. 23 illustrates a variation of the aforementioned process that can be used to produce the image sensing device (200) of FIG. 2a. The variation relates to a shift from the etching process used to form trenches (803) as illustrated in the cross-sectional view (800) of FIG. 8. The shift results in trenches (2303), which have a maximum width (W6) at a predetermined distance below the front side (106). Variations in process conditions may relate to the power and pressure of the DRIE process, particularly the portion forming the upper portions of the trenches (2303). The etching power may be kept relatively low. In some embodiments, the etching power is sufficiently low so that the etching rate is kept below 2 μm / min. In some embodiments, the etching power is sufficiently low so that the etching rate is about 1 μm / min or less. The pressure may also be kept relatively low. In some embodiments, the pressure is in the range of about 1 to about 100 millitors. In some embodiments, the pressure is in the range of about 3 to about 30 millitors. In some embodiments, the pressure is in the range of about 5 to about 20 millitors. Varying the power and pressure controls the shape of the trenches (2303). After the trenches (2303) are formed, the process may continue as illustrated and described in relation to the cross-sectional views (900-2200) of FIG. 9 through 22 to create the image sensing device (200) of FIG. 2a.

[0061] The cross-sectional view (2400) of FIG. 24 illustrates a different variation of the process of FIG. 7 through FIG. 22 that can be used to create the image sensing device (400) of FIG. 4a. The variation also relates to a change from the etching process used to form the trenches (803) shown in the cross-sectional view (800) of FIG. 8. In this variation, the etching power is increased to provide the trenches (2403). The sidewalls (129) of the trenches (2403) are substantially vertical. After the trenches (2403) are formed, the process can continue as illustrated and described in relation to the cross-sectional views (900-2200) of FIG. 9 through FIG. 22 to create the image sensing device (400) of FIG. 4a.

[0062] The cross-sectional view (2500) of FIG. 25 illustrates a variation of the process of FIG. 7 through FIG. 22 that can be used to create the image sensing device (300) of FIG. 3. The variation relates to a change in the process used to deposit the isolation dielectric (145) within the openings (2001) (see FIG. 20). The change causes the isolation dielectric (145) to fill the trenches defined by the sidewalls (127) of the epitaxial layer (114), so that the DTI structure (123) is formed without voids (149) (see FIG. 20). In some embodiments, the process of depositing the isolation dielectric (145) to form the DTI structure (123) without voids includes a fluid CVD process. In some embodiments, the first part of the deposition process is ALD, etc., and the last part of the deposition process is fluid CVD. In some embodiments, all isolation dielectrics (145) forming the DTI structure (123) are deposited by a fluid CVD process. Fluid CVD processes include the steps of applying a liquid to the back side (102), allowing the liquid to flow into the gaps with the semiconductor body (101), and curing the liquid to solidify it to create a gap-filling dielectric that is substantially free of voids. Dielectrics that can be deposited by a fluid CVD process include, without limitation, silicon dioxide (SiO2), silicon nitride (Si3N4), aluminum oxide (Al2O3), hafnium oxide (HfO2), etc. Forming trenches (2403) as illustrated by the cross-sectional view (2400) of FIG. 24 facilitates the formation of the DTI structure (123) without voids (149) (see FIG. 20), regardless of which process is used to deposit the isolation dielectric (145).

[0063] The cross-sectional view (2600) of FIG. 26 illustrates a variation of the process of FIG. 7 through FIG. 22 that can be used to create the image sensing device (500) of FIG. 5. The variation relates to a difference in the way the epitaxial layer (114) is formed. In the process illustrated by the cross-sectional view (900) of FIG. 9, the epitaxial layer (114) is grown by a non-selective growth process, that is, a process without a mask on the front side (106) so that the front epitaxial layer (165) is created. The process illustrated by the cross-sectional view (2600) of FIG. 26 is a selective epitaxial growth process, that is, a process in which the epitaxial layer (114) is grown while the mask (801) remains on the front side (106) to prevent the formation of the front epitaxial layer (165). Processing may continue through an additional doping step to create a p-doped layer (501) on the front side (106) (see FIG. 5), as illustrated in the cross-sectional views (1000-2200) of FIG. 10 to 22.

[0064] FIG. 27 provides a flowchart for a method (2700) for forming an image sensing device according to some embodiments. Although the method (2700) is illustrated and described below as a series of actions or events, it will be understood that the illustrated order of these actions or events should not be interpreted as limiting. For example, some actions may occur in a different order than those illustrated or described herein, and / or may occur concurrently with other actions or events. Furthermore, not all of the illustrated actions may be required to implement one or more aspects or embodiments of the description herein. Furthermore, one or more of the actions illustrated herein may be performed as one or more separate actions and / or steps.

[0065] The method (2700) may begin with an operation (2701) of performing one or more dopant injections. In some embodiments, at least one of these dopant injections is a blanket injection of n-type dopants as illustrated by the cross-sectional view (700) of FIG. 7. This doping may provide n-type regions that later combine with a p-type semiconductor grown epitaxially to form PN junctions for a photodiode having narrow regions of p-type doping as illustrated in FIG. 12b.

[0066] Operation (2703) is to form trenches within a semiconductor substrate. In some embodiments, these trenches are formed with relatively low energy, so that the trenches have inclined sidewalls but relatively low substrate damage. The cross-sectional view of FIG. 8 provides an example. In some embodiments, these trenches are formed by higher energy etching. Higher energy etching causes more substrate damage but creates more vertical sidewalls. The cross-sectional view of FIG. 24 provides an example. In some embodiments, these trenches are formed by a process that causes the trenches to widen under the trench mouths. The cross-sectional view of FIG. 23 provides an example.

[0067] Operation (2705) is to grow an epitaxial layer of a p-doped semiconductor on the trench sidewalls. The p-doped epitaxial layer reduces the aspect ratio of the trenches. In some embodiments, the p-doped epitaxial layer is formed by a non-selective growth process. The cross-sectional view of FIG. 9 provides an example. In some embodiments, the p-doped epitaxial layer is formed by a selective growth process. The cross-sectional view of FIG. 26 provides an example. In some embodiments, the epitaxial growth seals the trench mice. In some embodiments, dislocations are formed where the epitaxial growths from both sides of the trenches meet.

[0068] Operation (2707) is an optional step that may be performed if the formation of dislocations during the epitaxial growth process is not avoided or improved. Operation (2707) is annealing. In some embodiments, the annealing process is laser annealing. The cross-sectional view of FIG. 10 provides an example.

[0069] Operation (2709) is an optional step of planarizing the epitaxial growth on the front side of the substrate. Planarization can be used to remove surface roughness caused by the annealing process or to remove only the surface roughness left by the epitaxial growth process. The cross-sectional view of FIG. 11 provides an example.

[0070] Operation (2711) is shallow well doping. This doping can complete the formation of photodiodes. In some embodiments, this step involves the formation of shallow p-wells within the front epitaxial layer created by the epitaxial growth process of operation (2705). The cross-sectional view (1200) of FIG. 12a provides an example. In some embodiments, these shallow p-wells facilitate the formation of contacts for grounding the epitaxial layer. In some embodiments, these shallow p-wells provide isolation for floating diffusion regions to be formed later.

[0071] Operation (2713) is to form front-side photodetector components. These components may include, for example, transfer gates and floating diffusion regions. The cross-sectional views (1300-1700) of FIGS. 13 through 17 provide examples.

[0072] Operation (2715) is to form a metal interconnect structure on the front side. The cross-sectional view (1800) of FIG. 18 provides an example. Operation (2717) is to bond to a separate substrate. The cross-sectional view (1900) of FIG. 19 provides an example.

[0073] Operation (2719) is to thin the substrate from the rear. In some embodiments, the thinning process creates openings within trenches created by operation (2703) and narrowed by operation (2705). The cross-sectional view (2000) of FIG. 20 provides an example.

[0074] Operation (2721) is to deposit an isolation dielectric within the trenches to create a DTI structure within the trenches. In some embodiments, this process is performed in a manner that leaves voids within the trenches. The cross-sectional view (2100) of FIG. 21 provides an example. In some embodiments, this process is performed in a manner that fills the trenches while removing the voids. The cross-sectional view of FIG. 25 provides an example.

[0075] Operation (2723) is to form rear photodetector structures. These additional structures may include a rear metal grid, color filters, microlenses, etc. The cross-sectional view (2200) of FIG. 22 provides an example of forming a rear metal grid. The image sensing device (100) of FIG. 1a provides examples of color filters and microlenses.

[0076] Some aspects of the present disclosure relate to an image sensing device having photodetectors in a semiconductor body. A deep trench isolation structure extends into the semiconductor body to laterally surround the photodetectors. The semiconductor body comprises an epitaxial layer of a p-doped semiconductor lining the deep trench isolation structure. In some embodiments, the epitaxial layer of the p-doped semiconductor extends from the front side to the rear side. In some embodiments, the deep trench isolation structure extends from the rear side but is spaced apart from the front side. In some embodiments, the deep trench isolation structure is widest within the semiconductor body at a point between the front and rear sides. In some embodiments, the epitaxial layer of the p-doped semiconductor gradually narrows from the front side to the rear side or has a constant width. In some embodiments, the epitaxial layer extends over the front side.

[0077] Some aspects of the present disclosure relate to an image sensing element arranged within a substrate. A p-doped semiconductor on the sidewalls of the substrate forms one or more trenches on both sides of the image sensing element. The trenches gradually widen as the distance from the first side increases in a first zone adjacent to the first side. The trenches gradually widen as the distance from the second side increases in a second zone adjacent to the second side. In some embodiments, the first zone and the second zone meet. In some embodiments, the first zone and the second zone extend together from the top of the trenches to the bottom of the trenches. In some embodiments, one or more trenches are filled with a dielectric.

[0078] Some aspects of the present disclosure relate to a method for manufacturing an image sensing device. The method comprises the steps of providing a semiconductor body, etching a grid of trenches within the front side of the semiconductor body, and epitaxially growing a p-doped semiconductor within the trenches. An array of photodiodes is formed within the semiconductor body. The photodiodes are laterally separated by trenches. In some embodiments, the epitaxial layer is annealed on the front side of the semiconductor body. In some embodiments, the annealing includes laser annealing. In some embodiments, the method further comprises the step of chemically mechanically polishing the front side. In some embodiments, epitaxially growing a p-doped semiconductor within the trenches seals the trenches. In some embodiments, the semiconductor is thinned from the back side, and then a dielectric is deposited in the trenches from the back side. In some embodiments, the process of epitaxially growing a p-doped semiconductor in trenches also epitaxially grows the p-doped semiconductor on the front side to provide a front-side epitaxial layer. In some embodiments, a floating diffusion region is formed within the front-side epitaxial layer. In some embodiments, a deep n-well is implanted into the semiconductor body before etching the trenches. In some embodiments, the photodiodes include a PN junction formed by the p-doped semiconductor grown in the trenches along with the deep n-well. In some embodiments, the process of etching the trenches on the front side provides greater widths to the trenches within the semiconductor body than on the front side.

[0079] The foregoing describes the features of some embodiments to enable those skilled in the art to better understand aspects of the present disclosure. Those skilled in the art should recognize that they can readily use the present disclosure as a basis for designing or modifying other processes and structures to perform and / or achieve the same purposes or the same advantages as the embodiments introduced herein. Those skilled in the art should also recognize that various variations, substitutions, and modifications can be made to the present invention without departing from the spirit and scope of the present disclosure.

[0080] Examples

[0081] Example 1. In an image detection device,

[0082] Semiconductor body having a front side and a rear side;

[0083] Photodetectors within the semiconductor body above;

[0084] A deep trench isolation structure extending into the semiconductor body to laterally surround the above photodetectors; and

[0085] Epitaxial layer of a p-doped semiconductor lining the above deep trench isolation structure

[0086] An image detection device including

[0087] Example 2. In Example 1,

[0088] An image sensing device in which the epitaxial layer of the p-doped semiconductor extends from the front side to the rear side.

[0089] Example 3. In Example 1,

[0090] An image sensing device in which the deep trench isolation structure is the widest within the semiconductor body at a point between the front side and the rear side.

[0091] Example 4. In Example 3,

[0092] An image sensing device in which the epitaxial layer of the p-doped semiconductor gradually narrows from the front side to the rear side or has a constant width.

[0093] Example 5. In Example 4,

[0094] An image sensing device in which the deep trench isolation structure is spaced apart from the front side.

[0095] Example 6. In Example 1,

[0096] An image sensing device in which the above epitaxial layer extends above the above front side.

[0097] Example 7. In an image detection device,

[0098] A substrate having a first surface and a second surface; and

[0099] An image sensing element arranged within the above substrate - a p-doped semiconductor on the sidewalls of the above substrate forms one or more trenches on both sides of the image sensing element -

[0100] Includes,

[0101] The above trenches gradually become wider as the distance from the first surface increases in the first zone adjacent to the first surface, and

[0102] An image sensing device in which the trenches above gradually become wider as the distance from the second surface increases in a second zone adjacent to the second surface.

[0103] Example 8. In Example 7,

[0104] An image detection device in which the first zone and the second zone meet.

[0105] Example 9. In Example 7,

[0106] An image sensing device in which the first zone and the second zone together extend from the top of the trenches to the bottom of the trenches.

[0107] Example 10. In Example 7,

[0108] An image sensing device in which one or more of the above trenches are filled with a dielectric.

[0109] Example 11. A method for manufacturing an image sensing device,

[0110] A step of providing a semiconductor body having a front side and a rear side;

[0111] Step of etching trenches on the front side above - said trenches form a grid - ;

[0112] A step of epitaxially growing a p-doped semiconductor within the above trenches; and

[0113] Step of forming an array of photodiodes within the semiconductor body - the photodiodes are laterally separated by the trenches -

[0114] A method for manufacturing an image sensing device comprising

[0115] Example 12. In Example 11,

[0116] Step of epitaxially growing the p-doped semiconductor in the trenches, and then annealing the front side of the semiconductor body.

[0117] A method for manufacturing an image sensing device, further comprising

[0118] Example 13. In Example 12,

[0119] A method for manufacturing an image sensing device, wherein the annealing step described above includes laser annealing.

[0120] Example 14. In Example 13,

[0121] After the annealing step, the step of chemically mechanically polishing the front side

[0122] A method for manufacturing an image sensing device, further comprising

[0123] Example 5. In Example 11,

[0124] A method for manufacturing an image sensing device, wherein the step of epitaxially growing a p-doped semiconductor within the trenches seals the trenches.

[0125] Example 16. In Example 11,

[0126] A step of thinning the semiconductor body from the rear side; and

[0127] Step of forming a dielectric film within the trenches from the rear side

[0128] A method for manufacturing an image sensing device, further comprising

[0129] Example 17. In Example 11,

[0130] A method for manufacturing an image sensing device, wherein the step of epitaxially growing a p-doped semiconductor in the trenches further comprises the step of epitaxially growing the p-doped semiconductor on the front side to provide a front epitaxial layer.

[0131] Example 18. In Example 17,

[0132] Step of forming a floating diffusion region within the above-mentioned front epitaxial layer

[0133] A method for manufacturing an image sensing device, further comprising

[0134] Example 19. In Example 11,

[0135] Step of injecting a deep n-well into the semiconductor body before etching the above trenches

[0136] A method for manufacturing an image sensing device, further comprising, wherein the p-doped semiconductor grown in the trenches forms a PN junction of the photodiodes together with the deep n-well.

[0137] Example 20. In Example 11,

[0138] A method for manufacturing an image sensing device, wherein the step of etching the trenches on the front side provides trenches having a wider width within the semiconductor body than on the front side.

Claims

Claim 1 An image sensing device comprising: a semiconductor body having a front side and a rear side; photodetectors within the semiconductor body; a deep trench isolation structure extending into the semiconductor body to surround the photodetectors laterally; and an epitaxial layer of a p-doped semiconductor lining the deep trench isolation structure, wherein the epitaxial layer of the p-doped semiconductor gradually narrows from the front side to the rear side or has a constant width. Claim 2 An image sensing device according to claim 1, wherein the epitaxial layer of the p-doped semiconductor extends from the front side to the rear side. Claim 3 An image sensing device according to claim 1, wherein the deep trench isolation structure is the widest within the semiconductor body at a point between the front side and the rear side. Claim 4 An image sensing device according to claim 1, wherein the deep trench isolation structure is spaced apart from the front side. Claim 5 An image sensing device according to claim 1, wherein the epitaxial layer extends above the front side. Claim 6 An image sensing device comprising: a substrate having a first surface and a second surface; and an image sensing element arranged within the substrate, wherein a p-doped semiconductor on the sidewalls of the substrate forms one or more trenches on both sides of the image sensing element, wherein the trenches gradually widen as the distance from the first surface increases in a first zone adjacent to the first surface, and the trenches gradually widen as the distance from the second surface increases in a second zone adjacent to the second surface, and wherein the p-doped semiconductor has a width that gradually narrows from the second surface to the first surface. Claim 7 An image sensing device according to claim 6, wherein the first zone and the second zone meet. Claim 8 An image sensing device according to claim 6, wherein the first zone and the second zone together extend from the top of the trenches to the bottom of the trenches. Claim 9 An image sensing device according to claim 6, wherein one or more of the above trenches are filled with a dielectric. Claim 10 A method for manufacturing an image sensing device, comprising: providing a semiconductor body having a front side and a rear side; etching trenches on the front side, wherein the trenches form a grid; epitaxially growing a p-doped semiconductor within the trenches, wherein the p-doped semiconductor has a width that gradually narrows from the front side to the rear side or a constant width; and forming an array of photodiodes within the semiconductor body, wherein the photodiodes are laterally separated by the trenches.

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