Vertically stacked light sensors

Abstract

Various embodiments of the present disclosure relate to a semiconductor structure comprising a first substrate comprising a first semiconductor material. A first optical sensor is disposed within the first substrate. The first optical sensor is configured to absorb electromagnetic radiation within a first wavelength range. A second optical sensor is disposed within an absorption structure located beneath the first substrate. The second optical sensor is configured to absorb electromagnetic radiation within a second wavelength range different from the first wavelength range. The absorption structure is located beneath the first optical sensor and comprises a second semiconductor material different from the first semiconductor material.

Description

Technology Field

[0001] Reference to related applications

[0002] This application claims the benefit of U.S. provisional application No. 63 / 498,309 filed on April 26, 2023, the contents of which are incorporated herein by reference in their entirety. Background Technology

[0003] Integrated chips (ICs) equipped with image sensors are used in a wide range of today's electronic devices. An image sensor comprises one or more photodetectors (e.g., photodiodes, phototransistors, photoresistors, etc.) configured to absorb incident light and output an electrical signal corresponding to the incident light. Some types of image sensors include charge-coupled device (CCD) image sensors and complementary metal-oxide-semiconductor (CMOS) image sensors. Compared to CCD image sensors, CMOS image sensors are preferred due to their lower power consumption, smaller size, faster data processing, direct data output, and lower manufacturing costs. Brief explanation of the drawing

[0004] The aspects of the present disclosure are best understood from the following detailed description when read together with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not depicted to scale. In practice, the dimensions of various features may be increased or decreased at will for clarity of discussion. FIG. 1 illustrates a cross-sectional view of some embodiment of a stacked integrated chip (IC) structure comprising a first optical sensor on top of a second optical sensor, wherein the first optical sensor and the second optical sensor are configured to absorb electromagnetic radiation of different wavelength ranges. FIG. 2 illustrates a top layout diagram of some embodiment of the stacked IC structure of FIG. 1. FIG. 3a illustrates a cross-sectional view of some other embodiment of a stacked integrated chip (IC) structure comprising a first optical sensor on top of a second optical sensor, wherein the first optical sensor and the second optical sensor are configured to absorb electromagnetic radiation of different wavelength ranges. FIGS. 3b to 3d illustrate cross-sectional views of some alternative embodiments of the stacked IC structure of FIG. 3a. FIGS. 4a and 4b illustrate cross-sectional views of some other embodiments of the stacked IC structure of FIG. 1. FIGS. 5 to 17 illustrate various cross-sectional views of some embodiments of a method for forming a stacked IC structure including a first optical sensor on a second optical sensor, wherein the first optical sensor and the second optical sensor are configured to absorb electromagnetic radiation of different wavelength ranges. FIGS. 18 to 24 illustrate various cross-sectional views of some other embodiments of a method for forming a stacked IC structure including a first optical sensor on a second optical sensor, wherein the first optical sensor and the second optical sensor are configured to absorb electromagnetic radiation of different wavelength ranges. FIGS. 25 to 30 illustrate various cross-sectional views of different embodiments of a method for forming a stacked IC structure including a first optical sensor on a second optical sensor, wherein the first optical sensor and the second optical sensor are configured to absorb electromagnetic radiation of different wavelength ranges. FIGS. 31 to 35 illustrate various cross-sectional views of another embodiment of a method for forming a stacked IC structure including a first optical sensor on a second optical sensor, wherein the first optical sensor and the second optical sensor are configured to absorb electromagnetic radiation of different wavelength ranges. FIG. 36 illustrates a flowchart of some embodiment of a method for forming a stacked IC structure including a first optical sensor on a second optical sensor, wherein the first optical sensor and the second optical sensor are configured to absorb electromagnetic radiation of different wavelength ranges. Specific details for implementing the invention

[0005] The present disclosure provides many different embodiments or examples for implementing different features of the present disclosure. To simplify the present disclosure, specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature on or above a second feature may include embodiments in which the first feature and the second feature are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature are not in direct contact. Additionally, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplification and clarification and does not itself determine the relationship between the various embodiments and / or configurations discussed.

[0006] Additionally, for ease of description regarding the relationship of one element or feature to other element(s) or feature(s) illustrated in the drawings, spatial relative terms such as “bottom,” “below,” “lower,” “above,” and “top” may be used herein. Spatial relative terms are intended to encompass different orientations of the device in use or operation, in addition to the orientations illustrated in the drawings. The device may be oriented differently (rotated 90 degrees or to other orientations), and the spatial relative terms used herein may be interpreted accordingly.

[0007] A complementary metal-oxide-semiconductor (CMOS) image sensor (CMOS image sensor; CIS) may include a plurality of image sensors disposed on a substrate. Each image sensor is configured to generate an electrical signal from incident light. A lens structure is placed on the substrate and is configured to direct the incident light toward the image sensor. Additionally, an interconnect structure and / or one or more semiconductor devices (e.g., a transfer transistor) are disposed on the substrate and are configured to facilitate the reading of the generated electrical signal.

[0008] An image sensor can be configured to generate an electrical signal from light within a specific range of wavelengths. For example, an image sensor can be placed within a silicon substrate that has a high absorption coefficient for light within the visible light spectrum (e.g., light having wavelengths in the range of approximately 380 nm to approximately 700 nm). Thus, an image sensor placed within a silicon substrate increases the performance of visible light detection. However, the absorption coefficient of silicon decreases as the wavelength of light increases. An image sensor placed within germanium provides a better option for light within the infrared (IR) range (e.g., light having wavelengths in the range of approximately 900 nm to 3,000 nm) because germanium has higher absorption of IR (infrared) light compared to silicon (e.g., due to germanium having a smaller bandgap than silicon). As a result, an image sensor placed within germanium increases the performance of IR light detection. Therefore, in order to efficiently detect light within two or more wavelength ranges (e.g., visible light range, IR range, etc.), two or more CISs, each including an image sensor, an optical filter, a microlens, etc., may be used, thereby increasing manufacturing costs. In addition, in some cases, two or more CISs may be arranged laterally adjacent to each other on a package structure, so that the CISs occupy a relatively large lateral footprint.

[0009] Various embodiments of the present application are directed toward a stacked integrated chip (IC) structure comprising a second IC chip having a plurality of IR light sensors and a first IC chip having a plurality of visible light sensors stacked vertically. The first IC chip comprises a first substrate comprising a first semiconductor material (e.g., silicon) having a high absorption coefficient for visible light. The visible light sensors are disposed within the first substrate. The second IC chip comprises one or more absorption structures disposed on and / or within the second substrate, and the absorption structures comprise a second semiconductor material (e.g., germanium) having a high absorption coefficient for infrared (IR) light. The IR light sensors are disposed within the corresponding absorption structures. The first IC chip and the second IC chip each comprise an interconnect structure and a bond structure. The first IC chip and the second IC chip meet at a bond interface vertically disposed between the first substrate and the second substrate, and a single lens structure is placed over the first IC chip and the second IC chip. Therefore, the visible light sensor is stacked vertically with the IR light sensor, so that the stacked IC structure can efficiently detect light within two or more wavelength ranges while reducing the lateral footprint and manufacturing costs.

[0010] FIG. 1 illustrates a cross-sectional view (100) of a partial embodiment of a stacked integrated chip (IC) structure comprising a first light sensor on a second light sensor, wherein the first light sensor and the second light sensor are configured to absorb electromagnetic radiation of different wavelength ranges.

[0011] A stacked IC structure includes a first IC chip (102) stacked vertically with a second IC chip (104). The first IC chip (102) includes a first substrate (106), and the second IC chip (104) includes a second substrate (108). The first substrate and the second substrate (106, 108) may each include a first semiconductor material and / or include a first doping type [e.g., p-type]. In some embodiments, the first semiconductor material may be, for example, silicon, epitaxial silicon, etc., or may include these. Additionally, the first IC chip (102) includes a plurality of first optical sensors (129), and the second IC chip (104) includes one or more second optical sensors (137). The plurality of first optical sensors (129) and one or more second optical sensors (137) are each configured to absorb electromagnetic radiation (148) and generate a corresponding electrical signal. A plurality of first light sensors (129) are configured to absorb electromagnetic radiation (148) within a first wavelength range, and one or more second light sensors (137) are configured to absorb electromagnetic radiation (148) within a second wavelength range different from the first wavelength range. For example, a plurality of first light sensors (129) are configured to absorb visible light, and one or more second light sensors (137) are configured to absorb infrared (IR) light [e.g., near IR (NIR) light, short-wave IR (SWIR) light, etc.]. In some embodiments, the first wavelength range includes electromagnetic radiation having wavelengths within a range of approximately 380 nm to approximately 700 nm. In various embodiments, the second wavelength range includes electromagnetic radiation having wavelengths within a range of approximately 900 nm to approximately 2,500 nm, a range of approximately 1,400 nm to approximately 3,000 nm, or some other suitable value.

[0012] The first IC chip (102) further includes a first interconnect structure (110) and a first bond structure (114) disposed on the front-side surface (106f) of the first substrate (106). The second IC chip (104) further includes a second interconnect structure (112) and a second bond structure (116) disposed on the front-side surface (108f) of the second substrate (108). The first interconnect structure and the second interconnect structure (110, 112) each include a plurality of metallization structures (119, 120, 122) (e.g., metal contacts, metal vias, metal wires, etc.) disposed within an interconnect dielectric structure (118). The first bond structure and the second bond structure (114, 116) each include a conductive bond structure (126, 128) disposed within a dielectric bond structure (124). The first IC chip and the second IC chip (102, 104) meet at a bond interface (105), where the first bond structure (114) is bonded to the second bond structure (116). The first interconnect structure and the second interconnect structure (110, 112) are electrically coupled to each other by the first bond structure and the second bond structure (114, 116). A plurality of optical filters (142) (e.g., color filters, etc.) are disposed on the back-side surface (106b) of the first substrate (106). An optical filter (142) is configured to transmit electromagnetic radiation (148) of a specific wavelength to a first optical sensor and a second optical sensor (129, 137). Additionally, an upper optical guide structure (145) is disposed on a plurality of optical filters (142). In some embodiments, the upper optical guide structure (145) includes a plurality of micro-lenses (144) configured to focus the electromagnetic radiation (148) toward the first optical sensor and the second optical sensor (129, 137).

[0013] A plurality of first optical sensors (129) each include a doped photodetector region (134) disposed on a first substrate (106). The doped photodetector region (134) has a second doping type [e.g., n-type] opposite to the first doping type (e.g., p-type) of the region of the first substrate (106) adjacent to the doped photodetector region (134). In some embodiments, the first doping type is p-type and the second doping type is n-type, or vice versa. Accordingly, in some embodiments, a plurality of first optical sensors (129) each include and / or are configured as photodiodes such as a PN photodiode, a PIN photodiode, etc. In various embodiments, by means of a first optical sensor (129) each comprising a doped photodetector region (134) disposed on a first substrate (106) - the first substrate (106) comprises a first semiconductor material (e.g., silicon) - the first optical sensor (129) has a high absorption coefficient for electromagnetic radiation (148) (e.g., visible light) within a first wavelength range.

[0014] Additionally, a plurality of floating diffusion nodes (132) are disposed within the first substrate (106). The floating diffusion nodes (132) have a second doping type (e.g., n-type). A plurality of pixel devices (130) are disposed on the front side (106f) of the first substrate (106). In various embodiments, the floating diffusion nodes (132) and the plurality of pixel devices (130) are configured to facilitate the reading of an electrical signal generated by a first light sensor (129), wherein the electrical signal corresponds to absorbed light within a first wavelength range.

[0015] One or more second optical sensors (137) comprise an absorption structure (138) and a first doping region and a second doping region (135, 136) disposed within the absorption structure (138). In some embodiments, the first doping region (135) and the second doping region (136) have opposite doping types. For example, the first doping region (135) comprises a first doping type (e.g., p-type), and the second doping region (136) comprises a second doping type (e.g., n-type). One or more second optical sensors (137) may be photodiodes such as, for example, a PN photodiode, a PIN photodiode, an avalanche photodiode, etc. The absorption structure (138) comprises a second semiconductor material (e.g., germanium) that is different from the first semiconductor material (e.g., silicon) of the first substrate (106). The second semiconductor material may be, for example, germanium, etc., or may include these. With one or more second optical sensors (137) having an absorption structure (138) having the second semiconductor material (e.g., germanium), the one or more second optical sensors (137) have a high absorption coefficient for electromagnetic radiation (148) (e.g., IR light, NIR light, SWIR light, etc.) within a second wavelength range. This is partly because the band gap of the second material (e.g., germanium) of the absorption structure (138) is smaller than the band gap of the first semiconductor material (e.g., silicon) of the first substrate (106).

[0016] While FIG. 1 illustrates a stacked IC structure comprising a single second optical sensor (137), this is merely a non-limiting example, and it will be understood that the second IC chip (104) may include any number of second optical sensors (137), each comprising a corresponding absorption structure (138) and a first doping region and a second doping region (135, 136), respectively (e.g., as illustrated in FIG. 3d). For example, the second IC chip (104) may include an array of second optical sensors (137) arranged in multiple columns and multiple rows, wherein one or more of the first optical sensors (129) are located directly above each second optical sensor (137).

[0017] By having a plurality of first optical sensors (129) disposed within a first substrate (106) (e.g., silicon) and one or more second optical sensors (137) having an absorption structure (138) (e.g., germanium), the stacked IC structure comprises two or more optical sensors that efficiently absorb electromagnetic radiation (148) of different wavelength ranges. Additionally, stacking the first IC chip (102) vertically with the second IC chip (104) facilitates increasing the number of optical sensors that can be disposed in a lateral area and facilitates the stacked IC structure having individual upper optical guide structures (145). Thus, the stacked IC structure can efficiently detect light within two or more wavelength ranges while increasing device density and reducing manufacturing costs.

[0018] In various embodiments, the second substrate (108) includes one or more surfaces defining a recess that extends into the front side surface (108f) of the second substrate (108). An absorption structure (138) is disposed within the recess. Additionally, a capping layer (140) extends over the top surface of the absorption structure (138). In various embodiments, the top surface of the absorption structure (138) is recessed below the front side surface (108f) of the second substrate (108), and the capping layer (140) extends along the recessed top surface of the absorption structure (138). In some embodiments, the top surface of the capping layer (140) is aligned with the front side surface (108f) of the second substrate (108).

[0019] In another embodiment, a plurality of light guide regions (146) are disposed on the first interconnect structure and the second interconnect structure (110, 112) and the first bond structure and the second bond structure (114, 116). The light guide regions (146) extend continuously from a plurality of first light sensors (129) to a corresponding second light sensor (137). For example, each light guide region (146) may extend continuously from a doped photodetector region (134) of a corresponding first light sensor (129) to an absorption structure (138). The plurality of light guide regions (146) extend toward the second substrate (108) in a direction orthogonal to the front side (106f) of the first substrate (106). In various embodiments, a plurality of light guide regions (146) are regions of a first interconnect structure and a second interconnect structure (110, 112) and a first bond structure and a second bond structure (114) that are free of metal wiring structures (119, 120, 122) and conductive bond structures (126, 128). For example, the plurality of light guide regions (146) may include one or more dielectric materials and are free of metal wiring structures (119, 120, 122) and conductive bond structures (126, 128). As a result, at least a portion of the electromagnetic radiation (148) can travel to one or more second light sensors (137) through the first substrate (106), the first interconnect structure and the second interconnect structure (110, 112), the first bond structure and the second bond structure (114, 116) [e.g., through the light guide area (146)].

[0020] FIG. 2 illustrates a top layout diagram (200) of a partial embodiment of the stacked IC structure of FIG. 1.

[0021] In some embodiments, the stacked IC structure comprises a plurality of pixels (202), each comprising a plurality of first light sensors (129) and at least one second light sensor (137). In various embodiments, the first light sensors (129) of each pixel (202) may have a 2x2 layout arranged in a Bayer pattern. For example, the first pixel (202a) comprises a first subset of first light sensors (129a to 129d), comprising a blue light sensor (129a), a first green light sensor (129b), a second green light sensor (129c), and a red light sensor (129d). In various embodiments, the first pixel (202a) comprises individual second light sensors (137a) located below the first light sensors (129a to 129d). It will be understood that the light sensor of each pixel (202) may have different layouts, such as a 2x1 layout, a 4x2 layout, a 4x4 layout, etc. Additionally, the light sensor of each pixel (202) may have a combination of layouts between the first light sensor (129) and the second light sensor (137). In another embodiment, the size of the absorption structure (e.g., 138 in FIG. 1) may be approximately the same as the size of the first light sensor (129) above the corresponding pixel (202). For example, when viewed in the top view, the area of ​​the absorption structure (e.g., 138 in FIG. 1) of the individual second light sensor (137a) may be approximately the same as the area of ​​the first light sensors (129a to 129d).

[0022] FIG. 3a illustrates a cross-sectional view (300a) of some other embodiment of a stacked IC structure including a first optical sensor on top of a second optical sensor, wherein the first optical sensor and the second optical sensor are configured to absorb electromagnetic radiation of different wavelength ranges.

[0023] A stacked IC structure comprises a first IC chip (102) bonded to a second IC chip (104). The first IC chip (102) comprises a first substrate (106), a first interconnect structure (110), and a first bond structure (114). The second IC structure comprises a second substrate (108), a second interconnect structure (112), and a second bond structure (116). The first substrate and the second substrate (106, 108) may be, for example, silicon, single-crystal silicon, CMOS bulk, epitaxial silicon, silicon-on-insulator (SOI) substrate, some other suitable substrate material, or any combination thereof, respectively. In some embodiments, the first substrate and the second substrate (106, 108) comprise a first semiconductor material (e.g., silicon) having a first doping type (e.g., p-type).

[0024] The first interconnect structure and the second interconnect structure (110, 112) each comprise an interconnect dielectric structure (118), a plurality of conductive contacts (119), a plurality of conductive vias (120), and a plurality of conductive wires (122). The interconnect dielectric structure (118) may comprise a plurality of dielectric layers, for example, silicon dioxide, a low-k dielectric material, some other dielectric material, or any combination thereof, or may comprise them. As used herein, a low-k dielectric material is a dielectric material having a dielectric constant less than about 3.9. The conductive contacts, vias, and wires (119, 120, 122) may be, for example, tungsten, copper, aluminum, titanium nitride, tantalum nitride, ruthenium, some other conductive material, or any combination thereof, or may comprise them.

[0025] The first bond structure and the second bond structure (114, 116) each include a plurality of bond contact portions (126), a plurality of bond pads (128), and a dielectric bond structure (124). The first bond structure and the second bond structure (114, 116) meet at a bond interface (105) including a dielectric-to-dielectric bond, a conductor-to-conductor bond, etc. The dielectric bond structure (124) includes one or more dielectric layers that may be, for example, silicon dioxide, silicon carbide, silicon nitride, silicon oxynitride, some other dielectric material, or any combination thereof, or may include these. The bond contact portions and pads (126, 128) may be, for example, copper, tungsten, titanium, tantalum, tungsten, some other conductive material, or any combination thereof, or may include these. The first IC chip (102) is electrically coupled to the second IC chip (104) by the first bond structure and the second bond structure (114, 116) and the first interconnect structure and the second interconnect structure (110, 112).

[0026] A plurality of first light sensors (129) are disposed within a first substrate (106) and each includes a doped photodetector region (134). In various embodiments, the doped photodetector region (134) is a part of the first substrate (106) having a second doping type (e.g., n-type) opposite to the first doping type (e.g., p-type). Additionally, a plurality of floating diffusion nodes (132) are disposed within the first substrate (106) adjacent to at least one doped photodetector region (134). The floating diffusion nodes have a second doping type (e.g., n-type) and may have a doping concentration higher than, for example, the doping concentration of the doped photodetector region (134). A plurality of pixel devices (130) are disposed on the front side (106f) of the first substrate (106). In some embodiments, a plurality of pixel devices (130) include transfer transistor(s), reset transistor(s), source-follower transistor(s), other suitable devices, etc. The first light sensor (129) is configured to absorb electromagnetic radiation (e.g., visible light) within a first wavelength range. Additionally, the pixel device (130) is configured to facilitate the reading of an electrical signal generated from the electromagnetic radiation absorbed by the first light sensor (129).

[0027] One or more second optical sensors (137) are disposed within and / or on the second substrate (108) and are located below a plurality of first optical sensors (129). In some embodiments, one or more second optical sensors (137) each include an absorption structure (138) disposed on the second substrate (108) and a first doping region and a second doping region (135, 136). The absorption structure (138) includes a second semiconductor material (e.g., germanium) that is different from the first semiconductor material (e.g., silicon). Additionally, a capping layer (140) extends along the top surface of the absorption structure (138). In some embodiments, the capping layer (140) includes the first semiconductor material (e.g., silicon) or some other suitable material. In various embodiments, the first doping region and the second doping region (135, 136) extend continuously from the capping layer (140) to below the top surface of the absorption structure (138). The first doping region (135) may include a first doping type (e.g., p-type), and the second doping region (136) may include a second doping type (e.g., n-type). One or more second optical sensors (137) are configured to absorb electromagnetic radiation (e.g., IR light, NIR light, SWIR light, etc.) within a second wavelength range different from the first wavelength range. Thus, the stacked IC structure includes two or more optical sensors that efficiently absorb electromagnetic radiation in different wavelength ranges while increasing device density and reducing manufacturing costs.

[0028] In some embodiments, the first doping region and the second doping region (135, 136) are electrically coupled to one or more second pixel devices (not shown) and / or control circuits (not shown) configured to selectively apply bias voltages to the first doping region and / or the second doping region (135, 136). When a suitable bias voltage is applied to the first doping region and / or the second doping region (135, 136), an electrical signal corresponding to a photon-generated charge carrier within the absorption structure (138) can be read. In various embodiments, one or more second pixel devices (not shown) may be disposed within and / or on the second IC chip (104) [e.g., on the second substrate (108)] and / or on another IC chip (not shown).

[0029] A plurality of optical filters (142) are disposed on the rear side (106b) of the first substrate (106). The optical filters (142) are configured to transmit electromagnetic radiation of a specific wavelength to the first optical sensor and the second optical sensor (129, 137). In some embodiments, the optical filters (142) include one or more of band-pass filters, red color filters, blue color filters, green color filters, etc. In another embodiment, each optical filter (142) may be configured to pass at least one color of light, while the optical filters (142) may also be configured to pass light within a second wavelength range. An upper optical guide structure (145) is disposed on the plurality of optical filters (142) and configured to direct the electromagnetic radiation toward the first optical sensor and the second optical sensor (129, 137). In some embodiments, the upper optical guide structure (145) includes a plurality of micro-lenses (144), each having a convex upper surface.

[0030] A plurality of light guide regions (146) are disposed in the first interconnect structure and the second interconnect structure (110, 112) and the first bond structure and the second bond structure (114, 116). The light guide regions (146) extend continuously from a plurality of first light sensors (129) to a corresponding second light sensor (137). In some embodiments, a plurality of light guide structures (302) are disposed within the plurality of light guide regions (146). Each of the plurality of light guide structures (302) includes a first light guide element (304) disposed in the first IC chip (102) and a second light guide element (306) disposed in the second IC chip (104). In various embodiments, the first light guide element and the second light guide element (304, 306) meet via a dielectric-to-dielectric bond. The first light guide element and the second light guide element (304, 306) may each be, for example, a high-k dielectric material, titanium oxide (e.g., TiO2), tantalum oxide (e.g., Ta2O5), zirconium oxide (e.g., ZrO2), some other suitable dielectric material, or any combination thereof, or may include these. As used herein, a high-k dielectric material is a dielectric material having a dielectric constant greater than about 3.9. The light guide structure (302) may be configured as a light pipe structure. The refractive index of the light guide structure (302) is greater than the refractive index of the dielectric bond structure (124) of the first bond structure and the second bond structure (114, 116) and the interconnect dielectric structure (118) of the first interconnect structure and the second interconnect structure (110, 112).Accordingly, the light guide structure (302) is configured to guide electromagnetic radiation to one or more second light sensors (137) by total internal reflection (TIR), thereby increasing the quantum efficiency (QE) of the stacked IC structure. In various embodiments, electromagnetic radiation within a first wavelength range may be absorbed by the first light sensor (129), and electromagnetic radiation within a second wavelength range may pass through the first substrate (106) and the light guide structure (302) to one or more second light sensors (137).

[0031] FIG. 3b illustrates a cross-sectional view (300b) corresponding to some other embodiment of the stacked IC structure of FIG. 3a, wherein the absorption structure (138) is disposed along the front side surface (108f) of the second substrate (108). In some embodiments, the bottom surface of the absorption structure (138) is in direct contact with the front side surface (108f) of the second substrate (108). A dielectric layer (308) is disposed on the front side surface (108f) of the second substrate (108) and laterally wraps around the absorption structure (138). Additionally, a capping layer (140) is disposed on the top surface of the absorption structure (138). In some embodiments, the top surface of the capping layer (140) is coplanar with the top surface of the dielectric layer (308).

[0032] FIG. 3c illustrates a cross-sectional view (300c) corresponding to some alternative embodiment of the stacked IC structure of FIG. 3b, wherein a plurality of light guide structures (302 of FIG. 3b) are omitted.

[0033] FIG. 3d illustrates a cross-sectional view (300d) corresponding to some other embodiment of the stacked IC structure of FIG. 3a, wherein individual second light sensors (137) are located directly below each first light sensor (129).

[0034] FIG. 4a illustrates a cross-sectional view (400a) corresponding to some other embodiment of the stacked IC structure of FIG. 1, wherein the upper light guide structure (145) includes a plurality of meta-lenses (402) configured to direct electromagnetic radiation toward the first light sensor and the second light sensor (129, 137). In various embodiments, two or more meta-lenses (402) are located directly above each light filter (142).

[0035] FIG. 4b illustrates a cross-sectional view (400b) corresponding to some alternative embodiment of the stacked IC structure of FIG. 1, wherein the upper light guide structure (145) includes a plurality of optical input structures (404). In various embodiments, the optical input structures (404) may be, for example, optical fibers, optical fiber structures, etc., or may include these. In some embodiments, the optical input structures (404) may be configured to direct electromagnetic radiation from an optical source (e.g., a laser) toward a first light sensor and a second light sensor (129, 137).

[0036] FIGS. 5 through 17 illustrate various cross-sectional views (500 through 1700) of some embodiments of a method for forming a stacked IC structure comprising a first optical sensor on a second optical sensor, wherein the first optical sensor and the second optical sensor are configured to absorb electromagnetic radiation of different wavelength ranges. The stacked IC structure may correspond, for example, to the stacked IC structure of FIG. 1. Although the cross-sectional views (500 through 1700) shown in FIGS. 5 through 17 are described in relation to the method, it will be understood that the structure shown in FIGS. 5 through 17 may be independent of the method rather than being limited to the method. Also, although FIGS. 5 through 17 are described as a series of acts, it will be understood that the disclosed method is not limited in that the order of the acts may be changed in other embodiments and that the disclosed method may also be applicable to other structures. In other embodiments, some acts that are illustrated / illustrated or described may be omitted in whole or in part.

[0037] As illustrated in the cross-sectional view (500) of FIG. 5, a plurality of first optical sensors (129) are formed within a first substrate (106) comprising a first semiconductor material (e.g., silicon), wherein the first optical sensors (129) are configured to absorb electromagnetic radiation (e.g., visible light) within a first wavelength range. In some embodiments, the first substrate (106) may be, for example, silicon, epitaxial silicon, bulk silicon, silicon-on-insulator (SOI) substrate, one or more epitaxial layers, some other suitable substrate material, or may include these. Additionally, the first substrate (106) may have a first doping type (e.g., p-type). In some embodiments, the first optical sensors (129) each include a doped photodetector region (134) disposed on the first substrate (106). In various embodiments, the process for forming the first photosensor (129) comprises forming an injection mask (not shown) on the first substrate (106) and injecting a dopant into the first substrate (106) along the injection mask. In some embodiments, the doped photodetector region (134) comprises one or more dopants [e.g., phosphorus, antimony, arsenic, etc.] having a second doping type (e.g., n-type) opposite to the first doping type.

[0038] As illustrated in the cross-sectional view (600) of FIG. 6, a plurality of pixel devices (130) are formed on the front side (106f) of the first substrate (106). In some embodiments, the process for forming the plurality of pixel devices (130) includes depositing a gate dielectric on the first substrate (106) [e.g. by physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), etc.]; depositing a gate electrode on the gate dielectric (e.g. by PVD, CVD, sputtering, electroplating, electroless plating, etc.); patterning the gate dielectric and the gate electrode; and forming sidewall spacers around the gate electrode and the gate dielectric. In various embodiments, forming the pixel devices (130) may further include performing an optional ion implantation process (not shown) to form one or more source / drain regions on the first substrate (106). The gate electrode may be, for example, polysilicon, a metal material, another conductive material, or any combination thereof, or may include these. The gate dielectric may be, for example, silicon dioxide, a high-k dielectric material, some other dielectric material, or any combination thereof, or may include these.

[0039] As illustrated in the cross-sectional view (700) of FIG. 7, a plurality of floating diffusion nodes (132) are formed on the first substrate (106). Each floating diffusion node (132) is adjacent to a corresponding doped photodetector region (134). In some embodiments, the process for forming the floating diffusion nodes (132) includes forming an injection mask (not shown) on the first substrate (106) and injecting a dopant (e.g., phosphorus, antimony, arsenic, etc.) into the first substrate (106) along the injection mask. In various embodiments, the floating diffusion nodes (132) include one or more dopants (e.g., phosphorus, antimony, arsenic, etc.) having a second doping type (e.g., n-type).

[0040] As illustrated in the cross-sectional view (800) of FIG. 8, a dielectric layer (802) and a plurality of conductive contacts (119) are formed on a first substrate (106). The dielectric layer (802) may be formed on the first substrate (106) by, for example, CVD, PVD, ALD, or some other suitable growth or deposition process. In some embodiments, the dielectric layer (802) comprises silicon dioxide, a low-k dielectric material, etc. In various embodiments, a process for forming a plurality of conductive contacts (119) comprises patterning the dielectric layer (802) to form a plurality of contact openings in the dielectric layer (802); depositing a conductive material (e.g., by CVD, PVD, electroplating, etc.) into the contact openings; and performing a planarization process [e.g., a chemical mechanical planarization (CMP) process] on the conductive material.

[0041] As illustrated in the cross-sectional view (900) of FIG. 9, a first interconnect structure (110) is formed on a first substrate (106), and a first bond structure (114) is formed on the first interconnect structure (110), thereby defining a first IC chip (102). The first interconnect structure (110) includes a conductive via (120) and a conductive wire (122) disposed within an interconnect dielectric structure (118). In some embodiments, a process for forming one or more layers of a conductive structure of the first interconnect structure (110) comprises: depositing a dielectric layer on the first substrate (106) (e.g., by CVD, PVD, ALD, etc.); etching the dielectric layer to form a conductive feature opening within the dielectric layer; and depositing a conductive material in the conductive feature opening (e.g., by CVD, PVD, electroplating, etc.). and includes performing a planarization process (e.g., CMP process) on conductive materials.

[0042] Additionally, the first bond structure (114) includes a plurality of bond contacts (126) and a plurality of bond pads (128) disposed within the dielectric bond structure (124). The plurality of bond contacts and pads (126, 128) are electrically coupled to the first interconnect structure (110). In some embodiments, a process for forming the bond contacts (126) comprises depositing a dielectric layer (e.g., by CVD, PVD, ALD, etc.) on the first interconnect structure (110); etching the dielectric layer to form a contact opening; depositing a conductive material on the contact opening; and performing a planarization process (e.g., a CMP process) on the conductive material. In other embodiments, a process for forming the bond pads (128) comprises depositing another dielectric layer (e.g., by CVD, PVD, ALD, etc.) on the bond contacts (126); It includes etching another dielectric layer to form a bond pad opening; depositing a conductive material at the bond pad opening; and performing a planarization process (e.g., CMP process) on the conductive material.

[0043] As illustrated in the cross-sectional view (1000) of FIG. 10, a second substrate (108) is provided, and a patterning process is performed on the second substrate (108) to form a recess (1004) that extends into the front side (108f) of the second substrate (108). In some embodiments, the second substrate (108) may be, for example, silicon, epitaxial silicon, bulk silicon, SOI substrate, one or more epitaxial layers, some other suitable substrate material, etc., or may include these. In various embodiments, the second substrate (108) includes a first semiconductor material (e.g., silicon). The recess (1004) is defined by one or more sides of the second substrate (108). In some embodiments, patterning the second substrate (108) to form a recess (1004) comprises forming a masking layer (1002) on the second substrate (108) and exposing the second substrate (108) to one or more etchants along the masking layer (1002). The masking layer (1002) may be removed during and / or after the patterning process. In various embodiments, the patterning process comprises performing a dry etching (e.g., reactive ion etching, plasma etching, etc.), a wet etching process, or any combination thereof.

[0044] As illustrated in the cross-sectional view (1100) of FIG. 11, an absorption structure (138) is formed on a second substrate (108), and a capping layer (140) is formed on the absorption structure (138). In some embodiments, the absorption structure (138) is formed along one or more faces of the second substrate (108) defining a recess (1004 in FIG. 10). The absorption structure (138) comprises a second semiconductor material (e.g., germanium) that is different from the first semiconductor material (e.g., silicon). In various embodiments, the absorption structure (138) has a first doping type (e.g., p-type). In some embodiments, the process for forming the absorption structure (138) comprises depositing a second semiconductor material (e.g., germanium) within a recess (1004 in FIG. 10) [e.g. by an epitaxial growth process such as CVD, PVD, molecular-beam epitaxy (MBE), vapor-phase epitaxy (VPE), liquid-phase epitaxy (LPE), etc.] and performing a removal process (e.g., etch back process, CMP process, etc.) on the second semiconductor material to remove excess material of the absorption structure (138) from the second substrate (108). In various embodiments, the top surface of the absorption structure (138) is recessed below the second substrate (108). In some embodiments, the capping layer (140) is formed on the absorption structure (138) by CVD, PVD, MBE, VPE, LPE, or some other suitable growth or deposition process. Additionally, a planarization process (e.g., a CMP process) may be performed on the capping layer (140). In various embodiments, the top surface of the capping layer (140) is coplanar with the front side surface (108f) of the second substrate (108). The capping layer (140) may be, for example, silicon, epitaxial silicon, some other suitable semiconductor material, or may include these.

[0045] As illustrated in the cross-sectional view (1200) of FIG. 12, a first doping region and a second doping region (135, 136) are formed in the absorption structure (138) to form one or more second optical sensors (137). The one or more second optical sensors (137) are configured to absorb electromagnetic radiation (e.g., IR light, NIR light, SWIR light, etc.) within a second wavelength range different from the first wavelength range. Additionally, a dielectric layer (1202) and a plurality of conductive contacts (119) are formed on the second substrate (108).

[0046] In some embodiments, the first doping region (135) is formed by a first injection process comprising forming a first injection mask (not shown) on the second substrate (108) and injecting a dopant into the absorption structure (138) and / or capping layer (140) along the first injection mask. In various embodiments, the first doping region (135) comprises one or more dopants (e.g., boron, gallium, aluminum, etc.) having a first doping type (e.g., p-type). In other embodiments, the first doping region (135) has a higher doping concentration than the region of the absorption structure (138) adjacent to the first doping region (135). In another embodiment, the second doping region (136) is formed by a second injection process comprising forming a second injection mask (not shown) on the second substrate (108) and injecting a dopant into an absorption structure and / or capping layer (140) along the second injection mask. In some embodiments, the second doping region (136) comprises one or more dopants (e.g., phosphorus, antimony, arsenic, etc.) having a second doping type (e.g., n-type).

[0047] The dielectric layer (1202) may be formed on the second substrate (108) by, for example, CVD, PVD, ALD, or some other suitable growth or deposition process. The dielectric layer (1202) may be, for example, silicon dioxide, a low-k dielectric material, or may include these. In various embodiments, a process for forming a plurality of conductive contacts (119) comprises patterning the dielectric layer (1202) to form a plurality of contact openings in the dielectric layer (1202); depositing a conductive material (e.g., by CVD, PVD, electroplating, etc.) into the contact openings; and performing a planarization process (e.g., CMP process) on the conductive material.

[0048] As illustrated in the cross-sectional view (1300) of FIG. 13, a second interconnect structure (112) is formed on the second substrate (108), and a second bond structure (116) is formed on the second interconnect structure (112), thereby defining the second IC chip (104). The second interconnect structure (112) includes a conductive via (120) and a conductive wire (122) disposed within an interconnect dielectric structure (118). The second bond structure (116) includes a bond contact (126) and a bond pad (128) disposed within a dielectric bond structure (124). The second interconnect structure (112) and the second bond structure (116) may be formed by one or more deposition processes, one or more patterning processes, one or more planarization processes, some other suitable manufacturing process, or any combination thereof. In some embodiments, the second interconnect structure (112) and the second bond structure (116) may be formed as the first interconnect structure (110 in FIG. 9), and the first bond structure (114 in FIG. 9) is formed as illustrated and / or described in FIG. 9.

[0049] As illustrated in the cross-sectional view (1400) of FIG. 14, the first IC chip (102) is flipped and subsequently bonded to the second IC chip (104) so ​​that the first bonding structure (114) and the second bonding structure (116) meet at the bonding interface (105). In some embodiments, the first IC chip (102) is bonded to the second IC chip (104) by a eutectic bond process, a fusion bond process, a metal-to-metal bond process, a dielectric-to-dielectric bond process, some other suitable bond process, or any combination thereof. In various embodiments, bonding the first IC chip (102) to the second IC chip (104) comprises bringing the dielectric bond structures (124) of the first bond structure and the second bond structure (114, 116) into contact with each other, bringing the bond pads (128) of the first bond structure and the second bond structure (114, 116) into contact with each other; and applying pressure to the first IC chip and / or the second IC chip (102, 104). In such embodiments, the temperature of the first bond structure and the second bond structure (114, 116) may be increased to form a bond interface (105).

[0050] As illustrated in the cross-sectional view (1500) of FIG. 15, a thinning process is performed on the first substrate (106). The thinning process includes reducing the first thickness (t1) of the first substrate (106) to a second thickness (t2). In some embodiments, the thinning process includes performing a CMP process, an etching process, a mechanical grinding process, some other thinning process, or any combination thereof.

[0051] As shown in the cross-sectional view (1600) of FIG. 16, a plurality of optical filters (142) are formed on the rear side (106b) of the first substrate (106). The optical filters (142) can be formed by depositing and patterning a color filter layer corresponding to each of the plurality of optical filters (142) (e.g., by CVD, PVD, ALD, etc.).

[0052] As illustrated in the cross-sectional view (1700) of FIG. 17, an upper light guide structure (145) is formed over a plurality of light filters (142). In various embodiments, the upper light guide structure (145) includes a plurality of micro-lenses (144). In such embodiments, the micro-lenses (144) may be formed by depositing a micro-lens material (e.g. by CVD, PVD, ALD, etc.) over the light filters (142) and by patterning the micro-lens material to form a plurality of micro-lenses (144). In other embodiments, the upper light guide structure (145) may be configured as illustrated and / or described in FIG. 4a and FIG. 4b.

[0053] FIGS. 18 through 24 illustrate various cross-sectional views (1800 through 2400) of some embodiments of a method for forming a stacked IC structure comprising a first optical sensor on a second optical sensor, wherein the first optical sensor and the second optical sensor are configured to absorb electromagnetic radiation of different wavelength ranges. The stacked IC structure may correspond, for example, to the stacked IC structure of FIG. 3a. Although the cross-sectional views (1800 through 2400) shown in FIGS. 18 through 24 are described in relation to the method, it will be understood that the structure shown in FIGS. 18 through 24 may be independent of the method rather than being limited to the method. Also, although FIGS. 18 through 24 are described as a series of acts, it will be understood that the disclosed method is also applicable to other structures, in that the order of the acts may be changed in other embodiments. In other embodiments, some acts that are illustrated / illustrated or described may be omitted in whole or in part.

[0054] As illustrated in the cross-sectional view (1800) of FIG. 18, a first substrate (106) is provided, and a first IC chip (102) is formed on the first substrate (106). The first IC chip (102) includes a plurality of first light sensors (129) configured to absorb electromagnetic radiation (e.g., visible light) within a first wavelength range, a first interconnect structure (110) on the first substrate (106), and a first bond structure (114) on the first interconnect structure (110). In various embodiments, the first IC chip (102) is formed as illustrated and / or described in FIGS. 5 through 9.

[0055] As illustrated in the cross-sectional view (1900) of FIG. 19, a patterning process is performed on the first interconnect structure (110) and the first bond structure (114). In some embodiments, the patterning process includes forming a masking layer (1902) over the first bond structure (114), and exposing the dielectric bond structure (124) of the first bond structure (114) and the interconnect dielectric structure (118) of the first interconnect structure (110) to one or more etchants along the masking layer (1902), thereby forming a first light guide opening (1904). The masking layer (1902) may be removed, for example, during and / or after the patterning process. In various embodiments, the patterning process includes performing reactive ion etching, plasma etching, wet etching, etc. In another embodiment, the patterning process exposes an area of ​​the front side (106f) of the first substrate (106).

[0056] As illustrated in the cross-sectional view (2000) of FIG. 20, a plurality of first light guide elements (304) are formed within the first interconnect structure (110) and the first bond structure (114). In various embodiments, a process for forming a plurality of first light guide elements (304) includes depositing a light guide material (e.g., by ALD, PVD, CVD, etc.) within a first light guide opening (1904 in FIG. 19) and performing a planarization process (e.g., CMP process) on the light guide material. The first light guide elements (304) may be, for example, a high k dielectric material (e.g., a dielectric material having a dielectric constant greater than 3.9), titanium oxide (e.g., TiO2), tantalum oxide (e.g., Ta2O5), zirconium oxide (e.g., ZrO2), some other suitable dielectric material, or any combination thereof, or may include these. In another embodiment, the refractive index of the first light guide element (304) is greater than the refractive index of the dielectric bond structure (124) of the first bond structure (114) and the interconnect dielectric structure (118) of the first interconnect structure (110).

[0057] As illustrated in the cross-sectional view (2100) of FIG. 21, a second substrate (108) is provided, and a second IC chip (104) is formed on the second substrate (108). Additionally, a patterning process is performed on the second IC chip (104) to form a plurality of second light guide openings (2104) on the first IC chip (104). The second IC chip (104) includes one or more second light sensors (137) configured to absorb electromagnetic radiation (e.g., IR light, NIR light, SWIR light, etc.) within a second wavelength range, a second interconnect structure (112) on the second substrate (108), and a second bond structure (116) on the second interconnect structure (112). In various embodiments, the second IC chip (104) is formed as illustrated and / or described in FIG. 10 through 13.

[0058] In various embodiments, the patterning process comprises forming a masking layer (2102) over a second bond structure (116), exposing a dielectric bond structure (124) of the second bond structure (116) and an interconnect dielectric structure (118) of the second interconnect structure (112) to one or more etchants along the masking layer (2102), thereby forming a second light guide opening (2104). The masking layer (2102) may be removed, for example, during and / or after the patterning process. In some embodiments, the patterning process comprises performing reactive ion etching, plasma etching, wet etching, etc. In other embodiments, the patterning process exposes an area of ​​the upper surface of the capping layer (140) and / or an area of ​​the front side (108f) of the second substrate (108).

[0059] As illustrated in the cross-sectional view (2200) of FIG. 22, a plurality of second light guide elements (306) are formed within the second interconnect structure (112) and the second bond structure (116). In some embodiments, the process for forming the plurality of second light guide elements (306) includes depositing a light guide material (e.g., by ALD, PVD, CVD, etc.) within the second light guide opening (2104 of FIG. 21) and performing a planarization process (e.g., CMP process) on the light guide material. The second light guide elements (306) may be, for example, a high k dielectric material, titanium oxide (e.g., TiO2), tantalum oxide (e.g., Ta2O5), zirconium oxide (e.g., ZrO2), some other suitable dielectric material, or any combination thereof, or may include these. In various embodiments, the refractive index of the second light guide element (306) is greater than the refractive index of the dielectric bond structure (124) of the second bond structure (116) and the interconnect dielectric structure (118) of the second interconnect structure (112).

[0060] As illustrated in the cross-sectional view (2300) of FIG. 23, the first IC chip (102) is flipped and subsequently bonded to the second IC chip (104) so ​​that the first bonding structure (114) and the second bonding structure (116) meet at the bonding interface (105). In some embodiments, the first IC chip (102) is bonded to the second IC chip (104) by a eutectic bonding process, a fusion bonding process, a metal-to-metal bonding process, a dielectric-to-dielectric bonding process, some other suitable bonding process, or any combination thereof. In other embodiments, bonding the first IC chip (102) to the second IC chip (104) forms a plurality of light guide structures (302), each comprising a corresponding first light guide element (304) and a corresponding second light guide element (306). A plurality of first light guide elements (304) can come into direct contact with a plurality of second light guide elements (306), where the first light guide elements (304) meet the second light guide elements (306) at the dielectric-to-dielectric bond interface.

[0061] Additionally, as shown in the cross-sectional view (2300) of FIG. 23, a thinning process is performed on the first substrate (106) after bonding the first IC chip (102) to the second IC chip (104). The thinning process includes reducing the first thickness (t1) of the first substrate (106) to a second thickness (t2). In various embodiments, the thinning process includes a mechanical grinding process, a CMP process, an etching process, etc.

[0062] As illustrated in the cross-sectional view (2400) of FIG. 24, a plurality of optical filters (142) are formed on the rear side (106b) of the first substrate (106). Additionally, an upper optical guide structure (145) is formed on the plurality of optical filters (142). In some embodiments, the upper optical guide structure (145) includes a plurality of micro-lenses (144).

[0063] FIGS. 25 through 30 illustrate various cross-sectional views (2500 through 3000) of some embodiments of a method for forming a stacked IC structure comprising a first optical sensor on a second optical sensor, wherein the first optical sensor and the second optical sensor are configured to absorb electromagnetic radiation of different wavelength ranges. The stacked IC structure may correspond, for example, to the stacked IC structure of FIG. 3c. Although the cross-sectional views (2500 through 3000) shown in FIGS. 25 through 30 are described in relation to the method, it will be understood that the structure shown in FIGS. 25 through 30 may be independent of the method rather than being limited to the method. Also, although FIGS. 25 through 30 are described as a series of acts, it will be understood that the disclosed method is not limited in that the order of the acts may be changed in other embodiments and that the disclosed method may also be applicable to other structures. In other embodiments, some acts that are illustrated / illustrated or described may be omitted in whole or in part.

[0064] As illustrated in the cross-sectional view (2500) of FIG. 25, an absorption layer (2502) is formed on the front side (108f) of the second substrate (108). The absorption layer (2502) comprises a second semiconductor material (e.g., germanium). In various embodiments, the absorption layer (2502) is formed on the second substrate (108) by an epitaxial growth process such as CVD, PVD, MBE, VPE, LPE, or some other suitable growth or deposition process. In some embodiments, the absorption layer (2502) comprises a first doping type (e.g., p-type).

[0065] As illustrated in the cross-sectional view (2600) of FIG. 26, a patterning process is performed on the absorption layer (2502 of FIG. 25) to remove a portion of the absorption layer (2502 of FIG. 25) and to form an absorption structure (138). Additionally, a capping layer (140) is formed on the absorption structure (138), and a dielectric layer (308) is formed on the second substrate (108). In some embodiments, the patterning process includes forming a masking layer (not shown) on the absorption layer (2502 of FIG. 25) and exposing the absorption layer (2502 of FIG. 25) to one or more etchants along the masking layer. The capping layer (140) may be formed on the absorption structure (138) by, for example, CVD, PVD, MBE, VPE, LPE, or some other suitable growth or deposition process. The dielectric layer (308) can be formed on the second substrate (108) by, for example, CVD, PVD, ALD, or some other suitable growth or deposition process.

[0066] As illustrated in the cross-sectional view (2700) of FIG. 27, a first doping region and a second doping region (135, 136) are formed in the absorption structure (138) and thereby define one or more second optical sensors (137). The first doping region and the second doping region (135, 136) may be formed as illustrated and / or described in FIG. 12.

[0067] As illustrated in the cross-sectional view (2800) of FIG. 28, a second interconnect structure (112) is formed on the absorption structure (138), and a second bond structure (116) is formed on the second interconnect structure (112), thereby defining a second IC chip (104). The second interconnect structure (112) and the second bond structure (116) may be formed as illustrated and / or described in FIG. 12 and / or FIG. 13.

[0068] As illustrated in the cross-sectional view (2900) of FIG. 29, a first IC chip (102) is provided and subsequently bonded to a second IC chip (104). The first IC chip (102) may be formed as illustrated and / or described in FIG. 5 through 9. Additionally, a thinning process is performed to reduce the first thickness (t1) of the first substrate (106) to a second thickness (t2).

[0069] As illustrated in the cross-sectional view (3000) of FIG. 30, a plurality of optical filters (142) are formed on the rear side (106b) of the first substrate (106). Additionally, an upper optical guide structure (145) is formed on the plurality of optical filters (142). In some embodiments, the upper optical guide structure (145) includes a plurality of micro-lenses (144).

[0070] FIGS. 31 through 35 illustrate various cross-sectional views (3100 through 3500) of some embodiments of a method for forming a stacked IC structure comprising a first optical sensor on a second optical sensor, wherein the first optical sensor and the second optical sensor are configured to absorb electromagnetic radiation of different wavelength ranges. The stacked IC structure may correspond, for example, to the stacked IC structure of FIG. 3b. Although the cross-sectional views (3100 through 3500) shown in FIGS. 31 through 35 are described in relation to the method, it will be understood that the structure shown in FIGS. 31 through 35 may be independent of the method rather than being limited to the method. Also, although FIGS. 31 through 35 are described as a series of acts, it will be understood that the disclosed method is also applicable to other structures, in that the order of the acts may be changed in other embodiments. In other embodiments, some acts that are illustrated / illustrated or described may be omitted in whole or in part.

[0071] As illustrated in the cross-sectional view (3100) of FIG. 31, a second substrate (108) is provided, and a second IC chip (104) is formed on the second substrate (108). The second IC chip (104) comprises one or more second light sensors (137) configured to absorb electromagnetic radiation (e.g., IR light, NIR light, SWIR light, etc.) within a second wavelength range, a second interconnect structure (112) on the second substrate (108), and a second bond structure (116) on the second interconnect structure (112). Additionally, a masking layer (3102) is formed on the second bond structure (116). In various embodiments, the second IC chip (104) is formed as illustrated and / or described in FIG. 25 through 28.

[0072] As illustrated in the cross-sectional view (3200) of FIG. 32, an etching process is performed on the second IC chip (104) to form a plurality of second light guide openings (3202). In various embodiments, the etching process is performed along the masking layer (3102) and includes performing reactive ion etching, plasma etching, wet etching, some other suitable etching, etc. In some embodiments, the masking layer (3102) is removed during and / or after the etching process.

[0073] As illustrated in the cross-sectional view (3300) of FIG. 33, a plurality of second light guide elements (306) are formed within the second interconnect structure (112) and the second bond structure (116). In some embodiments, the process for forming the plurality of second light guide elements (306) includes depositing a light guide material (e.g., high-k dielectric material, titanium oxide, tantalum oxide, zirconium oxide, etc.) within the second light guide opening (3202 in FIG. 32) (e.g., by ALD, PVD, CVD, etc.) and performing a planarization process (e.g., CMP process) on the light guide material.

[0074] As illustrated in the cross-sectional view (3400) of FIG. 34, a first IC chip (102) is provided and subsequently bonded to a second IC chip (104) so ​​that the first bond structure and the second bond structure meet at a bond interface (105). The first IC chip (102) may be formed as illustrated and / or described in FIG. 18 through 20. In some embodiments, the first IC chip (102) is bonded to the second IC chip (104) by a eutectic bonding process, a fusion bonding process, a metal-to-metal bonding process, a dielectric-to-dielectric bonding process, some other suitable bonding process, or any combination thereof. Additionally, bonding the first IC chip (102) to the second IC chip (104) forms a plurality of light guide structures (302), each comprising a corresponding first light guide element (304) and a corresponding second light guide element (306).

[0075] As illustrated in the cross-sectional view (3500) of FIG. 35, a plurality of light filters (142) are formed on the rear side (106b) of the first substrate (106), and an upper light guide structure (145) is formed on the plurality of light filters (142). In some embodiments, the upper light guide structure (145) includes a plurality of micro lenses (144).

[0076] FIG. 36 illustrates a flowchart of some embodiment of a method (3600) for forming a stacked IC structure comprising a first optical sensor on a second optical sensor, wherein the first optical sensor and the second optical sensor are configured to absorb electromagnetic radiation of different wavelength ranges. It will be understood that while the method (3600) is illustrated and / or described as a series of acts or events, the method is not limited to the illustrated order or acts. Accordingly, in some embodiments, acts may be executed in a different order than illustrated and / or simultaneously. Also, in some embodiments, the illustrated acts or events may be subdivided into multiple acts or events that may be executed at separate times or simultaneously with other acts or sub-acts. In some embodiments, some illustrated acts or events may be omitted, and other unillustrated acts or events may be included.

[0077] In the act (3602), a plurality of first light sensors are formed on a first substrate having a first semiconductor material, wherein the first light sensors are configured to absorb electromagnetic radiation within a first wavelength range. FIG. 5 illustrates a cross-sectional view (500) corresponding to various embodiments of the act (3602).

[0078] In the act (3604), a first interconnect structure is formed on the front side of the substrate. FIGS. 8 and 9 illustrate cross-sectional views (800 and 900) corresponding to various embodiments of the act (3604).

[0079] In Act (3606), a first bond structure is formed on a first interconnect structure, thereby forming a first IC chip. In some embodiments, a plurality of first light guide elements are formed on the first interconnect structure and the first bond structure. FIG. 9 illustrates a cross-sectional view (900) corresponding to various embodiments of Act (3606). FIG. 18 to 20 illustrate cross-sectional views (1800 to 2000) corresponding to some other embodiments of Act (3606).

[0080] In the act (3608), an absorption structure is formed in and / or on a second substrate, and one or more doping regions are formed in the absorption structure, thereby forming one or more second light sensors configured to absorb electromagnetic radiation within a second wavelength range different from a first wavelength range. The absorption structure comprises a second semiconductor material different from a first semiconductor material. FIGS. 10 to 12 illustrate cross-sectional views (1000 to 1200) corresponding to some embodiments of the act (3608). FIGS. 25 to 27 illustrate cross-sectional views (2500 to 2700) corresponding to some other embodiments of the act (3608).

[0081] In the act (3610), a second interconnect structure is formed on the front side of the substrate. FIGS. 12 and FIGS. 13 illustrate cross-sectional views (1200 and 1300) corresponding to various embodiments of the act (3610).

[0082] In Act (3612), a second bond structure is formed on a second interconnect structure, thereby forming a second IC chip. In some embodiments, a plurality of second light guide elements are formed on the second interconnect structure and the second bond structure. FIG. 13 illustrates a cross-sectional view (1300) corresponding to various embodiments of Act (3612). FIG. 21 and FIG. 22 illustrate cross-sectional views (2100 and 2200) corresponding to some other embodiments of Act (3612). FIG. 31 through 33 illustrate cross-sectional views (3100 through 3300) corresponding to yet another embodiment of Act (3612).

[0083] In Act (3614), the first IC chip is bonded to the second IC chip. FIG. 14 illustrates a cross-sectional view (1400) corresponding to various embodiments of Act (3614). FIG. 23 illustrates a cross-sectional view (2300) corresponding to some embodiments of Act (3614). FIG. 29 illustrates a cross-sectional view (2900) corresponding to some other embodiments of Act (3614). FIG. 34 illustrates a cross-sectional view (3400) corresponding to yet another embodiment of Act (3614).

[0084] In the act (3616), a plurality of optical filters and an upper optical guide structure are formed on the rear side of the first substrate. FIGS. 16 and 17 illustrate cross-sectional views (1600 and 1700) corresponding to some embodiments of the act (3616). FIG. 24 illustrates a cross-sectional view (2400) corresponding to various embodiments of the act (3616). FIG. 30 illustrates a cross-sectional view (3000) corresponding to some other embodiments of the act (3616). FIG. 35 illustrates a cross-sectional view (3500) corresponding to yet another embodiment of the act (3616).

[0085] Accordingly, in some embodiments, the present disclosure relates to a stacked IC structure comprising a first IC chip having a first optical sensor and a second IC chip bonded to the first IC chip and comprising a second optical sensor, wherein the first optical sensor and the second optical sensor are configured to absorb electromagnetic radiation of different wavelength ranges.

[0086] In some embodiments, the present application provides a semiconductor structure comprising: a first substrate comprising a first semiconductor material; a first optical sensor disposed within the first substrate—the first optical sensor is configured to absorb electromagnetic radiation within a first wavelength range—; and a second optical sensor disposed within an absorption structure beneath the first substrate—the second optical sensor is configured to absorb electromagnetic radiation within a second wavelength range different from the first wavelength range, and the absorption structure is beneath the first optical sensor and comprises a second semiconductor material different from the first semiconductor material. In an embodiment, the first optical sensor comprises a doped photodetector region within the first substrate, and the doped photodetector region is spaced apart between the two sidewalls of the absorption structure. In an embodiment, the second optical sensor comprises a first doped region and a second doped region disposed within the absorption structure, and the doped photodetector region is laterally spaced between the first doped region and the second doped region. In an embodiment, the semiconductor structure comprises a second substrate beneath the first substrate—the absorption structure is disposed within or on the second substrate—; It further comprises a first interconnect structure disposed on the front side surface of a first substrate; and a second interconnect structure disposed on the front side surface of a second substrate—the first interconnect structure is electrically coupled to the second interconnect structure—; the first interconnect structure and the second interconnect structure each comprise a plurality of conductive wires and a plurality of conductive vias disposed within a dielectric structure, and the conductive wires and conductive vias of the first interconnect structure and the second interconnect structure are completely laterally offset from a light guide region that extends continuously vertically from a first light sensor to a second light sensor.In an embodiment, the semiconductor structure further comprises: a first light guide element disposed in a first interconnect structure and spaced apart within an upper portion of a light guide region; and a second light guide element disposed in a second interconnect structure and spaced apart within a lower portion of a light guide region—the first light guide element is in direct contact with the second light guide element. In an embodiment, the width of the first light guide element continuously increases in a first direction toward the second substrate from the front side of the first substrate, and the width of the second light guide element continuously decreases in a first direction from the bottom surface of the first light guide element. In an embodiment, the first light guide element is in direct contact with the first substrate, a capping layer is disposed on an absorption structure, and the second light guide element is in direct contact with the capping layer. In an embodiment, the semiconductor structure further comprises a plurality of light filters on the first substrate; and a plurality of lenses disposed on the light filters.

[0087] In some embodiments, the present application provides a stacked integrated chip (IC) structure comprising: a first IC chip comprising a first interconnect structure disposed on the front side of a first substrate, a plurality of first optical sensors disposed on the first substrate, and a first bond structure on the first interconnect structure—the first substrate comprises silicon, and the first optical sensors each comprise a doped photodetector region of the first substrate—; and a second IC chip located below the first IC chip—the second IC chip comprises a second interconnect structure disposed on the front side of a second substrate, a plurality of second optical sensors disposed on the second substrate, and a second bond structure on the second interconnect structure, wherein a bond interface is disposed between the first IC chip and the second IC chip, and the second optical sensors each comprise one or more doped regions disposed within a germanium structure. In an embodiment, one or more doped regions are electrically coupled to the first interconnect structure by the second interconnect structure and the second bond structure. In an embodiment, the germanium structure is disposed within a second substrate and has a top surface recessed below the front side of the second substrate. In an embodiment, the stacked IC structure further comprises a capping layer disposed along the top surface of the germanium structure—the capping layer comprises silicon. In an embodiment, the stacked IC structure further comprises a plurality of optical pipe structures disposed within the first IC chip and the second IC chip—the optical pipe structures extend vertically from the first substrate to the second optical sensor. In an embodiment, the height of the optical pipe structures is at least equal to the distance between the front side of the first substrate and the front side of the second substrate. In an embodiment, the stacked IC structure further comprises a plurality of floating diffusion nodes disposed within the first substrate—the floating diffusion nodes are adjacent to the corresponding doped photodetector region—and a plurality of pixel devices disposed on the front side of the first substrate—the plurality of pixel devices are located directly above the germanium structure.

[0088] In various embodiments, the present application provides a method for forming a stacked integrated chip (IC) structure, the method comprising: doping a first substrate to form a plurality of first optical sensors within the first substrate, wherein the first optical sensors are configured to absorb electromagnetic radiation within a first wavelength range; forming a first interconnect structure on the front side of the first substrate; forming a first bond structure on the first interconnect structure; forming a plurality of second optical sensors within a second substrate, wherein the plurality of second optical sensors are configured to absorb electromagnetic radiation within a second wavelength range different from the first wavelength range; forming a second interconnect structure on the front side of the second substrate; forming a second bond structure on the second interconnect structure; and performing a bonding process to bond the first bond structure to the second bond structure, wherein the first optical sensors are located directly above the second optical sensors. In an embodiment, the step of forming the second optical sensors comprises forming an absorption structure on the second substrate; The method includes the step of doping the absorption structure to form a first doping region vertically separated from a second doping region within the absorption structure. In an embodiment, the step of forming the absorption structure includes the step of etching the second substrate to form a recess extending into the front side of the second substrate; and the step of depositing the absorption structure within the recess. In an embodiment, the step of forming the absorption structure includes the step of depositing an absorption layer along the front side of the second substrate; the step of etching the absorption layer to define the absorption structure thereby; and the step of depositing a dielectric layer on the second substrate and around the absorption structure.In an embodiment, the method further comprises the steps of: forming a plurality of first light guide elements within a first interconnect structure and a first bond structure; and forming a plurality of second light guide elements within a second interconnect structure and a second bond structure, and after the bonding process, the plurality of first light guide elements meet the plurality of second light guide elements at the dielectric-to-dielectric bond interface.

[0089] The foregoing describes an overview of the features of some embodiments to enable those skilled in the art to better understand the aspects of the present disclosure. Those skilled in the art should understand that they can readily use the present disclosure as a basis for designing or modifying other processes and structures to perform the same purpose or achieve the same advantages as the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent configurations do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and modifications to the present disclosure without departing from the spirit and scope of the present disclosure.

[0090] Examples

[0091] Example 1. In a semiconductor structure,

[0092] A first substrate comprising a first semiconductor material;

[0093] A first optical sensor disposed within the first substrate - the first optical sensor is configured to absorb electromagnetic radiation within a first wavelength range - ; and

[0094] A second optical sensor disposed within an absorption structure located beneath the first substrate—the second optical sensor is configured to absorb electromagnetic radiation within a second wavelength range different from the first wavelength range, and the absorption structure is located beneath the first optical sensor and includes a second semiconductor material different from the first semiconductor material.

[0095] A semiconductor structure including

[0097] Example 2. A semiconductor structure in Example 1, wherein the first optical sensor comprises a doped photodetector region within the first substrate, and the doped photodetector region is spaced apart between the two sidewalls of the absorption structure.

[0099] Example 3. The semiconductor structure of Example 2, wherein the second optical sensor comprises a first doping region and a second doping region disposed within the absorption structure, and the doped photodetector region is laterally spaced between the first doping region and the second doping region.

[0101] Example 4. In Example 1,

[0102] A second substrate located below the first substrate - the absorption structure is disposed within or on the second substrate - ;

[0103] A first interconnect structure disposed on the front-side surface of the first substrate; and

[0104] A second interconnect structure disposed on the front side of the second substrate - the first interconnect structure is electrically coupled to the second interconnect structure -

[0105] Includes more of;

[0106] A semiconductor structure wherein the first interconnect structure and the second interconnect structure each comprise a plurality of conductive wires and a plurality of conductive vias disposed within a dielectric structure, and the conductive wires and conductive vias of the first interconnect structure and the second interconnect structure are completely laterally offset from a light guide region that extends continuously vertically from the first light sensor to the second light sensor.

[0108] Example 5. In Example 4,

[0109] A first light guide element disposed in the first interconnected structure and spaced apart within the upper portion of the light guide region; and

[0110] A second light guide element disposed in the second interconnected structure and spaced apart within the lower portion of the light guide area - the first light guide element is in direct contact with the second light guide element -

[0111] A semiconductor structure that further includes

[0113] Example 6. A semiconductor structure in Example 5, wherein the width of the first light guide element continuously increases in a first direction toward the second substrate from the front side of the first substrate, and the width of the second light guide element continuously decreases in the first direction from the bottom surface of the first light guide element.

[0115] Example 7. A semiconductor structure in Example 5, wherein the first light guide element is in direct contact with the first substrate, a capping layer is disposed on the absorption structure, and the second light guide element is in direct contact with the capping layer.

[0117] Example 8. In Example 1,

[0118] A plurality of optical filters on the first substrate; and

[0119] A plurality of lenses disposed on the above light filter

[0120] A semiconductor structure that further includes

[0122] Example 9. In a stacked integrated chip (IC) structure,

[0123] A first IC chip comprising a first interconnect structure disposed on the front side surface of a first substrate, a plurality of first optical sensors disposed on the first substrate, and a first bond structure on the first interconnect structure - the first substrate comprises silicon, and the first optical sensors each comprise a doped photodetector region of the first substrate - ; and

[0124] A second IC chip located below the first IC chip - the second IC chip comprises a second interconnect structure disposed on the front side of a second substrate, a plurality of second optical sensors disposed on the second substrate, and a second bond structure on the second interconnect structure, wherein a bond interface is disposed between the first IC chip and the second IC chip, and each of the second optical sensors comprises one or more doping regions disposed within a germanium structure.

[0125] A stacked integrated chip (IC) structure including

[0127] Example 10. A stacked integrated chip (IC) structure in which, in Example 9, one or more doping regions are electrically coupled to the first interconnect structure by the second interconnect structure and the second bond structure.

[0129] Example 11. A stacked integrated chip (IC) structure in Example 9, wherein the germanium structure is disposed within the second substrate and has a recessed top surface below the front side surface of the second substrate.

[0131] Example 12. In Example 11,

[0132] A stacked integrated chip (IC) structure further comprising a capping layer disposed along the uppermost surface of the germanium structure—the capping layer comprising silicon.

[0134] Example 13. In Example 9,

[0135] A stacked integrated chip (IC) structure further comprising a plurality of optical pipe structures disposed within the first IC chip and the second IC chip, wherein the optical pipe structures extend vertically from the first substrate to the second optical sensor.

[0137] Example 14. A stacked integrated chip (IC) structure in Example 13, wherein the height of the optical pipe structure is at least equal to the distance between the front side of the first substrate and the front side of the second substrate.

[0139] Example 15. In Example 9,

[0140] A plurality of floating diffusion nodes disposed within the first substrate - said floating diffusion nodes are adjacent to a corresponding doped photodetector region - ; and

[0141] A plurality of pixel devices disposed on the front side of the first substrate - the plurality of pixel devices are located directly above the germanium structure -

[0142] A stacked integrated chip (IC) structure further comprising

[0144] Example 16. A method for forming a stacked integrated chip (IC) structure, wherein

[0145] A step of doping a first substrate to form a plurality of first optical sensors within the first substrate - the first optical sensors are configured to absorb electromagnetic radiation within a first wavelength range - ;

[0146] A step of forming a first interconnected structure on the front side surface of the first substrate;

[0147] A step of forming a first bond structure on the first interconnected structure;

[0148] A step of forming a plurality of second optical sensors within a second substrate - the plurality of second optical sensors are configured to absorb electromagnetic radiation within a second wavelength range different from the first wavelength range - ;

[0149] A step of forming a second interconnected structure on the front side surface of the second substrate;

[0150] A step of forming a second bond structure on the second interconnect structure; and

[0151] A step of performing a bonding process to bond the first bond structure to the second bond structure - the first optical sensor is located directly above the second optical sensor -

[0152] A method for forming a stacked integrated chip (IC) structure including

[0154] Example 17. In Example 16, the step of forming the second optical sensor is,

[0155] A step of forming an absorption structure on the second substrate; and

[0156] Step of doping the absorption structure to form a first doping region vertically separated from a second doping region within the absorption structure

[0157] A method that includes

[0159] Example 18. In Example 17, the step of forming the absorption structure is,

[0160] A step of etching the second substrate to form a recess extending into the front side of the second substrate; and

[0161] Step of depositing the absorption structure within the above recess

[0162] A method that includes

[0164] Example 19. In Example 17, the step of forming the absorption structure is,

[0165] A step of depositing an absorption layer along the front side of the second substrate;

[0166] A step of etching the absorption layer and thereby defining the absorption structure; and

[0167] Step of depositing a dielectric layer on the second substrate and around the absorption structure

[0168] A method that includes

[0170] Example 20. In Example 16,

[0171] A step of forming a plurality of first light guide elements within the first interconnect structure and the first bond structure; and

[0172] A step of forming a plurality of second light guide elements within the second interconnect structure and the second bond structure.

[0173] Includes more,

[0174] A method in which, after the bonding process, the plurality of first light guide elements meet the plurality of second light guide elements at the dielectric-to-dielectric bond interface.

Claims

Claim 1 A semiconductor structure comprising: a first substrate including a first semiconductor material; a first optical sensor disposed within the first substrate, wherein the first optical sensor is configured to absorb electromagnetic radiation within a first wavelength range; and a second optical sensor disposed within an absorption structure located below the first substrate, wherein the second optical sensor is configured to absorb electromagnetic radiation within a second wavelength range different from the first wavelength range, and the absorption structure is located below the first optical sensor and includes a second semiconductor material different from the first semiconductor material; wherein the first semiconductor material includes silicon and the second semiconductor material includes germanium. Claim 2 A semiconductor structure according to claim 1, wherein the first optical sensor comprises a doped photodetector region within the first substrate, and the doped photodetector region is spaced apart between the two sidewalls of the absorption structure. Claim 3 A semiconductor structure according to paragraph 2, wherein the second optical sensor comprises a first doping region and a second doping region disposed within the absorption structure, and the doped photodetector region is laterally spaced between the first doping region and the second doping region. Claim 4 A semiconductor structure according to claim 1, further comprising: a second substrate located below the first substrate—wherein the absorption structure is disposed within or on the second substrate—; a first interconnect structure disposed on the front-side surface of the first substrate; and a second interconnect structure disposed on the front-side surface of the second substrate—wherein the first interconnect structure is electrically coupled to the second interconnect structure—wherein the first interconnect structure and the second interconnect structure each comprise a plurality of conductive wires and a plurality of conductive vias disposed within a dielectric structure, and the conductive wires and conductive vias of the first interconnect structure and the second interconnect structure are completely laterally offset from a light guide region that extends continuously vertically from the first light sensor to the second light sensor. Claim 5 A semiconductor structure according to claim 4, further comprising: a first light guide element disposed in the first interconnection structure and spaced apart within the upper portion of the light guide region; and a second light guide element disposed in the second interconnection structure and spaced apart within the lower portion of the light guide region, wherein the first light guide element is in direct contact with the second light guide element. Claim 6 A semiconductor structure according to claim 5, wherein the width of the first light guide element continuously increases in a first direction toward the second substrate from the front side of the first substrate, and the width of the second light guide element continuously decreases in the first direction from the bottom surface of the first light guide element. Claim 7 A semiconductor structure according to claim 5, wherein the first light guide element is in direct contact with the first substrate, a capping layer is disposed on the absorption structure, and the second light guide element is in direct contact with the capping layer. Claim 8 A semiconductor structure according to claim 1, further comprising: a plurality of optical filters on the first substrate; and a plurality of lenses disposed on the optical filters. Claim 9 A stacked integrated chip (IC) structure comprising: a first IC chip comprising a first interconnect structure disposed on the front side of a first substrate, a plurality of first optical sensors disposed on the first substrate, and a first bond structure on the first interconnect structure, wherein the first substrate comprises silicon and the first optical sensors each comprise a doped photodetector region of the first substrate; and a second IC chip located below the first IC chip, wherein the second IC chip comprises a second interconnect structure disposed on the front side of a second substrate, a plurality of second optical sensors disposed on the second substrate, and a second bond structure on the second interconnect structure, wherein a bond interface is disposed between the first IC chip and the second IC chip, and the second optical sensors each comprise one or more doped regions disposed within a germanium structure. Claim 10 A method for forming a stacked integrated chip (IC) structure comprising: a step of doping a first substrate to form a plurality of first optical sensors within the first substrate, wherein the first optical sensors are configured to absorb electromagnetic radiation within a first wavelength range; a step of forming a first interconnect structure on the front side of the first substrate; a step of forming a first bond structure on the first interconnect structure; a step of forming a plurality of second optical sensors within a second optical sensor, wherein the plurality of second optical sensors are configured to absorb electromagnetic radiation within a second wavelength range different from the first wavelength range; a step of forming a second interconnect structure on the front side of the second substrate; a step of forming a second bond structure on the second interconnect structure; and a step of performing a bonding process to bond the first bond structure to the second bond structure, wherein the first optical sensor is located directly above the second optical sensor.

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