Image Sensor For Distance Measuring And Camera Module Including The Same

Abstract

An image sensor is disclosed. The image sensor comprises: a demodulation clock generating circuit that generates first to fourth demodulation clock signals each having first to fourth phases; a demodulation phase selecting circuit that receives the first to fourth demodulation clock signals and generates first to fourth pre-demolding signals according to a random number; a delay circuit that generates a plurality of first to fourth delay signals by delaying each of the first to fourth pre-demolding signals by a plurality of delay phases; and a phase mixer that receives the plurality of first to fourth delay signals and generates a plurality of first to fourth demodulation signals whose phases change according to an address that changes per packet, wherein the first to fourth phases have a phase difference of 90 degrees from each other.

Description

Technology Field

[0001] The present invention relates to an image sensor, and more specifically, to an image sensor for distance measurement and a camera module including the same. Background Technology

[0002] Time-of-Flight (ToF)-based image sensors can generate three-dimensional images of objects by measuring information regarding the distance to the object. ToF-based image sensors obtain information about the distance to an object by measuring the time it takes for light to travel from an object to it until the reflected light is received. Since distance information contains noise due to various factors, efforts to minimize noise are required to obtain accurate information. The problem to be solved

[0003] The technical problem of the present invention is to provide an image sensor for distance measurement capable of reducing readout noise and a camera module including the same. means of solving the problem

[0004] The image sensor of the present disclosure comprises, to solve the above problem, a demodulation clock generation circuit that generates first to fourth demodulation clock signals having first to fourth phases respectively, a demodulation phase selection circuit that receives the first to fourth demodulation clock signals and generates first to fourth pre-demolding signals according to a random number, a delay circuit that generates a plurality of first to fourth delay signals by delaying each of the first to fourth pre-demolding signals by a plurality of delay phases, and a phase mixer that receives the plurality of first to fourth delay signals and generates a plurality of first to fourth demodulation signals whose phases change according to an address that changes per packet, and the first to fourth phases may have a phase difference of 90 degrees from each other.

[0005] In addition, the image sensor of the present disclosure comprises a pixel array including a first pixel group and a second pixel group, and a control circuit that provides a modulation signal to a light source and provides a plurality of first to fourth demodulation signals to the pixel array, the phases of which change according to a random number and an address, wherein each of the first to fourth demodulation signals provided to the first pixel group has a phase different from each of the first to fourth demodulation signals provided to the second pixel group, the light collection time defining one frame is composed of a plurality of packets, and the random number and address can be changed when the packet is changed.

[0006] Additionally, the camera module according to the present disclosure includes a light source unit that transmits a light signal to an object, and an image sensor that receives a light signal reflected from the object. The image sensor further includes a pixel array comprising a plurality of unit pixels, a control circuit that provides a modulation signal to the light source unit, and provides a plurality of first to fourth demodulation signals to the pixel array whose phases change according to a random number and an address. The light collection time defining a frame is composed of a plurality of packets, and the random number and address may change when the packet changes. Effects of the invention

[0007] An image sensor according to the present disclosure generates modulation signals and demodulation signals according to a random number, and a light source is driven according to the modulation signal and an image sensor is driven according to the demodulation signals. A received signal from another image sensor for distance measurement can be converged into a random noise component and removed. Accordingly, readout noise caused by another camera module can be reduced.

[0008] In addition, the image sensor generates multiple demodulation signals to receive demodulation signals with different delay phases for each pixel group. Accordingly, the peak current of the multiple demodulation signals can be reduced, and noise associated with the peak current can be reduced. Brief explanation of the drawing

[0009] FIG. 1 is a schematic diagram of a system according to an exemplary embodiment of the present disclosure. FIG. 2 is a configuration diagram for explaining a camera module according to an exemplary embodiment of the present disclosure. FIG. 3 is a drawing for explaining an exemplary embodiment of the structure of a unit pixel shown in FIG. 2. FIG. 4 is a block diagram for explaining a control circuit included in an image sensor according to the present disclosure. Figure 5 is a block diagram illustrating the demodulation phase selection circuit of Figure 4. FIG. 6a is a timing diagram for explaining modulation signals and multiple pre-demolding signals according to random numbers. FIG. 6b is a timing diagram for explaining delay signals generated in a delay circuit of an image sensor according to the present disclosure. FIG. 7 is a block diagram illustrating a pixel array of an image sensor according to the present disclosure. FIG. 8 is a timing diagram for explaining the first to fourth demodulation signals provided to a pixel array according to an address. FIG. 9 is a diagram illustrating a first demodulation signal provided to each of a plurality of pixel groups included in a pixel array. FIG. 10 is a timing diagram for explaining the operation of an image sensor including a unit pixel of a 4-tap structure according to the present disclosure. FIG. 11 is a drawing for explaining an exemplary embodiment of the structure of a unit pixel shown in FIG. 2. FIGS. 12 and FIGS. 13 are timing diagrams for explaining the operation of an image sensor including a unit pixel of a 2-tap structure according to the present disclosure. FIG. 14 is a schematic diagram showing an image sensor according to an exemplary embodiment of the present disclosure. Specific details for implementing the invention

[0010] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the attached drawings.

[0011] FIG. 1 is a schematic diagram of a system according to an exemplary embodiment of the present disclosure.

[0012] Referring to FIG. 1, the system (10) may include a processor (30) and a camera module (100). The system (10) may further include a memory module (20) connected to the processor (30) to store information, such as image data received from the camera module (100). In an exemplary embodiment, the system (10) may be integrated on a single semiconductor chip, and the camera module (100), the processor (30), and the memory module (20) may each be implemented as separate semiconductor chips. The memory module (20) may include one or more memory chips. In an exemplary embodiment, the processor (30) may include multiple processing chips.

[0013] The system (10) may be an electronic device for the application of an image sensor for distance measurement according to an embodiment of the present disclosure. The system (10) may be portable or stationary. Examples of the portable form of the system (10) may include a mobile device, a mobile phone, a smartphone, a user device (UE), a tablet, a digital camera, a laptop or desktop computer, an electronic smartwatch, an M2M (Machine-to-Machine) communication device, a virtual reality (VR) device or module, a robot, etc. Examples of the stationary form of the system (10) may include a game console in a video game room, an interactive video terminal, a car, a machine vision system, an industrial robot, a virtual reality (VR) device, a driver-side camera in a car, etc.

[0014] The camera module (100) may include a light source unit (12) and an image sensor (14). The light source unit (12) can transmit a transmitted light signal (TX) to an object (200). The transmitted light signal (TX) output from the light source unit (12) may be reflected by the object (200), and the image sensor (14) may receive a received light signal (RX) reflected from the object (200). The image sensor (14) can obtain depth information, which is distance information for the object (200), using the Time-Of-Flight (TOF).

[0015] The light source unit (12) may include a light source and a light source driver that drives the light source. The image sensor (14) may include a pixel array, a control circuit that drives the pixel array, and a readout circuit that reads out a pixel signal output from the pixel array.

[0016] The processor (30) may be a general-purpose processor, such as a central processing unit (CPU). In an exemplary embodiment, the processor (30) may further include, in addition to the central processing unit, a microcontroller, a digital signal processor (DSP), a graphic processing unit (GPU), a dedicated application-specific integrated circuit (ASIC) processor, etc. Additionally, the processor (30) may include more than one central processing unit operating in a distributed processing environment. In an exemplary embodiment, the processor (30) may be a system on chip (SoC) having additional functions to the functions of the central processing unit.

[0017] The processor (30) can control the operations of the light source unit (12) and the image sensor (14). In an exemplary embodiment, the system (10) may be equipped with a mode switch that is controlled by a user and switches between a two-dimensional imaging mode and a three-dimensional imaging mode. When the user selects the two-dimensional imaging mode using the mode switch, the processor (30) activates the image sensor (14), and since the two-dimensional imaging mode uses ambient light, the light source unit (12) may not be activated.

[0018] When a user selects a 3D imaging mode using a mode switch, the processor (30) can activate both the light source unit (12) and the image sensor (14). Processed image data received from the read-out circuit (46) can be stored in the memory module (20) by the processor (30). The processor (30) can display the 2D or 3D image selected by the user on the display screen of the system (10). The processor (30) can be programmed with software or firmware to perform the various processing tasks described. In an exemplary embodiment, the processor (30) may include programmable hardware logic circuits to perform some or all of the aforementioned functions. For example, the memory module (20) may store program code, lookup tables, or intermediate operation results to enable the processor (30) to perform the corresponding functions.

[0019] The memory module (20) may be a DRAM (Dynamic Random Access Memory) such as SDRAM (Synchronous DRAM), an HBM (High Bandwidth Memory) module, or a DRAM-based 3DS (3-Dimensional Stack) memory module such as an HMC (Hybrid Memory Cube) memory module. The memory module (20) may be a semiconductor-based storage such as an SSD (Solid State Drive), a DRAM module, or SRAM (Static Random Access Memory), PRAM (Phase-Change Random Access Memory), RRAM (Resistive Random Access Memory), CBRAM (Conductive-Bridging RAM), MRAM (Magnetic RAM), STT-MRAM (Spin-Transfer Torque MRAM), etc.

[0020] FIG. 2 is a configuration diagram for explaining a camera module according to an exemplary embodiment of the present disclosure.

[0021] Referring to FIGS. 1 and 2, a camera module (100) may be used to obtain distance information for an object (200). The distance information may be calculated by a processor (30) based on image data (IDATA) output from an image sensor (14), or it may be calculated internally within the image sensor (14). In an exemplary embodiment, the distance information may be used by the processor (30) as part of a three-dimensional user interface to enable a user of the system (10) to interact with or use a three-dimensional image of the object (200) as part of a game or other application running on the system (10).

[0022] The light source unit (12) may include a light source driver (140) and a light source (150). The light source unit (12) may further include a lens.

[0023] A light source (150) can transmit a transmitted light signal (TX) to an object (200). The light source (150) may be a combination of a laser diode (LD) or light-emitting diode (LED) emitting infrared or visible light, a near-infrared laser (NIR), a point light source, a monochromatic light source combining a white lamp and a monochromator, or other laser light sources. For example, the light source (150) may be a vertical-cavity surface-emitting laser (or VCSEL). In an exemplary embodiment, the light source (150) may output a transmitted light signal (TX) of infrared having a wavelength of 800 nm to 1000 nm.

[0024] The light source driver (140) can generate a driving signal to drive the light source (150). The light source driver (140) can drive the light source (150) in response to a modulation signal (MOD) received from the control circuit (120).

[0025] The image sensor (14) can measure distance or depth using the TOF principle. The image sensor (14) can receive a received light signal (RX) reflected from an object (200). The image sensor (14) may include a pixel array (110), a control circuit (120), and a readout circuit (130). The image sensor (14) may further include a lens, and the received light signal (RX) may be provided to the pixel array (110) through the lens.

[0026] The pixel array (110) may include a plurality of unit pixels (111). The plurality of unit pixels (111) may operate in a TOF manner. The structure of each of the plurality of unit pixels (111) will be described later in FIG. 3, etc.

[0027] The pixel array (110) may be an RGB pixel array in which different pixels collect different colors of light. The pixel array (110) may be a two-dimensional sensor, such as a two-dimensional RGB sensor with an infrared (IR) blocking filter, a two-dimensional infrared (IR) sensor, a two-dimensional near-infrared (NIR) sensor, a two-dimensional RGBW sensor, a two-dimensional RGB-IR sensor, etc. The system (10) may use the same pixel array (110) not only to measure the distance to an object (200) but also for imaging the two-dimensional RGB color of the object (200) (or the scene containing the object).

[0028] The pixel array (110) can convert the received optical signal (RX) into corresponding electrical signals, i.e., pixel signals. The readout circuit (130) can generate image data (IDATA) based on the pixel signals output from the pixel array (110). For example, the readout circuit (130) can perform analog-to-digital conversion on the pixel signals.

[0029] The image sensor (14) may further include memory and may further include an image signal processor. Image data (IDATA) may be stored in the memory, and the image signal processor may process the image data (IDATA) to calculate distance information or depth information. The memory or the image signal processor may be provided outside the image sensor (14).

[0030] The control circuit (120) can control the components of the image sensor (14) (e.g., pixel array (110) and readout circuit (130)) and can control the light source driver (140) of the light source unit (12). The control circuit (120) can transmit a modulation signal (MOD) to the light source driver (140) and can transmit demodulation signals (DEMOD) corresponding to the modulation signal (MOD) to the pixel array (110). The demodulation signals (DEMOD) may refer to signals for controlling each of the transmission transistors included in each of the unit pixels (111), but are not limited thereto.

[0031] The control circuit (120) can generate a modulation signal (MOD) and demodulation signals (DEMOD) corresponding to the modulation signal (MOD) according to a random number. Accordingly, the image sensor (14) can eliminate noise (e.g., Multi User Interference (MUI)) generated in the received light signal (RX) by a light signal generated from a camera module other than the camera module (100) by converging it into a random noise component.

[0032] Additionally, the control circuit (120) can provide demodulation signals (DEMOD) having different delay phases for each of the multiple pixel groups included in the pixel array (110), and can provide demodulation signals (DEMOD) with different delay phases for each packet within the light collection time to one pixel group. Accordingly, the peak current of the demodulation signals (DEMOD) generated in the pixel array (110) can be reduced, and as a result, Electro Magnetic Interference (EMI) is reduced, high-speed modulation operation is enabled, and degradation due to depth Pixel Fixed-Pattern Noise (PFPN) can be prevented.

[0033] FIG. 3 is a drawing for explaining an exemplary embodiment of the structure of a unit pixel shown in FIG. 2.

[0034] The unit pixel (111) described in FIG. 3 may have a 4-tap structure. A 4-tap structure means a structure in which one unit pixel (111) includes four taps, and a tap may mean a unit component capable of transmitting photocharges generated and emitted within the unit pixel (111) by distinguishing them by phase as an external light signal is irradiated.

[0035] An image sensor (e.g., 14 in FIG. 2) comprising unit pixels (111) of a 4-tap structure can implement a method of transmitting for phases of 0°, 90°, 180°, and 270° using four taps. For example, based on a first tap of a unit pixel (111), when the first tap of the unit pixel (111) generates a first pixel signal (Vout1) for a phase of 0°, the second tap generates a second pixel signal (Vout2) for a phase of 90°, the third tap generates a third pixel signal (Vout3) for a phase of 180°, and the fourth tap generates a fourth pixel signal (Vout4) for a phase of 270°.

[0036] Referring to FIG. 3, a unit pixel (111) may include a photodiode (PD), an overflow gate (OG), transfer transistors (TS1–TS4), storage transistors (SS1–SS4), tap transfer transistors (TXS1–TXS4), reset transistors (RS1–RS4), source followers (SF1–SF4), and select transistors (SEL1–SEL4). According to an exemplary embodiment, at least one of the overflow gate (OG), storage transistors (SS1–SS4), tap transfer transistors (TXS1–TXS4), reset transistors (RX1–RX4), source followers (SF1–SF4), and select transistors (SEL1–SEL4) may be omitted.

[0037] A photodiode (PD) can generate a photocharge that varies according to the intensity of a received optical signal (e.g., RX in FIG. 2). That is, the photodiode (PD) can convert the received optical signal (RX) into an electrical signal. As an example of a photoelectric conversion device, the photodiode (PD) may be at least one of a phototransistor, a photogate, a pinned photodiode (PPD), and combinations thereof.

[0038] Each of the first to fourth transfer transistors (TS1 to TS4) can transfer the charge generated in the photodiode (PD) to each of the first to fourth storage transistors (SS1 to SS4) according to the first to fourth demodulation signals (DEMODA to DEMODD). Accordingly, each of the first to fourth transfer transistors (TS1 to TS4) can transfer the charge generated in the photodiode (PD) to the first to fourth floating diffusion nodes (FD1 to FD4) according to the first to fourth demodulation signals (DEMODA to DEMODD).

[0039] The first to fourth demodulation signals (DEMODA~DEMODD) may be included in the demodulation signals (DEMOD) of FIG. 2 and may be signals having the same frequency and duty ratio and different phases. The first to fourth demodulation signals (DEMODA~DEMODD) may have a phase difference of 90 degrees from each other. For example, with respect to the first modulation signal (DEMODA), when the first modulation signal (DEMODA) has a phase of 0°, the second modulation signal (DEMODB) may have a phase of 90°, the third modulation signal (DEMODC) may have a phase of 180°, and the fourth modulation signal (DEMODD) may have a phase of 270°.

[0040] The first to fourth storage transistors (SS1 to SS4) can store photocharges transmitted through each of the first to fourth transmission transistors (TS1 to TS4), and the first to fourth tap transmission transistors (TXS1 to TXS4) can transmit photocharges stored in each of the first to fourth storage transistors (SS1 to SS4) to the first to fourth floating diffusion nodes (FD1 to FD4).

[0041] Depending on the potential caused by the photocharge accumulated in the first to fourth floating diffusion nodes (FD1 to FD4), the first to fourth source followers (SF1 to SF4) can amplify and output the corresponding photocharge to the first to fourth selection transistors (SEL1 to SEL4). The first to fourth selection transistors (SEL1 to SEL4) can output the first to fourth pixel signals (Vout1 to Vout4) through column lines in response to selection control signals.

[0042] A unit pixel (111) can accumulate photocharges for a certain period of time, for example, integration time, and output first to fourth pixel signals (Vout1 to Vout4) generated according to the accumulation result to a readout circuit (for example, 130 in FIG. 2).

[0043] The first to fourth reset transistors (RS1 to RS4) can reset the first to fourth floating diffusion nodes (FD1 to FD4) to the power supply voltage (VDD). The overflow gate (OG) is a transistor for discharging overflow charge, the source of the overflow gate (OG) can be connected to a photodiode (PD), and the drain of the overflow gate (OG) can be provided with the power supply voltage (VDD).

[0044] Although a 4-tap pixel structure is illustrated and described in FIG. 3, the present disclosure is not limited thereto. The image sensor (14) may include 2-tap pixels. A 2-tap pixel structure will be described later in FIG. 11.

[0045] FIG. 4 is a block diagram for explaining a control circuit (120) included in an image sensor according to the present disclosure. FIG. 5 is a block diagram for explaining a demodulation phase selection circuit (123_2) of FIG. 4.

[0046] Referring to FIG. 4, the control circuit (120) can transmit a modulation signal (MOD) to a light source driver (e.g., 140 in FIG. 2) and can transmit first to fourth demodulation signals (DEMOD1 to DEMOD4) to a pixel array (e.g., 110 in FIG. 2). The control circuit (120) may include a random number generation circuit (121), a phase generation circuit (122), a phase selection circuit (123), a delay circuit (124), and a phase mixer (125).

[0047] Multiple packets can be distinguished during the aggregation time defining a single frame. The random number generation circuit (121) can generate a new random number (RN) for each packet. For example, the random number generation circuit (121) can generate 2-bit random numbers (#1:00, #2:01, #3:10, #4:11). The control circuit (120) may include a Linear Feedback Shift Register (LFSR) instead of the random number generation circuit (121).

[0048] The phase generation circuit (122) may include a modulation clock generation circuit (122_1) and a demodulation clock generation circuit (122_2). The modulation clock generation circuit (122_1) may generate a plurality of modulation clock signals, for example, first to fourth modulation clock signals (MCK1 to MCK4). The first to fourth modulation clock signals (MCK1 to MCK4) may have the same frequency and duty ratio and may have different phases. For example, the first modulation clock signal (MCK1) may have a phase of 0°, the second modulation clock signal (MCK2) may have a phase of 90°, the third modulation clock signal (MCK3) may have a phase of 180°, and the fourth modulation clock signal (MCK4) may have a phase of 270°.

[0049] The demodulation clock generation circuit (122_2) can generate a plurality of demodulation clock signals, for example, first to fourth demodulation clock signals (DCK1 to DCK4). The first to fourth demodulation clock signals (DCK1 to DCK4) may have the same frequency and duty ratio and may have different phases. For example, the first demodulation clock signal (DCK1) may have a phase of 0°, the second demodulation clock signal (DCK2) may have a phase of 90°, the third demodulation clock signal (DCK3) may have a phase of 180°, and the fourth demodulation clock signal (DCK4) may have a phase of 270°. At this time, the first to fourth demodulation clock signals (MCK1 to MCK4) and the first to fourth demodulation clock signals (DCK1 to DCK4) may have the same frequency.

[0050] The phase selection circuit (123) may include a modulation phase selection circuit (123_1) and a demodulation phase selection circuit (123_2). The modulation phase selection circuit (123_1) receives first to fourth modulation clock signals (MCK1 to MCK4) and outputs one of the first to fourth modulation clock signals (MCK1 to MCK4) as a modulation signal (MOD) according to a random number (RN).

[0051] Referring to FIGS. 4 and 5, the demodulation phase selection circuit (123_2) receives first to fourth demodulation clock signals (DCK1 to DCK4) and can generate first to fourth pre-demolding signals (PDEMOD1 to PDEMOD4) according to a random number (RN). The first to fourth pre-demolding signals (PDEMOD1 to PDEMOD4) may have the same frequency and duty ratio and different phases.

[0052] The demodulation phase selection circuit (123_2) may include first to fourth selection circuits (S1 to S4). Each of the first to fourth selection circuits (S1 to S4) may receive first to fourth demodulation clock signals (DCK1 to DCK4).

[0053] A first selection circuit (S1) can generate a first pre-demolding signal (PDEMOD1) from one of the first to fourth demodulation clock signals (DCK1 to DCK4) according to a random number (RN), and a second selection circuit (S2) can generate a second pre-demolding signal (PDEMOD2) from one of the first to fourth demodulation clock signals (DCK1 to DCK4) according to a random number (RN). A third selection circuit (S3) can generate a third pre-demolding signal (PDEMOD3) from one of the first to fourth demodulation clock signals (DCK1 to DCK4) according to a random number (RN), and a fourth selection circuit (S4) can generate a fourth pre-demolding signal (PDEMOD4) from one of the first to fourth demodulation clock signals (DCK1 to DCK4) according to a random number (RN).

[0054] At this time, the demodulation phase selection circuit (123_2) can generate the first to fourth pre-demolding signals (PDEMOD1~PDEMOD4) based on the first pre-demolding signal (PDEMOD1), such that the second pre-demolding signal (PDEMOD2) has a phase delayed by 90° compared to the first pre-demolding signal (PDEMOD1), the third pre-demolding signal (PDEMOD3) has a phase delayed by 180° compared to the first pre-demolding signal (PDEMOD1), and the fourth pre-demolding signal (PDEMOD4) has a phase delayed by 270° compared to the first pre-demolding signal (PDEMOD1). For example, if the first demodulation clock signal (DCK1) is selected as the first pre-demolding signal (PDEMOD1), each of the second to fourth demodulation clock signals (DCK2 to DCK4) may be selected as the second to fourth pre-demolding signals (PDEMOD2 to PDEMOD4). For example, if the second demodulation clock signal (DCK2) is selected as the first pre-demolding signal (PDEMOD1), each of the third, fourth, and first demodulation clock signals (DCK3, DCK4, DCK1) may be selected as the second to fourth pre-demolding signals (PDEMOD2 to PDEMOD4). For example, if the third demodulation clock signal (DCK3) is selected as the first pre-demoldation signal (PDEMOD1), the fourth, first, and second demodulation clock signals (DCK4, DCK1, DCK2) may each be selected as the second to fourth pre-demoldation signals (PDEMOD2~PDEMOD4). Alternatively, for example, if the fourth demodulation clock signal (DCK4) is selected as the first pre-demoldation signal (PDEMOD1), the first, second, and third demodulation clock signals (DCK1, DCK2, DCK3) may each be selected as the second to fourth pre-demoldation signals (PDEMOD2~PDEMOD4).

[0055] Referring again to FIG. 4, the delay circuit (124) can receive first to fourth pre-demolding signals (PDEMOD1 to PDEMOD4) and generate a plurality of first delay signals (DS1), a plurality of second delay signals (DS2), a plurality of third delay signals (DS3), and a plurality of fourth delay signals (DS4). In an exemplary embodiment, the delay circuit (124) can be implemented as a buffer chain.

[0056] The delay circuit (124) can generate a plurality of first delay signals (DS1) by delaying the first pre-demolding signal (PDEMOD1) by each specified delay phases (e.g., different delay phases such as 4, 10, 20, or 40). Additionally, the delay circuit (124) can generate a plurality of second delay signals (DS2) by delaying the second pre-demolding signal (PDEMOD2) by each specified delay phases, generate a plurality of third delay signals (DS3) by delaying the third pre-demolding signal (PDEMOD3) by each specified delay phases, and generate a plurality of fourth delay signals (DS4) by delaying the fourth pre-demolding signal (PDEMOD4) by each specified delay phases.

[0057] The phase mixer (125) can provide each of the first demodulation signals (DEMOD1), which are mixed with a plurality of first delay signals (DS1) according to the address (M_ADDR), to each of the corresponding pixel groups of the pixel array (110). For example, each of the first demodulation signals (DEMOD1) can be provided as a first demodulation signal (e.g., DEMODA in FIG. 3) to a first transfer transistor (e.g., TS1 in FIG. 3) of a unit pixel (e.g., 111 in FIG. 3) included in the corresponding pixel group.

[0058] The phase mixer (125) can mix a plurality of second delay signals (DS2) according to the address (M_ADDR) and provide each of the second demodulation signals (DEMOD2) to each of the corresponding pixel groups of the pixel array (110). For example, each of the second demodulation signals (DEMOD2) can be provided as a second demodulation signal (e.g., DEMODB of FIG. 3) to a second transfer transistor (e.g., TS2 of FIG. 3) of a unit pixel (111) included in the corresponding pixel group.

[0059] The phase mixer (125) can mix a plurality of third delay signals (DS3) according to the address (M_ADDR) and provide each of the third demodulation signals (DEMOD3) to each of the corresponding pixel groups of the pixel array (110). For example, each of the third demodulation signals (DEMOD3) can be provided as a third demodulation signal (e.g., DEMODC of FIG. 3) to a third transfer transistor (e.g., TS3 of FIG. 3) of a unit pixel (111) included in the corresponding pixel group.

[0060] Additionally, the phase mixer (125) can mix a plurality of fourth delay signals (DS4) according to the address (M_ADDR) and provide each of the fourth demodulation signals (DEMOD4) to each of the corresponding pixel groups of the pixel array (110). For example, each of the fourth demodulation signals (DEMOD4) can be provided as a fourth demodulation signal (e.g., DEMODD of FIG. 3) to a fourth transfer transistor (e.g., TS4 of FIG. 3) of a unit pixel (111) included in the corresponding pixel group.

[0061] The address (M_ADDR) may be changed at specific time intervals. For example, the address (M_ADDR) may be changed for each packet, and the phase mixer (125) may output first to fourth demodulation signals (DEMOD1~DEMOD4) in which the phase is changed for each packet.

[0062] Each of the first demodulation signals (DEMOD1) may have different delay phases, each of the second demodulation signals (DEMOD2) may have different delay phases, each of the third demodulation signals (DEMOD3) may have different delay phases, and each of the fourth demodulation signals (DEMOD3) may have different delay phases. Accordingly, a current dispersion effect of the first to fourth demodulation signals (DEMOD1~DEMOD4) may occur, and the peak current may be reduced. In addition, as the address (M_ADDRR) changes periodically, the phases of the first to fourth demodulation signals (DEMOD1~DEMOD4) provided to the pixel array (110) change periodically, so the depth offset error may be reduced.

[0063] FIG. 6a is a timing diagram for explaining modulation signals and multiple pre-demolding signals according to random numbers. The integration time can be divided into multiple packets, and a new random number (RN) can be assigned to each of the multiple packets. In an exemplary embodiment, the random number (RN) may be 2-bit, and in FIG. 6a, the random number (RN) may be represented by numbers 1 to 4. However, the present disclosure is not limited thereto, and the number of random numbers (RN) can be varied in many ways.

[0064] Referring to FIGS. 4 to 6a, a modulation signal (MOD) and a plurality of pre-demolding signals, for example, first to fourth pre-demolding signals (PDEMOD1 to PDEMOD4), may be changed together according to a random number (RN). The modulation signal (MOD) and the first to fourth pre-demolding signals (PDEMOD1 to PDEMOD4) may have the same period. In an exemplary embodiment, the modulation signal (MOD) may have a duty cycle of 50%, and each of the first to fourth pre-demolding signals (PDEMOD1 to PDEMOD4) may have a duty cycle of 25%. However, the present disclosure is not limited thereto, and the duty cycle of the modulation signal (MOD) and the duty cycle of the first to fourth pre-demolding signals (PDEMOD1 to PDEMOD4) may be varied.

[0065] For example, when the random number (RN) is 1, the phase of the demodulation signal (MOD) may be 0°, the phase of the first pre-demolding signal (PDEMOD1) may be 0°, the phase of the second pre-demolding signal (PDEMOD2) may be 90°, the phase of the third pre-demolding signal (PDEMOD3) may be 180°, and the phase of the fourth pre-demolding signal (PDEMOD4) may be 270°.

[0066] For example, when the random number (RN) is 2, the phase of the demodulation signal (MOD) may be 90°, the phase of the first pre-demolding signal (PDEMOD1) may be 90°, the phase of the second pre-demolding signal (PDEMOD2) may be 180°, the phase of the third pre-demolding signal (PDEMOD3) may be 270°, and the phase of the fourth pre-demolding signal (PDEMOD4) may be 0°.

[0067] For example, when the random number (RN) is 3, the phase of the demodulation signal (MOD) may be 180°, the phase of the first pre-demolding signal (PDEMOD1) may be 180°, the phase of the second pre-demolding signal (PDEMOD2) may be 270°, the phase of the third pre-demolding signal (PDEMOD3) may be 0°, and the phase of the fourth pre-demolding signal (PDEMOD4) may be 90°.

[0068] In addition, for example, when the random number (RN) is 4, the phase of the demodulation signal (MOD) may be 270°, the phase of the first pre-demolding signal (PDEMOD1) may be 270°, the phase of the second pre-demolding signal (PDEMOD2) may be 0°, the phase of the third pre-demolding signal (PDEMOD3) may be 90°, and the phase of the fourth pre-demolding signal (PDEMOD4) may be 180°.

[0069] The demodulation signal (MOD) and the first to fourth pre-demolding signals (PDEMOD1 to PDEMOD4) may be changed together according to the random number (RN), and as the first to fourth pre-demolding signals (PDEMOD1 to PDEMOD4) are changed, the first to fourth modulation signals (DEMOD1 to DEMOD4) may be changed. As the number of packets included in the light gathering time increases, noise caused by the optical signal output from another camera module may converge into a random noise component, and the depth measurement accuracy of the image sensor according to the present disclosure may be improved.

[0070] FIG. 6b is a timing diagram for explaining delay signals generated in a delay circuit of an image sensor according to the present disclosure. FIG. 6b describes the first delay signals (DS1) generated from the first pre-demolding signal (PDEMOD1), but the same can be applied to the second to fourth delay signals (DS2 to DS4) generated from each of the second to fourth demodulation signals (PDEMOD2 to PDEMOD4).

[0071] Referring to FIGS. 4 and 6b, the delay circuit (124) can generate a plurality of first delay signals (DS1) by delaying a first pre-demolding signal (PDEMOD1) by specified delay phases. For example, with respect to one pre-demolding signal (PDEMOD1), the delay time (Td) of the first signal (DS11) among the plurality of first delay signals (DS1) is 0 Δt, the delay time (Td) of the second signal (DS12) among the plurality of first delay signals (DS1) is 1 Δt, the delay time (Td) of the third signal (DS13) among the plurality of first delay signals (DS1) is 2 Δt, the delay time (Td) of the i-th signal (DS1i) among the plurality of first delay signals (DS1) is (i-1) Δt may be a natural number, for example, 4, 10, 20, 40, etc. In an exemplary embodiment, the delay time (Td) of the i-th signal (DS1i) among the plurality of first delay signals (DS1) may not exceed the delay time of the second pre-demolding signal (PDEMOD2) from the first pre-demolding signal (PDEMOD1).

[0072] FIG. 7 is a block diagram for explaining a pixel array of an image sensor according to the present disclosure. FIG. 8 is a timing diagram for explaining first to fourth demodulation signals provided to a pixel array according to an address.

[0073] Referring to FIG. 7, the pixel array (110) may include a plurality of pixel groups, for example, first to forty pixel groups (PG1 to PG40). The number of pixel groups included in the pixel array (110) being 40 is an example, and the number of pixel groups included in the pixel array (110) may be, for example, 4, 10, 20, or 40, and can be varied in various ways.

[0074] Each of the first to forty pixel groups (PG1 to PG40) may include at least one unit pixel. Among the first to forty pixel groups (PG1 to PG40), unit pixels included in the same pixel group may be unit pixels arranged side by side in the column direction, or unit pixels arranged side by side in the row direction. The first pixel group (PG1) may include at least one first unit pixel (PX1), the 20th pixel group (PG20) may include at least one 20th unit pixel (PX20), and the 40th pixel group (PG40) may include at least one 40th unit pixel (PX40).

[0075] A first signal set (SET1) may be provided as a first pixel group (PG1), a 20th signal set (SET20) may be provided as a 20th pixel group (PG20), and a 40th signal set (SET40) may be provided as a 40th pixel group (PG40). The first signal set (SET1) may include first to fourth demodulation signals (DEMOD1_1~DEMOD4_1), the 20th signal set (SET20) may include first to fourth demodulation signals (DEMOD1_20~DEMOD4_20), and the 40th signal set (SET40) may include first to fourth demodulation signals (DEMOD1_40~DEMOD4_40).

[0076] The first to fourth demodulation signals (DEMOD1_1 to DEMOD4_1) of the first signal set (SET1) may have a phase difference of 90° from each other. The first demodulation signal (DEMOD1_1) of the first signal set (SET1) may be provided to the first transmission transistor of the first unit pixel (PX1) of the first pixel group (PG1), and the second demodulation signal (DEMOD2_1) of the first signal set (SET1) may be provided to the second transmission transistor of the first unit pixel (PX1) of the first pixel group (PG1). The third demodulation signal (DEMOD3_1) of the first signal set (SET1) can be provided to the third transmission transistor of the first unit pixel (PX1) of the first pixel group (PG1), and the fourth demodulation signal (DEMOD4_1) of the first signal set (SET1) can be provided to the fourth transmission transistor of the first unit pixel (PX1) of the first pixel group (PG1).

[0077] The first to fourth demodulation signals (DEMOD1_20~DEMOD4_20) of the 20th signal set (SET20) may have a phase difference of 90° from each other. The first to fourth demodulation signals (DEMOD1_40~DEMOD4_40) of the 40th signal set (SET40) may have a phase difference of 90° from each other. The description of the first signal set (SET1) may be similarly applied to the description of the second to fortyth signal sets (SET2~SET40).

[0078] Referring to FIGS. 7 and 8, the integration time can be divided into multiple packets, and the address (M_ADDR) can be changed for each of the multiple packets. In an exemplary embodiment, the address (M_ADDR) may have a value from 1 to 40. However, the present disclosure is not limited thereto, and the number of values ​​of the address (M_ADDR) may be 4, 10, 20, or 40, and various variations are possible.

[0079] When the address (M_ADDR) is the same, the phases of each of the first demodulation signals (DEMOD1) within the activation interval (AT) may be different from each other. That is, within the activation interval (AT), the phases of the first demodulation signal (DEMOD1_1) of the first signal set (SET1), the first demodulation signal (DEMOD1_20) of the 20th signal set (SET20), and the first demodulation signal (DEMOD1_40) of the 40th signal set (SET40) may be different from each other.

[0080] Additionally, as the address (M_ADDR) changes, the phase of each of the first demodulation signals (DEMOD1) within the activation interval (AT) may change. That is, while the address (M_ADDR) changes from 1 to 40, the phase of the first demodulation signal (DEMOD1_1) of the first signal set (SET1) within the activation interval (AT) may change, the phase of the first demodulation signal (DEMOD1_20) of the 20th signal set (SET20) may change, and the phase of the first demodulation signal (DEMOD1_40) of the 40th signal set (SET40) may change.

[0081] The description of the first demodulation signals (DEMOD1) above may be similarly applied to the second to fourth demodulation signals (DEMOD2~DEMOD4).

[0082] Since the first demodulation signals (DEMOD1) include signals with different phases from each other (e.g., DEMOD1_1 to DEMOD1_40), the occurrence of a peak current in the first demodulation signals (DEMOD1) can be prevented. Additionally, since the second demodulation signals (DEMOD2) include signals with different phases from each other (e.g., DEMOD2_1 to DEMOD2_40), the occurrence of a peak current in the second demodulation signals (DEMOD2) can be prevented. For the same reason, the occurrence of a peak current in the third demodulation signals (DEMOD3) and the fourth demodulation signals (DEMOD4) can be prevented.

[0083] A phase mixer (e.g., 125 in FIG. 4) receives first to fourth delay signals (DS1 to DS4) from a delay circuit (e.g., 124 in FIG. 4) and, by mixing the first to fourth delay signals (DS1 to DS4) based on an address (M_ADDR), can output first to fourth demodulation signals (DEMOD1 to DEMOD4), whose phase changes every time interval (packet), to a pixel array (110). The address (M_ADDR) may have a number of values ​​corresponding to the number of delay signals generated by the delay circuit (124). Accordingly, all unit pixels of the pixel array (110) can receive all of the first to fourth delay signals (DS1 to DS4) generated by the delay circuit (124) as first to fourth demodulation signals (DEMOD1 to DEMOD4) during the light collection time. This operation can be referred to as a multiple interleaving operation. Since the pixel array (110) receives first to fourth demodulation signals (DEMOD1~DEMOD4) whose phases change within the light-gathering interval, the occurrence of a depth offset error can be prevented.

[0084] FIG. 9 is a diagram illustrating a first demodulation signal provided to each of a plurality of pixel groups included in a pixel array. Fig. 9 can be referenced together with Fig. 4.

[0085] FIG. 9 mainly describes the first demodulation signals (DEMOD1) generated from the first pre-demolding signal (PDEMOD1), but a similar description may be applied to the second demodulation signals (DEMOD2) generated from the second pre-demolding signal (PDEMOD2), the third demodulation signals (DEMOD3) generated from the third pre-demolding signal (PDEMOD3), and the fourth demodulation signals (DEMOD4) generated from the fourth pre-demolding signal (PDEMOD4). When each of the first demodulation signals (DEMOD1) is set as a reference (0°), the corresponding second demodulation signals (DEMOD2) may have a phase difference of 90°, the corresponding third demodulation signals (DEMOD3) may have a phase difference of 180°, and the corresponding fourth demodulation signals (DEMOD4) may have a phase difference of 270°.

[0086] Referring to FIG. 9, the delay circuit (124) can receive a first pre-demolding signal (PDEMOD1) and transmit a plurality of first delay signals to a phase mixer (125), and the phase mixer (125) can output the first demodulation signals (DEMOD1, e.g., DEMOD1_1 to DEMOD1_40) to a pixel array (110). The phase mixer (125) can output the first demodulation signal (DEMOD1_1) to a first pixel group (PG1), output the first demodulation signal (DEMOD1_2) to a second pixel group (PG2), and output the first demodulation signal (DEMOD1_40) to a 40 pixel group (PG40).

[0087] The first demodulation signal (DEMOD1_1) of the first pixel group (PG1) may have a phase that changes depending on the address (M_ADDR), and the delay time (Td) may change. For example, when the address (M_ADDR) changes to 1, 2, 3, 4, ..., 37, 38, 40, the delay time (Td) of the first demodulation signal (DEMOD1_1) of the first pixel group (PG1) is 0 Δt, 39 Δt, 38 Δt, 37 Δt, ... , 4 Δt, 3 Δt, 2 Δt, 1 It can be changed to Δt. The change in the delay time (Td) of the first demodulation signal (DEMOD1_1) according to the address (M_ADDR) described in FIG. 9 can be varied in various ways as one example.

[0088] The first demodulation signal (DEMOD1_2) of the second pixel group (PG2) may have a phase that changes depending on the address (M_ADDR), and the delay time (Td) may change. For example, when the address (M_ADDR) changes to 1, 2, 3, 4, ..., 37, 38, 40, the delay time (Td) of the first demodulation signal (DEMOD1_2) of the second pixel group (PG2) is 1 Δt, 0 Δt, 39 Δt, 38 Δt, ... , 5 Δt, 4 Δt, 3 Δt, 2 It can change to Δt.

[0089] The first demodulation signal (DEMOD1_40) of the 40th pixel group (PG40) may have a phase that changes depending on the address (M_ADDR), and the delay time (Td) may change. For example, when the address (M_ADDR) changes to 1, 2, 3, 4, ..., 37, 38, 40, the delay time (Td) of the first demodulation signal (DEMOD1_40) of the 40th pixel group (PG40) is 39 Δt, 38 Δt, 37 Δt, 36 Δt, ... , 3 Δt, 2 Δt, 1 Δt, 0 It can change to Δt.

[0090] FIG. 10 is a timing diagram for explaining the operation of an image sensor including a unit pixel of a 4-tap structure according to the present disclosure. A 4-tap structure may refer to a structure having taps capable of generating pixel signals according to four phases in a single frame.

[0091] Referring to FIG. 4 and FIG. 10, the delay circuit (124) can generate 40 first delay signals (DS1) by varying the delay phase from a first pre-demolding signal (PDEMOD1), generate 40 second delay signals (DS2) by varying the delay phase from a second pre-demolding signal (PDEMOD2), generate 40 third delay signals (DS3) by varying the delay phase from a third pre-demolding signal (PDEMOD3), and generate 40 fourth delay signals (DS4) by varying the delay phase from a fourth pre-demolding signal (PDEMOD4).

[0092] The address (M_ADDR) can be changed sequentially from 1 to 40 for each packet. The number of addresses (M_ADDR) may correspond to the number of delay signals generated by the delay circuit (124). As the address (M_ADDR) changes, the phase mixer (125) can mix the first delay signals (DS1) to generate the first demodulation signals (DEMOD1), mix the second delay signals (DS2) to generate the second demodulation signals (DEMOD2), mix the third delay signals (DS3) to generate the third demodulation signals (DEMOD3), and mix the fourth delay signals (DS4) to generate the fourth demodulation signals (DEMOD4).

[0093] Accordingly, the total number of packets within the light-gathering time may be a multiple (N times, where N is a natural number greater than or equal to 1) of the number of delay signals (e.g., the number of first delay signals (DS1)) generated based on one pre-demoding signal in the delay circuit (124). For example, when the delay circuit (124) generates delay signals having 40 different delay phases, the number of packets during the light-gathering time may be a multiple of 40. The number of packets may be adjusted by taking into account the operational accuracy of the image sensor and the operational speed of the image sensor.

[0094] In the image sensor according to the present disclosure, when a packet changes, the phase difference between the modulation signal (MOD) that operates the light source and the first to fourth demodulation signals (DEMOD1~DEMOD4) input to the pixel array is not fixed and can change with each packet. Accordingly, the first to fourth demodulation signals (DEMOD1~DEMOD4) have additional phase changes regardless of whether the modulation signal (MOD) changes according to the change of the random number (RN). Through this, it is possible to implement a high-performance camera module having low peak current and high depth measurement accuracy.

[0095] FIG. 11 is a drawing for explaining an exemplary embodiment of the structure of a unit pixel shown in FIG. 2.

[0096] The unit pixel (111A) described in FIG. 11 may have a 2-tap structure. A 2-tap structure means a structure in which one unit pixel (111A) includes two taps, and a tap may mean a unit component capable of transmitting photocharges generated and emitted within the unit pixel (111A) by distinguishing them by phase as an external light signal is irradiated.

[0097] An image sensor (e.g., 14 in FIG. 2) comprising unit pixels (111A) of a 2-tap structure can implement a method of transmitting for phases of 0°, 90°, 180°, and 270° using two taps. For example, when generating a first pixel signal (Vout1) for a phase of 0° based on the first tap of the unit pixel (111A) in an even frame (first frame), the second tap can generate a second pixel signal (Vout2) for a phase of 180°, and in an odd frame (second frame), the first tap can generate a first pixel signal (Vout1) for a phase of 90°, and the second tap can generate a second pixel signal (Vout2) for a phase of 270°.

[0098] Referring to FIG. 11, a unit pixel (111A) may include a photodiode (PD), an overflow gate (OG), transfer transistors (TS1, TS2), storage transistors (SS1, SS2), tap transfer transistors (TXS1, TXS2), reset transistors (RS1, RS2), source followers (SF1, SF2), and select transistors (SEL1, SEL2). According to an exemplary embodiment, at least one of the overflow gate (OG), storage transistors (SS1, SS2), tap transfer transistors (TXS1, TXS2), reset transistors (RS1, RS2), source followers (SF1, SF2), and select transistors (SEL1, SEL2) may be omitted.

[0099] The first transfer transistor (TS1) can transfer the charge generated in the photodiode (PD) to the first storage transistor (SS1) according to the first demodulation signal (DEMODA) in an even frame, and can transfer the charge generated in the photodiode (PD) to the first storage transistor (SS1) according to the second demodulation signal (DEMODB) in an odd frame. The second transfer transistor (TS2) can transfer the charge generated in the photodiode (PD) to the second storage transistor (SS2) according to the third demodulation signal (DEMODC) in an even frame, and can transfer the charge generated in the photodiode (PD) to the second storage transistor (SS2) according to the fourth demodulation signal (DEMODD) in an odd frame. The first to fourth demodulation signals (DEMODA~DEMODD) may be included in the demodulation signals (DEMOD) of FIG. 2 and may be signals having the same frequency and duty ratio and different phases. The first to fourth demodulation signals (DEMODA~DEMODD) may have a phase difference of 90 degrees from each other. For example, when the first modulation signal (DEMODA) has a phase of 0° relative to the first modulation signal (DEMODA), the second modulation signal (DEMODB) may have a phase of 90°, the third modulation signal (DEMODC) may have a phase of 180°, and the fourth modulation signal (DEMODD) may have a phase of 270°.

[0100] A unit pixel (111A) can accumulate photocharges during a light-gathering time in an even frame and output a first pixel signal (Vput1) and a second pixel signal (Vout2) generated according to the accumulation result to a readout circuit (e.g., 130 in FIG. 2). Additionally, a unit pixel (111A) can accumulate photocharges during a light-gathering time in an odd frame and output a first pixel signal (Vput1) and a second pixel signal (Vout2) generated according to the accumulation result to a readout circuit (130).

[0101] FIGS. 12 and FIGS. 13 are timing diagrams for explaining the operation of an image sensor including a unit pixel of a 2-tap structure according to the present disclosure. FIG. 12 is a diagram illustrating the operation of an image sensor in an even frame, and FIG. 14 is a diagram illustrating the operation of an image sensor in an odd frame. Even frames and odd frames can be performed alternately.

[0102] Referring to FIGS. 12 and 13, the duty cycle of the modulation signal (MOD) may be 50%, and the duty cycle of each of the first to fourth pre-demolding signals (PDEMOD1 to PDEMOD4) may be 50%. However, the duty cycle of each of the first to fourth pre-demolding signals (PDEMOD1 to PDEMOD4) may be freely modified.

[0103] A first pre-demolding signal (PDEMOD1) and a third pre-demolding signal (PDEMOD3) can be generated in an even frame. The phase difference of the third pre-demolding signal (PDEMOD3) with respect to the phase of the first pre-demolding signal (PDEMOD1) can be 180°. A delay circuit (e.g., 124 in FIG. 4) can generate a specified number (e.g., 40) of first delay signals (DS1) by varying the delay phase from the first pre-demolding signal (PDEMOD1), and can generate 40 third delay signals (DS3) by varying the delay phase from the third pre-demolding signal (PDEMOD3).

[0104] A second pre-demolding signal (PDEMOD2) and a fourth pre-demolding signal (PDEMOD4) can be generated in an odd frame. The phase difference of the second pre-demolding signal (PDEMOD2) with respect to the phase of the first pre-demolding signal (PDEMOD1) can be 90°, and the phase difference of the fourth pre-demolding signal (PDEMOD4) can be 270°. The delay circuit (124) can generate 40 second delay signals (DS2) by varying the delay phase from the second pre-demolding signal (PDEMOD2), and can generate 40 fourth delay signals (DS4) by varying the delay phase from the fourth pre-demolding signal (PDEMOD4).

[0105] The address (M_ADDR) can be changed sequentially from 1 to 40 for each packet. The number of addresses (M_ADDR) may correspond to the number of delay signals generated by the delay circuit (124). In an even frame, the phase mixer (e.g., 125 in FIG. 4) can mix the first delay signals (DS1) to generate the first demodulation signals (DEMOD1) and mix the third delay signals (DS3) to generate the third demodulation signals (DEMOD3) as the address (M_ADDR) changes. In an odd frame, the phase mixer (125) can mix the second delay signals (DS2) to generate the second demodulation signals (DEMOD2) and mix the fourth delay signals (DS4) to generate the fourth demodulation signals (DEMOD4) as the address (M_ADDR) changes.

[0106] The 2-tap structure has the advantage of having a simpler configuration of unit pixels compared to the 4-tap structure, and the 4-tap structure has the advantage of being able to generate pixel signals according to four phases (0°, 90°, 180°, 270°) within one frame compared to the 2-tap structure.

[0107] FIG. 14 is a schematic diagram showing an image sensor according to an exemplary embodiment of the present disclosure.

[0108] Referring to FIG. 14, the image sensor (1000) may be a stacked image sensor comprising a first chip (CP1) and a second chip (CP2) stacked in a vertical direction. The image sensor (1000) may be an implementation of the image sensor (14) described in FIG. 1.

[0109] The first chip (CP1) may include a pixel area (PR1) and a pad area (PR2), and the second chip (CP2) may include a peripheral circuit area (PR3) and a lower pad area (PR2'). A pixel array in which a plurality of unit pixels (PX) are arranged may be formed in the pixel area (PR1), and may include the pixel array (110) described in FIGS. 2, FIGS. 7 and FIGS. 9.

[0110] The peripheral circuit area (PR3) of the second chip (CP2) may include a logic circuit block (LC) and may include a plurality of transistors. For example, the logic circuit block (LC) may include at least some of the control circuit (120) and readout circuit (130) described in FIG. 2. The peripheral circuit area (PR3) may provide a constant signal to each of the plurality of unit pixels (PX) included in the pixel area (PR1) and may read out a pixel signal output from each of the plurality of unit pixels (PX).

[0111] The lower pad region (PR2') of the second chip (CP2) may include a lower conductive pad (PAD'). There may be multiple lower conductive pads (PAD'), and each may correspond to a conductive pad (PAD). The lower conductive pad (PAD') may be electrically connected to the conductive pad (PAD) of the first chip (CP1) by a via structure (VS).

[0112] As described above, exemplary embodiments have been disclosed in the drawings and specification. Although specific terms have been used to describe the embodiments in this specification, they are used only for the purpose of explaining the technical concept of this disclosure and are not intended to limit the meaning or the scope of this disclosure as defined in the claims. Therefore, those skilled in the art will understand that various modifications and equivalent alternative embodiments are possible therefrom. Accordingly, the true technical scope of protection of this disclosure should be determined by the technical concept of the appended claims.

Claims

Claim 1 An image sensor comprising: a demodulation clock generating circuit that generates first to fourth demodulation clock signals each having first to fourth phases; a demodulation phase selection circuit that receives the first to fourth demodulation clock signals and generates first to fourth pre-demodation signals according to a random number; a delay circuit that generates a plurality of first to fourth delay signals by delaying each of the first to fourth pre-demodation signals by a plurality of delay phases; and a phase mixer that receives the plurality of first to fourth delay signals and generates a plurality of first to fourth demodulation signals whose phases change according to an address that changes per packet, wherein the first to fourth phases have a phase difference of 90 degrees from each other. Claim 2 An image sensor according to claim 1, further comprising a random number generation circuit that generates the random number and provides the random number to the phase selection circuit. Claim 3 An image sensor according to claim 1, further comprising: a modulation clock generating circuit that generates first to fourth modulation clock signals each having the first to fourth phases; and a modulation phase selection circuit that receives the first to fourth modulation clock signals and outputs one of the first to fourth modulation clock signals as a modulation signal according to the random number. Claim 4 An image sensor according to claim 1, wherein the demodulation phase selection circuit comprises: a first selection circuit that outputs one of the first to fourth demodulation clock signals as the first pre-demoldation signal according to the random number; a second selection circuit that outputs one of the first to fourth demodulation clock signals as the second pre-demoldation signal according to the random number; a third selection circuit that outputs one of the first to fourth demodulation clock signals as the third pre-demoldation signal according to the random number; and a fourth selection circuit that outputs one of the first to fourth demodulation clock signals as the fourth pre-demoldation signal according to the random number. Claim 5 An image sensor according to claim 4, characterized in that, with respect to the first pre-demolding signal, the phase difference of the second pre-demolding signal is 90 degrees, the phase difference of the third pre-demolding signal is 180 degrees, and the phase difference of the fourth pre-demolding signal is 270 degrees. Claim 6 An image sensor according to claim 1, further comprising a pixel array that includes a plurality of unit pixels and receives the plurality of first to fourth demodulation signals, wherein the plurality of unit pixels have a 4-tap structure comprising four taps that generate each of the first to fourth pixel signals. Claim 7 An image sensor according to claim 6, wherein the plurality of unit pixels receive the plurality of first to fourth demodulation signals within a single frame. Claim 8 An image sensor according to claim 1, further comprising a pixel array that includes a plurality of unit pixels and receives the plurality of first to fourth demodulation signals, wherein the plurality of unit pixels have a 2-tap structure comprising two taps that generate a first pixel signal and a second pixel signal, respectively. Claim 9 An image sensor according to claim 8, wherein the plurality of unit pixels receive the first demodulation signals and the third demodulation signals in a first frame, and receive the second demodulation signals and the fourth demodulation signals in a second frame following the first frame. Claim 10 An image sensor according to claim 1, further comprising a pixel array including a plurality of pixel groups, wherein each of the plurality of pixel groups receives a first demodulation signal having a different phase among the plurality of first demodulation signals, each of the plurality of second demodulation signals having a different phase, each of the plurality of third demodulation signals having a different phase, each of the plurality of third demodulation signals having a different phase, and each of the plurality of fourth demodulation signals having a different phase. Claim 11 An image sensor comprising: a pixel array including a first pixel group and a second pixel group; and a control circuit that provides a modulation signal to a light source and provides a plurality of first to fourth demodulation signals to the pixel array, wherein each of the first to fourth demodulation signals provided to the first pixel group has a phase different from each of the first to fourth demodulation signals provided to the second pixel group, the light collection time defining one frame is composed of a plurality of packets, and the random number and the address are changed when the packet is changed. Claim 12 An image sensor according to claim 11, wherein the control circuit comprises: a random number generation circuit for generating the random number; a demodulation clock generation circuit for generating first to fourth demodulation clock signals having different phases; a demodulation phase selection circuit for receiving the first to fourth demodulation clock signals and generating first to fourth pre-demolding signals according to the random number; a delay circuit for generating a plurality of first to fourth delay signals by delaying each of the first to fourth pre-demolding signals by a plurality of delay phases; and a phase mixer for receiving the plurality of first to fourth delay signals and outputting the plurality of first to fourth demodulation signals to the pixel array according to the address. Claim 13 An image sensor according to claim 12, characterized in that the number of the plurality of packets is a multiple of the number of the plurality of delay phases. Claim 14 An image sensor according to claim 12, characterized in that the number of addresses is equal to the number of the plurality of delay phases. Claim 15 A camera module comprising: a light source unit that transmits a light signal to an object; an image sensor that receives a light signal reflected from the object, wherein the image sensor comprises a pixel array including a plurality of unit pixels; and a control circuit that further comprises a modulation signal to the light source unit and provides a plurality of first to fourth demodulation signals, the phases of which are changed according to a random number and an address to the pixel array, wherein the light gathering time defining a frame is composed of a plurality of packets, and the random number and the address are changed when the packet is changed. Claim 16 A camera module according to claim 15, wherein the pixel array comprises a plurality of pixel groups, and the first demodulation signals provided to different pixel groups among the plurality of pixel groups have different phases from each other. Claim 17 A camera module according to claim 15, wherein the control circuit comprises: a random number generation circuit for generating the random number; a demodulation clock generation circuit for generating first to fourth demodulation clock signals; a demodulation phase selection circuit for receiving the first to fourth demodulation clock signals and generating first to fourth pre-demolding signals according to the random number; a delay circuit for generating a plurality of first to fourth delay signals by delaying each of the first to fourth pre-demolding signals by a plurality of delay phases; and a phase mixer for receiving the plurality of first to fourth delay signals and outputting the plurality of first to fourth demodulation signals to the pixel array according to the address. Claim 18 A camera module according to claim 17, characterized in that the number of the plurality of packets is a multiple of the number of the plurality of delay phases. Claim 19 A camera module according to claim 17, wherein the plurality of unit pixels are provided with all of the plurality of first to fourth delay signals within one frame as the plurality of first to fourth demodulation signals. Claim 20 A camera module according to claim 15, wherein the control circuit comprises: a modulation clock generating circuit that generates first to fourth modulation clock signals; and a modulation phase selection circuit that receives the first to fourth modulation clock signals and outputs one of the first to fourth modulation clock signals as the modulation signal according to the random number.

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