Display apparatus

Abstract

The present invention provides a display device for preventing conductive patterns disposed in a part of a display area from being visible by external light, comprising: a substrate in which a display area and a peripheral area outside the display area are defined; a semiconductor layer disposed on the substrate; a first pixel circuit disposed on the display area; a first data line disposed on the display area and connected to the first pixel circuit; a second pixel circuit disposed on the peripheral area; a second data line disposed on the peripheral area and connected to the second pixel circuit; and a data connection line interposed between the substrate and the semiconductor layer and connecting the first data line to the second data line.

Description

Technology Field

[0001] The present invention relates to a display device. Background Technology

[0002] A display device is a device that visually displays data. Display devices are used as displays for small products such as mobile phones, as well as for large products such as televisions.

[0003] A display device includes multiple pixels that receive electrical signals and emit light to display an image externally. Each pixel includes a light-emitting element; for example, in the case of an organic light-emitting display device, it includes an organic light-emitting diode (OLED) as the light-emitting element. Generally, an organic light-emitting display device forms thin-film transistors and organic light-emitting diodes on a substrate, and operates by the organic light-emitting diode emitting light on its own.

[0004] Recently, as the applications of display devices have diversified, various design attempts are being made to improve their quality. In particular, a variety of display devices with excellent characteristics such as thinness, lightness, and low power consumption are being introduced. Furthermore, there is a recent trend of reducing dead space and expanding the display area of ​​display devices. The problem to be solved

[0005] The present invention aims to solve various problems by providing a display panel with an expanded display area and a display device equipped with the same, so that an image can be displayed even in an area where an electronic component is placed. However, this problem is exemplary and the scope of the present invention is not limited thereby. means of solving the problem

[0006] According to one aspect of the present invention, a display device is provided comprising: a substrate having a display area and a peripheral area outside the display area defined therein; a semiconductor layer disposed on the substrate; a first pixel circuit disposed on the display area; a first data line disposed on the display area and connected to the first pixel circuit; a second pixel circuit disposed on the peripheral area; a second data line disposed on the peripheral area and connected to the second pixel circuit; and a data connection line interposed between the substrate and the semiconductor layer and connecting the first data line to the second data line.

[0007] According to one example, the display area includes a component area and a main area surrounding at least a portion of the component area, the transparency of the component area is higher than the transparency of the main area, and the data connection line may overlap at least a portion with the component area.

[0008] According to one example, the display device further includes a camera positioned below the component area, the component area includes a central area corresponding to the lens of the camera and an edge area surrounding the central area, and the data connection line may overlap at least partially with the edge area of ​​the component area.

[0009] According to one example, the data connection line has a first part that overlaps with the component area, a second part that is connected to the first part and extends in a first direction, and a third part that is connected to the second part and extends in a second direction, and the second part and the third part of the data connection line may overlap at least partially with the main area.

[0010] According to one example, the display device further includes a voltage line disposed on the semiconductor layer and extending in the first direction and connected to the first pixel circuit, and the second portion of the data connection line and the voltage line may overlap at least partially with each other.

[0011] According to one example, the display device further includes a first display element disposed on the display area and connected to the first pixel circuit, and the first pixel circuit may include a driving transistor that controls the current flowing to the first display element; and an initialization transistor that is connected to the voltage line and applies an initialization voltage transmitted from the voltage line to the gate of the driving transistor in response to a scan signal.

[0012] According to one example, the conductivity type of the driving transistor may be opposite to the conductivity type of the initialization transistor.

[0013] According to one example, the first pixel circuit and the data connection line are provided in plurality, the plurality of first pixel circuits are arranged in a matrix, the second portions of the plurality of data connection lines are arranged in each row of the pixel circuit, and the third portions of the plurality of data connection lines can be arranged in each column of the pixel circuit or each pair of columns of the pixel circuit.

[0014] According to one example, the display device may further include an auxiliary row line extending in the first direction and having a first row connecting portion and a second row connecting portion spaced apart from each other by the third portion of the data connecting line; and an auxiliary column line extending in the second direction and having a first column connecting portion and a second column connecting portion spaced apart from each other by the second portion of the data connecting line.

[0015] According to one example, the same level of driving voltage can be applied to the auxiliary row line and the auxiliary column line.

[0016] According to one example, the display device further comprises a first display element disposed on the display area and connected to the first pixel circuit; and a second display element disposed on the display area and connected to the second pixel circuit, wherein the light-emitting area of ​​the second display element may be larger than the light-emitting area of ​​the first display element.

[0017] According to one example, the display device further comprises a third pixel circuit disposed on the display area; and a third display element disposed on the display area and connected to the third pixel circuit, wherein the display area comprises a component area including a first area and a second area adjacent to each other, and a main area surrounding a portion of the component area, wherein the first pixel circuit and the first display element are disposed in the main area and overlap at least partially with each other, the second display element is disposed in the first area of ​​the component area, and the third pixel circuit and the third display element are disposed in the second area of ​​the component area and overlap at least partially with each other, and the light-emitting area of ​​the third display element may be larger than the light-emitting area of ​​the first display element.

[0018] According to one example, the first display element, the second display element, and the third display element are provided in plurality, and the number of the plurality of first display elements per unit area is greater than the number of the plurality of second display elements per unit area, and the number of the plurality of second display elements per unit area may be equal to the number of the plurality of third display elements per unit area.

[0019] According to another aspect of the present invention, a display device is provided comprising: a component area, a display area including a main area surrounding at least a portion of the component area, and a peripheral area outside the display area; a plurality of first pixel circuits disposed on the main area; a plurality of first display elements disposed on the main area and connected to the plurality of first pixel circuits; a plurality of first data lines disposed on the main area and connected to the plurality of first pixel circuits; a plurality of second pixel circuits disposed on the peripheral area; a plurality of second display elements disposed on the component area and connected to the plurality of second pixel circuits; a plurality of second data lines disposed on the peripheral area and connected to the plurality of second pixel circuits; and a plurality of data connection lines that overlap at least a portion with the component area and connect the plurality of first data lines to the plurality of second data lines, wherein the number of the plurality of first display elements per unit area is greater than the number of the plurality of second display elements per unit area.

[0020] According to one example, the display device further includes a camera positioned below the component area, the component area includes a central area corresponding to the lens of the camera and an edge area surrounding the central area, and the plurality of data connection lines may overlap at least partially with the edge area of ​​the component area.

[0021] According to one example, each of the plurality of data connection lines has a first part that overlaps with the component area, a second part that is connected to the first part and extends in a first direction, and a third part that is connected to the second part and extends in a second direction, and the second part and the third part of each of the plurality of data connection lines may overlap at least partially with the main area.

[0022] According to one example, the display device further includes a plurality of voltage lines that are disposed on the main area and each extend in the first direction and are connected to first pixel circuits located in the same row among the plurality of first pixel circuits, and the second portions of the plurality of data connection lines and the plurality of voltage lines may each overlap at least partially with one another.

[0023] According to one example, each of the plurality of first pixel circuits may include a driving transistor that controls a current flowing to a corresponding first display element among the plurality of first display elements; and an initialization transistor that applies an initialization voltage transmitted from a corresponding voltage line among the plurality of voltage lines to the gate of the driving transistor in response to a scan signal.

[0024] According to one example, the second portions of the plurality of data connection lines may be arranged for each row of pixel circuits, and the third portions of the plurality of data connection lines may be arranged for each column of pixel circuits or each pair of pixel circuits.

[0025] According to one example, the display device further comprises a plurality of auxiliary row lines, each having a plurality of row connection portions that extend in the first direction and are spaced apart by the third portions of the plurality of data connection lines; and a plurality of auxiliary column lines, each having a plurality of column connection portions that extend in the second direction and are spaced apart by the second portions of the plurality of data connection lines, and the same level of driving voltage may be applied to the plurality of auxiliary row lines and the plurality of auxiliary column lines.

[0026] According to one example, the number of the plurality of row connections of each of the plurality of auxiliary row lines can increase monotonically along the second direction.

[0027] Other aspects, features, and advantages other than those described above will become clear from the following specific details, claims, and drawings for implementing the invention.

[0028] These general and specific aspects may be implemented using a system, method, computer program, or any combination of a system, method, or computer program. Effects of the invention

[0029] According to various embodiments of the present invention, conductive patterns disposed in a part of a display area can be prevented from being visible by external light. Of course, the scope of the present invention is not limited by this effect. Brief explanation of the drawing

[0030] FIG. 1 is a perspective view schematically illustrating a display device according to one embodiment of the present invention. FIG. 2 is a cross-sectional view schematically illustrating a part of a display device according to one embodiment of the present invention. FIG. 3 is a plan view schematically illustrating a display panel that may be included in a display device according to one embodiment of the present invention. FIG. 4 is an enlarged plan view schematically illustrating a display panel according to one embodiment of the present invention. FIG. 5 is an exemplary cross-sectional view of the data connection line of FIG. 4 cut along II' and II-II'. FIG. 6 is an enlarged plan view schematically illustrating a display panel according to one embodiment of the present invention. FIG. 7 is an enlarged plan view schematically illustrating a display panel according to one embodiment of the present invention. FIG. 8 illustrates an equivalent circuit diagram of a pixel according to one embodiment of the present invention. FIG. 9 is a plan view schematically illustrating a display panel that may be included in a display device according to one embodiment of the present invention. FIG. 10 is an enlarged plan view schematically illustrating a part of FIG. 9. FIG. 11 is an enlarged plan view schematically illustrating a part of FIG. 9. FIG. 12 is an exemplary cross-sectional view of the pixel circuit of FIG. 11 cut along IV-IV' and V-V'. FIG. 13 is an enlarged plan view schematically illustrating a part of FIG. 9. Specific details for implementing the invention

[0031] The present invention is capable of various modifications and may have various embodiments; specific embodiments are illustrated in the drawings and described in detail in the detailed description. The effects and features of the present invention, and the methods for achieving them, will become clear by referring to the embodiments described below in detail together with the drawings. However, the present invention is not limited to the embodiments disclosed below but can be implemented in various forms.

[0032] Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings. When describing with reference to the drawings, identical or corresponding components are given the same reference numerals, and redundant descriptions thereof will be omitted.

[0033] In the following embodiments, terms such as first, second, etc. are used not in a limiting sense, but for the purpose of distinguishing one component from another component.

[0034] In the following embodiments, singular expressions include plural expressions unless the context clearly indicates otherwise.

[0035] In the following embodiments, terms such as "include" or "have" mean that the features or components described in the specification are present, and do not preclude the possibility that one or more other features or components may be added.

[0036] In the following embodiments, when a part such as a film, region, or component is described as being on or above another part, it includes not only cases where it is directly on top of the other part, but also cases where another film, region, or component is interposed therein.

[0037] In the drawings, the size of components may be exaggerated or reduced for convenience of explanation. For example, the size and thickness of each component shown in the drawings are depicted arbitrarily for convenience of explanation, so the present invention is not necessarily limited to what is illustrated.

[0038] Where an embodiment can be implemented differently, a specific process sequence may be performed differently from the order described. For example, two processes described consecutively may be performed substantially simultaneously or proceed in the reverse order of the description.

[0039] In this specification, "A and / or B" indicates the case where it is A, B, or both A and B. And, "at least one of A and B" indicates the case where it is A, B, or both A and B.

[0040] In the following embodiments, when a membrane, region, component, etc. is described as being connected, it includes cases where the membrane, region, or component is directly connected, or / or cases where other membranes, regions, or components are interposed between the membranes, regions, or components to be indirectly connected. For example, when a membrane, region, component, etc. is described as being electrically connected in this specification, it indicates cases where the membrane, region, or component, etc. are directly electrically connected, and / or cases where other membranes, regions, or components are interposed between them to be indirectly electrically connected.

[0041] The x-axis, y-axis, and z-axis are not limited to the three axes of an orthogonal coordinate system but can be interpreted in a broader sense that includes them. For example, the x-axis, y-axis, and z-axis may be orthogonal to each other, but they may also refer to different directions that are not orthogonal to each other.

[0042] FIG. 1 is a perspective view schematically illustrating a display device according to one embodiment of the present invention.

[0043] Referring to FIG. 1, a display device (1) may include a display area (DA) and a peripheral area (PA) outside the display area (DA). The display area (DA) may include a component area (CA) and a main area (MA) that at least partially surrounds the component area (CA). That is, the component area (CA) and the main area (MA) may each display an image individually or together. The peripheral area (PA) may be a type of non-display area where display elements are not placed. The display area (DA) may be entirely surrounded by the peripheral area (PA).

[0044] FIG. 1 illustrates a component area (CA) located within a main area (MA). In another embodiment, the display device (1) may have two or more component areas (CA), and the shapes and sizes of the multiple component areas (CA) may differ from one another. When viewed from a direction approximately perpendicular to the upper surface of the display device (1), the shape of the component area (CA) may have various shapes such as a circle, an ellipse, a polygon such as a square, a star shape, or a diamond shape. Although FIG. 1 illustrates the component area (CA) being positioned at the upper center (+y direction) of the main area (MA), which has a roughly rectangular shape when viewed from a direction approximately perpendicular to the upper surface of the display device (1), the component area (CA) may be positioned on one side of the rectangular main area (MA), for example, the upper right or upper left side.

[0045] A display device (1) can provide an image using a plurality of pixels (PX) arranged in a display area (DA). A display device (1) can provide an image using a plurality of first pixels (PX1) arranged in a main area (MA) and a plurality of second pixels (PX2) arranged in a component area (CA). Each of the plurality of first pixels (PX1) and the plurality of second pixels (PX2) may have a display element. Each of the plurality of first pixels (PX1) and the plurality of second pixels (PX2) may include a display element such as an organic light-emitting diode (OLED). Each pixel (PX) may emit light of, for example, red, green, blue, or white light through an organic light-emitting diode (OLED). In the present specification, each pixel (PX) refers to a sub-pixel that emits a different color, and each pixel (PX) may be one of, for example, a red sub-pixel, a green sub-pixel, and a blue sub-pixel.

[0046] As described below with reference to FIG. 2, a component (20), which is an electronic element, may be disposed in the lower part of the display panel corresponding to the component area (CA). The component (20) may be a camera that uses infrared or visible light, and may be equipped with an imaging element. Alternatively, the component (20) may be a solar cell, a flash, an illuminance sensor, a proximity sensor, or an iris sensor. Alternatively, the component (20) may have a function of receiving sound. To minimize the limitation of the function of such a component (20), the component area (CA) may include a transmission area (TA) through which light or / or sound, which is output from the component (20) to the outside or travels from the outside toward the component (20), can be transmitted. In the case of a display panel and a display device equipped with the same according to one embodiment of the present invention, when light is transmitted through a component area (CA), the light transmittance may be about 10% or more, more preferably 40% or more, 25% or more, 50% or more, 85% or more, or 90% or more.

[0047] The component area (CA) may include a central area (CAm) and an edge area (CAe) surrounding the central area (CAm). The central area (CAm) may be an area where a component (20) placed below the component area (CA) substantially receives light. For example, if the component (20) is a camera, the central area (CAm) may correspond to the camera lens. The central area (CAm) may correspond within the angle of view range of the camera lens. The edge area (CAe) may correspond outside the angle of view range of the camera lens.

[0048] In FIG. 1, the shape of the central region (CAm) is depicted as a circle, but in other embodiments, the shape of the central region (CAm) may have various shapes such as an ellipse, a polygon such as a square, a star shape, or a diamond shape.

[0049] A plurality of second pixels (PX2) may be disposed in the component area (CA). The plurality of second pixels (PX2) may emit light to provide a predetermined image. The image displayed in the component area (CA) is an auxiliary image and may have a lower resolution compared to the image displayed in the main area (MA). That is, the component area (CA) is equipped with a transmission area (TA) through which light and sound can pass, and since no pixels are disposed on the transmission area (TA), the number of second pixels (PX2) that can be disposed per unit area may be smaller than the number of first pixels (PX1) disposed per unit area in the main area (MA).

[0050] FIG. 2 is a cross-sectional view schematically illustrating a part of a display device according to one embodiment of the present invention.

[0051] Referring to FIG. 2, the display device (1) may include a display panel (10) and a component (20) that is overlapped with the display panel (10). A cover window (not shown) that protects the display panel (10) may be further disposed on the upper part of the display panel (10).

[0052] The display panel (10) includes a component area (CA) that overlaps with the component (20), and a main area (MA) where a main image is displayed. The display panel (10) may include a substrate (100), a display layer (DISL) on the substrate (100), a touch screen layer (TSL), an optical function layer (OFL), and a panel protection member (PB) disposed on the lower part of the substrate (100).

[0053] The display layer (DISL) may include a circuit layer (PCL) containing a thin-film transistor (TFT), a display element layer (DEL) containing display elements (DE1, DE2), and a sealing member (ENCM) such as a thin-film encapsulation layer (TFEL) or a sealing substrate (not shown). An insulating layer (IL, IL') may be disposed between the substrate (100) and the display layer (DISL), and within the display layer (DISL).

[0054] The substrate (100) may be made of an insulating material such as glass, quartz, or polymer resin. The substrate (100) may be a rigid substrate or a flexible substrate capable of bending, folding, rolling, etc.

[0055] A first pixel (PX1) may be disposed in the main area (MA) of the display panel (10). The first pixel (PX1) may include a first pixel circuit (PC1) and a first display element (DE1) connected to the first pixel circuit (PC1). The first pixel circuit (PC1) includes at least one thin-film transistor (TFT) and can control the light emission of the first display element (DE1). The first pixel (PX1) may be realized by the light emission of the first display element (DE1).

[0056] A second pixel (PX2) may be disposed in the component area (CA) of the display panel (10). The second pixel (PX2) may include a second pixel circuit (PC2) and a second display element (DE2) connected to the second pixel circuit (PC2). The second pixel circuit (PC2) includes at least one thin-film transistor (TFT) and can control the light emission of the second display element (DE2). The second pixel (PX2) may be realized by the light emission of the second display element (DE2).

[0057] In one embodiment, the second pixel circuit (PC2) driving the second display element (DE2) may not be placed in the component area (CA) but may be placed in the peripheral area (PA), which is a non-display area. In another embodiment, various variations are possible, such as the second pixel circuit (PC2) being placed in a part of the main area (MA) or between the main area (MA) and the component area (CA). That is, the second pixel circuit (PC2) may be placed so as not to overlap with the second display element (DE2).

[0058] The second pixel circuit (PC2) can be electrically connected to the second display element (DE2) by an electrode connection line (EWL). The electrode connection line (EWL) can be provided with a transparent conductive material.

[0059] The area within the component area (CA) where the second display element (DE2) is placed may be referred to as the auxiliary area (AA). Additionally, the area within the component area (CA) where the second display element (DE2) is not placed may be referred to as the transmission area (TA). The transmission area (TA) may be an area where light / signals emitted from a component (20) placed in correspondence with the component area (CA) or light / signals incident on the component (20) are transmitted. The auxiliary area (AA) and the transmission area (TA) may be alternately placed within the component area (CA). The electrode connection line (EWL) connecting the second pixel circuit (PC2) and the second display element (DE2) may be placed in the transmission area (TA). Since the electrode connection line (EWL) may be provided with a transparent conductive material having high transmittance, the transmittance of the transmission area (TA) can be secured even if the electrode connection line (EWL) is placed in the transmission area (TA).

[0060] In this embodiment, since the second pixel circuit (PC2) is not placed in the component area (CA), the area of ​​the transmission area (TA) can be secured, and thus the light transmittance can be further improved.

[0061] The component area (CA) may include a central area (CAm) and an edge area (CAe) surrounding the central area (CAm). The central area (CAm) may be an area where the component (20) placed below the component area (CA) substantially receives light. For example, if the component (20) is a camera, the central area (CAm) may correspond to the camera lens (20R). The central area (CAm) may correspond within the field of view range of the camera lens (20R). The edge area (CAe) may correspond outside the field of view range of the camera lens (20R).

[0062] The display element layer (DEL) may be covered by a thin film encapsulation layer (TFEL) or by a sealing substrate. In some embodiments, the thin film encapsulation layer (TFEL) may include at least one inorganic encapsulation layer and at least one organic encapsulation layer as shown in FIG. 2. In one embodiment, the thin film encapsulation layer (TFEL) may include a first inorganic encapsulation layer (131) and a second inorganic encapsulation layer (133), and an organic encapsulation layer (132) between them.

[0063] The first inorganic encapsulation layer (131) and the second inorganic encapsulation layer (133) are silicon oxide (SiO2) and silicon nitride (SiN x ), silicon oxynitride (SiO₂ x N y It may include one or more inorganic insulating materials such as aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO2), and may be formed by chemical vapor deposition (CVD), etc. The organic encapsulation layer (132) may include a polymer-based material. Polymer-based materials may include silicone resin, acrylic resin, epoxy resin, polyimide, and polyethylene.

[0064] The first inorganic encapsulation layer (131), the organic encapsulation layer (132), and the second inorganic encapsulation layer (133) can be integrally formed to cover the main area (MA) and the component area (CA).

[0065] When the display element layer (DEL) is sealed with a sealing substrate (not shown), the sealing substrate may be positioned to face the substrate (100) with the display element layer (DEL) in between. A gap may exist between the sealing substrate and the display element layer (DEL). The sealing substrate may include glass. A sealant made of frit, etc., is disposed between the substrate (100) and the sealing substrate, and the sealant may be disposed in the aforementioned surrounding area (PA). The sealant disposed in the surrounding area (PA) can surround the display area (DA) and prevent moisture from penetrating through the sides.

[0066] The touch screen layer (TSL) can acquire coordinate information based on external input, such as a touch event. The touch screen layer (TSL) may include touch electrodes and touch wiring connected to the touch electrodes. The touch screen layer (TSL) can detect external input using a magnetic capacitance method or a mutual capacitance method.

[0067] A touch screen layer (TSL) may be formed on a thin film encapsulation layer (TFEL). Alternatively, the touch screen layer (TSL) may be formed separately on a touch substrate and then bonded onto the thin film encapsulation layer (TFEL) through an adhesive layer such as an optically clear adhesive (OCA). In one embodiment, the touch screen layer (TSL) may be formed directly on the thin film encapsulation layer (TFEL), in which case the adhesive layer may not be interposed between the touch screen layer (TSL) and the thin film encapsulation layer (TFEL).

[0068] The optical functional layer (OFL) may include an anti-reflection layer. The anti-reflection layer can reduce the reflectivity of light (external light) incident from the outside toward the display device (1).

[0069] In some embodiments, the optical functional layer (OFL) may be a polarizing film. The optical functional layer (OFL) may have an opening (OFL_OP) corresponding to a transmission region (TA). Accordingly, the light transmittance of the transmission region (TA) may be significantly improved. The opening (OFL_OP) of the optical functional layer (OFL) may be filled with a transparent material such as an optically clear resin (OCR).

[0070] In some embodiments, the optical functional layer (OFL) may be provided as a filter plate comprising a black matrix and color filters.

[0071] A panel protection member (PB) may be attached to the lower part of a substrate (100) to support and protect the substrate (100). The panel protection member (PB) may be provided with an opening (PB_OP) corresponding to a component area (CA). By providing an opening (PB_OP) in the panel protection member (PB), the light transmittance of the component area (CA) can be improved. The panel protection member (PB) may be provided by including polyethylene terephthalate (PET) or polyimide (PI).

[0072] The area of ​​the component area (CA) can be provided to be larger than the area where the component (20) is placed. Accordingly, the area of ​​the opening (PB_OP) provided in the panel protection member (PB) may not match the area of ​​the component area (CA).

[0073] Additionally, a plurality of components (20) may be arranged in the component area (CA). The plurality of components (20) may have different functions from each other. For example, the plurality of components (20) may include at least two of a camera (imaging element), a solar cell, a flash, a proximity sensor, an illuminance sensor, and an iris sensor.

[0074] FIG. 3 is a plan view schematically illustrating a display panel that may be included in a display device according to one embodiment of the present invention.

[0075] Referring to FIG. 3, various components forming a display panel (10) may be placed on a substrate (100). The substrate (100) may include a display area (DA) and a peripheral area (PA) surrounding the display area (DA).

[0076] The display area (DA) may include a main area (MA) where a main image is displayed, and a component area (CA) having a transparent area (TA) where an auxiliary image is displayed. As previously described, the component area (CA) may be located on one side of the main area (MA) or placed inside the display area (DA) and surrounded by the main area (MA). The auxiliary image may form a single overall image together with the main image, or the auxiliary image may be an image independent of the main image.

[0077] A plurality of first pixels (PX1), each comprising a first pixel circuit (PC1) and a first display element (DE1), are disposed in the main area (MA). The first pixel circuit (PC1) and the first display element (DE1) are disposed in the main area (MA) and may overlap at least partially with each other. Each first pixel (PX1) may emit light, for example, red, green, blue, or white.

[0078] The second pixel circuit (PC2) of each of the plurality of second pixels (PX2) may be placed in the peripheral area (PA), and the second display element (DE2) of each of the plurality of second pixels (PX2) may be placed in the component area (CA). The second pixel circuit (PC2) and the second display element (DE2) may not overlap each other. The second pixel circuit (PC2) and the second display element (DE2) may be connected by an electrode connection line (EWL). Each second pixel (PX2) may emit light, for example, red, green, blue, or white.

[0079] In one embodiment, the light-emitting area of ​​the second display element (DE2) may be larger than the light-emitting area of ​​the first display element (DE1).

[0080] Meanwhile, the transparent area (TA) of the component area (CA) may be arranged to surround a plurality of second display elements (DE2). Alternatively, the transparent area (TA) of the component area (CA) may be arranged in a grid form with a plurality of second display elements (DE2).

[0081] Since the component area (CA) has a transmission area (TA), the resolution of the component area (CA) may be lower than the resolution of the main area (MA). In other words, the number of multiple first display elements (DE1) per unit area may be greater than the number of multiple second display elements (DE2) per unit area. For example, the resolution of the component area (CA) may be about 1 / 2, 3 / 8, 1 / 3, 1 / 4, 2 / 9, 1 / 8, 1 / 9, 1 / 12.25, 1 / 16, etc. of the resolution of the main area (MA). For example, the resolution of the main area (MA) may be about 400 ppi or higher, and the resolution of the component area (CA) may be about 200 ppi or about 100 ppi.

[0082] Each pixel circuit driving the pixels can be electrically connected to an outer circuit placed in a peripheral area (PA). A first driving unit (DU1), a second driving unit (DU2), a pad unit (PAD), a first driving voltage supply line (11), a second driving voltage supply line (12), and a common voltage supply line (13) may be placed in the peripheral area (PA).

[0083] The first driving unit (DU1) may include a plurality of gate driving circuits. The gate driving circuit may be connected to a gate line (GL) extended in a first direction (e.g., ±x direction). The gate line (GL) may be connected to first pixel circuits (PC1) located in the same row, and may sequentially transmit electrical signals to the first pixel circuits (PC1) through the gate line (GL).

[0084] In FIG. 3, the gate line (GL) is depicted as a single wire, but the gate line (GL) may be composed of multiple wires. For example, the gate line (GL) may include a scan line, a light emission control line, etc.

[0085] Each of the plurality of gate driving circuits may include a scan driving circuit and a light emission control driving circuit. The scan driving circuit included in the gate driving circuit may provide a scan signal to the first pixel circuit (PC1) through a scan line. Additionally, the light emission control driving circuit included in the gate driving circuit may provide a light emission control signal to the first pixel circuit (PC1) through a light emission control line.

[0086] The second driving unit (DU2) may be positioned side-by-side with the first driving unit (DU1) with the display area (DA) in between. Pixels (PX) placed in the display area (DA) may be connected in common to the first driving unit (DU1) and the second driving unit (DU2). In another embodiment, some of the pixels (PX) placed in the display area (DA) may be electrically connected to the first driving unit (DU1), and the remainder may be connected to the second driving unit (DU2). In another embodiment, the second driving unit (DU2) may be omitted.

[0087] A pad portion (PAD) may be disposed on one side of the substrate (100). The pad portion (PAD) may be exposed without being covered by an insulating layer and connected to a display circuit board (30). A display driving portion (32) may be disposed on the display circuit board (30).

[0088] The display driver (32) can generate a control signal to be transmitted to the first driver (DU1) and the second driver (DU2). The display driver (32) generates a data signal, and the generated data signal can be transmitted to the first pixel circuits (PC1) through the fan-out wiring (FW) and the first data line (DL1) connected to the fan-out wiring (FW). The first data line (DL1) can be extended in a second direction (e.g., ±y direction) and connected to the first pixel circuits (PC1) located in the same column.

[0089] Additionally, the generated data signal can be transmitted to the second pixel circuits (PC2) through the second data line (DL2) connected to the first data line (DL1). The second data line (DL2) can be connected to the first data line (DL1) through the data connection line (DWL).

[0090] In one embodiment, the data connection line (DWL) may overlap at least partially with the component area (CA). In other words, at least a portion of the data connection line (DWL) may overlap with the component area (CA). At least a portion of the data connection line (DWL) may overlap with the edge area (CAe) of the component area (CA). Since at least a portion of the data connection line (DWL) overlaps with the edge area (CAe) where the component placed below the display panel (10) does not substantially receive light, the function of the component may not be limited.

[0091] The display driving unit (32) can supply a driving voltage (ELVDD, see FIG. 8) to the first driving voltage supply line (11) and / or the second driving voltage supply line (12), and can supply a common voltage (ELVSS, see FIG. 8) to the common voltage supply line (13). The driving voltage (ELVDD) is applied to the pixel circuit of the pixels through the driving voltage line (PL) connected to the first driving voltage supply line (11) and / or the second driving voltage supply line (12), and the common voltage (ELVSS) can be applied to the opposite electrode of the display element through the common voltage supply line (13).

[0092] The first driving voltage supply line (11) and the second driving voltage supply line (12) may be extended parallel to each other along a first direction (e.g., ±x direction) with the display area (DA) in between. The common voltage supply line (13) may have a shape with one side open in a loop shape and may partially surround the display area (DA).

[0093] FIG. 4 is an enlarged plan view schematically illustrating a display panel according to an embodiment of the present invention. Specifically, FIG. 4 illustrates a component area, a main area surrounding it, and a part of a surrounding area.

[0094] Referring to FIG. 4, a plurality of first pixels (PX1), each including a first pixel circuit (PC1) and a first display element (DE1), may be arranged in the main area (MA). In the main area (MA), the first pixel circuits (PC1) and the first display elements (DE1) may be arranged so as to overlap each other.

[0095] A plurality of first pixel circuits (PC1) can be arranged in a matrix shape along a first direction (e.g., ±x direction) and a second direction (e.g., ±y direction).

[0096] A plurality of first display elements (DE1) can each emit one of red, green, or blue light. Among the plurality of first display elements (DE1), the first display elements (DE1) that emit red light may be referred to as the first red display elements (DE1r), the first display elements (DE1) that emit green light may be referred to as the first green display elements (DE1g), and the first display elements (DE1) that emit blue light may be referred to as the first blue display elements (DE1b).

[0097] In one embodiment, a plurality of first pixels (PX1) may be arranged in a pentile structure. In other words, a plurality of first display elements (DE1) may be arranged in a pentile structure. For example, a first red display element (DE1r) may be placed at the first and third vertices facing each other among the vertices of a virtual rectangle with the center point of the first green display element (DE1g) as the center point of the rectangle, and a first blue display element (DE1b) may be placed at the remaining second and fourth vertices. The light-emitting area of ​​the first green display element (DE1g) may be smaller than the light-emitting area of ​​the first red display element (DE1r) and the light-emitting area of ​​the first blue display element (DE1b).

[0098] This pixel array structure is called a Pentile Matrix structure or Pentile structure, and by applying a rendering drive that expresses color by sharing adjacent pixels, high resolution can be achieved with a small number of pixels.

[0099] Although FIG. 4 illustrates a plurality of first pixels (PX1) arranged in a pentile matrix structure, in other embodiments, the plurality of first pixels (PX1) may be arranged in various shapes such as a stripe structure, a mosaic array structure, or a delta array structure.

[0100] Multiple second display elements (DE2) may be placed in the component area (CA). An area in the component area (CA) where the second display elements (DE2) are not placed may be defined (or referred to) as a high light transmittance area (TA). An area in the component area (CA) that does not overlap with the second display elements (DE2) may be defined (or referred to) as a high light transmittance area (TA).

[0101] A plurality of second display elements (DE2) can each emit one of red, green, or blue light. Among the plurality of second display elements (DE2), the second display elements (DE2) that emit red light may be referred to as second red display elements (DE2r), the second display elements (DE2) that emit green light may be referred to as second green display elements (DE2g), and the second display elements (DE2) that emit blue light may be referred to as second blue display elements (DE2b).

[0102] Multiple second display elements (DE2) can be arranged in various shapes. Multiple second display elements (DE2) may form a group by combining some of the second display elements (DE2), and within the group, they can be arranged in various shapes such as a pentile structure, a stripe structure, a mosaic array structure, or a delta array structure. At this time, the distance between the second display elements (DE2) arranged within the group may be the same as the distance between the first display elements (DE1).

[0103] Alternatively, as illustrated in FIG. 4, the second display elements (DE2) may be distributed within the component area (CA). The distance between the second display elements (DE2) may be greater than the distance between the first display elements (DE1). For example, the distance between the second red display element (DE2r) and the second green display element (DE2g) may be greater than the distance between the first red display element (DE1r) and the first green display element (DE1g). The distance between the second green display element (DE2g) and the second blue display element (DE2b) may be greater than the distance between the first green display element (DE1g) and the first blue display element (DE1b). The distance between the second red display element (DE2r) and the second blue display element (DE2b) may be greater than the distance between the first red display element (DE1r) and the first blue display element (DE1b).

[0104] In one embodiment, the number of first display elements (DE1) per unit area may be greater than the number of second display elements (DE2) per unit area. For example, the number of second display elements (DE2) and the number of first display elements (DE1) arranged per unit area may be provided in a ratio of 1:2, 1:4, 1:8, 1:9, etc. In other words, the resolution of the component area (CA) may be 1 / 2, 1 / 4, 1 / 8, 1 / 9, etc. of the resolution of the main area (MA).

[0105] In one embodiment, the light-emitting area of ​​the second display element (DE2) may be larger than the light-emitting area of ​​the first display element (DE1). For example, the light-emitting area of ​​the second red display element (DE2r) may be larger than the light-emitting area of ​​the first red display element (DE1r). The light-emitting area of ​​the second green display element (DE2g) may be larger than the light-emitting area of ​​the first green display element (DE1g). The light-emitting area of ​​the second blue display element (DE2b) may be larger than the light-emitting area of ​​the first blue display element (DE1b). The difference between the light-emitting area of ​​the first display element (DE1) and the light-emitting area of ​​the second display element (DE2) may be determined based on the difference in brightness and / or resolution between the main area (MA) and the component area (CA).

[0106] In the peripheral area (PA), a plurality of second pixel circuits (PC2) that implement the light emission of a plurality of second display elements (DE2) may be disposed. Since the second pixel circuits (PC2) are not disposed in the component area (CA), the component area (CA) can secure a wider transmission area (TA).

[0107] The second pixel circuits (PC2) can each be connected to the second display elements (DE2) through electrode connection lines (EWL). Being connected to the second display elements (DE2) means that the electrode connection lines (EWL) are electrically connected to the pixel electrodes of the second display elements (DE2).

[0108] Meanwhile, as an RC delay may occur when the length of the electrode connection line (EWL) increases, the second pixel circuits (PC2) can be arranged taking into account the length of the electrode connection lines (EWL).

[0109] In one embodiment, the second pixel circuits (PC2) may be arranged on an extension line connecting the second display elements (DE2) arranged along the second direction (e.g., ±y direction). Additionally, the second pixel circuits (PC2) may be arranged along the second direction (e.g., ±y direction) as many times as the number of second display elements (DE2) arranged along the second direction (e.g., ±y direction).

[0110] In FIG. 4, the second pixel circuits (PC2) are shown arranged along the second direction (e.g., ±y direction), but in another embodiment, the second pixel circuits (PC2) may be arranged along the first direction (e.g., ±x direction).

[0111] The electrode connection lines (EWL) extend in a second direction (e.g., ±y direction) so that the second display elements (DE2) and the second pixel circuits (PC2) can be connected, respectively. The electrode connection lines (EWL) may be provided with a transparent conductive material. For example, the electrode connection lines (EWL) may be provided with a transparent conducting oxide (TCO). The electrode connection lines (EWL) may include conductive oxides such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), or aluminum zinc oxide (AZO).

[0112] In FIG. 4, the electrode connection line (EWL) is shown as being integrally provided from the peripheral region (PA) to the second indicator element (DE2) of the component region (CA), but in another embodiment, the electrode connection line (EWL) may include a first connection part and a second connection part provided with different materials.

[0113] For example, the first connection portion may be a portion disposed in a peripheral area (PA) and connected to a second pixel circuit (PC2). The first connection portion may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may be formed as a multilayer or single layer including the above materials.

[0114] The second connecting portion is positioned in the component region (CA) and may be a portion connected to the first connecting portion at the edge of the component region (CA). The second connecting portion may be provided with a transparent conductive material. For example, the electrode connecting line (EWL) may be provided with a transparent conducting oxide (TCO). The electrode connecting line (EWL) may include a conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), or aluminum zinc oxide (AZO).

[0115] A plurality of first data lines (DL1) may be arranged in the main area (MA), and a plurality of second data lines (DL2) may be arranged in the peripheral area (PA). The first data line (DL1) may be connected to a first pixel circuit (PC1), and the second data line (DL2) may be connected to a second pixel circuit (PC2). For example, the first data line (DL1) may be extended in a second direction (e.g., ±y direction) and connected to first pixel circuits (PC1) arranged in the same column among a plurality of first pixel circuits (PC1). The second data line (DL2) may be extended in a second direction (e.g., ±y direction) and connected to second pixel circuits (PC2) arranged in the same column among a plurality of second pixel circuits (PC2).

[0116] The second data line (DL2) can be connected to the first data line (DL1) through the data connection line (DWL). In other words, the data connection line (DWL) can connect the first data line (DL1) to the second data line (DL2). For example, as illustrated in FIG. 4, the second data line (DL2) can be connected through the data connection line (DWL) to the first data line (DL1) that is disconnected by the component area (CA) among the first data lines (DL1). The second data line (DL2) can be connected through the data connection line (DWL) to the first data line (DL1) that substantially corresponds to a virtual line extending along a second direction (e.g., ±y direction) from the second data line (DL2) among the first data lines (DL1). In this case, the same signal can be applied to the first pixel circuits (PC1) and the second pixel circuits (PC2) that are placed in substantially the same column.

[0117] Meanwhile, although FIG. 4 illustrates that the data connection line (DWL) and the first data line (DL1) are connected to each other on the component area (CA), in another embodiment, the data connection line (DWL) and the first data line (DL1) may be connected to each other on the main area (MA) or on the boundary between the main area (MA) and the component area (CA).

[0118] The data connection line (DWL) is placed on a different layer from the first data line (DL1) and the second data line (DL2), so that the data connection line (DWL) can be connected to the first data line (DL1) and the second data line (DL2), respectively, through contact holes. For example, as shown in FIG. 5 which will be described later, the data connection line (DWL) is interposed between the substrate (100) and the semiconductor layer (Act), and the first data line (DL1) and the second data line (DL2) can be placed on the semiconductor layer (Act).

[0119] Meanwhile, when a data connection line (DWL) is interposed between a substrate (100) and a semiconductor layer (Act), the probability of external light reaching the data connection line (DWL) is low (or, the reflectivity of the data connection line (DWL) by external light is low), so the data connection line (DWL) can be placed only in a part of the display area (DA) and prevented from being visible.

[0120] The data connection line (DWL) may have a shape that is bent at least once. The data connection line (DWL) may include a plurality of parts that extend in a first direction (e.g., ±x direction) and a second direction (e.g., ±y direction), respectively. For example, the data connection line (DWL) may include a first part (DWLa) that overlaps with a component area (CA), a second part (DWLb) that extends in the first direction (e.g., ±x direction), a third part (DWLc) that extends in the second direction (e.g., ±y direction), and a fourth part (DWLd) that extends in the first direction (e.g., ±x direction).

[0121] Both ends of the first part (DWLa) of the data connection line (DWL) can be connected to the first data line (DL1) and the second part (DWLb) of the data connection line (DWL), respectively. Both ends of the second part (DWLb) of the data connection line (DWL) can be connected to the first part (DWLa) and the third part (DWLc) of the data connection line (DWL), respectively. Both ends of the third part (DWLc) of the data connection line (DWL) can be connected to the second part (DWLb) and the fourth part (DWLd) of the data connection line (DWL), respectively. Both ends of the fourth part (DWLd) of the data connection line (DWL) can be connected to the third part (DWLc) and the second data line (DL2) of the data connection line (DWL), respectively.

[0122] A first part (DWLa) of the data connection line (DWL) may overlap with a component area (CA). A first part (DWLa) of the data connection line (DWL) may overlap with an edge area (CAe) of the component area (CA). A first part (DWLa) of the data connection line (DWL) may be positioned to bypass the central area (CAm) of the component area (CA). A first part (DWLa) of the data connection line (DWL) may be positioned along the shape of the central area (CAm). For example, as shown in FIG. 5, if the planar shape of the central area (CAm) is circular, the first part (DWLa) of the data connection line (DWL) may have a curve.

[0123] Meanwhile, since the first part (DWLa) of the data connection line (DWL) is positioned to bypass the central area (CAm) where the component placed at the bottom of the display panel substantially receives light, the function of the component may not be restricted. Additionally, since the first part (DWLa) of the data connection line (DWL) overlaps with the component area (CA), the area where the data connection line (DWL) and the main area (MA) overlap can be reduced. Since the area where the data connection line (DWL) and the main area (MA) overlap is reduced, interference between the elements within the first pixel circuits (PC1) placed in the main area (MA) by the data connection line (DWL) can be reduced.

[0124] The second part (DWLb) and the third part (DWLc) of the data connection line (DWL) may overlap at least partially with the main area (MA). The fourth part (DWLd) of the data connection line (DWL) may overlap with the surrounding area (PA).

[0125] FIG. 5 is an exemplary cross-sectional view of the data connection lines of FIG. 4 cut along II' and II-II'. FIG. 5 also shows a schematic cross-sectional view of a portion of the main area.

[0126] Referring to FIG. 5, the first data line (DL1) and the second data line (DL2) can be connected to each other through a data connection line (DWL). The same signal can be applied to the first data line (DL1) and the second data line (DL2) connected to each other through the data connection line (DWL).

[0127] The data connection line (DWL) may be placed on a different layer from the first data line (DL1) and the second data line (DL2), and may be connected to the first data line (DL1) and the second data line (DL2), respectively, through contact holes formed in the insulating layers. For example, the data connection line (DWL) may be interposed between the substrate (100) and the semiconductor layer (Act), and the first data line (DL1) and the second data line (DL2) may be placed on the semiconductor layer (Act).

[0128] When a data connection line (DWL) is interposed between a substrate (100) and a semiconductor layer (Act), the probability of external light reaching the data connection line (DWL) is low (or, the reflectivity of the data connection line (DWL) by external light is low), so the data connection line (DWL) placed only in a part of the display area (DA) can be prevented from being visible by external light.

[0129] Hereinafter, with reference to FIG. 5, the configuration included in the display panel will be described in more detail according to the stacked structure, and the positional relationship of the data connection line (DWL), the first data line (DL1), and the second data line (DL2) will be described.

[0130] The substrate (100) may include glass or a polymer resin. The polymer resin may include polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate. The substrate (100) containing the polymer resin may have flexible, rollable, or bendable properties. The substrate (100) may have a multilayer structure including a layer containing the aforementioned polymer resin and an inorganic layer (not shown).

[0131] The buffer layer (111) can reduce or block the penetration of foreign matter, moisture, or outside air from the bottom of the substrate (100) and can provide a flat surface on the substrate (100). The buffer layer (111) may include an inorganic material such as an oxide or a nitride, an organic material, or an organic-inorganic composite, and may be composed of a single layer or a multilayer structure of inorganic and organic materials.

[0132] A barrier layer (not shown) may be further included between the substrate (100) and the buffer layer (111). The barrier layer may serve to prevent or minimize the penetration of impurities from the substrate (100), etc., into the semiconductor layer (Act). The barrier layer may include inorganic materials such as oxides or nitrides, organic materials, or organic-inorganic composites, and may be composed of a single layer or a multilayer structure of inorganic and organic materials.

[0133] A data connection line (DWL) may be interposed between the substrate (100) and the buffer layer (111). The data connection line (DWL) may be composed of a single layer or multiple layers, including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc. For example, the data connection line (DWL) may be a single layer of Mo. Alternatively, the data connection line (DWL) may be composed of a multilayer structure of Ti / Al / Ti. In another embodiment, the data connection line (DWL) may be provided with a transparent conducting oxide (TCO).

[0134] Meanwhile, when the data connection line (DWL) contains Mo, the reflectivity of the data connection line (DWL) to external light is low due to the material properties, so the data connection line (DWL) placed only in a part of the display area (DA) can be prevented from being visible.

[0135] A semiconductor layer (Act) may be disposed on the buffer layer (111). The semiconductor layer (Act) may include amorphous silicon or polysilicon. In another embodiment, the semiconductor layer (Act) may include an oxide of at least one material selected from the group comprising indium (In), gallium (Ga), stanium (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), aluminum (Al), cesium (Cs), cerium (Ce), and zinc (Zn).

[0136] The semiconductor layer (Act) may include a channel region and source and drain regions disposed on both sides of the channel region. The semiconductor layer (Act) may be composed of a single layer or multiple layers.

[0137] A first gate insulating layer (113) and a second gate insulating layer (115) may be laminated and disposed on a substrate (100) to cover a semiconductor layer (Act). The first gate insulating layer (113) and the second gate insulating layer (115) may be silicon oxide (SiO2) or silicon nitride (SiN x It may include silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO2), etc.

[0138] A gate electrode (GE) may be disposed on the first gate insulating layer (113). The gate electrode (GE) may be disposed to overlap at least partially with the semiconductor layer (Act). The gate electrode (GE) may be composed of molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may be a single layer or a multilayer. As an example, the gate electrode (GE) may be a single layer of Mo.

[0139] A second electrode (CE2) of a storage capacitor (Cst) may be disposed on the second gate insulating layer (115). The second electrode (CE2) of the storage capacitor (Cst) may be composed of molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may be made of a single layer or multiple layers. As an example, the second electrode (CE2) of the storage capacitor (Cst) may be a single layer of Mo.

[0140] In one embodiment, the storage capacitor (Cst) is provided with a first electrode (CE1) and a second electrode (CE2) and may overlap with the transistor (TFT) as shown in FIG. 5. For example, the gate electrode (GE) of the transistor (TFT) may function as the first electrode (CE1) of the storage capacitor (Cst). Alternatively, the storage capacitor (Cst) may not overlap with the transistor (TFT) and may exist separately.

[0141] The second electrode (CE2) of the storage capacitor (Cst) overlaps with the first electrode (CE1) with the second gate insulating layer (115) in between, forming a capacitance. In this case, the second gate insulating layer (115) can function as a dielectric layer of the storage capacitor (Cst).

[0142] An interlayer insulating layer (117) may be provided on the second gate insulating layer (115) to cover the second electrode (CE2) of the storage capacitor (Cst). The interlayer insulating layer (117) may be silicon oxide (SiO2) or silicon nitride (SiN x It may include silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO2), etc.

[0143] A first connecting electrode (CM1), a second connecting electrode (CM2), and a third connecting electrode (CM3) may be disposed on the interlayer insulating layer (117). The first connecting electrode (CM1), the second connecting electrode (CM2), and the third connecting electrode (CM3) may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may be formed as a multilayer or single layer including the above materials. As an example, the first connecting electrode (CM1), the second connecting electrode (CM2), and the third connecting electrode (CM3) may be formed as a multilayer structure of Ti / Al / Ti.

[0144] The first connection electrode (CM1) can be connected to the semiconductor layer (Act) through a contact hole formed in the first gate insulating layer (113), the second gate insulating layer (115), and the interlayer insulating layer (117). The second connection electrode (CM2) can be connected to the data connection line (DWL) through a contact hole formed in the buffer layer (111), the first gate insulating layer (113), the second gate insulating layer (115), and the interlayer insulating layer (117). The third connection electrode (CM3) can be connected to the data connection line (DWL) through a contact hole formed in the buffer layer (111), the first gate insulating layer (113), the second gate insulating layer (115), and the interlayer insulating layer (117).

[0145] The first connecting electrode (CM1), the second connecting electrode (CM2), and the third connecting electrode (CM3) may be covered with an inorganic protective layer (not shown). The inorganic protective layer is silicon nitride (SiN x ) and silicon oxide (SiO x It may be a single film or a multilayer film. The inorganic protective layer may be introduced to cover and protect some wiring placed on the interlayer insulating layer (117).

[0146] A flattening layer (119) is disposed to cover the first connecting electrode (CM1), the second connecting electrode (CM2), and the third connecting electrode (CM3), and the flattening layer (119) may include contact holes for connecting the transistor (TFT) and the pixel electrode (210).

[0147] The flattening layer (119) may be formed as a single layer or a multilayer film made of organic material and provides a flat upper surface. Such flattening layer (119) may include general-purpose polymers such as BCB (Benzocyclobutene), polyimide, HMDSO (Hexamethyldisiloxane), polymethylmethacrylate (PMMA), or polystyrene (PS), polymer derivatives having a phenolic group, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluorine polymers, p-xylene polymers, vinyl alcohol polymers, and blends thereof.

[0148] The flattening layer (119) may include a first flattening layer (119a) and a second flattening layer (119b). A fourth connecting electrode (CM4), a first data line (DL1), and a second data line (DL2) may be disposed on the first flattening layer (119a). The fourth connecting electrode (CM4), the first data line (DL1), and the second data line (DL2) may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may be formed as a multilayer or single layer including the above materials. As an example, the fourth connecting electrode (CM4), the first data line (DL1), and the second data line (DL2) may be formed as a multilayer structure of Ti / Al / Ti.

[0149] The fourth connection electrode (CM4) can be connected to the first connection electrode (CM1) through a contact hole formed in the first flattening layer (119a) and can be connected to a transistor (TFT) connected to the first connection electrode (CM1). The first data line (DL1) can be connected to the second connection electrode (CM2) through a contact hole formed in the first flattening layer (119a) and can be connected to a data connection line (DML) connected to the second connection electrode (CM2). The second data line (DL2) can be connected to the third connection electrode (CM3) through a contact hole formed in the first flattening layer (119a) and can be connected to a data connection line (DML) connected to the third connection electrode (CM3).

[0150] A first display element (DE1) may be disposed on the flattening layer (119). The first display element (DE1) may be an organic light-emitting diode (OLED). The first display element (DE1) may include a pixel electrode (210), an intermediate layer (220) including an organic light-emitting layer, and a counter electrode (230).

[0151] The first display element (DE1) can be connected to a transistor (TFT) through a contact hole formed in the second flattening layer (119b) and a fourth connecting electrode (CM4). As a result, the first display element (DE1) can be electrically connected to a first pixel circuit (PC1) including a transistor (TFT).

[0152] The pixel electrode (210) may be a (semi)transparent electrode or a reflective electrode. In some embodiments, the pixel electrode (210) may have a reflective layer formed of Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, and compounds thereof, and a transparent or translucent electrode layer formed on the reflective layer. The transparent or translucent electrode layer may have at least one selected from the group comprising indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), and aluminum zinc oxide (AZO). In some embodiments, the pixel electrode (210) may be provided as ITO / Ag / ITO.

[0153] In the display area of ​​the substrate (100), a pixel defining film (121) may be disposed on the flattening layer (119). The pixel defining film (121) may cover the edge of the pixel electrode (210) and may have an opening that exposes the central part of the pixel electrode (210). The light-emitting area of ​​the first display element (DE1) may be defined by the opening.

[0154] The pixel defining film (121) can prevent arcs from occurring at the edge of the pixel electrode (210) by increasing the distance between the edge of the pixel electrode (210) and the opposing electrode (230) above the pixel electrode (210).

[0155] The pixel definition film (121) can be formed by a method such as spin coating, using one or more organic insulating materials selected from the group consisting of polyimide, polyamide, acrylic resin, benzocyclobutene and phenolic resin.

[0156] The intermediate layer (220) is disposed within the opening formed by the pixel defining film (121) and may include an organic light-emitting layer. The organic light-emitting layer may include an organic material comprising a fluorescent or phosphorescent material that emits red, green, blue, or white light. The organic light-emitting layer may be a low-molecular-weight organic material or a high-molecular-weight organic material, and functional layers such as a hole transport layer (HTL), a hole injection layer (HIL), an electron transport layer (ETL), or an electron injection layer (EIL) may be optionally further disposed below and above the organic light-emitting layer.

[0157] The counter electrode (230) may be a transparent electrode or a reflective electrode. In some embodiments, the counter electrode (230) may be a transparent or translucent electrode and may be formed from a metal thin film with a low work function comprising Li, Ca, LiF / Ca, LiF / Al, Al, Ag, Mg, and compounds thereof. Additionally, a transparent conductive oxide (TCO) film such as ITO, IZO, ZnO, or In2O3 may be further disposed on the metal thin film. The counter electrode (230) is disposed across the display area and may be disposed on top of the intermediate layer (220) and the pixel defining film (121). The counter electrode (230) may be formed integrally in a plurality of organic light-emitting diodes (OLEDs) and may correspond to a plurality of pixel electrodes (210).

[0158] Since these organic light-emitting diodes (OLEDs) can be easily damaged by external moisture or oxygen, an encapsulation layer (not shown) may cover and protect these organic light-emitting diodes (OLEDs). The encapsulation layer covers a display area and may extend to at least a portion of the surrounding area. This encapsulation layer may include a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer.

[0159] FIG. 6 is an enlarged plan view schematically illustrating a display panel according to an embodiment of the present invention. FIG. 6 is a modified embodiment of FIG. 4, differing in the structure of the data connection lines. Hereinafter, redundant content will be replaced by the description of FIG. 4, and the differences will be explained primarily.

[0160] Referring to FIG. 6, at least one of the plurality of data connection lines (DWL) may be placed on a component area (CA). At least one of the plurality of data connection lines (DWL) may be placed on an edge area (CAe) of the component area (CA) to bypass the central area (CAm) of the component area (CA). In other words, at least one of the plurality of data connection lines (DWL) may not overlap with the main area (MA).

[0161] When at least one of the multiple data connection lines (DWL) is placed on the component area (CA), the overlapping area between the data connection lines (DWL) and the main area (MA) may be reduced. An illuminance sensor, a proximity sensor, etc. may be placed below a portion of the main area (MA) that does not overlap with the data connection lines (DWL). Since the overlapping area between the data connection lines (DWL) and the main area (MA) may be reduced, the illuminance sensor, a proximity sensor, etc. may be placed closer to the component area (CA).

[0162] In FIG. 6, some of the multiple data connection lines (DWL) are shown placed on the component area (CA), but all of the multiple data connection lines (DWL) may be placed on the component area (CA).

[0163] FIG. 7 is an enlarged plan view schematically illustrating a display panel according to an embodiment of the present invention. FIG. 7 is a modified embodiment of FIG. 4, differing in the structure of the component area. Hereinafter, overlapping content will be replaced by the description of FIG. 4, and the differences will be explained primarily.

[0164] Referring to FIG. 7, the component region (CA) may include a first region (AR1) and a second region (AR2). The first region (AR1) and the second region (AR2) may be adjacent to each other. For example, the first region (AR1) and the second region (AR2) may be adjacent to each other along a second direction (e.g., ±y direction).

[0165] In FIG. 7, the first region (AR1) and the second region (AR2) are shown as being adjacent to each other along the second direction (e.g., ±y direction), but in another embodiment, the first region (AR1) and the second region (AR2) may be adjacent to each other along the first direction (e.g., ±x direction).

[0166] The first region (AR1) may correspond to the component region (CA) illustrated in FIG. 4. That is, a plurality of second display elements (DE2) may be placed in the first region (AR1). The area in the first region (AR1) where the second display elements (DE2) are not placed may be defined (or referred to) as a high light transmittance region (TA). Additionally, a central region (CAm) and an edge region (CAe) may be defined in the first region (AR1) depending on whether the component placed below the display panel substantially receives light.

[0167] In the second area (AR2), a plurality of third pixels (PX3), each including a third pixel circuit (PC3) and a third display element (DE3), may be arranged. In the second area (AR2), the third pixel circuits (PC3) and the third display elements (DE3) may be arranged so as to overlap at least partially with each other.

[0168] The third pixel circuits (PC3) can be arranged along a first direction (e.g., ±x direction) and a second direction (e.g., ±y direction). Each of the third display elements (DE3) can emit light of one of red, green, or blue. The third display elements (DE3) can be arranged in various shapes. The arrangement structure of the third display elements (DE3) can be substantially the same as the arrangement structure of the second display elements (DE2).

[0169] For example, as illustrated in FIG. 7, the third display elements (DE3) may be distributed within the second area (AR2). The distance between the third display elements (DE3) may be greater than the distance between the first display elements (DE1). The distance between the third display elements (DE3) may be substantially the same as the distance between the second display elements (DE2).

[0170] In one embodiment, the number of first display elements (DE1) per unit area may be greater than the number of third display elements (DE3) per unit area. For example, the number of third display elements (DE3) and the number of first display elements (DE1) arranged per unit area may be provided in a ratio of 1:2, 1:4, 1:8, 1:9, etc. In other words, the resolution of the second area (AR2) may be 1 / 2, 1 / 4, 1 / 8, 1 / 9, etc. of the resolution of the main area (MA).

[0171] In one embodiment, the number of third display elements (DE3) per unit area may be the same as the number of second display elements (DE2) per unit area. In other words, the resolution of the second area (AR2) may be the same as the resolution of the first area (AR1).

[0172] In one embodiment, the light-emitting area of ​​the third display element (DE3) may be larger than the light-emitting area of ​​the first display element (DE1). The difference between the light-emitting area of ​​the first display element (DE1) and the light-emitting area of ​​the third display element (DE3) may be determined based on the difference in brightness and / or resolution between the main area (MA) and the second area (AR2). The light-emitting area of ​​the third display element (DE3) may be the same as the light-emitting area of ​​the second display element (DE2).

[0173] Meanwhile, although FIG. 7 illustrates that the data connection lines (DWL) each overlap at least partially with the component area (CA), as in another embodiment, at least one of the plurality of data connection lines (DWL) may be placed on the component area (CA) as described above in FIG. 6. At least one of the plurality of data connection lines (DWL) may bypass the central area (CAm) of the component area (CA) on the edge area (CAe) of the component area (CA) and may overlap at least partially with the second area (AR2). In other words, at least one of the plurality of data connection lines (DWL) may not overlap with the main area (MA).

[0174] FIG. 8 illustrates an equivalent circuit diagram of a pixel according to one embodiment of the present invention.

[0175] Referring to FIG. 8, a pixel (PX) is connected to first to fourth scan lines (GWL, GCL, GIL, GBL) that respectively transmit first to fourth scan signals (GW, GC, GI, GB), a data line (DL) that transmits a data voltage (Dm), and a light emission control line (EL) that transmits a light emission control signal (EM). The pixel (PX) is connected to a driving voltage line (PL) that transmits a driving voltage (ELVDD) and an initialization voltage line (VL) that transmits an initialization voltage (VINT). The pixel (PX) is connected to a common electrode to which a common voltage (ELVSS) is applied. The pixel (PX) may correspond to the first pixel (PX1) and / or the second pixel (PX2) shown in FIG. 3, respectively.

[0176] The elements included in the pixel (PX) are described below.

[0177] A pixel (PX) includes a display element (DE), first to seventh transistors (T1 to T7), and a storage capacitor (Cst). The display element (DE) may be an organic light-emitting diode having an anode and a cathode. The cathode may be a common electrode to which a common voltage (ELVSS) is applied. The first to seventh transistors (T1 to T7) may be formed as thin-film transistors.

[0178] Some of the first to seventh transistors (T1 to T7) may be equipped with NMOS (n-channel MOSFETs), and the remainder may be equipped with PMOS (p-channel MOSFETs). For example, among the first to seventh transistors (T1 to T7), the third transistor (T3) and the fourth transistor (T4) may be equipped with NMOS (n-channel MOSFETs), and the remainder may be equipped with PMOS (p-channel MOSFETs).

[0179] In another embodiment, among the first to seventh transistors (T1 to T7), the third transistor (T3), the fourth transistor (T4), and the seventh transistor (T7) may be provided as NMOS, and the remainder may be provided as PMOS. Alternatively, only one of the first to seventh transistors (T1 to T7) may be provided as NMOS and the remainder as PMOS. Alternatively, all of the first to seventh transistors (T1 to T7) may be provided as NMOS or PMOS.

[0180] The first transistor (T1) is a driving transistor in which the magnitude of the drain current is determined according to the gate-source voltage, and the second to seventh transistors (T2 to T7) may be switching transistors that are turned on / off according to the gate-source voltage, substantially the gate voltage.

[0181] The first transistor (T1) may be referred to as a driving transistor, the second transistor (T2) as a scan transistor, the third transistor (T3) as a compensation transistor, the fourth transistor (T4) as a gate initialization transistor, the fifth transistor (T5) as an operation control transistor, the sixth transistor (T6) as a light emission control transistor, and the seventh transistor (T7) as an anode initialization transistor.

[0182] A storage capacitor (Cst) is connected between the driving voltage line (PL) and the gate of the driving transistor (T1). The storage capacitor (Cst) may have a second electrode (CE2) connected to the driving voltage line (PL) and a first electrode (CE1) connected to the gate of the driving transistor (T1).

[0183] The driving transistor (T1) can control the magnitude of the driving current (Id) flowing from the driving voltage line (PL) to the display element (DE) according to the gate-source voltage. The driving transistor (T1) may have a gate connected to the first electrode (CE1) of the storage capacitor (Cst), a source connected to the driving voltage line (PL) through the operation control transistor (T5), and a drain connected to the display element (DE) through the light emission control transistor (T6).

[0184] The driving transistor (T1) can output a driving current (Id) to the display element (DE) according to the gate-source voltage. The magnitude of the driving current (Id) is determined based on the difference between the gate-source voltage and the threshold voltage of the driving transistor (T1). The display element (DE) receives the driving current (Id) from the driving transistor (T1) and can emit light with a brightness corresponding to the magnitude of the driving current (Id).

[0185] The scan transistor (T2) transmits a data voltage (Dm) to the source of the driving transistor (T1) in response to the first scan signal (GW). The scan transistor (T2) may have a gate connected to the first scan line (GWL), a source connected to the data line (DL), and a drain connected to the source of the driving transistor (T1).

[0186] The compensation transistor (T3) connects the drain and gate of the driving transistor (T1) to each other in response to the second scan signal (GC). The compensation transistor (T3) may have a gate connected to the second scan line (GCL), a source connected to the gate of the driving transistor (T1), and a drain connected to the drain of the driving transistor (T1).

[0187] The gate initialization transistor (T4) applies an initialization voltage (VINT) to the gate of the driving transistor (T1) in response to the third scan signal (GI). The gate initialization transistor (T4) may have a gate connected to the third scan line (GIL), a source connected to the initialization voltage line (VL), and a drain connected to the gate of the driving transistor (T1).

[0188] The anode initialization transistor (T7) applies an initialization voltage (VINT) to the anode of the display element (DE) in response to the fourth scan signal (GB). The anode initialization transistor (T7) may have a gate connected to the fourth scan line (GBL), a source connected to the anode of the display element (DE), and a drain connected to the initialization voltage line (VL).

[0189] In FIG. 8, the gate initialization transistor (T4) and the anode initialization transistor (T7) are shown connected to the same initialization voltage line (VL), but in another embodiment, the gate initialization transistor (T4) and the anode initialization transistor (T7) may be connected to different initialization voltage lines, respectively.

[0190] The operation control transistor (T5) can connect the source of the driving voltage line (PL) and the driving transistor (T1) to each other in response to the light emission control signal (EM). The operation control transistor (T5) may have a gate connected to the light emission control line (EL), a source connected to the driving voltage line (PL), and a drain connected to the source of the driving transistor (T1).

[0191] The light-emitting control transistor (T6) can connect the drain of the driving transistor (T1) and the anode of the display element (DE) to each other in response to the light-emitting control signal (EM). The light-emitting control transistor (T6) may have a gate connected to the light-emitting control line (EL), a source connected to the drain of the driving transistor (T1), and a drain connected to the anode of the display element (DE).

[0192] The first scan signal (GW) and the second scan signal (GC) can be substantially synchronized. The third scan signal (GI) can be substantially synchronized with the first scan signal (GW) of the previous row. The fourth scan signal (GB) can be substantially synchronized with the first scan signal (GW). According to another example, the fourth scan signal (GB) can be substantially synchronized with the first scan signal (GW) of the next row.

[0193] The specific operation process of a pixel (PX) according to one embodiment is described in detail below.

[0194] First, when a high-level light emission control signal (EM) is received, the operation control transistor (T5) and the light emission control transistor (T6) are turned off, the driving transistor (T1) stops outputting the driving current (Id), and the display element (DE) stops emitting light.

[0195] Subsequently, during the gate initialization period when a high-level third scan signal (GI) is received, the gate initialization transistor (T4) is turned on, and the initialization voltage (VINT) is applied to the gate of the driving transistor (T1), that is, to the first electrode (CE1) of the storage capacitor (Cst). The difference (ELVDD - VINT) between the driving voltage (ELVDD) and the initialization voltage (VINT) is stored in the storage capacitor (Cst).

[0196] Subsequently, during the data writing period when a low-level first scan signal (GW) and a high-level second scan signal (GC) are received, the scan transistor (T2) and the compensation transistor (T3) are turned on, and the data voltage (Dm) is received at the source of the driving transistor (T1). The driving transistor (T1) is diode-connected by the compensation transistor (T3) and forward-biased. The gate voltage of the driving transistor (T1) rises from the initialization voltage (VINT). When the gate voltage of the driving transistor (T1) becomes equal to the data compensation voltage (Dm - |Vth|), which is reduced by the threshold voltage (Vth) of the driving transistor (T1) from the data voltage (Dm), the driving transistor (T1) is turned off, and the rise of the gate voltage of the driving transistor (T1) stops. Accordingly, the difference (ELVDD - Dm + |Vth|) between the driving voltage (ELVDD) and the data compensation voltage (Dm - |Vth|) is stored in the storage capacitor (Cst).

[0197] Additionally, during the anode initialization period when a low-level fourth scan signal (GB) is received, the anode initialization transistor (T7) is turned on, and an initialization voltage (VINT) is applied to the anode of the display element (DE). By applying the initialization voltage (VINT) to the anode of the display element (DE) to completely de-emit the display element (DE), the phenomenon in which the display element (DE) emits light in response to the black gradation in the next frame can be eliminated.

[0198] The first scan signal (GW) and the fourth scan signal (GB) can be substantially synchronized, in which case the data write period and the anode initialization period may be the same period.

[0199] Subsequently, when a low-level light emission control signal (EM) is received, the operation control transistor (T5) and the light emission control transistor (T6) are turned on, and the driving transistor (T1) outputs a driving current (Id) corresponding to the voltage (ELVDD - Dm) obtained by subtracting the threshold voltage (|Vth|) of the driving transistor (T1) from the voltage stored in the storage capacitor (Cst), that is, the source-gate voltage (ELVDD - Dm + |Vth|) of the driving transistor (T1), and the display element (DE) can emit light with a brightness corresponding to the magnitude of the driving current (Id).

[0200] In this embodiment, at least one of the first to seventh transistors (T1 to T7) includes a semiconductor layer containing oxide, and the others include a semiconductor layer containing silicon.

[0201] Specifically, the driving transistor (T1), which directly affects the brightness of the display device, is configured to include a semiconductor layer composed of polycrystalline silicon with high reliability, thereby enabling the implementation of a high-resolution display device.

[0202] Meanwhile, oxide semiconductors possess high carrier mobility and low leakage current, so the voltage drop is not significant even during long driving times. In other words, since the change in image color due to voltage drop is not significant even during low-frequency driving, low-frequency driving is possible.

[0203] As such, since oxide semiconductors have the advantage of low leakage current, at least one of the compensation transistor (T3), gate initialization transistor (T4), and anode initialization transistor (T7) connected to the gate of the driving transistor (T1) is adopted as an oxide semiconductor to prevent leakage current from flowing to the gate of the driving transistor (T1) while simultaneously reducing power consumption.

[0204] FIG. 9 is a plan view schematically illustrating a display panel that may be included in a display device according to one embodiment of the present invention.

[0205] Referring to FIG. 9, the display panel (10) may include a plurality of first pixel circuits (PC1) and a plurality of first display elements (DE1) disposed in a main area (MA), a plurality of second display elements (DE2) disposed in a component area (CA), and a plurality of second pixel circuits (PC2) disposed in a peripheral area (PA). The first pixel circuits (PC1) and the first display elements (DE1) may overlap each other, and the second pixel circuits (PC2) and the second display elements (DE2) may not overlap each other.

[0206] As described above in FIG. 4, a first data line (DL1) connected to a first pixel circuit (PC1) and a second data line (DL2) connected to a second pixel circuit (PC2) can be connected to each other through a data connection line (DWL). The data connection line (DWL) may include a first part (DWLa), a second part (DWLb) extended in a first direction (e.g., ±x direction), a third part (DWLc) extended in a second direction (e.g., ±y direction), and a fourth part (DWLd) extended in a first direction (e.g., ±x direction). The first part (DWLa) of the data connection line (DWL) overlaps with the edge region (CAe) of the component region (CA), the second part (DWLb) and the third part (DWLc) of the data connection line (DWL) overlap at least partially with the main region (MA), and the fourth part (DWLd) of the data connection line (DWL) may overlap with the surrounding region (PA).

[0207] The display panel (10) may include a plurality of auxiliary row lines (SRL) and a plurality of auxiliary column lines (SCL). Some of the plurality of auxiliary row lines (SRL) may be referred to as a first auxiliary row line (SRL1), and others as a second auxiliary row line (SRL2). Some of the plurality of auxiliary column lines (SCL) may be referred to as a first auxiliary column line (SCL1), and others as a second auxiliary column line (SCL2).

[0208] The first auxiliary row lines (SRL1) may be extended in a first direction (e.g., ±x direction). Some of the first auxiliary row lines (SRL1) may be positioned to the left of the component area (CA), and others may be positioned to the right. In other words, the first auxiliary row lines (SRL1) may be physically separated by the component area (CA).

[0209] A driving voltage (ELVDD, see FIG. 8) may be applied to the first auxiliary row lines (SRL1). For example, the first auxiliary row lines (SRL1) may be connected to auxiliary column lines (SCL) connected to the second driving voltage supply line (12).

[0210] Each of the first auxiliary row lines (SRL1) may include a plurality of row connection parts separated by third parts (DWLc) of the data connection lines (DWL).

[0211] In one embodiment, the number of row connections of each of the first auxiliary row lines (SRL1) may increase monotonically along the +y direction. In other words, the shorter the distance of the first auxiliary row line (SRL1) from the surrounding area (PA) along the +y direction, the greater the number of row connections of the first auxiliary row line (SRL1). This will be described in more detail in FIG. 10.

[0212] The second auxiliary row lines (SRL2) can be extended in the first direction (e.g., ±x direction). A driving voltage (ELVDD) can be applied to the second auxiliary row lines (SRL2). For example, the second auxiliary row lines (SRL2) can be connected to auxiliary column lines (SCL) connected to the second driving voltage supply line (12).

[0213] The first auxiliary column lines (SCL1) may be extended in a second direction (e.g., ±y direction). Each of the first auxiliary column lines (SCL1) may include a plurality of column connection parts separated by second parts (DWLb) of the data connection lines (DWL).

[0214] A driving voltage (ELVDD) may be applied to the first auxiliary heat lines (SCL1). For example, at least one of the heat connections of the first auxiliary heat line (SCL1) may be connected to the second driving voltage supply line (12). The first auxiliary heat lines (SCL1) may be connected to auxiliary row lines (SRL) to which the driving voltage (ELVDD) is applied.

[0215] The second auxiliary heat lines (SCL2) can be extended in a second direction (e.g., ±y direction). A driving voltage (ELVDD) can be applied to the second auxiliary heat lines (SCL2). For example, the second auxiliary heat lines (SCL2) can be connected to a second driving voltage supply line (12) to receive the driving voltage (ELVDD).

[0216] In one embodiment, auxiliary row lines (SRL) and auxiliary column lines (SCL) may be placed on the same layer. The auxiliary row lines (SRL) and auxiliary column lines (SCL) may be a single unit, except for the portion separated by a data connection line (DWL).

[0217] FIG. 10 is an enlarged plan view schematically illustrating a part of FIG. 9.

[0218] First, referring to FIG. 10, the first auxiliary row lines (SRL1) may be extended in a first direction (e.g., ±x direction). Each of the first auxiliary row lines (SRL1) may include a plurality of row connections separated by third parts (DWLc) of data connection lines (DWL).

[0219] In one embodiment, the number of row connections of each of the first auxiliary row lines (SRL1) may increase monotonically along the +y direction. In other words, the number of third parts (DWLc) of data connection lines (DWL) intersecting the first auxiliary row line (SRL1) may increase monotonically along the +y direction.

[0220] For example, a first-1 auxiliary row line (SRL1-1), which is one of the first auxiliary row lines (SRL1), may include a first row connection part (SRL1a) and a second row connection part (SRL1b) separated by a third part (DWLc) of the data connection line (DWL). A first-2 auxiliary row line (SRL1-2), which is another of the first auxiliary row lines (SRL1), may include a first row connection part (SRL1a), a second row connection part (SRL1b), and a third row connection part (SRL1c) separated by third parts (DWLc) of the data connection lines (DWL). Another first-third auxiliary row line (SRL1-3) among the first auxiliary row lines (SRL1) may include a first row connection part (SRL1a), a second row connection part (SRL1b), a third row connection part (SRL1c), and a fourth row connection part (SRL1d) separated by third parts (DWLc) of data connection lines (DWL).

[0221] The first-1 auxiliary row line (SRL1-1) may include two row connections, the first-2 auxiliary row line (SRL1-2) may include three row connections, and the first-3 auxiliary row line (SRL1-3) may include four row connections. In other words, the first-1 auxiliary row line (SRL1-1) may intersect with the third part (DWLc) of one data connection line (DWL), the first-2 auxiliary row line (SRL1-2) may intersect with the third parts (DWLc) of two data connection lines (DWL), and the first-3 auxiliary row line (SRL1-3) may intersect with the third parts (DWLc) of three data connection lines (DWL). At this time, the 1-2 auxiliary row line (SRL1-2) may be located in the +y direction relative to the 1-1 auxiliary row line (SRL1-1), and the 1-3 auxiliary row line (SRL1-3) may be located in the +y direction relative to the 1-2 auxiliary row line (SRL1-2).

[0222] Some of the row connecting parts of the first auxiliary row line (SRL1) may be connected to the first auxiliary column line (SCL1), and others may be connected to the second auxiliary column line (SCL2). For example, as shown in FIG. 10, the second row connecting part (SRL1b), the third row connecting part (SRL1c), and the fourth row connecting part (SRL1d) may be connected to the first column connecting part (SCL1a) of the first auxiliary column line (SCL1), and the first row connecting part (SRL1a) may be connected to the second auxiliary column line (SCL2).

[0223] The second auxiliary row lines (SRL2) may be extended in the first direction (e.g., ±x direction). The second auxiliary row lines (SRL2) may be connected to the second column connections (SCL1b) of the first auxiliary column lines (SCL1) and to the second auxiliary column lines (SCL2).

[0224] The first auxiliary column lines (SCL1) may be extended in a second direction (e.g., ±y direction). Each of the first auxiliary column lines (SCL1) may include a plurality of column connections separated by second portions (DWLb) of the data connection lines (DWL). For example, each of the first auxiliary column lines (SCL1) may include a first column connection (SCL1a) and a second column connection (SCL1b) separated by second portions (DWLb) of the data connection lines (DWL). As described above in FIG. 9, the first column connections (SCL1a) of the first auxiliary column lines (SCL1) may be connected to a second driving voltage supply line (12) to receive a driving voltage (ELVDD).

[0225] In FIG. 10, the number of column connections of each of the first auxiliary column lines (SCL1) is shown as constant, but in other embodiments, the number of column connections of each of the first auxiliary column lines (SCL1) may differ from one another. For example, as with the first auxiliary row lines (SRL1), the number of column connections of each of the first auxiliary column lines (SCL1) may increase monotonically along the +x direction.

[0226] The second auxiliary heat lines (SCL2) can be extended in a second direction (e.g., ±y direction). As described above in FIG. 9, the second auxiliary heat lines (SCL2) can be connected to the second driving voltage supply line (12) to receive the driving voltage (ELVDD).

[0227] In one embodiment, auxiliary row lines (SRL) and auxiliary column lines (SCL) may be arranged on the same layer. Auxiliary row lines (SRL) and auxiliary column lines (SCL) may be integral, except for the portion separated by a data connection line (DWL). For example, as shown in FIG. 10, the first row connection portions (SRL1a) of the first auxiliary row lines (SRL1), the second auxiliary row lines (SRL2), the second column connection portions (SCL1b) of the first auxiliary column lines (SCL1), and the second auxiliary column lines (SCL2) may be integral. The first column connection portions (SCL1a) of the first auxiliary column lines (SCL1) and the remaining row connection portions of the first auxiliary row lines (SRL1) may each be integral.

[0228] In one embodiment, the first auxiliary row lines (SRL1) and the second auxiliary row lines (SRL2) are arranged for each pixel circuit row, and the first auxiliary column lines (SCL1) and the second auxiliary column lines (SCL2) are arranged for each pixel circuit column.

[0229] In one embodiment, as illustrated in FIG. 10, the second portions (DWLb) of the data connection lines (DWL) may be arranged for each row of the pixel circuit, and the third portions (DWLc) may be arranged for each pair of pixel circuit columns. When the third portions (DWLc) of the data connection lines (DWL) are arranged for each pair of pixel circuit columns, the third portions (DWLc) of the data connection lines (DWL) may be placed at the boundaries of adjacent pixel circuits, thereby minimizing the area of ​​overlap with the elements (e.g., transistors) within the pixel circuit. Thus, it is possible to prevent interference with the elements within the pixel circuit by the third portions (DWLc) of the data connection lines (DWL) to which various levels of data voltages are applied.

[0230] In FIG. 10, the third portion (DWLc) of the data connection lines (DWL) is shown as being arranged in each pair of pixel circuit rows, but in another embodiment, the third portion (DWLc) of the data connection lines (DWL) may be arranged in each pixel circuit row. This will be described later in FIG. 13.

[0231] FIG. 11 is an enlarged plan view schematically illustrating a portion of FIG. 9. FIG. 11 is a modified embodiment of FIG. 10, differing in the structure of the data connection lines. In the following, redundant content will be replaced by the description of FIG. 10, and the differences will be explained primarily.

[0232] Referring to FIG. 11, the display panel may include a plurality of initialization voltage lines (VL) extending in a first direction (e.g., ±x direction). The initialization voltage lines (VL) may be arranged for each row of pixel circuits.

[0233] The initialization voltage line (VL) is connected to the first pixel circuits (PC1) located in the same row among the plurality of first pixel circuits (PC1) and can transmit an initialization voltage (VINT, see FIG. 8).

[0234] In one embodiment, as shown in FIG. 11, the second part (DWLb) of the data connection line (DWL) and the initialization voltage line (VL) may overlap at least partially with each other. Since the second part (DWLb) of the data connection lines (DWL) each overlap at least partially with the initialization voltage line (VL) to which the initialization voltage (VINT), which is a constant voltage, is applied, it is possible to prevent the elements within the pixel circuit from being interfered with by the second part (DWLb) of the data connection lines (DWL) to which various data voltages are applied.

[0235] FIG. 12 is an exemplary cross-sectional view of the pixel circuit of FIG. 11 cut along IV-IV' and V-V'.

[0236] Referring to FIG. 12, the first pixel circuit (PC1) may include a first transistor (TFT1) and a second transistor (TFT2). The first transistor (TFT1) may include a first semiconductor layer (Act1) and a first gate electrode (GE1), and the second transistor (TFT2) may include a second semiconductor layer (Act) and a second gate electrode (GE2). The second gate electrode (GE2) may include a lower gate electrode (GE2a) and an upper gate electrode (GE2b). The first transistor (TFT1) corresponds to the driving transistor (T1) of FIG. 8, and the second transistor (TFT2) may correspond to the compensation transistor (T3) or the gate initialization transistor (T4) of FIG. 8.

[0237] Between the substrate (100) and the buffer layer (111), a first column connection part (SCL1a) of the first auxiliary column line (SCL1), a second row connection part (SRL1b) of the first auxiliary row line (SRL1), and a second part (DWLb) of the data connection line (DWL) may be arranged. The first column connection part (SCL1a) of the first auxiliary column line (SCL1) and the second row connection part (SRL1b) of the first auxiliary row line (SRL1) may be integral.

[0238] Meanwhile, FIG. 12 illustrates the first column connection part (SCL1a) of the first auxiliary column line (SCL1), the second row connection part (SRL1b) of the first auxiliary row line (SRL1), and the second part (DWLb) of the data connection line (DWL), and can be understood as being extended so that the first auxiliary column line (SCL1), the first auxiliary row line (SRL1), and the data connection line (DWL) are placed between the substrate (100) and the buffer layer (111).

[0239] A first semiconductor layer (Act1) may be disposed on the buffer layer (111). The first semiconductor layer (Act1) may include amorphous silicon or polysilicon.

[0240] In one embodiment, as shown in FIG. 12, the first column connection portion (SCL1a) of the first auxiliary column line (SCL1) and the second row connection portion (SRL1b) of the first auxiliary row line (SRL1) may overlap at least partially with the first semiconductor layer (Act1). The first column connection portion (SCL1a) of the first auxiliary column line (SCL1) and the second row connection portion (SRL1b) of the first auxiliary row line (SRL1) may serve to prevent the characteristics of the first semiconductor layer (Act1) from changing due to external light penetrating the substrate (100).

[0241] A first gate insulating layer (113) is disposed on the first semiconductor layer (Act1), and a first gate electrode (GE1) can be disposed on the first gate insulating layer (113) so as to overlap at least partially with the first semiconductor layer (Act1).

[0242] A second gate insulating layer (115) may be disposed on the first gate electrode (GE1), and a second electrode (CE2), a lower gate electrode (GE2a), and an initial voltage line (VL) of a storage capacitor (Cst) may be disposed on the second gate insulating layer (115). The second electrode (CE2), the lower gate electrode (GE2a), and the initial voltage line (VL) of the storage capacitor (Cst) may be composed of molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may be made of a single layer or multiple layers. As an example, the second electrode (CE2), the lower gate electrode (GE2a), and the initial voltage line (VL) of the storage capacitor (Cst) may be a single layer of Mo.

[0243] In one embodiment, the initialization voltage line (VL) may overlap with the second part (DWLb) of the data connection line (DWL). Since the second part (DWLb) of the data connection line (DWL) overlaps with the initialization voltage line (VL) to which a constant voltage is applied, it is possible to prevent the elements within the pixel circuit from being interfered with by the second part (DWLb) of the data connection line (DWL), to which various levels of data voltages are applied.

[0244] The interlayer insulating layer (117) may include a first interlayer insulating layer (117a) and a second interlayer insulating layer (117b). The first interlayer insulating layer (117a) is disposed on the second electrode (CE2), the lower gate electrode (GE2a), and the initialization voltage line (VL) of the storage capacitor (Cst), and the second interlayer insulating layer (117b) may be disposed on the first interlayer insulating layer (117a).

[0245] A second semiconductor layer (Act2) may be disposed on the first interlayer insulating layer (117a). The second semiconductor layer (Act2) may include an oxide of at least one material selected from the group comprising indium (In), gallium (Ga), stanium (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), aluminum (Al), cesium (Cs), cerium (Ce), and zinc (Zn).

[0246] In one embodiment, as shown in FIG. 12, the lower gate electrode (GE2a) may overlap at least partially with the second semiconductor layer (Act2). The lower gate electrode (GE2a) may serve to prevent the characteristics of the second semiconductor layer (Act2) from changing due to external light penetrating the substrate (100).

[0247] A third gate insulating layer (116) may be disposed on the second semiconductor layer (Act2). The third gate insulating layer (116) may be silicon oxide (SiO2) or silicon nitride (SiN x It may include silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO2), etc.

[0248] In one embodiment, the third gate insulating layer (116) may be patterned to overlap a portion of the second semiconductor layer (Act2). In another embodiment, the third gate insulating layer (116) may be placed on the upper surface of the substrate (100) so as not to be patterned and to cover the second semiconductor layer (Act2).

[0249] An upper gate electrode (GE2b) may be disposed on the third gate insulating layer (116). The upper gate electrode (GE2b) may be composed of molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may be a single layer or a multilayer. As an example, the upper gate electrode (GE2b) may be a single layer of Mo.

[0250] FIG. 13 is an enlarged plan view schematically illustrating a portion of FIG. 9. FIG. 13 is a modified embodiment of FIG. 10, differing in the structure of the data connection lines. Below, redundant content will be replaced by the description of FIG. 10, and the explanation will focus on the differences.

[0251] Referring to FIG. 13, the first auxiliary row lines (SRL1) and the second auxiliary row lines (SRL2) may be arranged for each row of the pixel circuit, and the first auxiliary column lines (SCL1) and the second auxiliary column lines (SCL2) may be arranged for each column of the pixel circuit. Additionally, the second portion (DWLb) of the data connection lines (DWL) may be arranged for each row of the pixel circuit, and the third portion (DWLc) of the data connection lines (DWL) may be arranged for each column of the pixel circuit.

[0252] The first auxiliary row lines (SRL1) may be extended in a first direction (e.g., ±x direction). Each of the first auxiliary row lines (SRL1) may include a plurality of row connection portions separated by third portions (DWLc) of the data connection lines (DWL). For example, each of the first auxiliary row lines (SRL1) may include a first row connection portion (SRL1a) and a second row connection portion (SRL1b) separated by third portions (DWLc) of the data connection lines (DWL).

[0253] The first auxiliary column lines (SCL1) may be extended in a second direction (e.g., ±y direction). Each of the first auxiliary column lines (SCL1) may include a plurality of column connections separated by second portions (DWLb) of the data connection lines (DWL). For example, each of the first auxiliary column lines (SCL1) may include a first column connection (SCL1a) and a second column connection (SCL1b) separated by second portions (DWLb) of the data connection lines (DWL).

[0254] Although the present invention has primarily described display devices so far, it is not limited thereto. For example, a method for manufacturing such a display device is also considered to fall within the scope of the present invention.

[0255] The present invention has been described with reference to the embodiments illustrated in the drawings, but this is merely illustrative, and those skilled in the art will understand that various modifications and equivalent alternative embodiments are possible therefrom. Accordingly, the true technical scope of protection of the present invention should be determined by the technical spirit of the appended claims. Explanation of the symbols

[0256] 1: Display device 10: Display panel 100: Substrate PX: Pixel PC: Pixel circuit DE: Display element Act: Semiconductor layer DL1, DL2: First data line and second data line DWL: Data connection line

Claims

Claim 1 A display device comprising: a substrate having a display area and a peripheral area outside the display area defined therein; a semiconductor layer disposed on the substrate; a first pixel circuit disposed on the display area; a first data line disposed on the display area and connected to the first pixel circuit; a second pixel circuit disposed on the peripheral area; a second data line disposed on the peripheral area and connected to the second pixel circuit; and a data connection line interposed between the substrate and the semiconductor layer and connecting the first data line to the second data line. Claim 2 A display device according to claim 1, wherein the display area includes a component area and a main area surrounding at least a portion of the component area, the transmittance of the component area is higher than the transmittance of the main area, and the data connection line overlaps at least a portion with the component area. Claim 3 A display device according to claim 2, further comprising a camera disposed below the component area, wherein the component area includes a central area corresponding to the lens of the camera and an edge area surrounding the central area, and the data connection line overlaps at least partially with the edge area of ​​the component area. Claim 4 In claim 2, the data connection line has a first part overlapping with the component area, a second part connected to the first part and extending in a first direction, and a third part connected to the second part and extending in a second direction, and the second part and the third part of the data connection line overlap at least partially with the main area. Claim 5 A display device according to claim 4, further comprising a voltage line disposed on the semiconductor layer and extending in the first direction and connected to the first pixel circuit, wherein the second portion of the data connection line and the voltage line overlap at least partially with each other. Claim 6 A display device according to claim 5, further comprising a first display element disposed on the display area and connected to the first pixel circuit, wherein the first pixel circuit comprises: a driving transistor that controls the current flowing to the first display element; and an initialization transistor that is connected to the voltage line and applies an initialization voltage transmitted from the voltage line to the gate of the driving transistor in response to a scan signal. Claim 7 A display device according to claim 6, wherein each of the driving transistor and the initialization transistor is one of an NMOS (n-channel MOSFET) and a PMOS (p-channel MOSFET). Claim 8 A display device according to claim 4, wherein the first pixel circuit and the data connection line are provided in plurality, the plurality of first pixel circuits are arranged in a matrix, the second portions of the plurality of data connection lines are arranged in each row of the pixel circuit, and the third portions of the plurality of data connection lines are arranged in each column of the pixel circuit or each pair of columns of the pixel circuit. Claim 9 A display device according to claim 4, further comprising: an auxiliary row line extending in the first direction and having a first row connecting portion and a second row connecting portion spaced apart from each other by the third portion of the data connecting line; and an auxiliary column line extending in the second direction and having a first column connecting portion and a second column connecting portion spaced apart from each other by the second portion of the data connecting line. Claim 10 In claim 9, a display device in which the same level of driving voltage is applied to the auxiliary row line and the auxiliary column line. Claim 11 A display device according to claim 1, further comprising: a first display element disposed on the display area and connected to the first pixel circuit; and a second display element disposed on the display area and connected to the second pixel circuit, wherein the light-emitting area of ​​the second display element is larger than the light-emitting area of ​​the first display element. Claim 12 A display device according to claim 11, further comprising: a third pixel circuit disposed on the display area; and a third display element disposed on the display area and connected to the third pixel circuit, wherein the display area comprises a component area including a first area and a second area adjacent to each other, and a main area surrounding a portion of the component area, wherein the first pixel circuit and the first display element are disposed in the main area and overlap each other at least partially, the second display element is disposed in the first area of ​​the component area, the third pixel circuit and the third display element are disposed in the second area of ​​the component area and overlap each other at least partially, and the light-emitting area of ​​the third display element is larger than the light-emitting area of ​​the first display element. Claim 13 A display device according to claim 12, wherein the first display element, the second display element, and the third display element are provided in plurality, the number of the plurality of first display elements per unit area is greater than the number of the plurality of second display elements per unit area, and the number of the plurality of second display elements per unit area is equal to the number of the plurality of third display elements per unit area. Claim 14 A display device comprising: a component area, a display area including a main area surrounding at least a portion of the component area, and a peripheral area defined outside the display area; a plurality of first pixel circuits disposed on the main area; a plurality of first display elements disposed on the main area and connected to the plurality of first pixel circuits; a plurality of first data lines disposed on the main area and connected to the plurality of first pixel circuits; a plurality of second pixel circuits disposed on the peripheral area; a plurality of second display elements disposed on the component area and connected to the plurality of second pixel circuits; a plurality of second data lines disposed on the peripheral area and connected to the plurality of second pixel circuits; and a plurality of data connection lines that overlap at least partially with the component area and connect the plurality of first data lines to the plurality of second data lines, wherein the number of the plurality of first display elements per unit area is greater than the number of the plurality of second display elements per unit area. Claim 15 A display device according to claim 14, further comprising a camera disposed below the component area, wherein the component area includes a central area corresponding to the lens of the camera and an edge area surrounding the central area, and wherein the plurality of data connection lines overlap at least partially with the edge area of ​​the component area. Claim 16 In claim 14, each of the plurality of data connection lines has a first part that overlaps with the component area, a second part that is connected to the first part and extends in a first direction, and a third part that is connected to the second part and extends in a second direction, and the second part and the third part of each of the plurality of data connection lines overlap at least partially with the main area. Claim 17 A display device according to claim 16, further comprising a plurality of voltage lines disposed on the main area and each extending in the first direction and connected to first pixel circuits located in the same row among the plurality of first pixel circuits, wherein the second portions of the plurality of data connection lines and the plurality of voltage lines each overlap at least partially with one another. Claim 18 A display device according to claim 17, wherein each of the plurality of first pixel circuits comprises: a driving transistor that controls a current flowing to a corresponding first display element among the plurality of first display elements; and an initialization transistor that applies an initialization voltage transmitted from a corresponding voltage line among the plurality of voltage lines to the gate of the driving transistor in response to a scan signal. Claim 19 A display device according to claim 16, wherein the second portions of the plurality of data connection lines are arranged in each pixel circuit row, and the third portions of the plurality of data connection lines are arranged in each pixel circuit column or each pair of pixel circuit columns. Claim 20 A display device according to claim 16, further comprising: a plurality of auxiliary row lines, each having a plurality of row connection portions extended in the first direction and spaced apart by the third portions of the plurality of data connection lines; and a plurality of auxiliary column lines, each having a plurality of column connection portions extended in the second direction and spaced apart by the second portions of the plurality of data connection lines, wherein the same level of driving voltage is applied to the plurality of auxiliary row lines and the plurality of auxiliary column lines. Claim 21 In claim 20, a display device in which the number of the plurality of row connecting parts of each of the plurality of auxiliary row lines increases monotonically along the second direction.

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