Input sensing panel and display apparatus including the same

Abstract

A display device comprises a display panel including a pixel that provides light, and an input sensing panel that detects an external input, wherein the input sensing panel comprises a first sensing insulating layer disposed on the display panel, first conductive patterns disposed on the first sensing insulating layer, a second sensing insulating layer covering the first conductive patterns, second conductive patterns disposed on the second sensing insulating layer, a piezoelectric pattern covering the second conductive patterns, a light-blocking pattern covering the piezoelectric pattern and defining a transmission opening that transmits the light, and a third sensing insulating layer covering the light-blocking pattern.

Description

Technology Field

[0001] The present invention relates to a display device including an input sensing panel capable of adjusting the area of ​​a light-emitting region. Background Technology

[0002] The display device may include a display panel for displaying images and an input detection panel for detecting external inputs. The input detection panel may be formed integrally with the display panel through a continuous process. Alternatively, the input detection panel may be formed through a separate process from the display panel and then coupled to the display panel. The problem to be solved

[0003] The present invention aims to provide a display device capable of enhancing privacy protection according to user needs by reducing the viewing angle through adjusting the area of ​​the light-emitting region. means of solving the problem

[0004] A display device according to the present invention comprises a display panel including a pixel that provides light, and an input sensing panel that detects an external input, wherein the input sensing panel comprises a first sensing insulating layer disposed on the display panel, first conductive patterns disposed on the first sensing insulating layer, a second sensing insulating layer disposed on the first sensing insulating layer and covering the first conductive patterns, second conductive patterns disposed on the second sensing insulating layer, a piezoelectric pattern covering the second conductive patterns, a light-blocking pattern covering the piezoelectric pattern and defining a transmission opening that transmits the light, and a third sensing insulating layer disposed on the second sensing insulating layer and covering the light-blocking pattern.

[0005] The above-mentioned transparent opening may be characterized by having a first width in one direction in a first mode, and having a second width smaller than the first width in one direction in a second mode in which a voltage different from that of the first mode is applied.

[0006] The above display panel may be characterized by comprising a base layer, a circuit element layer including a transistor disposed on the base layer, a first electrode connected to the transistor, a second electrode disposed on the first electrode, a light-emitting layer disposed between the first electrode and the second electrode, a pixel defining film having a display opening defined that exposes at least a portion of the first electrode, and an encapsulation layer covering the display element layer, wherein the first sensing insulating layer is directly disposed on the encapsulation layer.

[0007] The above piezoelectric pattern may be characterized by having a relatively larger volume in the second mode than in the first mode.

[0008] The side of the above-mentioned light-blocking pattern defines the boundary of the light-emitting area, and the light-emitting area may be characterized by having a narrower area in the second mode than in the first mode.

[0009] During the transition from the first mode to the second mode, the light-blocking pattern protrudes in a direction toward the light-emitting area, and the width of the light-blocking pattern protruding during the transition from the first mode to the second mode may be 2 micrometers or more and 5 micrometers or less.

[0010] The above light-blocking pattern may be characterized by including a light-absorbing material.

[0011] It may further include a color filter layer disposed on the input detection panel and overlapping with the light-emitting region, and a window disposed on the color filter layer.

[0012] The input sensing panel may further include a cover layer disposed on the third sensing insulating layer, wherein the third sensing insulating layer exposes at least a portion of the second sensing insulating layer and defines a cover opening that overlaps with at least a portion of the light-emitting region, and the cover layer may be characterized by contacting the second sensing insulating layer in the region that overlaps with the cover opening.

[0013] The above second challenge patterns may be characterized by including a plurality of mesh lines.

[0014] A display device according to the present invention comprises a display panel including a pixel that provides light, and an input sensing panel that detects an external input, wherein the input sensing panel comprises a plurality of sensing insulating layers, conductive patterns disposed between the sensing insulating layers, a piezoelectric pattern covering at least a portion of the conductive patterns, and a light-blocking pattern covering the piezoelectric pattern and defining a transmitting opening that transmits the light, wherein the transmitting opening has a first width in one direction in a first mode and a second width smaller than the first width in one direction in a second mode that is subjected to a voltage different from the first mode.

[0015] The above display panel may include a base layer, a circuit element layer comprising a transistor disposed on the base layer, a first electrode connected to the transistor, a second electrode disposed on the first electrode, a light-emitting layer disposed between the first electrode and the second electrode, a display element layer comprising a pixel defining film having a display opening defined that exposes at least a portion of the first electrode, and an encapsulation layer covering the display element layer, wherein the sensing insulating layer disposed closest to the display panel among the sensing insulating layers may be characterized by being directly disposed on the encapsulation layer.

[0016] The above piezoelectric pattern may be characterized by having a relatively larger volume in the second mode than in the first mode.

[0017] The side of the above-mentioned light-blocking pattern defines the boundary of the light-emitting area, and the light-emitting area may be characterized by having a narrower area in the second mode than in the first mode.

[0018] During the transition from the first mode to the second mode, the light-blocking pattern protrudes in a direction toward the light-emitting area, and the width of the light-blocking pattern protruding during the transition from the first mode to the second mode may be 2 micrometers or more and 5 micrometers or less.

[0019] It may further include a color filter layer disposed on the input detection panel and overlapping with the light-emitting region, and a window disposed on the color filter layer.

[0020] The input sensing panel may further include a cover layer covering at least a portion of the sensing insulating layers, and the sensing insulating layer located at the top of the sensing insulating layers may be characterized by being configured in a trapezoidal shape in cross-section and defining a cover opening that overlaps with at least a portion of the light-emitting region.

[0021] An input sensing panel according to the present invention comprises a first sensing insulating layer, first conductive patterns disposed on the first sensing insulating layer, a second sensing insulating layer disposed on the first sensing insulating layer and covering the first conductive patterns, second conductive patterns disposed on the second sensing insulating layer, a piezoelectric pattern covering the second conductive patterns, a light-blocking pattern covering the piezoelectric pattern and defining a transparent opening that exposes at least a portion of the second sensing insulating layer, and a third sensing insulating layer disposed on the second sensing insulating layer and covering the light-blocking pattern.

[0022] The above-mentioned transparent opening may be characterized by having a first width in one direction in a first mode, and having a second width smaller than the first width in one direction in a second mode in which a voltage different from that of the first mode is applied.

[0023] The above piezoelectric pattern may be characterized by having a variable volume when converting from the first mode to the second mode. Effects of the invention

[0024] According to the present invention, the volume of the piezoelectric pattern and the light-blocking pattern included in the input sensing panel can be varied. At this time, the viewing angle of the electronic device may be reduced or increased. By reducing the viewing angle as necessary, the viewing angle of a third party looking from the side is blocked, thereby providing a display device with enhanced privacy protection. Brief explanation of the drawing

[0025] FIG. 1a is a combined perspective view of a display device according to one embodiment of the present invention. FIG. 1b is an exploded perspective view of a display device according to one embodiment of the present invention. FIG. 2a is a cross-sectional view of a display module according to one embodiment of the present invention. Figure 2b is an enlarged view of a portion of the display module shown in Figure 2a. FIG. 3 is a plan view of a display panel according to one embodiment of the present invention. FIG. 4a is an equivalent circuit diagram of a pixel according to one embodiment of the present invention. FIG. 4b is a cross-sectional view of a pixel according to one embodiment of the present invention. FIG. 5a is a plan view of an input detection panel according to one embodiment of the present invention. FIG. 5b is a plan view showing an enlarged view of the PP' area illustrated in FIG. 5a. FIG. 5c is a plan view illustrating the arrangement relationship between the light-emitting region, the conductive pattern, and the cover layer in the QQ' region shown in FIG. 5a. FIG. 6a is a cross-sectional view of a display device cut along I-I' of FIG. 5b when in the first mode. FIG. 6b is a cross-sectional view of a display device cut along I-I' of FIG. 5b when in the second mode. FIG. 7a is a cross-sectional view of the display device in the first mode. FIG. 7b is a cross-sectional view of the display device in the second mode. Specific details for implementing the invention

[0026] In this specification, where a component (or region, layer, part, etc.) is described as being "on," "connected," or "combined" with another component, it means that it may be directly placed / connected / combined with the other component, or that a third component may be placed between them.

[0027] Identical reference numerals denote identical components. Additionally, in the drawings, the thicknesses, proportions, and dimensions of the components are exaggerated for the effective illustration of the technical content. "And / or" includes all one or more combinations that the associated components may define.

[0028] Terms such as "first," "second," etc., may be used to describe various components, but said components should not be limited by said terms. These terms are used solely for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be named the second component, and similarly, the second component may be named the first component. A singular expression includes a plural expression unless the context clearly indicates otherwise.

[0029] Additionally, terms such as "below," "lower side," "above," and "upper side" are used to describe the relationships between the components depicted in the drawings. These terms are relative concepts and are described based on the directions indicated in the drawings.

[0030] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as generally understood by those skilled in the art to which the present invention pertains. Furthermore, terms such as those defined in commonly used dictionaries should be interpreted as having a dictionary meaning consistent with their meaning in the context of the relevant technology, and should not be interpreted in an overly ideal or overly formal sense unless explicitly defined herein.

[0031] Terms such as "include" or "have" are intended to specify the existence of the features, numbers, steps, actions, components, parts, or combinations thereof described in the specification, and should be understood as not precluding the existence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof. Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[0033] FIG. 1a is an assembled perspective view of a display device according to one embodiment of the present invention. FIG. 1b is an exploded perspective view of a display device according to one embodiment of the present invention.

[0034] Referring to FIGS. 1a and 1b, the display device (EA) may be a device that is activated according to an electrical signal. The display device (EA) may include various embodiments. For example, the display device (EA) may include a tablet, a laptop, a computer, a smart television, etc. In this embodiment, the display device (EA) is illustrated as a smartphone.

[0035] A display device (EA) can provide an image (IM) toward a third direction (DR3) on a display surface (IS) parallel to each of the first direction (DR1) and the second direction (DR2). The display surface (IS) on which the image (IM) is displayed may correspond to the front surface of the display device (EA). The image (IM) may include a still image as well as a dynamic image. In FIG. 1a, a clock window and icons are shown as examples of the image (IM).

[0036] In this embodiment, the front (or front) and back (or bottom) sides of each component are defined based on the direction in which the image (IM) is displayed. The front and back sides are opposed to each other in a third direction (DR3), and the normal direction of each of the front and back sides may be parallel to the third direction (DR3).

[0037] The separation distance in the third direction (DR3) between the front and back surfaces may correspond to the thickness / height in the third direction (DR3) of the display device (EA). Meanwhile, the directions indicated by the first to third directions (DR1, DR2, DR3) are relative concepts and can be converted to other directions.

[0038] The front surface of the display device (EA) may be divided into a transparent area (TA) and a bezel area (BZA). The transparent area (TA) may be an area where an image (IM) is displayed. The user perceives the image (IM) through the transparent area (TA). In this embodiment, the transparent area (TA) is depicted as a square shape with rounded vertices. However, this is illustrated as an example, and the transparent area (TA) may have various shapes and is not limited to any single embodiment.

[0039] The bezel area (BZA) is adjacent to the transparent area (TA). The bezel area (BZA) may have a predetermined color. The bezel area (BZA) may surround the transparent area (TA). Accordingly, the shape of the transparent area (TA) may be substantially defined by the bezel area (BZA). However, this is illustrated as an example, and the bezel area (BZA) may be positioned adjacent to only one side of the transparent area (TA) or may be omitted. A display device according to one embodiment of the present invention may include various embodiments and is not limited to any one embodiment.

[0040] A display device (EA) can detect an external input (TC) applied from the outside. The external input (TC) may include various forms of input provided from outside the display device (EA). For example, the external input (TC) may include contact by a part of the body, such as a user's hand, as well as external inputs applied while in close proximity to the display device (EA) or at a predetermined distance (e.g., hovering). Additionally, it may take various forms such as force, pressure, light, etc., and is not limited to any one embodiment. FIG. 1a shows a user's hand as an example of an external input (TC).

[0041] Referring to FIG. 1b, the display device (EA) may include a window member (WM), an outer case (EDC), a display module (DM), a main circuit board (MF), and flexible circuit boards (FF, TF). The display module (DM) may include a display panel (DP) and an input sensing panel (ISP).

[0042] The window member (WM) is placed on the display module (DM). The window member (WM) protects the display module (DM) by preventing external impact and preventing the intrusion of foreign substances.

[0043] The window member (WM) may be made of a transparent material capable of emitting an image. For example, it may be composed of glass, sapphire, plastic, etc. Although the window member (WM) is depicted as a single layer, it is not limited thereto and may include multiple layers. Meanwhile, although not depicted, the bezel area (BZA) of the display device (EA) described above may substantially be provided as an area in which a material containing a predetermined color is printed on a part of the window member (WM).

[0044] The outer case (EDC) accommodates the display module (DM). The outer case (EDC) can be combined with a window member (WM) to define the appearance of the display device (EA). The outer case (EDC) absorbs external shocks and protects the components housed within the outer case (EDC) by preventing foreign substances / moisture from penetrating the display module (DM). Meanwhile, although not illustrated, the outer case (EDC) may be provided in a form in which multiple housing members are combined.

[0046] FIG. 2a is a cross-sectional view of a display module according to an embodiment of the present invention. FIG. 2b is an enlarged view of a portion of the display module shown in FIG. 2a.

[0047] Referring to FIGS. 2a and 2b, a display module (DM) according to the present invention includes a display panel (DP) and an input sensing panel (ISP) disposed on the display panel (DP). The display module (DM) can display an image according to an electrical signal and transmit / receive information regarding an external input (TC).

[0048] The display module (DM) may be defined as an active area (AA) and an inactive area (NAA). The active area (AA) is defined as an area that emits an image provided by the display module (DM), and the inactive area (NAA) may be an area surrounding the active area (AA). However, this is illustrated as an example, and the inactive area (NAA) may be defined in various shapes and is not limited to any one embodiment. The active area (AA) of the display module (DM) may correspond to a transmission area (TA).

[0049] The display panel (DP) includes a base substrate (SUB), a circuit element layer (CL), a display element layer (PE), and an encapsulation layer (TFE).

[0050] The base substrate (SUB) may be a flexible substrate or a rigid substrate. The base substrate (SUB) may be a base layer on which components included in the circuit element layer (CL) are placed.

[0051] The circuit element layer (CL) is disposed on the base substrate (SUB). The circuit element layer (CL) may include multiple transistors including unillustrated signal lines, a control circuit, and a semiconductor layer.

[0052] The display element layer (PE) may include an organic light-emitting diode and a pixel definition film. The encapsulation layer (TFE) seals the display element layer (PE). The encapsulation layer (TFE) according to one embodiment of the present invention may include at least one organic film and at least one inorganic film.

[0053] The input sensing panel (ISP) according to the present invention is placed directly on a display panel (DP). In this specification, "the configuration of B1 is placed directly on the configuration of A1" means that no separate adhesive member is placed between the configuration of A1 and the configuration of B1. The configuration of B1 is formed through a continuous process on the base surface provided by the configuration of A1 after the configuration of A1 is formed.

[0054] As illustrated in FIG. 2b, the encapsulation layer (TFE) according to the present invention may include a first encapsulation inorganic layer (LIL), an organic layer (OEL), and a second encapsulation inorganic layer (UIL).

[0055] The first encapsulating inorganic layer (LIL) can cover the display element layer (PE). The first encapsulating inorganic layer (LIL) can prevent external moisture or oxygen from penetrating into the organic light-emitting diode (OLED). For example, the first encapsulating inorganic layer (LIL) may include silicon nitride, silicon oxide, or a compound combining these. The first encapsulating inorganic layer (LIL) can be formed through a chemical vapor deposition process.

[0056] An organic layer (OEL) may be disposed on a first encapsulating inorganic layer (LIL) and connected to the first encapsulating inorganic layer (LIL). The organic layer (OEL) may provide a flat surface on the first encapsulating inorganic layer (LIL). Curvatures formed on the upper surface of the first encapsulating inorganic layer (LIL) or particles present on the first encapsulating inorganic layer (LIL) may be covered by the organic layer (OEL), thereby blocking the influence of the surface condition of the upper surface of the first encapsulating inorganic layer (LIL) on the components formed on the organic layer (OEL). Additionally, the organic layer (OEL) may relieve stress between contacting layers. The organic layer (OEL) may contain organic material and may be formed through solution processes such as spin coating, slit coating, or inkjet processes.

[0057] The second encapsulating inorganic layer (UIL) is placed on the organic layer (OEL) to cover the organic layer (OEL). The second encapsulating inorganic layer (UIL) can be stably formed on a relatively flat surface compared to the one placed on the first encapsulating inorganic layer (LIL). The second encapsulating inorganic layer (UIL) encapsulates moisture, etc. released from the organic layer (OEL) to prevent it from entering to the outside. The second encapsulating inorganic layer (UIL) may include silicon nitride, silicon oxide, or a compound combining these. The second encapsulating inorganic layer (UIL) can be formed through a chemical vapor deposition process.

[0058] The input sensing panel (ISP) is placed on the encapsulation layer (TFE). The input sensing panel (ISP) can be placed directly on the encapsulation layer (TFE) and formed through a continuous process with the encapsulation layer (TFE). The input sensing panel (ISP) can detect external input by either a self-capacitance type or a mutual capacitance type. The conductive patterns included in the input sensing panel (ISP) can be varied, placed, and connected in accordance with the method.

[0059] The input sensing panel (ISP) may include sensing insulating layers (TIL1, TIL2, TIL3), conductive patterns (TML1, TML2), and a functional layer (FL). The sensing insulating layers (TIL1, TIL2, TIL3) may include a first sensing insulating layer (TIL1), a second sensing insulating layer (TIL2), and a third sensing insulating layer (TIL3) comprising either an inorganic or an organic material. The functional layer (FL) may include a piezoelectric pattern and a light-blocking pattern.

[0060] According to the present invention, a first sensing insulating layer (TIL1) may be directly disposed on a second encapsulating inorganic layer (UIL) among the encapsulating layers (TFE). A first conductive layer (TML1) is disposed on the first sensing insulating layer (TIL1). A second sensing insulating layer (TIL2) is disposed on the first sensing insulating layer (TIL1) and may cover the first conductive layer (TML1). A second conductive layer (TML2) is disposed on the second sensing insulating layer (TIL2). A functional layer (FL) is disposed on the second sensing insulating layer (TIL2) and may cover the second conductive layer (TML2). A third sensing insulating layer (TIL3) is disposed on the second sensing insulating layer (TIL2) and may cover the functional layer (FL).

[0061] The functional layer (FL) includes a piezoelectric material and its volume can be varied by the voltage applied to the second conductive layer (TML2). Accordingly, the area of ​​the light-emitting region can be adjusted to change the viewing angle according to the user's purpose. A detailed description of the functional layer (FL) will be provided later in FIGS. 5C, FIGS. 7A, and FIGS. 7B.

[0062] The conductive layers (TML1, TML2) according to one embodiment may include either a metal with a single-layer structure or a transparent conductive material. For example, the metal may include molybdenum, silver, titanium, copper, aluminum, and alloys thereof.

[0063] Transparent conductive materials may include transparent conductive oxides such as ITO (indium tin oxide), IZO (indium zinc oxide), ZnO (zinc oxide), ITZO (indium tin zinc oxide), etc. Other transparent conductive materials may include conductive polymers such as PEDOT, metal nanowires, graphene, etc.

[0064] The conductive layers (TML1, TML2) may include metal layers with a multilayer structure. The metal layers with a multilayer structure may have, for example, a three-layer structure of titanium / aluminum / titanium. The conductive layers with a multilayer structure (TML1, TML2) may include at least one metal layer and at least one transparent conductive layer.

[0066] FIG. 3 is a plan view of a display panel according to an embodiment of the present invention. FIG. 4a is an equivalent circuit diagram of a pixel according to an embodiment of the present invention. FIG. 4b is a cross-sectional view of a pixel according to an embodiment of the present invention.

[0067] Referring to FIG. 3, the display panel (DP) may include a driving circuit (GDC), signal lines (SGL), and pixels (PX). The display panel (DP) may include a pixel pad section (PDD) comprising pixel pads (D-PD) that are placed in an inactive area (NAA) and connected to corresponding signal lines among the signal lines (SGL). For convenience of explanation, a first flexible circuit board (FF) connected to the pixel pad section (PDD) is shown with a dotted line.

[0068] Pixels (PX) are provided in plurality and placed in an active area (AA). Each pixel (PX) includes an organic light-emitting diode (OLED) and a pixel driving circuit connected thereto. The driving circuit (GDC), signal lines (SGL), pixel pad portion (PDD), and pixel driving circuit may be included in the circuit element layer (CL) shown in FIG. 2a.

[0069] The driving circuit (GDC) may include a gate driving circuit. The gate driving circuit generates gate signals and sequentially outputs the gate signals to the gate lines (GL) described below. The gate driving circuit may further output another control signal to the pixel driving circuit.

[0070] The gate driving circuit may include a plurality of transistors formed through the same process as the driving circuit of the pixels (PX), such as the LTPS (Low Temperature Polycrystalline Silicon) process or the LTPO (Low Temperature Polycrystalline Oxide) process.

[0071] The signal lines (SGL) include gate lines (GL), data lines (DL), power lines (PL), and control signal lines (CSL). One gate line among the gate lines (GL) is connected to a corresponding pixel among the pixels (PX), and one data line among the data lines (DL) is connected to a corresponding pixel among the pixels (PX). The power line (PL) is connected to the pixels (PX). The control signal line (CSL) can provide control signals to the gate driving circuit.

[0072] The pixel pad portion (PDD) is a portion to which the first flexible circuit board (FF) is connected, and the pixel pads (D-PD) of the pixel pad portion (PDD) are connected to pads (not shown) included in the first flexible circuit board (FF). Accordingly, the display panel (DP) and the main circuit board (MF) can be connected through the first flexible circuit board (FF).

[0073] Pixel pads (D-PDs) can be provided by some of the wirings disposed in the circuit element layer (CL) being exposed from the insulating layer included in the circuit element layer (CL).

[0074] Pixel pads (D-PDs) are connected to signal lines (SGLs) and connected to corresponding pixels (PXs). Additionally, a driving circuit (GDC) may be connected to any one of the pixel pads (D-PDs).

[0076] Referring to FIG. 4a, one pixel (PX-1, hereinafter pixel) among the pixels (PX) illustrated in FIG. 3 may be electrically connected to signal lines. Among the signal lines, gate lines (GLi, GLi-1), data line (DL), first power line (PL1), second power line (PL2), initialization power line (VIL), and light emission control line (ECLi) are illustrated as examples. However, this is illustrated as an example, and the pixel (PX-1) according to one embodiment of the present invention may be additionally connected to various signal lines, and some of the illustrated signal lines may be omitted.

[0077] A pixel (PX-1) may include an organic light-emitting diode (OLED) and a pixel circuit (CC). The pixel circuit (CC) may include transistors (T1-T7) and a capacitor (CP). The pixel circuit (CC) can control the amount of current flowing through the organic light-emitting diode (OLED) in response to a data signal.

[0078] An organic light-emitting diode (OLED) can emit light with a predetermined brightness in response to the amount of current provided from a pixel circuit (CC). To this end, the level of the first power supply (ELVDD) can be set higher than the level of the second power supply (ELVSS).

[0079] Each of the transistors (T1-T7) may include an input electrode (or source electrode), an output electrode (or drain electrode), and a control electrode (or gate electrode). For convenience within this specification, either the input electrode or the output electrode may be referred to as the first electrode and the other as the second electrode.

[0080] The first electrode of the first transistor (T1) may be connected to the first power wiring (PL1) via the fifth transistor (T5). The first power wiring (PL1) may be a wiring that provides the first power (ELVDD). The second electrode of the first transistor (T1) is connected to the anode electrode of the organic light-emitting diode (OLED) via the sixth transistor (T6). The first transistor (T1) may be referred to as a driving transistor within this specification. The first transistor (T1) can control the amount of current flowing through the organic light-emitting diode (OLED) in response to the voltage applied to the control electrode of the first transistor (T1).

[0081] The second transistor (T2) is connected between the data line (DL) and the first electrode of the first transistor (T1). The control electrode of the second transistor (T2) is connected to the i-th gate line (GLi). When the i-th scan signal is provided to the i-th gate line (GLi), the second transistor (T2) is turned on to electrically connect the data line (DL) and the first electrode of the first transistor (T1).

[0082] The third transistor (T3) is connected between the second electrode of the first transistor (T1) and the control electrode of the first transistor (T1). The control electrode of the third transistor (T3) is connected to the i-th gate line (GLi). When the i-th scan signal is provided to the i-th gate line (GLi), the third transistor (T3) is turned on to electrically connect the second electrode of the first transistor (T1) and the control electrode of the first transistor (T1). Thus, when the third transistor (T3) is turned on, the first transistor (T1) is connected in the form of a diode.

[0083] The fourth transistor (T4) is connected between the node (ND) and the initialization power line (VIL). Also, the control electrode of the fourth transistor (T4) is connected to the i-1th gate line (GLi-1). The node (ND) may be the node where the control electrodes of the fourth transistor (T4) and the first transistor (T1) are connected. When the i-1th scan signal is provided to the i-1th gate line (GLi-1), the fourth transistor (T4) is turned on to provide an initialization voltage (Vint) to the node (ND).

[0084] The fifth transistor (T5) is connected between the first power wiring (PL1) and the first electrode of the first transistor (T1). The sixth transistor (T6) is connected between the second electrode of the first transistor (T1) and the anode electrode of the organic light-emitting diode (OLED). The control electrode of the fifth transistor (T5) and the control electrode of the sixth transistor (T6) are connected to the i-th light-emitting control wiring (ECLi).

[0085] The seventh transistor (T7) is connected between the initialization power wiring (VIL) and the anode electrode of the organic light-emitting diode (OLED). The control electrode of the seventh transistor (T7) is connected to the i-th gate line (GLi). When the i-th scan signal is provided to the i-th gate line (GLi), the seventh transistor (T7) is turned on to provide an initialization voltage (Vint) to the anode electrode of the organic light-emitting diode (OLED).

[0086] The seventh transistor (T7) can improve the black expression capability of the pixel (PX-1). Specifically, when the seventh transistor (T7) is turned on, the parasitic capacitor (not shown) of the organic light-emitting diode (OLED) is discharged. Then, when black luminance is achieved, the organic light-emitting diode (OLED) does not emit light due to leakage current from the first transistor (T1), and accordingly, the black expression capability can be improved.

[0087] Additionally, in FIG. 4a, the control electrode of the seventh transistor (T7) is shown connected to the i-th gate line (GLi), but the present invention is not limited thereto. In another embodiment of the present invention, the control electrode of the seventh transistor (T7) may be connected to the i-1-th gate line (GLi-1) or the i+1-th gate line (not shown).

[0088] Although FIG. 4a is illustrated based on a PMOS, it is not limited thereto. In another embodiment of the present invention, the pixel circuit (CC) may be composed of an NMOS. In yet another embodiment of the present invention, the pixel circuit (CC) may be composed of a combination of an NMOS and a PMOS.

[0089] A capacitor (CP) is placed between the first power line (PL1) and the node (ND). The capacitor (CP) stores a voltage corresponding to a data signal. Depending on the voltage stored in the capacitor (CP), the amount of current flowing through the first transistor (T1) can be determined when the fifth transistor (T5) and the sixth transistor (T6) are turned on.

[0090] The organic light-emitting diode (OLED) can be electrically connected to the sixth transistor (T6) and the second power line (PL2). The organic light-emitting diode (OLED) can receive the second power (ELVSS) through the second power line (PL2). The organic light-emitting diode (OLED) may include a light-emitting layer.

[0091] An organic light-emitting diode (OLED) can emit light at a voltage corresponding to the difference between the signal transmitted through the sixth transistor (T6) and the second power supply (ELVSS) received through the second power supply wiring (PL2).

[0092] In the present invention, the structure of the pixel (PX-1) is not limited to the structure shown in FIG. 4a. In other embodiments of the present invention, the pixel (PX-1) can be implemented in various forms to emit light from an organic light-emitting diode (OLED).

[0094] Referring to FIG. 4b, the display panel (DP) may include insulating layers, semiconductor patterns, conductive patterns, signal lines, etc. Insulating layers, semiconductor layers, and conductive layers may be formed by methods such as coating or deposition. Subsequently, insulating layers, semiconductor layers, and conductive layers may be selectively patterned by photolithography. In this way, semiconductor patterns, conductive patterns, signal lines, etc. included in the circuit element layer (CL) and the display element layer (PE) can be formed.

[0095] The base substrate (SUB) may include a synthetic resin layer. The synthetic resin layer may include a thermosetting resin. The base substrate (SUB) may have a multilayer structure. For example, the base substrate (SUB) may have a three-layer structure consisting of a synthetic resin layer, an adhesive layer, and a synthetic resin layer. In particular, the synthetic resin layer may be a polyimide-based resin layer, and the material thereof is not particularly limited. The synthetic resin layer may include at least one of an acrylic resin, a methacrylate resin, a polyisoprene, a vinyl resin, an epoxy resin, a urethane resin, a cellulose resin, a siloxane resin, a polyamide resin, and a perylene resin. In addition, the base substrate (SUB) may include a glass substrate, a metal substrate, or an organic / inorganic composite material substrate, etc.

[0096] At least one inorganic layer may be disposed on the upper surface of a base substrate (SUB). The inorganic layer may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide. The inorganic layer may be formed in multiple layers. The multiple inorganic layers may constitute a barrier layer and / or a buffer layer.

[0097] In this embodiment, the display panel (DP) is shown to include a buffer layer (BFL). The buffer layer (BFL) enhances the bonding strength between the base substrate (SUB) and the semiconductor pattern included in the transistor. The base substrate (SUB) may include a silicon oxide layer and a silicon nitride layer. The silicon oxide layer and the silicon nitride layer may be stacked alternately.

[0098] A semiconductor pattern is disposed on a buffer layer (BFL). The semiconductor pattern may include polysilicon. However, it is not limited thereto, and the semiconductor pattern may include amorphous silicon or metal oxide.

[0099] FIG. 4b illustrates only a partial semiconductor pattern, and additional semiconductor patterns may be placed in other regions of the pixel (PX) on the plane. The semiconductor patterns may be arranged according to specific rules across the pixels. The electrical properties of the semiconductor patterns differ depending on whether they are doped. The semiconductor patterns may include doped regions and non-doped regions. The doped regions may be doped with an N-type dopant or a P-type dopant. A P-type transistor includes a doped region doped with a P-type dopant.

[0100] The doped region has greater conductivity than the undoped region and effectively functions as an electrode or signal line. The undoped region effectively corresponds to the active (or channel) of the transistor. In other words, a portion of the semiconductor pattern may be the active of the transistor, another portion may be the source or drain, and yet another portion may be an additional electrode or signal line.

[0101] As shown in FIG. 4b, the source (S1), active (A1), and drain (D1) of the first transistor (T1) are formed from a semiconductor pattern, and the source (S6), active (A6), and drain (D6) of the sixth transistor (T6) are formed from a semiconductor pattern. The sources (S1, S6) and drains (D1, D6) extend in opposite directions from the active (A1, A6) on a cross-section.

[0102] A first intermediate insulating layer (10) is disposed on a buffer layer (BFL). The first intermediate insulating layer (10) overlaps commonly with a plurality of pixels and covers a semiconductor pattern. The first intermediate insulating layer (10) may be an inorganic layer and / or an organic layer, and may have a single layer or a multilayer structure.

[0103] The first intermediate insulating layer (10) may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide. In this embodiment, the first intermediate insulating layer (10) may be a single layer of silicon oxide.

[0104] The insulating layer of the first intermediate insulating layer (10) as well as the insulating layer of the circuit element layer (CL) described later may be an inorganic layer and / or an organic layer, and may have a single layer or a multilayer structure. The inorganic layer may include at least one of the materials described above.

[0105] A gate (G1, G6) is placed on the first intermediate insulating layer (10). The gate (G1) may be part of a metal pattern. The gate (G1, G6) may be superimposed on an active (A1, A6). In the process of doping a semiconductor pattern, the gate (G1, G6) is like a mask.

[0106] A second intermediate insulating layer (20) covering gates (G1, G6) is disposed on the first intermediate insulating layer (10). The second intermediate insulating layer (20) can be superimposed on pixels in common. The second intermediate insulating layer (20) may be an inorganic layer and / or an organic layer, and may have a single-layer or multi-layer structure. In this embodiment, the second intermediate insulating layer (20) may be a single-layer silicon oxide layer.

[0107] A first additional electrode (SD1) may be disposed on the second intermediate insulating layer (20). The first additional electrode (SD1) may be connected to a drain (D6) through a contact hole (CNT-1) penetrating the first intermediate insulating layer (10) and the second intermediate insulating layer (20).

[0108] A first insulating layer (30) is disposed on a second intermediate insulating layer (20). The first insulating layer (30) may be an organic layer. A second additional electrode (SD2) may be connected to a first additional electrode (SD1) through a contact hole (CNT-2) penetrating the first insulating layer (30).

[0109] A second insulating layer (40) covering a second additional electrode (SD2) is disposed on the first insulating layer (30). The second insulating layer (40) may be an organic layer. A first electrode (EL1) is disposed on the second insulating layer (40). The first electrode (EL1) is connected to the second additional electrode (SD2) through a contact hole (CNT-3) penetrating the second insulating layer (40). A display opening (OP) is defined in the pixel defining film (PDL). The display opening (OP) of the pixel defining film (PDL) exposes at least a portion of the first electrode (EL1).

[0110] The hole control layer (HCL) includes a hole transport layer and may further include a hole injection layer. An emitting layer (EML) is disposed on the hole control layer (HCL). The emitting layer (EML) may be disposed in an area corresponding to a display aperture (OP). That is, the emitting layer (EML) may be formed separately for each pixel.

[0111] An electronic control layer (ECL) is disposed on the light-emitting layer (EML). The electronic control layer (ECL) includes an electron transport layer and may further include an electron injection layer. The hole control layer (HCL) and the electronic control layer (ECL) can be formed commonly across multiple pixels using an open mask. A second electrode (EL2) is disposed on the electronic control layer (ECL). The second electrode (EL2) has a single shape and is disposed commonly across multiple pixels.

[0112] An encapsulation layer (TFE) is disposed on the second electrode (EL2). The encapsulation layer (TFE) is disposed commonly across a plurality of pixels. In this embodiment, the encapsulation layer (TFE) can directly cover the second electrode (EL2). In one embodiment of the present invention, a capping layer covering the second electrode (EL2) may be further disposed between the encapsulation layer (TFE) and the second electrode (EL2). In this case, the encapsulation layer (TFE) can directly cover the capping layer.

[0113] The encapsulation layer (TFE) is disposed on the organic light-emitting diode (OLED) to encapsulate the organic light-emitting diode (OLED). Meanwhile, although not illustrated, a capping layer covering the second electrode (EL2) may be further disposed between the second electrode (EL2) and the organic light-emitting diode (OLED). The encapsulation layer (TFE) illustrated in FIG. 4b may correspond to the encapsulation layer (TFE) described in FIG. 2b.

[0114] Referring again to FIG. 1b, the main circuit board (MF) includes a base circuit board (MP) and a driving element (MC). The base circuit board (MP) is connected to a first flexible circuit board (FF) and is electrically connected to a display panel (DP), and the base circuit board (MP) is connected to a second flexible circuit board (TF) and is electrically connected to an input sensing panel (ISP). The base circuit board (MP) may be composed of a flexible printed circuit board (FPCB).

[0115] The driving element (MC) may include a signal control unit (Timing controller). The signal control unit receives input video signals and converts the input video signals into video data corresponding to the operation of the pixels. Additionally, the signal control unit receives various control signals, such as a vertical synchronization signal, a horizontal synchronization signal, a main clock signal, and a data in-mage signal, and can output signals corresponding to each of the said signals. Furthermore, the driving element (MC) may include a control unit that controls an input sensing panel (ISP), and is not limited to any one embodiment.

[0116] The first flexible circuit board (FF) is connected to one side of the display panel (DP) and electrically connects the display panel (DP) and the main circuit board (MF). The first flexible circuit board (FF) includes a base film (FB) and a driving chip (FC).

[0117] The base film (FB) is flexible and may include circuit wiring (not shown). Accordingly, the base film (FB) can be provided in various forms corresponding to the purpose and form of the display panel (DP).

[0118] The driving chip (FC) may be mounted on the base film (FB) in the form of a Chip On Film (COF). The driving chip (FC) may include a driving element for driving pixels, for example, a data driving circuit. Although the first flexible circuit board (FF) according to one embodiment of the present invention is illustrated as a single unit, it is not limited thereto and may be provided in multiple units and connected to a display panel (DP).

[0119] The second flexible circuit board (FF) is connected to one side of the input detection panel (ISP) to electrically connect the input detection panel (ISP) and the main circuit board (MF). The second flexible circuit board (TF) has flexibility and may include a plurality of circuit wires (not shown). The second flexible circuit board (TF) transmits input detection signals provided by the main circuit board (MF) to the input detection panel (ISP).

[0121] FIG. 5a is a plan view of an input sensing panel according to an embodiment of the present invention. FIG. 5b is an enlarged plan view of the PP' region shown in FIG. 5a. FIG. 5c is a plan view showing the arrangement relationship between the light-emitting region, the conductive pattern, and the cover layer in the QQ' region shown in FIG. 5a.

[0122] Referring to FIG. 5a, the input sensing panel (ISP) may include a sensing pad section (TDL) comprising a first sensing electrode (TE1), a second sensing electrode (TE2), a first signal line (SL1), a second signal line (SL2), and sensing pads (T-PD).

[0123] Additionally, the input sensing panel (ISP) according to the present invention may include a functional layer (FL) that surrounds at least a portion of the first sensing electrode (TE1) and the second sensing electrode (TE2). For convenience of explanation, the functional layer (FL) is omitted in FIGS. 5a and 5b.

[0124] The first sensing electrode (TE1) extends along the second direction (DR2). The first sensing electrode (TE1) may be provided in multiple numbers and arranged along the first direction (DR1). The first sensing electrode (TE1) includes first sensing patterns (SP1) arranged along the second direction (DR2) and a first connecting pattern (BP1) disposed between the first sensing patterns (SP1).

[0125] The second sensing electrode (TE2) may be positioned to be insulated from the first sensing electrode (TE1). The second sensing electrode (TE2) extends along the first direction (DR1). The second sensing electrode (TE2) may be provided in multiple numbers and arranged along the second direction (DR2). The second sensing electrode (TE2) includes second sensing patterns (SP2) arranged along the first direction (DR1) and a second connecting pattern (BP2) positioned between the second sensing patterns (SP2).

[0126] The input sensing panel (ISP) can detect an external input (TC: see FIG. 1a) by detecting a change in mutual capacitance between the first sensing electrode (TE1) and the second sensing electrode (TE2), or detect an external input (TC) by detecting a change in the magnetic capacitance of each of the first sensing electrode (TE1) and the second sensing electrode (TE2). An input sensing panel (ISP) according to one embodiment of the present invention can detect an external input (TC) in various ways and is not limited to any one embodiment.

[0127] The first signal line (SL1) is connected to the first sensing electrode (TE1). The first signal line (SL1) may be placed in the surrounding area (NAA) and may not be visible from the outside. The second signal line (SL2) is connected to the second sensing electrode (TE2). The second signal line (SL2) may be placed in the surrounding area (NAA) and may not be visible from the outside.

[0128] Meanwhile, in this embodiment, one first sensing electrode (TE1) can be connected to two first signal lines. One end and the other end of one first sensing electrode (TE1) can be connected to different first signal lines (SL1) and connected to two first pads. Accordingly, even if the first sensing electrode (TE1) has a relatively longer length than the second sensing electrode (TE2), an electrical signal can be applied uniformly over the entire area. Therefore, the input sensing panel (ISP) can provide an even external input sensing environment over the entire active area (AA) regardless of its shape.

[0129] However, this is illustrated as an example, and the second sensing electrode (TE2) may also be connected to two second signal lines, or the first sensing electrode (TE1) and the second sensing electrode (TE2) may each be connected to only one signal line. An input sensing panel (ISP) according to one embodiment of the present invention may be driven in various ways and is not limited to any one embodiment.

[0130] The sensing pad section (TDL) is a part to which the second flexible circuit board (TF) is connected, and the sensing pads (T-PD) of the sensing pad section (TDL) are connected to pads (not shown) included in the second flexible circuit board (TF). Accordingly, the input sensing panel (ISP) and the main circuit board (MF) can be connected through the second flexible circuit board (TF).

[0132] In FIG. 5b, a portion of each of the first sensing patterns (SP1), the first connection pattern (BP1), the second sensing patterns (SP2), and the second connection pattern (BP2) constituting a pattern of one of the sensing electrodes (TE1, TE2, see FIG. 5a) is shown in enlarged view.

[0133] The input sensing panel (ISP) according to the present invention may include mesh lines (MSL1, MSL2). The mesh lines (MSL1, MSL2) may be composed of a first mesh line (MSL1) and a second mesh line (MSL2). The first mesh line (MSL1) may extend along a fourth direction (DR4), and the second mesh line (MSL2) may intersect the first mesh line (MSL1) and extend along a fifth direction (DR5).

[0134] According to the present invention, the first conductive patterns (TML1) described in FIG. 2b may be composed of a first connecting pattern (BP1). The second conductive patterns (TML2) described in FIG. 2b may be composed of first sensing patterns (SP1), second sensing patterns (SP2), and a second connecting pattern (BP2).

[0135] According to the present embodiment, the first sensing patterns (SP1), the second sensing patterns (SP2), and the second connection pattern (BM2) constituting the second conduction patterns (TML2) may include mesh lines (MSL1, MSL2).

[0136] A first connection pattern (BP1) may be placed on a first sensing insulating layer (TML1) and covered by a second sensing insulating layer (TML2). First sensing patterns (SP1), second sensing patterns (SP2), and second connection pattern (BP2) may be placed on a second sensing insulating layer (TML2) and covered by a third sensing insulating layer (TML3, see FIG. 2b).

[0137] Contact holes (B-CNT) are defined in the second sensing insulating layer (TIL2), and the first conductive patterns (SP1) and the first connecting pattern (BP1) can be connected through the contact holes (B-CNT).

[0139] FIG. 5c illustrates the relationship between the light-emitting regions (PXA-R, PXA-G, PXA-B), the second conductive patterns (TML2) included in the input sensing panel (ISP), and the functional layer (FL).

[0140] The functional layer (FL) can cover at least a portion of the mesh lines (MSL1, MSL2). Although FIG. 5c shows the functional layer (FL) covering all of the mesh lines (MSL1, MSL2), it is not limited thereto, and the functional layer (FL) can cover only a portion of the mesh lines (MSL1, MSL2).

[0141] Functional openings (OP-FR, OP-FG, OP-FB) can be defined by the outer edge of the functional layer (FL). The functional openings (OP-FR, OP-FG, OP-FB) may consist of a first functional opening (OP-FR), a second functional opening (OP-FG), and a third functional opening (OP-FB).

[0142] The light-emitting regions (PXA-R, PXA-G, PXA-B) according to the present invention may correspond to the area on the plane of the functional openings (OP-FR, OP-FG, OP-FB) defined in the functional layer (FL). Accordingly, the light-emitting regions (PXA-R, PXA-G, PXA-B) according to the present invention may be increased or decreased depending on the volume change of the functional layer (FL) described later.

[0143] The non-luminous region (NPXA) may be adjacent to the luminous regions (PXA-R, PXA-G, PXA-B). The mesh lines (MSL1, MSL2) constituting the input sensing panel (ISP) may be arranged to overlap with the non-luminous region (NPXA). Accordingly, even if the input sensing panel (ISP) is placed directly on the display panel (DP, see FIG. 2a), interference with light formed on the display panel (DP) can be minimized. Accordingly, a display device (EA, see FIG. 1a) with improved color purity can be provided.

[0144] According to the present embodiment, the light-emitting regions (PXA-R, PXA-G, PXA-B) may be composed of a first light-emitting region (PXA-R), a second light-emitting region (PXA-G), and a third light-emitting region (PXA-B). Each of the light-emitting regions (PXA-R, PXA-G, PXA-B) may provide light of a different color.

[0145] According to the present invention, the functional layer (FL) may include a piezoelectric material. By means of the piezoelectric material, the volume of the functional layer (FL) may be varied as voltage is applied to the mesh lines (MSL1, MSL2). At this time, as the area of ​​the functional openings (OP-RF, OP-RG, OP-RB) is varied, the area of ​​the light-emitting regions (PXA-R, PXA-G, PXA-B) may be varied. A detailed description will be provided later.

[0146] The functional openings (OP-FR, OP-FG, OP-FB) may have different areas. For example, the third functional opening (OP-FB) may be larger than the areas of the first functional opening (OP-FR) and the second functional opening (OP-FG). The first functional opening (OP-FR) may be larger than the area of ​​the second functional opening (OP-FG).

[0147] The areas of the functional openings (OP-FR, OP-FG, OP-FB) are shown as different from each other as an example, but are not limited thereto. The areas of the functional openings (OP-FR, OP-FG, OP-FB) may be the same.

[0148] The display opening (OP) illustrated in FIG. 5c corresponds to the display opening (OP) illustrated in FIG. 4b. For convenience of explanation, the areas of the functional openings (OP-FR, OP-FG, OP-FB) are depicted as being larger than the area of ​​the corresponding display opening (OP), but the areas of the functional openings (OP-FR, OP-FG, OP-FB) may be equal to the area of ​​the corresponding display opening (OP), and depending on the volume change of the functional layer (FL), the areas of the functional openings (OP-FR, OP-FG, OP-FB) may be smaller than the area of ​​the display opening (OP).

[0150] FIG. 6a is a cross-sectional view of a display device cut along I-I' of FIG. 5c in the first mode. FIG. 6b is a cross-sectional view of a display device cut along I-I' of FIG. 5c in the second mode.

[0151] In the present invention, the second conduction patterns (TML2) may be subjected to different voltages. For example, the first signal line (SL1, see FIG. 5a) and the second signal line (SL2, see FIG. 5a) may apply different voltages to the second conduction patterns (TML2).

[0152] In the present invention, a state in which a (+) voltage is applied to the second conduction patterns (TML2) is defined as the first mode, and a state in which a (-) voltage is applied to the second conduction patterns (TML2) is defined as the second mode.

[0153] According to the present embodiment, a voltage of +5V may be applied to the second conduction patterns (TML2) in the first mode, and a voltage of -5V may be applied in the second mode. However, this is not limited thereto, and a (-) voltage may be applied in the first mode, and a (+) voltage may be applied in the second mode. Alternatively, voltages of different values ​​with the same sign may be applied in each mode.

[0154] However, it is not limited thereto, and the second challenge patterns (TML2) may be connected to multiple first signal lines or connected to multiple second signal lines to receive different voltages, and are not limited to any one embodiment.

[0155] Referring to FIG. 6a, the display panel (DP) may include a base layer (SUB), a circuit element layer (CL), and a display element layer (PE, see FIG. 2a). Among the components of the display element layer (PE), only the first electrodes (EL1-R, EL1-G, EL1-B) and the pixel definition film (PDL) are shown. Refer to FIG. 4b for the detailed structure of the display element layer (PE).

[0156] A circuit element layer (CL) may be disposed on a base layer (SUB). First electrodes (EL1-R, EL1-G, EL1-B) may be disposed on the circuit element layer (CL). Display openings (OP-R, OP-G, OP-B) are defined by a pixel defining film (PDL). The display opening (OP) described in FIGS. 4b and 5c may correspond to at least one of the display openings (OP-R, OP-G, OP-B) shown in FIG. 6a.

[0157] The encapsulation layer (TFE) may be disposed on the display element layer (PE). The encapsulation layer (TFE) may include a first encapsulation inorganic layer (LIL), an organic layer (OEL), and a second encapsulation inorganic layer (UIL).

[0158] The input sensing pattern (ISP) can be placed directly on the encapsulation layer (TFE). The input sensing pattern (ISP) may include sensing insulating layers (TIL1, TIL2, TIL3), conductive patterns (TML1, TML2), a piezoelectric pattern (PP), and a light-blocking pattern (BM).

[0159] A first sensing insulating layer (TIL1) is disposed on a second encapsulating inorganic layer (UIL) of an encapsulating layer (TFE), and first conductive patterns (TML1) may be disposed on the first sensing insulating layer (TIL1). A second sensing insulating layer (TIL2) is disposed on the first sensing insulating layer (TIL1) and may cover the first conductive patterns (TML1). Second conductive patterns (TML2) may be disposed on the second sensing insulating layer (TIL2).

[0160] A piezoelectric pattern (PP) can be placed on a second sensing insulating layer (TIL2). The piezoelectric pattern (PP) can cover the upper surface (TU) and side surface (TS) of the second conductive patterns (TML2).

[0161] The piezoelectric pattern (PP) may be composed of a single crystal, ceramics, a thin film, etc. The single crystal may include at least one of quartz and lithium niobate (LiNbO3). The ceramic may include at least one of barium titanate (BaTiO3) and lead zirconate titanate (PZT). The thin film may include at least one of zinc oxide (ZnO), lead zirconate titanate (PZT), and aluminum nitride (AlN). However, it is not limited thereto, and is not limited to any one of the materials whose volume varies according to the applied voltage.

[0162] A light-blocking pattern (BM) can be placed on the second sensing insulating layer (TIL2). The light-blocking pattern (BM) can cover the upper surface (PU) and the side surface (PS) of the piezoelectric pattern (PP).

[0163] The light-blocking pattern (BM) may include a material capable of absorbing light. The material constituting the light-blocking pattern (BM) is not limited to any one of the materials capable of absorbing light.

[0164] A display device (EA) according to the present invention can provide first mode light-emitting regions (PXA-R1, PXA-G1, PXA-B1) to a user in a first mode. In the first mode, the width between adjacent sides (BS) of the light-blocking pattern (BM) is defined by first transmission openings (OP-BR1, OP-BG1, OP-BB1). Depending on the change in area of ​​the first transmission openings (OP-BR1, OP-BG1, OP-BB1), the area of ​​the first mode light-emitting regions (PXA-R1, PXA-G1, PXA-B1) can be determined.

[0165] For example, the first permeable openings (OP-BR1, OP-BG1, OP-BB1) may include a first-1 permeable opening (OP-BR1), a first-2 permeable opening (OP-BG1), and a first-3 permeable opening (OP-BB1).

[0166] The first-1 light-emitting region (PXA-R1) may correspond to the area of ​​the first transmission opening (OP-BR1). The first-2 light-emitting region (PXA-G1) may correspond to the area of ​​the second transmission opening (OP-BG1). The first-3 light-emitting region (PXA-B1) may correspond to the area of ​​the third transmission opening (OP-BB1).

[0167] In cross-section, each of the first transparent openings (OP-BR1, OP-BG1, OP-BB1) may overlap with at least a portion of the corresponding display openings (OP-R, OP-G, OP-B).

[0168] According to FIG. 6a, the edges of the piezoelectric pattern (PP) and the light-shielding pattern (BM) in cross-section are shown to have curvature. However, this is not limited to the piezoelectric pattern (PP) and the light-shielding pattern (BM), and the piezoelectric pattern (PP) and the light-shielding pattern (BM) may have various shapes in cross-section.

[0169] The third sensing insulating layer (TIL3) is disposed on the second sensing insulating layer (TIL2) and can cover the upper surface (BU) and side surface (BS) of the light-blocking pattern (BM). The third sensing insulating layer (TIL3) can be in contact with the second sensing insulating layer (TIL2) in an area overlapping with the first transparent openings (OP-BR1, OP-BG1, OP-BB1).

[0170] Color filters (CF-R, CF-G, CF-B) may be disposed on the third sensing insulating layer (TIL3). Each of the first color filter (CF-R), the second color filter (CF-G), and the third color filter (CF-B) may correspond to the first-1 light-emitting region (PXA-R), the first-2 light-emitting region (PXA-G), and the first-3 light-emitting region (PXA-B).

[0171] Color filters (CF-R, CF-G, CF-B) may comprise a base resin and a dye and / or pigment dispersed in the base resin. The base resin is a medium in which the dye and / or pigment is dispersed and may consist of various resin compositions that can generally be referred to as a binder.

[0172] The color filters (CF-R, CF-G, CF-B) can reduce the reflectance of external light. Each of the first color filter (CF-R), the second color filter (CF-G), and the third color filter (CF-B) transmits light within a specific wavelength range and absorbs light outside that wavelength range, so they can absorb most of the natural light and reflect only a portion of it.

[0173] A window member (WM) may be disposed on the color filters (CF-R, CF-G, CF-B). The window member (WM) may be bonded to the color filters (CF-R, CF-G, CF-B) by an adhesive layer (AL).

[0174] The adhesive layer (AL) may be a transparent adhesive layer such as any one of a pressure-sensitive adhesive film (PSA), an optically clear adhesive film (OCA), and an optically clear resin (OCR).

[0175] However, the adhesive layer (AL) may include a conventional adhesive or pressure-sensitive adhesive and is not particularly limited. Additionally, the adhesive layer (AL) may be omitted.

[0176] In the present invention, the volume of the piezoelectric pattern (PP) can be varied according to the voltage applied to the second conductive patterns (TML2). The volume of the light-blocking pattern (BM) can be varied simultaneously with the piezoelectric pattern (BM) as the volume of the piezoelectric pattern (PP) is varied.

[0178] In FIG. 6b, a configuration that changes as the volumes of the piezoelectric pattern (PP) and the light-blocking pattern (BM) vary in the second mode is described, and a description of a configuration that remains the same as FIG. 6a is omitted.

[0179] According to the present invention, when converting from a first mode to a second mode, the volumes of the piezoelectric pattern (PP) and the light-blocking pattern (BM) can be increased simultaneously.

[0180] The display device (EA) according to the present invention can provide the user with second mode light-emitting regions (PXA-R2, PXA-G2, PXA-B2) in a second mode. In the second mode, the width between adjacent sides (BS) of the light-blocking pattern (BM) is defined by second transmission openings (OP-BR2, OP-BG2, OP-BB2).

[0181] As the area of ​​the second transmission openings (OP-BR2, OP-BG2, OP-BB2) is reduced, the area of ​​the second mode emission regions (PXA-R2, PXA-G2, PXA-B2) can also be reduced.

[0182] According to the present invention, the width of each of the second transmission openings (OP-BR2, OP-BG2, OP-BB2) can be reduced compared to the width of the first transmission openings (OP-BR1, OP-BG1, OP-BB1).

[0183] For example, the width of the 2-1 permeable opening (OP-BR2) may be smaller than the width of the 1-1 permeable opening (OP-BR1). The width of the 2-2 permeable opening (OP-BG2) may be smaller than the width of the 1-2 permeable opening (OP-BG1). The width of the 2-3 permeable opening (OP-BB2) may be smaller than the width of the 1-3 permeable opening (OP-BB1).

[0184] When switching from the first mode to the second mode, the light-blocking pattern (BM) may be increased by a protrusion width (W) in the direction toward the second mode light-emitting regions (PXA-R2, PXA-G2, PXA-B2). In this embodiment, the protrusion width (W) may be defined as the width of the light-blocking pattern (BM) that protrudes toward the second mode light-emitting regions (PXA-R2, PXA-G2, PXA-B2) more than the display openings (OP-R, OP-G, OP-B) when switching from the first mode to the second mode based on the boundaries of the display openings (OP-R, OP-G, OP-B).

[0185] Accordingly, the 2-1 light-emitting region (PXA-R2) may have a light-emitting region reduced by the leftward protrusion width (W) and the rightward protrusion width (W) compared to the 1-1 light-emitting region (PXA-R1). The 2-2 light-emitting region (PXA-G2) may have a light-emitting region reduced by the leftward protrusion width (W) and the rightward protrusion width (W) compared to the 1-2 light-emitting region (PXA-G1). The 2-3 light-emitting region (PXA-B2) may have a light-emitting region reduced by the leftward protrusion width (W) and the rightward protrusion width (W) compared to the 1-3 light-emitting region (PXA-B1).

[0186] In the present invention, the protrusion width (W) may be 2 micrometers or more and 5 micrometers or less. When the protrusion width (W) is less than 2 micrometers, the effect of reducing the viewing angle may not be sufficient. When the protrusion width (W) is greater than 5 micrometers, the viewing angle is reduced, and a problem may occur in which the non-luminous area (NPXA) is visible to the user.

[0187] Although it has been illustrated as an example that the second mode light-emitting regions (PXA-R2, PXA-G2, PXA-B2) are reduced to the same width, this is not limited thereto, and when switching from the first mode to the second mode, the second mode light-emitting regions (PXA-R2, PXA-G2, PXA-B2) may have different protrusion widths (W) of the light-blocking pattern (BM).

[0188] The light provided to the second mode light-emitting regions (PXA-R2, PXA-G2, PXA-B2) can be provided to the user with a narrower viewing angle than the light provided to the first mode light-emitting regions (PXA-R1, PXA-G1, PXA-B1).

[0189] According to the present invention, by increasing or decreasing the viewing angle as needed to block the viewing angle of a third party looking from the side, a display device with enhanced privacy protection can be provided.

[0191] FIG. 7a is a cross-sectional view of a display device in a first mode. FIG. 7b is a cross-sectional view of a display device in a second mode. Hereinafter, identical or similar reference numerals are used for configurations identical or similar to those described with reference to FIG. 1 to FIG. 6b, and redundant descriptions are omitted.

[0192] Referring to FIG. 7a, a display device (EA-A) according to the present embodiment may include a display panel (DP), an input sensing panel (ISP), an anti-reflection member (ARL), and a window member (WM). The anti-reflection member (ARL) may include a polarization layer (POL) and a phase delay layer (PRL). The display panel (DP) illustrated in FIG. 7a and FIG. 7b may correspond to the display panel (DP) described in FIG. 4b. Therefore, redundant descriptions are omitted.

[0193] An input sensing panel (ISP) may be placed on a display panel (DP). The input sensing panel (ISP) may include sensing insulating layers (TIL1, TIL2, TIL3-A), conductive patterns (TML1, TML2), and a cover layer (HRF).

[0194] A first sensing insulating layer (TIL1) is disposed on a display panel (DP), and first conductive patterns (TML1) may be disposed on the first sensing insulating layer (TIL1). A second sensing insulating layer (TIL2) is disposed on the first sensing insulating layer (TIL1) and may cover the first conductive patterns (TML1). Second conductive patterns (TML2) may be disposed on the second sensing insulating layer (TIL2).

[0195] A piezoelectric pattern (PP) is placed on a second sensing insulating layer (TIL2) and can cover the second conductive patterns (TML2). A light-blocking pattern (BM) is placed on the second sensing insulating layer (TIL2) and can cover the piezoelectric pattern (PP).

[0196] The third sensing insulating layer (TIL3-A) is disposed on the second sensing insulating layer (TIL2) and can cover the light-blocking pattern (BM). In this embodiment, the third sensing insulating layer (TIL3-A) may have a predetermined pattern.

[0197] For example, the third sensing insulating layer (TIL3-A) can cover the upper and side surfaces of the light-blocking pattern (BM) in cross-section and expose the second sensing insulating layer (TIL2) in the area overlapping with the first light-emitting region (PXA-1) of the second sensing insulating layer (TIL2).

[0198] According to the present embodiment, the third sensing insulating layer (TIL3-A) may have a trapezoidal shape in cross-section. Accordingly, it may include an inclined surface (IS) inclined from the second sensing insulating layer (TIL2) in the direction in which light is emitted from the display panel (DP).

[0199] The inclined surface (IS) is depicted as a straight line in cross-section, but is not limited thereto. The inclined surface (IS) may be curved in cross-section and is not limited to any single embodiment.

[0200] The third sensing insulating layer (TIL3-A) can define a first cover opening (OP-H1). The width of the first cover opening (OP-H1) can be defined as the minimum width between adjacent inclined surfaces (IS).

[0201] During the transition from the first mode to the second mode, as the volume of the light-blocking pattern (BM) varies, the volume of the third sensing insulating layer (TIL3-A) can also be varied simultaneously. Accordingly, the width of the first cover opening (OP-H1) can be varied.

[0202] A cover layer (HRF) may be disposed on a second sensing insulating layer (TIL2). The cover layer (HRF) may cover the upper surface and the inclined surface (IS) of the third sensing insulating layer (TIL3-A). The area of ​​the second sensing insulating layer (TIL2) that overlaps with the first cover opening (OP-H1) may be in contact with the cover layer (HRF). The cover layer (HRF) may provide a flattening layer.

[0203] The cover layer (HRF) may be made of a material having a relatively high refractive index compared to the insulating layers placed below the cover layer (HRF). In this embodiment, the refractive index of the cover layer (HRF) may be 1.6 or higher and 1.8 or lower.

[0204] An anti-reflection member (ARL) can be placed on an input sensing panel (ISP). A phase delay layer (PRL) can be placed on a cover layer (HRF), and a polarization layer (POL) can be placed on the phase delay layer (PRL).

[0205] Although not shown in the drawing, supports (not shown) disposed above and below the polarization layer (POL) may be further included. The supports (not shown) support the polarization layer (POL) and can prevent contamination from the outside and shock from the outside.

[0206] A phase delay layer (PRL) can have optical anisotropy and can delay a component of incident light. A phase delay layer (PRL) can change the polarization state of light. For example, light passing through a phase delay layer (PRL) can change from a linearly polarized state to a circularly polarized state, or from a circularly polarized state to a linearly polarized state.

[0207] The phase delay layer (PRL) may include one or more of a polycarbonate (PC)-based resin, a cycloolefin polymer (COP)-based resin, an acrylic-based resin, and a cellulose-based resin. However, the present invention is not particularly limited to the material of the phase delay layer (PRL), and the phase delay layer (PRL) may include a liquid crystal.

[0208] The polarization layer (POL) is not shown but has a transmission axis (not shown) and an absorption axis (not shown) intersecting the transmission axis (not shown). In this embodiment, the transmission axis (not shown) and the absorption axis (not shown) may be perpendicular.

[0209] Accordingly, one component of the external light incident on the polarization layer (POL) may be absorbed or reflected at an absorption axis (not shown) and may not pass through the polarization layer (POL). A component of the external light incident on the polarization layer (POL) that is perpendicular to the aforementioned component may pass through the polarization layer (POL). That is, the polarization layer (POL) can linearly polarize the external light.

[0210] The polarization layer (POL) may be composed of a polymer resin stretched in a specific direction. However, it is not limited thereto, and the polarization layer (POL) may be a wire grid polarizer.

[0211] Consequently, external light incident on the polarization layer (POL) is linearly polarized and incident on the phase delay layer (PRL), and can be circularly polarized as it passes through the phase delay layer (PRL). The circularly polarized external light can be reflected by the display module (DM), and the polarization direction of the external light can be changed.

[0212] The reflected light, with its polarization direction changed, is incident again on the phase delay layer (PRL), and the phase of one component can be delayed by the phase delay layer (PRL). Accordingly, it can change from a circularly polarized state to a linearly polarized state. The linear polarization direction of the reflected light can be parallel to the absorption axis of the polarization layer (POL), and the linearly polarized reflected light can be absorbed by the polarization layer (POL).

[0213] Accordingly, the anti-reflection member (ARL) serves to prevent external light incident on the display device (EA-A) from the outside from being reflected by the display module (DM) and becoming visible to the user.

[0214] A window member (WM) may be placed on an anti-reflective member (ARL). The window member (WM) and the anti-reflective member (ARL) may be bonded together by an adhesive layer (AL). However, the adhesive layer (AL) may be omitted.

[0216] In FIG. 7b, a configuration that changes as the volumes of the piezoelectric pattern (PP) and the light-blocking pattern (BM) vary in the second mode is described, and a description of a configuration that remains the same as FIG. 7a is omitted.

[0217] According to the present invention, as the volume of the light-blocking pattern (BM) increases overall during the transition from the first mode to the second mode, the volume of the third sensing insulating layer (TIL3-A) can also increase overall. Accordingly, the width of the second cover opening (OP-H2) can be narrower than the width of the first cover opening (OP-H1).

[0218] In the present invention, the area of ​​the second light-emitting region (PXA-2) may be reduced compared to the area of ​​the first light-emitting region (PXA-1). Accordingly, as the light provided to the second light-emitting region (PXA-2) passes through a narrower light-emitting region than the light provided to the first light-emitting region (PXA-1), it may be provided to the user with a relatively narrow viewing angle in the second mode.

[0219] According to the present invention, by increasing or decreasing the viewing angle according to the user's needs, a display device with enhanced privacy protection can be provided by blocking the viewing angle of a third party looking from the side.

[0221] Although the present invention has been described above with reference to preferred embodiments, those skilled in the art or those with ordinary knowledge in the art will understand that various modifications and changes can be made to the invention without departing from the spirit and technical scope of the invention as described in the claims set forth below.

[0222] Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be determined by the claims. Explanation of the symbols

[0223] EA: Display device DM: Display Module DP: Display Panel ISP: Input Detection Panel FL: Functional layer TIL1: First sensing insulation layer TML1: First Challenge Patterns TIL2: Second sensing insulation layer TML2: Second Challenge Patterns TIL3: Third sensing insulation layer PP: Piezoelectric pattern BM: Shading pattern

Claims

Claim 1 A display device comprising: a display panel including a pixel that provides light; and an input sensing panel that detects an external input, wherein the input sensing panel comprises: a first sensing insulating layer disposed on the display panel; first conductive patterns disposed on the first sensing insulating layer; a second sensing insulating layer disposed on the first sensing insulating layer and covering the first conductive patterns; second conductive patterns disposed on the second sensing insulating layer; a piezoelectric pattern in full contact with the upper surface and side surfaces of each of the second conductive patterns; a light-blocking pattern covering the piezoelectric pattern and defining a transmission opening that transmits the light; and a third sensing insulating layer disposed on the second sensing insulating layer and covering the light-blocking pattern, wherein a first voltage is applied to the second conductive patterns in a first mode, and a second voltage different from the first voltage is applied to the second conductive patterns in a second mode. Claim 2 A display device according to claim 1, wherein the transparent opening has a first width in one direction in the first mode and a second width smaller than the first width in the one direction in the second mode. Claim 3 In claim 2, the display panel comprises: a base layer; a circuit element layer including a transistor disposed on the base layer; a display element layer including a first electrode connected to the transistor, a second electrode disposed on the first electrode, a light-emitting layer disposed between the first electrode and the second electrode, and a pixel defining film having a display opening defined that exposes at least a portion of the first electrode; and an encapsulation layer covering the display element layer, wherein the first sensing insulating layer is disposed directly on the encapsulation layer. Claim 4 A display device according to claim 3, wherein the piezoelectric pattern has a relatively larger volume in the second mode than in the first mode. Claim 5 A display device according to claim 3, wherein the side of the light-blocking pattern defines the boundary of the light-emitting area, and the light-emitting area has a narrower area in the second mode than in the first mode. Claim 6 A display device according to claim 5, wherein, during conversion from the first mode to the second mode, the light-blocking pattern protrudes in a direction toward the light-emitting region, and the width of the light-blocking pattern protruding during conversion from the first mode to the second mode is 2 micrometers or more and 5 micrometers or less. Claim 7 A display device according to claim 1, wherein the light-blocking pattern comprises a light-absorbing material. Claim 8 A display device according to claim 5, further comprising: a color filter layer disposed on the input sensing panel and overlapping with the light-emitting region; and a window disposed on the color filter layer. Claim 9 A display device according to claim 5, wherein the input sensing panel further comprises a cover layer disposed on the third sensing insulating layer, the third sensing insulating layer defines a cover opening that exposes at least a portion of the second sensing insulating layer and overlaps with at least a portion of the light-emitting region, and the cover layer contacts the second sensing insulating layer in the region overlapping with the cover opening. Claim 10 A display device according to claim 1, wherein the second challenge patterns include a plurality of mesh lines. Claim 11 A display device comprising: a display panel including a pixel that provides light; and an input sensing panel that detects an external input, wherein the input sensing panel comprises: a plurality of sensing insulating layers; conductive patterns disposed between the sensing insulating layers; a piezoelectric pattern that is in full contact with the upper surface and side surface of each of the conductive patterns; and a light-blocking pattern that covers the piezoelectric pattern and defines a transmitting opening that transmits the light, wherein the transmitting opening has a first width in one direction in a first mode and a second width in one direction that is smaller than the first width in a second mode that is subjected to a voltage different from that of the first mode. Claim 12 A display device according to claim 11, wherein the display panel comprises: a base layer; a circuit element layer including a transistor disposed on the base layer; a display element layer including a first electrode connected to the transistor, a second electrode disposed on the first electrode, a light-emitting layer disposed between the first electrode and the second electrode, and a pixel defining film having a display opening that exposes at least a portion of the first electrode; and an encapsulation layer covering the display element layer, wherein the sensing insulating layer disposed closest to the display panel among the sensing insulating layers is disposed directly on the encapsulation layer. Claim 13 A display device according to claim 12, wherein the piezoelectric pattern has a relatively larger volume in the second mode than in the first mode. Claim 14 A display device according to claim 13, wherein the side of the light-blocking pattern defines the boundary of the light-emitting area, and the light-emitting area has a narrower area in the second mode than in the first mode. Claim 15 A display device according to claim 14, wherein, during conversion from the first mode to the second mode, the light-blocking pattern protrudes in a direction toward the light-emitting area, and the width of the light-blocking pattern protruding during conversion from the first mode to the second mode is 2 micrometers or more and 5 micrometers or less. Claim 16 A display device according to claim 14, further comprising: a color filter layer disposed on the input sensing panel and overlapping with the light-emitting region; and a window disposed on the color filter layer. Claim 17 A display device according to claim 14, wherein the input sensing panel further comprises a cover layer covering at least a portion of the sensing insulating layers, and the sensing insulating layer located at the top of the sensing insulating layers is configured in a trapezoidal shape in cross-section and defines a cover opening that overlaps with at least a portion of the light-emitting region. Claim 18 An input sensing panel comprising: a first sensing insulating layer; first conductive patterns disposed on the first sensing insulating layer; a second sensing insulating layer disposed on the first sensing insulating layer and covering the first conductive patterns; second conductive patterns disposed on the second sensing insulating layer; a piezoelectric pattern in full contact with the upper surface and side surfaces of each of the second conductive patterns; a light-blocking pattern covering the piezoelectric pattern and defining a transparent opening that exposes at least a portion of the second sensing insulating layer; and a third sensing insulating layer disposed on the second sensing insulating layer and covering the light-blocking pattern, wherein a first voltage is applied to the second conductive patterns in a first mode, and a second voltage different from the first voltage is applied to the second conductive patterns in a second mode. Claim 19 An input sensing panel according to claim 18, wherein the transmission opening has a first width in one direction in the first mode and a second width smaller than the first width in the one direction in the second mode. Claim 20 In claim 19, the input sensing panel is characterized in that the volume of the piezoelectric pattern varies when converting from the first mode to the second mode.

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