Memory device

Abstract

A memory device contains a first memory array configuration, a second memory array configuration, and a central connection configuration located between the first and the second memory array configuration. The memory device includes a stack structure having a plurality of insulating layers and a plurality of conductive layers stacked alternately in above configurations. A plurality of ground select line structures is included in the plurality of conductive layers in a lower portion of the stack structure. The stack structure in the central connection configuration further includes a first connect structure, a second connect structure, and a bridge structure. The first and the second connect structures are respectively connected with the stack structure of the first and the second memory array configuration, wherein the second connect structure and the first connect structure are arranged in a staggered pattern. The bridge structure connects the first and the second connect structure.

Description

[Technical Field]

[0001] This invention relates to a semiconductor element, and more particularly to a memory device. [Previous Technology]

[0002] Non-volatile memory elements have become a widely used type of memory element in personal computers and other electronic devices because they have the advantage that stored data will not be lost after power is turned off.

[0003] Currently, the most commonly used flash memory arrays in the industry include NOR flash memory and NAND flash memory. Because NAND flash memory's structure involves connecting memory cells in series, its density and area utilization are better than NOR flash memory, and it has been widely used in various electronic products. Furthermore, to further improve the density of memory components, a three-dimensional NAND flash memory has been developed. However, many challenges related to three-dimensional NAND flash memory still exist. [Summary of the Invention]

[0004] The present invention provides a memory device that can reduce word line (WL) RC delay in a memory array structure.

[0005] In one embodiment of the present invention, a memory device includes a first memory array structure, a second memory array structure, and a central connection structure located between the first and second memory array structures. The memory device includes a stacked structure. This stacked structure includes multiple insulating layers and multiple conductor layers alternately stacked in the first memory array structure, the second memory array structure, and the central connection structure, wherein multiple ground select line structures (GSLs) are contained in the conductor layers in the lower part of the stacked structure in the first memory array structure, the second memory array structure, and the central connection structure. The stacked structure of the central connection structure further includes a first connection structure, a second connection structure, and a bridging structure. The first connection structure is connected to the stacked structure of the first memory array structure, and the second connection structure is connected to the stacked structure of the second memory array structure, wherein the second connection structure and the first connection structure are alternately arranged. The bridging structure connects the first connection structure and the second connection structure.

[0006] In one embodiment of the present invention, a memory device includes a plurality of zones, each zone being disposed between opposing first and second partition walls and separated from adjacent zones. The memory device includes a stacked structure. The stacked structure includes a plurality of insulating layers and a plurality of conductive layers alternately stacked in each zone, wherein the stacked structure at a first end of the zone includes a first memory array structure, the stacked structure at a second end of the zone includes a second memory array structure, and a plurality of ground select line structures are located at the bottom of the stacked structure. The ground select line structures extend from the first end of the zone to the second end of the zone. Each zone also includes a central connection structure disposed between the first memory array structure and the second memory array structure. The stacked structure of the central connection structure includes a first connection structure, a second connection structure, and a bridging structure. The first connection structure is disposed along the first partition wall to connect the first memory array structure. The second connection structure is disposed along the second partition wall to connect the second memory array structure. The bridging structure connects the first connection structure and the second connection structure.

[0007] Based on the above, the central connection structure of the present invention is a bridge structure that connects two connection structures (such as WL structure) that are respectively connected to the first and second memory array structures. Therefore, the WL of the first and second memory array structures at both ends can be connected with the same distance conduction path to reduce the WL RC delay in the memory array structure.

Implementation Method

[0008] Figure 1 is a perspective view of a memory device according to an embodiment of the present invention.

[0009] Referring to Figure 1, the memory device includes a first memory array structure MA1, a second memory array structure MA2, and a central connection structure CC located between the first memory array structure MA1 and the second memory array structure MA2. The memory device is constructed from a stacked structure 100, which includes multiple insulating layers and multiple conductive layers alternately stacked in the first memory array structure MA1, the second memory array structure MA2, and the central connection structure CC. Detailed construction of the stacked structure 100, the first memory array structure MA1, and the second memory array structure MA2 will be described below. In the lower LP of the stacked structure 100 in the first memory array structure MA1, the second memory array structure MA2, and the central connection structure CC, there are multiple ground selection line structures GSL (i.e., the conductive layers of the lower LP), and only one layer of conductive layers is shown in the stacked structure 100 in Figure 1, while insulating layers (not shown) are interposed between the conductive layers. The stacked structure 100 of the central connection structure CC also includes a first connection structure C1, a second connection structure C2, and a bridging structure BS. The first connection structure C1 is connected to the stacked structure 100 of the first memory array structure MA1, and the second connection structure C2 is connected to the stacked structure 100 of the second memory array structure MA2, wherein the second connection structure C2 and the first connection structure C1 are alternately configured. The bridging structure BS connects the first connection structure C1 and the second connection structure C2.

[0010] In Figure 1, the first connection structure C1 extends in the first direction D1 and continuously extends from the first memory array structure MA1 to the bridging structure BS; the second connection structure C2 also extends in the first direction D1 and continuously extends from the second memory array structure MA2 to the bridging structure BS. Accordingly, the bridging structure BS extends in the second direction D2, and the second direction D2 is different from the first direction D1, for example, the second direction D2 is perpendicular to the first direction D1 or there is an angle between the second direction D2 and the first direction D1. The memory device includes multiple stepped portions, for example, each ground selection line structure GSL in the central connection structure CC has multiple stepped portions SC extending in the first direction D1. The multiple stepped portions SC are separated from each other in the first direction D1.

[0011] The memory device of this embodiment also includes multiple ground selection line contact windows GC, which land on the stepped portion SC to electrically connect to the ground selection line structures GSL respectively. For example, the multiple ground selection line structures GSL in this embodiment include a first ground selection line structure GSL1, a second ground selection line structure GSL2, and a third ground selection line structure GSL3, wherein the second ground selection line structure GSL2 is located between the first ground selection line structure GSL1 and the third ground selection line structure GSL3. The first ground selection line structure GSL1, the second ground selection line structure GSL2, and the third ground selection line structure GSL3 can be isolated from each other by a bottom wall (not shown). Figure 1 shows four stepped sections SC, located respectively in the first ground selection line structure GSL1 at one end of the first connection structure C1 relative to the first memory array structure MA1, the third ground selection line structure GSL3 at one end of the second connection structure C2 relative to the second memory array structure MA2, the second ground selection line structures GSL2 and GSL3 adjacent to the first memory array structure MA1, and the second ground selection line structure GSL2 and the first ground selection line structure GSL1 adjacent to the second memory array structure MA2. Therefore, the ground selection line contact window GC can be coupled to all ground selection line structures GSL of the first memory array structure MA1 and the second memory array structure MA2 through the stepped sections SC.

[0012] In some embodiments, the first connection structure C1 is disposed directly above the first ground select line structure GSL1 and is connected to multiple conductor layers (such as word lines (WL)) above the lower LP in the stacked structure 100 of the first memory array structure MA1. In some embodiments, the second connection structure C2 is disposed directly above the third ground select line structure GSL3 and is connected to multiple conductor layers above the lower LP in the stacked structure 100 of the second memory array structure MA2. In some embodiments, the bridging structure BS is disposed directly above the second ground select line structure GSL2 and is connected to the first connection structure C1 and the second connection structure C2. Since the first connection structure C1 and the second connection structure C2 are connected to the first memory array structure MA1 and the second memory array structure MA2 at approximately the same distance, the WL RC delay in the first memory array structure MA1 and the second memory array structure MA2 can be reduced.

[0013] FIG2 is a top view of a memory device according to an embodiment of the present invention. FIG3 is a cross-sectional view along line A-A' of FIG2. FIG4 is a cross-sectional view along line B-B' of FIG2. FIG5 is a cross-sectional view along line C-C' of FIG2.

[0014] Referring to Figures 2 and 3, the memory device includes multiple zones 200, each zone 200 being disposed between opposing first slits 202 and second slits 204 and separated from adjacent zones 200. Figure 2 shows three zones 200, and the configuration of adjacent zones 200 is mirrored, so adjacent zones 200 can share the same second slit 204 (or first slit 202), and so on. Moreover, the number of zones 200 can be increased or decreased as needed, and is not limited thereto. The memory device includes a stack structure 100. The stack structure 100 includes multiple insulating layers 102 and multiple conductive layers 104 alternately stacked in each zone 200, wherein the stack structure 100 at the first end 200a of zone 200 includes a first memory array structure 206, and the stack structure 100 at the second end 200b of zone 200 includes a second memory array structure 208.

[0015] In Figure 3, components are located below the stacked structure 100, so the memory device in this embodiment belongs to a CUA (CMOS-Under-Array) structure, but the present invention is not limited thereto. In some embodiments, a component layer 20 is formed on the substrate 10. The component layer 20 may include active components or passive components. Active components are, for example, transistors, diodes, etc. Passive components are, for example, capacitors, inductors, etc. The transistor may be an N-type metal-oxide-semiconductor (NMOS) transistor, a P-type metal-oxide-semiconductor (PMOS) transistor, or a complementary metal-oxide-semiconductor (CMOS) device. A metal interconnect structure 30 is present on the component layer 20. The metal interconnect structure 30 may include multiple dielectric layers 32 and metal interconnects 34 (including plugs, wires, etc.) formed in the multiple dielectric layers 32. The metal interconnects 34 may be connected to the component layer 20. A source line plate SLP is present on the metal interconnect structure 30. The source line plate SLP may include multiple insulating layers 302 and multiple conductor layers 304 and conductor layers 306. In one embodiment, the insulating layer 302 is made of silicon oxide. The conductor layers 304 and 306 are made of doped polycrystalline silicon. The number of insulating layers 302 and conductor layers 304 and 306 is not limited to those shown in the figures. Furthermore, a conductor post 308 may be present in the source line plate SLP. The conductor post 308 has a low resistance. In one embodiment, the conductor layer 304 is doped polycrystalline silicon, and the conductor post 308 is a metal, such as tungsten, titanium nitride, tantalum, or a combination thereof, with a resistance lower than that of the conductor layer 304 in the source line plate SLP. The conductor post 308 can be electrically connected to the substrate 10 via a metal interconnect 34 in the metal interconnect structure 30, thereby grounding. Therefore, the conductor post 308 can serve as a discharge path.

[0016] Referring again to FIG3, a stacked structure 100 is formed on the source line plate SLP. The number of insulating layers 102 and conductor layers 104 in the stacked structure 100 is not limited to those shown in the figure. In one embodiment, the material of the insulating layer 102 includes silicon oxide. The conductor layer 104 includes, for example, a barrier layer and a metal layer. In one embodiment, the material of the aforementioned barrier layer includes titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or a combination thereof, and the material of the aforementioned metal layer includes tungsten (W). In some embodiments, the positions of each conductor layer 104 were originally polycrystalline silicon, and a metal material layer was formed through a gate substitution process. A first memory array and a second memory array are formed in the middle of the stacked structure 100 of the first memory array structure 206 and the second memory array structure 208. Each first memory array and the second memory array include multiple word lines WL, vertical channel pillars consisting of channel layers 310, insulating pillars 312, and conductor plugs 314, and charge storage structures 316 surrounding each vertical channel pillar to form multiple memory cells arranged in a three-dimensional configuration. The word lines WL are the conductor layers 104 in the middle of the stacked structure 100. In some embodiments, the channel layers 310 are made of polysilicon, the conductor plugs 314 are made of polysilicon, and the insulating pillars 312 are made of silicon oxide, but are not limited thereto. The charge storage structures 316 vertically surround the outer surface of the aforementioned vertical channel pillars. In some embodiments, the charge storage structures 316 are oxide / nitride / oxide (ONO) composite layers, but are not limited thereto. The upper part of the stacked structure 100 also includes string selection lines SSL. The string selection lines SSL are the conductor layers 104 in the upper part of the stacked structure 100. The memory device also includes a metal interconnect structure 40 disposed above the stacked structure 100. The metal interconnect structure 40 may include multiple dielectric layers 42, multiple plugs 44, and multiple conductors 46. The dielectric layers 42 separate each conductor 46 from the underlying first memory array structure 206 and second memory array structure 208. The conductors 46 can be connected by plugs 44, and the conductors 46 can be coupled to the ground select line contact window GC, the serial select line contact window SSLC, and the word line contact window WLC, respectively. Although the word line contact window WLC is not shown in Figure 3, its specific location can be obtained from the upper view (Figure 2), i.e., the part marked by the arrow in Figure 3. That is to say, the middle and upper parts of the stacked structure 100 also have multiple stepped sections, providing areas where the word line contact window WLC or the serial select line contact window SSLC is located. The conductors 46 coupled to the conductor plugs 314 of the vertical channel pillars can be used as bit lines (or local bit lines) BL.

[0017] Referring again to Figure 2, each block 200 has multiple ground selection line structures GSL; for example, in this embodiment, the ground selection line structure GSL includes a first ground selection line structure GSL1, a second ground selection line structure GSL2, and a third ground selection line structure GSL3, wherein the second ground selection line structure GSL2 is located between the first ground selection line structure GSL1 and the third ground selection line structure GSL3. The first ground selection line structure GSL1, the second ground selection line structure GSL2, and the third ground selection line structure GSL3 can be isolated from each other by a bottom wall GLC. The ground selection line structure GSL extends from the first end 200a of the block 200 to the second end 200b of the block 200. Each block 200 also includes a central connection structure CC. The central connection structure CC is disposed between the first memory array structure 206 and the second memory array structure 208. The central connection structure CC includes a first connection structure C1, a second connection structure C2, and a bridge structure BS. The first connection structure C1 is disposed along the first partition wall 202 to connect the first memory array structure 206. The second connection structure C2 is disposed along the second partition wall 204 to connect the second memory array structure 208. The bridging structure BS connects the first connection structure C1 and the second connection structure C2. The positional relationship between the first connection structure C1, the second connection structure C2 and the bridging structure BS is similar to that in the previous embodiment, and will not be described again. Block 200 also includes a string selection line cut (SLC), which can be located on top of the stacked structure (as shown in the stacked structure 100 in Figure 3) to separate the upper conductor layers of the stacked structure. The string selection line cut (SLC) is made of an insulating material, such as silicon oxide. Therefore, two string selection lines (SSL) are paired with a ground selection line structure (GSL) separated by the cut (SLC). This design allows control of different sub-blocks via the string selection lines (SSL) and avoids read interference (WL).

[0018] For example, in Figure 3, the serial select line SSL and the ground select line structure GSL3 are electrically coupled to opposite ends of the vertical channel VC. The serial select line SSL is electrically connected between the bit line BL and the underlying word line WL, and the intersection of the serial select line SSL and the vertical channel VC can be defined as the serial select transistor. As for the third ground select line structure GSL3, it is electrically connected between the source line SLP and the vertical channel VC, and the intersection of the third ground select line structure GSL3 and the word line WL can be defined as the ground select transistor. When the memory device shown in Figure 3 is in a read operation, for example, a read operation is performed on a selected memory cell in the first memory array structure 206, a voltage is applied to the serial select line SSL electrically connected to the selected memory cell to turn on the serial select transistor electrically connected to the serial select line SSL, and a voltage is applied to the third ground select line structure GSL3 electrically connected to the selected memory cell to turn on the ground select transistor electrically connected to the third ground select line structure GSL3. Because of the design of the two string select lines (SSL) paired with the ground select line (GSL) in Figure 2, the unselected memory cells can remain off during this read operation. No capacitance is generated in the channel layer 310 electrically connecting these unselected memory cells, thus preventing issues such as increased word line load and read interference. In one embodiment, the channel layer 310 in the unselected memory cells can be electrically floating.

[0019] In Figure 3, the third ground selection line structure GSL3 is located at the bottom of the stacked structure 100, and has a second connection structure C2 and a partial bridging structure BS above it. That is, the stacked structure 100 with the central connection structure CC includes the second connection structure C2 and the bridging structure BS. The word lines WL of each layer in the second memory array structure 208 are on the same conductor layer 104 as the second connection structure C2 and the bridging structure BS, respectively. Therefore, the second connection structure C2 is directly connected to the second memory array structure 208, and the bridging structure BS is directly connected to the second memory array structure 208 via the second connection structure C2. The second connection structure C2 is located directly above the third ground selection line structure GSL3.

[0020] In Figure 4, the first ground selection line structure GSL1 is located at the bottom of the stacked structure 100, and has a first connection structure C1 and a partial bridging structure BS above it. That is, the stacked structure 100 with the central connection structure CC includes the first connection structure C1 and the bridging structure BS. The word lines WL of each layer in the first memory array structure 206 are on the same conductor layer 104 as the first connection structure C1 and the bridging structure BS, respectively. Therefore, the first connection structure C1 is directly connected to the first memory array structure 206, and the bridging structure BS is directly connected to the first memory array structure 206 via the first connection structure C1. The first connection structure C1 is located directly above the first ground selection line structure GSL1.

[0021] Referring to Figures 2 and 5, the first ground selection line structure GSL1, the second ground selection line structure GSL2, and the third ground selection line structure GSL3 are located at the lower LP of the stacked structure 100. Furthermore, the number of layers of the first ground selection line structure GSL1, the second ground selection line structure GSL2, and the third ground selection line structure GSL3 can be increased or decreased as needed, and is not limited to the three layers shown in the figures. Between the ground selection line structures GSL, there is a bottom wall GLC, wherein the bottom wall GLC is an insulating material, such as silicon oxide, SiN, SiON, SiC, SiCN, Al₂O₃, or a high dielectric constant material, such as HfO. In addition, the bottom wall GLC can also be used to cut dummy character lines (not shown). Each block 200 is disposed between opposing first partition walls 202 and second partition walls 204, and discontinuous partition walls 210 can be disposed between the first partition walls 202 and the second partition walls 204. Discontinuous partition wall 210 extends from the first end 200a of block 200 to the second end 200b of block 200 and has at least one partition wall opening SO, such as one or more. A bridging structure BS passes through the partition wall opening SO to achieve an electrical connection; therefore, the bridging structure BS passes directly above the second ground selection line structure GSL2 through the partition wall opening SO and connects the first connection structure C1 and the second connection structure C2. In some embodiments, the first partition wall 202, the second partition wall 204, and the discontinuous partition wall 210 are all made of insulating material, such as silicon oxide. In other embodiments, the first partition wall 202, the second partition wall 204, and the discontinuous partition wall 210, in addition to including insulating material, also include a conductive material covered by the insulating material, such as polycrystalline silicon or tungsten.

[0022] In Figure 2, the memory device also includes multiple stepped portions SC located in each ground selection line structure GSL in the central connection structure CC, and multiple ground selection line contact windows GC can be provided landing on the stepped portions SC to electrically connect the multiple ground selection line structures GSL respectively. In this embodiment, the aforementioned multiple stepped portions SC are separated from each other in a first direction D1, which is the extension direction of the first partition wall 202.

[0023] In FIG. 3, the third ground selection line structure GSL3 extending from one end of the second connection structure C2 relative to the second memory array structure 208 has two separate stepped portions SC. Ground selection line contact windows GC land on these stepped portions SC respectively to electrically connect the plurality of third ground selection line structures GSL3 of the second memory array structure 208 and the plurality of third ground selection line structures GSL3 of the first memory array structure 206 respectively. Moreover, the stepped portions SC may be covered by a dielectric layer 103 on top of the stacked structure 100. The dielectric layer 103 may be a single layer or multiple layers. In some embodiments, the dielectric layer 103 includes silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

[0024] In Figure 4, the first ground selection line structure GSL1 extending from one end relative to the first connection structure C1 of the first memory array structure 206 also has two separate stepped portions SC. The ground selection line contact window GC lands on these stepped portions SC respectively to electrically connect the plurality of first ground selection line structures GSL1 of the first memory array structure 206 and the plurality of first ground selection line structures GSL1 of the second memory array structure 208 respectively.

[0025] In addition to the CUA structure, the present invention can also be applied to the CBA (CMOS directly bonded to array) structure, as shown in Figure 6. The same component symbols as those in Figure 3 are used in Figure 6 to represent the same or similar parts and components, and the relevant content of the same or similar parts and components can also refer to the content of the previous embodiment, which will not be repeated here.

[0026] Referring to Figure 6, a CMOS wafer 600 is formed by a substrate 10, a component layer 20, and a metal interconnect structure 30. A redistribution layer 602 is formed on the metal interconnect structure 30, wherein the redistribution layer 602 includes a dielectric layer 606a and a conductor layer 608a. The stacked structure 100 is formed in the array wafer 610. For details, refer to the stacked structure 100 in Figure 3. The stacked structure 100 in this figure is a flip of the structure in Figure 3, so the step portion SC is on top, and the second connection structure C2 and the bridging structure BS are below the step portion SC. The array wafer 610 also has a redistribution layer 604 connected to the CMOS wafer 600, wherein the redistribution layer 604 includes a dielectric layer 606b and a conductor layer 608b. The CMOS wafer 600 can be directly bonded to the array wafer 610 by hybrid bonding between the redistribution layers 602 and 604. Furthermore, a metal interconnect structure 40 can be formed on the back side of the substrate 612 of the array chip 610 to form a CBA structure.

[0027] In summary, a memory device according to one embodiment of the present invention can connect the word lines of the first and second memory array structures at both ends with the same or similar conduction paths, thus reducing the WL RC delay in the memory array structure. [Simplified Explanation of the Diagram]

[0028] FIG1 is a perspective view of a memory device according to an embodiment of the present invention. FIG2 is a top view of a memory device according to an embodiment of the present invention. FIG3 is a cross-sectional view along line A-A' of FIG2. FIG4 is a cross-sectional view along line B-B' of FIG2. FIG5 is a cross-sectional view along line C-C' of FIG2. FIG6 is a cross-sectional view of a memory device according to an embodiment of the present invention.

Claims

1. A memory device, comprising a first memory array structure, a second memory array structure, and a central connecting structure located between the first memory array structure and the second memory array structure, the memory device comprising: A stacked structure includes multiple insulating layers and multiple conductor layers alternately stacked in a first memory array structure, a second memory array structure, and a central connection structure. Multiple ground select line structures are included in the multiple conductor layers in the lower portion of the stacked structure in the first memory array structure, the second memory array structure, and the central connection structure. The stacked structure in the central connection structure further includes: a first connection structure connected to the stacked structure of the first memory array structure; a second connection structure connected to the stacked structure of the second memory array structure, wherein the second connection structure and the first connection structure are staggered in a first direction; and a bridging structure connecting the first connection structure and the second connection structure, wherein the first direction is perpendicular to the direction in which the multiple insulating layers and the multiple conductor layers are alternately stacked.

2. The memory device as claimed in claim 1, wherein the first connection structure extends in the first direction and continuously extends from the first memory array structure to the bridging structure, and the second connection structure extends in the first direction and continuously extends from the second memory array structure to the bridging structure.

3. The memory device as claimed in claim 2, wherein the bridging structure extends in a second direction, and the second direction is different from the first direction.

4. The memory device as claimed in claim 2 further includes a plurality of stepped portions located in each of the plurality of ground select line structures in the central connection structure, and the plurality of stepped portions extending in the first direction.

5. The memory device as claimed in claim 1, wherein the plurality of ground selection line structures include a first ground selection line structure, a second ground selection line structure and a third ground selection line structure, wherein the second ground selection line structure is located between the first ground selection line structure and the third ground selection line structure, and the bridging structure is disposed directly above the second ground selection line structure.

6. A memory device comprising a plurality of blocks, each block being disposed between opposing first and second partition walls and separated from adjacent blocks, the memory device comprising: A stacked structure includes multiple insulating layers and multiple conductive layers alternately stacked in each block, wherein the stacked structure at a first end of the block includes a first memory array structure; the stacked structure at a second end of the block includes a second memory array structure; and multiple ground select line structures located at the bottom of the stacked structure, the multiple ground select line structures extending from the first end of the block to the second end of the block, wherein each block further includes a central connection structure disposed between the first memory array structure and the second memory array structure, wherein the stacked structure in the central connection structure includes: a first connection structure disposed along the first partition wall to connect the first memory array structure; a second connection structure disposed along the second partition wall to connect the second memory array structure; and a bridging structure connecting the first connection structure and the second connection structure, wherein the second connection structure and the first connection structure are staggered in a first direction, and the first direction is perpendicular to the direction in which the multiple insulating layers and the multiple conductive layers are alternately stacked.

7. The memory device as claimed in claim 6 further includes a discontinuous partition wall disposed between the first partition wall and the second partition wall, wherein the discontinuous partition wall extends from the first end of the block to the second end of the block.

8. The memory device as claimed in claim 7, wherein the discontinuous partition wall has at least one partition wall opening, and the bridging structure passes through the at least one partition wall opening.

9. The memory device as claimed in claim 6 further includes a plurality of stepped portions located in each of the plurality of ground select line structures in the central connection structure.

10. The memory device as claimed in claim 6, wherein the plurality of ground selection line structures include a first ground selection line structure, a second ground selection line structure and a third ground selection line structure, wherein the second ground selection line structure is located between the first ground selection line structure and the third ground selection line structure, and the bridging structure is disposed directly above the second ground selection line structure.

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