Apparatus and circuit for processing carrier aggregation

The CA circuit and apparatus address frequency offset challenges by using a reference clock and PLL units to stabilize carrier frequencies, enhancing performance in LTE systems with multiple CCs.

USRE50933E1Active Publication Date: 2026-06-23SAMSUNG ELECTRONICS CO LTD
View PDF 24 Cites 0 Cited by

Patent Information

Authority / Receiving Office
US · United States
Patent Type
Patents(United States)
Current Assignee / Owner
SAMSUNG ELECTRONICS CO LTD
Filing Date
2024-01-16
Publication Date
2026-06-23

AI Technical Summary

Technical Problem

Current CA schemes in LTE mobile communication systems face challenges in properly compensating frequency offsets when signals are transmitted/received at different timing points from different locations with different frequency offsets, leading to decreased transmission/reception performance, especially in inter-band or intra-band non-contiguous bandwidth scenarios.

Method used

A circuit and apparatus for Carrier Aggregation (CA) that utilizes a reference clock generator and Phase Lock Loop (PLL) units to estimate and compensate frequency offsets for each Component Carrier (CC), using a reference frequency offset to generate reception and transmission carrier frequencies.

Benefits of technology

The solution effectively compensates for frequency offsets across multiple CCs, improving transmission/reception performance by stabilizing carrier frequencies and enhancing channel quality.

✦ Generated by Eureka AI based on patent content.

Smart Images

  • Figure USRE050933-D00000_ABST
    Figure USRE050933-D00000_ABST
Patent Text Reader

Abstract

A circuit for processing Carrier Aggregation (CA) is provided. The circuit includes a plurality of Component Carrier (CC) processors, each CC processor configured to estimate a frequency offset for a related CC and to compensate the estimated frequency offset, a reference clock generator configured to generate a reference clock using a reference frequency offset as one of frequency offsets output from the plurality of CC processors, a plurality of reception Phase Lock Loop (PLL) units, each reception PLL unit configured to generate a reception carrier frequency for the related CC corresponding to the reference clock, and a plurality of transmission PLL units, each transmission PLL unit configured to generate a transmission carrier frequency for the related CC corresponding to the reference clock.
Need to check novelty before this filing date? Find Prior Art