Shift register, gate driving circuit and display apparatus

Abstract

A shift register, a gate driving circuit and a display apparatus. The shift register comprises a first control module (10), a first output module (20), a second output module (30), a second control module (40), a third control module (50), a fourth control module (60), a fifth control module (70), a sixth control module (80), and an energy storage module (90). The first output module (20), under the voltage control of a second node (N2), provides a first power supply signal of a first power supply signal end (VGH) to a first output signal end (OUT1). The second output module (30), under the voltage control of a first node (N1), provides a second power supply signal of a second power supply signal end (VGL) to the first output signal end (OUT1). The first control module (10), the second control module (40), the third control module (50), the fourth control module (60), the fifth control module (70), the sixth control module (80) and the energy storage module (90) cooperate with each other to control the potentials of the first node (N1), the second node (N2), and a third node (N3).

Description

Shift register, gate drive circuit and display device

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on April 24, 2022, with application number 202210455783.7 and invention name “Shift register, gate drive circuit and display device”, the content of which should be understood as incorporated into this application by reference. Technical Field

[0002] The embodiments of the present disclosure relate to, but are not limited to, the field of display technology, and in particular to a shift register, a gate driving circuit, and a display device. Background Art

[0003] Gate Driver on Array (GOA) technology integrates thin-film transistor (TFT) gate switching circuits on the array substrate of a display panel to drive the display panel. This eliminates the wiring space in the bonding and fan-out areas of the integrated circuit (IC), thereby achieving a narrow bezel.

[0004] Oxide thin-film transistors (TFTs) are gaining increasing attention due to their transparency, relatively simple manufacturing process, and low processing temperature. However, new GOA circuits need to be designed to accommodate the low carrier mobility of TFTs.

[0005] Summary of the Invention

[0006] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0007] An embodiment of the present disclosure provides a shift register, comprising: a first control module, a first output module, a second output module, a second control module, a third control module, a fourth control module, a fifth control module, a sixth control module, and an energy storage module;

[0008] a first control module connected to the first power signal terminal, the first input signal terminal, and the second node, and configured to provide the first power signal of the first power signal terminal to the second node under the control of the first input signal of the first input signal terminal;

[0009] a first output module connected to the second node, the first clock signal terminal and the first output signal terminal, and configured to provide the first clock signal of the first clock signal terminal to the first output signal terminal under the voltage control of the second node;

[0010] a second output module connected to the first node, the second power signal terminal and the first output signal terminal, and configured to provide the second power signal of the second power signal terminal to the first output signal terminal under the voltage control of the first node;

[0011] a second control module connected to the second power signal terminal, the second input signal terminal, the first clock signal terminal, and the third node, and configured to provide the second power signal from the second power signal terminal to the third node under the control of the second input signal from the second input signal terminal, and to provide the second power signal from the second power signal terminal to the third node under the control of the first clock signal from the first clock signal terminal;

[0012] a third control module connected to the third node, the second clock signal terminal and the first node, and configured to provide the second clock signal of the second clock signal terminal to the first node under voltage control of the third node;

[0013] a fourth control module connected to the third node, the second power signal terminal and the second node, and configured to provide the second power signal of the second power signal terminal to the second node under the voltage control of the third node;

[0014] a fifth control module connected to the first node, the second power signal terminal, and the second node, and configured to provide the second power signal of the second power signal terminal to the second node under voltage control of the first node;

[0015] a sixth control module connected to the second node, the second power signal terminal and the first node, and configured to provide the second power signal of the second power signal terminal to the first node under the voltage control of the second node;

[0016] The energy storage module includes a first capacitor, wherein two ends of the first capacitor are respectively connected to the third node and the second clock signal end.

[0017] An embodiment of the present disclosure also provides a gate drive circuit, comprising N cascaded shift registers SR(i); the first output signal terminal of the kth shift register SR(k) is connected to the first input signal terminal of the k+1th shift register SR(k+1); 1≤k≤N-1, N>1; at least one shift register SR(i) among the N shift registers adopts the above-mentioned shift register; 1≤i≤N.

[0018] An embodiment of the present disclosure further provides a display device, comprising the above-mentioned gate driving circuit.

[0019] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The accompanying drawings are used to provide an understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation to the technical solution of the present disclosure.

[0021] FIG1 is a schematic structural diagram of a shift register provided by an embodiment of the present disclosure;

[0022] FIG2 is a schematic diagram of an equivalent circuit of a shift register provided by an embodiment of the present disclosure;

[0023] FIG3 is a schematic diagram of an equivalent circuit of another shift register provided by an embodiment of the present disclosure (including a second capacitor and a third capacitor);

[0024] FIG4 is a schematic diagram of an equivalent circuit of another shift register provided by an embodiment of the present disclosure (including a tenth transistor);

[0025] FIG5 is a schematic diagram of an equivalent circuit of another shift register provided by an embodiment of the present disclosure (including a second output signal terminal);

[0026] FIG6 is a signal timing diagram of a shift register provided by an embodiment of the present disclosure;

[0027] FIG7 is a signal timing diagram of another shift register provided by an embodiment of the present disclosure;

[0028] FIG8 is a schematic diagram of a cascade structure of a gate drive circuit provided by an embodiment of the present disclosure;

[0029] FIG9 is a schematic diagram of a cascade structure of a gate driving circuit provided in an embodiment of the present disclosure (the first input signal and the second input signal are the same);

[0030] FIG10 is a schematic diagram of a cascade structure of a gate driving circuit provided in an embodiment of the present disclosure (the first input signal and the second input signal are different). DETAILED DESCRIPTION

[0031] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Note that the embodiments can be implemented in a variety of different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other.

[0032] In the drawings, the sizes of various components, layer thicknesses, or regions may be exaggerated for clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to these dimensions, and the shapes and sizes of the components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate idealized examples, and one embodiment of the present disclosure is not limited to the shapes or numerical values ​​shown in the drawings.

[0033] In this specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0034] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure.

[0035] In this specification, a transistor refers to a device consisting of at least three terminals: a gate, a drain, and a source. The source and drain of a transistor are symmetrical. However, the functions of the "source" and "drain" are sometimes reversed when using transistors with opposite polarities or when the direction of current changes during circuit operation. In the disclosed embodiments, one of the source and drain is referred to as the first electrode, the other is referred to as the second electrode, and the gate is referred to as the control electrode.

[0036] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0037] In the following examples, the driving transistor is described as an N-type thin film transistor, and the other transistors have the same or different types as the driving transistor according to the circuit design. Similarly, in other embodiments, the driving transistor can also be shown as a P-type thin film transistor. It can be understood by those skilled in the art that the technical solution of the present disclosure can also be implemented by changing the types of other transistors accordingly and inverting each driving signal and level signal (and / or performing other additional adaptive modifications).

[0038] The embodiment of the present disclosure provides a shift register. As shown in FIG1 , the shift register provided by the embodiment of the present disclosure includes: a first control module 10, a first output module 20, a second output module 30, a second control module 40, a third control module 50, a fourth control module 60, a fifth control module 70, a sixth control module 80 and an energy storage module 90;

[0039] a first control module connected to the first power signal terminal VGH, the first input signal terminal IN1 and the second node N2, and configured to provide the first power signal of the first power signal terminal to the second node under the control of the first input signal of the first input signal terminal;

[0040] a first output module connected to the second node N2, the first clock signal terminal CK1 and the first output signal terminal OUT1, and configured to provide the first clock signal of the first clock signal terminal to the first output signal terminal under the voltage control of the second node;

[0041] a second output module connected to the first node N1, the second power signal terminal VGL and the first output signal terminal OUT1, and configured to provide the second power signal of the second power signal terminal to the first output signal terminal under the voltage control of the first node;

[0042] a second control module connected to the second power signal terminal VGL, the second input signal terminal IN2, the first clock signal terminal CK1, and the third node N3, and configured to provide the second power signal from the second power signal terminal to the third node under the control of the second input signal from the second input signal terminal, and to provide the second power signal from the second power signal terminal to the third node under the control of the first clock signal from the first clock signal terminal;

[0043] a third control module connected to the third node N3, the second clock signal terminal CK2 and the first node N1, and configured to provide the second clock signal of the second clock signal terminal to the first node under the voltage control of the third node;

[0044] a fourth control module connected to the third node N3, the second power signal terminal VGL, and the second node N2, and configured to provide the second power signal from the second power signal terminal to the second node under voltage control of the third node;

[0045] a fifth control module connected to the first node N1, the second power signal terminal VGL, and the second node N2, and configured to provide the second power signal of the second power signal terminal to the second node under the voltage control of the first node;

[0046] a sixth control module connected to the second node N2, the second power signal terminal VGL and the first node N1, and configured to provide the second power signal of the second power signal terminal to the first node under the voltage control of the second node;

[0047] The energy storage module includes a first capacitor C1, wherein two ends of the first capacitor are respectively connected to the third node and the second clock signal terminal CK2.

[0048] The shift register provided in the above embodiment includes a first output module, a second output module, a first control module, a second control module, a third control module, a fourth control module, a fifth control module, a sixth control module and an energy storage module; the first output module provides the first clock signal of the first clock signal end to the first output signal end under the voltage control of the second node, the second output module provides the second power supply signal of the second power supply signal end to the first output signal end under the voltage control of the first node, the third control module and the sixth control module control the voltage of the first node, the first control module, the fourth control module and the fifth control module control the voltage of the second node, and the second control module controls the voltage of the third node. Through the cooperation of the six control modules and the energy storage module, the node potential can jump in time, shorten the time of the rising edge and falling edge of the output pulse signal, so that the output waveform meets the requirements.

[0049] FIG2 is an equivalent circuit diagram of a shift register.

[0050] As shown in FIG2 , in some exemplary embodiments, the first control module includes a first transistor T1 , a control electrode of the first transistor connected to a first input signal terminal, a first electrode of the first transistor connected to a first power signal terminal, and a second electrode of the first transistor connected to a second node.

[0051] As shown in FIG2 , in some exemplary embodiments, the first output module includes a second transistor T2 , a control electrode of the second transistor connected to the second node, a first electrode of the second transistor connected to the first clock signal terminal, and a second electrode of the second transistor connected to the first output signal terminal.

[0052] As shown in FIG2 , in some exemplary embodiments, the second output module includes a third transistor T3 , a control electrode of the third transistor being connected to the first node, a first electrode of the third transistor being connected to the second power signal terminal, and a second electrode of the third transistor being connected to the first output signal terminal.

[0053] As shown in Figure 2, in some exemplary embodiments, the second control module includes a fourth transistor and a fifth transistor, the control electrode of the fourth transistor is connected to the first clock signal terminal, the first electrode of the fourth transistor is connected to the second power signal terminal, the second electrode of the fourth transistor is connected to the third node, the control electrode of the fifth transistor is connected to the second input signal terminal, the first electrode of the fifth transistor is connected to the second power signal terminal, and the second electrode of the fifth transistor is connected to the third node.

[0054] As shown in FIG2 , in some exemplary embodiments, the third control module includes a sixth transistor T6 , a control electrode of the sixth transistor being connected to the third node, a first electrode of the sixth transistor being connected to the second clock signal terminal, and a second electrode of the sixth transistor being connected to the first node.

[0055] As shown in FIG2 , in some exemplary embodiments, the fourth control module includes a seventh transistor T7 , a control electrode of the seventh transistor being connected to the third node, a first electrode of the seventh transistor being connected to the second power signal terminal, and a second electrode of the seventh transistor being connected to the second node.

[0056] As shown in FIG2 , in some exemplary embodiments, the fifth control module includes an eighth transistor T8 , a control electrode of the eighth transistor being connected to the first node, a first electrode of the eighth transistor being connected to the second power signal terminal, and a second electrode of the eighth transistor being connected to the second node.

[0057] As shown in FIG2 , in some exemplary embodiments, the sixth control module includes a ninth transistor T9 , a control electrode of the ninth transistor being connected to the second node, a first electrode of the ninth transistor being connected to the second power signal terminal, and a second electrode of the ninth transistor being connected to the first node.

[0058] FIG3 provides an equivalent circuit diagram of another shift register.

[0059] As shown in FIG3 , in some exemplary embodiments, the first output module further includes a second capacitor C2, one end of which is connected to the control electrode of the second transistor, and the other end of which is connected to the second electrode of the second transistor. The second capacitor is connected between the control electrode and the second electrode of the second transistor to stabilize the potential of the control electrode of the second transistor.

[0060] As shown in FIG3 , in some exemplary embodiments, the second output module further includes a third capacitor C3, one end of which is connected to the control electrode of the third transistor, and the other end of which is connected to the first electrode of the third transistor. The third capacitor is connected between the control electrode and the first electrode of the third transistor to stabilize the potential of the control electrode of the third transistor.

[0061] FIG4 provides an equivalent circuit diagram of another shift register.

[0062] As shown in FIG4 , in some exemplary embodiments, the first output module further includes a tenth transistor T10, wherein a control electrode of the tenth transistor is connected to the first power signal terminal, a first electrode of the tenth transistor is connected to the second node, and a second electrode of the tenth transistor is connected to the control electrode of the second transistor. Providing the tenth transistor between the second node and the control electrode of the second transistor can stabilize the potential of the control electrode of the second transistor.

[0063] FIG5 provides an equivalent circuit diagram of another shift register.

[0064] As shown in FIG5 , in some exemplary embodiments, the second node N2 is further connected to a second output signal terminal OUT2 , which outputs a second output signal.

[0065] In some exemplary embodiments, all transistors in the shift register are N-type transistors.

[0066] In some exemplary embodiments, when all transistors in the shift register are N-type transistors, a working cycle of the shift register includes the following multiple time periods: a first time period, a second time period, a third time period, a fourth time period, and a fifth time period and a sixth time period that alternate multiple times;

[0067] The first power supply signal and the second power supply signal are DC signals, the first power supply signal is a high-level signal, the second power supply signal is a low-level signal, the first input signal and the second input signal are pulse signals, and the first clock signal and the second clock signal are periodic pulse signals; the first input signal and the second input signal are high-level signals in the first time period and low-level signals in other time periods; the first clock signal is a low-level signal in the first time period, the third time period and the fifth time period, and is a high-level signal in the second time period, the fourth time period and the sixth time period; the second clock signal is a high-level signal in the first time period, the third time period and the fifth time period, and is a low-level signal in the second time period, the fourth time period and the sixth time period.

[0068] In some exemplary embodiments, when all transistors in the shift register are N-type transistors, a working cycle of the shift register includes the following multiple time periods: a first time period, a second time period, a third time period, a fourth time period, and a fifth time period and a sixth time period that alternate multiple times;

[0069] The first power supply signal and the second power supply signal are DC signals, the first power supply signal is a high-level signal, the second power supply signal is a low-level signal, the first input signal and the second input signal are pulse signals, and the first clock signal and the second clock signal are periodic pulse signals; the first input signal is a high-level signal in the first time period and a low-level signal in other time periods; the second input signal is a high-level signal in the first time period and the second time period and a low-level signal in other time periods; the first clock signal is a low-level signal in the first time period, the third time period and the fifth time period, and a high-level signal in the second time period, the fourth time period and the sixth time period; the second clock signal is a high-level signal in the first time period, the third time period and the fifth time period, and a low-level signal in the second time period, the fourth time period and the sixth time period.

[0070] In some exemplary embodiments, all transistors in the shift register are oxide thin-film transistors. Oxide thin-film transistors have low carrier mobility. The coordination of the six control modules and the energy storage module enables timely node potential changes, shortening the rising and falling edge times of the output pulse signal, thereby ensuring that the output waveform meets the requirements.

[0071] The working process of the shift register is explained below with reference to the signal timing diagram.

[0072] Figure 6 provides a signal timing diagram for a shift register. The shift register adopts any of the structures shown in Figures 2 to 5, wherein all transistors are N-type transistors, the first power signal terminal provides a first power signal, the second power signal terminal provides a second power signal, the first clock signal terminal provides a first clock signal, the second clock signal terminal provides a second clock signal, the first input signal terminal provides a first input signal, the second input signal terminal provides a second input signal, the first output signal terminal outputs a first output signal, and the second output signal terminal outputs a second output signal (with respect to Figure 5). The first power signal and the second power signal are DC signals, the first input signal and the second input signal are pulse signals, the first input signal and the second input signal are identical, the first clock signal and the second clock signal are periodic pulse signals, and the first clock signal and the second clock signal are opposite in phase.

[0073] For an N-type transistor, when the voltage of the transistor gate (control electrode) is higher than the turn-on voltage, the transistor is turned on. When the voltage of the transistor gate is lower than the turn-on voltage, the transistor is in the off state. A high-level signal is a signal higher than the transistor turn-on voltage, and a low-level signal is a signal lower than the transistor turn-on voltage. The first power supply signal is a high-level signal, and the second power supply signal is a low-level signal.

[0074] A working cycle of the shift register may include multiple time periods: a first time period (t1), a second time period (t2), a third time period (t3), a fourth time period (t4), and a fifth time period (t5) and a sixth time period (t6) that appear alternately multiple times.

[0075] (1) The first period (t1 period)

[0076] The first input signal and the second input signal are high-level signals, the first clock signal is a low-level signal, and the second clock signal is a high-level signal.

[0077] The first clock signal is a low-level signal, the fourth transistor is turned off, the second input signal is a high-level signal, the fifth transistor is turned on, and the second power supply signal is provided to the third node. The second power supply signal is a low-level signal, so the potential of the third node is low.

[0078] The potential of the third node is at a low level, the sixth transistor and the seventh transistor are turned off, and the second clock signal is a high level signal, which charges the first capacitor.

[0079] The first input signal is a high-level signal, the first transistor is turned on, and the first power supply signal is provided to the second node. The first power supply signal is a high-level signal, so the potential of the second node is a high level.

[0080] The potential of the second node is high, the ninth transistor is turned on, and the second power signal is provided to the first node. The second power signal is a low-level signal, so the potential of the first node is low.

[0081] The potential of the first node is low, and the third and eighth transistors are turned off. The potential of the second node is high, and the second transistor is turned on, and the first clock signal is provided to the first output signal terminal. The first clock signal is a low-level signal, so the first output signal output by the first output signal terminal is a low-level signal. When the second capacitor is connected between the control electrode and the second electrode of the second transistor, the second node charges the second capacitor.

[0082] When the second node is also connected to the second output signal terminal, the second output signal output by the second output signal terminal is a high level signal.

[0083] (2) The second period (t2 period)

[0084] The first input signal and the second input signal are low-level signals, the first clock signal is a high-level signal, and the second clock signal is a low-level signal.

[0085] The second input signal is a low-level signal, the fifth transistor is turned off, the first clock signal is a high-level signal, the fourth transistor is turned on, and the second power supply signal is provided to the third node. The second power supply signal is a low-level signal, so the potential of the third node is low.

[0086] The potential of the third node is at a low level, and the sixth transistor and the seventh transistor are turned off.

[0087] The first input signal is a low-level signal, the first transistor is turned off, and the second node maintains the potential of the previous period ( t1 ), which is a high level potential.

[0088] The potential of the second node is high, the ninth transistor is turned on, and the second power signal is provided to the first node. The second power signal is a low-level signal, so the potential of the first node is low.

[0089] The potential of the first node is low, and the third and eighth transistors are turned off. The potential of the second node is high, and the second transistor is turned on. The first clock signal is provided to the first output signal terminal. The first clock signal is a high-level signal, so the first output signal output by the first output signal terminal jumps from a low-level signal to a high-level signal. Because the second transistor remains on during the second time period, it can quickly follow the jumps of the first clock signal, thereby shortening the rising edge time of the first output signal.

[0090] When the second node is also connected to the second output signal terminal, the second output signal output by the second output signal terminal is a high level signal.

[0091] (3) The third period (T3 period)

[0092] The first input signal and the second input signal are high-level signals, the first clock signal is a low-level signal, and the second clock signal is a high-level signal.

[0093] The first clock signal is a low-level signal, and the fourth transistor is turned off. The second input signal is a low-level signal, and the fifth transistor is turned off.

[0094] The second clock signal transitions from a low-level signal to a high-level signal, and the third node also transitions from a low-level signal to a high-level signal under the action of the third capacitor. After the third node transitions to a high-level signal, the sixth and seventh transistors turn on, the second clock signal is provided to the first node, and the second power supply signal is provided to the second node. The second clock signal is a high-level signal, and the potential of the first node transitions from a low-level signal to a high-level signal. The first input signal is a low-level signal, and the first transistor is turned off. The second power supply signal is a low-level signal, and the potential of the second node transitions from a high-level signal to a low-level signal.

[0095] The potential of the second node is at a low level, and the ninth transistor and the second transistor are turned off.

[0096] The potential of the first node is high, and the eighth transistor and the third transistor are turned on. A second power supply signal is provided to the second node, and the second power supply signal is a low-level signal, and the potential of the second node is low. The second power supply signal is provided to the first output signal terminal, and the second power supply signal is a low-level signal, and the first output signal output by the first output signal terminal jumps from a high-level signal to a low-level signal. When the third capacitor is connected between the control electrode and the first electrode of the third transistor, the first node charges the third capacitor.

[0097] After the potential of the third node jumps, the potentials of the second node and the first node are simultaneously controlled to jump, so that the second transistor is turned off and the third transistor is turned on at the same time, and the first output signal jumps from a high level to a low level, shortening the falling edge time of the first output signal.

[0098] When the second node is also connected to the second output signal terminal, the second output signal output by the second output signal terminal is a low level signal.

[0099] (4) The fourth period (T4 period)

[0100] The first input signal and the second input signal are low-level signals, the first clock signal is a high-level signal, and the second clock signal is a low-level signal.

[0101] The second input signal is a low-level signal, the fifth transistor is turned off, the first clock signal is a high-level signal, the fourth transistor is turned on, and the second power supply signal is provided to the third node. The second power supply signal is a low-level signal, so the potential of the third node changes from a high level to a low level.

[0102] The potential of the third node is at a low level, and the sixth transistor and the seventh transistor are turned off.

[0103] The first input signal is a low-level signal, the first transistor is turned off, and the second node maintains the potential of the previous period (t3), which is a low-level potential.

[0104] The potential of the second node is at a low level, and the ninth transistor and the second transistor are turned off.

[0105] The sixth transistor and the ninth transistor are turned off, and the first node maintains the potential of the previous period (t3), which is a high level.

[0106] The potential of the first node is high, the eighth transistor and the third transistor remain turned on, the potential of the second node remains low, the first output signal remains low, and the third capacitor maintains the high level of the control electrode of the third transistor.

[0107] When the second node is also connected to the second output signal terminal, the second output signal output by the second output signal terminal is a low level signal.

[0108] After the fourth period, the fifth period and the sixth period appear alternately several times until the end of this working cycle.

[0109] (5) The fifth period (T5 period)

[0110] The first input signal and the second input signal are low-level signals, the first clock signal is a low-level signal, and the second clock signal is a high-level signal.

[0111] The first clock signal is a low-level signal, and the fourth transistor is turned off. The second input signal is a low-level signal, and the fifth transistor is turned off.

[0112] The second clock signal transitions from a low-level signal to a high-level signal, and the third node also transitions from a low-level signal to a high-level signal under the action of the third capacitor. After the third node transitions to a high-level signal, the sixth and seventh transistors turn on, the second clock signal is provided to the first node, and the second power supply signal is provided to the second node. Since the second clock signal is a high-level signal, the potential of the first node remains high. Since the first input signal is a low-level signal, the first transistor is turned off. Since the second power supply signal is a low-level signal, the potential of the second node remains low.

[0113] The potential of the second node is at a low level, and the ninth transistor and the second transistor are turned off.

[0114] The potential of the first node is high, the eighth transistor and the third transistor remain on. The potential of the second node remains low, and the first output signal remains low. When the third capacitor is connected between the control electrode and the first electrode of the third transistor, the first node charges the third capacitor.

[0115] When the second node is also connected to the second output signal terminal, the second output signal output by the second output signal terminal is a low level signal.

[0116] (6) The sixth period (T6 period)

[0117] The first input signal and the second input signal are low-level signals, the first clock signal is a high-level signal, and the second clock signal is a low-level signal.

[0118] The second input signal is a low-level signal, the fifth transistor is turned off, the first clock signal is a high-level signal, the fourth transistor is turned on, and the second power supply signal is provided to the third node. The second power supply signal is a low-level signal, so the potential of the third node changes from a high level to a low level.

[0119] The potential of the third node is at a low level, and the sixth transistor and the seventh transistor are turned off.

[0120] The first input signal is a low-level signal, the first transistor is turned off, and the second node maintains the potential of the previous period (t5), which is a low-level potential.

[0121] The potential of the second node is at a low level, and the ninth transistor and the second transistor are turned off.

[0122] The sixth transistor and the ninth transistor are turned off, and the first node maintains the potential of the previous period (t5), which is a high level.

[0123] The potential of the first node is high, the eighth transistor and the third transistor remain turned on, the potential of the second node remains low, the first output signal remains low, and the third capacitor maintains the high level of the control electrode of the third transistor.

[0124] When the second node is also connected to the second output signal terminal, the second output signal output by the second output signal terminal is a low level signal.

[0125] FIG7 provides another signal timing diagram of a shift register. The shift register adopts any of the structures shown in FIG2 to FIG5 , wherein all transistors are N-type transistors, the first power signal terminal provides a first power signal, the second power signal terminal provides a second power signal, the first clock signal terminal provides a first clock signal, the second clock signal terminal provides a second clock signal, the first input signal terminal provides a first input signal, the second input signal terminal provides a second input signal, the first output signal terminal outputs a first output signal, and the second output signal terminal outputs a second output signal (with respect to FIG5 ). The first power signal and the second power signal are DC signals, the first input signal and the second input signal are pulse signals, the first input signal and the second input signal are different, the first clock signal and the second clock signal are periodic pulse signals, and the first clock signal and the second clock signal are in opposite phases.

[0126] A working cycle of the shift register may include multiple time periods: a first time period (t1), a second time period (t2), a third time period (t3), a fourth time period (t4), and a fifth time period (t5) and a sixth time period (t6) that appear alternately multiple times.

[0127] The first input signal in FIG6 has the same waveform as the first input signal in FIG7 , and the second input signal in FIG6 has a different waveform than the second input signal in FIG7 . The difference is that the second input signal in FIG6 is at a low level in the second time period, and the second input signal in FIG7 is at a high level in the second time period.

[0128] In the second time period, according to Figure 7, the fifth transistor is turned on, and according to Figure 6, the fifth transistor is turned off. However, no matter whether the fifth transistor is turned on or off, since the first clock signal is at a high level, the fourth transistor is turned on, so the second power supply signal is always provided to the third node, causing the potential of the third node to be a low level.

[0129] Therefore, although the second input signals in Figure 7 and Figure 6 are different, the potential changes of all nodes (first node, second node, third node) of the shift register within one working cycle are the same, and the waveforms of the first output signal and the second output signal are also exactly the same.

[0130] As shown in Figure 8, an embodiment of the present disclosure also provides a gate drive circuit, including N cascaded shift registers SR(i); the first output signal terminal of the kth shift register SR(k) is connected to the first input signal terminal of the k+1th shift register SR(k+1); 1≤k≤N-1, N>1; at least one shift register SR(i) among the N shift registers adopts the shift register in the above embodiment; 1≤i≤N.

[0131] As shown in FIG9 , in some exemplary embodiments, the first output signal terminal of the kth shift register SR(k) is further connected to the second input signal terminal of the k+1th shift register SR(k+1). In this case, the signals input to the first input signal terminal and the second input signal terminal of the shift register are the same.

[0132] As shown in FIG10 , in some exemplary embodiments, the gate drive circuit further includes N cascaded shift registers R(i), wherein the second input signal terminal of the k+1th shift register SR(k+1) is connected to the output signal terminal GOUT of the kth other shift register R(k); 1≤k≤N-1, N>1; 1≤i≤N; and the output signal output by the output signal terminal of the kth other shift register R(k) meets the requirements of the second input signal of the k+1th shift register SR(k+1). In this case, the signals input to the first input signal terminal and the second input signal terminal of the shift register are different.

[0133] The gate driving circuit may be connected to a pixel driving circuit of a display panel to provide various control signals, such as a row scanning signal, a reset signal, etc., to the pixel driving circuit.

[0134] The display panel includes an organic light-emitting diode (OLED) display panel.

[0135] An embodiment of the present disclosure further provides a display device, comprising the above-mentioned gate driving circuit.

[0136] The display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, or a navigation system. Other essential components of the display device are well understood by those skilled in the art and are not described in detail here, nor should they be construed as limiting the present invention.

[0137] Although the embodiments disclosed in this application are as described above, the contents described are merely embodiments adopted to facilitate understanding of this application and are not intended to limit the present invention. Any person skilled in the art to which the present invention belongs may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed in the present invention. However, the scope of patent protection of the present invention shall still be based on the scope defined by the attached claims.

Claims

1. A shift register comprising: A first control module, a first output module, a second output module, a second control module, a third control module, a fourth control module, a fifth control module, a sixth control module and an energy storage module; a first control module connected to the first power signal terminal, the first input signal terminal, and the second node, and configured to provide the first power signal of the first power signal terminal to the second node under the control of the first input signal of the first input signal terminal; a first output module connected to the second node, the first clock signal terminal and the first output signal terminal, and configured to provide the first clock signal of the first clock signal terminal to the first output signal terminal under the voltage control of the second node; a second output module connected to the first node, the second power signal terminal and the first output signal terminal, and configured to provide the second power signal of the second power signal terminal to the first output signal terminal under the voltage control of the first node; a second control module connected to the second power signal terminal, the second input signal terminal, the first clock signal terminal, and the third node, and configured to provide the second power signal from the second power signal terminal to the third node under the control of the second input signal from the second input signal terminal, and to provide the second power signal from the second power signal terminal to the third node under the control of the first clock signal from the first clock signal terminal; a third control module connected to the third node, the second clock signal terminal and the first node, and configured to provide the second clock signal of the second clock signal terminal to the first node under voltage control of the third node; a fourth control module connected to the third node, the second power signal terminal and the second node, and configured to provide the second power signal of the second power signal terminal to the second node under the voltage control of the third node; a fifth control module connected to the first node, the second power signal terminal, and the second node, and configured to provide the second power signal of the second power signal terminal to the second node under voltage control of the first node; a sixth control module connected to the second node, the second power signal terminal and the first node, and configured to provide the second power signal of the second power signal terminal to the first node under the voltage control of the second node; The energy storage module includes a first capacitor, wherein two ends of the first capacitor are respectively connected to the third node and the second clock signal end.

2. The shift register according to claim 1, wherein: The first output module includes a second transistor, a control electrode of the second transistor is connected to the second node, a first electrode of the second transistor is connected to the first clock signal terminal, and a second electrode of the second transistor is connected to the first output signal terminal; The second output module includes a third transistor, a control electrode of the third transistor is connected to the first node, a first electrode of the third transistor is connected to the second power signal terminal, and a second electrode of the third transistor is connected to the first output signal terminal.

3. The shift register according to claim 1, wherein: The first control module includes a first transistor, a control electrode of the first transistor is connected to the first input signal terminal, a first electrode of the first transistor is connected to the first power signal terminal, and a second electrode of the first transistor is connected to the second node; The fourth control module includes a seventh transistor, wherein the control electrode of the seventh transistor is connected to the third node, the first electrode of the seventh transistor is connected to the second power signal terminal, and the second electrode of the seventh transistor is connected to the second node; The fifth control module includes an eighth transistor, wherein the control electrode of the eighth transistor is connected to the first node, the first electrode of the eighth transistor is connected to the second power signal terminal, and the second electrode of the eighth transistor is connected to the second node.

4. The shift register according to claim 1, wherein: The third control module includes a sixth transistor, wherein the control electrode of the sixth transistor is connected to the third node, the first electrode of the sixth transistor is connected to the second clock signal terminal, and the second electrode of the sixth transistor is connected to the first node; The sixth control module includes a ninth transistor, wherein a control electrode of the ninth transistor is connected to the second node, a first electrode of the ninth transistor is connected to the second power signal terminal, and a second electrode of the ninth transistor is connected to the first node.

5. The shift register according to claim 1, wherein: The second control module includes a fourth transistor and a fifth transistor, the control electrode of the fourth transistor is connected to the first clock signal terminal, the first electrode of the fourth transistor is connected to the second power signal terminal, the second electrode of the fourth transistor is connected to the third node, the control electrode of the fifth transistor is connected to the second input signal terminal, the first electrode of the fifth transistor is connected to the second power signal terminal, and the second electrode of the fifth transistor is connected to the third node.

6. The shift register according to claim 2, wherein: The first output module further includes a second capacitor, one end of the second capacitor is connected to the control electrode of the second transistor, and the other end of the second capacitor is connected to the second electrode of the second transistor; The second output module further includes a third capacitor, one end of the third capacitor is connected to the control electrode of the third transistor, and the other end of the third capacitor is connected to the first electrode of the third transistor.

7. The shift register according to claim 2, wherein: The first output module further includes a tenth transistor, wherein the control electrode of the tenth transistor is connected to the first power signal terminal, the first electrode of the tenth transistor is connected to the second node, and the second electrode of the tenth transistor is connected to the control electrode of the second transistor.

8. The shift register according to claim 1, wherein: The second node is further connected to a second output signal terminal, and the second output signal terminal outputs a second output signal.

9. The shift register according to any one of claims 2 to 8, wherein: All transistors included in the shift register are oxide thin film transistors.

10. The shift register according to any one of claims 2 to 8, wherein: When all transistors in the shift register are N-type transistors, one working cycle of the shift register includes the following multiple time periods: a first time period, a second time period, a third time period, a fourth time period, and a fifth time period and a sixth time period that appear alternately multiple times; The first power supply signal and the second power supply signal are DC signals, the first power supply signal is a high-level signal, the second power supply signal is a low-level signal, the first input signal and the second input signal are pulse signals, and the first clock signal and the second clock signal are periodic pulse signals; the first input signal and the second input signal are high-level signals in the first time period and low-level signals in other time periods; the first clock signal is a low-level signal in the first time period, the third time period and the fifth time period, and is a high-level signal in the second time period, the fourth time period and the sixth time period; the second clock signal is a high-level signal in the first time period, the third time period and the fifth time period, and is a low-level signal in the second time period, the fourth time period and the sixth time period.

11. A gate drive circuit comprising: The invention comprises N cascaded shift registers SR(i); the first output signal terminal of the kth shift register SR(k) is connected to the first input signal terminal of the k+1th shift register SR(k+1); 1≤k≤N-1, N>1; at least one shift register SR(i) among the N shift registers adopts the shift register described in any one of claims 1 to 10; 1≤i≤N.

12. The gate driving circuit according to claim 11, wherein: The first output signal terminal of the kth shift register SR(k) is also connected to the second input signal terminal of the (k+1)th shift register SR(k+1).

13. A display device comprising: The gate drive circuit according to claim 11 or 12.

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