Display substrate and manufacturing method therefor, and display apparatus

Abstract

Provided in the present disclosure are a display substrate and a manufacturing method therefor, and a display apparatus. The display substrate comprises: a base substrate, which comprises a display region and a peripheral region located on the periphery of the display region, wherein the display region comprises: at least two display sub-regions. The display substrate further comprises: a plurality of scanning lines and a plurality of sub-pixels, wherein the plurality of scanning lines comprise a plurality of first scanning lines, which comprise at least two scanning line segments independent of each other, the at least two scanning line segments being located in different display sub-regions; and the plurality of sub-pixels are divided into a plurality of rows of sub-pixels, which comprise a target row of sub-pixels, and the target row of sub-pixels can be divided into at least two sub-pixel groups, the at least two sub-pixel groups being located in different display sub-regions, and the scanning line segments respectively being coupled to sub-pixels in the corresponding sub-pixel groups belonging to the same display sub-region.

Description

Display substrate, manufacturing method thereof, and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display substrate and a manufacturing method thereof, and a display device. Background Art

[0002] Organic Light-Emitting Diode (OLED) display products offer advantages such as high contrast, fast response, and low power consumption. To further reduce power consumption, OLED display products utilize a drive mode that combines low-temperature polysilicon transistors with oxide transistors, known as low-temperature polycrystalline oxide display technology. This technology enables low frame rate display and reduces driving power consumption by reducing the repeated refresh of static images.

[0003] Summary of the Invention

[0004] The present disclosure aims to provide a display substrate, a method for manufacturing the same, and a display device.

[0005] In order to achieve the above objectives, the present disclosure provides the following technical solutions:

[0006] A first aspect of the present disclosure provides a display substrate, comprising: a base substrate, the base substrate comprising a display area and a peripheral area located around the display area, the display area comprising at least two sub-display areas; the display substrate further comprising:

[0007] a plurality of scan lines, the plurality of scan lines including a plurality of first scan lines, the first scan line including at least two independent scan line segments, the at least two scan line segments being located in different sub-display areas;

[0008] A plurality of sub-pixels are divided into a plurality of rows of sub-pixels, the plurality of rows of sub-pixels include a target row of sub-pixels, the target row of sub-pixels can be divided into at least two groups of sub-pixel groups, the at least two groups of sub-pixel groups are located in different sub-display areas, and the scan line segments are respectively coupled to the sub-pixels in the corresponding sub-pixel groups belonging to the same sub-display area.

[0009] Optionally, the multiple rows of sub-pixels also include non-target row sub-pixels, and the sub-pixels included in the same row of non-target row sub-pixels are all located in the same sub-display area; the multiple scan lines also include multiple second scan lines, and the second scan lines are respectively coupled to the corresponding sub-pixels in the non-target row sub-pixels.

[0010] Optionally, the display area includes two sub-display areas arranged along a first direction, the first scan line includes two scan line segments arranged along the first direction, and at least a portion of the scan line segments is located in the corresponding sub-display area; or,

[0011] The display area includes at least three sub-display areas arranged along a first direction, the first scan line includes at least three scan line segments arranged along the first direction, and at least parts of the scan line segments are located in corresponding sub-display areas.

[0012] Optionally, the display area further includes a plurality of sub-display areas distributed in an array, the plurality of sub-display areas are divided into a plurality of rows of sub-display areas, and the number of sub-display areas included in each row of sub-display areas is the same or different.

[0013] Optionally, in the same first scan line, there is an nth spacing area between the nth scan line segment and the (n+1)th scan line segment, where n is an integer greater than or equal to 1; in at least part of the first scan lines, the nth spacing area is staggered along the first direction.

[0014] Optionally, in the same first scan line, there is an nth spacing area between the nth scan line segment and the (n+1)th scan line segment, where n is an integer greater than or equal to 1; in at least part of the first scan lines, the nth spacing area is located in the same column along the second direction.

[0015] Optionally, the target row sub-pixels include m sub-pixels arranged along the first direction, and the layout range of the nth spacer area is between (m / 2-a) and (m / 2+a), (m / 2-a) represents the (m / 2-a)th sub-pixel, and (m / 2+a) represents the (m / 2+a)th sub-pixel; a satisfies: a*d1≤d; d1 is the width of the layout area occupied by the sub-pixels along the first direction, and d2 is the width of the display area along the first direction.

[0016] Optionally, among the plurality of first scan lines, the nth spacing region of the odd-numbered first scan lines and the nth spacing region of the even-numbered first scan lines are staggered along the first direction.

[0017] Optionally, among the multiple first scan lines, the nth spacing region of the odd-numbered first scan lines is adjacent to the (m / 2-a)th sub-pixel, and the nth spacing region of the even-numbered first scan lines is adjacent to the (m / 2+a)th sub-pixel.

[0018] Optionally, the display substrate further includes:

[0019] a first gate driving circuit to a k-th gate driving circuit, wherein the first scan line includes k scan line segments arranged along a first direction, where k is an integer greater than or equal to 2;

[0020] The first gate driving circuit and the kth gate driving circuit are located in the peripheral area and are arranged opposite to each other along a first direction, and the display area is located between the first gate driving circuit and the kth gate driving circuit;

[0021] The first gate driving circuit is coupled to a first adjacent scanning line segment, and the kth gate driving circuit is coupled to a kth adjacent scanning line segment.

[0022] Optionally, k is an integer greater than or equal to 3;

[0023] The second gate driving circuit to the k-1th gate driving circuit are located in the display area; the yth gate driving circuit is coupled to the yth scanning line segment, where y is an integer satisfying 2≤y≤k-1.

[0024] Optionally, k is an integer greater than or equal to 3;

[0025] The second gate driving circuit to the k-1th gate driving circuit are located in the peripheral area, and the second gate driving circuit to the k-1th gate driving circuit are located on one side of the display area along the second direction; the yth gate driving circuit is coupled to the yth scan line segment, and y is an integer satisfying 2≤y≤k-1.

[0026] Optionally, the sub-pixel includes a sub-pixel driving circuit; the sub-pixel driving circuit includes a driving transistor and a compensation transistor, a first electrode of the compensation transistor is coupled to a second electrode of the driving transistor, and the second electrode of the compensation transistor is coupled to a gate of the driving transistor;

[0027] The first scan line includes a first gate line, the scan line segment includes a first gate line segment, and the first gate line segment is coupled to a gate of a corresponding compensation transistor belonging to the same sub-display area.

[0028] Optionally, the display substrate further includes a first initialization signal line; the sub-pixel driving circuit further includes: a first reset transistor, wherein a first electrode of the first reset transistor is coupled to the corresponding initialization signal line, and a second electrode of the first reset transistor is coupled to the second electrode of the driving transistor;

[0029] The first scan line further includes a first reset line, and the scan line segment further includes a first reset line segment. The first reset line segment is coupled to a gate of a corresponding first reset transistor belonging to the same sub-display area.

[0030] Optionally, the display substrate further includes a plurality of data lines; the sub-pixel driving circuit further includes: a data writing transistor, wherein a first electrode of the data writing transistor is coupled to a corresponding data line, and a second electrode of the data writing transistor is coupled to a first electrode of the driving transistor;

[0031] The first scan line further includes a second gate line, and the scan line segment further includes a second gate line segment. The second gate line segment is coupled to a gate of a corresponding data writing transistor belonging to the same sub-display area.

[0032] Optionally, the display substrate further includes a power line, at least a portion of which is located in a spacing area between adjacent first gate line segments; and / or, at least a portion of which is located in a spacing area between adjacent first reset line segments; and / or, at least a portion of which is located in a spacing area between adjacent second gate line segments.

[0033] Optionally, the display substrate further includes a power line; the sub-pixel driving circuit further includes: a power control transistor, a first electrode of the power control transistor being coupled to the power line, and a second electrode of the power control transistor being coupled to the first electrode of the driving transistor;

[0034] The first scan line further includes a light emitting control line, and the scan line segment further includes a light emitting control line segment. The light emitting control line segment is coupled to a gate of a corresponding power control transistor belonging to the same sub-display area.

[0035] Optionally, the display substrate further includes a third initialization signal line and a second reset line; the sub-pixel driving circuit further includes: a third reset transistor, wherein a first electrode of the third reset transistor is coupled to the third initialization signal line, a second electrode of the third reset transistor is coupled to the first electrode of the driving transistor, and a gate of the third reset transistor is coupled to the corresponding second reset line;

[0036] At least a portion of the third initialization signal line is located in a space between adjacent light emitting control line segments.

[0037] Optionally, the display substrate further includes a third initialization signal line; the sub-pixel driving circuit further includes: a third reset transistor, a first electrode of the third reset transistor being coupled to the third initialization signal line, and a second electrode of the third reset transistor being coupled to the first electrode of the driving transistor;

[0038] The first scan line further includes a second reset line, the scan line segment further includes a second reset line segment, and the second reset line segment is coupled to a gate of a corresponding third reset transistor belonging to the same sub-display area.

[0039] Optionally, the display substrate further includes a first initialization signal line; the sub-pixel driving circuit further includes: a first reset transistor and a first reset line, wherein a first electrode of the first reset transistor is coupled to the corresponding initialization signal line, a second electrode of the first reset transistor is coupled to the second electrode of the driving transistor, and a gate of the first reset transistor is coupled to the corresponding first reset line;

[0040] At least a portion of the first initialization signal line is located in a space between adjacent second reset line segments.

[0041] Optionally, the display substrate further includes: a power line, a first initialization signal line, a second initialization signal line, a third initialization signal line and a cathode layer;

[0042] The power lines located in different sub-display areas are independent of each other; and / or,

[0043] The first initialization signal lines located in different sub-display areas are independent of each other; and / or,

[0044] The second initialization signal lines located in different sub-display areas are independent of each other; and / or,

[0045] The third initialization signal lines located in different sub-display areas are independent of each other; and / or,

[0046] The cathode layers in different sub-display areas are independent of each other.

[0047] Based on the technical solution of the display substrate, a second aspect of the present disclosure provides a display device comprising the above-mentioned display substrate.

[0048] Based on the technical solution of the display substrate, a third aspect of the present disclosure provides a method for manufacturing a display substrate, which is used to manufacture the above-mentioned display substrate, wherein the display substrate includes a base substrate, the base substrate includes a display area and a peripheral area located around the display area, the display area includes: at least two sub-display areas;

[0049] The production method comprises:

[0050] Producing a plurality of scan lines, the plurality of scan lines including a plurality of first scan lines, the first scan lines including at least two independent scan line segments, the at least two scan line segments being located in different sub-display areas;

[0051] A plurality of sub-pixels are produced, and the plurality of sub-pixels are divided into a plurality of rows of sub-pixels, and the plurality of rows of sub-pixels include a target row of sub-pixels, and the target row of sub-pixels can be divided into at least two groups of sub-pixel groups, and the at least two groups of sub-pixel groups are located in different sub-display areas, and the scan line segments are respectively coupled to the sub-pixels in the corresponding sub-pixel groups belonging to the same sub-display area.

[0052] Optionally, the step of manufacturing a plurality of sub-pixels specifically includes:

[0053] Producing non-target row sub-pixels, wherein all sub-pixels included in the same row of non-target row sub-pixels are located in the same sub-display area;

[0054] The steps for making multiple scan lines include:

[0055] A plurality of second scan lines are manufactured, wherein the second scan lines are respectively coupled to the corresponding sub-pixels in the non-target row of sub-pixels. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] The drawings described herein are used to provide a further understanding of the present disclosure and constitute a part of the present disclosure. The exemplary embodiments of the present disclosure and their descriptions are used to explain the present disclosure and do not constitute an improper limitation of the present disclosure. In the drawings:

[0057] FIG1 is a first schematic diagram of a display substrate including a plurality of sub-display areas provided by an embodiment of the present disclosure;

[0058] FIG2 is a second schematic diagram of a display substrate including a plurality of sub-display areas provided by an embodiment of the present disclosure;

[0059] FIG3 is a schematic diagram of a first layout of a display substrate provided by an embodiment of the present disclosure;

[0060] FIG4 is a schematic diagram of a second layout of a display substrate provided in an embodiment of the present disclosure;

[0061] FIG5 is a schematic diagram of a third layout of a display substrate provided in an embodiment of the present disclosure;

[0062] FIG6 is a schematic diagram of a fourth layout of a display substrate provided in an embodiment of the present disclosure;

[0063] FIG7 is a fifth schematic diagram of a layout of a display substrate provided in an embodiment of the present disclosure;

[0064] FIG8 is a sixth schematic layout diagram of a display substrate provided in an embodiment of the present disclosure;

[0065] FIG9 is a seventh schematic layout diagram of a display substrate provided in an embodiment of the present disclosure;

[0066] FIG10 is a circuit structure diagram of a sub-pixel driving circuit provided in an embodiment of the present disclosure;

[0067] FIG11 is a schematic diagram of the layout of the second gate metal layer of the display substrate provided by an embodiment of the present disclosure;

[0068] FIG12 is a schematic diagram showing the layout of the second gate metal layer and the third gate metal layer of the display substrate provided by an embodiment of the present disclosure;

[0069] FIG13 is a schematic diagram showing the layout of multiple sub-pixel driving circuits of a display substrate provided by an embodiment of the present disclosure;

[0070] FIG14 is a schematic diagram of the layout of light shielding layers corresponding to two sub-pixels provided by an embodiment of the present disclosure;

[0071] FIG15 is a schematic diagram of the layout of the light shielding layer and the first active layer corresponding to two sub-pixels provided by an embodiment of the present disclosure;

[0072] FIG16 is a schematic diagram of the layout of the first active layer corresponding to two sub-pixels provided in an embodiment of the present disclosure;

[0073] FIG17 is a schematic diagram of a layout in which a first gate metal layer is added based on FIG16;

[0074] FIG18 is a schematic diagram of the layout of the first gate metal layer added in FIG17;

[0075] FIG19 is a schematic diagram of a layout in which a second gate metal layer is added on the basis of FIG17;

[0076] FIG20 is a schematic diagram of the layout of the second gate metal layer added in FIG19;

[0077] FIG21 is a schematic diagram of a layout in which a second active layer is added on the basis of FIG19;

[0078] FIG22 is a schematic diagram of the layout of the second active layer added in FIG21;

[0079] FIG23 is a schematic diagram of a layout in which a third gate metal layer is added on the basis of FIG21;

[0080] FIG24 is a schematic diagram of the layout of the third gate metal layer added in FIG23;

[0081] FIG25 is a schematic diagram of a layout in which an interlayer insulating layer is added on the basis of FIG23;

[0082] FIG26 is a schematic diagram of the layout of the deeper via holes in the interlayer insulating layer added in FIG25;

[0083] FIG27 is a schematic diagram of a layout in which a shallower via hole is formed in the interlayer insulating layer based on FIG25;

[0084] FIG28 is a schematic diagram of the layout of the shallower vias in the interlayer insulating layer added in FIG27;

[0085] FIG29 is a schematic diagram of a layout in which a first source / drain metal layer is added based on FIG27 ;

[0086] FIG30 is a schematic diagram of the layout of the first source / drain metal layer added in FIG29;

[0087] FIG31 is a schematic diagram of a layout with a passivation layer added on the basis of FIG29;

[0088] FIG32 is a schematic diagram of the layout of the through holes in the passivation layer added in FIG31;

[0089] FIG33 is a schematic diagram of a layout with a first planar layer added on the basis of FIG31;

[0090] FIG34 is a schematic diagram of the layout of through holes in the first planar layer added in FIG33;

[0091] FIG35 is a schematic diagram of a layout in which a second source / drain metal layer is added based on FIG33 ;

[0092] FIG36 is a schematic diagram of the layout of the second source / drain metal layer added in FIG35 ;

[0093] FIG37 is a schematic diagram of a layout in which a second first gate metal layer is added on the basis of FIG16 ;

[0094] FIG38 is a schematic diagram of the layout of the first gate metal layer added in FIG37;

[0095] FIG39 is a schematic diagram of a layout in which a second gate metal layer is added on the basis of FIG37;

[0096] FIG40 is a schematic diagram of a layout in which a second active layer and a third gate metal layer are added on the basis of FIG39;

[0097] FIG41 is a schematic diagram of a layout in which an interlayer insulating layer is added on the basis of FIG40;

[0098] FIG42 is a schematic diagram of a layout in which a first source / drain metal layer is added based on FIG41;

[0099] FIG43 is a schematic diagram of a layout in which a second source / drain metal layer is added based on FIG42;

[0100] FIG44 is a schematic diagram of a layout in which a third first gate metal layer is added on the basis of FIG16 ;

[0101] FIG45 is a schematic diagram of the layout of the first gate metal layer added in FIG44 ;

[0102] FIG46 is a schematic diagram of a layout in which a second gate metal layer is added based on FIG44 ;

[0103] FIG47 is a schematic diagram of a layout in which a second active layer and a third gate metal layer are added to the layout of FIG46;

[0104] FIG48 is a schematic diagram of a layout in which an interlayer insulating layer is added based on FIG47;

[0105] FIG49 is a schematic diagram of a layout in which a first source / drain metal layer is added based on FIG48;

[0106] FIG50 is a schematic diagram of a layout in which a second source / drain metal layer is added based on FIG49 DETAILED DESCRIPTION

[0107] In order to further illustrate the display substrate and its manufacturing method, and the display device provided by the embodiments of the present disclosure, a detailed description is given below with reference to the accompanying drawings.

[0108] Currently, OLED display products still require initialization and rewriting of all pixel voltages within a single frame when updating the display screen. However, in some special applications, such as videos on the left and comments on the right, the pixel voltages of half the screen do not need to be frequently updated, and the original display brightness can be maintained. In this case, repeatedly rewriting the full screen pixels would waste power.

[0109] Therefore, how to achieve split-screen refresh of display products and effectively reduce the power consumption of display products has become an urgent problem to be solved.

[0110] Referring to FIG. 1 and FIG. 2 , an embodiment of the present disclosure provides a display substrate, comprising: a base substrate, the base substrate comprising a display area 10 and a peripheral area 20 located around the display area 10 , the display area 10 comprising: at least two sub-display areas 101 ; the display substrate further comprising:

[0111] Multiple scan lines, as shown in Figures 3 to 9, 11 and 12, the multiple scan lines include multiple first scan lines 31, the first scan line 31 includes at least two independent scan line segments 310, and the at least two scan line segments 310 are located in different sub-display areas;

[0112] As shown in Figure 13, multiple sub-pixels P are divided into multiple rows of sub-pixels, and the multiple rows of sub-pixels include target row sub-pixels. The target row sub-pixels can be divided into at least two groups of sub-pixel groups P1, and the at least two groups of sub-pixel groups P1 are located in different sub-display areas. The scan line segment 310 is respectively coupled to each sub-pixel in the corresponding sub-pixel group P1 belonging to the same sub-display area.

[0113] It is worth noting that the driver chip S-IC is shown in Figures 1 to 9. In Figures 3 to 9, i represents the pixel corresponding to the i-th row, j represents the pixel corresponding to the j-th row, x represents the pixel corresponding to the x-th column, and z represents the pixel corresponding to the z-th column.

[0114] Exemplarily, the frequencies of the scanning signals transmitted by at least two scanning line segments 310 can be independently controlled, enabling the scanning signals transmitted by at least two scanning line segments 310 to have the same or different frequencies. Exemplarily, the scanning line segments 310 are coupled to corresponding gate drive circuits, which provide scanning signals thereto. The frequency of the scanning signal can be adjusted by adjusting the frequency of a frame start signal coupled to the gate drive circuit, but is not limited thereto.

[0115] Exemplarily, the display includes a display area 10 and a peripheral area 20 , wherein the peripheral area 20 at least partially surrounds the display area 10 , or the peripheral area 20 completely surrounds the display area 10 .

[0116] Exemplarily, the display area 10 includes two sub-display areas arranged along a first direction.

[0117] Exemplarily, the display area 10 includes at least three sub-display areas arranged along the first direction.

[0118] Exemplarily, as shown in FIG1 , the display area 10 includes a plurality of sub-display areas arranged in an array. The plurality of sub-display areas include two rows of sub-display areas arranged along a second direction. The first row of sub-display areas includes two sub-display areas arranged along the first direction, and the second row of sub-display areas includes one sub-display area. The width of the sub-display area along the first direction is greater than the width of any sub-display area in the first row along the first direction. Exemplarily, the two sub-display areas in the first row can achieve refresh rates of 120 Hz and 30 Hz, respectively, and the one sub-display area in the second row can achieve a refresh rate of 1 Hz, but the present invention is not limited thereto.

[0119] Exemplarily, as shown in FIG2 , the display area 10 includes a plurality of sub-display areas arranged in an array, the plurality of sub-display areas including two rows of sub-display areas arranged along the second direction, the first row of sub-display areas including three sub-display areas arranged along the first direction, and the second row of sub-display areas including two sub-display areas arranged along the first direction. The width of any one of the two sub-display areas along the first direction may be greater than, equal to, or less than the width of any one of the sub-display areas in the first row along the first direction. Exemplarily, the three sub-display areas in the first row may respectively achieve refresh rates of 120 Hz, 60 Hz, and 30 Hz, and the two sub-display areas in the second row may respectively achieve refresh rates of 10 Hz and 1 Hz, but the present invention is not limited thereto.

[0120] Exemplarily, the first direction and the second direction intersect, for example, the first direction includes a horizontal direction, and the second direction includes a vertical direction, but the present invention is not limited thereto.

[0121] Exemplarily, the display substrate includes a plurality of scan lines, at least part of which is located in the display area 10, and the scan lines may also include a part located in the peripheral area 20. The scan lines are used to transmit scan signals.

[0122] Exemplarily, the plurality of scan lines are arranged along the second direction, and the scan lines include at least a portion extending along the first direction.

[0123] Exemplarily, the multiple first scan lines 31 are arranged along the second direction, and the first scan lines 31 include at least two independent scan line segments 310 arranged along the first direction, and the scan line segment 310 includes at least a portion extending along the first direction. The at least two scan line segments 310 are located in different sub-display areas, that is, each scan line segment 310 is located in a different sub-display area.

[0124] For example, as shown in FIG10 , the display substrate includes a plurality of sub-pixels, which are located in the display area 10. The sub-pixels include a sub-pixel driving circuit and a light-emitting element EL. The sub-pixel driving circuit is coupled to the anode of the light-emitting element EL and is configured to provide a driving signal to the light-emitting element EL to drive the light-emitting element EL to emit light.

[0125] Exemplarily, the plurality of sub-pixels are distributed in an array. The plurality of sub-pixels are divided into a plurality of rows of sub-pixels and a plurality of columns of sub-pixels. The plurality of rows of sub-pixels are arranged along the second direction, and each row of sub-pixels includes a plurality of sub-pixels arranged along the first direction. The plurality of columns of sub-pixels are arranged along the first direction, and each column of sub-pixels includes a plurality of sub-pixels arranged along the second direction.

[0126] Exemplarily, the multiple rows of sub-pixels include multiple rows of target row sub-pixels, and the target row sub-pixels can be divided into at least two sub-pixel groups P1 arranged along the first direction, and each sub-pixel group P1 includes multiple sub-pixels arranged along the first direction.

[0127] Exemplarily, the at least two sub-pixel groups P1 are located in different sub-display areas, that is, the sub-pixel groups P1 belonging to the same sub-display area are located in different sub-display areas.

[0128] Exemplarily, the multiple rows of sub-pixels correspond one-to-one to the multiple scan lines, and the scan lines are respectively coupled to each sub-pixel in a corresponding row of sub-pixels.

[0129] Exemplarily, the plurality of first scan lines 31 correspond one-to-one to a plurality of target row sub-pixels, and the first scan lines 31 are respectively coupled to each sub-pixel in the corresponding target row sub-pixels. Exemplarily, the first scan line 31 includes at least two independent scan line segments 310. The target row sub-pixels can be divided into at least two sub-pixel groups P1. The at least two scan line segments 310 correspond one-to-one to the at least two sub-pixel groups P1, and the scan line segments 310 are respectively coupled to each sub-pixel in the corresponding sub-pixel group P1 belonging to the same sub-display area.

[0130] According to the specific structure of the display substrate described above, in the display substrate provided by the embodiment of the present disclosure, the display area 10 is configured to include at least two sub-display areas; the first scan line 31 is configured to include at least two independent scan line segments 310, and the at least two scan line segments 310 are located in different sub-display areas; and the target row sub-pixels are configured to be divided into at least two groups of sub-pixel groups P1, and the at least two groups of sub-pixel groups P1 are located in different sub-display areas, and the scan line segments 310 are respectively coupled to each sub-pixel in the corresponding sub-pixel group P1 belonging to the same sub-display area. This configuration enables the sub-pixel groups P1 in each sub-display area to be independently controlled through the scan line segments 310, thereby achieving partitioned refresh of each sub-display area, so that each sub-display area can achieve a different refresh rate. Therefore, the display substrate provided by the embodiment of the present disclosure can achieve split-screen refresh, while ensuring image display, reducing data transmission in the display substrate and power consumption of the system end, thereby effectively reducing the display power consumption of the display substrate.

[0131] In some embodiments, the multiple rows of sub-pixels also include non-target row sub-pixels, and the sub-pixels included in the same row of non-target row sub-pixels are all located in the same sub-display area; the multiple scan lines also include multiple second scan lines, and the second scan lines are respectively coupled to the corresponding sub-pixels in the non-target row sub-pixels.

[0132] 1 , the non-target row sub-pixels are located in the second row of the sub-display area 101, and a plurality of second scan lines are located in the second row of the sub-display area 101. Exemplarily, the second scan lines include first gate lines, but are not limited thereto.

[0133] Exemplarily, the multiple rows of sub-pixels include multiple rows of non-target row sub-pixels, the multiple rows of non-target row sub-pixels are arranged along the second direction, each non-target row sub-pixel includes multiple sub-pixels arranged along the first direction, each sub-pixel included in the same row of non-target row sub-pixels is located in the same sub-display area, and the non-target row sub-pixels and the second scan lines coupled thereto are located in the same sub-display area.

[0134] Exemplarily, the second scanning line does not include a plurality of line segments, and is an integral structure along the first direction.

[0135] Exemplarily, the sub-pixels in the non-target row can be sequentially arranged from the left edge of the display area 10 to the right edge of the display area 10. The second scan line can extend from the left side of the display area 10 to the right side of the display area 10.

[0136] The above-mentioned setting of the multiple rows of sub-pixels also includes non-target row sub-pixels, and the setting of the multiple scan lines also includes multiple second scan lines, so that the display substrate can include a sub-display area, and the sub-display area can span the entire display area 10 along the first direction, so that the display substrate can have a more diverse split-screen method.

[0137] In some embodiments, as shown in FIG3 to FIG9 , the display area 10 includes two sub-display areas arranged along a first direction, the first scan line 31 includes two scan line segments 310 arranged along the first direction, and at least a portion of the scan line segments 310 is located in the corresponding sub-display area; or,

[0138] The display area 10 includes at least three sub-display areas arranged along a first direction. The first scan line 31 includes at least three scan line segments 310 arranged along the first direction. At least part of the scan line segments 310 is located in the corresponding sub-display area.

[0139] Exemplarily, the display area 10 includes two sub-display areas arranged along a first direction, and the areas of the two sub-display areas are the same or different. By setting the display area 10 to include two sub-display areas arranged along the first direction, the display substrate can achieve left-right split-screen refresh.

[0140] Exemplarily, the display area 10 includes at least three sub-display areas arranged along the first direction, and the areas of the at least three sub-display areas can be the same or different. The sub-pixels in each sub-display area can be independently controlled through the scan line segment 310 coupled thereto.

[0141] In some embodiments, as shown in FIG. 1 and FIG. 2 , the display area 10 further includes a plurality of sub-display areas distributed in an array, the plurality of sub-display areas being divided into a plurality of rows of sub-display areas, and the number of sub-display areas included in each row of sub-display areas being the same or different.

[0142] For example, in the plurality of sub-display areas distributed in an array, the areas of the display areas may be the same or different. The boundaries between adjacent display areas may extend along the second direction, or extend in a direction forming a certain angle with the second direction.

[0143] The display area 10 is configured to include a plurality of sub-display areas distributed in an array, so that the display substrate can achieve refresh at different frequencies in multiple areas, which can better reduce the power consumption of the display substrate.

[0144] As shown in Figures 3 and 4, in some embodiments, in the same first scan line 31, there is an nth spacing area 311 between the nth scan line segment and the (n+1)th scan line segment, where n is an integer greater than or equal to 1; in at least part of the first scan line 31, the nth spacing area 311 is staggered along the first direction.

[0145] As shown in Figures 5 and 6, in some embodiments, in the same first scan line 31, there is an nth spacer 311 between the nth scan line segment 310 and the (n+1)th scan line segment 310, where n is an integer greater than or equal to 1; in at least part of the first scan line 31, the nth spacer 311 is located in the same column along the second direction.

[0146] It is worth noting that the spacing region 311 is the disconnection position of the first scan line 31 , ie, the region between adjacent scan line segments 310 along the first direction.

[0147] As shown in FIG. 12 , illustratively, in at least some of the first scan lines 31 , the n-th spacing regions in each first scan line 31 are staggered along the first direction.

[0148] Exemplarily, in different types of the first scan lines 31, the nth spacing regions are staggered along the first direction. For example, among the nth spacing regions in the first gate line NGate, the nth spacing regions in the second gate line PGate, the nth spacing regions in the first reset line Preset1, the nth spacing regions in the second reset line Preset2, and the nth spacing regions in the emission control line EM, the nth spacing regions in at least two different types of signal lines are staggered along the first direction. For example, the nth spacing regions in the first gate line NGate are staggered with the nth spacing regions in the second gate line PGate.

[0149] Exemplarily, in at least some of the first scan lines 31 , the n-th spacing regions in each first scan line 31 are located in the same column along the second direction.

[0150] In the display substrate provided by the above embodiment, by setting the nth spacer area in at least part of the first scan line 31 to be staggered along the first direction, and the nth spacer area in at least part of the first scan line 31 to be located in the same column along the second direction, the boundaries between adjacent sub-display areas can be better blurred, that is, the split-screen position of the display substrate can be blurred, ensuring that there is no clear split-screen boundary when the split-screen is refreshed, thereby improving the split-screen image quality.

[0151] In some embodiments, the target row sub-pixels include m sub-pixels arranged along a first direction, where m is a positive integer; the layout range of the nth spacer is between (m / 2-a) and (m / 2+a), (m / 2-a) represents the (m / 2-a)th sub-pixel, and (m / 2+a) represents the (m / 2+a)th sub-pixel; a satisfies: a*d1≤d; d1 is the width of the layout area occupied by the sub-pixels along the first direction, and d2 is the width of the display area 10 along the first direction.

[0152] For example, in each target row of sub-pixels, the nth spacer can be arranged at any position between the (m / 2-a)th sub-pixel and the (m / 2+a)th sub-pixel. It is worth noting that the layout position of the m / 2th sub-pixel is approximately located at the center of the display area 10 along the first direction.

[0153] Exemplarily, among the plurality of first scan lines 31 , the n-th spacing regions of the odd-numbered first scan lines 31 and the n-th spacing regions of the even-numbered first scan lines 31 are staggered along the first direction.

[0154] Exemplarily, among the multiple first scan lines 31, the nth spacing region of the odd-numbered first scan lines 31 is adjacent to the (m / 2-a)th sub-pixel, and the nth spacing region of the even-numbered first scan lines 31 is adjacent to the (m / 2+a)th sub-pixel.

[0155] In the display substrate provided by the above embodiment, the position of the nth spacer area included in each first scan line 31 can be unequally distributed between the (m / 2-a)th sub-pixel and the (m / 2+a)th sub-pixel. This can effectively blur the split-screen position of the display substrate, ensuring that there is no clear split-screen boundary when the split-screen is refreshed, thereby improving the split-screen image quality.

[0156] As shown in FIG. 3 to FIG. 9 , in some embodiments, the display substrate further includes:

[0157] The first gate driving circuit GOA1 to the k-th gate driving circuit, the first scanning line 31 includes k scanning line segments 310 arranged along the first direction, where k is an integer greater than or equal to 2;

[0158] The first gate driving circuit GOA1 and the kth gate driving circuit are located in the peripheral area 20 and are arranged opposite to each other along a first direction, and the display area 10 is located between the first gate driving circuit GOA1 and the kth gate driving circuit;

[0159] The first gate driving circuit GOA1 is coupled to the first adjacent scan line segment 310 , and the kth gate driving circuit is coupled to the kth adjacent scan line segment 310 .

[0160] Exemplarily, the display substrate is divided into a first sub-display area and a second sub-display area arranged along a first direction. k = 2. The first gate drive circuit GOA1 is located on the left side of the display substrate, near the first sub-display area, and the second gate drive circuit GOA2 is located on the right side of the display substrate, near the second sub-display area. The first gate drive circuit GOA1 is coupled to multiple first scan line segments 31 in the first sub-display area. The second gate drive circuit GOA2 is coupled to multiple second scan line segments 310 in the second sub-display area.

[0161] Exemplarily, the gate driving circuit includes a plurality of shift register units, each of which is coupled to at least one corresponding scan line segment 310 and configured to provide a corresponding scan signal to the at least one scan line segment 310 .

[0162] The above-mentioned setting couples the first gate drive circuit GOA1 with the first adjacent scan line segment 310, and couples the k-th gate drive circuit with the k-th adjacent scan line segment 310, so that while providing a scan signal to the scan line segment 310, the layout difficulty of the gate drive circuit is minimized, which is conducive to achieving a narrow frame of the display substrate.

[0163] As shown in Figures 7 to 9, in some embodiments, k is an integer greater than or equal to 3; the second gate driving circuit GOA2 to the k-1th gate driving circuit are located in the display area 10; the yth gate driving circuit is coupled to the yth scan line segment 310, and y is an integer satisfying 2≤y≤k-1.

[0164] Exemplarily, each gate driving circuit from the second gate driving circuit GOA2 to the (k-1)th gate driving circuit is located in the sub-display area where the scan line segment 310 coupled thereto is located, but is not limited thereto.

[0165] Exemplarily, as shown in FIG. 7 , which illustrates a case where k=3, the second gate driving circuit GOA2 is located in the display area 10 , and the third gate driving circuit GOA3 is located in the right frame.

[0166] Exemplarily, as shown in FIG8 , which illustrates the case where k=4, the second gate driving circuit GOA2 and the third gate driving circuit GOA3 are located in the display area 10 , and the fourth gate driving circuit GOA4 is located in the right frame.

[0167] The above-mentioned arrangement of the second gate driving circuit GOA2 to the k-1th gate driving circuit being located in the display area 10 and the yth gate driving circuit being coupled to the yth scan line segment 310 can reduce the difficulty of connecting the scan line segment 310 in the middle position (i.e., neither the first segment nor the last segment) with the corresponding gate driving circuit, and is also conducive to achieving a narrow frame of the display substrate.

[0168] As shown in Figure 9, in some embodiments, k is an integer greater than or equal to 3; the second gate drive circuit GOA2 to the k-1th gate drive circuit are located in the peripheral area 20, and the second gate drive circuit GOA2 to the k-1th gate drive circuit are located on one side of the display area 10 along the second direction; the yth gate drive circuit is coupled to the yth scan line segment 310, and y is an integer satisfying 2≤y≤k-1.

[0169] As shown in FIG9 , when k=3, the second gate driving circuit GOA2 is located on one side of the display area 10 along the second direction, the third gate driving circuit GOA3 is located on the right frame, and the first gate driving circuit GOA1 is located on the left frame.

[0170] Exemplarily, the second gate driving circuit GOA2 to the k-1th gate driving circuit are located on the upper frame of the display substrate, but the present invention is not limited thereto. The driving chip S-IC included in the display substrate is located on the lower frame.

[0171] Exemplarily, the y-th gate drive circuit is coupled to the y-th scan line segment 310 via a transparent conductive connecting line. The transparent conductive connecting line can be made of indium tin oxide (ITO) and can be formed in the same patterning process as other film layers made of ITO in the display substrate, but is not limited to this.

[0172] Exemplarily, the transparent conductive connecting line includes at least a portion extending along the second direction.

[0173] Exemplarily, the transparent conductive connecting line may extend in the same direction as the data line Data, or in the same direction as the power line ELVDD, but is not limited thereto.

[0174] The second gate driving circuit GOA2 to the k-1th gate driving circuit are arranged along the second direction on one side of the display area 10, thereby avoiding reducing the layout space of the molecular pixels inside the display area 10 and effectively reducing the layout difficulty of the gate driving circuit.

[0175] In some embodiments, the display substrate further includes: a plurality of power lines ELVDD, a plurality of data lines Data, a plurality of first initialization signal lines Vinit1, a plurality of second initialization signal lines Vinit2, a plurality of third initialization signal lines Vinit3, a plurality of first gate lines NGate, a plurality of second gate lines PGate, a plurality of first reset lines Preset1, a plurality of second reset lines Preset2, and a plurality of emission control lines EM. The power lines ELVDD include at least a portion extending along the second direction. The data lines Data include at least a portion extending along the second direction. The first initialization signal lines Vinit1 include at least a portion extending along the first direction. The second initialization signal lines Vinit2 include at least a portion extending along the first direction. The third initialization signal lines Vinit3 include at least a portion extending along the first direction. The first gate lines NGate include at least a portion extending along the first direction. The second gate lines PGate include at least a portion extending along the first direction. The first reset lines Preset1 include at least a portion extending along the first direction. The second reset lines Preset2 include at least a portion extending along the first direction. The light emitting control line EM includes at least a portion extending along the first direction.

[0176] The sub-pixel includes a sub-pixel driving circuit, which adopts an 8T1C (i.e., 8 transistors and 1 capacitor) structure, but is not limited thereto. The sub-pixel driving circuit includes: a driving transistor T3, a first reset transistor T1, a compensation transistor T2, a data writing transistor T4, a power control transistor T5, a light emission control transistor T6, a second reset transistor T7, a third reset transistor T8, and a storage capacitor Cst.

[0177] A gate of the first reset transistor T1 is coupled to a corresponding reset line, a first electrode of the first reset transistor T1 is coupled to a corresponding first initialization signal line Vinit1, and a second electrode of the first reset transistor T1 is coupled to a second electrode of the driving transistor T3.

[0178] The gate of the compensation transistor T2 is coupled to the corresponding first gate line NGate, the first electrode of the compensation transistor T2 is coupled to the second electrode of the driving transistor T3, and the second electrode of the compensation transistor T2 is coupled to the gate T3-g of the driving transistor T3.

[0179] The gate of the data writing transistor T4 is coupled to the corresponding second gate line PGate, the first electrode of the data writing transistor T4 is coupled to the corresponding data line Data, and the second electrode of the data writing transistor T4 is coupled to the first electrode of the driving transistor T3.

[0180] The gate of the power control transistor T5 is coupled to the corresponding light emitting control line EM, the first electrode of the power control transistor T5 is coupled to the corresponding power line ELVDD, and the second electrode of the power control transistor T5 is coupled to the first electrode of the driving transistor T3.

[0181] The gate of the light emitting control transistor T6 is coupled to the corresponding light emitting control line EM, the first electrode of the light emitting control transistor T6 is coupled to the second electrode of the driving transistor T3, and the second electrode of the light emitting control transistor T6 is coupled to the anode of the corresponding light emitting element EL.

[0182] The gate of the second reset transistor T7 is coupled to the corresponding second reset line Preset2, the first electrode of the second reset transistor T7 is coupled to the corresponding second initialization signal line Vinit2, the second electrode of the second reset transistor T7 is coupled to the anode of the corresponding light-emitting element EL, and the cathode of the light-emitting element EL receives the power signal ELVSS.

[0183] A gate of the third reset transistor T8 is coupled to the corresponding second reset line Preset2 , a first electrode of the third reset transistor T8 is coupled to the corresponding third initialization signal line Vinit3 , and a second electrode of the third reset transistor T8 is coupled to the first electrode of the driving transistor T3 .

[0184] The first plate of the storage capacitor Cst is coupled to the gate T3-g of the driving transistor T3, and the second plate Cst2 of the storage capacitor Cst is coupled to the power line ELVDD. Exemplarily, the gate T3-g of the driving transistor T3 is reused as the first plate of the storage capacitor Cst.

[0185] As shown in Figures 14 to 36 , the display substrate exemplarily includes the following layers stacked sequentially on the base substrate in a direction away from the base substrate: a light shielding layer LS, a first active layer, a first gate insulating layer, a first gate metal layer, a second gate insulating layer, a second gate metal layer, a third gate insulating layer, a second active layer, a fourth gate insulating layer, a third gate metal layer, an interlayer insulating layer, a first source / drain metal layer, a passivation layer, a first planarizing layer, a second source / drain metal layer, a second planarizing layer, an anode layer, a light-emitting functional layer, a cathode layer, and an encapsulation layer. It is worth noting that the display substrate may also include other film layers.

[0186] As shown in Figures 16 and 17, illustratively, the first active layer includes: a first active pattern 41 in the first reset transistor T1, a third active pattern 43 in the driving transistor T3, a fourth active pattern 44 in the data writing transistor T4, a fifth active pattern 45 in the power control transistor T5, a sixth active pattern 46 in the light emission control transistor T6, a seventh active pattern 47 in the second reset transistor T7, and an eighth active pattern 48 in the third reset transistor T8.

[0187] As shown in FIG18 , illustratively, the first gate metal layer includes: a first reset line Preset1 , a second gate line PGate, a gate T3 - g of the driving transistor T3 , a light emitting control line EM, a first reset line Preset1 , and a second reset line Preset2 .

[0188] As shown in FIG. 20 , illustratively, the second gate metal layer includes: a second electrode Cst2 of the storage capacitor Cst, and a first gate film layer NGate- 1 in the first gate line NGate.

[0189] As shown in FIG. 22 , illustratively, the second active layer includes: a second active pattern 42 in the compensation transistor T2 .

[0190] As shown in FIG24 , illustratively, the third gate metal layer includes: a first initialization signal line Vinit1 , a second initialization signal line Vinit2 , a second gate film layer NGate- 2 in the first gate line NGate , and a third initialization signal line Vinit3 .

[0191] Exemplarily, a plurality of through holes are formed in the interlayer insulating layer. As shown in FIG26 , a deep hole in the interlayer insulating layer is shown. The deep hole can achieve coupling between the first active layer and the first source-drain metal layer, or achieve coupling between the first gate metal layer and the first source-drain metal layer, or achieve coupling between the second gate metal layer and the first source-drain metal layer. As shown in FIG28 , a submerged hole in the interlayer insulating layer is shown. The submerged hole can achieve coupling between the third gate metal layer and the first source-drain metal layer, or couple the second active layer to the first source-drain metal layer.

[0192] As shown in FIG. 30 , illustratively, the first source-drain metal layer includes a first conductive connection portion 51 to a tenth conductive connection portion 50 .

[0193] The first conductive connection portion 51 is coupled to the first electrode of the first reset transistor T1 and the first initialization signal line Vinit1, respectively. The second conductive connection portion 52 is coupled to the first electrode of the data write transistor T4 and the data line Data, respectively. The third conductive connection portion 53 is coupled to the second electrode of the first reset transistor T1 and the second electrode of the drive transistor T3, respectively. The fourth conductive connection portion 54 is coupled to the second electrode of the compensation transistor T2 and the gate T3-g of the drive transistor T3, respectively. The fifth conductive connection portion 55 is coupled to the second electrode of the third reset transistor T8 and the first electrode of the drive transistor T3, respectively. The sixth conductive connection portion 56 is coupled to the first electrode of the power control transistor T5 and the second plate Cst2 of the storage capacitor Cst, respectively. The seventh conductive connection portion 57 is coupled to the first electrode of the third reset transistor T8 and the third initialization signal line Vinit3, respectively. The eighth conductive connection portion 58 is coupled to the first electrode of the second reset transistor T7 and the second initialization signal line Vinit2, respectively. The ninth conductive connection portion 59 is coupled to the second electrode of the light emission control transistor T6 and the eleventh conductive connection portion 61. The tenth conductive connection portion 50 is coupled to the second plate Cst2 of the storage capacitor Cst and the power line ELVDD.

[0194] As shown in FIG. 32 , illustratively, a plurality of through holes are formed on the passivation layer.

[0195] As shown in Figure 34, illustratively, a plurality of vias are formed on the first planar layer. The vias on the first planar layer overlap with the vias on the passivation layer to achieve coupling between the first source-drain metal layer and the second source-drain metal layer.

[0196] As shown in FIG36 , illustratively, the second source-drain metal layer includes: a data line Data, a power line ELVDD and an eleventh conductive connection portion 61 , and the eleventh conductive connection portion 61 is coupled to the ninth conductive connection portion 59 and the corresponding anode layer, respectively.

[0197] As shown in FIG10 to FIG36 , in some embodiments, the sub-pixel includes a sub-pixel driving circuit; the sub-pixel driving circuit includes a driving transistor T3 and a compensation transistor T2, wherein a first electrode of the compensation transistor T2 is coupled to a second electrode of the driving transistor T3, and a second electrode of the compensation transistor T2 is coupled to a gate T3-g of the driving transistor T3;

[0198] As shown in FIG. 23 , the first scan line 31 includes a first gate line NGate, and the scan line segment 310 includes a first gate line segment coupled to a gate of a corresponding compensation transistor T2 belonging to the same sub-display area.

[0199] Exemplarily, the first gate line NGate includes a first gate film layer NGate-1 and a second gate film layer NGate-2 stacked together, wherein the first gate film layer NGate-1 is formed using a second gate metal layer, and the second gate film layer NGate-2 is formed using a third gate metal layer. Each spacer is formed on the first gate line NGate, and the first gate film layer NGate-1 and the second gate film layer NGate-2 are both disconnected.

[0200] Exemplarily, the first gate line segment is multiplexed as the gate of the corresponding compensation transistor T2 belonging to the same sub-display area.

[0201] In the display substrate provided in the above embodiment, by setting the first scan line 31 to include the first gate line NGate, the compensation transistor T2 in each sub-display area can be independently controlled, thereby achieving independent refresh of each sub-display area and better minimizing the power consumption of the display substrate.

[0202] As shown in FIG10 and FIG37 to FIG43, in some embodiments, the display substrate further includes a first initialization signal line Vinit1; the sub-pixel driving circuit further includes: a first reset transistor T1, wherein a first electrode of the first reset transistor T1 is coupled to the corresponding initialization signal line, and a second electrode of the first reset transistor T1 is coupled to the second electrode of the driving transistor T3;

[0203] The first scan line 31 further includes a first reset line Preset1 , and the scan line segment 310 further includes a first reset line segment. The first reset line segment is coupled to the gate of the corresponding first reset transistor T1 belonging to the same sub-display area.

[0204] In the display substrate provided by the above embodiment, by setting the first scan line 31 to also include the first reset line Preset1, the first reset transistor T1 in each sub-display area can be independently controlled, thereby better controlling the independent refresh of each sub-display area, minimizing power consumption while ensuring display quality.

[0205] As shown in FIG10 and FIG37 to FIG43, in some embodiments, the display substrate further includes a plurality of data lines Data; the sub-pixel driving circuit further includes: a data writing transistor T4, wherein a first electrode of the data writing transistor T4 is coupled to the corresponding data line Data, and a second electrode of the data writing transistor T4 is coupled to the first electrode of the driving transistor T3;

[0206] The first scan line 31 further includes a second gate line PGate, and the scan line segment 310 further includes a second gate line segment. The second gate line segment is coupled to the gate of the corresponding data writing transistor T4 belonging to the same sub-display area.

[0207] In the display substrate provided by the above embodiment, by setting the first scan line 31 to also include the second gate line PGate, it is possible to independently control the data writing transistor T4 in each sub-display area, thereby better controlling the independent refresh of each sub-display area, minimizing power consumption while ensuring display quality.

[0208] As shown in Figure 43, in some embodiments, the display substrate further includes a power line ELVDD, at least a portion of the power line ELVDD is located in the spacing area between adjacent first gate line segments; and / or, at least a portion of the power line ELVDD is located in the spacing area between adjacent first reset line segments; and / or, at least a portion of the power line ELVDD is located in the spacing area between adjacent second gate line segments.

[0209] Exemplarily, the power line ELVDD completely covers the spacing area between adjacent first gate line segments.

[0210] Exemplarily, the power line ELVDD completely covers the space between adjacent first reset line segments.

[0211] Exemplarily, the power line ELVDD completely covers the space between adjacent second gate line segments.

[0212] Exemplarily, the power line ELVDD at least partially covers the space between adjacent second reset line segments.

[0213] Exemplarily, the power line ELVDD at least partially covers the space between adjacent light emitting control line segments.

[0214] The above configuration enables the power line ELVDD located in the upper layer to shield the spacing area (ie, the disconnected portion of the first scan line 31 ), thereby reducing the influence of the spacing area on the display effect.

[0215] In some embodiments, the display substrate further includes a data line Data, wherein the data line Data at least partially covers the spacer area between adjacent first gate line segments; and / or, the data line Data at least partially covers the spacer area between adjacent first reset line segments; and / or, the data line Data at least partially covers the spacer area between adjacent second gate line segments; and / or, the data line Data at least partially covers the spacer area between adjacent second reset line segments; and / or, the data line Data at least partially covers the spacer area between adjacent light-emitting control line segments.

[0216] In some embodiments, the display substrate further includes an anode layer, at least a portion of the anode layer being located in a spacer region between adjacent first gate line segments; and / or at least a portion of the anode layer being located in a spacer region between adjacent first reset line segments; and / or at least a portion of the anode layer being located in a spacer region between adjacent second gate line segments.

[0217] The above arrangement enables the anode layer located on the upper layer to shield the spacer area, thereby reducing the influence of the spacer area on the display effect.

[0218] In some embodiments, the display substrate includes a first source-drain metal layer, at least a portion of the first source-drain metal layer is located in the spacer area between adjacent first gate line segments; and / or, at least a portion of the first source-drain metal layer is located in the spacer area between adjacent first reset line segments; and / or, at least a portion of the first source-drain metal layer is located in the spacer area between adjacent second gate line segments.

[0219] The above arrangement enables the first source-drain metal layer located on the upper layer to shield the spacer area, thereby reducing the influence of the spacer area on the display effect.

[0220] As shown in FIG10 and FIG44 to FIG50 , in some embodiments, the display substrate further includes a power line ELVDD; the sub-pixel driving circuit further includes: a power control transistor T5, wherein a first electrode of the power control transistor T5 is coupled to the power line ELVDD, and a second electrode of the power control transistor T5 is coupled to a first electrode of the driving transistor T3;

[0221] The first scan line 31 further includes a light emitting control line EM, and the scan line segment 310 further includes a light emitting control line segment. The light emitting control line segment is coupled to the gate of the corresponding power control transistor T5 belonging to the same sub-display area.

[0222] In the display substrate provided by the above embodiment, by setting the first scanning line 31 to also include a light-emitting control line EM, it is possible to independently control the power control transistor T5 and the light-emitting control transistor T6 in each sub-display area, thereby better controlling the independent refresh of each sub-display area, minimizing power consumption while ensuring display quality.

[0223] As shown in FIG10 and FIG44 to FIG50, in some embodiments, the display substrate further includes a third initialization signal line Vinit3 and a second reset line Preset2; the sub-pixel driving circuit further includes: a third reset transistor T8, wherein a first electrode of the third reset transistor T8 is coupled to the third initialization signal line Vinit3, a second electrode of the third reset transistor T8 is coupled to the first electrode of the driving transistor T3, and a gate of the third reset transistor T8 is coupled to the corresponding second reset line Preset2;

[0224] As shown in FIG47 , at least a portion of the third initialization signal line Vinit3 is located in the spacing area between adjacent light emitting control line segments.

[0225] The above arrangement enables the third initialization signal line Vinit3 located in the upper layer to shield the spacing area between the light-emitting control line segments, thereby reducing the influence of the spacing area on the display effect.

[0226] As shown in FIG10 and FIG44 to FIG50, in some embodiments, the display substrate further includes a third initialization signal line Vinit3; the sub-pixel driving circuit further includes: a third reset transistor T8, a first electrode of the third reset transistor T8 is coupled to the third initialization signal line Vinit3, and a second electrode of the third reset transistor T8 is coupled to the first electrode of the driving transistor T3;

[0227] The first scan line 31 further includes a second reset line Preset2 , and the scan line segment 310 further includes a second reset line segment. The second reset line segment is coupled to the gate of the corresponding third reset transistor T8 belonging to the same sub-display area.

[0228] In the display substrate provided in the above embodiment, by setting the first scan line 31 to also include the second reset line Preset2, it is possible to independently control the second reset transistor T7 and the third reset transistor T8 in each sub-display area, thereby better controlling the independent refresh of each sub-display area, minimizing power consumption while ensuring display quality.

[0229] As shown in FIG10 and FIG44 to FIG50, in some embodiments, the display substrate further includes a first initialization signal line Vinit1; the sub-pixel driving circuit further includes: a first reset transistor T1 and a first reset line Preset1, wherein a first electrode of the first reset transistor T1 is coupled to the corresponding initialization signal line, a second electrode of the first reset transistor T1 is coupled to the second electrode of the driving transistor T3, and a gate of the first reset transistor T1 is coupled to the corresponding first reset line Preset1;

[0230] As shown in FIG47 , at least a portion of the first initialization signal line Vinit1 is located in a space between adjacent second reset line segments.

[0231] The above configuration enables the first initialization signal line Vinit1 located in the upper layer to shield the space between the second reset line segments, thereby reducing the influence of the space on the display effect.

[0232] It should be noted that the schematic diagrams of a portion of a single-layer film in the embodiments corresponding to Figures 37 to 43 are the same as those in the embodiments corresponding to Figures 14 to 36 and are not repeated in this application. The schematic diagrams of a portion of a single-layer film in the embodiments corresponding to Figures 44 to 50 are the same as those in the embodiments corresponding to Figures 14 to 36 and are not repeated in this application.

[0233] In some embodiments, the display substrate further includes: a power line ELVDD, a first initialization signal line Vinit1, a second initialization signal line Vinit2, a third initialization signal line Vinit3 and a cathode layer;

[0234] The power lines ELVDD located in different sub-display areas are independent of each other; and / or,

[0235] The first initialization signal lines Vinit1 located in different sub-display areas are independent of each other; and / or,

[0236] The second initialization signal lines Vinit2 located in different sub-display areas are independent of each other; and / or,

[0237] The third initialization signal lines Vinit3 located in different sub-display areas are independent of each other; and / or,

[0238] The cathode layers in different sub-display areas are independent of each other.

[0239] The above configuration can independently control each sub-display area, thereby better realizing independent refresh control of each sub-display area, minimizing power consumption while ensuring display quality.

[0240] The embodiment of the present disclosure also includes a display device, including the display substrate provided by the above embodiment.

[0241] It should be noted that the display device can be any product or component with a display function, such as a television, a monitor, a digital photo frame, a mobile phone, a tablet computer, a wearable display product, a notebook, etc., wherein the display device also includes a flexible circuit board, a printed circuit board and a backplane, etc.

[0242] In the display substrate provided by the above embodiment, the display area is set to include at least two sub-display areas; the first scan line is set to include at least two independent scan line segments, and the at least two scan line segments are located in different sub-display areas; and the target row sub-pixels are set to be able to be divided into at least two groups of sub-pixel groups, and the at least two groups of sub-pixel groups are located in different sub-display areas, and the scan line segments are respectively coupled to each sub-pixel in the corresponding sub-pixel group belonging to the same sub-display area. This setting method enables the sub-pixel groups in each sub-display area to be independently controlled through the scan line segments, thereby achieving partitioned refresh of each sub-display area, so that each sub-display area can achieve a different refresh rate. Therefore, the display substrate provided by the above embodiment can achieve split-screen refresh, while ensuring the display of the picture, reducing the data transmission in the display substrate and the power consumption of the system end, thereby effectively reducing the display power consumption of the display substrate.

[0243] Therefore, the display device provided by the embodiment of the present disclosure also has the above-mentioned beneficial effects when it includes the above-mentioned display substrate, which will not be described in detail here.

[0244] The embodiment of the present disclosure further provides a method for manufacturing a display substrate, which is used to manufacture the above-mentioned display substrate, wherein the display substrate includes a base substrate, the base substrate includes a display area and a peripheral area located around the display area, the display area includes: at least two sub-display areas;

[0245] The production method comprises:

[0246] Producing a plurality of scan lines, the plurality of scan lines including a plurality of first scan lines, the first scan lines including at least two independent scan line segments, the at least two scan line segments being located in different sub-display areas;

[0247] A plurality of sub-pixels are produced, and the plurality of sub-pixels are divided into a plurality of rows of sub-pixels, and the plurality of rows of sub-pixels include a target row of sub-pixels, and the target row of sub-pixels can be divided into at least two groups of sub-pixel groups, and the at least two groups of sub-pixel groups are located in different sub-display areas, and the scan line segments are respectively coupled to the sub-pixels in the corresponding sub-pixel groups belonging to the same sub-display area.

[0248] In some embodiments, the step of manufacturing a plurality of sub-pixels specifically includes:

[0249] Producing non-target row sub-pixels, wherein all sub-pixels included in the same row of non-target row sub-pixels are located in the same sub-display area;

[0250] The steps for making multiple scan lines include:

[0251] A plurality of second scan lines are manufactured, wherein the second scan lines are respectively coupled to the corresponding sub-pixels in the non-target row of sub-pixels.

[0252] It should be noted that the signal line extending along the X-direction means that the signal line includes a main portion and a secondary portion connected to the main portion, the main portion is a line, a line segment, or a strip-shaped body, the main portion extends along the X-direction, and the length of the main portion extending along the X-direction is greater than the length of the secondary portion extending along other directions.

[0253] It should be noted that the "same layer" in the embodiment of the present disclosure may refer to a film layer on the same structural layer. Or, for example, a film layer in the same layer may be a film layer formed by using the same film forming process to form a specific pattern, and then patterning the film layer using the same mask through a single composition process to form a layer structure. Depending on the specific pattern, a single composition process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous. These specific patterns may also be at different heights or have different thicknesses.

[0254] In the various method embodiments of the present disclosure, the serial numbers of the steps cannot be used to limit the order of the steps. For ordinary technicians in this field, without paying any creative work, changes to the order of the steps are also within the scope of protection of the present disclosure.

[0255] It should be noted that the various embodiments in this specification are described in a progressive manner. Similar parts between the various embodiments can be referred to in conjunction with each other. Each embodiment focuses on the differences from other embodiments. In particular, the method embodiments are described briefly because they are generally similar to the product embodiments. For relevant parts, refer to the description of the product embodiments.

[0256] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect", "couple" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0257] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “under” another element, it can be “directly on” or “under” the other element or intervening elements may be present.

[0258] In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0259] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A display substrate, comprising: A base substrate, the base substrate including a display area and a peripheral area located around the display area, the display area including at least two sub-display areas; the display substrate further including: a plurality of scan lines, the plurality of scan lines including a plurality of first scan lines, the first scan line including at least two independent scan line segments, the at least two scan line segments being located in different sub-display areas; A plurality of sub-pixels are divided into a plurality of rows of sub-pixels, the plurality of rows of sub-pixels include a target row of sub-pixels, the target row of sub-pixels can be divided into at least two groups of sub-pixel groups, the at least two groups of sub-pixel groups are located in different sub-display areas, and the scan line segments are respectively coupled to the sub-pixels in the corresponding sub-pixel groups belonging to the same sub-display area.

2. The display substrate according to claim 1, wherein The multiple rows of sub-pixels also include non-target row sub-pixels, and the sub-pixels included in the same row of non-target row sub-pixels are all located in the same sub-display area; the multiple scan lines also include multiple second scan lines, and the second scan lines are respectively coupled to the corresponding sub-pixels in the non-target row sub-pixels.

3. The display substrate according to claim 1, wherein The display area includes two sub-display areas arranged along a first direction, the first scan line includes two scan line segments arranged along the first direction, and at least a portion of the scan line segments is located in the corresponding sub-display area; or, The display area includes at least three sub-display areas arranged along a first direction, the first scan line includes at least three scan line segments arranged along the first direction, and at least parts of the scan line segments are located in corresponding sub-display areas.

4. The display substrate according to claim 1, wherein The display area further includes a plurality of sub-display areas distributed in an array. The plurality of sub-display areas are divided into a plurality of rows of sub-display areas. The number of sub-display areas included in each row of sub-display areas is the same or different.

5. The display substrate according to claim 1, wherein In the same first scan line, there is an nth spacing area between the nth scan line segment and the (n+1)th scan line segment, where n is an integer greater than or equal to 1; in at least part of the first scan lines, the nth spacing area is staggered along the first direction. The display substrate according to claim 1 , wherein: In the same first scan line, there is an nth spacing area between the nth scan line segment and the (n+1)th scan line segment, where n is an integer greater than or equal to 1; in at least some of the first scan lines, the nth spacing area is located in the same column along the second direction.

7. The display substrate according to claim 5 or 6, wherein: The target row sub-pixels include m sub-pixels arranged along a first direction, and the layout range of the nth interval area is between (m / 2-a) and (m / 2+a), (m / 2-a) represents the (m / 2-a)th sub-pixel, and (m / 2+a) represents the (m / 2+a)th sub-pixel; a satisfies: a*d1≤d; d1 is the width of the layout area occupied by the sub-pixels along the first direction, and d2 is the width of the display area along the first direction.

8. The display substrate according to claim 7, wherein: Among the plurality of first scan lines, the n-th spacing regions of the odd-numbered first scan lines and the n-th spacing regions of the even-numbered first scan lines are staggered along the first direction.

9. The display substrate according to claim 8, wherein: Among the plurality of first scan lines, the nth spacing region of the odd-numbered first scan lines is adjacent to the (m / 2-a)th sub-pixel, and the nth spacing region of the even-numbered first scan lines is adjacent to the (m / 2+a)th sub-pixel.

10. The display substrate according to claim 1, wherein The display substrate further includes: a first gate driving circuit to a k-th gate driving circuit, wherein the first scan line includes k scan line segments arranged along a first direction, where k is an integer greater than or equal to 2; The first gate driving circuit and the kth gate driving circuit are located in the peripheral area and are arranged opposite to each other along a first direction, and the display area is located between the first gate driving circuit and the kth gate driving circuit; The first gate driving circuit is coupled to a first adjacent scanning line segment, and the kth gate driving circuit is coupled to a kth adjacent scanning line segment.

11. The display substrate according to claim 10, wherein: k is an integer greater than or equal to 3; The second gate driving circuit to the k-1th gate driving circuit are located in the display area; the yth gate driving circuit is coupled to the yth scanning line segment, where y is an integer satisfying 2≤y≤k-1.

12. The display substrate according to claim 10, wherein: k is an integer greater than or equal to 3; The second gate driving circuit to the k-1th gate driving circuit are located in the peripheral area, and the second gate driving circuit to the k-1th gate driving circuit are located on one side of the display area along the second direction; the yth gate driving circuit is coupled to the yth scan line segment, and y is an integer satisfying 2≤y≤k-1.

13. The display substrate according to claim 1, wherein The sub-pixel includes a sub-pixel driving circuit; the sub-pixel driving circuit includes a driving transistor and a compensation transistor, a first electrode of the compensation transistor is coupled to a second electrode of the driving transistor, and a second electrode of the compensation transistor is coupled to a gate of the driving transistor; The first scan line includes a first gate line, the scan line segment includes a first gate line segment, and the first gate line segment is coupled to a gate of a corresponding compensation transistor belonging to the same sub-display area.

14. The display substrate according to claim 13, wherein: The display substrate further includes a first initialization signal line; the sub-pixel driving circuit further includes: a first reset transistor, a first electrode of the first reset transistor being coupled to the corresponding initialization signal line, and a second electrode of the first reset transistor being coupled to the second electrode of the driving transistor; The first scan line further includes a first reset line, and the scan line segment further includes a first reset line segment. The first reset line segment is coupled to a gate of a corresponding first reset transistor belonging to the same sub-display area.

15. The display substrate according to claim 14, wherein: The display substrate further includes a plurality of data lines; the sub-pixel driving circuit further includes: a data writing transistor, wherein a first electrode of the data writing transistor is coupled to a corresponding data line, and a second electrode of the data writing transistor is coupled to a first electrode of the driving transistor; The first scan line further includes a second gate line, and the scan line segment further includes a second gate line segment. The second gate line segment is coupled to a gate of a corresponding data writing transistor belonging to the same sub-display area.

16. The display substrate according to claim 15, wherein: The display substrate further includes a power line, at least a portion of which is located in a spacing area between adjacent first gate line segments; and / or at least a portion of which is located in a spacing area between adjacent first reset line segments; and / or at least a portion of which is located in a spacing area between adjacent second gate line segments.

17. The display substrate according to claim 13, wherein: The display substrate further includes a power line; the sub-pixel driving circuit further includes: a power control transistor, a first electrode of the power control transistor being coupled to the power line, and a second electrode of the power control transistor being coupled to the first electrode of the driving transistor; The first scan line further includes a light emitting control line, and the scan line segment further includes a light emitting control line segment. The light emitting control line segment is coupled to a gate of a corresponding power control transistor belonging to the same sub-display area.

18. The display substrate according to claim 17, wherein: The display substrate further includes a third initialization signal line and a second reset line; The sub-pixel driving circuit further includes: a third reset transistor, wherein a first electrode of the third reset transistor is coupled to the third initialization signal line, a second electrode of the third reset transistor is coupled to the first electrode of the driving transistor, and a gate of the third reset transistor is coupled to the corresponding second reset line; At least a portion of the third initialization signal line is located in a space between adjacent light emitting control line segments.

19. The display substrate according to claim 13, wherein: The display substrate further includes a third initialization signal line; the sub-pixel driving circuit further includes: a third reset transistor, a first electrode of the third reset transistor being coupled to the third initialization signal line, and a second electrode of the third reset transistor being coupled to the first electrode of the driving transistor; The first scan line further includes a second reset line, the scan line segment further includes a second reset line segment, and the second reset line segment is coupled to a gate of a corresponding third reset transistor belonging to the same sub-display area.

20. The display substrate according to claim 19, wherein The display substrate further includes a first initialization signal line; the sub-pixel driving circuit further includes: a first reset transistor and a first reset line, wherein a first electrode of the first reset transistor is coupled to the corresponding initialization signal line, a second electrode of the first reset transistor is coupled to the second electrode of the driving transistor, and a gate of the first reset transistor is coupled to the corresponding first reset line; At least a portion of the first initialization signal line is located in a space between adjacent second reset line segments.

21. The display substrate according to claim 13, wherein The display substrate further comprises: a power line, a first initialization signal line, a second initialization signal line, a third initialization signal line and a cathode layer; The power lines located in different sub-display areas are independent of each other; and / or, The first initialization signal lines located in different sub-display areas are independent of each other; and / or, The second initialization signal lines located in different sub-display areas are independent of each other; and / or, The third initialization signal lines located in different sub-display areas are independent of each other; and / or, The cathode layers in different sub-display areas are independent of each other.

22. A display device comprising the display substrate according to any one of claims 1 to 21.

23. A method for manufacturing a display substrate, for manufacturing the display substrate according to any one of claims 1 to 21, wherein the display substrate comprises a base substrate, the base substrate comprising a display area and a peripheral area located around the display area, the display area comprising: at least two sub-display areas; The production method comprises: Producing a plurality of scan lines, the plurality of scan lines including a plurality of first scan lines, the first scan lines including at least two independent scan line segments, the at least two scan line segments being located in different sub-display areas; A plurality of sub-pixels are produced, and the plurality of sub-pixels are divided into a plurality of rows of sub-pixels, and the plurality of rows of sub-pixels include a target row of sub-pixels, and the target row of sub-pixels can be divided into at least two groups of sub-pixel groups, and the at least two groups of sub-pixel groups are located in different sub-display areas, and the scan line segments are respectively coupled to the sub-pixels in the corresponding sub-pixel groups belonging to the same sub-display area.

24. The method for manufacturing a display substrate according to claim 23, wherein: The steps of manufacturing a plurality of sub-pixels specifically include: Producing non-target row sub-pixels, wherein all sub-pixels included in the same row of non-target row sub-pixels are located in the same sub-display area; The steps for making multiple scan lines include: A plurality of second scan lines are manufactured, wherein the second scan lines are respectively coupled to the corresponding sub-pixels in the non-target row of sub-pixels.

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