Array substrate, array motherboard, light-emitting substrate, backlight module, and display device

Abstract

An array substrate (10). A relief opening (101) is formed at an edge of the array substrate (10), and the orthographic projection of the relief opening (101) on a first reference plane has a first edge. The array substrate (10) comprises a base substrate (11') and at least one positioning structure (12). The at least one positioning structure (12) is arranged on one side of the base substrate (11'). The positioning structure (12) comprises a body portion (124), and the body portion (124) is substantially parallel with the first edge. The first reference plane is a plane where the surface of the base substrate away from the positioning structure (12) is located.

Description

Array substrate, array motherboard, light-emitting substrate, backlight module and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to an array substrate, an array motherboard, a light-emitting substrate, a backlight module, and a display device. Background Art

[0002] With the development of light-emitting diode (LED) technology, backlight sources using submillimeter or even micron-scale light-emitting diodes (LEDs) have become widely used. This not only allows products using these backlights, such as liquid crystal displays (LCDs), to achieve contrast levels comparable to those of organic light-emitting diode (OLED) displays, but also allows these products to retain the technical advantages of LCDs, thereby improving display quality and providing users with a superior visual experience.

[0003] Summary of the Invention

[0004] In one aspect, an array substrate is provided. An edge of the array substrate is provided with a clearance opening, and an orthographic projection of the clearance opening onto a first reference plane has a first edge. The array substrate includes a substrate and at least one positioning structure. The at least one positioning structure is disposed on a side of the substrate. The positioning structure includes a main body that is substantially parallel to the first edge. The first reference plane is a plane of the substrate surface that is distal to the positioning structure.

[0005] In some embodiments, a first side of an orthographic projection of the avoidance opening on the first reference plane is an arc, and an orthographic projection of the positioning structure on the first reference plane is an arc.

[0006] In some embodiments, the positioning structure further includes ends located at both ends of the main body, and the ends of the positioning structure are substantially parallel to corresponding boundaries of the array substrate.

[0007] In some embodiments, the main body of the positioning structure surrounds the avoidance opening, and the avoidance opening is located between two ends of the positioning structure.

[0008] In some embodiments, the array substrate further comprises a first conductive metal layer, a first insulating layer, and a second conductive metal layer. The first conductive metal layer is disposed on one side of the substrate; the first conductive metal layer comprises a plurality of signal lines. The first insulating layer is disposed on a side of the first conductive metal layer away from the substrate; the first insulating layer is provided with a first via that penetrates the first insulating layer. The second conductive metal layer is disposed on a side of the first insulating layer away from the substrate; the second conductive metal layer comprises a plurality of conductive portions and a plurality of adapter wires; the adapter wires are connected to the conductive portions and are in electrical contact with the signal lines through the first vias. The positioning structure is located in any one of the first conductive metal layer, the second conductive metal layer, and the first insulating layer.

[0009] In some embodiments, the first insulating layer includes a first sub-insulating layer and a second sub-insulating layer that are stacked, and the first sub-insulating layer is closer to the first conductive metal layer than the second sub-insulating layer.

[0010] In some embodiments, the array substrate further comprises a second insulating layer disposed on a side of the second conductive metal layer away from the substrate. A second via hole is defined in the second insulating layer, extending through the second insulating layer; the second via hole exposes at least a portion of the conductive portion. The positioning structure is located in any one of the first conductive metal layer, the second conductive metal layer, the first insulating layer, and the second insulating layer.

[0011] In some embodiments, the array substrate further includes an alignment mark layer disposed between the first conductive metal layer and the substrate; the alignment mark layer includes at least one alignment mark. The positioning structure is located in any one of the first conductive metal layer, the second conductive metal layer, the first insulating layer, and the alignment mark layer. If the array substrate includes a second insulating layer, the positioning structure is located in any one of the first conductive metal layer, the second conductive metal layer, the first insulating layer, the second insulating layer, and the alignment mark layer.

[0012] In some embodiments, a side of the main portion of the positioning structure close to the avoidance opening is exposed by the avoidance opening, and the positioning structure is located in the first insulating layer. When the array substrate includes a second insulating layer, the positioning structure is located in the first insulating layer or the second insulating layer.

[0013] In some embodiments, the array substrate includes a plurality of positioning structures, and the plurality of positioning structures are made of the same material and are disposed in the same layer.

[0014] In another aspect, an array motherboard is provided. The array motherboard includes a plurality of array daughter boards, each of which includes a light-emitting area and a test area. The test area is located on at least one side of the light-emitting area. The test area includes a functional device placement area and a peripheral area, with the boundary between the peripheral area and the functional device placement area being a first dividing line.

[0015] The array sub-board includes a substrate motherboard and at least one positioning structure. The at least one positioning structure is arranged on the substrate motherboard and is located in the test area. The positioning structure includes a main body, and the main body is substantially parallel to the first dividing line. At least part of the main body of at least one positioning structure is located in the array area. The maximum distance between the boundary of the main body of the positioning structure located in the peripheral area and the first dividing line is greater than a first preset value and less than or equal to a second preset value. The first preset value is the process accuracy of excluding the part of the array sub-board located in the functional device setting area; the second preset value is the minimum distance between the light-emitting area and the first dividing line.

[0016] In some embodiments, the first dividing line is arc-shaped, and the positioning structure further includes ends located at both ends of the main body, and the ends of the positioning structure are substantially parallel to the corresponding boundaries of the array sub-board.

[0017] In some embodiments, the main body portion is positioned in the peripheral area as a first positioning structure. The main body portion is positioned in the functional device placement area as a second positioning structure. The main body portion is partially positioned in the peripheral area and partially positioned in the functional device placement area as a third positioning structure.

[0018] The main body of the first positioning structure surrounds the first dividing line, and the first dividing line is located between the two ends of the first positioning structure. The first dividing line surrounds the main body of the second positioning structure, and the first dividing line is located between the two ends of the second positioning structure. The main body of the third positioning structure covers the first dividing line, and the first dividing line is located between the two ends of the third positioning structure.

[0019] In some embodiments, the array daughterboard includes multiple positioning structures, each end of which is substantially parallel to a corresponding boundary of the array daughterboard. Among the multiple positioning structures, the ends of the positioning structures furthest from the center of the array substrate extend to the boundary of the array daughterboard, and the ends of the positioning structures are substantially flush with the boundary of the array daughterboard. Furthermore, / or, the same ends of the multiple positioning structures are connected to form a first line segment, and the straight line on which the first line segment lies intersects and is substantially perpendicular to the boundary of the peripheral area.

[0020] In some embodiments, the array daughterboard includes a plurality of positioning structures, and the orthographic projection of the boundary of the main portion of at least one of the plurality of positioning structures on a second reference plane substantially coincides with the orthographic projection of the first dividing line on the second reference plane. The second reference plane is a plane on which a surface of the substrate motherboard away from the positioning structures lies.

[0021] In some embodiments, the array motherboard includes a first metal film, a first insulating film, a second metal film, and a second insulating film. The first metal film is disposed on one side of the substrate motherboard; the first metal film includes a plurality of signal lines. The first insulating film is disposed on a side of the first metal film away from the substrate motherboard. The first insulating film has a first via extending through the first insulating film.

[0022] The second metal film is disposed on a side of the first insulating film away from the substrate motherboard; the second metal film includes multiple conductive portions and multiple adapter wires; the adapter wires are connected to the conductive portions and electrically contact the signal lines through the first vias. The second insulating film is disposed on a side of the second metal film away from the substrate motherboard; the second insulating film is provided with a second via extending through the second insulating film; the second via exposes at least a portion of the conductive portion. The positioning structure is located on any one of the first metal film, the second metal film, the first insulating film, and the second insulating film.

[0023] In some embodiments, the positioning structure of the main body portion located in the peripheral region is a first positioning structure. The positioning structure of the main body portion located in the functional device placement region is a second positioning structure. The positioning structure of a portion of the main body portion located in the peripheral region and another portion located in the functional device placement region is a third positioning structure. The first positioning structure is located in any one of the first metal film, the second metal film, the first insulating film, and the second insulating film. The second positioning structure is located in either the first insulating film or the second insulating film. The third positioning structure is located in either the first insulating film or the second insulating film.

[0024] In another aspect, a light-emitting substrate is provided. The light-emitting substrate comprises the array substrate described in any one of the above embodiments and a plurality of electronic devices. The plurality of electronic devices are disposed on the array substrate.

[0025] In another aspect, a backlight module is provided. The backlight module includes the above-mentioned light-emitting substrate and a plurality of optical films. The light-emitting substrate has a light-emitting side and a non-light-emitting side opposite to each other. The plurality of optical films are disposed on the light-emitting side of the light-emitting substrate.

[0026] In another aspect, a display device is provided. The display device includes the aforementioned backlight module, a functional device, and a display panel. The functional device is disposed in an avoidance opening of the array substrate. The display panel is disposed on a side of the plurality of optical films in the backlight module that is away from the light-emitting substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] To more clearly illustrate the technical solutions of the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below are schematic diagrams and are not intended to limit the actual dimensions of the products, actual processes of the methods, actual timing of signals, and the like involved in the embodiments of the present disclosure.

[0028] FIG1 is a structural diagram of a display device according to some embodiments;

[0029] FIG2 is a structural diagram of another display device according to some embodiments;

[0030] FIG3 is a structural diagram of another display device according to some embodiments;

[0031] FIG4 is a cross-sectional view of a display device according to some embodiments;

[0032] FIG5 is a circuit diagram of a light emitting substrate according to some embodiments;

[0033] FIG6 is a top view of a light emitting substrate according to some embodiments;

[0034] FIG7 is a top view of a partial layout of a light-emitting substrate according to some embodiments;

[0035] FIG8 is a structural diagram of an array substrate according to some embodiments;

[0036] FIG9 is a structural diagram of another array substrate according to some embodiments;

[0037] FIG10 is a structural diagram of another array substrate according to some embodiments;

[0038] FIG11A is a partial enlarged view of an avoidance opening of an array substrate according to some embodiments;

[0039] FIG11B is a cross-sectional view along section line AA′ in FIG11A;

[0040] FIG11C is another cross-sectional view along section line AA′ in FIG11A ;

[0041] FIG11D is another cross-sectional view along section line AA′ in FIG11A ;

[0042] FIG12 is a partial enlarged view of an avoidance opening of another array substrate according to some embodiments;

[0043] FIG13A is a partial enlarged view of an avoidance opening of another array substrate according to some embodiments;

[0044] FIG13B is a cross-sectional view taken along section line BB′ in FIG13A;

[0045] FIG14 is a cross-sectional view of an array substrate according to some embodiments;

[0046] FIG15 is a structural diagram of an array motherboard according to some embodiments;

[0047] FIG16A is a structural diagram of an array daughter board according to some embodiments;

[0048] FIG16B is a cross-sectional view taken along section line CC′ in FIG16A;

[0049] FIG17 is a structural diagram of another array daughter board according to some embodiments;

[0050] FIG18 is a partial enlarged view of a functional device arrangement area of ​​an array substrate according to some embodiments;

[0051] FIG19 is a partial enlarged view of a functional device arrangement area of ​​another array substrate according to some embodiments;

[0052] FIG20 is a partial enlarged view of a functional device arrangement area of ​​another array substrate according to some embodiments;

[0053] FIG21 is a partial enlarged view of point M in FIG20;

[0054] FIG. 22 is a cross-sectional view of an array motherboard according to some embodiments. DETAILED DESCRIPTION

[0055] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, rather than all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0056] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and its other forms, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open and inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" are intended to indicate that the particular features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the particular features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0057] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0058] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. The term "connected" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium. The term "coupled" indicates, for example, that two or more components are in direct physical or electrical contact. The term "coupled" or "communicatively coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0059] “At least one of A, B and C” has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B and C.

[0060] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0061] The use of "adapted to" or "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0062] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0063] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0064] As used herein, "parallel," "perpendicular," and "equal" include the stated conditions and conditions that are similar to the stated conditions, within an acceptable range of deviations as determined by one of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "equal" includes both absolute equality and approximate equality, where the acceptable range of deviations for approximate equality may include, for example, a difference between two conditions that is less than or equal to 5% of either condition.

[0065] It will be understood that when a layer or element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present therebetween.

[0066] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0067] As shown in FIG. 1 , some embodiments of the present disclosure provide a display device 1000 , which may be any device that displays an image, whether in motion (eg, video) or stationary (eg, still image), and whether textual or graphic.

[0068] For example, referring to Figures 1, 2 and 3, the display device 1000 can be any product or component with a display function, such as a television, a laptop computer, a tablet computer, a mobile phone, a personal digital assistant (PDA), a navigator, a wearable device, a virtual reality (VR) device, etc.

[0069] The display device 1000 may be a liquid crystal display (LCD) or a mini / micro light emitting display (Mini / Micro Light Emitting Display), etc., which is not specifically limited in the embodiments of the present disclosure.

[0070] The following takes the display device 1000 as a liquid crystal display device as an example to schematically illustrate some embodiments of the present disclosure, but the implementation of the present disclosure is not limited to this, and any other display device 1000 can also be considered as long as the same technical concept is applied.

[0071] In some embodiments, referring to FIG. 4 , a display device 1000 includes a display panel 100 .

[0072] As shown in FIG4 , the display panel 100 includes a light-emitting side and a non-light-emitting side that are disposed opposite each other. The light-emitting side refers to the side of the display panel 100 used for displaying images (the upper side of the display panel 100 in FIG4 ), and the non-light-emitting side refers to the side opposite the light-emitting side (the lower side of the display panel 100 in FIG4 ).

[0073] It is understandable that, depending on different application scenarios, the shape of the surface of the light-emitting side of the display panel 100 is not unique.

[0074] For example, as shown in Figures 1 and 2, the display device 1000 may be a portable display product, which may be a mobile phone as shown in Figures 1 or 2. In this case, the shape of the surface of the light-emitting side of the display panel 100 is substantially rectangular.

[0075] In this document, "substantially rectangular" means that the shape is generally rectangular, but is not limited to a standard rectangle. That is, "rectangular" here includes not only substantially rectangular shapes but also shapes similar to rectangles. For example, the long and short sides of a rectangle are curved at each intersection (i.e., at the corners), meaning the corners are smooth and the shape is a rounded rectangle. For example, some segments of the long and short sides of a rectangle are curved.

[0076] For another example, as shown in Figure 3, the display device 1000 may be a wearable device, and the wearable device may be a round watch as shown in Figure 3. In this case, the shape of the surface of the light-emitting side of the display panel 100 is substantially circular or elliptical.

[0077] In this article, "substantially circular or elliptical" means that the shape is circular or elliptical as a whole, but is not limited to a standard circular or elliptical shape. That is, the "circular or elliptical" here includes not only a substantially circular or elliptical shape, but also a shape similar to a circular or elliptical shape.

[0078] The following uses the display device 1000 as a bar phone and the shape of the surface of the light-emitting side of the display panel 100 is approximately rectangular as an example to schematically illustrate some embodiments of the present disclosure, but the embodiments of the present disclosure are not limited thereto.

[0079] Exemplarily, referring to FIG. 1 to FIG. 4 , the display device 1000 further includes a backlight module 200 , a glass cover 300 and a functional device 400 .

[0080] As shown in Figures 1 to 3, the functional device 400 includes at least one of an image sensor, an optical sensor, an acoustic sensor, a distance sensor, etc. For example, the functional device 400 includes at least one of a camera, an earpiece, a flash, an infrared sensor, a proximity sensor, an eye tracking module, and a face recognition module.

[0081] The following uses the functional device 400 as an example to schematically illustrate some embodiments of the present disclosure. However, the implementation of the present disclosure is not limited to this, and any other functional device 400 can also be considered as long as the same technical concept is applied.

[0082] As shown in FIG. 4 , the backlight module 200 is disposed on the non-light-emitting side of the display panel 100 . The backlight module 200 is used to provide light source for the display panel 100 .

[0083] 4 , the glass cover 300 is disposed on the light-emitting side of the display panel 100 to protect the display panel 100. For example, the glass cover 300 may be made of rigid materials such as glass, quartz, and plastic, or flexible materials such as polymer resin.

[0084] In some examples, please continue to refer to FIG. 4 , the backlight module 200 includes a light-emitting substrate 210 and a plurality of optical films 220 .

[0085] As shown in Figure 4, the light-emitting substrate 210 has a light-emitting side and a non-light-emitting side relative to each other. The light-emitting side refers to the side of the light-emitting substrate 210 that provides a light source (the upper side of the light-emitting substrate 210 in Figure 4), and the non-light-emitting side refers to the other side opposite to the light-emitting side (the lower side of the light-emitting substrate 210 in Figure 4).

[0086] It should be understood that the surface shape of the light-emitting side of the light-emitting substrate 210 should be substantially the same as the surface shape of the light-emitting side of the display panel 100. That is, if the surface shape of the light-emitting side of the display panel 100 is substantially circular or elliptical, the surface shape of the light-emitting side of the light-emitting substrate 210 should also be substantially circular or elliptical. If the surface shape of the light-emitting side of the display panel 100 is substantially rectangular, the surface shape of the light-emitting side of the light-emitting substrate 210 should also be substantially rectangular.

[0087] As shown in FIG. 4 , a plurality of optical films 220 are disposed on the light emitting side of the light emitting substrate 210 .

[0088] The light-emitting substrate 210 can directly emit white light, which is then homogenized by the multiple optical films 220 and then emitted toward the display panel 100. Alternatively, the light-emitting substrate 210 can also emit light of other colors (e.g., blue light), which is then color-converted and homogenized by the multiple optical films 220 and then emitted toward the display panel 100.

[0089] For example, referring to FIG. 4 , along a direction perpendicular to the light emitting substrate 210 and away from the light emitting substrate 210 , the plurality of optical films 220 include a diffuser 221 , a quantum dot film 222 , a diffuser 223 and a composite film 224 that are sequentially arranged.

[0090] The diffuser 221 blurs the light emitted by the light-emitting substrate 210 and provides support for the quantum dot film 222, diffuser 223, and composite film 224. The quantum dot film 222, when stimulated by light of a certain color emitted by the light-emitting substrate 210, converts that light into white light, thereby improving the utilization of the light energy of the light-emitting substrate 210. The diffuser 223 evens out the light passing through it. The composite film 224 improves the light extraction efficiency of the backlight module 200, thereby increasing the display brightness of the display device 1000.

[0091] It should be noted that the composite film 224 may include a brightness enhancement film (BEF) and a reflective polarized brightness enhancement film (DBEF), which utilizes the principles of total reflection, refraction, and polarization to increase the light flux within a certain angle range to improve the brightness of the display device 1000.

[0092] For example, the light-emitting substrate 210 emits blue light in a direction away from the light-emitting substrate 210. The quantum dot film 222 may include a red quantum dot material, a green quantum dot material, and a transparent material. When the blue light emitted by the light-emitting substrate 210 passes through the red quantum dot material, it is converted into red light; when the blue light passes through the green quantum dot material, it is converted into green light; the blue light can directly pass through the transparent material; then, the blue light, red light, and green light are mixed and superimposed in a certain proportion to present white light. Finally, the diffuser 221 and the diffuser sheet 223 can mix the white light evenly to improve the light shadow produced by the light-emitting substrate 210 and improve the display quality of the display device 1000.

[0093] In some embodiments, referring to FIG. 6 , the light-emitting substrate 210 has a light-emitting area A1 and a test area A2 located at at least one side of the light-emitting area A1 .

[0094] Exemplarily, as shown in FIG6 , the light-emitting substrate 210 further has a binding area A3 , and the test area A2 and the binding area A3 are respectively located on two opposite sides of the light-emitting area A1 .

[0095] The light-emitting substrate 210 includes an array substrate 10 and an electronic component 20 . The electronic component 20 is disposed on the array substrate 10 and located in the light-emitting area A1 .

[0096] Exemplarily, referring to FIG. 4 , the electronic component 20 may be electrically connected to the pads on the array substrate 10 to be fixed on the array substrate 10 .

[0097] 4 , the electronic component 20 may include a light emitting device 21 and / or a microchip 22 .

[0098] As shown in FIG4 , the light emitting device 21 may include a Micro LED and a Mini LED. The size (e.g., length) of the Micro LED is less than 50 μm, for example, 10 μm to 50 μm. The size (e.g., length) of the Mini LED is 50 μm to 150 μm, for example, 80 μm to 120 μm.

[0099] As shown in FIG4 , the microchip 22 may include a sensor chip and a driver chip. The sensor chip may be, for example, a photosensor chip or a thermal sensor chip, etc. The driver chip is used to provide a driving signal to the light emitting device 21 .

[0100] As shown in FIG5 , FIG6 and FIG7 , the light emitting substrate 210 includes a plurality of driving units 211 arranged in an array, and each driving unit 211 includes a plurality of light emitting devices 21 connected in series and / or in parallel.

[0101] For example, as shown in Figures 5, 6, and 7, each driving unit 211 includes four light-emitting devices 21 connected in series. Of course, each driving unit 211 may also include four, five, seven, or eight light-emitting devices 21, and the connection mode of the multiple light-emitting devices 21 in the driving unit 211 is not limited to series connection, but may also be parallel connection, but the embodiments of the present disclosure are not limited thereto.

[0102] The microchip 22 may be a driver chip, for example, to drive the plurality of light-emitting devices 21 to emit light. Here, one microchip 22 may only drive the plurality of light-emitting devices 21 in one driver unit 211 to emit light, or one microchip 22 may drive the plurality of light-emitting devices 21 in a plurality of driver units 211 to emit light.

[0103] 5 and 6 , every four driving units 211 are electrically connected to a microchip 22 , and the microchip 22 is electrically connected to the multiple light-emitting devices 21 in the four driving units 211 , respectively, to drive the multiple light-emitting devices 21 in the four driving units 211 to emit light.

[0104] As shown in Figures 1 to 3, the functional device 400 can be disposed in the middle of the upper end of the array substrate 10. As shown in Figure 2, the functional device 400 can also be disposed at the left or right corner of the upper end of the array substrate 10. Of course, the functional device 400 can also be disposed in other locations on the array substrate 10, and this is not specifically limited in the present embodiment.

[0105] In related technologies, interference occurs between functional components and the array substrate during system assembly, causing them to squeeze each other, resulting in deformation of the array substrate or failure of the functional components. Therefore, preventing interference between the array substrate and functional components is a currently unresolved issue.

[0106] To reduce manufacturing costs, as shown in Figure 15 , an array substrate 10 (see Figure 9 ) is typically obtained from an array motherboard 100 ′ through processes such as cutting. Some embodiments of the present disclosure provide an array motherboard 100 ′ comprising a plurality of array daughterboards 10 ′. The array daughterboards 10 ′ include a light-emitting area A1 and a test area A2 . The test area A2 includes a functional device placement area A21 and a peripheral area A22 .

[0107] 9 and 15 , the portion of the array sub-board 10 ′ located in the peripheral area A22 is a reserved portion of the array sub-board 10 ′ to form the required array substrate 10 .

[0108] Referring to Figures 9 and 15, the portion of the array sub-board 10' located in the functional device setting area A22 is the portion of the array sub-board 10' that needs to be removed to form an avoidance opening 101, thereby avoiding interference between the functional device 400 and the array substrate 10, avoiding extrusion between the functional device 400 (see Figure 2) and the array substrate 10, and reducing the risk of deformation of the array substrate 10 or failure of the functional device.

[0109] 16A , the functional device placement area A21 is located at the edge of the peripheral area A22 , and the boundary between the peripheral area A22 and the functional device placement area A21 is a first boundary line L1 .

[0110] The shape of the functional device placement area A21 may be set according to the shape and position of the functional device 400 .

[0111] For example, referring to FIG. 16A and FIG. 17 , the first dividing line L1 is substantially any one of a C-shape, a U-shape, and an arc shape.

[0112] For example, as shown in FIG16A , the first dividing line L1 is substantially arc-shaped. For another example, as shown in FIG17 , the first dividing line L1 is substantially U-shaped.

[0113] In this article, "substantially arc-shaped" means that the shape is arc-shaped as a whole, but is not limited to a standard arc-shaped. That is, the "arc-shaped" here includes not only a basic arc-shaped shape, but also a shape similar to an arc-shaped shape.

[0114] The following takes the example of the first dividing line L1 being substantially arc-shaped to schematically illustrate some embodiments of the present disclosure, but the embodiments of the present disclosure are not limited thereto.

[0115] The area of ​​the functional device placement region A21 may be set according to the area and shape of the functional device 400 .

[0116] In some examples, the distance between the two ends of the first dividing line L1 ranges from 15 mm to 25 mm. For example, the distance between the two ends of the first dividing line L1 is any one of 15 mm, 16 mm, 16.5 mm, 17 mm, 18 mm, 18.7 mm, 19 mm, 19.5 mm, 20 mm, 20.1 mm, 20.5 mm, 21 mm, 21.3 mm, 22 mm, 22.5 mm, 23 mm, 23.5 mm, 24 mm, 24.5 mm, and 25 mm, which is not specifically limited in the embodiments of the present disclosure.

[0117] In some examples, the distance between the two ends of the first dividing line L1 ranges from 60 mm to 70 mm. For example, the distance between the two ends of the first dividing line L1 is any one of 60 mm, 60.5 mm, 61 mm, 62.1 mm, 63.5 mm, 64 mm, 64.3 mm, and 65 mm, which is not specifically limited in the embodiments of the present disclosure.

[0118] In some examples, the maximum distance between the portion of the array daughter board 10' corresponding to the functional device placement area A21 and the first dividing line L1 ranges from 1 mm to 2 mm. For example, the maximum distance between the portion of the array daughter board 10' corresponding to the functional device placement area A21 and the first dividing line L1 is any one of 1 mm, 1.1 mm, 1.2 mm, 1.3 mm, 1.35 mm, 1.355 mm, 1.4 mm, 1.45 mm, 1.5 mm, 1.6 mm, 1.7 mm, 1.8 mm, 1.9 mm, and 2 mm, which is not specifically limited in the embodiments of the present disclosure.

[0119] The array motherboard 100 ′ can be preliminarily divided by a cutting process to obtain a plurality of array daughter boards 10 ′; and then the functional device arrangement area A21 of the array daughter boards 10 ′ is removed to obtain the array substrate 10 having the avoidance opening 101 .

[0120] For example, referring to Figures 15, 16A, 16B and 17, the portion of the array sub-plate 10' located in the functional device setting area A21 can be removed through a grinding process using a grinding tool. Before this step, the edge of the array sub-plate 10' can be ground to form a chamfer structure 110, thereby increasing the strength of the array sub-plate 10' and avoiding cracks in the process of removing the functional device setting area A21 of the array sub-plate 10'.

[0121] The distance between the orthographic projections of two opposing edges of the chamfered structure 110 on the second reference surface may be, for example, in the range of 250 μm to 350 μm. For example, the distance between the orthographic projections of two opposing edges of the chamfered structure 110 on the second reference surface is any one of 250 μm, 260 μm, 270 μm, 280 μm, 290 μm, 300 μm, 310 μm, 320 μm, 330 μm, 340 μm, and 350 μm, which is not specifically limited in the present embodiment.

[0122] It should be noted that the second reference plane is a plane where the surface of the array motherboard 100 ′ away from the display panel 100 is located.

[0123] In some embodiments, referring to FIG. 16A and FIG. 17 , the array daughter board 10 ′ includes a substrate motherboard 11 ′ and at least one positioning structure 12 .

[0124] As shown in Figures 16A and 17, the substrate motherboard 11' can be any one of a glass substrate, a quartz substrate, a sapphire substrate, a ceramic substrate, etc.; or any one of a semiconductor substrate such as a single crystal semiconductor substrate or a polycrystalline semiconductor substrate made of silicon or silicon carbide, a compound semiconductor substrate such as silicon germanium, a silicon-on-insulator substrate, etc.; the substrate motherboard 11' can also be a film layer made of one or more organic resin materials such as epoxy resin, triazine, silicone resin and polyimide.

[0125] As shown in Figures 16A and 17 , the positioning structure 12 is disposed on the substrate motherboard 11 ′ and is located in the test area A2 . The positioning structure 12 includes a main body 124 , which is substantially parallel to the first boundary line L1 .

[0126] The main body 124 described in the embodiment of the present disclosure is roughly parallel to the first dividing line L1, which means that the main body 124 and the first dividing line L1 are both intercepted by the first reference line, and the difference in the corresponding angles does not exceed 2°; the point where the first reference line intersects the first dividing line L1 is the first intersection, and the first reference line is perpendicular to the tangent line at the first intersection.

[0127] For example, referring to FIG18 , at least one positioning structure 12 has a main portion 124 located in the peripheral area A22. The positioning structure 12 having the main portion 124 located in the peripheral area A22 is the first positioning structure 121. The main portion 124 of the first positioning structure 121 is close to or away from the boundary of the functional device placement area A21 and is substantially parallel to the first boundary line L1.

[0128] For example, referring to Figures 20 and 21 , at least one positioning structure 12 has a main portion 124 located in functional device placement area A21. The positioning structure 12 having main portion 124 located in functional device placement area A21 is a second positioning structure 122. The main portion 124 of the second positioning structure 122 is located close to or away from the boundary of array area B and is substantially parallel to the first boundary line L1.

[0129] For example, referring to Figures 20 and 21 , at least one positioning structure 12 has a main portion 124 partially located in the peripheral area A22 and another portion located in the functional device placement area A21. The positioning structure 12 with a portion of the main portion 124 located in the peripheral area A22 and another portion located in the functional device placement area A21 is a third positioning structure 123. The main portion 124 of the third positioning structure 123 is located at the boundary between the functional device placement area A21 and the peripheral area A22, and is generally parallel to the first boundary line L1.

[0130] The positioning structure 12 is substantially a strip-shaped structure with uniform width, and the shape of the positioning structure 12 can be designed according to the first dividing line L1 .

[0131] For example, referring to FIG. 16A to FIG. 20 , the orthographic projection of the main body 124 of the positioning structure 12 on the second reference plane is any one of a straight line, a U-shape, a U-shape, and an arc.

[0132] For example, as shown in FIG. 17 , the orthographic projection of the first dividing line L1 on the second reference plane is substantially U-shaped, and the orthographic projection of the main body 124 of the positioning structure 12 on the second reference plane is substantially U-shaped.

[0133] For another example, as shown in FIG. 16A and FIG. 18 , the orthographic projection of the first dividing line L1 on the second reference plane is substantially arc-shaped, and the orthographic projection of the main body 124 of the positioning structure 12 on the second reference plane is substantially arc-shaped.

[0134] In the following, some embodiments of the present disclosure are schematically described by taking the example that the orthographic projection of the main body 124 of the positioning structure 12 on the second reference plane is substantially arc-shaped, but the embodiments of the present disclosure are not limited thereto.

[0135] At this time, as shown in Figures 16A and 18 , when the orthographic projection of the main body 124 of the positioning structure 12 on the second reference plane is substantially arc-shaped, the positioning structure 12 may further include, for example, end portions 125 located at both ends of the main body 124. The end portions 125 of the positioning structure 12 may be substantially parallel to the corresponding boundaries of the array daughter board 10 ′, so as to facilitate obtaining the distance between the positioning structure 12 and the corresponding boundaries of the array daughter board 10 ′, i.e., the distance indicated by the positioning structure 12.

[0136] The width of the positioning structure 12 can be set according to actual conditions. For example, the width of the positioning structure 12 ranges from 5 μm to 50 μm. For example, the width of the positioning structure 12 is any one of 5 μm, 10 μm, 15 μm, 20 μm, 25 μm, 30 μm, 35 μm, 40 μm, 45 μm, and 50 μm, which is not specifically limited in the present embodiment.

[0137] It should be understood that during the lapping process to remove the portion of the array daughterboard 10' located in the functional device placement area A21, the lapping boundary is approximately parallel to the first dividing line L1, meaning that the positioning structure 12 is approximately parallel to the lapping boundary. Therefore, the actual lapping amount can be determined by obtaining the distance between the positioning structure 12 and the lapping boundary and subtracting the distance between the positioning structure 12 and the lapping boundary from the distance indicated by the positioning structure 12.

[0138] At least a portion of the main body 124 of at least one positioning structure 12 is located in the peripheral area A22 , and the maximum distance between the boundary of the positioning structure 12 in the peripheral area A22 and the first dividing line L1 is greater than the first preset value and less than or equal to the second preset value.

[0139] It should be noted that the main portion 124 of the positioning structure 12 can have a single boundary within the peripheral area A22, i.e., the main portion 124 of the positioning structure 12 is completely within the peripheral area A22. The positioning structure 12 can also have two boundaries within the peripheral area A22, i.e., the main portion 124 of the positioning structure 12 is partially within the peripheral area A22 and partially within the functional device placement area A21.

[0140] When the positioning structure 12 is completely located in the peripheral area A22, the maximum distance is the distance between the boundary of the positioning structure 12 in the peripheral area A22 and the first dividing line L1. When the positioning structure 12 is partially located in the peripheral area A22 and partially located in the functional device placement area A21, the maximum distance is the distance between the boundary of the positioning structure 12 away from the first dividing line L1 and the first dividing line L1.

[0141] The first preset value is the process accuracy for removing the portion of the array daughterboard 10' located in the functional device placement area A21. For example, the first preset value ranges from 0.02 mm to 0.1 mm. For example, the first preset value can be any one of 0.02 mm, 0.03 mm, 0.04 mm, 0.05 mm, 0.06 mm, 0.07 mm, 0.08 mm, 0.09 mm, and 0.1 mm, which is not specifically limited in the present embodiment.

[0142] The second preset value is the minimum distance between the light-emitting area A1 and the first dividing line L1. For example, the second preset value ranges from 0.4 mm to 0.6 mm. For example, the second preset value is any one of 0.4 mm, 0.45 mm, 0.46 mm, 0.48 mm, 0.5 mm, 0.52 mm, 0.55 mm, 0.58 mm, and 0.6 mm. This is not specifically limited in the present embodiment.

[0143] In this case, the actual grinding amount of the grinding process can be obtained through the positioning structure 12, and the actual grinding amount can be compared with the preset grinding amount, so that unqualified products whose actual grinding amount is not within the preset grinding amount range can be eliminated, thereby preventing the outflow of unqualified products. In addition, by obtaining the actual grinding amount of the grinding process in real time, the grinding equipment can be monitored. When the actual grinding amount is not within the preset grinding amount range, the grinding equipment can be adjusted in time to ensure that the actual grinding amount meets the preset grinding amount requirement, thereby improving the product yield.

[0144] The preset grinding amount can be, for example, the maximum distance between the portion of the boundary of the array sub-board 10' corresponding to the functional device placement area A21 and the first dividing line L1. Exemplarily, the preset grinding amount is 1 mm to 2 mm. For example, the preset grinding amount is 1.3 mm to 1.4 mm, which is not specifically limited in the present embodiment.

[0145] In this case, the range of the preset grinding amount can be, for example, a range formed by the maximum distance and the grinding process accuracy (i.e., the first preset value). For example, the preset grinding amount is 1 mm, the first preset value is 0.05 mm, and the range of the preset grinding amount is 0.95 mm to 1.05 mm. The embodiments of the present disclosure are not limited to this.

[0146] 18 , at the same marking distance, only one positioning structure 12 may be provided. Referring to FIG19 , at the same marking distance, multiple positioning structures 12 may also be provided at intervals.

[0147] Here, in the case where multiple positioning structures 12 are arranged at intervals at the same identification distance, as shown in Figure 19, among the multiple positioning structures 12, the positioning structure 12 located at the edge can also include an end 125, for example. The end 125 is located at the end of the main body 124 of the positioning structure 12 away from the other positioning structures 12, and the end 125 can be roughly parallel to the boundary corresponding to the array sub-board 10', so as to obtain the distance between the positioning structure 12 and the boundary corresponding to the array sub-board 10', that is, the distance identified by the positioning structure 12.

[0148] The following takes the example of providing only one positioning structure 12 at the same marking distance to schematically illustrate some embodiments of the present disclosure, but the embodiments of the present disclosure are not limited thereto.

[0149] In some examples, as shown in FIG. 18 , the main body 124 of the first positioning structure 121 may surround a first dividing line L1 , for example, and the first dividing line L1 is located between two ends 125 of the first positioning structure 121 .

[0150] In this way, during the process of removing the portion of the array sub-board 10' located within the area enclosed by the first positioning structure 121 through the grinding process, a corresponding first positioning structure 121 exists at any point of the grinding boundary, which facilitates the collection of the distance between the first positioning structure 121 and the grinding boundary.

[0151] In some examples, referring to FIG. 20 and FIG. 21 , the first dividing line L1 may, for example, surround the main body 124 of the second positioning structure 122 , and the first dividing line L1 is located between the two ends 125 of the second positioning structure 122 .

[0152] In this way, in the process of removing the portion of the array sub-board 10' located within the area enclosed by the second positioning structure 122 through the grinding process, there is a corresponding second positioning structure 122 at any point of the grinding boundary, which facilitates the collection of the distance between the second positioning structure 122 and the grinding boundary.

[0153] In some examples, referring to FIG. 20 and FIG. 21 , the main body 124 of the third positioning structure 123 may, for example, cover the first dividing line L1 , and the first dividing line L1 is located between the two ends 125 of the third positioning structure 123 .

[0154] In this way, in the process of removing the portion of the array sub-board 10' located within the area enclosed by the third positioning structure 123 through the grinding process, there is a corresponding third positioning structure 123 at any point of the grinding boundary, which facilitates the collection of the distance between the third positioning structure 123 and the grinding boundary.

[0155] The length of the positioning structure 12 can be set according to the length of the first dividing line L1.

[0156] In some examples, the distance between the two ends of the positioning structure 12 ranges from 16 mm to 30 mm. For example, the distance between the two ends of the positioning structure 12 is any one of 16 mm, 17 mm, 17.5 mm, 18 mm, 19 mm, 19.7 mm, 20 mm, 20.5 mm, 21 mm, 21.1 mm, 21.5 mm, 22 mm, 22.3 mm, 23 mm, 23.5 mm, 24 mm, 24.5 mm, 25 mm, 25.5 mm, 26 mm, 27 mm, 28 mm, 29 mm, and 30 mm, which is not specifically limited in the embodiments of the present disclosure.

[0157] In some examples, the distance between the two ends of the positioning structure 12 ranges from 61 mm to 75 mm. For example, the distance between the two ends of the positioning structure 12 is any one of 61 mm, 61.5 mm, 62 mm, 63.1 mm, 64.5 mm, 65 mm, 65.3 mm, 65.6 mm, 66 mm, 67 mm, 67.5 mm, 68 mm, 69 mm, and 70 mm.

[0158] In some embodiments, as shown in FIG18 , the array daughterboard 10 ′ includes a positioning structure 12 . The positioning structure 12 is located in the peripheral area A22 , and the maximum distance between the boundary of the positioning structure 12 and the first dividing line L1 is greater than a first predetermined value. For example, the first predetermined value is 0.05 mm, and the maximum distance between the boundary of the positioning structure 12 and the first dividing line L1 is 0.06 mm.

[0159] In other embodiments, as shown in Figures 20 and 21, the array sub-board 10' includes a plurality of positioning structures 12, and among the plurality of positioning structures 12, there is at least one group of two adjacent positioning structures 12 whose spacing is not equal to the spacing between another group of two adjacent positioning structures 12.

[0160] For example, as shown in Figures 20 and 21, the array daughterboard 10' includes six positioning structures 12. The spacing between the six positioning structures 12 increases in a stepwise manner from the outside of the array daughterboard 10' toward the inside. For example, from the outside of the array daughterboard 10' toward the inside, the spacing between adjacent two positioning structures 12 is 0.03mm, 0.05mm, 0.05mm, 0.07mm, and 0.11mm, respectively.

[0161] In some examples, as shown in FIG21 , among the plurality of positioning structures 12 , the two ends of the positioning structure 12 farthest from the center of the array sub-board 10 ′ extend to the boundary of the array sub-board 10 ′, and the end 125 of the positioning structure 12 is substantially flush with the boundary of the array sub-board 10 ′.

[0162] In some examples, as shown in FIG21 , the same end of multiple positioning structures 12 is connected to form a first line segment L2. The line on which the first line segment L2 is located intersects the boundary of the peripheral area A22 and is substantially perpendicular. Substantially perpendicular includes absolutely perpendicular and approximately perpendicular. The acceptable deviation range of approximately perpendicular can also be, for example, within 3°.

[0163] In some examples, as shown in FIG21 , among the plurality of positioning structures 12 , the orthographic projection of the boundary of the main body 124 of at least one positioning structure 12 on the second reference plane substantially coincides with the orthographic projection of the first dividing line L1 on the second reference plane.

[0164] It should be noted that the second reference plane is the plane where the surface of the substrate motherboard 11 ′ away from the positioning structure 12 is located.

[0165] In some embodiments, referring to FIG. 22 , the array motherboard 100 ′ includes a first metal film 13 ′, a first insulating film 14 ′, a second metal film 15 ′, and a second insulating film 16 ′.

[0166] 22 , a first metal film 13 ′ is disposed on one side of the substrate motherboard 11 ′. The first metal film 13 ′ is made of at least one of copper, aluminum, and silver.

[0167] 5 and 22 , the first metal film 13 ′ includes a plurality of signal lines 130 , which may include, for example, a device power signal line 131 , a common voltage line 132 , a data signal line 133 , a clock signal line 134 , a feedback signal line 135 , an address signal line 136 and a chip power signal line 137 .

[0168] 22 , the first insulating film 14 ′ is disposed on a side of the first metal film 13 ′ away from the substrate motherboard 11 ′. The first insulating film 14 ′ is provided with a first via hole 140 penetrating the first insulating film 14 ′. The first insulating film 14 ′ is made of resin, for example, epoxy resin.

[0169] In some examples, as shown in FIG. 22 , the first insulating film 14 ′ includes a first sub-insulating film 141 ′ and a second sub-insulating film 142 ′ that are stacked, and the first sub-insulating film 141 ′ is closer to the first metal film 13 ′ than the second sub-insulating film 142 ′.

[0170] Arranged in this way, the first sub-insulating film 141' and the second sub-insulating film 142' can be formed separately in a two-step process, and the microcracks generated in the first sub-insulating film 141' and the second sub-insulating film 142' during the process are dislocated, thereby reducing the risk of microcracks penetrating the first insulating film 14' and reducing the risk of water vapor intrusion.

[0171] 22 , the second metal film 15 ′ is disposed on a side of the first insulating film 14 ′ away from the substrate motherboard 11 ′. The second metal film 15 ′ is made of at least one of copper, aluminum, and silver.

[0172] The second metal film 15 ′ includes a plurality of conductive portions 151 and a plurality of adapter lines 152 . The adapter lines 152 are connected to the conductive portions 151 and are electrically connected to the signal lines 131 through the first vias 140 .

[0173] 6, 7, and 22, the plurality of conductive portions 151 may include, for example, a device conductive portion 1511, a chip conductive portion 1512, a testing portion 1513, and a binding portion 1514. The device conductive portion 1511 and the chip conductive portion 1512 are located in the light emitting area A1, the testing portion 1513 is located in the testing area A2, and the binding portion 1514 is located in the binding area A3.

[0174] At this time, referring to FIG. 7 , the positioning structure 12 may be located in the test area A2 , for example, and between two adjacent binding portions 1514 .

[0175] Exemplarily, referring to FIG. 6 and FIG. 7 , the plurality of patch cords 152 may include, for example, a first patch cord 1521 , a second patch cord 1522 , a third patch cord 1523 , a fourth patch cord 1524 and a fifth patch cord 1525 .

[0176] As shown in Figures 6 and 7, one end of the first patch cord 1521 can be connected to, for example, a signal line 130, and the other end can be connected to a device conductive portion 1511. One end of the second patch cord 1522 can be connected to, for example, a device conductive portion 1511, and the other end can be connected to another device conductive portion 1511. One end of the third patch cord 1523 can be connected to, for example, a device conductive portion 1511, and the other end can be connected to a chip conductive portion 1512. One end of the fourth patch cord 1524 can be connected to, for example, a signal line 130, and the other end can be connected to a chip conductive portion 1512. One end of the fifth patch cord 1525 can be connected to, for example, a signal line 130, and the other end can be connected to a test portion 1513.

[0177] Referring to FIG. 22 , a second insulating film 16 ′ is disposed on a side of the second metal film 15 ′ away from the substrate motherboard 11 ′. A second via 161 is defined through the second insulating film 16 ′, exposing at least a portion of the conductive portion 151 . The second insulating film 16 ′ is made of a resin, such as epoxy resin.

[0178] It should be noted that the portion of the conductive portion 151 exposed by the second via hole 161 forms a pad.

[0179] Based on the above, referring to FIG. 20 and FIG. 22 , the positioning structure 12 may be located in any one of the first metal film 13 ′, the second metal film 15 ′, the first insulating film 14 ′, and the second insulating film 16 ′.

[0180] For example, referring to Figures 20 and 22 , the first positioning structure 121 is located on any one of the first metal film 13 ′, the second metal film 15 ′, the first insulating film 14 ′, and the second insulating film 16 ′. The second positioning structure 122 is located on the first insulating film 14 ′ or the second insulating film 16 ′. The third positioning structure 123 is located on the first insulating film 14 ′ or the second insulating film 16 ′.

[0181] It should be understood that during the process of removing the portion of the array daughter board 10 ′ located within the area surrounded by the third positioning structure 123 , the positioning structures 12 located in the functional device placement area A22 , ie, the second positioning structure 122 and the third positioning structure 123 , will be removed simultaneously.

[0182] Based on this, referring to Figures 20 and 22, the second positioning structure 122 and the third positioning structure 123 are located on the first insulating film 14' or the second insulating film 16'. When the second positioning structure 122 and the third positioning structure 123 are exposed to the polished surface, water and oxygen corrosion can still be prevented, thereby improving the reliability of the obtained array substrate 10.

[0183] In some embodiments, referring to FIG. 22 , the array motherboard 100 ′ includes an alignment mark film 17 ′ disposed between the first metal film 13 ′ and the substrate motherboard 11 ′. The alignment mark film 17 ′ is made of a metal or a dark-colored material (e.g., black, brown, tan, green, etc.). For example, the alignment mark film 17 ′ includes at least one of molybdenum, titanium, and niobium. Alternatively, the alignment mark film 17 ′ may include at least one of a dark resin and a dark ink.

[0184] As shown in FIG. 22 , the alignment mark film 17 ′ includes at least one alignment mark 171 , so that alignment can be performed by capturing an image of the alignment mark 171 during the process.

[0185] At this time, referring to FIG. 20 and FIG. 22 , the first positioning structure 121 , the second positioning structure 122 , and the third positioning structure 123 may also be located on the alignment mark film 17 ′.

[0186] When the array daughter board 10' includes multiple positioning structures 12, all positioning structures 12 can be made of the same material and disposed on the same layer to reduce production costs. Of course, different positioning structures 12 can also be located on different layers, which is not specifically limited in this embodiment of the disclosure.

[0187] In addition, when the array sub-board 10' includes a positioning structure 12, and the positioning structure 12 is located in the peripheral area A22, the positioning structure 12 can, for example, be located in any one of the first metal film 13', the second metal film 15' and the alignment mark film 17', so as to facilitate the detection of the distance between the positioning structure 12 and the grinding boundary by automatic optical detection equipment.

[0188] Some embodiments of the present disclosure provide an array substrate 10 , which can be obtained from the above-mentioned array motherboard 100 ′ through processes such as cutting.

[0189] Referring to Figures 9 and 10, at least one avoidance opening 101 is provided at the edge of the array substrate 10, and the above-mentioned functional device 400 is arranged at the avoidance opening 101 of the array substrate 10 to avoid interference between the functional device 400 and the array substrate 10, avoid extrusion between the functional device 400 and the array substrate 10, and reduce the risk of deformation of the array substrate 10 or failure of the functional device.

[0190] In some examples, referring to FIG. 13A and FIG. 13B , the surface of the avoidance opening 101 formed by the grinding process is perpendicular to the plane of the array substrate 10 , and the orthographic projection of the avoidance opening 101 on the first reference plane has a first side L11 .

[0191] It should be noted that the first reference plane is the plane where the surface of the array substrate 10 away from the display panel 100 is located, and the first reference plane and the second reference plane mentioned above are the same plane.

[0192] In other examples, referring to Figures 11A, 11B, 11C, and 11D, the surface of the avoidance opening 101 formed by the grinding process has an inclined surface or a curved surface. The orthographic projection of the surface of the avoidance opening 101 on the first reference plane has two first sides L11. In this case, the distance between the two first sides L11 ranges from approximately 50 μm to 150 μm. For example, the distance between the two first sides L11 ranges from 50 μm, 60 μm, 70 μm, 80 μm, 90 μm, 100 μm, 110 μm, 120 μm, 130 μm, 140 μm, and 150 μm. This is not specifically limited in the embodiments of the present disclosure.

[0193] The shape of the avoidance opening 101 can be set according to the shape and position of the functional device 400 .

[0194] Exemplarily, referring to FIG. 9 and FIG. 10 , the first side L11 of the orthographic projection of the avoidance opening 101 on the first reference plane is substantially any one of a C-shape, a U-shape, and an arc shape.

[0195] For example, as shown in FIG. 9 , a first side L11 of an orthographic projection of the avoidance opening 101 on the first reference plane is substantially arc-shaped.

[0196] In this context, "substantially arc-shaped" refers to an overall arc-shaped shape, but is not limited to a standard arc. Specifically, "arc-shaped" here encompasses not only curves with uniform curvature throughout but also smooth curves. It will be appreciated that in the actual preparation of the avoidance opening, methods such as grinding or laser cutting may be employed. In some cases, the resulting first side L11 may be a plurality of end-to-end connected broken line segments with a substantially arc-shaped shape.

[0197] For another example, as shown in FIG10 , the first side L11 of the orthographic projection of the avoidance opening 101 on the first reference plane is substantially U-shaped.

[0198] In the following, some embodiments of the present disclosure are schematically described by taking the example that the first side L11 of the orthographic projection of the avoidance opening 101 on the first reference plane is substantially arc-shaped, but the embodiments of the present disclosure are not limited thereto.

[0199] The area of ​​the avoidance opening 101 can be set according to the area and shape of the functional device 400 .

[0200] In some examples, the distance between the two ends of the first side L11 of the orthographic projection of the avoidance opening 101 on the first reference plane ranges from 15 mm to 25 mm. For example, the distance between the two ends of the boundary of the avoidance opening 101 is any one of 15 mm, 16 mm, 16.5 mm, 17 mm, 18 mm, 18.7 mm, 19 mm, 19.5 mm, 20 mm, 20.1 mm, 20.5 mm, 21 mm, 21.3 mm, 22 mm, 22.5 mm, 23 mm, 23.5 mm, 24 mm, 24.5 mm, and 25 mm, which is not specifically limited in the embodiments of the present disclosure.

[0201] In some examples, the distance between the ends of the first side L11 of the orthographic projection of the avoidance opening 101 on the first reference plane ranges from 60 mm to 70 mm. For example, the distance between the ends of the first dividing line L1 is any one of 60 mm, 60.5 mm, 61 mm, 62.1 mm, 63.5 mm, 64 mm, 64.3 mm, and 65 mm, which is not specifically limited in the embodiments of the present disclosure.

[0202] In some examples, the maximum distance between the portion of the array daughter board 10' corresponding to the functional device placement area A21 and the boundary of the avoidance opening 101 ranges from 1 mm to 2 mm. For example, the maximum distance between the portion of the array daughter board 10' corresponding to the functional device placement area A21 and the boundary of the avoidance opening 101 is any one of 1 mm, 1.1 mm, 1.2 mm, 1.3 mm, 1.35 mm, 1.355 mm, 1.4 mm, 1.45 mm, 1.5 mm, 1.6 mm, 1.7 mm, 1.8 mm, 1.9 mm, and 2 mm, which is not specifically limited in the embodiments of the present disclosure.

[0203] 9 and 10 , an edge of the array substrate 10 may be provided with a clearance opening 101. Referring to FIG8 , the edge of the array substrate 10 may also be provided with multiple clearance openings 101. Each clearance opening 101 may be provided with multiple functional devices 400 or a single functional device 400.

[0204] In some examples, as shown in FIG. 1 and FIG. 10 , an edge of the array substrate 10 is provided with an escape opening 101 , and a plurality of functional devices 400 are disposed in the escape opening 101 .

[0205] In other examples, as shown in FIG. 2 and FIG. 8 , five avoidance openings 101 are provided on the edge of the array substrate 10 , and one functional device 400 is disposed in one avoidance opening 101 .

[0206] As shown in FIG. 8 , along the extending direction of the edge of the array substrate 10 , the distance between two adjacent avoidance openings 101 ranges from 100 mm to 120 mm.

[0207] For example, along the extension direction of the edge of the array substrate 10, the spacing between two adjacent avoidance openings is any one of 100mm, 101mm, 104mm, 105mm, 108mm, 110mm, 113mm, 115mm, 117mm, 118mm and 120mm, which is not specifically limited in the embodiments of the present disclosure.

[0208] Furthermore, when the array substrate 10 is substantially rectangular, as shown in FIG8 , the plurality of avoidance openings 101 can be disposed on the same edge of the array substrate 10. Furthermore, the distance between two avoidance openings 101 located on opposite sides of the plurality of avoidance openings 101 and the other adjacent edges is in the range of 10 mm to 20 mm.

[0209] For example, the distance between two avoidance openings 101 located on opposite sides among the multiple avoidance openings 101 and the other adjacent edges is any one of 10mm, 11mm, 12.5mm, 14mm, 15mm, 15.5mm, 16mm, 17.5mm, 18mm, 18.5mm, 19mm and 20mm, which is not specifically limited in the embodiments of the present disclosure.

[0210] In the following, some embodiments of the present disclosure are schematically described by taking an example in which an avoidance opening 101 is provided at the edge of the array substrate 10 , but the embodiments of the present disclosure are not limited thereto.

[0211] 8 to 10 , the array substrate 10 includes a substrate 11 and at least one positioning structure 12. Here, the first reference plane is the plane where the surface of the substrate 11 of the array substrate 10 away from the positioning structure 12 is located.

[0212] It should be noted that the material of the substrate 11 can refer to the substrate motherboard 11 ′ mentioned above, and will not be described in detail in the embodiment of the present disclosure.

[0213] As shown in FIG8 to FIG10 , the positioning structure 12 is disposed on one side of the substrate 11 . The positioning structure 12 includes a main body 124 . The main body 124 is substantially parallel to the first side L11 .

[0214] Here, "main body 124 is substantially parallel to first side L11" means that both main body 124 and first side L11 are intersected by a second reference line, and the difference in their corresponding angles does not exceed 2°. The point where the second reference line intersects the first side L11 is a second intersection point, and the second reference line is perpendicular to the tangent line at the second intersection point.

[0215] It should be noted that the shape of the positioning structure 12 can be referred to above, and will not be described in detail in the embodiment of the present disclosure.

[0216] As shown in FIG9 and FIG11A , when the orthographic projection of the main body 124 of the positioning structure 12 on the second reference plane is substantially arc-shaped, the positioning structure 12 may further include, for example, end portions 125 located at both ends of the main body 124. The end portions 125 of the positioning structure 12 may be substantially parallel to the corresponding boundaries of the array substrate 10, so as to facilitate obtaining the distance between the positioning structure 12 and the corresponding boundaries of the array substrate 10, that is, the distance marked by the positioning structure 12.

[0217] In this manner, the distance between the positioning structure 12 and the boundary of the avoidance opening 101 can be obtained, and the distance indicated by the positioning structure 12 can be subtracted from the distance between the positioning structure 12 and the boundary of the avoidance opening 101 to obtain the position of the boundary of the avoidance opening 101. In this case, the position of the boundary of the avoidance opening 101 is compared with the range of the preset grinding amount, so that unqualified products whose avoidance opening 101 is not in the preset position can be rejected, thereby preventing unqualified products from being outflowed.

[0218] It should be noted that the range of the preset grinding amount can be referred to above, and the embodiments of the present disclosure will not be elaborated here.

[0219] 11A , at the same marking distance, only one positioning structure 12 may be provided. Referring to FIG12 , at the same marking distance, multiple positioning structures 12 may also be provided at intervals.

[0220] Here, in the case where a plurality of positioning structures 12 are spaced apart at the same identification distance, as shown in FIG12 , among the plurality of positioning structures 12, the positioning structure 12 located at the edge may further include an end portion 125, for example. The end portion 125 is located at an end of the main body 124 of the positioning structure 12 away from the other positioning structures 12, and the end portion 125 may be roughly parallel to the boundary corresponding to the array substrate 10, so as to obtain the distance between the positioning structure 12 and the boundary corresponding to the array substrate 10, that is, the distance identified by the positioning structure 12.

[0221] The following takes the example of providing only one positioning structure 12 at the same marking distance to schematically illustrate some embodiments of the present disclosure, but the embodiments of the present disclosure are not limited thereto.

[0222] In some examples, as shown in FIG11A , the main body 124 of the positioning structure 12 can surround the avoidance opening 101, and the avoidance opening 101 is located between the two ends 125 of the positioning structure 12. In this manner, a corresponding positioning structure 12 is present at any location along the boundary of the avoidance opening 101, facilitating the acquisition of the distance between the positioning structure 12 and the boundary of the avoidance opening 101.

[0223] In some embodiments, referring to Figure 11A , the array substrate 10 includes one positioning structure 12. In other embodiments, referring to Figure 13A , the array substrate 10 includes multiple positioning structures 12. Figure 13A illustrates an example in which the array substrate 10 includes two positioning structures 12.

[0224] In some embodiments, referring to FIG. 14 , the array substrate 10 includes a first conductive metal layer 13 , a first insulating layer 14 , and a second conductive metal layer 15 .

[0225] 14 , a first conductive metal layer 13 is disposed on one side of the substrate 11. The material of the first conductive metal layer 13 includes at least one of copper, aluminum, and silver.

[0226] 5 and 14 , the first conductive metal layer 13 includes a plurality of signal lines 130. The plurality of signal lines 130 may be specifically described above and will not be described in detail in the present embodiment.

[0227] 14 , the first insulating layer 14 is disposed on a side of the first conductive metal layer 13 away from the substrate 11. The first insulating layer 14 is provided with a first via 140 penetrating the first insulating layer 14. The first insulating layer 14 is made of resin, for example, epoxy resin.

[0228] In some examples, as shown in FIG. 14 , the first insulating layer 14 includes a first sub-insulating layer 141 and a second sub-insulating layer 142 that are stacked. The first sub-insulating layer 141 is closer to the first conductive metal layer 13 than the second sub-insulating layer 142 .

[0229] Arranged in this manner, the first sub-insulating layer 141 and the second sub-insulating layer 142 can be formed separately in a two-step process, and the microcracks generated in the first sub-insulating layer 141 and the second sub-insulating layer 142 during the process are dislocated, thereby reducing the risk of microcracks penetrating the first insulating layer 14 and reducing the risk of water vapor infiltration.

[0230] 14 , the second conductive metal layer 15 is disposed on a side of the first insulating layer 14 away from the substrate 11. The second conductive metal layer 15 is made of at least one of copper, aluminum, and silver.

[0231] The second conductive metal layer 15 includes a plurality of conductive parts 151 and a plurality of adapter lines 152. The conductive parts 151 and the adapter lines 152 are described above in detail, and are not described in detail in the embodiment of the present disclosure.

[0232] Based on the above, referring to FIG. 13A and FIG. 14 , the positioning structure 12 is located in any one of the first conductive metal layer 13 , the second conductive metal layer 15 and the first insulating layer 14 .

[0233] For example, referring to Figures 13A and 14, the main body 124 of the positioning structure 12 is exposed by the avoidance opening 101 on one side close to the avoidance opening 101. The positioning structure 12 can be located in the first insulating layer 14, for example. In this way, when the positioning structure 12 is exposed to the polished surface, it can still prevent water and oxygen corrosion, thereby improving the reliability of the array substrate 10.

[0234] It should be noted that the main body 124 of the positioning structure 12 may not be exposed in the avoidance opening 101. In this case, the positioning structure 12 may be located in any one of the first conductive metal layer 13, the second conductive metal layer 15 and the first insulating layer 14, which is not specifically limited in the present embodiment.

[0235] In some embodiments, referring to FIG. 14 , the array substrate 10 further includes a first passivation layer 181 , a second passivation layer 182 and a third passivation layer 183 .

[0236] As shown in FIG14 , the first passivation layer 181 is disposed between the first conductive metal layer 13 and the first insulating layer 14. The second passivation layer 182 is disposed between the second conductive metal layer 15 and the first insulating layer 14. The third passivation layer 183 is disposed on the side of the second conductive metal layer 15 away from the substrate 11.

[0237] The materials of the first, second and third passivation layers 181, 182 and 183 may include at least one of inorganic insulating materials such as silicon nitride, silicon oxynitride and silicon oxide.

[0238] In some embodiments, referring to FIG. 14 , the array substrate 10 further comprises a second insulating layer 16 disposed on a side of the second conductive metal layer 15 away from the substrate 11 . A second via 161 is defined through the second insulating layer 16 , exposing at least a portion of the conductive portion 151 . The material of the second insulating layer 16 comprises a resin, for example, the material of the second insulating film 16 ′ comprises epoxy resin.

[0239] In this case, the positioning structure 12 may also be located in the second insulating layer 16. For example, referring to FIG14 , a side of the main body 124 of the positioning structure 12 close to the avoidance opening 101 is exposed by the avoidance opening 101. The positioning structure 12 may be located in the second insulating layer 16, so that even when the positioning structure 12 is exposed to the polished surface, it can still prevent water and oxygen corrosion, thereby improving the reliability of the array substrate 10.

[0240] In some examples, referring to Figures 13A and 14, the positioning structure 12 is located in the first conductive metal layer 13, and at least one of the first insulating layer 14, the first passivation layer 181, the second passivation layer 182, the third passivation layer 183 and the second insulating layer 16 covers the test area A2 (see Figure 6) to avoid exposure of the positioning structure 12, thereby reducing the risk of static electricity generated by the positioning structure 12.

[0241] In other examples, referring to Figures 13A and 14, the positioning structure 12 is located in the first conductive metal layer 13, and the first insulating layer 14, the first passivation layer 181, the second passivation layer 182, the third passivation layer 183, and the second insulating layer 16 are, for example, all located in the light-emitting area A1 (see Figure 6), while the test area A2 (see Figure 6) is exposed. On this basis, the array substrate 10 may further include a third insulating layer that covers the positioning structure 12 to prevent the positioning structure 12 from being exposed, thereby reducing the risk of static electricity generated by the positioning structure 12.

[0242] In some examples, referring to FIG. 13A and FIG. 14 , the positioning structure 12 is located in the second conductive metal layer 15 , and the third passivation layer 183 and / or the second insulating layer 16 cover the test area A2 to prevent the positioning structure 12 from being exposed, thereby reducing the risk of static electricity generated by the positioning structure 12 .

[0243] In other examples, referring to Figures 13A and 14 , the positioning structure 12 is located on the second conductive metal layer 15 , and the third passivation layer 183 and the second insulating layer 16 are both provided in the light-emitting area A1 (see Figure 6 ), while the test area A2 (see Figure 6 ) is exposed. On this basis, the array substrate 10 may further include a third insulating layer that covers the positioning structure 12 to prevent the positioning structure 12 from being exposed, thereby reducing the risk of static electricity generated by the positioning structure 12 .

[0244] In some embodiments, referring to FIG. 14 , the array substrate 10 further includes an alignment mark layer 17 disposed between the first conductive metal layer 13 and the substrate 11. The material of the alignment mark layer 17 can be a material having high reflectivity or a non-transparent color easily visible in visible light, such as a metal or a dark material. For example, the material of the alignment mark layer 17 includes at least one of molybdenum, titanium, and niobium. The material of the alignment mark film 17' can also include at least one of a dark resin or a dark ink.

[0245] As shown in FIG. 14 , the alignment mark layer 17 includes at least one alignment mark 171 , so that alignment can be performed by capturing an image of the alignment mark 171 during the process.

[0246] At this time, the positioning structure 12 may also be located on the alignment mark layer 17 .

[0247] Wherein, when the array substrate 10 includes multiple positioning structures 12, all positioning structures 12 can be made of the same material and disposed on the same layer to reduce production costs. Of course, different positioning structures 12 can also be located on different layers, which is not specifically limited in the present embodiment.

[0248] In addition, when the array substrate 10 includes a positioning structure 12, the positioning structure 12 can, for example, be located in any one of the first conductive metal layer 13, the second conductive metal layer 15 and the alignment mark layer 17, so as to facilitate detection of the distance between the positioning structure 12 and the boundary of the avoidance opening 101 by automatic optical detection equipment.

[0249] In some embodiments, referring to FIG. 14 , the array substrate 10 further includes a buffer layer 19 . The buffer layer 19 is disposed between the alignment mark layer 17 and the substrate 11 to buffer and protect the substrate 11 .

[0250] The material of the buffer layer 19 includes an inorganic insulating material. Exemplarily, the material of the buffer layer 19 includes silicon oxide and / or silicon nitride. For example, the material of the buffer layer 19 includes silicon nitride.

[0251] In the description of this specification, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0252] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that a person skilled in the art can conceive within the technical scope disclosed in the present disclosure should be included within the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. An array substrate, wherein: The edge of the array substrate is provided with an avoidance opening, and the orthographic projection of the avoidance opening on the first reference plane has a first side. The array substrate comprises: substrate; At least one positioning structure is arranged on one side of the substrate; the positioning structure comprises a main body, the main body is substantially parallel to the first side; the first reference plane is a plane where a surface of the substrate away from the positioning structure is located.

2. The array substrate according to claim 1, wherein: The first side of the orthographic projection of the avoidance opening on the first reference plane is an arc, and the orthographic projection of the positioning structure on the first reference plane is an arc.

3. The array substrate according to claim 2, wherein: The positioning structure further includes end portions located at two ends of the main body, and the end portions of the positioning structure are substantially parallel to the boundaries corresponding to the array substrate.

4. The array substrate according to claim 3, wherein: The main body of the positioning structure surrounds the avoidance opening, and the avoidance opening is located between two ends of the positioning structure.

5. The array substrate according to any one of claims 1 to 4, further comprising: A first conductive metal layer is disposed on one side of the substrate; the first conductive metal layer includes a plurality of signal lines; A first insulating layer is provided on a side of the first conductive metal layer away from the substrate; the first insulating layer is provided with a first via hole penetrating the first insulating layer; A second conductive metal layer is disposed on a side of the first insulating layer away from the substrate; the second conductive metal layer comprises a plurality of conductive parts and a plurality of adapter wires; the adapter wires are connected to the conductive parts and are in electrical contact with the signal wires through the first vias; Wherein, the positioning structure is located in any one of the first conductive metal layer, the second conductive metal layer and the first insulating layer.

6. The array substrate according to claim 5, wherein: The first insulating layer includes a first sub-insulating layer and a second sub-insulating layer that are stacked, and the first sub-insulating layer is closer to the first conductive metal layer than the second sub-insulating layer.

7. The array substrate according to claim 5 or 6, further comprising: A second insulating layer is disposed on a side of the second conductive metal layer away from the substrate; The second insulating layer is provided with a second via hole penetrating through the second insulating layer; The second via hole exposes at least a portion of the conductive portion; Wherein, the positioning structure is located in any one of the first conductive metal layer, the second conductive metal layer, the first insulating layer and the second insulating layer.

8. The array substrate according to any one of claims 5 to 7, further comprising: An alignment mark layer is disposed between the first conductive metal layer and the substrate; the alignment mark layer includes at least one alignment mark; Wherein, the positioning structure is located in any one of the first conductive metal layer, the second conductive metal layer, the first insulating layer and the alignment mark layer; when the array substrate includes a second insulating layer, the positioning structure is located in any one of the first conductive metal layer, the second conductive metal layer, the first insulating layer, the second insulating layer and the alignment mark layer.

9. The array substrate according to any one of claims 5 to 8, wherein: A side of the main body of the positioning structure close to the avoidance opening is exposed by the avoidance opening, and the positioning structure is located in the first insulating layer; In the case that the array substrate includes a second insulating layer, the positioning structure is located in the first insulating layer or the second insulating layer.

10. The array substrate according to any one of claims 1 to 9, wherein: The array substrate comprises a plurality of positioning structures, and the plurality of positioning structures are made of the same material and are arranged in the same layer.

11. An array motherboard, comprising a plurality of array daughter boards, wherein the array daughter boards comprise a light-emitting area and a test area, wherein the test area is located at least on one side of the light-emitting area; the test area comprises a functional device setting area and a peripheral area; The boundary between the peripheral area and the functional device setting area is a first dividing line; The array daughter board comprises: Substrate motherboard; At least one positioning structure is arranged on the substrate motherboard and is located in the test area; the positioning structure includes a main body, and the main body is roughly parallel to the first dividing line; there is at least one positioning structure with at least part of its main body located in the peripheral area, and the maximum distance between the boundary of the main body of the positioning structure located in the peripheral area and the first dividing line is greater than a first preset value and less than or equal to a second preset value; the first preset value is the process accuracy of removing the part of the array sub-board located in the functional device setting area; the second preset value is the minimum distance between the light-emitting area and the first dividing line.

12. The array motherboard according to claim 11, wherein: The first dividing line is arc-shaped, and the positioning structure further includes ends located at two ends of the main body, and the ends of the positioning structure are substantially parallel to the boundaries corresponding to the array sub-board.

13. The array motherboard according to claim 12, wherein: The positioning structure in which the main body is located in the peripheral area is a first positioning structure; the positioning structure in which the main body is located in the functional device setting area is a second positioning structure; the positioning structure in which a part of the main body is located in the peripheral area and another part is located in the functional device setting area is a third positioning structure; The main body of the first positioning structure surrounds the first dividing line, and the first dividing line is located between two ends of the first positioning structure; The first dividing line surrounds the main body of the second positioning structure, and the first dividing line is located between two ends of the second positioning structure; The main body of the third positioning structure covers the first dividing line, and the first dividing line is located between two ends of the third positioning structure.

14. The array motherboard according to claim 12 or 13, wherein: The array sub-board includes a plurality of positioning structures; Among the multiple positioning structures, both ends of the positioning structure farthest from the center of the array sub-board extend to the boundary of the array sub-board, and the end of the positioning structure is roughly flush with the boundary of the array sub-board; and / or, the same end of the multiple positioning structures is connected to form a first line segment, and the straight line where the first line segment is located intersects with the boundary of the peripheral area and is roughly perpendicular.

15. The array motherboard according to any one of claims 11 to 14, wherein: The array sub-board includes a plurality of positioning structures, among which there is at least one positioning structure whose main body boundary has an orthographic projection on a second reference plane that roughly coincides with the orthographic projection of the first dividing line on the second reference plane; the second reference plane is a plane where the surface of the substrate motherboard away from the positioning structure is located.

16. The array motherboard according to any one of claims 11 to 15, comprising: A first metal film is disposed on one side of the substrate motherboard; the first metal film includes a plurality of signal lines; A first insulating film is arranged on a side of the first metal film away from the substrate motherboard; the first insulating film is provided with a first via hole penetrating the first insulating film; A second metal film is disposed on a side of the first insulating film away from the substrate motherboard; the second metal film comprises a plurality of conductive parts and a plurality of adapter wires; the adapter wires are connected to the conductive parts and are in electrical contact with the signal wires through the first vias; A second insulating film is provided on a side of the second metal film away from the substrate motherboard; the second insulating film is provided with a second via hole penetrating the second insulating film; the second via hole exposes at least a part of the conductive portion; The positioning structure is located in any one of the first metal film, the second metal film, the first insulating film and the second insulating film.

17. The array motherboard according to claim 16, wherein: The positioning structure in which the main body is located in the peripheral area is a first positioning structure; the positioning structure in which the main body is located in the functional device setting area is a second positioning structure; the positioning structure in which a part of the main body is located in the peripheral area and another part is located in the functional device setting area is a third positioning structure; The first positioning structure is located in any one of the first metal film, the second metal film, the first insulating film, and the second insulating film; The second positioning structure is located at the first insulating film or the second insulating film; and the third positioning structure is located at the first insulating film or the second insulating film.

18. A light-emitting substrate, comprising: The array substrate according to any one of claims 1 to 10; A plurality of electronic devices are arranged on the array substrate.

19. A backlight module, comprising: The light-emitting substrate as claimed in claim 18, wherein the light-emitting substrate has a light-emitting side and a non-light-emitting side opposite to each other; A plurality of optical films are arranged on the light emitting side of the light emitting substrate.

20. A display device, comprising: The backlight module as claimed in claim 19; A functional device is arranged at the avoidance opening of the array substrate of the backlight module; The display panel is arranged on a side of the plurality of optical films in the backlight module away from the light-emitting substrate.

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