Array substrate, shift register unit, and display device

Abstract

An array substrate, a shift register unit, and a display device. The array substrate comprises data lines (210), gate lines (220), first control signal lines (310), and sub-pixels (100). Each sub-pixel (100) comprises a first sub-pixel portion (110) and a second sub-pixel portion (120), the first sub-pixel portion (110) comprises a first pixel electrode (111), and the second sub-pixel portion (120) comprises a second pixel electrode (121); the first sub-pixel portion (110) comprises a first transistor (114), and the first transistor (114) is connected to the first pixel electrode (111); the second sub-pixel portion (120) comprises a second transistor (123) and a third transistor (124), and the second transistor (123) and the third transistor (124) are connected to the second pixel electrode (121); the first transistor (114) and the second transistor (123) are connected to the same gate line (220) and the same data line (210), and the third transistor (124) is connected to the corresponding first control signal line (310). The array substrate further comprises second control signal lines (320), the second sub-pixel portion (120) further comprises an adjustable capacitor (125), the adjustable capacitor (125) is connected to the third transistor (124), and each second control signal line (320) is connected to the corresponding adjustable capacitor (125) to apply a voltage to change the capacitance value of the adjustable capacitor (125), thereby facilitating alleviation of the color shift phenomenon at a large viewing angle.

Description

Array substrate, shift register unit and display device Technical Field

[0001] Embodiments of the present disclosure relate to an array substrate, a shift register unit, and a display device. Background Art

[0002] Liquid crystal displays (LCDs) are a common display product used today. They consist of two stacked substrates with a liquid crystal layer located between them. With technological advancements, demands for improved display performance and performance are increasing, such as high- and low-refresh rate compatibility, low-temperature startup capability, and wide-viewing-angle display.

[0003] Summary of the Invention

[0004] Embodiments of the present disclosure provide an array substrate, a shift register unit, and a display device.

[0005] An embodiment of the present disclosure provides an array substrate, comprising: a base substrate; a plurality of sub-pixels located on the base substrate, the plurality of sub-pixels being arranged in an array along a first direction and a second direction, the first direction intersecting the second direction; a plurality of data lines located on the base substrate and arranged along the first direction; a plurality of gate lines located on the base substrate and arranged along the second direction; and a plurality of first control signal lines located on the base substrate and arranged along the second direction. Each sub-pixel in at least some of the sub-pixels includes a first sub-pixel portion and a second sub-pixel portion arranged along the second direction, the first sub-pixel portion includes a first pixel electrode, the second sub-pixel portion includes a second pixel electrode, the first pixel electrode and the second pixel electrode are arranged at intervals, and the first sub-pixel portion and the second sub-pixel portion share a common electrode; the first sub-pixel portion includes a first transistor, the first electrode of the first transistor is connected to the first pixel electrode, the second sub-pixel portion includes a second transistor and a third transistor, the first electrode of the second transistor and the first electrode of the third transistor are both connected to the second pixel electrode, the control electrode of the first transistor and the control electrode of the second transistor are both connected to the same gate line, the second electrode of the first transistor and the second electrode of the second transistor are both connected to the same data line, and the control electrode of the third transistor is connected to the first control signal line. The array substrate also includes a second control signal line, and the second sub-pixel portion also includes an adjustable capacitor, the first electrode of the adjustable capacitor is connected to the second electrode of the third transistor, and the second control signal line is connected to the second electrode of the adjustable capacitor to apply a voltage to change the capacitance value of the adjustable capacitor; a semiconductor layer and an insulating layer are arranged between the first electrode of the adjustable capacitor and the second electrode of the adjustable capacitor, and the semiconductor layer, the active layer of the first transistor, the active layer of the second transistor and the active layer of the third transistor are all arranged in the same layer; a first protrusion is provided on the side of the second pixel electrode close to the first pixel electrode, and a second protrusion is provided on the side of the second electrode of the adjustable capacitor close to the second pixel electrode, and the first control signal line includes a bent portion located between the first protrusion and the second protrusion.

[0006] For example, according to an embodiment of the present disclosure, the active layer of the first transistor, the active layer of the second transistor, the active layer of the third transistor, and the first and second electrodes of the adjustable capacitor are all located between the first pixel electrode and the second pixel electrode.

[0007] For example, according to an embodiment of the present disclosure, the same gate line electrically connected to the control electrode of the first transistor and the control electrode of the second transistor is located between the first pixel electrode and the second pixel electrode.

[0008] For example, according to an embodiment of the present disclosure, the first control signal line is located between the first pixel electrode and the second pixel electrode.

[0009] For example, according to an embodiment of the present disclosure, the second control signal line is located between the same gate line and the first control signal line.

[0010] For example, according to an embodiment of the present disclosure, the multiple gate lines are located between the multiple data lines and the base substrate, the second electrode of the adjustable capacitor and the control electrode of each transistor are arranged on the same layer as the multiple gate lines, and the first electrode of the adjustable capacitor is arranged on the same layer as the multiple data lines.

[0011] For example, according to an embodiment of the present disclosure, a straight line extending along the second direction passes through the active layer of the second transistor and the semiconductor layer of the adjustable capacitor.

[0012] For example, according to an embodiment of the present disclosure, a straight line extending along the first direction passes through the control electrode of the third transistor and the second electrode of the adjustable capacitor.

[0013] For example, according to an embodiment of the present disclosure, the first electrode of the second transistor and the first electrode of the third transistor are integrated into one structure, and the first electrode of the third transistor is provided in the same layer as the plurality of data lines.

[0014] For example, according to an embodiment of the present disclosure, the second electrode of the third transistor and the first electrode of the adjustable capacitor are integrated into a structure, and the second electrode of the third transistor is located between at least part of the first electrode of the second transistor and the second pixel electrode.

[0015] For example, according to an embodiment of the present disclosure, the multiple sub-pixels are arranged into multiple rows and columns of sub-pixels, the multiple rows of sub-pixels are arranged along the second direction, the second pole of the adjustable capacitor in each row of sub-pixels is connected to the same second control signal line, and the multiple second control signal lines connected to the adjustable capacitors of the multiple rows of sub-pixels are arranged along the second direction.

[0016] For example, according to an embodiment of the present disclosure, the array substrate further includes: at least one third control signal line and at least one pin electrically connected to the at least one third control signal line. The at least one third control signal line extends in the same direction as the data line, and the plurality of second control signal lines are connected to the at least one third control signal line.

[0017] For example, according to an embodiment of the present disclosure, the array substrate further includes a plurality of pins, and each second control signal line is connected to one pin so that each second control signal line is configured to independently input a control signal.

[0018] The present disclosure provides an array substrate, comprising: a base substrate; a plurality of sub-pixels located on the base substrate, the plurality of sub-pixels being arranged in an array along a first direction and a second direction, the first direction intersecting the second direction; a plurality of data lines located on the base substrate and arranged along the first direction; and a plurality of gate lines located on the base substrate and arranged along the second direction. Each sub-pixel comprises a transistor and a stacked pixel electrode and a common electrode, the first electrode of the transistor being connected to the data line, the second electrode of the transistor being connected to the pixel electrode, and the control electrode of the transistor being connected to the gate line; the array substrate further comprises at least one control signal line, and at least some of the sub-pixels further comprise an adjustable capacitor, the adjustable capacitor comprising a first electrode, a semiconductor layer, and a second electrode stacked in sequence along a direction perpendicular to the base substrate, the semiconductor layer being in the same layer as the active layer of the transistor and spaced apart, the first electrode of the adjustable capacitor being connected to the pixel electrode, the control signal line being connected to the second electrode of the adjustable capacitor to apply a voltage to change the capacitance value of the adjustable capacitor, and a straight line extending along the first direction passing through the active layer and the semiconductor layer.

[0019] For example, according to an embodiment of the present disclosure, at least one gate line is multiplexed as the control signal line.

[0020] For example, according to an embodiment of the present disclosure, the gate line is spaced apart from the control signal line, and the second electrode of the adjustable capacitor is completely located between the control signal line and the pixel electrode connected to the first electrode of the adjustable capacitor.

[0021] For example, according to an embodiment of the present disclosure, the control electrode of the transistor is arranged in the same layer as the gate line, and the control electrode includes two parts located on both sides of the gate line. The size of the part of the two parts close to the adjustable capacitor in the second direction is a first size, and the size of the part of the two parts far from the adjustable capacitor in the second direction is a second size, and the first size is larger than the second size.

[0022] For example, according to an embodiment of the present disclosure, the second electrode of the transistor is spaced apart from the first electrode of the adjustable capacitor.

[0023] For example, according to an embodiment of the present disclosure, the control signal line is set in the same layer as the gate line; the multiple sub-pixels are arranged into multiple rows and columns of sub-pixels, and the multiple rows of sub-pixels are arranged along the second direction. The second pole of the adjustable capacitor in each row of sub-pixels is connected to the same control signal line, and the multiple control signal lines connected to the adjustable capacitors of the multiple rows of sub-pixels are arranged along the second direction.

[0024] For example, according to an embodiment of the present disclosure, the array substrate further includes: at least one control signal connection line and at least one pin electrically connected to the at least one control signal connection line. The at least one control signal connection line extends in the same direction as the data line, and the plurality of control signal lines are connected to the at least one control signal connection line.

[0025] For example, according to an embodiment of the present disclosure, the array substrate further includes a plurality of pins, wherein each control signal line is connected to one pin so that each control signal line is configured to input a control signal independently.

[0026] For example, according to an embodiment of the present disclosure, the array substrate further includes: multiple rows of shift register units located on the base substrate. The shift register units include an input circuit, an output circuit, and a node noise reduction circuit; the input circuit is connected to a first node and configured to provide an input signal to the first node; the node noise reduction circuit is connected to the first node and a second node and configured to perform noise reduction on the first node under the control of the voltage level of the second node; the output circuit is connected to the first node and an output terminal and configured to output an output signal at the output terminal under the control of the voltage level of the first node. Each control signal line is connected to the second node of the shift register unit located in the same row as it.

[0027] An embodiment of the present disclosure provides a shift register unit, comprising an input circuit, an output circuit, and a reset circuit. The input circuit is connected to a first node and configured to provide an input signal to the first node; the reset circuit is connected to the first node and a reset terminal and configured to reset the first node in response to a reset signal provided by the reset terminal; the output circuit is connected to the first node and an output terminal and configured to output an output signal at the output terminal under control of the voltage level of the first node. The output circuit comprises an adjustable capacitor, wherein a first electrode of the adjustable capacitor is connected to the output terminal, and the first node is connected to a second electrode of the adjustable capacitor to change the capacitance value of the adjustable capacitor when the voltage of the first node changes; the output circuit comprises a transistor electrically connected to the adjustable capacitor, wherein a control electrode of the transistor is connected to the first node, and one electrode of the transistor is connected to the second electrode of the adjustable capacitor. A semiconductor layer and an insulating layer are provided between the first electrode of the adjustable capacitor and the second electrode of the adjustable capacitor, and an active layer of the transistor is provided on the same layer as the semiconductor layer of the adjustable capacitor.

[0028] For example, according to an embodiment of the present disclosure, the input circuit includes a first transistor, a first electrode of the first transistor is connected to the first power supply terminal, a second electrode of the first transistor is connected to the first node, and a gate of the first transistor is connected to the first signal control terminal; the reset circuit includes a second transistor, a first electrode of the second transistor is connected to the first node, a second electrode of the second transistor is connected to the second power supply terminal, and a gate of the second transistor is connected to the second signal control terminal; the output circuit also includes a third transistor, a first electrode of the third transistor is connected to the clock signal terminal, a second electrode of the third transistor is connected to the first electrode of the adjustable capacitor, and a gate of the third transistor is connected to the first node; the shift register unit also includes a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor and an eleventh transistor, wherein the first electrode of the fourth transistor is connected to the first node, the second electrode of the fourth transistor is connected to the third voltage terminal, and the gate of the fourth transistor is connected to the frame reset signal terminal; the first electrode of the fifth transistor is connected to the fourth voltage terminal, the second electrode of the fifth transistor is connected to the second node; the first electrode of the sixth transistor is connected to the second node, and the second electrode of the sixth transistor is connected to the second node. The second electrode of the transistor is connected to the third voltage terminal, and the gate of the sixth transistor is connected to the first node; the first electrode of the seventh transistor is connected to the first node, the second electrode of the seventh transistor is connected to the third voltage terminal, and the gate of the seventh transistor is connected to the frame reset signal terminal; the first electrode of the eighth transistor is connected to the gate of the fifth transistor, the second electrode of the eighth transistor is connected to the third voltage terminal, and the gate of the eighth transistor is connected to the first node; the first electrode of the ninth transistor is connected to the fourth voltage terminal, the second electrode of the ninth transistor is connected to the first electrode of the eighth transistor, and the gate of the ninth transistor is connected to the fourth voltage terminal; the first electrode of the tenth transistor is connected to the first node, the second electrode of the tenth transistor is connected to the third signal terminal, and the gate of the tenth transistor is connected to the second node; the first electrode of the eleventh transistor is connected to the second electrode of the third transistor, the second electrode of the eleventh transistor is connected to the third voltage terminal, and the gate of the eleventh transistor is connected to the first node.

[0029] An embodiment of the present disclosure provides a display device, comprising any one of the above-mentioned array substrates or shift register units. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limiting the present disclosure.

[0031] FIG1 is a schematic diagram of a partial planar structure of an array substrate provided according to an embodiment of the present disclosure.

[0032] FIG. 2 is a schematic diagram showing a partial structure of a sub-pixel in the array substrate shown in FIG. 1 and a connection relationship between the sub-pixel and a signal line.

[0033] FIG3 is a schematic diagram of the circuit structure of the sub-pixel shown in FIG2 .

[0034] FIG. 4 is a schematic diagram of a cross-sectional structure of the adjustable capacitor taken along line AA′ shown in FIG. 2 .

[0035] 5 and 6 are schematic diagrams of partial planar structures of array substrates provided according to different examples of the embodiments of the present disclosure.

[0036] FIG7 is a schematic diagram of a partial planar structure of an array substrate provided according to another embodiment of the present disclosure.

[0037] FIG8 is a schematic diagram showing a partial structure of two adjacent sub-pixels in the array substrate shown in FIG7 and a connection relationship between the sub-pixels and signal lines.

[0038] FIG9 is a schematic diagram of the circuit structure of the sub-pixel shown in FIG8 .

[0039] FIG10 is a schematic diagram of the cross-sectional structure of the adjustable capacitor taken along line BB′ shown in FIG8 .

[0040] FIG11 is a schematic diagram of a partial planar structure of an array substrate provided according to another example of an embodiment of the present disclosure.

[0041] 12 to 14 are schematic diagrams of partial planar structures of array substrates provided according to different examples of the embodiments of the present disclosure.

[0042] FIG. 15 is a circuit diagram of a shift register unit in the array substrate shown in FIG. 14 .

[0043] FIG16 is a schematic diagram of a shift register unit according to another embodiment of the present disclosure.

[0044] FIG17 is a circuit diagram of a specific implementation example of the shift register unit shown in FIG16 .

[0045] FIG18 is a layout diagram of the circuit shown in FIG17 .

[0046] FIG19 is an operation timing diagram of the shift register unit shown in FIG17 . DETAILED DESCRIPTION

[0047] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0048] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the ordinary meaning understood by a person of ordinary skill in the art to which this disclosure belongs. The terms "first," "second," and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are simply used to distinguish different components. The terms "include" or "comprises" and similar terms mean that the element or object preceding the term includes the elements or objects listed after the term and their equivalents, without excluding other elements or objects. The characteristics of "parallel," "perpendicular," and "same" used in the embodiments of this disclosure include the characteristics of "parallel," "perpendicular," and "same" in the strict sense, as well as "approximately parallel," "approximately perpendicular," and "approximately the same" that include certain errors, taking into account the errors associated with the measurement of specific quantities (for example, the limitations of the measurement system), and represent the acceptable deviation range for a specific value determined by a person of ordinary skill in the art. For example, "approximately" can mean within one or more standard deviations, or within 10% or 5% of the stated value. When the number of a component is not specifically specified below in the embodiments of this disclosure, it means that the component can be one or more, or can be understood as at least one. "At least one" means one or more, and "a plurality" means at least two. As used herein, "same-layer arrangement" refers to a structure in which two (or more) structures are formed through the same deposition process and patterned through the same patterning process, and the materials used for the structures may be the same or different. As used herein, "integrated arrangement" refers to a structure in which two (or more) structures are formed through the same deposition process and patterned through the same patterning process, and the materials used for the structures may be the same or different.

[0049] During the research, the inventors of this application found that the display effect of the display device will be limited by the capacitance in the panel. For example, the fixed pixel storage capacitance makes it difficult for the display panel to be compatible with high-low refresh rates, or the capacitance in the shift register unit in the display device is too small, which will cause the pull-up node, such as the PU point voltage, to be unable to be maintained and poor display will occur. The capacitance in the shift register unit is too large, which will cause difficulty in charging and discharging the pull-up node and poor low-temperature startup capability.

[0050] The disclosed embodiment provides an array substrate, comprising a base substrate, and a plurality of data lines, a plurality of gate lines, and a plurality of first control signal lines located on the base substrate. A plurality of sub-pixels are arranged in an array along a first direction and a second direction, the first direction intersecting the second direction; a plurality of data lines are arranged along the first direction; a plurality of gate lines are arranged along the second direction; a plurality of first control signal lines are arranged along the second direction. Each sub-pixel in at least some of the sub-pixels comprises a first sub-pixel portion and a second sub-pixel portion arranged along the second direction, the first sub-pixel portion comprises a first pixel electrode, the second sub-pixel portion comprises a second pixel electrode, the first pixel electrode and the second pixel electrode are spaced apart, and the first sub-pixel portion and the second sub-pixel portion share a common electrode; the first sub-pixel portion comprises a first transistor, the first electrode of the first transistor is connected to the first pixel electrode, the second sub-pixel portion comprises a second transistor and a third transistor, the first electrode of the second transistor and the first electrode of the third transistor are both connected to the second pixel electrode, the control electrode of the first transistor and the control electrode of the second transistor are both connected to the same gate line, the second electrode of the first transistor and the second electrode of the second transistor are both connected to the same data line, and the control electrode of the third transistor is connected to the first control signal line; The array substrate further includes a second control signal line, and the second sub-pixel portion further includes an adjustable capacitor, wherein a first electrode of the adjustable capacitor is connected to the second electrode of the third transistor, and the second control signal line is connected to the second electrode of the adjustable capacitor to apply a voltage to change the capacitance value of the adjustable capacitor; a semiconductor layer and an insulating layer are provided between the first electrode of the adjustable capacitor and the second electrode of the adjustable capacitor, and the semiconductor layer, the active layer of the first transistor, the active layer of the second transistor, and the active layer of the third transistor are all provided in the same layer; a first protrusion is provided on a side of the second pixel electrode close to the first pixel electrode, and a second protrusion is provided on a side of the second electrode of the adjustable capacitor close to the second pixel electrode, and the first control signal line includes a bent portion located between the first protrusion and the second protrusion. The array substrate provided by the present disclosure, by providing an adjustable capacitor in the second sub-pixel portion, and providing protrusions in both the adjustable capacitor and the second pixel electrode, and the first control signal line including a bent portion located between the two protrusions, is conducive to alleviating color shift under a wide viewing angle while maximizing the adjustable capacitance value range of the storage capacitor and the adjustable capacitor of the first sub-pixel portion, and avoiding interference of the first control signal line on the storage capacitor and the adjustable capacitor.

[0051] The present disclosure also provides an array substrate, comprising a base substrate and a plurality of gate lines and a plurality of data lines located on the base substrate. A plurality of sub-pixels are arranged in an array along a first direction and a second direction, the first direction intersecting the second direction; a plurality of data lines are arranged along the first direction; and a plurality of gate lines are arranged along the second direction. Each sub-pixel includes a transistor and a stacked pixel electrode and a common electrode, wherein the first electrode of the transistor is connected to the data line, the second electrode of the transistor is connected to the pixel electrode, and the control electrode of the transistor is connected to the gate line. The array substrate further includes at least one control signal line, and at least some of the sub-pixels further include an adjustable capacitor, wherein the adjustable capacitor includes a first electrode, a semiconductor layer, and a second electrode stacked in sequence along a direction perpendicular to the base substrate, the semiconductor layer being in the same layer as the active layer of the transistor and spaced apart from each other, the first electrode of the adjustable capacitor being connected to the pixel electrode, the control signal line being connected to the second electrode of the adjustable capacitor to apply a voltage to change the capacitance value of the adjustable capacitor, and a straight line extending along the first direction passes through the active layer and the semiconductor layer. The array substrate provided by the present disclosure sets an adjustable capacitor in the sub-pixel and sets the positional relationship between the active layer of the transistor and the semiconductor layer of the adjustable capacitor. While achieving compatibility with high and low refresh rates, the position of the adjustable capacitor is set to maximize the aperture ratio of the sub-pixel.

[0052] The embodiment of the present disclosure also provides a shift register unit, including an input circuit, an output circuit and a reset circuit. The input circuit is connected to the first node and is configured to provide an input signal to the first node; the reset circuit is connected to the first node and the reset terminal and is configured to reset the first node in response to the reset signal provided by the reset terminal; the output circuit is connected to the first node and the output terminal and is configured to output the output signal at the output terminal under the control of the voltage level of the first node. The output circuit includes an adjustable capacitor, the first node is connected to the second electrode of the adjustable capacitor to change the capacitance value of the adjustable capacitor when the voltage of the first node changes; the output circuit includes a transistor electrically connected to the adjustable capacitor, the control electrode of the transistor is connected to the first node, one electrode of the transistor is connected to the second electrode of the adjustable capacitor, a semiconductor layer and an insulating layer are provided between the first electrode of the adjustable capacitor and the second electrode of the adjustable capacitor, and the active layer of the transistor is provided on the same layer as the semiconductor layer of the adjustable capacitor. The shift register unit provided in the present disclosure sets an adjustable capacitor so that the capacitance value of the adjustable capacitor increases as the voltage of the first node increases. For example, the first node is quickly increased to improve the low-temperature startup capability. After the voltage of the first node is increased, the capacitance value of the adjustable capacitor increases. When the shift register unit is applied to a touch display device, the voltage at the first node can be better maintained during the touch stage. When the first node discharges, the capacitance value of the adjustable capacitor decreases accordingly, so that the first node can be discharged quickly.

[0053] The array substrate, the shift register unit, and the display device provided by the present disclosure are described below with reference to the accompanying drawings.

[0054] Figure 1 is a schematic diagram of a partial planar structure of an array substrate provided according to an embodiment of the present disclosure. Figure 2 is a schematic diagram of the partial structure of a subpixel in the array substrate shown in Figure 1 and the connection relationship between the subpixel and the signal line. Figure 3 is a schematic diagram of the circuit structure of the subpixel shown in Figure 2. Figure 4 is a schematic diagram of the cross-sectional structure of the adjustable capacitor taken along line AA' in Figure 2.

[0055] As shown in Figures 1 to 3, the array substrate includes a base substrate 10 and a plurality of sub-pixels 100, a plurality of data lines 210, a plurality of gate lines 220, and a plurality of first control signal lines 310 located on the base substrate 10. The plurality of sub-pixels 100 are arranged in an array along a first direction and a second direction, and the first direction intersects the second direction. For example, Figure 1 schematically shows that the first direction is the X direction and the second direction is the Y direction, but it is not limited to this, and the first direction and the second direction can be interchangeable. For example, the first direction is perpendicular to the second direction. However, it is not limited to this, and the angle between the first direction and the second direction can be 80 to 100 degrees, such as 85 to 95 degrees. For example, the area where the plurality of sub-pixels 100 are located is a display area for displaying images, and the array substrate also includes a peripheral area surrounding the display area.

[0056] As shown in Figures 1 to 3, a plurality of data lines 210 are arranged along a first direction, a plurality of gate lines 220 are arranged along a second direction, and a plurality of first control signal lines 310 are arranged along the second direction. For example, the plurality of data lines 210 and the plurality of gate lines 220 are arranged to intersect. For example, the gate lines 220 are located between the data lines 210 and the base substrate 10.

[0057] As shown in Figures 1 to 3, each of at least some of the sub-pixels 100 includes a first sub-pixel portion 110 and a second sub-pixel portion 120 arranged along a second direction. The first sub-pixel portion 110 includes a first pixel electrode 111, and the second sub-pixel portion 120 includes a second pixel electrode 121. The first pixel electrode 111 and the second pixel electrode 121 are spaced apart, and the first sub-pixel portion 110 and the second sub-pixel portion 120 share a common electrode 113. For example, each sub-pixel 100 constitutes a display unit, and the first sub-pixel portion 110 and the second sub-pixel portion 120 constitute two parts of the display unit, which are adjacent to each other and are used to display sub-pixels 100 of the same color.

[0058] As shown in Figures 2 to 3, the first sub-pixel portion 110 includes a first transistor 114, the first electrode 1141 of the first transistor 114 is connected to the first pixel electrode 111, the second sub-pixel portion 120 includes a second transistor 123 and a third transistor 124, the first electrode 1231 of the second transistor 123 and the first electrode 1241 of the third transistor 124 are both connected to the second pixel electrode 121, the control electrode 1143 of the first transistor 114 and the control electrode 1233 of the second transistor 123 are both connected to the same gate line 220, the second electrode 1142 of the first transistor 114 and the second electrode 1232 of the second transistor 123 are both connected to the same data line 210, and the control electrode 1243 of the third transistor 124 is connected to the first control signal line 310.

[0059] It should be noted that the transistors used in the embodiments of the present disclosure may be thin film transistors, field effect transistors, or other switching devices with the same characteristics. The embodiments of the present disclosure are described using thin film transistors as examples. The source and drain of the transistors used here may be symmetrical in structure, so the source and drain may be structurally indistinguishable. In the embodiments of the present disclosure, in order to distinguish the two poles of the transistor other than the gate, one pole is directly described as the first pole and the other pole is directly described as the second pole.

[0060] As shown in Figures 2 to 3, the array substrate also includes a second control signal line 320, and the second sub-pixel portion 120 also includes an adjustable capacitor 125. The first electrode 1251 of the adjustable capacitor is connected to the second electrode 1242 of the third transistor 124, and the second control signal line 320 is connected to the second electrode 1252 of the adjustable capacitor 125 to apply a voltage to change the capacitance value of the adjustable capacitor 125.

[0061] The array substrate provided by the present disclosure is advantageous in alleviating large viewing angle color deviation that occurs when the array substrate is used for display by disposing an adjustable capacitor in the second sub-pixel portion.

[0062] For example, the array substrate shown in Figures 1 to 3 can be applied to a liquid crystal display device using a multi-domain vertical alignment (VA) mode. For example, the multi-domain mode can be an 8-domain mode.

[0063] For example, as shown in Figures 2 and 3, the first sub-pixel portion 110 can be a bright sub-pixel portion, and the second sub-pixel portion 120 can be a dark sub-pixel portion. By adjusting the voltages on the pixel electrodes of the two pixel portions of the same sub-pixel, the deflection angle of the liquid crystal can be adjusted to achieve brightness adjustment, thereby correcting the color skew at large viewing angles. For example, the first pixel electrode 111 and the second pixel electrode 121 are both plate-shaped structures, and the common electrode 113 can include a strip-shaped structure. For example, a column of sub-pixels 100 is provided between two adjacent data lines 210.

[0064] In some examples, as shown in Figures 1 to 3, the same gate line 220 electrically connected to the control electrode of the first transistor 114 and the control electrode of the second transistor 123 is located between the first pixel electrode 111 and the second pixel electrode 121. By arranging the gate line between the first pixel electrode and the second pixel electrode, the electrical connection between the control electrode of the first transistor and the control electrode of the second transistor and the gate line is facilitated, and space is saved to increase the aperture ratio of the sub-pixel.

[0065] For example, as shown in FIG. 2 and FIG. 3 , the first pixel electrode 111 and the common electrode 113 form a storage capacitor 115 of the first sub-pixel portion 110 , and the second pixel electrode 121 and the common electrode 113 form a storage capacitor 126 of the second sub-pixel portion 210 .

[0066] For example, as shown in Figures 2 and 3, the voltage of the gate line 220 is set high, the first transistor 114 and the second transistor 123 are turned on, and the data line 210 charges the storage capacitor 115 of the first sub-pixel portion 110 and the storage capacitor 126 of the second sub-pixel portion 210 at the same time. At this time, the voltages of the storage capacitors of the first sub-pixel portion 110 and the second sub-pixel portion 120 are consistent, and the brightness of the first sub-pixel portion 110 and the second sub-pixel portion 120 are the same. After the storage capacitors of the first sub-pixel portion 110 and the second sub-pixel portion 120 are charged, the voltage of the gate line 220 is set low, and the first transistor 114 and the second transistor 123 are turned off. Then, the voltage of the first control signal line 310 is set high, the third transistor 124 is turned on, and the charge in the storage capacitor 126 of the second sub-pixel portion 120 is charged to the adjustable capacitor 125 through the third transistor 124. The voltage at the second electrode (i.e., the control electrode) of the adjustable capacitor 125 is adjusted via the second control signal line 320. This adjusts the capacitance of the adjustable capacitor 125, thereby changing the voltage at the second pixel electrode 121 in the second sub-pixel 120. This adjusts the deflection angle of the liquid crystal until the color deflection problem at large viewing angles is resolved. Finally, the voltage of the second control signal line is set low, turning off the third transistor 124, completing the adjustment.

[0067] For example, as shown in FIG4 , the adjustable capacitor 125 includes a first metal layer 01, an insulating layer 02, a semiconductor layer 03, and a second metal layer 04, wherein the first metal layer 01 is located between the second metal layer 02 and the substrate. When the first metal layer 01 and the second metal layer 04 are electrically connected, the actual capacitance value of the adjustable capacitor 125 changes with the voltage of the first metal layer 01. For example, when the adjustable capacitor 125 is an N-type capacitor, the capacitance value of the adjustable capacitor 125 increases as the voltage input to the first metal layer 01 increases; when the adjustable capacitor 125 is a P-type capacitor, the capacitance value of the adjustable capacitor 125 decreases as the voltage of the first metal layer 01 increases.

[0068] In some examples, as shown in Figures 2 and 3, the active layer 1140 of the first transistor 114, the active layer 1230 of the second transistor 123, the active layer 1240 of the third transistor 124, and the first electrode 1251 and the second electrode 1252 of the adjustable capacitor 125 are all located between the first pixel electrode 111 and the second pixel electrode 121. By disposing the active layer of each transistor and the adjustable capacitor between the first pixel electrode and the second pixel electrode, space can be saved and the aperture ratio of the sub-pixel can be improved.

[0069] 2 , the active layer 1140 of the first transistor 114 and the active layer 1230 of the second transistor 123 are arranged along a first direction. For example, the active layer 1140 of the first transistor 114 and the active layer 1230 of the second transistor 123 may be integrated to further save space between the two sub-pixels.

[0070] As shown in Figures 2 and 3, a first protrusion 121-1 is provided on the side of the second pixel electrode 121 near the first pixel electrode 111. A second protrusion 125-1 is provided on the side of the second electrode 1252 of the adjustable capacitor 125 near the second pixel electrode 121. The first control signal line 310 includes a bent portion 311 located between the first protrusion 121-1 and the second protrusion 125-1. Thus, in this display substrate, while maximizing the storage capacitance of the first sub-pixel and the adjustable capacitance range of the adjustable capacitor, interference with the storage capacitance and the adjustable capacitor by the first control signal line is avoided.

[0071] For example, as shown in FIG2 , the second protrusion 125-1 includes a second inclined side, and the first protrusion 121-1 includes a first inclined side. The first inclined side is substantially parallel to the second inclined side, and the two side edges of the bent portion 311 of the first control signal line 310 located between the two protrusions are substantially parallel to the first inclined side and the second inclined side, respectively. For example, the extension directions of the first inclined side and the second inclined side both intersect with the first direction and intersect with the second direction.

[0072] For example, as shown in FIG. 2 , a straight line extending along the X direction passes through the second protrusion 125 - 1 and the gate of the third transistor.

[0073] As shown in FIG. 2 , the second protrusion 125 - 1 of the second electrode 1252 of the adjustable capacitor 125 refers to a portion thereof protruding toward the second pixel electrode 121 relative to the second control signal line 320 .

[0074] For example, as shown in FIG2 , a distance D1 between the active layers (e.g., active layer 1140 and active layer 1230) of the first transistor 114 and the second transistor 123 and the first pixel electrode 111 is less than a distance D2 between the active layers and the second pixel electrode 121, and an edge of the first pixel electrode 111 near the active layer includes a protrusion 111-1, and the protrusion 111-1 does not overlap with an orthographic projection of the active layer on a plane extending along the first direction and perpendicular to the XY plane. Providing a protrusion in the first pixel electrode that protrudes toward a side closer to the second pixel electrode, and the protrusion does not overlap with an orthographic projection of the active layer on a plane extending in the first direction and perpendicular to the XY plane, helps to prevent interference between the first pixel electrode and the active layers of the first and second transistors while maximizing the storage capacitance of the first sub-pixel.

[0075] For example, the ratio of the distance D1 to the distance D2 may be 0.5 to 5. For example, the ratio of the distance D1 to the distance D2 may be 1 to 4. For example, the ratio of the distance D1 to the distance D2 may be 2 to 3.5. For example, the ratio of the distance D1 to the distance D2 may be 2 to 3.

[0076] 2 , the control electrode of the first transistor 114 and the control electrode of the second transistor are integrated to save space. For example, the second electrode of the first transistor 114 and the second electrode of the second transistor 123 are integrated to save space.

[0077] In some examples, as shown in Figures 1 to 4, multiple gate lines 220 are located between multiple data lines 210 and the base substrate 10, the second electrode 1252 of the adjustable capacitor 125 (the first metal layer 01 as shown in Figure 4) and the control electrode of each transistor are arranged in the same layer as the multiple gate lines 220, the first electrode 1251 of the adjustable capacitor 125 (the second metal layer 04 as shown in Figure 4) is arranged in the same layer as the multiple data lines 210, and a semiconductor layer 03 and an insulating layer 02 are arranged between the first electrode 1251 of the adjustable capacitor 125 and the second electrode 1252 of the adjustable capacitor 125, and the semiconductor layer 03 and the active layer of each transistor (such as the active layer 1140 and the active layer 1230) are in the same layer and are spaced apart.

[0078] For example, as shown in FIG. 2 , the control electrode of the first transistor 114 , the control electrode of the second transistor 123 , and the gate line 220 may be integrated into one structure.

[0079] In some examples, as shown in FIG2 , the first control signal line 310 is located between the first pixel electrode 111 and the second pixel electrode 121. In some examples, as shown in FIG2 , the second control signal line 320 is located between the same gate line 220 and the first control signal line 310. Arranging the positions of the gate line, the first control signal line, and the second control signal line helps save layout space and improve layout utilization.

[0080] For example, as shown in Figure 2, among the gate line 220, the first control signal line 310 and the second control signal line 320 located between the first pixel electrode 111 and the second pixel electrode 121, the distance between the gate line 220 (such as the position other than the control electrode of the first transistor 114 and the second transistor 123) and the second control signal line 320 (such as the position other than the second electrode 1252 of the adjustable capacitor) is greater than the distance between the second control signal line 320 and the first control signal line 310 (such as the position other than the control electrode of the third transistor 124).

[0081] 2 , the gate line 220 , the first control signal line 310 , and the second control signal line 320 extend along the first direction. For example, the edge of the second control signal line 320 facing the gate line 220 may be a straight edge extending along the first direction.

[0082] In some examples, as shown in Figures 2 and 4 , a straight line extending along the second direction passes through the active layer 1230 of the second transistor 123 and the semiconductor layer 03 of the adjustable capacitor 125. For example, the orthographic projections of the active layer 1230 of the second transistor 123 and the semiconductor layer 03 of the adjustable capacitor 125 on a plane extending along the first direction and perpendicular to the XY plane overlap.

[0083] In some examples, as shown in FIG2 , a straight line extending along the first direction passes through the control electrode of the third transistor 124 and the second electrode of the adjustable capacitor 125. For example, the control electrode of the third transistor 124 and the second electrode of the adjustable capacitor 125 may overlap in their orthographic projections on a plane extending along the second direction and perpendicular to the XY plane.

[0084] The array substrate provided by the present disclosure, by arranging the positional relationship of the second transistor, the adjustable capacitor and the third transistor in the first direction and the second direction, is advantageous in preventing interference between the active layer of each transistor and the semiconductor layer of the adjustable capacitor, while maximizing the area of ​​the active layer of each transistor and the semiconductor layer of the adjustable capacitor, preventing the film layer from overlapping with the common electrode, and reducing interference between the film layers, while improving the layout utilization and maximizing the aperture ratio of the sub-pixel.

[0085] For example, as shown in FIG. 2 , the second electrode of the adjustable capacitor 125 includes a protrusion protruding toward the first control signal line 310 , and the first control signal line 310 is bent at a position corresponding to the protrusion.

[0086] In some examples, as shown in FIG. 2 , the first electrode of the second transistor 123 and the first electrode of the third transistor 124 are integrated into one structure, and the first electrode of the third transistor 124 is provided in the same layer as the plurality of data lines 210 .

[0087] In some examples, as shown in FIG. 2 , the second electrode of the third transistor 124 and the first electrode of the adjustable capacitor 125 are integrated into a structure, and the second electrode of the third transistor 124 is located between at least a portion of the first electrode of the second transistor 123 and the second pixel electrode 121 .

[0088] When the second transistor, the third transistor and the adjustable capacitor are all located between the first pixel electrode and the second pixel electrode and are arranged at a close distance, by setting the first electrode of the second transistor and the first electrode of the third transistor to an integrated structure, and setting the second electrode of the third transistor and the first electrode of the adjustable capacitor to an integrated structure, it is beneficial to save layout space and improve the aperture ratio of the sub-pixel.

[0089] In some examples, as shown in Figures 1 and 2, multiple sub-pixels 100 are arranged into multiple rows and columns of sub-pixels, and the multiple rows of sub-pixels 100 are arranged along the second direction. For example, the first direction can be the row direction, and the second direction can be the column direction. The second electrodes of the adjustable capacitors 125 in each row of sub-pixels 100 are connected to the same second control signal line 320, and the multiple second control signal lines 320 connected to the adjustable capacitors 125 of the multiple rows of sub-pixels 100 are arranged along the second direction.

[0090] 5 and 6 are schematic diagrams of partial planar structures of array substrates provided according to different examples of the embodiments of the present disclosure.

[0091] For example, as shown in FIG6 , the array substrate further includes at least one third control signal line 330 and at least one pin 331 electrically connected to the at least one third control signal line 330 . The at least one third control signal line 330 extends in the same direction as the data line 210 , and a plurality of second control signal lines 320 are connected to the at least one third control signal line 330 . FIG6 schematically illustrates one third control signal line 330 , and all second control signal lines 320 are electrically connected to this third control signal line 330 to transmit control signals. Of course, the number of third control signal lines is not limited to one. For example, the number of third control signal lines can be two, three, or more, so as to divide multiple rows of sub-pixels into multiple groups, and different third control signal lines are configured to transmit control signals to the adjustable capacitors of different groups.

[0092] 5 , the third control signal line 330 and the data line 210 may be provided in the same layer. Of course, the present disclosure is not limited thereto. For example, the third control signal line may be located on a side of the data line away from the substrate.

[0093] For example, as shown in FIG5 , a plurality of data lines 210 are electrically connected to a circuit board via a plurality of pins 211. For example, the circuit board includes a chip-on-film (COF), and the COF includes a source IC. For example, the third control signal line 330 can be electrically connected to the source IC via a pin 331. For example, when the third control signal line is not provided in the array substrate, the pin 331 can be a dummy pin, i.e., a pin to which no electrical signal is input. After the third control signal line is provided, the pin is electrically connected to the third control signal line and receives the corresponding control signal.

[0094] In some examples, as shown in FIG6 , the array substrate further includes a plurality of pins 321, and each second control signal line 320 is connected to one of the pins 321 so that each second control signal line 320 is configured to independently input a control signal. For example, the second control signal line 320 is electrically connected to a gate circuit control chip (Gate IC) via the pins 321, and the gate line 220 is electrically connected to the Gate IC via the pins 321. The Gate IC is configured to transmit signals to the gate line and the second control signal line 320.

[0095] For example, as shown in FIG6 , the first control signal line 310 is connected to the pin 321 to be electrically connected to the Gate IC.

[0096] Figure 7 is a schematic diagram of a partial planar structure of an array substrate provided according to another embodiment of the present disclosure. Figure 8 is a schematic diagram of the partial structure of two adjacent sub-pixels in the array substrate shown in Figure 7 and the connection relationship between the sub-pixels and signal lines. Figure 9 is a schematic diagram of the circuit structure of the sub-pixel shown in Figure 8. Figure 10 is a schematic diagram of the cross-sectional structure of the adjustable capacitor taken along line BB' shown in Figure 8.

[0097] As shown in FIG7 , the array substrate includes a base substrate 10 and a plurality of sub-pixels 100, a plurality of data lines 210, and a plurality of gate lines 220 located on the base substrate 10. The plurality of sub-pixels 100 are arranged in an array along a first direction and a second direction, and the first direction intersects the second direction. For example, FIG7 schematically shows that the first direction is the X direction and the second direction is the Y direction, but is not limited to this, and the first direction and the second direction can be interchangeable. For example, the first direction is perpendicular to the second direction. However, not limited to this, the angle between the first direction and the second direction can be 80 to 100 degrees, such as 85 to 95 degrees. For example, the area where the plurality of sub-pixels 100 are located is a display area for displaying images, and the array substrate also includes a peripheral area surrounding the display area.

[0098] As shown in FIG7 , a plurality of data lines 210 are arranged along a first direction, and a plurality of gate lines 220 are arranged along a second direction. For example, the plurality of data lines 210 and the plurality of gate lines 220 are arranged to intersect to define the areas where the sub-pixels 100 are located. For example, the gate lines 220 are located between the data lines 210 and the base substrate 10.

[0099] As shown in Figures 8 and 9, each sub-pixel 100 includes a transistor 101 and a stacked pixel electrode 102 and a common electrode 103. A first electrode 1011 of the transistor 101 is connected to the data line 210, a second electrode 1012 of the transistor 101 is connected to the pixel electrode 102, and a control electrode 1013 of the transistor 101 is connected to the gate line 220. For example, the pixel electrode 102 may have a plate-like structure, and the common electrode 103 may have a strip-like structure.

[0100] It should be noted that the transistors used in the embodiments of the present disclosure may be thin film transistors, field effect transistors, or other switching devices with the same characteristics. The embodiments of the present disclosure are described using thin film transistors as examples. The source and drain of the transistors used here may be symmetrical in structure, so the source and drain may be structurally indistinguishable. In the embodiments of the present disclosure, in order to distinguish the two poles of the transistor other than the gate, one pole is directly described as the first pole and the other pole is directly described as the second pole.

[0101] As shown in Figures 7 to 10, the array substrate further includes at least one control signal line 410, and at least some sub-pixels 100 further include an adjustable capacitor 104. The adjustable capacitor 104 includes a first electrode 1041, a semiconductor layer 03, and a second electrode 1042, which are sequentially stacked in a direction perpendicular to the base substrate 10. The semiconductor layer 03 and the active layer 1010 of the transistor 101 are co-layered and spaced apart. The first electrode 1041 of the adjustable capacitor 104 is connected to the pixel electrode 102, and the control signal line 410 is connected to the second electrode 1042 of the adjustable capacitor 104 to apply a voltage to change the capacitance of the adjustable capacitor 104. A straight line extending in the first direction passes through the active layer 1010 and the semiconductor layer 03. For example, the capacitor 105 formed between the pixel electrode 102 and the common electrode 103, together with the adjustable capacitor 104, forms the storage capacitor of the sub-pixel 100.

[0102] The array substrate provided by the present disclosure can achieve a small storage capacitance of the sub-pixel at a high refresh rate to achieve fast charging by setting an adjustable capacitor in the sub-pixel; at a low refresh rate, the storage capacitance of the sub-pixel is large, and the pixel voltage can be better maintained to achieve high-low refresh rate compatibility; at the same time, by setting the positional relationship between the transistor and the adjustable capacitor, the layout can be made compact, which is conducive to improving the aperture ratio of the sub-pixel.

[0103] For example, as shown in Figures 8 and 9, when a display device including this array substrate uses a high refresh rate, a smaller storage capacitor is required for better charging. In this case, the voltage input to the adjustable capacitor is adjusted by the control signal line to minimize the capacitance of the adjustable capacitor. The sub-pixel has a small storage capacitance, which facilitates charging and enables a high refresh rate. When a display device including this array substrate uses a low refresh rate, the charging time is longer, and the sub-pixel needs to better maintain the voltage. In this case, a larger storage capacitor is required. Therefore, the control signal line adjusts the voltage input to the adjustable capacitor to maximize the capacitance of the adjustable capacitor. In this case, the sub-pixel has a large storage capacitance, enabling a low refresh rate.

[0104] In some examples, as shown in FIG7 and FIG8 , the gate line 220 is spaced apart from the control signal line 410 , and the second electrode 1042 of the adjustable capacitor 104 is completely located between the control signal line 410 and the pixel electrode 102 connected to the first electrode 1041 of the adjustable capacitor 104 .

[0105] In some examples, as shown in Figures 7 and 8, the control electrode 1013 of the transistor 101 is provided in the same layer as the gate line 220. For example, the control electrode 1013 of the transistor 101 and the gate line 220 can be an integrated structure, such as a portion of the gate line 220 can be used as a portion of the control electrode 1013. The control electrode 1013 includes two parts located on both sides of the gate line 220. The portion of the two parts close to the adjustable capacitor 104 has a first size S1 in the second direction, and the portion of the two parts away from the adjustable capacitor 104 has a second size in the second direction. The first size S1 is greater than the second size S2.

[0106] For example, as shown in FIG8 , the ratio of the first size S1 to the second size S2 can be 1.5 to 10. For example, the ratio of the first size S1 to the second size S2 can be 2 to 3. For example, the ratio of the first size S1 to the second size S2 can be 2.5 to 8. While ensuring the gate area of ​​the transistor, setting the ratio of the first size to the second size as large as possible is beneficial for maximizing the overlap area between the semiconductor layer and the second electrode in the adjustable capacitor.

[0107] For example, as shown in Figure 8, the orthographic projections of the second electrode 1042 of the adjustable capacitor 104 and the control electrode 1013 of the transistor 101 on a plane extending along the Y direction and perpendicular to the XY plane overlap. For example, the second electrode 1042 of the adjustable capacitor 104 and the control electrode 1013 of the transistor 101 are arranged in the same layer.

[0108] By setting most of the control electrode of the transistor between the gate line and the control signal line, and setting the second electrode of the adjustable capacitor between the gate line and the control signal line, while realizing that the transistor has a larger channel area and the first electrode and the second electrode of the adjustable capacitor have a larger overlapping area, it is beneficial to save space in the second direction of the layout, thereby improving the aperture ratio of the sub-pixel.

[0109] For example, as shown in FIG8 , the first electrode 1011 and the second electrode 1012 of the transistor 101 , the first electrode 1041 of the adjustable capacitor 104 , and the data line 210 are arranged in the same layer.

[0110] In some examples, as shown in FIG8 , the second electrode 1012 of the transistor 101 is spaced apart from the first electrode 1041 of the adjustable capacitor 104 , which helps save layout space in the second direction while preventing interference between the first electrode of the adjustable capacitor and the second electrode of the transistor.

[0111] For example, as shown in FIG8 , the distance between the second electrode 1012 of the transistor 101 and the first electrode 1041 of the adjustable capacitor 104 is greater than the size of the first electrode 1041 of the adjustable capacitor 104 in the first direction.

[0112] In some examples, as shown in Figures 7 and 8, the control signal line 410 is provided in the same layer as the gate line 220; the plurality of sub-pixels 100 are arranged into multiple rows and columns of sub-pixels 100, the multiple rows of sub-pixels 100 are arranged along the second direction, the second electrodes of the adjustable capacitors 104 in each row of sub-pixels 100 are connected to the same control signal line 410, and the multiple control signal lines 410 connected to the adjustable capacitors 104 of the multiple rows of sub-pixels 100 are arranged along the second direction. For example, the first direction may be a row direction, and the second direction may be a column direction.

[0113] For example, as shown in FIG. 7 , a plurality of control signal lines 410 and a plurality of gate lines 220 are alternately arranged along the second direction.

[0114] FIG11 is a schematic diagram of a partial planar structure of an array substrate provided according to another example of an embodiment of the present disclosure. The array substrate shown in FIG11 differs from the array substrate shown in FIG7 in that at least one gate line 220 is multiplexed as a control signal line 410. For example, each gate line 220 is multiplexed as a control signal line 410. For example, the gate signal transmitted by the gate line 220 can be multiplexed as a control signal transmitted by the control signal line 410.

[0115] The array substrate provided in this example helps save layout space by reusing gate lines as control signal lines connected to adjustable capacitors.

[0116] 12 to 14 are schematic diagrams of partial planar structures of array substrates provided according to different examples of the embodiments of the present disclosure.

[0117] For example, as shown in FIG12 , the array substrate further includes at least one control signal connection line 420 and at least one pin 411 electrically connected to the at least one control signal connection line 420. The at least one control signal connection line 420 extends in the same direction as the data line 210, and multiple control signal lines 410 are connected to the at least one control signal connection line 420. FIG12 schematically illustrates one control signal connection line 420, and all control signal lines 410 are electrically connected to this control signal connection line 420 to transmit control signals. Of course, the number of control signal connection lines is not limited to one. For example, the number of control signal connection lines can be two, three, or more, so as to divide multiple rows of sub-pixels into multiple groups, and different control signal connection lines are configured to transmit control signals to adjustable capacitors in different groups.

[0118] For example, as shown in Figure 12, the control signal connection line 420 and the data line 210 may be provided in the same layer. Of course, the embodiments of the present disclosure are not limited thereto. For example, the control signal connection line may be located on a side of the data line away from the substrate.

[0119] For example, as shown in FIG12 , a plurality of data lines 210 are electrically connected to a circuit board via a plurality of pins 211. For example, the circuit board includes a chip-on-film (COF), and the COF includes a source IC. For example, a control signal connection line 420 can be electrically connected to the source IC via a pin 411. For example, when a control signal connection line is not provided in the array substrate, the pin 411 can be a dummy pin, i.e., no electrical signal is input. After a control signal connection line is provided, the pin is electrically connected to the control signal connection line and receives a corresponding control signal.

[0120] In some examples, as shown in FIG13 , the array substrate further includes a plurality of pins 321 , and each control signal line 410 is connected to one of the pins 321 so that each control signal line 410 is configured to independently input a control signal. For example, the control signal line 410 is electrically connected to a gate circuit control chip (Gate IC) via the pins 321 , and the gate line 220 is electrically connected to the Gate IC via the pins 321 . The Gate IC is configured to transmit signals to the gate line and the control signal line 410 .

[0121] FIG. 15 is a circuit diagram of a shift register unit in the array substrate shown in FIG. 14 .

[0122] In some examples, as shown in Figures 14 and 15, the array substrate further includes multiple rows of shift register units 510 located on the base substrate 10. The shift register units 510 include input circuits 511, output circuits 512, and node noise reduction circuits 513. The input circuit 511 is connected to the first node N1 and configured to provide an input signal to the first node N1. The node noise reduction circuit 513 is connected to the first node N1 and the second node N2 and configured to reduce noise on the first node N1 under the control of the voltage level of the second node N2. The output circuit 512 is connected to the first node N1 and the output terminal OUT and configured to output an output signal at the output terminal OUT under the control of the voltage level of the first node N1. Each control signal line 410 is connected to the second node N2 of the shift register unit 510 located in the same row as it.

[0123] For example, the control signal line 410 may be connected to the position of the second node N2 through a film layer provided at the same layer as the pixel electrode.

[0124] 14 and 15 , the output terminal OUT of the shift register unit 510 is connected to the gate line 220 to transmit a gate signal to the gate line 220. For example, the output circuit 512 is connected to the clock signal terminal CLK.

[0125] For example, as shown in FIG15 , the node noise reduction circuit 513 may include a transistor, the gate of which is connected to the second node N2, the first electrode of which is connected to the N1 node, and the second electrode of which is connected to the voltage terminal VGL. The transistor pulls down the first node N1 under the control of the second node N2 to achieve noise reduction. For example, the shift register unit 510 further includes a pull-down circuit 514, which is connected to the second node N2 and the voltage terminal VGL and is configured to output the low-level voltage of the voltage terminal VGL to the output terminal OUT under the control of the second node N2.

[0126] The shift register unit shown in FIG15 can be implemented using the specific circuit diagram shown in FIG17, such as an 11T1C circuit, where T represents a transistor and C represents a capacitor. However, the shift register unit shown in FIG15 can also use other circuits, such as 9T1C, 10T1C, etc.

[0127] FIG16 is a schematic diagram of a shift register unit according to another embodiment of the present disclosure. FIG17 is a circuit diagram of a specific implementation example of the shift register unit shown in FIG16. FIG18 is a layout diagram of the circuit shown in FIG17. FIG19 is an operating timing diagram of the shift register unit shown in FIG17.

[0128] As shown in FIG16 , the shift register unit includes an input circuit 610, an output circuit 620, and a reset circuit 630. The input circuit 610 is connected to a first node N1 and configured to provide an input signal to the first node N1. The reset circuit 630 is connected to the first node N1 and a reset terminal RST and configured to reset the first node N1 in response to a reset signal provided by the reset terminal RST. The output circuit 620 is connected to the first node N1 and an output terminal OUT and configured to output an output signal at the output terminal OUT under the control of the voltage level of the first node N1. The output circuit 620 includes an adjustable capacitor C, a first electrode of the adjustable capacitor C being connected to the output terminal OUT, and a second electrode of the adjustable capacitor C being connected to the first node N1 so as to change the capacitance of the adjustable capacitor C when the voltage of the first node N1 changes.

[0129] As shown in Figures 16 to 18, the output circuit 610 includes a transistor 621 electrically connected to the adjustable capacitor C, such as the third transistor M3 mentioned later, the control electrode of the transistor 621 is connected to the first node N1, one electrode of the transistor 621 is connected to the second electrode of the adjustable capacitor C, a semiconductor layer and an insulating layer are arranged between the first electrode of the adjustable capacitor C and the second electrode of the adjustable capacitor C, and the active layer of the transistor 621 is arranged on the same layer as the semiconductor layer of the adjustable capacitor C.

[0130] For example, the film layers in the adjustable capacitor may be shown in FIG4 , including a first metal layer 01, an insulating layer 02, a semiconductor layer 03, and a second metal layer 04 stacked in sequence. For example, the first electrode of the adjustable capacitor may be in the same layer as and electrically connected to the source or drain of the transistor M3, or the two may be integrated into one structure; the second electrode of the adjustable capacitor may be in the same layer as and electrically connected to the gate of the transistor M3, or the two may be integrated into one structure; and the semiconductor layer of the adjustable capacitor may be in the same layer as and spaced from the active layer of the transistor M3.

[0131] In the shift register provided by the present disclosure, the control end of the adjustable capacitor is connected to the first node, and the capacitance value of the adjustable capacitor increases as the voltage of the first node increases. When the first node is charged, the initial capacitance value of the adjustable capacitor is small, which can make the voltage at the first node increase quickly to improve the low-temperature startup capability; after the voltage of the first node is raised, the capacitance value of the adjustable capacitor increases, and when the display device including the shift register is applied to the touch stage, the voltage of the first node can be better maintained; when the first node is discharged, the capacitance value of the adjustable capacitor decreases accordingly, so that the first node can be discharged quickly.

[0132] In some examples, as shown in Figures 16 and 17, the input circuit 610 includes a first transistor M1, a first electrode of the first transistor M1 is connected to the first power supply terminal VDD, a second electrode of the first transistor M1 is connected to the first node N1, and a gate of the first transistor M1 is connected to the first signal control terminal INT. When the first signal control terminal INT outputs a high level, the first transistor M1 is turned on and outputs the voltage of the first power supply terminal VDD to the first node N1 for charging the first node N1. The first node N1 can be referred to as a pull-up node. When the first power supply terminal VDD provides a voltage to the first node N1, the capacitance value of the adjustable capacitor increases as the voltage of the first node increases.

[0133] In some examples, as shown in Figures 16 and 17, the reset circuit 630 includes a second transistor M2, a first electrode of the second transistor M2 is connected to the first node N1, a second electrode of the second transistor M2 is connected to the second power supply terminal VSS, and a gate of the second transistor M2 is connected to the second signal control terminal RST. For example, under the control of the second signal control terminal RST, the second transistor M2 outputs the voltage of the second power supply terminal VSS to the first node N1 for resetting the first node N1.

[0134] In some examples, as shown in Figures 16 and 17, the output circuit 620 further includes a third transistor M3, wherein a first electrode of the third transistor M3 is connected to the clock signal terminal CLK, a second electrode of the third transistor M3 is connected to the first electrode of the adjustable capacitor C, and a gate of the third transistor M3 is connected to the first node N1. When the first node N1 is at a high potential, the third transistor M3 is turned on, outputting the low level of the clock signal segment CLK to the output terminal OUT.

[0135] In some examples, as shown in FIG16 and FIG17 , the shift register unit further includes a fourth transistor M4 , a fifth transistor M5 , a sixth transistor M6 , a seventh transistor M7 , an eighth transistor M8 , a ninth transistor M9 , a tenth transistor M10 , and an eleventh transistor M11 .

[0136] In some examples, as shown in Figures 16 and 17, the fourth transistor M4 can be a structure in a pull-up node reset circuit, which is used to output the voltage of the third voltage terminal VGL to the first node N1 under the control of the frame reset signal terminal STV. The first electrode of the fourth transistor M4 is connected to the first node N1, the second electrode of the fourth transistor M4 is connected to the third voltage terminal VGL, and the gate of the fourth transistor M4 is connected to the frame reset signal terminal STV. For example, when the frame reset signal terminal STV outputs a high level, the fourth transistor M4 is turned on, so that the fourth transistor M4 inputs the low level of the third voltage terminal VGL to the first node N1 to reset the first node N1. For example, when the frame reset signal terminal STV outputs a low level, the fourth transistor M4 is turned off.

[0137] In some examples, as shown in Figures 16 and 17, the fifth transistor M5, the ninth transistor M9, the eighth transistor M8, and the sixth transistor M6 are structures in a pull-down control circuit. A first electrode of the fifth transistor M5 is connected to the fourth voltage terminal GCH, a second electrode of the fifth transistor M5 is connected to the second node N2, a gate of the fifth transistor M5 is connected to the second electrode of the ninth transistor M9, a first electrode of the ninth transistor M9 is connected to the fourth voltage terminal GCH, a gate of the ninth transistor M9 is connected to the fourth voltage terminal GCH, a first electrode of the sixth transistor M6 is connected to the second node N2, a second electrode of the sixth transistor M6 is connected to the third voltage terminal VGL, a gate of the sixth transistor M6 is connected to the first node N1, a first electrode of the eighth transistor M8 is connected to the gate of the fifth transistor M5, a second electrode of the eighth transistor M8 is connected to the third voltage terminal VGL, and a gate of the eighth transistor M8 is connected to the first node N1.

[0138] For example, as shown in FIG17 , the pull-down control circuit can control the potential of the second node N2 so that the second node N2 can control the noise reduction circuit (including the tenth transistor M10 described later) to pull the potential of the first node N1 down to the potential of the fourth voltage terminal GCH, thereby reducing noise on the first node N1. For example, under the control of a high potential at the first node N1, the sixth transistor M6 is turned on, and under the control of a high level at the fourth voltage terminal GCH, the fifth transistor M5 is turned on. However, because the width-to-length ratio of the channel of the sixth transistor M6 is greater than the width-to-length ratio of the channel of the fifth transistor M5, the potential of the second node N2 is still pulled down to the low level of the third voltage terminal VGL through the sixth transistor M6. For example, under the control of the high potential of the first node N1, the sixth transistor M6 and the eighth transistor M8 are turned on, and under the control of the high level of the fourth voltage terminal GCH, the ninth transistor M9 is turned on. However, since the width-to-length ratio of the channel of the eighth transistor M8 is greater than the width-to-length ratio of the channel of the ninth transistor M9, the gate of the fifth transistor M5 is at a low level, which controls the fifth transistor M5 to be turned off. The potential of the second node N2 is still pulled down to the low level of the third voltage terminal VGL through the sixth transistor M6.

[0139] In some examples, as shown in Figures 16 and 17, the seventh transistor M7 is included in the output terminal reset circuit. The signal output terminal reset circuit is connected to the frame reset signal terminal STV, the third voltage terminal VGL, and the output terminal OUT, and is configured to output the voltage of the third voltage terminal VGL to the signal output terminal OUT under the control of the frame reset signal terminal STV. A first electrode of the seventh transistor M7 is connected to the first node N1, a second electrode of the seventh transistor M7 is connected to the third voltage terminal VGL, and a gate of the seventh transistor M7 is connected to the frame reset signal terminal STV.

[0140] For example, as shown in FIG17 , a low level is input to the frame reset signal terminal STV, turning off the seventh transistor M7. For example, a high level is input to the frame reset signal terminal STV, turning on the seventh transistor M7, causing the seventh transistor M7 to input the low level of the third voltage terminal VGL to the output terminal OUT, thereby resetting the output terminal OUT.

[0141] In some examples, as shown in Figures 16 and 17, the tenth transistor M10 is included in the noise reduction circuit. The noise reduction circuit is connected to the second node N2, the third voltage terminal VGL, and the first node N1, and is configured to output the voltage of the third voltage terminal VGL to the first node N1 under the control of the second node N2. A first electrode of the tenth transistor M10 is connected to the first node N1, a second electrode of the tenth transistor M10 is connected to the third signal terminal VGL, and a gate of the tenth transistor M10 is connected to the second node N2.

[0142] In some examples, as shown in Figures 16 and 17, the eleventh transistor M11 is a structure in a pull-down circuit. The pull-down circuit is connected to the second node N2, the third voltage terminal VGL, and the output terminal OUT, and is configured to output the voltage of the third voltage terminal VGL to the signal output terminal OUT under the control of the second node N2. The first electrode of the eleventh transistor M11 is connected to the second electrode of the third transistor M3, the second electrode of the eleventh transistor M11 is connected to the third voltage terminal VGL, and the gate of the eleventh transistor M11 is connected to the first node N1.

[0143] For example, as shown in Figure 17, under the control of the low potential of the first node N1, the sixth transistor M6 is turned off, and the fifth transistor M5 is turned on under the control of the high level of the fourth voltage terminal GCH, and outputs the high level of the fourth voltage terminal GCH to the second node N2. Under the control of the high potential of the second node N2, the tenth transistor M10 and the eleventh transistor M11 are both turned on, and the potential of the first node N1 is pulled down to the low level of the third voltage terminal VGL through the tenth transistor M10, and the potential of the signal output terminal OUT is pulled down to the low level of the third voltage terminal VGL through the eleventh transistor M11.

[0144] In an embodiment of the present disclosure, for example, when each circuit is implemented as an N-type transistor, the term "pull-up" means charging a node or an electrode of a transistor so that the absolute value of the level of the node or the electrode increases, thereby realizing the operation of the corresponding transistor (for example, turn-on); "pull-down" means discharging a node or an electrode of a transistor so that the absolute value of the level of the node or the electrode decreases, thereby realizing the operation of the corresponding transistor (for example, turn-off).

[0145] For another example, when each circuit is implemented as a P-type transistor, the term "pull-up" means discharging a node or an electrode of a transistor so that the absolute value of the level of the node or the electrode is reduced, thereby realizing the operation of the corresponding transistor (for example, turn-on); "pull-down" means charging a node or an electrode of a transistor so that the absolute value of the level of the node or the electrode is increased, thereby realizing the operation of the corresponding transistor (for example, turn-off).

[0146] It should be noted that in the description of various embodiments of the present disclosure, the first node N1 and the second node N2 do not represent actual components, but represent junction points of related electrical connections in a circuit diagram.

[0147] It should be noted that the transistors used in the embodiments of the present disclosure may be thin film transistors, field effect transistors, or other switching devices with the same characteristics. The embodiments of the present disclosure are described using thin film transistors as examples. The source and drain of the transistors used here may be symmetrical in structure, so the source and drain may be structurally indistinguishable. In the embodiments of the present disclosure, in order to distinguish the two poles of the transistor other than the gate, one pole is directly described as the first pole and the other pole is directly described as the second pole.

[0148] In addition, the transistors in the embodiments of the present disclosure are all described by taking N-type transistors as an example. In this case, the first electrode of the transistor is the drain electrode and the second electrode is the source electrode. It should be noted that the present disclosure includes but is not limited to this. For example, one or more transistors in the shift register unit provided in the embodiments of the present disclosure may also adopt P-type transistors. In this case, the first electrode of the transistor is the source electrode and the second electrode is the drain electrode. It is only necessary to connect the electrodes of the selected type of transistors accordingly with reference to the electrodes of the corresponding transistors in the embodiments of the present disclosure, and make the corresponding voltage terminals provide the corresponding high voltage or low voltage. When an N-type transistor is used, indium gallium zinc oxide (IGZO) can be used as the active layer of the thin film transistor. Compared with using low temperature polysilicon (LTPS) or amorphous silicon (such as hydrogenated amorphous silicon) as the active layer of the thin film transistor, the size of the transistor can be effectively reduced and leakage current can be prevented.

[0149] For example, as shown in Figure 19, the frame reset signal terminal STV turns on four rows of dummy shift register units, and the OUT output signal corresponds to the clock signal terminals CLK5-6. Subsequent rows of shift register units are then turned on and matched to the corresponding CLK outputs. Figure 19 schematically illustrates the Nth frame and the N+1th frame, as well as the blank time between them. N can be a positive integer greater than or equal to 1.

[0150] The present disclosure also provides a gate drive circuit comprising a plurality of cascaded shift register units, wherein any one or more of the shift register units may employ the structure of the shift register unit provided in any embodiment of the present disclosure or a variation thereof, such as the shift register unit shown in FIG17 . For example, the gate drive circuit may be directly integrated onto an array substrate of a display device using the same semiconductor process as thin-film transistors to implement progressive or interlaced scanning drive functions.

[0151] An embodiment of the present disclosure provides a display device, comprising any of the above-mentioned array substrates or the above-mentioned shift register units.

[0152] The display device in this embodiment can be any product or component with a display function, such as a liquid crystal panel, a liquid crystal television, a monitor, a mobile phone, a tablet computer, a laptop computer, a digital photo frame, a navigator, etc. The display device can also include other conventional components such as a display panel, which is not limited in the embodiments of the present disclosure.

[0153] The technical effects of the display device provided by the embodiments of the present disclosure can be described with reference to the corresponding descriptions of the array substrate and the shift register unit in the above embodiments, which will not be repeated here.

[0154] There are a few points to note:

[0155] (1) The drawings of the embodiments of the present disclosure only involve structures related to the embodiments of the present disclosure, and other structures can refer to general designs.

[0156] (2) In the absence of conflict, features in the same embodiment and different embodiments of the present disclosure may be combined with each other.

[0157] The foregoing description is merely an exemplary embodiment of the present disclosure and is not intended to limit the scope of protection of the present disclosure. The scope of protection of the present disclosure is determined by the appended claims.

Claims

1. An array substrate, comprising: A substrate; A plurality of sub-pixels located on the substrate, the plurality of sub-pixels being arranged in an array along a first direction and a second direction, the first direction intersecting the second direction; A plurality of data lines located on the substrate and arranged along the first direction; A plurality of gate lines located on the substrate and arranged along the second direction; A plurality of first control signal lines located on the substrate and arranged along the second direction; Wherein, each of at least some of the sub-pixels includes a first sub-pixel portion and a second sub-pixel portion arranged along the second direction, the first sub-pixel portion includes a first pixel electrode, the second sub-pixel portion includes a second pixel electrode, the first pixel electrode and the second pixel electrode are arranged at intervals, and the first sub-pixel portion and the second sub-pixel portion share a common electrode; The first sub-pixel portion includes a first transistor, a first pole of the first transistor is connected to the first pixel electrode, the second sub-pixel portion includes a second transistor and a third transistor, a first pole of the second transistor and a first pole of the third transistor are both connected to the second pixel electrode, a control pole of the first transistor and a control pole of the second transistor are both connected to the same gate line, a second pole of the first transistor and a second pole of the second transistor are both connected to the same data line, and a control pole of the third transistor is connected to the first control signal line; Wherein, the array substrate further includes a second control signal line, the second sub-pixel portion further includes an adjustable capacitor, a first pole of the adjustable capacitor is connected to a second pole of the third transistor, and the second control signal line is connected to a second pole of the adjustable capacitor to apply a voltage to change the capacitance value of the adjustable capacitor; A semiconductor layer and an insulating layer are arranged between a first pole and a second pole of the adjustable capacitor, and the semiconductor layer, an active layer of the first transistor, an active layer of the second transistor, and an active layer of the third transistor are all arranged in the same layer; A first protrusion is arranged on a side of the second pixel electrode close to the first pixel electrode, a second protrusion is arranged on a side of the second pole of the adjustable capacitor close to the second pixel electrode, and the first control signal line includes a bent portion located between the first protrusion and the second protrusion.

2. The array substrate according to claim 1, wherein, The active layer of the first transistor, the active layer of the second transistor, the active layer of the third transistor, and the first pole and the second pole of the adjustable capacitor are all located between the first pixel electrode and the second pixel electrode.

3. The array substrate according to claim 2, wherein, The same gate line electrically connected to both the control pole of the first transistor and the control pole of the second transistor is located between the first pixel electrode and the second pixel electrode.

4. The array substrate according to claim 3, wherein, The first control signal line is located between the first pixel electrode and the second pixel electrode.

5. The array substrate according to claim 4, wherein, The second control signal line is located between the same gate line and the first control signal line.

6. The array substrate according to any one of claims 1-5, wherein, The multiple gate lines are located between the multiple data lines and the substrate, the second pole of the adjustable capacitor and the control poles of the transistors are disposed on the same layer as the multiple gate lines, and the first pole of the adjustable capacitor is disposed on the same layer as the multiple data lines.

7. The array substrate according to claim 1, wherein, A straight line extending along the second direction passes through the active layer of the second transistor and the semiconductor layer of the adjustable capacitor.

8. The array substrate according to claim 6, wherein, A straight line extending along the first direction passes through the control pole of the third transistor and the second pole of the adjustable capacitor.

9. The array substrate according to any one of claims 1-8, wherein, The first pole of the second transistor and the first pole of the third transistor are integrally formed, and the first pole of the third transistor is disposed on the same layer as the multiple data lines.

10. The array substrate according to any one of claims 1-9, wherein, The second pole of the third transistor and the first pole of the adjustable capacitor are integrally formed, and the second pole of the third transistor is located between at least a part of the first pole of the second transistor and the second pixel electrode.

11. The array substrate according to any one of claims 1-10, wherein, The multiple sub-pixels are arranged in multiple rows and columns. The multiple rows of sub-pixels are arranged along the second direction. The second poles of the adjustable capacitors in each row of sub-pixels are connected to the same second control signal line, and multiple second control signal lines connected to the adjustable capacitors of the multiple rows of sub-pixels are arranged along the second direction.

12. The array substrate according to claim 11, further comprising: At least one third control signal line and at least one pin electrically connected to the at least one third control signal line, wherein the extending direction of the at least one third control signal line is the same as the extending direction of the data lines, and the multiple second control signal lines are connected to the at least one third control signal line.

13. The array substrate according to claim 11 further includes a plurality of pins, wherein, Each second control signal line is connected to one pin so that each second control signal line is configured to input a control signal separately.

14. An array substrate, comprising: A substrate; Multiple sub-pixels, located on the substrate, the multiple sub-pixels are arranged in an array along a first direction and a second direction, and the first direction intersects with the second direction; Multiple data lines, located on the substrate and arranged along the first direction; Multiple gate lines, located on the substrate and arranged along the second direction; wherein each sub-pixel includes a transistor and a pixel electrode and a common electrode arranged in a stacked manner, the first pole of the transistor is connected to the data line, the second pole of the transistor is connected to the pixel electrode, and the control pole of the transistor is connected to the gate line; The array substrate further includes at least one control signal line, and at least some of the sub-pixels further include an adjustable capacitor. The adjustable capacitor includes a first pole, a semiconductor layer, and a second pole that are sequentially stacked in a direction perpendicular to the substrate. The semiconductor layer is on the same layer as the active layer of the transistor and is spaced apart. The first pole of the adjustable capacitor is connected to the pixel electrode, and the control signal line is connected to the second pole of the adjustable capacitor to apply a voltage to change the capacitance value of the adjustable capacitor, and a straight line extending along the first direction passes through the active layer and the semiconductor layer.

15. The array substrate according to claim 14, wherein, At least one gate line is multiplexed as the control signal line.

16. The array substrate according to claim 14, wherein, The gate lines and the control signal lines are arranged at intervals, and the second pole of the adjustable capacitor is completely located between the control signal line and the pixel electrode connected to the first pole of the adjustable capacitor.

17. The array substrate according to claim 16, wherein, The control pole of the transistor is arranged on the same layer as the gate line. The control pole includes two parts located on both sides of the gate line. The dimension of the part closer to the adjustable capacitor in the second direction is the first dimension, and the dimension of the part farther from the adjustable capacitor in the second direction is the second dimension. The first dimension is greater than the second dimension.

18. The array substrate according to any one of claims 14-17, wherein, The second pole of the transistor is arranged at intervals from the first pole of the adjustable capacitor.

19. The array substrate according to claim 16 or 17, wherein The control signal line is arranged on the same layer as the gate line; The multiple sub-pixels are arranged in multiple rows and multiple columns. The multiple rows of sub-pixels are arranged along the second direction. The second poles of the adjustable capacitors in each row of sub-pixels are connected to the same control signal line, and the multiple control signal lines connected to the adjustable capacitors of the multiple rows of sub-pixels are arranged along the second direction.

20. The array substrate according to claim 19, further comprising: At least one control signal connection line and at least one pin electrically connected to the at least one control signal connection line, Wherein, the extending direction of the at least one control signal connection line is the same as the extending direction of the data line, and the multiple control signal lines are connected to the at least one control signal connection line.

21. The array substrate according to claim 19 further includes a plurality of pins, wherein, Each control signal line is connected to a pin so that each control signal line is configured to input a control signal separately.

22. The array substrate according to claim 19, further comprising: Multiple rows of shift register units located on the substrate, Wherein, the shift register unit includes an input circuit, an output circuit and a node noise reduction circuit; The input circuit is connected to the first node and is configured to provide an input signal to the first node; The node noise reduction circuit is connected to the first node and the second node, and is configured to perform noise reduction on the first node under the control of the level of the second node; The output circuit is connected to the first node and the output terminal, and is configured to output an output signal at the output terminal under the control of the level of the first node, Wherein, each control signal line is connected to the second node of the shift register unit in the same row as it.

23. A shift register unit, comprising an input circuit, an output circuit and a reset circuit, Among them, The input circuit is connected to the first node and is configured to provide an input signal to the first node; The reset circuit is connected to the first node and the reset terminal, and is configured to reset the first node in response to the reset signal provided by the reset terminal; The output circuit is connected to the first node and the output terminal, and is configured to output an output signal at the output terminal under the control of the level of the first node, Wherein, the output circuit includes an adjustable capacitor. The first pole of the adjustable capacitor is connected to the output terminal, and the first node is connected to the second pole of the adjustable capacitor to change the capacitance value of the adjustable capacitor when the voltage of the first node changes; The output circuit includes a transistor electrically connected to the adjustable capacitor. A control electrode of the transistor is connected to the first node. One electrode of the transistor is connected to a second electrode of the adjustable capacitor. A semiconductor layer and an insulating layer are provided between a first electrode and the second electrode of the adjustable capacitor. An active layer of the transistor is provided on the same layer as the semiconductor layer of the adjustable capacitor.

24. The shift register unit according to claim 23, wherein, The input circuit includes a first transistor. A first electrode of the first transistor is connected to a first power supply terminal. A second electrode of the first transistor is connected to the first node. A gate of the first transistor is connected to a first signal control terminal. The reset circuit includes a second transistor. A first electrode of the second transistor is connected to the first node. A second electrode of the second transistor is connected to a second power supply terminal. A gate of the second transistor is connected to a second signal control terminal. The output circuit further includes a third transistor. A first electrode of the third transistor is connected to a clock signal terminal. A second electrode of the third transistor is connected to the first electrode of the adjustable capacitor. A gate of the third transistor is connected to the first node. The shift register unit further includes a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, and an eleventh transistor. Among them, a first electrode of the fourth transistor is connected to the first node. A second electrode of the fourth transistor is connected to a third voltage terminal. A gate of the fourth transistor is connected to a frame reset signal terminal. A first electrode of the fifth transistor is connected to a fourth voltage terminal. A second electrode of the fifth transistor is connected to a second node. A first electrode of the sixth transistor is connected to the second node. A second electrode of the sixth transistor is connected to the third voltage terminal. A gate of the sixth transistor is connected to the first node. A first electrode of the seventh transistor is connected to the first node. A second electrode of the seventh transistor is connected to the third voltage terminal. A gate of the seventh transistor is connected to the frame reset signal terminal. A first electrode of the eighth transistor is connected to a gate of the fifth transistor. A second electrode of the eighth transistor is connected to the third voltage terminal. A gate of the eighth transistor is connected to the first node. A first electrode of the ninth transistor is connected to the fourth voltage terminal. A second electrode of the ninth transistor is connected to the first electrode of the eighth transistor. A gate of the ninth transistor is connected to the fourth voltage terminal. A first electrode of the tenth transistor is connected to the first node. A second electrode of the tenth transistor is connected to a third signal terminal. A gate of the tenth transistor is connected to the second node. A first electrode of the eleventh transistor is connected to the second electrode of the third transistor. A second electrode of the eleventh transistor is connected to the third voltage terminal. A gate of the eleventh transistor is connected to the first node.

25. A display device, comprising the array substrate according to any one of claims 1-22 or the shift register unit according to claim 23 or 24.

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