Electronic paper display panel, display apparatus and driving method

Abstract

An electronic paper display panel, a display apparatus and a driving method. The electronic paper display panel comprises: a plurality of sub-pixels (2), each of which comprises a first conduction circuit (10), a second conduction circuit (20) and a pixel electrode (3), wherein the first conduction circuit (10) and second conduction circuit (20) in the same sub-pixel (2) are both coupled to the pixel electrode (3), the first conduction circuit (10) is configured to provide a reset signal from a reset signal end (RE) to the pixel electrode (3) in response to a signal from a first control signal end (CS1), the second conduction circuit (20) is configured to provide a data signal from a data signal end (DA) to the pixel electrode (3) in response to a signal from a second control signal end (CS2), and the first conduction circuit (10) and second conduction circuit (20) in the same sub-pixel (2) work in a time-sharing manner; and a gate driving circuit (30), which comprises a plurality of shift registers (SR), wherein in the same sub-pixel (2), the first control signal end (CS1) corresponding to the first conduction circuit (10) and the second control signal end (CS2) corresponding to the second conduction circuit (20) are connected to different shift registers (SR).

Description

Electronic paper display panel, display device and driving method

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office of the People's Republic of China on May 17, 2023, with application number 202310558987.8 and invention name "Electronic paper display panel, display device and driving method", the entire contents of which are incorporated by reference into this application. Technical Field

[0003] The present disclosure relates to the field of display technology, and in particular to an electronic paper display panel, a display device, and a driving method. Background Art

[0004] Electronic paper display products have attracted widespread attention due to their eye-protection and power-saving properties. Non-encapsulated electrophoretic display structures offer advantages in terms of increased reflectivity, reduced response time, and improved grayscale capabilities.

[0005] In a non-capsule electrophoretic display structure, an electrophoretic liquid layer is formed on the backplane surface, and then the upper glass substrate is covered with this layer using a vacuum cell assembly method. The electrophoretic liquid in the electrophoretic liquid layer contains charged particles. By controlling the vertical electric field generated by electrodes located on both sides of the electrophoretic liquid layer, the concentration of charged particles at the bottom and top of the cell is adjusted to achieve different grayscale levels.

[0006] Summary of the Invention

[0007] The electronic paper display panel provided by the embodiment of the present disclosure includes:

[0008] A plurality of sub-pixels, each of the plurality of sub-pixels comprising: a first conductive circuit, a second conductive circuit, and a pixel electrode; wherein the first conductive circuit and the second conductive circuit in the same sub-pixel are both coupled to the pixel electrode; the first conductive circuit is configured to provide a reset signal at a reset signal terminal to the pixel electrode in response to a signal at a first control signal terminal; and the second conductive circuit is configured to provide a data signal at a data signal terminal to the pixel electrode in response to a signal at a second control signal terminal; wherein the first conductive circuit and the second conductive circuit in the same sub-pixel operate in a time-sharing manner;

[0009] The gate driving circuit includes a plurality of shift registers, and the first control signal terminal corresponding to the first conduction circuit and the second control signal terminal corresponding to the second conduction circuit in the same sub-pixel are connected to different shift registers.

[0010] In some possible implementations, the first conduction circuit includes: a first transistor; a gate of the first transistor coupled to the first control signal terminal, a first electrode of the first transistor coupled to the reset signal terminal, and a second electrode of the first transistor coupled to the pixel electrode.

[0011] In some possible implementations, the second conduction circuit includes: a second transistor; a gate of the second transistor coupled to the second control signal terminal, a first electrode of the second transistor coupled to the data signal terminal, and a second electrode of the second transistor coupled to the pixel electrode.

[0012] In some possible implementations, the method further includes: a plurality of first scan signal lines and a plurality of second scan signal lines;

[0013] The first control signal terminals corresponding to the sub-pixels in a row are all coupled to a first scanning signal line among the plurality of first scanning signal lines;

[0014] The second control signal terminals corresponding to a row of the sub-pixels are all coupled to a second scanning signal line among the plurality of second scanning signal lines.

[0015] In some possible implementations, the plurality of shift registers include: a plurality of first shift registers, a plurality of second shift registers;

[0016] A first shift register among the plurality of first shift registers is coupled to a first scan signal line among the plurality of first scan signal lines;

[0017] One of the plurality of second shift registers is coupled to one of the plurality of second scan signal lines.

[0018] In some possible implementations, the plurality of shift registers include: a plurality of third shift registers;

[0019] A third shift register among the plurality of third shift registers is coupled to a first scan signal line among the plurality of first scan signal lines;

[0020] The first scanning signal line corresponding to the sub-pixels in the mth row is coupled to the second scanning signal line corresponding to the sub-pixels in the nth row, where m is greater than n; both m and n are positive integers.

[0021] In some possible implementations, the method further includes: a plurality of reset signal lines and a plurality of data lines;

[0022] The reset signal terminals corresponding to the sub-pixels in a column are coupled to a reset signal line among the plurality of reset signal lines;

[0023] The data signal terminals corresponding to a column of the sub-pixels are coupled to a data line among the plurality of data lines.

[0024] In some possible implementations, the further comprising: a plurality of gating control circuits and a plurality of source driving input terminals; a column of the sub-pixels corresponds to one gating control circuit of the plurality of gating control circuits and one source driving input terminal of the plurality of source driving input terminals;

[0025] The source drive input terminal is coupled to the reset signal line and data line of the corresponding column sub-pixel through the corresponding selection control circuit, and the selection control circuit is configured to provide the signal of the source drive input terminal to the corresponding reset signal line in response to the signal of the first selection control terminal, and to provide the signal of the source drive input terminal to the corresponding data line in response to the signal of the second selection control terminal.

[0026] In some possible implementations, the gating control circuit includes: a first gating control transistor, a second gating control transistor;

[0027] The gate of the first gating control transistor is coupled to the first gating control terminal, the first electrode of the first gating control transistor is coupled to the reset signal line, and the second electrode of the first gating control transistor is coupled to the source driving input terminal;

[0028] The gate of the second gating control transistor is coupled to the second gating control terminal, the first electrode of the second gating control transistor is coupled to the data line, and the second electrode of the second gating control transistor is coupled to the source driving input terminal.

[0029] In some possible implementations, the multiple reset signal lines are coupled to each other.

[0030] In some possible implementations, the method further includes: a plurality of data lines and a plurality of source driving input terminals; a column of the sub-pixels corresponds to one data line of the plurality of data lines and one source driving input terminal of the plurality of source driving input terminals;

[0031] The data signal terminals corresponding to a column of the sub-pixels are coupled to the corresponding source driving input terminals through the corresponding data lines.

[0032] In some possible implementations, the method further includes: a first base substrate; the plurality of sub-pixels are located on one side of the first base substrate;

[0033] Each of the plurality of sub-pixels further comprises:

[0034] a common electrode, located on a side of the pixel electrode facing away from the first substrate;

[0035] an electrophoretic liquid layer, located between the pixel electrode and the common electrode, and comprising a plurality of charged particles;

[0036] The pixel electrode is configured to drive the plurality of charged particles to adjust the grayscale display.

[0037] The display device provided by the embodiment of the present disclosure includes the above-mentioned electronic paper display panel.

[0038] The present disclosure also provides a method for driving the electronic paper display panel, including:

[0039] In the first stage, the first conduction circuit provides the reset signal of the reset signal terminal to the pixel electrode in response to the signal of the first control signal terminal;

[0040] In the second stage, the second conduction circuit provides the data signal of the data signal terminal to the pixel electrode in response to the signal of the second control signal terminal;

[0041] The first conducting circuit and the second conducting circuit in the same sub-pixel operate in a time-sharing manner.

[0042] In some possible implementations, the reset signal input to the pixel electrode in the same sub-pixel has an opposite potential to that of the data signal.

[0043] In some possible implementations, the potential of the reset signal input to the pixel electrode in each of the sub-pixels is a fixed potential. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] FIG1 is a schematic diagram of some structures of an electronic paper display panel provided by an embodiment of the present disclosure;

[0045] FIG2 is a schematic diagram of another structure of an electronic paper display panel provided by an embodiment of the present disclosure;

[0046] FIG3 is a schematic diagram of some further structures of the electronic paper display panel provided by an embodiment of the present disclosure;

[0047] FIG4 is a schematic diagram of some further structures of the electronic paper display panel provided by an embodiment of the present disclosure;

[0048] FIG5 is a schematic diagram of some further structures of the electronic paper display panel provided by an embodiment of the present disclosure;

[0049] FIG6 is a schematic diagram of some further structures of the electronic paper display panel provided by an embodiment of the present disclosure;

[0050] FIG7 is a flow chart of a driving method of an electronic paper display panel provided by an embodiment of the present disclosure;

[0051] FIG8 is a timing diagram of some signals provided by an embodiment of the present disclosure;

[0052] FIG9 is a schematic diagram of some further structures of the electronic paper display panel provided by an embodiment of the present disclosure;

[0053] FIG10 is a schematic diagram of some further structures of the electronic paper display panel provided by an embodiment of the present disclosure;

[0054] FIG11 is another signal timing diagram provided by an embodiment of the present disclosure;

[0055] FIG12 is a schematic diagram of some further structures of the electronic paper display panel provided by an embodiment of the present disclosure;

[0056] FIG13 is a timing diagram of some further signals provided by an embodiment of the present disclosure;

[0057] FIG14 is a schematic diagram of some further structures of the electronic paper display panel provided by an embodiment of the present disclosure;

[0058] FIG15 is a further signal timing diagram provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0059] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. And in the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0060] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0061] It should be noted that the sizes and shapes of the figures in the accompanying drawings do not reflect the actual scale and are only for the purpose of illustrating the present disclosure. The same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions.

[0062] The embodiment of the present disclosure provides an electronic paper display panel, as shown in FIG1 , comprising: a first base substrate 1, and a plurality of sub-pixels 2; the plurality of sub-pixels 2 are located on one side of the first base substrate;

[0063] Each sub-pixel 2 in the plurality of sub-pixels includes:

[0064] pixel electrode 3;

[0065] The common electrode 6 is located on a side of the pixel electrode 3 facing away from the first substrate 1;

[0066] The electrophoretic liquid layer 35 is located between the pixel electrode 3 and the common electrode 6 and includes a plurality of charged particles 7 , wherein the pixel electrode 3 is configured to drive the plurality of charged particles 7 to adjust the grayscale display.

[0067] In some possible embodiments, as shown in FIG. 1 , the electronic paper display panel further includes: a second base substrate 34 located on a side of the common electrode 6 facing away from the first base substrate 1 .

[0068] In a specific implementation, for example, a pixel electrode can be formed on a first base substrate to obtain a first substrate; a common electrode can be formed on a second base substrate to obtain a second substrate; an electrophoretic liquid layer can be formed on one side of the first substrate, and then a vacuum box-matching process can be used to cover the second substrate with the electrophoretic liquid layer to obtain the structure of the electronic paper display panel provided in the embodiment of the present disclosure.

[0069] In a specific implementation, the common electrodes of different sub-pixels are loaded with the same common electrode voltage. By controlling the voltages loaded on the pixel electrodes to be different, each sub-pixel can present a desired grayscale. Accordingly, in some embodiments, the common electrodes of multiple sub-pixels can be connected as a whole, that is, the common electrode is a planar electrode provided on the entire surface of one side of the second substrate. In a specific implementation, the common electrode is, for example, a transparent electrode, and the material of the common electrode includes indium tin oxide (ITO).

[0070] In some possible embodiments, in a direction perpendicular to the first substrate, the distance between the pixel electrode and the common electrode is greater than or equal to 5 micrometers and less than or equal to 20 micrometers. For example, the distance between the pixel electrode and the common electrode can be 7 micrometers, 10 micrometers, or 15 micrometers.

[0071] In some possible embodiments, as shown in FIG2 , the electronic paper display panel further includes a second insulating layer 5 located between the pixel electrode 3 and the electrophoretic liquid layer 35. The electronic paper display panel provided by the embodiments of the present disclosure further includes a second insulating layer disposed between the pixel electrode and the electrophoretic liquid layer. This prevents contact between charged particles and the pixel electrode, preventing adsorption and aggregation of charged particles at the pixel electrode that could affect the display effect. It also prevents direct contact between the pixel electrode and charged particles, resulting in electrochemical corrosion that could affect the lifespan of the electronic paper display panel.

[0072] As shown in FIG. 3 , the electronic paper display panel further includes a reflective layer 19 located between the first base substrate 1 and the electrophoretic liquid layer 35 .

[0073] The electronic paper display panel provided by the embodiment of the present disclosure includes a reflective layer, so that light can be reflected after reaching the reflective layer, thereby improving the reflectivity.

[0074] Exemplarily, light is incident from a side of the second substrate facing away from the common electrode.

[0075] For example, the larger the area of ​​the reflective layer blocked by the black charged particles is, the lower the brightness of the pixel light is; and the smaller the area of ​​the reflective layer blocked by the black charged particles is, the higher the brightness of the pixel light is.

[0076] For example, in conjunction with Figures 1 to 3, the multiple charged particles can be black charged particles, and the black charged particles are positively charged. The black charged particles move in response to the bias between the common electrode and the pixel electrode. When the voltage bias causes the black charged particles to move near the top of the electrophoretic liquid layer (i.e., near the common electrode), the black charged particles may enter the first region Z1 (e.g., to a depth of up to about 1 micron) and suppress total internal reflection (TIR). The depth of the first region Z1 may vary depending on the wavelength of the incident light, the angle of the incident light, and the refractive index of the front sheet and the medium. The incident light may be absorbed by the black charged particles, thereby producing a black state or a dark state. In such cases, the electronic paper display panel may display a dark or black color. When the black charged particles move away from the first region Z1 (e.g., by reverse bias), the light may be reflected by total internal reflection (TIR). This results in a white state or a bright state at one or more sub-pixels. The pixel electrode may be used to drive black charged particles into or out of the first region Z1 to form a combination of a black state and a white state, thereby being used to generate an image.

[0077] Exemplarily, the plurality of charged particles may also include black charged particles and white charged particles, which is not limited here.

[0078] In some embodiments, as shown in FIG. 3 , the reflective layer 19 is located between the first base substrate 1 and the pixel electrode 3 .

[0079] In some embodiments, as shown in FIG. 3 , the reflective layer 19 includes a metal material, and the electronic paper display panel further includes a first insulating layer 9 located between the reflective layer 19 and the pixel electrode 3 .

[0080] In some embodiments, as shown in FIG1 to FIG3 , the electronic paper display panel further includes a plurality of barrier structures 33. That is, the barrier structures are provided to prevent charged particles from moving toward adjacent sub-pixels.

[0081] The electronic paper display panel provided by the embodiment of the present disclosure, as shown in Figure 4, each of the multiple sub-pixels 2 may also include: a first conduction circuit 10 and a second conduction circuit 20; wherein, the first conduction circuit 10 and the second conduction circuit 20 in the same sub-pixel 2 are both coupled to the pixel electrode 3; the first conduction circuit 10 is configured to respond to the signal of the first control signal terminal CS1 and provide the reset signal of the reset signal terminal RE to the pixel electrode 3; the second conduction circuit 20 is configured to respond to the signal of the second control signal terminal CS2 and provide the data signal of the data signal terminal DA to the pixel electrode 3; wherein, the first conduction circuit 10 and the second conduction circuit 20 in the same sub-pixel 2 work in a time-sharing manner.

[0082] In some embodiments of the present disclosure, as shown in Figure 4, the electronic paper display panel also includes: a gate driving circuit 30, including multiple shift registers SR, and the first control signal terminal CS1 corresponding to the first conduction circuit 10 in the same sub-pixel 2 and the second control signal terminal CS2 corresponding to the second conduction circuit 20 are connected to different shift registers.

[0083] The disclosed embodiments control the signal on the pixel electrode through the interaction of a gate drive circuit, a first conduction circuit, and a second conduction circuit. By controlling the first and second conduction circuits in the same sub-pixel to operate in a time-sharing manner through the gate drive circuit, the use of integrated circuit chips (ICs) can be reduced, thereby lowering production costs.

[0084] In some embodiments of the present disclosure, as shown in Figure 5, the first conduction circuit 10 includes: a first transistor T1; wherein the gate of the first transistor T1 is coupled to the first control signal terminal CS1, the first electrode of the first transistor T1 is coupled to the reset signal terminal RE, and the second electrode of the first transistor T1 is coupled to the pixel electrode 3.

[0085] For example, the first transistor T1 can be turned on under the control of the active level of the first control signal transmitted by the first control signal terminal CS1, and can be turned off under the control of the inactive level of the first control signal. For example, if the first transistor T1 is configured as a P-type transistor, the active level of the first control signal is a low level, and the inactive level of the first control signal is a high level. Alternatively, if the first transistor T1 is configured as an N-type transistor, the active level of the first control signal is a high level, and the inactive level of the first control signal is a low level.

[0086] In some embodiments of the present disclosure, as shown in Figure 5, the second conduction circuit 20 includes: a second transistor T2; wherein the gate of the second transistor T2 is coupled to the second control signal terminal CS2, the first electrode of the second transistor T2 is coupled to the data signal terminal DA, and the second electrode of the second transistor T2 is coupled to the pixel electrode 3.

[0087] For example, the second transistor T2 can be turned on under the control of the active level of the second control signal transmitted by the second control signal terminal CS2, and can be turned off under the control of the inactive level of the second control signal. For example, if the second transistor T2 is configured as a P-type transistor, the active level of the second control signal is a low level, and the inactive level of the second control signal is a high level. Alternatively, if the second transistor T2 is configured as an N-type transistor, the active level of the second control signal is a high level, and the inactive level of the second control signal is a low level.

[0088] In some embodiments of the present disclosure, as shown in Figures 4 and 5, it also includes: multiple first scanning signal lines Cs1 and multiple second scanning signal lines Cs2; wherein, the first control signal terminals CS1 corresponding to a row of sub-pixels 2 are all coupled to a first scanning signal line Cs1 among the multiple first scanning signal lines Cs1; the second control signal terminals CS2 corresponding to a row of sub-pixels 2 are all coupled to a second scanning signal line Cs2 among the multiple second scanning signal lines Cs2.

[0089] In some embodiments of the present disclosure, as shown in Figures 4 and 5, multiple shift registers SR include: multiple first shift registers (for example, SR_A1, SR_A2, SR_An in Figure 5), multiple second shift registers (for example, SR_B1, SR_B2, SR_Bn in Figure 5); one first shift register (for example, SR_A1, SR_A2, SR_An in Figure 5) among the multiple first shift registers (for example, SR_A1, SR_A2, SR_An in Figure 5) is coupled to a first scan signal line Cs1 among the multiple first scan signal lines Cs1; one second shift register (for example, SR_B1, SR_B2, SR_Bn in Figure 5) among the multiple second shift registers (for example, SR_B1, SR_B2, SR_Bn in Figure 5) is coupled to a second scan signal line Cs2 among the multiple second scan signal lines Cs2.

[0090] Exemplarily, as shown in FIG6 , the electronic paper display panel further includes: a trigger signal line (e.g., STVA and STVB in FIG6 ), a clock signal line (e.g., CLK1, CLK2, CLK3, and CLK4 in FIG6 ). Multiple first shift registers (e.g., SR_A1, SR_A2, SR_A3, and SR_An in FIG6 ) all include output signal terminals (e.g., OUTA1, OUTA2, OUTA3, and OUTAn in FIG6 ) and reset signal terminals (e.g., RSA1, RSA2, RSA3, and RSAn in FIG6 ). Multiple second shift registers (e.g., SR_B1, SR_B2, SR_B3, and SR_Bn in FIG6 ) all include output signal terminals (e.g., OUTB1, OUTB2, OUTB3, and OUTBn in FIG6 ) and reset signal terminals (e.g., RSB1, RSB2, RSB3, and RSBn in FIG6 ). The trigger signal for the first-stage shift register is derived from the signal loaded on the trigger signal line, while the signal at the output signal terminal of the previous-stage shift register serves as the trigger signal for the next-stage shift register, and the signal at the output signal terminal of the next-stage shift register serves as the signal at the reset signal terminal of the previous-stage shift register. For example, the first shift register SR_A1 is coupled to the trigger signal line STVA, and the signal at the output signal terminal OUTA1 of the first shift register SR_A1 serves as the trigger signal for the first shift register SR_A2, while the signal at the output signal terminal OUTA2 of the first shift register SR_A2 serves as the signal at the reset signal terminal RSA1 of the first shift register SR_A1.

[0091] In some embodiments of the present disclosure, as shown in Figure 5, it also includes: multiple reset signal lines (for example, Re1, Re2, Ren in Figure 5) and multiple data lines (for example, Da1, Da2, Dan in Figure 5); wherein, the reset signal terminal RE corresponding to a column of sub-pixels 2 is coupled to one reset signal line (for example, Re1, Re2, Ren in Figure 5) among the multiple reset signal lines (for example, Re1, Re2, Ren in Figure 5); the data signal terminal DA corresponding to a column of sub-pixels 2 is coupled to one data line (for example, Da1, Da2, Dan in Figure 5) among the multiple data lines (for example, Da1, Da2, Dan in Figure 5).

[0092] Exemplarily, as shown in Figure 5, multiple source drive input terminals (for example, SDP1, SDP2, SDPn in Figure 5) are also included, and one data line (for example, Da1, Da2, Dan in Figure 5) among the multiple data lines (for example, Da1, Da2, Dan in Figure 5) is coupled to one source drive input terminal (for example, SDP1, SDP2, SDPn in Figure 5) among the multiple source drive input terminals (for example, SDP1, SDP2, SDPn in Figure 5).

[0093] For example, the first electrode of the transistor can be its source electrode, and the second electrode can be its drain electrode. Alternatively, the first electrode can be its drain electrode, and the second electrode can be its source electrode. This is not limited here.

[0094] Generally, transistors using low-temperature polysilicon (LTPS) as active layers have high mobility and can be made thinner and smaller, with lower power consumption. In a specific implementation, the active layer of at least one of the transistors can be made of low-temperature polysilicon. This allows the transistor to be configured as an LTPS transistor, thereby achieving high mobility, thinner and smaller size, and lower power consumption.

[0095] Generally, transistors using metal oxide semiconductor materials as active layers have low leakage current. Therefore, in order to reduce leakage current, in some embodiments of the present disclosure, the active layer of at least one transistor may include a metal oxide semiconductor material, such as IGZO (Indium Gallium Zinc Oxide). Of course, other metal oxide semiconductor materials are also possible and are not limited here. In this way, the transistor can be configured as an oxide thin film transistor to reduce leakage current.

[0096] Generally, amorphous silicon (a-Si) material can also be used as the active layer. In specific implementation, the material of the active layer of the at least one transistor can be set to amorphous silicon, so that the transistor can be set as an a-Si type transistor.

[0097] For example, all transistors can be configured as LTPS transistors. Alternatively, all transistors can be configured as oxide transistors. Since metal oxides are relatively low-cost, there is no need to use laser equipment for crystallization. Alternatively, some transistors can be configured as oxide transistors, while the remaining transistors can be configured as LTPS transistors. Alternatively, all transistors can be configured as a-Si transistors.

[0098] For example, as shown in FIG4 and FIG5 , the voltage applied to the common electrode 6 is the common electrode voltage Vcom. In practical applications, the specific value of the common electrode voltage Vcom can be designed and determined according to the actual application environment and is not limited here.

[0099] The driving method of the electronic paper display panel provided by the embodiment of the present disclosure, as shown in FIG7 , includes:

[0100] S100, in the first stage, the first conduction circuit provides a reset signal from the reset signal terminal to the pixel electrode in response to a signal from the first control signal terminal;

[0101] S200, second stage, the second conduction circuit responds to the signal of the second control signal terminal and provides the data signal of the data signal terminal to the pixel electrode;

[0102] The first conducting circuit and the second conducting circuit in the same sub-pixel operate in a time-sharing manner.

[0103] In some embodiments of the present disclosure, the reset signal input to the pixel electrode in the same sub-pixel has an opposite potential to that of the data signal. For example, if the reset signal input to the pixel electrode in the same sub-pixel is a high potential signal, the data signal is a low potential signal. Alternatively, if the reset signal input to the pixel electrode in the same sub-pixel is a low potential signal, the data signal is a high potential signal. This is not limited here. By setting the reset signal input to the pixel electrode in the same sub-pixel to have an opposite potential to that of the data signal, DC balance can be achieved to prevent low potential accumulation or high potential accumulation in the pixel electrode.

[0104] In some embodiments of the present disclosure, the potential of the reset signal input to the pixel electrode of each sub-pixel is a fixed potential. In actual applications, the specific value of the potential of the reset signal can be designed and determined according to the actual application environment and is not limited here.

[0105] The following describes the working process of the electronic paper display panel provided by the embodiment of the present disclosure by taking the electronic paper display panel shown in FIG. 5 as an example and combining it with the signal timing diagram shown in FIG. 8 .

[0106] As shown in Figure 8, stva represents the trigger signal loaded on the trigger signal line STVA, stvb represents the trigger signal loaded on the trigger signal line STVB, clk1 represents the clock signal loaded on the clock signal line CLK1, clk2 represents the clock signal loaded on the clock signal line CLK2, clk3 represents the clock signal loaded on the clock signal line CLK4, clk4 represents the clock signal loaded on the clock signal line CLK4, outa1 represents the scan drive signal loaded on the output signal terminal OUTA1, outa2 represents the scan drive signal loaded on the output signal terminal OUTA2, outb1 represents the scan drive signal loaded on the output signal terminal OUTB1, and outb2 represents the scan drive signal loaded on the output signal terminal OUTB2.

[0107] In the first stage, a reset signal is input to the sub-pixel 2 controlled by multiple first shift registers (e.g., SR_A1, SR_A2, and SR_An in FIG5 ) in the gate drive circuit 30, thereby resetting the electronic paper display panel. Specifically, the first shift register SR_A1 among the multiple first shift registers applies a scan drive signal to the first first scan signal line Cs1 among the multiple first scan signal lines, the second shift register SR_A2 among the multiple first shift registers applies a scan drive signal to the second first scan signal line Cs1 among the multiple first scan signal lines, and the nth shift register SR_An among the multiple first shift registers applies a scan drive signal to the nth first scan signal line Cs1 among the multiple first scan signal lines. When a high level appears in the scan drive signals outa1 to outan, the first control signal terminal CS1 coupled to the first scan signal line Cs1 can be controlled to apply a high level signal. The first transistor T1 is turned on under the control of the high level signal and provides the reset signal from the reset signal terminal RE to the pixel electrode 3.

[0108] In the second phase, the sub-pixels 2 controlled by the plurality of second shift registers (e.g., SR_B1, SR_B2, and SR_Bn in FIG. 5 ) in the gate drive circuit 30 input data signals, thereby driving the electronic paper display panel to display an image. Specifically, the first shift register SR_B1 in the plurality of second shift registers applies a scan drive signal to the first second scan signal line Cs2 in the plurality of second scan signal lines, the second shift register SR_B2 in the plurality of second shift registers applies a scan drive signal to the second second scan signal line Cs2 in the plurality of second scan signal lines, and the nth shift register SR_Bn in the plurality of second shift registers applies a scan drive signal to the nth second scan signal line Cs2 in the plurality of second scan signal lines. When a high level appears in the scan drive signals outb1 to outbn, the second control signal terminal CS2 coupled to the second scan signal line Cs2 can be controlled to apply a high level signal. The second transistor T2 is turned on under the control of the high level signal, and provides the data signal from the data signal terminal DA to the pixel electrode 3.

[0109] The present disclosure provides other embodiments of electronic paper display panels, which are modifications of the embodiments described above. The following only describes the differences between this embodiment and the above embodiment, and the similarities are not repeated here.

[0110] In some other embodiments of the present disclosure, as shown in FIG9 , a plurality of reset signal lines (eg, Re1 , Re2 , and Ren in FIG9 ) are coupled to each other.

[0111] The present disclosure provides further embodiments of electronic paper display panels, which are modifications of the embodiments described above. The following only describes the differences between this embodiment and the above embodiments, and the similarities are not repeated here.

[0112] In some other embodiments of the present disclosure, as shown in FIG10 , the present invention includes: a plurality of data lines (e.g., Da1, Da2, Dan in FIG10 ), a plurality of source drive input terminals (e.g., SDP1, SDP2, SDPn in FIG10 ); a column of sub-pixels 2 corresponds to one data line (e.g., Da1, Da2, Dan in FIG10 ) among the plurality of data lines (e.g., Da1, Da2, Dan in FIG10 ) and one source drive input terminal (e.g., SDP1, SDP2, SDPn in FIG10 ); a data signal terminal DA corresponding to a column of sub-pixels 2 is coupled to the corresponding source drive input terminal (e.g., SDP1, SDP2, SDPn in FIG10 ) via the corresponding data line (e.g., Da1, Da2, Dan in FIG10 ). A reset signal terminal RE corresponding to the sub-pixels 2 in the same column is coupled to the data line (e.g., Da1, Da2, Dan in FIG10 ) corresponding to the sub-pixels 2 in the same column.

[0113] The following describes the working process of the electronic paper display panel provided by the embodiment of the present disclosure by taking the electronic paper display panel shown in FIG. 10 as an example and combining it with the signal timing diagram shown in FIG. 11 .

[0114] As shown in Figure 11, stva represents the trigger signal loaded on the trigger signal line STVA, stvb represents the trigger signal loaded on the trigger signal line STVB, clk1 represents the clock signal loaded on the clock signal line CLK1, clk2 represents the clock signal loaded on the clock signal line CLK2, clk3 represents the clock signal loaded on the clock signal line CLK4, clk4 represents the clock signal loaded on the clock signal line CLK4, outa1 represents the scan drive signal loaded on the output signal terminal OUTA1, outa2 represents the scan drive signal loaded on the output signal terminal OUTA2, outa3 represents the scan drive signal loaded on the output signal terminal OUTA3, outb1 represents the scan drive signal loaded on the output signal terminal OUTB1, outb2 represents the scan drive signal loaded on the output signal terminal OUTB2, outb3 represents the scan drive signal loaded on the output signal terminal OUTB3, and sdp represents the signal loaded on the source drive input terminal, wherein Vda represents the voltage of the data signal, and Vre represents the voltage of the reset signal.

[0115] In the first phase, a reset signal is input to the sub-pixel 2 controlled by the multiple first shift registers (e.g., SR_A1, SR_A2, and SR_An in FIG10 ) in the gate drive circuit 30, thereby resetting the electronic paper display panel. Specifically, the first shift register SR_A1 among the multiple first shift registers applies a scan drive signal to the first first scan signal line Cs1 among the multiple first scan signal lines. The second shift register SR_A2 among the multiple first shift registers applies a scan drive signal to the second first scan signal line Cs1 among the multiple first scan signal lines. Finally, the nth shift register SR_An among the multiple first shift registers applies a scan drive signal to the nth first scan signal line Cs1 among the multiple first scan signal lines. When a high level appears in the scan drive signals outa1 to outan, the first control signal terminal CS1 coupled to the first scan signal line Cs1 can be controlled to apply a high level signal. The first transistor T1 is turned on under the control of the high level signal, and provides the reset signal from the reset signal terminal RE to the pixel electrode 3.

[0116] In the second phase, the sub-pixels 2 controlled by the plurality of second shift registers (e.g., SR_B1, SR_B2, and SR_Bn in FIG. 10 ) in the gate drive circuit 30 receive data signals, thereby driving the electronic paper display panel to display an image. Specifically, the first shift register SR_B1 in the plurality of second shift registers applies a scan drive signal to the first second scan signal line Cs2 in the plurality of second scan signal lines, the second shift register SR_B2 in the plurality of second shift registers applies a scan drive signal to the second second scan signal line Cs2 in the plurality of second scan signal lines, and the nth shift register SR_Bn in the plurality of second shift registers applies a scan drive signal to the nth second scan signal line Cs2 in the plurality of second scan signal lines. When a high level appears in the scan drive signals outb1 to outbn, the first second scan signal line Cs2 in the plurality of second scan signal lines can be controlled to apply a high level signal to the second control signal terminal CS2 coupled thereto. The second transistor T2 is turned on under the control of the high level signal, and provides the data signal from the data signal terminal DA to the pixel electrode 3.

[0117] The present disclosure provides further embodiments of electronic paper display panels, which are modifications of the embodiments described above. The following only describes the differences between this embodiment and the above embodiments, and the similarities are not repeated here.

[0118] In some other embodiments of the present disclosure, as shown in FIG12 , the present invention includes: a plurality of gating control circuits 40, a plurality of source driving input terminals (e.g., SDP1, SDP2, and SDPn in FIG12 ); a column of sub-pixels 2 corresponds to one gating control circuit 40 among the plurality of gating control circuits 40 and one source driving input terminal (e.g., SDP1, SDP2, and SDPn in FIG12 ); wherein the source driving input terminal (e.g., SDP1, SDP2, and SDPn in FIG12 ) is connected to the reset signal line (e.g., SDP1, SDP2, and SDPn in FIG12 ) of the corresponding column of sub-pixels 2 through the corresponding gating control circuit 40. As shown in Figure 12, Re1, Re2, Ren) and data lines (such as Da1, Da2, Dan in Figure 12) are coupled, the selection control circuit 40 is configured to provide the signal of the source drive input terminal (such as SDP1, SDP2, SDPn in Figure 12) to the corresponding reset signal line (such as Re1, Re2, Ren in Figure 12) in response to the signal of the first selection control terminal XC1, and to provide the signal of the source drive input terminal (such as SDP1, SDP2, SDPn in Figure 12) to the corresponding data line (such as Da1, Da2, Dan in Figure 12) in response to the signal of the second selection control terminal XC2.

[0119] In some other embodiments of the present disclosure, as shown in Figure 12, the selection control circuit 40 includes: a first selection control transistor M1 and a second selection control transistor M2; wherein, the gate of the first selection control transistor M1 is coupled to the first selection control terminal XC1, the first electrode of the first selection control transistor M1 is coupled to the reset signal line (for example, Re1, Re2, Ren in Figure 12), and the second electrode of the first selection control transistor M1 is coupled to the source drive input terminal (for example, SDP1, SDP2, SDPn in Figure 12); the gate of the second selection control transistor M2 is coupled to the second selection control terminal XC2, the first electrode of the second selection control transistor M2 is coupled to the data line (for example, Da1, Da2, Dan in Figure 5), and the second electrode of the second selection control transistor M2 is coupled to the source drive input terminal (for example, SDP1, SDP2, SDPn in Figure 12).

[0120] Exemplarily, the first gate control transistor M1 can be turned on under the control of the active level of the first gate control signal transmitted by the first gate control terminal XC1, and can be turned off under the control of the inactive level of the first gate control signal. Exemplarily, if the first gate control transistor M1 is configured as a P-type transistor, the active level of the first gate control signal is a low level, and the inactive level of the first gate control signal is a high level. Alternatively, if the first gate control transistor M1 is configured as an N-type transistor, the active level of the first gate control signal is a high level, and the inactive level of the first gate control signal is a low level.

[0121] Exemplarily, the second gate control transistor M2 can be turned on under the control of the active level of the second gate control signal transmitted by the second gate control signal terminal XC2, and can be turned off under the control of the inactive level of the second gate control signal. Exemplarily, if the second gate control transistor M2 is configured as a P-type transistor, the active level of the second gate control signal is a low level, and the inactive level of the second gate control signal is a high level. Alternatively, if the second gate control transistor M2 is configured as an N-type transistor, the active level of the second gate control signal is a high level, and the inactive level of the second gate control signal is a low level.

[0122] The following describes the working process of the electronic paper display panel provided by the embodiment of the present disclosure by taking the electronic paper display panel shown in FIG. 12 as an example and combining it with the signal timing diagram shown in FIG. 13 .

[0123] As shown in FIG13 , stva represents the trigger signal loaded on the trigger signal line STVA, stvb represents the trigger signal loaded on the trigger signal line STVB, clk1 represents the clock signal loaded on the clock signal line CLK1, clk2 represents the clock signal loaded on the clock signal line CLK2, clk3 represents the clock signal loaded on the clock signal line CLK4, clk4 represents the clock signal loaded on the clock signal line CLK4, outa1 represents the scan drive signal loaded on the output signal terminal OUTA1, outa2 represents the scan drive signal loaded on the output signal terminal OUTA2, and outa 3 represents the scan drive signal loaded on the output signal terminal OUTA3, outb1 represents the scan drive signal loaded on the output signal terminal OUTB1, outb2 represents the scan drive signal loaded on the output signal terminal OUTB2, outb3 represents the scan drive signal loaded on the output signal terminal OUTB3, sdp represents the signal loaded on the source drive input terminal, wherein Vda represents the voltage of the data signal, Vre represents the voltage of the reset signal, xc1 represents the first selection control signal loaded on the first selection control terminal XC1, and xc2 represents the second selection control signal loaded on the second selection control terminal XC2.

[0124] In the first stage, a reset signal is input to the sub-pixel 2 controlled by the plurality of first shift registers (e.g., SR_A1, SR_A2, and SR_An in FIG12 ) in the gate drive circuit 30, thereby resetting the electronic paper display panel. Specifically, the first shift register SR_A1 among the plurality of first shift registers applies a scan drive signal to the first first scan signal line Cs1 among the plurality of first scan signal lines, the second shift register SR_A2 among the plurality of first shift registers applies a scan drive signal to the second first scan signal line Cs1 among the plurality of first scan signal lines, and the nth shift register SR_An among the plurality of first shift registers applies a scan drive signal to the nth first scan signal line Cs1 among the plurality of first scan signal lines. When a high level appears in the scan drive signals outa1 to outan, the first control signal terminal CS1 coupled to the first scan signal line Cs1 can be controlled to apply a high level signal. The first selection control transistor M1 is turned on under the control of a high-level signal, and provides the signal of the source driving input terminal (for example, SDP1, SDP2, SDPn in FIG12 ) to the corresponding reset signal line (for example, Re1, Re2, Ren in FIG12 ). The first transistor T1 is turned on under the control of a high-level signal, and provides the reset signal of the reset signal terminal RE to the pixel electrode 3.

[0125] In the second stage, the sub-pixels 2 controlled by the plurality of second shift registers (e.g., SR_B1, SR_B2, and SR_Bn in FIG. 12 ) in the gate drive circuit 30 input data signals, thereby driving the electronic paper display panel to display an image. Specifically, the first shift register SR_B1 among the plurality of second shift registers loads a scan drive signal to the first second scan signal line Cs2 among the plurality of second scan signal lines, the second shift register SR_B2 among the plurality of second shift registers loads a scan drive signal to the second second scan signal line Cs2 among the plurality of second scan signal lines… The nth shift register SR_Bn among the plurality of second shift registers loads a scan drive signal to the nth second scan signal line Cs2 among the plurality of second scan signal lines. When a high level appears in the scan drive signals outb1 to outbn, the second control signal terminal CS2 coupled to the second scan signal line Cs2 can be controlled to load a high level signal. The second selection control transistor M2 is turned on under the control of a high-level signal, and provides the signal of the source drive input terminal (for example, SDP1, SDP2, SDPn in FIG12) to the corresponding data line (for example, Da1, Da2, Dan in FIG12). The second transistor T2 is turned on under the control of a high-level signal, and provides the data signal of the data signal terminal DA to the pixel electrode 3.

[0126] The present disclosure provides further embodiments of electronic paper display panels, which are modifications of the embodiments described above. The following only describes the differences between this embodiment and the above embodiments, and the similarities are not repeated here.

[0127] In some other embodiments of the present disclosure, as shown in Figure 14, the multiple shift registers include: multiple third shift registers (for example, SR_C1, SR_C2, SR_Cn in Figure 14); wherein, one third shift register (for example, SR_C1, SR_C2, SR_Cn in Figure 14) among the multiple third shift registers (for example, SR_C1, SR_C2, SR_Cn in Figure 14) is coupled to a first scanning signal line Cs1 among the multiple first scanning signal lines Cs1; the first scanning signal line Cs1 corresponding to the sub-pixel 2 in the mth row is coupled to the second scanning signal line Cs2 corresponding to the sub-pixel 2 in the nth row, m is greater than n; m and n are both positive integers. For example, the first scanning signal line Cs1 corresponding to the sub-pixel 2 in the third row is coupled to the second scanning signal line Cs2 corresponding to the sub-pixel 2 in the first row, the first scanning signal line Cs1 corresponding to the sub-pixel 2 in the mth row is coupled to the second scanning signal line Cs2 corresponding to the sub-pixel 2 in the nth row, the first scanning signal line Cs1 corresponding to the sub-pixel 2 in the fourth row is coupled to the second scanning signal line Cs2 corresponding to the sub-pixel 2 in the second row, the first scanning signal line Cs1 corresponding to the sub-pixel 2 in the fifth row is coupled to the second scanning signal line Cs2 corresponding to the sub-pixel 2 in the third row… The connection method of the remaining scanning signal lines can be inferred accordingly and will not be elaborated here.

[0128] The following describes the working process of the electronic paper display panel provided by the embodiment of the present disclosure by taking the electronic paper display panel shown in FIG. 14 as an example and combining it with the signal timing diagram shown in FIG. 15 .

[0129] As shown in Figure 15, stvc represents the trigger signal loaded on the trigger signal line STVC, clk1 represents the clock signal loaded on the clock signal line CLK1, clk2 represents the clock signal loaded on the clock signal line CLK2, outc1 represents the scan drive signal loaded on the output signal terminal OUTC1, outc2 represents the scan drive signal loaded on the output signal terminal OUTC2, outcn-1 represents the scan drive signal loaded on the output signal terminal OUTCn-1, and outcn represents the scan drive signal loaded on the output signal terminal OUTCn.

[0130] In the first phase, a plurality of third shift registers (e.g., SR_C1, SR_C2, and SR_Cn in FIG. 14 ) in the gate drive circuit 30 control the sub-pixels 2 to input reset signals, thereby resetting the electronic paper display panel. Specifically, the first shift register SR_C1 in the plurality of third shift registers applies a scan drive signal to the first first scan signal line Cs1 in the plurality of first scan signal lines. The second shift register SR_C2 in the plurality of third shift registers applies a scan drive signal to the second first scan signal line Cs1 in the plurality of first scan signal lines. Finally, the nth shift register SR_Cn in the plurality of third shift registers applies a scan drive signal to the nth first scan signal line Cs1 in the plurality of first scan signal lines. When a high level appears in any of the scan drive signals outc1 to outcn, the first control signal terminal CS1 coupled to the first scan signal line Cs1 can be controlled to apply a high level signal. The first transistor T1 is turned on under the control of the high level signal, and provides the reset signal from the reset signal terminal RE to the pixel electrode 3.

[0131] In the second stage, the sub-pixels 2 controlled by the plurality of third shift registers (eg, SR_C1 , SR_C2 , and SR_Cn in FIG. 14 ) in the gate driving circuit 30 input data signals, thereby driving the electronic paper display panel to display images. Specifically, a third shift register SR_C3 among the plurality of third shift registers applies a scan drive signal to a first second scan signal line Cs2 among the plurality of second scan signal lines, a fourth shift register SR_C4 among the plurality of third shift registers applies a scan drive signal to a second second scan signal line Cs2 among the plurality of second scan signal lines, a fifth shift register SR_C5 among the plurality of third shift registers applies a scan drive signal to a third second scan signal line Cs2 among the plurality of second scan signal lines, ... and an nth shift register SR_Cn among the plurality of third shift registers applies a scan drive signal to an n-2th second scan signal line Cs2 among the plurality of second scan signal lines. When a high level appears in any of the scan drive signals outc1 to outcn, the second control signal terminal CS2 coupled to the second scan signal line Cs2 can be controlled to apply a high level signal. The second transistor T2 is turned on under the control of the high level signal and provides the data signal at the data signal terminal DA to the pixel electrode 3.

[0132] Based on the same disclosed concept, embodiments of the present disclosure further provide a display device comprising the aforementioned electronic paper display panel provided in embodiments of the present disclosure. The principles underlying the problems solved by this display device are similar to those of the aforementioned electronic paper display panel. Therefore, the implementation of this display device can refer to the implementation of the aforementioned electronic paper display panel, and any repetitions will not be repeated here.

[0133] In specific implementations, in the embodiments of the present disclosure, the display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigation system, or the like. Other essential components of the display device are well understood by those skilled in the art and are not detailed here, nor should they be construed as limitations of the present disclosure.

[0134] Although the preferred embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present disclosure.

[0135] Obviously, those skilled in the art may make various changes and modifications to the embodiments of the present disclosure without departing from the spirit and scope of the embodiments of the present disclosure. Thus, if such changes and modifications of the embodiments of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is intended to include such changes and modifications.

Claims

1. An electronic paper display panel, comprising: A plurality of sub-pixels, each of the plurality of sub-pixels comprises: a first conduction circuit, a second conduction circuit, and a pixel electrode; wherein the first conduction circuit and the second conduction circuit in the same sub-pixel are both coupled to the pixel electrode; the first conduction circuit is configured to respond to a signal at a first control signal terminal and provide a reset signal at a reset signal terminal to the pixel electrode; the second conduction circuit is configured to respond to a signal at a second control signal terminal and provide a data signal at a data signal terminal to the pixel electrode; wherein the first conduction circuit and the second conduction circuit in the same sub-pixel work in time-sharing manner; The gate driving circuit includes a plurality of shift registers, and a first control signal terminal corresponding to the first conduction circuit and a second control signal terminal corresponding to the second conduction circuit in the same sub-pixel are connected to different shift registers.

2. The electronic paper display panel according to claim 1, wherein: The first conduction circuit includes: a first transistor; a gate of the first transistor is coupled to the first control signal terminal, a first electrode of the first transistor is coupled to the reset signal terminal, and a second electrode of the first transistor is coupled to the pixel electrode.

3. The electronic paper display panel according to claim 1, wherein: The second conduction circuit includes: a second transistor; a gate of the second transistor and the second control signal terminal, a first electrode of the second transistor and the data signal terminal are coupled, and a second electrode of the second transistor and the pixel electrode are coupled.

4. The electronic paper display panel according to any one of claims 1 to 3, wherein: Also includes: A plurality of first scanning signal lines and a plurality of second scanning signal lines; The first control signal terminals corresponding to a row of the sub-pixels are all coupled to a first scanning signal line among the plurality of first scanning signal lines; The second control signal terminals corresponding to a row of the sub-pixels are all coupled to a second scanning signal line among the plurality of second scanning signal lines.

5. The electronic paper display panel according to claim 4, wherein: The plurality of shift registers include: a plurality of first shift registers and a plurality of second shift registers; A first shift register among the plurality of first shift registers is coupled to a first scan signal line among the plurality of first scan signal lines; One second shift register among the plurality of second shift registers is coupled to one second scan signal line among the plurality of second scan signal lines.

6. The electronic paper display panel according to claim 4, wherein: The plurality of shift registers include: a plurality of third shift registers; A third shift register among the plurality of third shift registers is coupled to a first scan signal line among the plurality of first scan signal lines; The first scanning signal line corresponding to the sub-pixels in the mth row is coupled to the second scanning signal line corresponding to the sub-pixels in the nth row, where m is greater than n; and both m and n are positive integers.

7. The electronic paper display panel according to any one of claims 1 to 3, wherein: Also includes: Multiple reset signal lines and multiple data lines; A reset signal terminal corresponding to a column of the sub-pixels is coupled to a reset signal line among the plurality of reset signal lines; The data signal terminals corresponding to a column of the sub-pixels are coupled to a data line among the plurality of data lines.

8. The electronic paper display panel according to claim 7, wherein: It also includes: a plurality of gating control circuits and a plurality of source driving input terminals; a column of the sub-pixels corresponds to one gating control circuit in the plurality of gating control circuits and one source driving input terminal in the plurality of source driving input terminals; The source drive input terminal is coupled to the reset signal line and the data line of the corresponding column sub-pixel through the corresponding selection control circuit, and the selection control circuit is configured to provide the signal of the source drive input terminal to the corresponding reset signal line in response to the signal of the first selection control terminal, and to provide the signal of the source drive input terminal to the corresponding data line in response to the signal of the second selection control terminal.

9. The electronic paper display panel according to claim 8, wherein: The gating control circuit comprises: a first gating control transistor and a second gating control transistor; The gate of the first gating control transistor is coupled to the first gating control terminal, the first electrode of the first gating control transistor is coupled to the reset signal line, and the second electrode of the first gating control transistor is coupled to the source driving input terminal; The gate of the second gate control transistor is coupled to the second gate control terminal, the first electrode of the second gate control transistor is coupled to the data line, and the second electrode of the second gate control transistor is coupled to the source drive input terminal.

10. The electronic paper display panel according to claim 7, wherein: The plurality of reset signal lines are coupled to each other.

11. The electronic paper display panel according to any one of claims 1 to 3, wherein: Also includes: A plurality of data lines and a plurality of source driving input terminals; a column of the sub-pixels corresponds to one data line among the plurality of data lines and one source driving input terminal among the plurality of source driving input terminals; The data signal terminal corresponding to a column of the sub-pixels is coupled to the corresponding source driving input terminal through the corresponding data line.

12. The electronic paper display panel according to any one of claims 1 to 11, further comprising: a first substrate base plate; The plurality of sub-pixels are located on one side of the first substrate; Each of the plurality of sub-pixels further comprises: A common electrode, located at a side of the pixel electrode away from the first substrate; an electrophoretic liquid layer, located between the pixel electrode and the common electrode, and comprising a plurality of charged particles; Wherein, the pixel electrode is configured to drive the plurality of charged particles to adjust the grayscale display.

13. A display device, wherein: Comprising the electronic paper display panel as described in any one of claims 1-12.

14. A method for driving an electronic paper display panel according to any one of claims 1 to 12, comprising: In the first stage, the first conduction circuit provides a reset signal from the reset signal terminal to the pixel electrode in response to a signal from the first control signal terminal; In the second stage, the second conduction circuit provides the data signal at the data signal terminal to the pixel electrode in response to the signal at the second control signal terminal; The first conducting circuit and the second conducting circuit in the same sub-pixel work in time-sharing manner.

15. The driving method of the electronic paper display panel according to claim 14, wherein: The reset signal input to the pixel electrode in the same sub-pixel has a potential opposite to that of the data signal.

16. The driving method of the electronic paper display panel according to claim 14, wherein: The potential of the reset signal input to the pixel electrode in each of the sub-pixels is a fixed potential.

Images