Array substrate, display panel, and display device

Abstract

An array substrate, comprising a substrate, a plurality of pixel driving circuits, and a plurality of first scanning signal lines. The plurality of pixel driving circuits are located on one side of the substrate and are arranged in a plurality of rows and a plurality of columns. One pixel driving circuit comprises a compensation transistor, a driving transistor, and a first conductive connecting portion, wherein a control electrode of the driving transistor and a second electrode of the compensation transistor are both electrically connected to the first conductive connecting portion. The plurality of first scanning signal lines are located on one side of the substrate. The plurality of first scanning signal lines all extend in a row direction and are sequentially arranged in a column direction. The row direction and the column direction are both parallel to the substrate and are arranged crosswise. One first scanning signal line is electrically connected to control electrodes of compensation transistors of a row of pixel driving circuits. The first conductive connecting portions and the first scanning signal lines do not overlap in a direction perpendicular to the substrate.

Description

Array substrate, display panel and display device

[0001] This application claims priority to Chinese patent application No. 202310621415.X filed on May 29, 2023, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present disclosure relates to the field of display technology, and in particular to an array substrate, a display panel, and a display device. Background Art

[0003] At present, OLED (Organic Light-Emitting Diode) display devices are widely used due to their self-luminescence, fast response, wide viewing angle and ability to be manufactured on flexible substrates. OLED display devices include multiple sub-pixels, each of which includes a pixel driving circuit and a light-emitting device. The pixel driving circuit drives the light-emitting device to emit light, thereby achieving display.

[0004] Summary of the Invention

[0005] On the one hand, an array substrate is provided. The array substrate includes a substrate, a plurality of pixel driving circuits, and a plurality of first scanning signal lines. The plurality of pixel driving circuits are located on one side of the substrate and are arranged in multiple rows and columns. A pixel driving circuit includes a compensation transistor, a driving transistor, and a first conductive connection portion, wherein the control electrode of the driving transistor and the second electrode of the compensation transistor are both electrically connected to the first conductive connection portion. A plurality of first scanning signal lines are located on one side of the substrate, and the plurality of first scanning signal lines extend along the row direction and are arranged in sequence along the column direction. The row direction and the column direction are both parallel to the substrate and are arranged crosswise; a first scanning signal line is electrically connected to the control electrode of the compensation transistor of a row of pixel driving circuits. The first conductive connection portion and the first scanning signal line do not overlap in a direction perpendicular to the substrate.

[0006] In some embodiments, the pixel driving circuit further comprises: a data writing transistor and a first light-emitting control transistor, wherein the second electrode of the data writing transistor is electrically connected to the first electrode of the driving transistor and the second electrode of the first light-emitting control transistor. The array substrate further comprises: a plurality of second scanning signal lines and a plurality of light-emitting control signal lines, located on one side of the substrate; the plurality of second scanning signal lines all extend in the row direction and are sequentially arranged in the column direction, and one second scanning signal line is electrically connected to the control electrode of the data writing transistor of a row of pixel driving circuits; the plurality of light-emitting control signal lines all extend in the row direction and are sequentially arranged in the column direction, and one light-emitting control signal line is electrically connected to the control electrode of the first light-emitting control transistor of a row of pixel driving circuits. The array substrate further comprises: a plurality of row pixel regions, the plurality of row pixel regions extend in the row direction and are sequentially arranged in the column direction; a row of pixel driving circuits is disposed in a row pixel region, and the first scanning signal line, second scanning signal line, and light-emitting control signal line electrically connected to the row pixel driving circuit are located in the row pixel region where the row pixel driving circuit is located. Among them, in a row of pixel areas: the orthographic projection of the first scanning signal on the substrate is located on the side of the orthographic projection of the second scanning signal line on the substrate away from the orthographic projection of the light-emitting control signal line on the substrate, and the orthographic projection of the driving transistor on the substrate is located between the orthographic projection of the second scanning signal line on the substrate and the orthographic projection of the light-emitting control signal line on the substrate.

[0007] In some embodiments, within a row of pixel areas, the compensation transistor and the first conductive connection portion are arranged sequentially along the column direction; wherein, the compensation transistor passes through the first scanning signal line, and the positive projection of the second electrode of the compensation transistor on the substrate is located on a side of the positive projection of the first scanning signal line on the substrate close to the positive projection of the light-emitting control signal line on the substrate, and the first conductive connection portion is located on a side of the first scanning signal line close to the light-emitting control signal line.

[0008] In some embodiments, within a row of pixel regions, a portion of the positive projection of the data write transistor on the substrate is arranged opposite to the positive projection of the compensation transistor on the substrate in the row direction, and another portion of the positive projection of the data write transistor on the substrate is arranged opposite to the positive projection of the first conductive connection portion on the substrate in the row direction.

[0009] In some embodiments, the data write transistor passes through the second scan signal line, and the data write transistor is located on the side of the first scan signal line close to the light-emitting control signal line. The array substrate also includes: a plurality of data transfer parts, and the plurality of data transfer parts are located on the side of the plurality of pixel driving circuits away from the substrate. The array substrate also includes: a plurality of data lines, and the plurality of data lines are located on the side of the plurality of data transfer parts away from the substrate. The plurality of data lines all extend in the column direction and are arranged in sequence along the row direction. One data line is electrically connected to the first electrode of the data write transistor of a row of pixel driving circuits through one data transfer part. Wherein, in a row pixel area, the orthographic projection of the data transfer part on the substrate is located between the orthographic projection of the first scan signal line on the substrate and the orthographic projection of the second scan signal line on the substrate.

[0010] In some embodiments, within a row of pixel regions, a portion of the orthographic projection of the first conductive connection portion on the substrate overlaps with a portion of the orthographic projection of the compensation transistor on the substrate, and another portion of the orthographic projection of the first conductive connection portion on the substrate overlaps with a portion of the orthographic projection of the driving transistor on the substrate.

[0011] In some embodiments, the pixel driving circuit further includes a second conductive connection portion electrically connected to the first electrode of the driving transistor, the second electrode of the first light emission control transistor, and the second electrode of the data writing transistor. An orthographic projection of the second conductive connection portion on the substrate does not overlap with an orthographic projection of the first scanning signal line on the substrate.

[0012] In some embodiments, the pixel driving circuit further comprises: a third reset transistor, wherein the second electrode of the third reset transistor is electrically connected to the second conductive connection portion. The array substrate further comprises: a plurality of second reset signal lines, the plurality of second reset signal lines being located on a side of the plurality of pixel driving circuits away from the substrate, the plurality of second reset signal lines extending in the row direction and arranged sequentially in the column direction; one second reset signal line being electrically connected to the control electrode of the third reset transistor of a row of pixel driving circuits; the second reset signal line electrically connected to a row of pixel driving circuits being located within the row pixel region where the row of pixel driving circuits is located. Specifically, within a row pixel region: the second reset signal line is located on a side of the light emitting control signal line away from the first scanning signal line.

[0013] In some embodiments, the array substrate further includes: a plurality of third initialization signal lines, the plurality of third initialization signal lines being located on one side of the substrate; the plurality of third initialization signal lines extending in a row direction and arranged sequentially in a column direction, one third initialization signal line being electrically connected to a first electrode of a third reset transistor in a row of pixel driving circuits; and within a row of pixel regions, an orthographic projection of the third initialization signal line on the substrate at least partially overlaps with an orthographic projection of the light emission control signal line on the substrate.

[0014] In some embodiments, within a row of pixels, a third reset transistor passes through a second reset signal line and is located on a side of the third initialization signal line away from a light emission control signal line; an orthographic projection of a first electrode of the third reset transistor on the substrate is located between an orthographic projection of the third initialization signal line and an orthographic projection of the second reset signal line on the substrate, and an orthographic projection of a second electrode of the third reset transistor on the substrate is located on a side of the orthographic projection of the second reset signal line on the substrate away from an orthographic projection of the third initialization signal line on the substrate. A second conductive connection crosses the third initialization signal line, the light emission control signal line, and the second reset signal line and is electrically connected to the second electrode of the third reset transistor.

[0015] In some embodiments, a portion of an orthographic projection of the second conductive connection portion on the substrate overlaps with an orthographic projection of the second electrode, the control electrode, and a portion of the first electrode of the third reset transistor on the substrate.

[0016] In some embodiments, the pixel driving circuit further comprises a second light-emitting control transistor and a second reset transistor; the first electrode of the second light-emitting control transistor is electrically connected to the second electrode of the driving transistor and the first electrode of the compensation transistor, and the second electrode of the second light-emitting control transistor is electrically connected to the light-emitting device and the second electrode of the second reset transistor; wherein the control electrode of the second light-emitting control transistor of a row of pixel driving circuits is electrically connected to a light-emitting control signal line, and the control electrode of the second reset transistor of a row of pixel driving circuits is electrically connected to a second reset signal line. The array substrate further comprises: a plurality of second initialization signal lines, the plurality of second initialization signal lines being located on a side of the plurality of pixel driving circuits away from the substrate, the plurality of second initialization signal lines extending in the row direction and arranged sequentially in the column direction; a second initialization signal line being electrically connected to the first electrode of the second reset transistor of a row of pixel driving circuits. wherein, within a row of pixel regions: the orthogonal projection of the second initialization signal line on the substrate is located on a side of the orthogonal projection of the second reset signal line on the substrate away from the orthogonal projection of the first scanning signal line on the substrate.

[0017] In some embodiments, the pixel driving circuit further includes: a first reset transistor and a third conductive connection portion, the third conductive connection portion being electrically connected to the second electrode of the first reset transistor, the second electrode of the driving transistor, and the first electrode of the compensation transistor. The array substrate further includes: a plurality of first reset signal lines, the plurality of first reset signal lines being located on a side of the plurality of pixel driving circuits away from the substrate; the plurality of first reset signal lines extending in a row direction and arranged sequentially in a column direction, one first reset signal line being electrically connected to the control electrode of the first reset transistor of a row of pixel driving circuits. Within the row pixel region, the orthogonal projection of the first reset signal line on the substrate is located on a side of the orthogonal projection of the light emitting control signal line on the substrate away from the orthogonal projection of the first scanning signal line on the substrate.

[0018] In some embodiments, the array substrate further comprises: a plurality of first initialization signal lines, the plurality of first initialization signal lines being located on a side of the plurality of pixel driving circuits away from the substrate, the plurality of first initialization signal lines extending in a row direction and being sequentially arranged in a column direction, one first initialization signal line being electrically connected to a first electrode of a first reset transistor in a row of pixel driving circuits. Within the row pixel region, the first initialization signal line is located on a side of the first reset signal line away from the first scan signal line.

[0019] In some embodiments, the first reset transistor passes through the first reset signal line, the orthographic projection of the first electrode of the first reset transistor on the substrate is located between the orthographic projection of the first reset signal line on the substrate and the orthographic projection of the first initialization signal line on the substrate, and the orthographic projection of the second electrode of the first reset transistor on the substrate is located between the orthographic projection of the first reset signal line on the substrate and the orthographic projection of the second reset signal line on the substrate.

[0020] In some embodiments, an orthographic projection of the first reset signal line on the substrate overlaps with an orthographic projection of the second initialization signal line on the substrate.

[0021] In some embodiments, the array substrate further includes: a plurality of auxiliary signal lines, the plurality of auxiliary signal lines being located on one side of the substrate, the plurality of auxiliary signal lines extending in a column direction and arranged sequentially in a row direction, wherein one auxiliary signal line is electrically connected to any one of the first initialization signal line, the second initialization signal line, and the third initialization signal line.

[0022] In some embodiments, a row of pixel driving circuits is divided into a plurality of repeating units sequentially arranged along the row direction, each repeating unit includes at least one pixel driving circuit, and the auxiliary signal line is located between two adjacent repeating units in the row direction.

[0023] In some embodiments, the repeating unit includes two pixel driving circuits, and the two pixel driving circuits in one repeating unit are symmetrically arranged in a row direction.

[0024] In some embodiments, the multiple auxiliary signal lines include a first auxiliary signal line, a second auxiliary signal line and a third auxiliary signal line, the first auxiliary signal line is electrically connected to the first initialization signal line, the second auxiliary signal line is electrically connected to the second initialization signal line, and the third auxiliary signal line is electrically connected to the third initialization signal line.

[0025] In some embodiments, the array substrate further includes: a light shielding layer located between the substrate and the pixel driving circuit, wherein the orthographic projection of the light shielding layer on the substrate covers the orthographic projection of the driving transistor on the substrate.

[0026] In some embodiments, the light shielding layer includes a plurality of light shielding portions and a plurality of connecting portions, wherein the orthographic projections of the light shielding portions on the substrate overlap the orthographic projections of the driving transistors on the substrate. Two adjacent light shielding portions in the row direction are connected by a connecting portion; and / or two adjacent light shielding portions in the column direction are connected by a connecting portion. The light shielding layer is configured to receive a first voltage signal.

[0027] In another aspect, a display panel is provided. The display panel comprises: an array substrate according to any of the above embodiments, a light-emitting device layer, and an encapsulation layer. The light-emitting device layer is located on a side of the array substrate away from the substrate; and the encapsulation layer is located on a side of the light-emitting device layer away from the array substrate.

[0028] In another aspect, a display device is provided, comprising: a display panel according to any of the above embodiments and a driver chip, wherein the driver chip is electrically connected to the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] To more clearly illustrate the technical solutions of the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below are schematic diagrams and do not limit the actual dimensions of the products, actual processes of the methods, actual timing of signals, etc. involved in the embodiments of the present disclosure.

[0030] FIG1 is a structural diagram of a display device according to some embodiments;

[0031] FIG2 is a structural diagram of a display panel according to some embodiments;

[0032] FIG3 is a structural diagram of a display panel according to some embodiments;

[0033] FIG4 is a structural diagram of a display panel according to some embodiments;

[0034] FIG5 is an equivalent circuit diagram of an “8T1C” pixel driving circuit according to some embodiments;

[0035] FIG6 is a timing diagram of an “8T1C” pixel driving circuit according to some embodiments;

[0036] FIG7 is a schematic diagram of an “8T1C” pixel driving circuit in a first phase t1 according to some embodiments;

[0037] FIG8 is a schematic diagram of an “8T1C” pixel driving circuit in a second phase t2 according to some embodiments;

[0038] FIG9 is a schematic diagram of an “8T1C” pixel driving circuit in a third phase t3 according to some embodiments;

[0039] FIG10 is a schematic diagram of an “8T1C” pixel driving circuit in a fourth stage t4 according to some embodiments;

[0040] Figure 11 is a measured timing diagram of the "8T1C" pixel driving circuit;

[0041] FIG12 is a structural diagram of an array substrate according to some embodiments;

[0042] FIG13 is a diagram showing a film layer structure of an array substrate according to some embodiments;

[0043] FIG14A is a diagram illustrating another film layer structure of an array substrate according to some embodiments;

[0044] FIG14B is another film layer structure diagram of an array substrate according to some embodiments;

[0045] FIG15 is another schematic structural diagram of an array substrate according to some embodiments;

[0046] FIG16 is a structural diagram of an array substrate according to some embodiments;

[0047] FIG17 is a structural diagram of a first active film layer of an array substrate according to some embodiments;

[0048] FIG18A is a structural diagram of a first active film layer of an array substrate according to some embodiments;

[0049] FIG18B is a diagram showing the stacking of film layers of an array substrate based on the first active film layer in FIG18A ;

[0050] FIG19 is a structural diagram of a first gate metal layer of an array substrate according to some embodiments;

[0051] FIG20 is a structural diagram of a stacked arrangement of a first active film layer and a first gate metal layer according to some embodiments;

[0052] FIG21 is a structural diagram of a second gate metal layer of an array substrate according to some embodiments;

[0053] FIG22 is a structural diagram of a stacked arrangement of a first active film layer, a first gate metal layer, and a second gate metal layer according to some embodiments;

[0054] FIG23 is a structural diagram of a second active film layer of an array substrate according to some embodiments;

[0055] FIG24 is a structural diagram of a stacked arrangement of a first active film layer, a first gate metal layer, a second gate metal layer, and a second active film layer according to some embodiments;

[0056] FIG25 is a structural diagram of a third gate metal layer of an array substrate according to some embodiments;

[0057] FIG26 is a structural diagram of a stacked arrangement of a first active film layer, a first gate metal layer, a second gate metal layer, a second active film layer, and a third gate metal layer according to some embodiments;

[0058] FIG27 is a structural diagram of an insulating layer of an array substrate according to some embodiments;

[0059] FIG28 is a structural diagram of a stacked arrangement of a first active film layer, a first gate metal layer, a second gate metal layer, a second active film layer, a third gate metal layer, and an insulating layer according to some embodiments;

[0060] FIG29 is a structural diagram of a first source / drain metal layer of an array substrate according to some embodiments;

[0061] 30 is a structural diagram of a stacked arrangement of a first active film layer, a first gate metal layer, a second gate metal layer, a second active film layer, a third gate metal layer, an insulating layer, and a first source / drain metal layer according to some embodiments;

[0062] FIG31 is a structural diagram of a second source / drain metal layer of an array substrate according to some embodiments;

[0063] Figure 32 is a structural diagram of a stacked arrangement of a first active film layer, a first gate metal layer, a second gate metal layer, a second active film layer, a third gate metal layer, an insulating layer, a first source-drain metal layer, and a second source-drain metal layer according to some embodiments. DETAILED DESCRIPTION

[0064] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0065] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and its other forms, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open and inclusive, that is, "including, but not limited to". In the description of the specification, the terms "some embodiments", "example" or "some examples" and the like are intended to indicate that the particular features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the particular features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0066] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0067] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. The term "connected" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium. The term "coupled" indicates, for example, that two or more components are in direct physical or electrical contact. The term "coupled" or "communicatively coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0068] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0069] As used herein, "about" or "approximately" includes the stated value and the average value that is within an acceptable range of deviation from the particular value, where the acceptable range of deviation is determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0070] As used herein, "parallel" and "perpendicular" include the conditions described and conditions similar to the conditions described, and the range of the similar conditions is within an acceptable deviation range, wherein the acceptable deviation range is determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range for approximate parallelism can be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range for approximate perpendicularity can also be, for example, a deviation within 5°.

[0071] It will be understood that when a layer or element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present therebetween.

[0072] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0073] Some embodiments of the present disclosure provide a display device.

[0074] FIG. 1 is a structural diagram of a display device according to some embodiments.

[0075] Referring to FIG. 1 , a display device 100 is a product capable of displaying images (including static or dynamic images, where dynamic images may be videos). For example, the display device 100 may be any of the following: a monitor, a television, a billboard, a digital photo frame, a laser printer with a display function, a telephone, a mobile phone, a personal digital assistant (PDA), a digital camera, a camcorder, a viewfinder, a navigation system, a vehicle, a large-area wall, a home appliance, an information query device (such as a service query device for e-government, banks, hospitals, power departments, etc.), a monitor, and the like.

[0076] The display device 100 includes a display panel 200 and a driver chip, wherein the driver chip is electrically connected to the display panel 200 and can provide the display panel 200 with data signals required for the display panel 200 to emit light.

[0077] FIG. 2 is a structural diagram of a display panel 200 according to some embodiments.

[0078] 2 , the display panel 200 may include a display area AA and a peripheral area BB located at least on one side of the display area AA. The peripheral area BB may surround the display area AA.

[0079] The display panel 200 may include a plurality of sub-pixels 210 , and the plurality of sub-pixels 210 are disposed in the display area AA, wherein the plurality of sub-pixels may be arranged in an array.

[0080] Sub-pixel 210 is the smallest unit for displaying images on the display panel 200. Multiple sub-pixels 210 may include red sub-pixels, blue sub-pixels, and green sub-pixels. By adjusting the brightness (grayscale) of sub-pixels of different colors, multiple colors can be displayed through color combination and superposition, thereby realizing full-color display of the display panel 200.

[0081] In some other examples, the display panel 200 may further include white sub-pixels.

[0082] FIG. 3 is a structural diagram of a display panel 200 according to some embodiments.

[0083] Referring to FIG. 3 , each sub-pixel 210 may include a light-emitting device 212 and a pixel driving circuit 211 for driving the light-emitting device 212 to emit light.

[0084] In addition, the display panel 200 may further include a plurality of signal lines. For example, the signal lines may include a data line Dt, a first power signal line Vdd, a first scan signal line GN, a second scan signal line GP, a light-emitting control signal line Em, a first reset signal line Rst-P, a second reset signal line Rst-H, a first initialization signal line (not shown), a second initialization signal line, and a third initialization signal line. The plurality of signal lines may be electrically connected to the pixel driving circuit 211 to provide the pixel driving circuit 211 with the signals it needs.

[0085] FIG. 4 is a structural diagram of a display panel 200 according to some embodiments.

[0086] 4 , the display panel 200 includes an array substrate 300 , a light emitting device layer 400 , and an encapsulation layer 500 , which are stacked in sequence.

[0087] The array substrate 300 includes a plurality of pixel driving circuits 211 (as shown in FIG3 ), and the light emitting device layer 400 includes a plurality of light emitting devices 212 (as shown in FIG3 ).

[0088] The light emitting device layer 400 includes an anode layer, a light emitting layer, and a cathode layer stacked in sequence. In some examples, an electron transport layer is further disposed between the cathode layer and the light emitting layer, and a hole transport layer is further disposed between the anode layer and the light emitting layer.

[0089] The encapsulation layer 500 can cover the multiple light-emitting devices 212 in the light-emitting device layer 400 and encapsulate the light-emitting devices 212 to prevent moisture and oxygen in the external environment from entering the display panel 200 and damaging the organic materials in the light-emitting devices 212, thereby shortening the life of the display panel 200.

[0090] In some embodiments, the pixel driving circuit 211 includes a plurality of transistors. In some embodiments, the structure of the pixel driving circuit 211 in the present disclosure includes multiple structures, which can be selected according to actual needs. For example, the structure of the pixel driving circuit may include "2T1C", "6T1C", "7T1C", "6T2C", "7T2C" or "8T1C", etc. Here, "T" represents a thin film transistor, and the number in front of "T" represents the number of thin film transistors; "C" represents a storage capacitor C, and the number in front of "C" represents the number of storage capacitors C. The following is an introduction taking the "8T1C" pixel driving circuit as an example.

[0091] FIG. 5 is an equivalent circuit diagram of an “8T1C” pixel driving circuit 211 according to some embodiments.

[0092] 5 , the pixel driving circuit 211 includes a first reset transistor T1 , a compensation transistor T2 , a driving transistor T3 , a data writing transistor T4 , a first emission control transistor T5 , a second emission control transistor T6 , a second reset transistor T7 , a third reset transistor T8 and a capacitor Cst.

[0093] The gate g1 of the first reset transistor T1 is electrically connected to the first reset signal line Rst-P, the first electrode s1 of the first reset transistor T1 is electrically connected to the first initialization signal line Vt1, and the second electrode d1 of the first reset transistor T1 is electrically connected to the third node N3.

[0094] A gate g2 of the compensation transistor T2 is electrically connected to the first scan signal line GN, a first electrode s2 of the compensation transistor T2 is electrically connected to the third node N3, and a second electrode d2 of the compensation transistor T2 is electrically connected to the first node N1.

[0095] A gate g3 of the driving transistor T3 is electrically connected to the first scanning signal line GN, a first electrode s3 of the driving transistor T3 is electrically connected to the second node N2, and a second electrode d3 of the driving transistor T3 is electrically connected to the third node N3.

[0096] A gate g4 of the data writing transistor T4 is electrically connected to the second scanning signal line GP, a first electrode s4 of the data writing transistor T4 is electrically connected to the data signal line Dt, and a second electrode d4 of the data writing transistor T4 is electrically connected to the second node N2.

[0097] A gate g5 of the first light emitting control transistor T5 is electrically connected to the light emitting control signal line Em, a first electrode s5 of the first light emitting control transistor T5 is electrically connected to the first power signal line Vdd, and a second electrode d5 of the first light emitting control transistor T5 is electrically connected to the second node N2.

[0098] The gate g6 of the second light emitting control transistor T6 is electrically connected to the light emitting control signal line Em, the first electrode s6 of the second light emitting control transistor T6 is electrically connected to the third node N3, and the second electrode d6 of the second light emitting control transistor T6 is electrically connected to the anode of the light emitting device 212.

[0099] The gate g7 of the second reset transistor T7 is electrically connected to the second reset signal line Rst-H, the first electrode s7 of the second reset transistor T7 is electrically connected to the second initialization signal line Vt2, and the second electrode d7 of the second reset transistor T7 is electrically connected to the anode of the light-emitting device 212 and the second electrode d6 of the second light-emitting control transistor T6.

[0100] A gate g8 of the third reset transistor T8 is electrically connected to the second reset signal line Rst-H, a first electrode s8 of the third reset transistor T8 is electrically connected to the third initialization signal line Vt3, and a second electrode d8 of the third reset transistor T8 is electrically connected to the second node N2.

[0101] A first electrode of the capacitor Cst is electrically connected to the first node N1 , and a second electrode thereof is electrically connected to the first power signal line Vdd.

[0102] The cathode of the light emitting device 212 is electrically connected to the second power signal line.

[0103] In some examples, the voltage of the power signal provided by the first power signal line Vdd is higher than the voltage of the power signal provided by the second power signal line.

[0104] In some examples, the compensation transistor T2 may be an N-type transistor, and the first reset transistor T1, the driving transistor T3, the data writing transistor T4, the first emission control transistor T5, the second emission control transistor T6, the second reset transistor T7, and the third reset transistor T8 may be P-type transistors.

[0105] In some examples, the compensation transistor T2 may be an oxide transistor, which may be an N-type transistor, and the other transistors may be LTPS (Low Temperature Poly Silicon) transistors, which may be P-type transistors.

[0106] Among them, the N-type transistor is turned on when the gate receives a high voltage signal, while the P-type transistor is turned on when the gate receives a low voltage signal. It should be noted that the "high voltage signal" and "low voltage signal" mentioned above are popular terms. Generally speaking, the turning-on condition of the N-type transistor is that the gate-source voltage difference is greater than its threshold voltage, that is, the gate voltage of the N-type transistor is greater than the sum of its source voltage and its threshold voltage. The threshold voltage of the N-type transistor is a positive value, and the gate voltage signal that turns on the N-type transistor is called a high voltage signal. The turning-on condition of the P-type transistor is that the absolute value of the gate-source voltage difference is greater than its threshold voltage. The threshold voltage of the P-type transistor is a negative value, that is, the gate voltage of the P-type transistor is less than the sum of its source voltage and its threshold voltage. The gate voltage signal that turns on the P-type transistor is called a low voltage signal, and the voltage of the "high voltage signal" is greater than the voltage of the "low voltage signal".

[0107] In some other examples, the plurality of transistors may all be P-type transistors, and in some other examples, the plurality of transistors may all be N-type transistors.

[0108] The following describes the driving process of the pixel driving circuit 211 provided in some embodiments of the present disclosure by taking the compensation transistor T2 as an N-type transistor and the other transistors as P-type transistors as an example.

[0109] FIG. 6 is a timing diagram of an “8T1C” pixel driving circuit 211 according to some embodiments.

[0110] Please refer to Figure 6, the first scanning signal line GN is used to transmit the first scanning signal Gt-N, the second scanning signal line GP is used to transmit the second scanning signal Gt-P, the light-emitting control signal line Em is used to transmit the light-emitting control signal EM, the first reset signal line Rst-P is used to transmit the first reset signal RST-P, and the second reset signal line Rst-H is used to transmit the second reset signal RST-H.

[0111] The driving process of the pixel driving circuit 211 is as follows: one frame period includes a first stage t1 , a second stage t2 , a third stage t3 and a fourth stage.

[0112] FIG7 is a schematic diagram of an "8T1C" pixel driving circuit 211 in the first phase t1 according to some embodiments. It should be noted that in FIG7 , a transistor covered with an "×" indicates that the transistor is in an off state, in which case the connection between the first and second electrodes of the transistor is not open, while a transistor not covered with an "×" indicates that the transistor is in an on state, in which case the connection between the first and second electrodes of the transistor is open.

[0113] Please refer to Figure 7 and combine it with Figure 6. In the first stage t1, the second reset signal RST-H is at a low level. Under the control of the second reset signal RST-H, the second reset transistor T7 and the third reset transistor T8 are turned on. Therefore, the second initialization signal provided by the second initialization signal line Vt2 can reset the anode of the light-emitting device 212 through the second reset transistor T7, and the third initialization signal provided by the third initialization signal line Vt3 can reset the second node N2 through the third reset transistor T8.

[0114] The light emitting control signal EM is at a high level. Under the control of the light emitting control signal EM, the first light emitting control transistor T5 and the second light emitting control transistor T5 are in a turned-off state.

[0115] The second scanning signal Gt-P is at a high level, and the data writing transistor T4 is in a closed state under the control of the second scanning signal Gt-P.

[0116] The first scanning signal Gt-N is at a high level. Under the control of the first scanning signal Gt-N, the compensation transistor T2 is in an on state.

[0117] The first reset signal RST-P is at a high level. Under the control of the first reset signal RST-P, the first reset transistor T1 is in a turned-off state.

[0118] The driving transistor T3 is in the off state.

[0119] FIG. 8 is a schematic diagram of an “8T1C” pixel driving circuit 211 in a second phase t2 according to some embodiments.

[0120] 8 and in combination with FIG. 6 , the second reset signal RST-H changes to a high level. Under the control of the second reset signal RST-H, the second reset transistor T7 and the third reset transistor T8 are turned off.

[0121] The first reset signal RST-P changes to a low level. Under the control of the first reset signal RST-P, the first reset transistor T1 is turned on. At this time, the first initialization signal provided by the first initialization signal line Vt1 can be written to the third node N3 through the first reset transistor T1, thereby resetting the third node N3.

[0122] At the same time, the first scan signal Gt-N is at a high level. Under the control of the first scan signal Gt-N, the compensation transistor T2 is in an on state. At this time, the first initialization signal provided by the first initialization signal line Vt1 can be written to the first node N1 through the first reset transistor T1 and the compensation transistor T2, thereby resetting the first node N1. At this time, the first node N1 can turn on the driving transistor T3.

[0123] When the driving transistor T3 is turned on, the first initialization signal provided by the first initialization signal line Vt1 may be written into the second node N2 through the first reset transistor T1 and the driving transistor T3 , thereby resetting the second node N2 .

[0124] Afterwards, the first reset signal RST-P changes to a high level, so that the first reset transistor T1 is turned off, and the second scan signal Gt-P changes to a low level. Under the control of the second scan signal Gt-P, the data write transistor T4 is turned on. Therefore, the data signal provided by the data signal line Dt can be written to the first node N1 through the data write transistor T4, the second node N2, the driving transistor T3, the third node N3 and the compensation transistor T2 in sequence. At this time, the first node N1 with the data signal written can turn off the driving transistor T3.

[0125] The light emitting control signal EM is at a high level. Under the control of the light emitting control signal EM, the first light emitting control transistor T5 and the second light emitting control transistor T5 are in a turned-off state.

[0126] FIG. 9 is a schematic diagram of the “8T1C” pixel driving circuit 211 in the third phase t3 according to some embodiments.

[0127] 9 and in combination with FIG. 6 , the second scanning signal Gt-P changes to a high level, and the data writing transistor T4 is turned off under the control of the second scanning signal Gt-P.

[0128] The first scanning signal Gt-N changes to a low level, and under the control of the first scanning signal Gt-N, the compensation transistor T2 is turned off.

[0129] The second reset signal RST-H changes to a low level. Under the control of the second reset signal RST-H, the second reset transistor T7 and the third reset transistor T8 are turned on. Therefore, the second initialization signal provided by the second initialization signal line Vt2 can reset the anode of the light-emitting device 212 through the second reset transistor T7, and the third initialization signal provided by the third initialization signal line Vt3 can reset the second node N2 through the third reset transistor T8.

[0130] Subsequently, the second reset signal RST-H changes to a high level, so that the second reset transistor T7 and the third reset transistor T8 are turned off.

[0131] The first reset signal RST-P maintains a high level. Under the control of the first reset signal RST-P, the first reset transistor T1 is in a turned-off state.

[0132] The light emitting control signal EM continues to maintain a high level. Under the control of the light emitting control signal EM, the first light emitting control transistor T5 and the second light emitting control transistor T5 are in a turned-off state.

[0133] The driving transistor T3 is in the off state.

[0134] FIG. 10 is a schematic diagram of the “8T1C” pixel driving circuit 211 in the fourth phase t4 according to some embodiments.

[0135] Referring to FIG10 and in combination with FIG6 , the light-emitting control signal EM changes to a low level. Under the control of the light-emitting control signal EM, the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are turned on, and then the first power signal provided by the first power signal line Vdd can be written into the second node N2 through the first light-emitting control transistor T5. At this time, a voltage difference is formed between the second node N2 and the first node N1, thereby turning on the driving transistor T3 and the second light-emitting control transistor T6. Therefore, the first power signal provided by the first power signal line Vdd can be written into the anode of the light-emitting device 212 through the first light-emitting control transistor T5, the second node N2, the driving transistor T3, the third node N3 and the second light-emitting control transistor T6 in sequence, thereby causing the light-emitting device 212 to emit light.

[0136] The second scanning signal Gt-P continues to maintain a high level, and the data writing transistor T4 is turned off under the control of the second scanning signal Gt-P.

[0137] The first scanning signal Gt-N continues to maintain a low level, and under the control of the first scanning signal Gt-N, the compensation transistor T2 is turned off.

[0138] The second reset signal RST-H changes to a high level. Under the control of the second reset signal RST-H, the second reset transistor T7 and the third reset transistor T8 are turned off.

[0139] The first reset signal RST-P continues to maintain a high level. Under the control of the first reset signal RST-P, the first reset transistor T1 is in a turned-off state.

[0140] FIG11 is a timing diagram of an actual measurement of the “8T1C” pixel driving circuit 211 .

[0141] Referring to Figure 11 , during waveform testing of the first scanning signal Gt-N in an actual product, the inventors discovered that the potential of the first scanning signal Gt-N jumps at the moment the transistor controlled by the second reset signal RST-H turns on. This glitch occurs in the waveform of the first scanning signal Gt-N. In Figure 11 , the glitch in the waveform of the first scanning signal Gt-N is within the dashed box CC.

[0142] According to analysis, the potential jump of the first scan signal Gt-N is mainly caused by the sudden change of the voltages of the second node N2 and the third node N3.

[0143] For example, please refer to Figures 6 and 7 again. During the driving process of the above-mentioned pixel driving circuit 211, in the first stage t1, the second reset signal RST-H transmitted by the second reset signal line Rst-H is at a low level, thereby enabling the third reset transistor T8 controlled by it to be turned on. At this time, the third initialization signal transmitted by the third initialization signal line Vt3 can be written to the second node N2 through the third reset transistor T8, causing the voltage of the second node N2 to change.

[0144] In the related art, the second node N2 overlaps with the first scan signal line GN. Therefore, a capacitor can be formed between the second node N2 and the first scan signal line GN. When the third initialization signal is written to the second node N2, the voltage of the second node N2 changes. Due to the capacitive coupling between the second node N2 and the first scan signal line GN, the voltage of the first scan signal line GN also changes with the voltage of the second node N2.

[0145] For another example, referring again to Figures 6 and 8 , in the second phase t2, the first reset signal RST-P changes to a low level, the first reset transistor T1 turns on, and the first initialization signal provided by the first initialization signal line Vt1 can be written to the third node N3 via the first reset transistor T1, thereby resetting the third node N3 and causing the voltage of the third node N3 to suddenly change. Simultaneously, the first scan signal Gt-N is at a high level, and the compensation transistor T2 is turned on. At this time, the first initialization signal provided by the first initialization signal line Vt1 can be written to the first node N1 via the first reset transistor T1 and the compensation transistor T2, thereby resetting the first node N1. At this time, the first node N1 can cause the driving transistor T3 to turn on. With the driving transistor T3 turned on, the first initialization signal provided by the first initialization signal line Vt1 can be written to the second node N2 via the first reset transistor T1 and the driving transistor T3, thereby resetting the second node N2 and causing the voltage of the second node N2 to suddenly change. In summary, in the second phase t2, the voltages of both the second node N2 and the third node N3 will suddenly change.

[0146] In the related art, both the second node N2 and the third node N3 overlap with the first scan signal line GN. Therefore, capacitance can be formed between the second node N2 and the third node N3 and the first scan signal line GN. Furthermore, when the voltages of the second node N2 and the third node N3 change, the voltage of the first scan signal line GN can change due to capacitive coupling between the second node N2 and the first scan signal line GN, and capacitive coupling between the third node N3 and the first scan signal line GN. In the related art, the capacitance between the second node N2 and the first scan signal line GN is 1.829 fF. The capacitance between the third node N3 and the first scan signal line GN is 3.340 fF. In this case, the capacitance between the second node N2 and the first scan signal line GN is larger, and the capacitance between the third node N3 and the first scan signal line GN is larger.

[0147] Furthermore, in the related art, a first scanning signal line GN may be arranged to overlap with a first node N1 of a row of pixel driving circuits 211. Therefore, a capacitance may be formed between the first scanning signal line GN and the first node N1 of a row of pixel driving circuits 211. When a voltage change at the second node N2 and / or the third node N3 of a pixel driving circuit 211 causes a voltage change at the first scanning signal line GN electrically connected to the pixel driving circuit 211, the capacitive coupling between the first scanning signal line GN and the first node N1 may cause the voltage at the first node N1 of the pixel driving circuit 211 to fluctuate, resulting in a voltage fluctuation of approximately 0.1 mV at point N1.

[0148] At the same time, the first scan signal line GN also affects the voltage of the first node N1 in the pixel driving circuit 211 adjacent to the pixel driving circuit 211 in the row direction. The voltage of the first node N1 affects the degree of opening of the driving transistor T3, thereby affecting the brightness of the light-emitting device 212. This phenomenon can be called lateral crosstalk deterioration.

[0149] Based on this, the present disclosure provides an array substrate 300 .

[0150] FIG. 12 is a structural diagram of an array substrate 300 according to some embodiments.

[0151] 12 , the array substrate 300 includes a substrate 310 , a plurality of first scanning signal lines Gate-N, and a plurality of pixel driving circuits 211 . The plurality of pixel driving circuits 211 and the plurality of first scanning signal lines GN are located on one side of the substrate 310 .

[0152] The substrate 310 may include a display area AA and a peripheral area BB. The display area AA of the substrate 310 is the same area as the display area AA of the display panel 200 provided in some of the above embodiments, and the peripheral area BB of the substrate 310 is the same area as the peripheral area BB of the display panel 200 provided in some of the above embodiments. The plurality of row pixel regions 301 may be located within the display area AA.

[0153] The substrate 310 may be a single-layer structure or a stacked-layer structure; it may be rigid or flexible.

[0154] In addition to the substrate 310, the array substrate 300 may further include a first active layer, a first gate metal layer, a second gate metal layer, a second active layer, a third gate metal layer, a first source-drain metal layer, and a second source-drain metal layer, which are sequentially stacked on the substrate 310. For example, the first active layer and the first gate metal layer are used to form some transistors in the pixel driving circuit 211, such as the first reset transistor T1, the driving transistor T3, the data writing transistor T4, the first emission control transistor T5, the second emission control transistor T6, the second reset transistor T7, and the third reset transistor T8. The second gate metal layer, the second active layer, and the third gate metal layer may be used to form another portion of transistors in the pixel driving circuit 211, such as the compensation transistor T2. Furthermore, the first gate metal layer, the second gate metal layer, and the third gate metal layer may also be used to form some signal lines that provide signals to the pixel driving circuit 211. The first source-drain metal layer and the second source-drain metal layer may be used to form the remaining signal lines that provide signals to the pixel driving circuit 211.

[0155] For example, the plurality of first scanning signal lines GN may be located on a side of the plurality of pixel driving circuits 211 facing away from the substrate 310. The plurality of pixel driving circuits 211 are arranged in multiple rows and columns. A row of pixel driving circuits 211 extends along a row direction X, and a column of pixel driving circuits 211 extends along a column direction Y. The row direction X and the column direction Y are both parallel to the substrate 310 and are arranged in an intersecting manner.

[0156] In some examples, the row direction X and the column direction Y may be approximately perpendicular, and in this case, the angle between the row direction X and the column direction Y is approximately 90°. For example, the angle between the row direction X and the column direction Y may be 85°, 90°, or 95°.

[0157] The plurality of first scanning signal lines GN extend along the row direction X and are sequentially arranged along the column direction Y. For example, one first scanning signal line GN passes through a row of pixel driving circuits 211. Here, "passes through" can be understood as an overlap between the orthographic projection of the first scanning signal line GN on the substrate 310 and the orthographic projection of the pixel driving circuit 211 on the substrate 310.

[0158] In which, the array substrate 300 may include: multiple row pixel areas 301, the multiple row pixel areas 301 extend along the row direction X and are arranged in sequence along the column direction Y; a row pixel driving circuit 211 is arranged in a row pixel area 301, and the first scanning signal line GN, the second scanning signal line GP, the light-emitting control signal line Em, the first reset signal line Rst-P and the second reset signal line Rst-H electrically connected to the row pixel driving circuit 211 are all located in the row pixel area 301 where the row pixel driving circuit 211 is located.

[0159] FIG. 13 is a diagram illustrating a film layer structure of an array substrate 300 according to some embodiments.

[0160] 13 , a pixel driving circuit 211 includes a compensation transistor T2 and a driving transistor T3 , wherein the compensation transistor T2 includes a control electrode g2 , a first electrode s2 , and a second electrode d2 , and the driving transistor T3 includes a control electrode g3 , a first electrode s3 , and a second electrode d3 .

[0161] A first scanning signal line GN is electrically connected to the control electrode g2 of the compensation transistor T2 of a row of pixel driving circuits 211 , so that the first scanning signal line GN can provide a first scanning signal Gt-N to the control electrode g2 of the compensation transistor T2 of a row of pixel driving circuits 211 .

[0162] FIG. 14A is another film layer structure diagram of the array substrate 300 according to some embodiments.

[0163] Referring to FIG. 14A , a pixel driving circuit 211 further includes a first conductive connection portion N11. The control electrode g3 of the driving transistor T3 (shown in FIG. 13 ) and the second electrode d2 of the compensation transistor T2 (shown in FIG. 13 ) are both electrically connected to the first conductive connection portion N11. The first conductive connection portion N11 does not overlap with the first scan signal line GN in a direction perpendicular to the substrate 310.

[0164] The first conductive connection portion N11 may be a first node N1 in the equivalent circuit diagram of the pixel driving circuit 211 (as shown in FIG. 5 ).

[0165] The first conductive connection portion N11 does not overlap with the first scan signal line GN in a direction perpendicular to the substrate 310. This means that the orthographic projection of the first conductive connection portion N11 on the substrate 310 does not overlap with the orthographic projection of the first scan signal line GN on the substrate 310. This reduces the capacitance between the first conductive connection portion N11 and the first scan signal line GN.

[0166] As can be seen from the above, during the driving process of the pixel driving circuit 211, in the first phase t1, the third initialization signal transmitted by the third initialization signal line Vt3 can be written to the second node N2 via the third reset transistor T8, causing the voltage of the second node N2 to suddenly change. In the second phase t2, the first initialization signal provided by the first initialization signal line Vt1 can be written to the third node N3 via the first reset transistor T1, causing the voltage of the third node N3 to suddenly change. Thereafter, when the driving transistor T3 is turned on, the first initialization signal provided by the first initialization signal line Vt1 can be written to the second node N2 via the first reset transistor T1 and the driving transistor T3, thereby causing the voltage of the second node N2 to suddenly change. The sudden change in the voltage of the second node N2 and / or the sudden change in the voltage of the third node N3 will cause the voltage of the first scanning signal line GN to change. In some embodiments of the present disclosure, by ensuring that the first conductive connection portion N11 does not overlap with the first scanning signal line GN, the capacitance value between the first conductive connection portion N11 and the first scanning signal line GN can be reduced. Furthermore, when the voltage of the first scanning signal line GN changes, the voltage change value of the first conductive connection portion N11 can be reduced, and the influence of the first scanning signal line GN on the voltage of the first conductive connection portion N11 in the pixel driving circuit 211 adjacent to the above-mentioned pixel driving circuit 211 in the row direction X can be reduced. In this way, the luminous brightness of the light-emitting device 212 driven by the adjacent pixel driving circuit 211 is less affected, thereby improving the problem of lateral crosstalk. When the above-mentioned array substrate 300 is applied to the display panel 200, the display effect of the display panel 200 can be improved.

[0167] Continuing with FIG14A , in some embodiments, the pixel driving circuit 211 further includes a data writing transistor T4 and a first light emission control transistor T5. A second electrode d4 (as shown in FIG13 ) of the data writing transistor T4 is electrically connected to a first electrode s3 of the driving transistor T3 and a second electrode d5 (as shown in FIG13 ) of the first light emission control transistor T5.

[0168] The array substrate 300 further includes: a plurality of second scanning signal lines GP and a plurality of light-emitting control signal lines Em, and the plurality of second scanning signal lines GP and the plurality of light-emitting control signal lines Em are located on one side of the substrate 310. For example, the plurality of second scanning signal lines GP and the plurality of light-emitting control signal lines Em can be located on a side of the plurality of pixel driving circuits 211 facing away from the substrate 310.

[0169] Among them, multiple second scanning signal lines GP all extend along the row direction X and are arranged in sequence along the column direction Y. One second scanning signal line GP is electrically connected to the control electrode g4 of the data writing transistor T4 of a row of pixel driving circuits 211 (as shown in Figure 13). In this way, one second scanning signal line GP can provide a second scanning signal Gt-P to the control electrode g4 of the data writing transistor T4 of a row of pixel driving circuits 211.

[0170] Multiple light-emitting control signal lines Em all extend along the row direction X and are arranged sequentially along the column direction Y. One light-emitting control signal line Em is electrically connected to the control electrode g5 of the first light-emitting control transistor T5 of a row of pixel driving circuits 211. In this way, one light-emitting control signal line Em can provide a light-emitting control signal EM to the first light-emitting control transistor T5 of a row of pixel driving circuits 211.

[0171] The first scanning signal line GN, the second scanning signal line GP and the light emitting control signal line Em electrically connected to a row of pixel driving circuits 211 are all located in the row pixel region 301 (as shown in FIG. 12 ) where the row of pixel driving circuits 211 is located.

[0172] In a row pixel area 301 (as shown in Figure 12): the orthographic projection of the first scanning signal GN on the substrate 310 is located on the side of the orthographic projection of the second scanning signal line GP on the substrate 310 away from the orthographic projection of the light-emitting control signal line Em on the substrate 310, and the orthographic projection of the driving transistor T3 on the substrate 310 is located between the orthographic projection of the second scanning signal line GP on the substrate 310 and the orthographic projection of the light-emitting control signal line Em on the substrate 310.

[0173] Referring again to FIG. 13 , in the pixel driving circuit 211, the first and second electrodes of the transistor are located on either side of the control electrode, respectively. A gate line is electrically connected to the control electrode of the transistor. Consequently, the location of the gate line to which the transistor is electrically connected determines the position of the transistor in the pixel driving circuit 211. The transistors may include a first reset transistor T1, a compensation transistor T2, ..., and a third reset transistor T8. The gate lines may include a first scanning signal line GN, a second scanning signal line GP, an emission control signal line Em, a first reset signal line Rst-P, and a second reset signal line Rst-H.

[0174] In one row of pixel regions 301 (as shown in FIG12 ), the orthographic projection of the first scanning signal line GN on the substrate 310 is located on a side of the orthographic projection of the second scanning signal line GP on the substrate 310 that is away from the orthographic projection of the emission control signal line Em on the substrate 310, and the orthographic projection of the driving transistor T3 on the substrate 310 is located between the orthographic projections of the second scanning signal line GP and the emission control signal line Em on the substrate 310. The first conductive connection portion N11 is electrically connected to the control electrode g3 of the driving transistor T3 and the second electrode d2 of the compensation transistor T2. Therefore, the orthographic projection of the end of the first conductive connection portion N11 electrically connected to the driving transistor T3 on the substrate 310 is located on a side of the second scanning signal line GP that is away from the orthographic projection of the first scanning signal line GN on the substrate 310. In addition, the first conductive connection portion N11 does not overlap with the first scan signal GN. Therefore, the orthographic projection of the first conductive connection portion N11 on the substrate 310 can be located on the side of the orthographic projection of the second scan signal line GP on the substrate 310 away from the orthographic projection on the substrate 310, so that the first conductive connection portion N11 does not overlap with the first scan signal GN.

[0175] 14A , in some embodiments, within a row of pixel regions 301 (as shown in FIG12 ), the compensation transistor T2 and the first conductive connection portion N11 are sequentially arranged along the column direction Y. The compensation transistor T2 passes through the first scanning signal line GN.

[0176] The first electrode s2 and the second electrode d2 of the compensation transistor T2 are respectively located on two sides of the first scanning signal line GN in the column direction Y.

[0177] The orthographic projection of the first electrode s2 of the compensation transistor T2 on the substrate 310 is located on a side of the orthographic projection of the first scanning signal line GN on the substrate 310 away from the orthographic projection of the light emitting control signal line EM on the substrate 310 .

[0178] The positive projection of the second electrode d2 of the compensation transistor T2 on the substrate 310 is located on the side where the positive projection of the first scanning signal line GN on the substrate 310 is close to the positive projection of the light-emitting control signal line EM on the substrate 310, and the first conductive connection part GN is located on the side of the first scanning signal line GN close to the light-emitting control signal line EM.

[0179] The phrase "compensation transistor T2 passes through the first scanning signal line GN" can be understood as meaning that the orthographic projection of the compensation transistor T2 on the substrate 310 overlaps with the orthographic projection of the first scanning signal line GN on the substrate 310. The overlapping portion of the first scanning signal line GN and the compensation transistor T2 can be reused as the control electrode g2 of the compensation transistor T2.

[0180] The first conductive connection portion N11 is electrically connected to the second electrode d2 of the compensation transistor T2 . Therefore, the orthographic projection of the first conductive connection portion N11 on the substrate 310 overlaps with the orthographic projection of the second electrode d2 of the compensation transistor T2 on the substrate 310 .

[0181] One end of the first conductive connection portion N11 is electrically connected between the control electrode g3 of the driving transistor T3 (as shown in FIG13 ) and the second electrode d2 of the compensation transistor T2 (as shown in FIG13 ). The orthographic projection of the second electrode d2 of the compensation transistor T2 on the substrate 310 is located on a side where the orthographic projection of the first scan signal line GN on the substrate 310 is close to the orthographic projection of the emission control signal line EM on the substrate 310. Therefore, the orthographic projection of the end of the first conductive connection portion GN electrically connected to the second electrode d2 of the compensation transistor T2 on the substrate 310 can be located on a side where the orthographic projection of the first scan signal line GN on the substrate 310 is close to the orthographic projection of the emission control signal line EM on the substrate 310. As can be seen from some of the above embodiments, the orthographic projection of the end of the first conductive connection portion N11 electrically connected to the driving transistor T3 on the substrate 310 is located on a side of the second scan signal line GP away from the orthographic projection of the first scan signal line GN on the substrate 310. Therefore, the orthographic projection of the first conductive connection portion N11 as a whole on the substrate 310 is located on the side of the orthographic projection of the first scanning signal line GN on the substrate 310 close to the orthographic projection of the light-emitting control signal line EM on the substrate 310, so that the first conductive connection portion GN and the first scanning signal line GN do not overlap.

[0182] Continuing with FIG. 14A , within a row of pixel regions 301 (as shown in FIG. 12 ), a portion of the orthogonal projection of the data write transistor T4 on the substrate 310 is disposed opposite to a portion of the orthogonal projection of the compensation transistor T2 on the substrate 310 in the row direction X. Another portion of the orthogonal projection of the data write transistor T4 on the substrate 310 is disposed opposite to a portion of the orthogonal projection of the first conductive connection portion N11 on the substrate 310 in the row direction X. This arrangement can reduce the size of the pixel driving circuit 211 in the column direction Y.

[0183] The data writing transistor T4 is located on one side of the compensation transistor T2 in the row direction X, and the data writing transistor T4 is also located on one side of the first conductive connection portion N11 in the row direction X.

[0184] Continuing with FIG14A , the data write transistor T4 passes through the second scan signal line GP and is located on the side of the first scan signal line GN near the light-emission control signal line EM. One second scan signal line GP overlaps with the data write transistor T4 in a row of pixel driver circuits 211.

[0185] The array substrate 300 further includes: a plurality of data transfer portions 394 . The plurality of data transfer portions 394 are located on a side of the plurality of pixel driving circuits 211 away from the substrate 310 .

[0186] FIG. 14B is another film layer structure diagram of the array substrate 300 according to some embodiments.

[0187] Referring to FIG. 14B , in conjunction with FIG. 14A , the array substrate 300 further includes a plurality of data lines Dt. The plurality of data lines Dt are located on a side of the plurality of data transfer portions 394 away from the substrate 310. The plurality of data lines Dt extend along the column direction Y and are sequentially arranged along the row direction Y. Each data line Dt is electrically connected to a first electrode s4 of a data write transistor T4 in a row of pixel driving circuits 211 via a data transfer portion 394.

[0188] In one row of pixel regions 301 , the orthographic projection of the data transfer portion 394 on the substrate 310 is located between the orthographic projection of the first scanning signal line GN on the substrate 310 and the orthographic projection of the second scanning signal line GP on the substrate 310 .

[0189] Among them, the data line Dt can be electrically connected to the first electrode s4 of the data writing transistor T4 through the data transfer part 394. Therefore, the data transfer part 394 can receive the data signal transmitted by the data line Dt. Therefore, the voltage of the data transfer part 394 can change with the data signal. When the voltage of the data transfer part 394 changes, it may interfere with the transistors around it. By setting the data transfer part 394 between the first scanning signal line GN and the second scanning signal line GP, the first scanning signal line GN and the second scanning signal line GP can shield the interference caused by the data transfer part 394 to other transistors.

[0190] In some examples, the first scan signal line GN and the second scan signal line GP have at least two different spacings in the column direction Y. For example, the first scan signal line GN may include a main portion G1 and an isolation portion G2, wherein the orthographic projection of the main portion G1 on the substrate 310 may be arranged opposite the orthographic projection of the data write transistor T4 on the substrate 310 in the column direction Y, and the orthographic projection of the isolation portion G2 on the substrate 310 may be arranged opposite the orthographic projection of the data transfer portion 394 on the substrate 310 in the column direction Y. The distance between the isolation portion G2 and the second scan signal line GP in the column direction Y is greater than the distance between the main portion G1 and the second scan signal line GP in the column direction Y. This arrangement provides a larger space for the data transfer portion 394.

[0191] In some examples, the isolation portion G2 has at least two different spacings from the second scan signal line GP in the column direction Y. For example, the isolation portion G2 may include a first isolation portion connected to the main portion G1 and a second isolation portion connected to the first isolation portion, wherein the distance between the second isolation portion and the second scan signal line GP in the column direction Y is greater than the distance between the first isolation portion and the second scan signal line GP in the column direction Y. The first isolation portion may extend in a direction away from the second scan signal line GP.

[0192] Continuing with FIG14A , within a row of pixel regions 301 (as shown in FIG12 ), a portion of the orthographic projection of the first conductive connection portion N11 on the substrate 310 overlaps with a portion of the orthographic projection of the compensation transistor T2 on the substrate 310. For example, a portion of the orthographic projection of the first conductive connection portion N11 on the substrate 310 may overlap with an orthographic projection of the second electrode d2 of the compensation transistor T2 on the substrate 310.

[0193] Another portion of the orthographic projection of the first conductive connection portion N11 on the substrate 310 overlaps with a portion of the orthographic projection of the driving transistor T3 on the substrate 310 .

[0194] The orthographic projection of the second electrode d2 of the compensation transistor T2 and the orthographic projection of the driving transistor T3 on the substrate 310 are both located on a side of the first scanning signal line GN close to the emission control signal line EM. In this case, the second scanning signal line GP, the emission control signal line EM, the second electrode d2 of the compensation transistor T2, and the driving transistor T3 are located on the same side of the first scanning signal line GN in the column direction Y. This arrangement ensures that the orthographic projection of the first conductive connection portion N11 on the substrate 310 does not overlap with the orthographic projection of the first scanning signal line GN on the substrate 310.

[0195] 14A , in some embodiments, the pixel driving circuit 211 further includes a second conductive connection portion N22 , which is electrically connected to the first electrode s3 of the driving transistor T3 , the second electrode d5 of the first light-emitting control transistor T5 , and the second electrode d4 of the data writing transistor T4 .

[0196] The orthographic projection of the second conductive connection portion N22 on the substrate 310 does not overlap with the orthographic projection of the first scan signal line GN on the substrate 310 .

[0197] The second conductive connection portion N22 may be a second node N2 in the equivalent circuit diagram of the pixel driving circuit 211 (as shown in FIG. 5 ).

[0198] Among them, the orthographic projection of the second conductive connection part N22 on the substrate 310 does not overlap with the orthographic projection of the first scanning signal line GN on the substrate 310. It can be understood that the second conductive connection part N22 and the first scanning signal line GN do not overlap in the direction perpendicular to the substrate 310, thereby reducing the capacitance between the second conductive connection part N22 and the first scanning signal line GN.

[0199] Referring again to FIG. 14A , in conjunction with FIG. 7 and FIG. 8 , during the driving process of the pixel driving circuit 211, the voltage of the second conductive connection portion N22 undergoes a sudden change in both the first stage t1 and the second stage t2. By ensuring that the orthographic projections of the second conductive connection portion N22 and the first scan signal line GN on the substrate 310 do not overlap, the capacitance formed between the second conductive connection portion N22 and the first scan signal line GN can be reduced, thereby reducing the impact of the sudden change in the voltage of the second conductive connection portion N22 on the voltage of the first scan signal line GN and the voltage variation of the first scan signal line GN. Furthermore, the impact of the first scan signal line GN on the voltage of the first conductive connection portion N11 can be reduced, i.e., the voltage variation of the first conductive connection portion N11 can be reduced. In summary, in some embodiments of the present disclosure, by ensuring that the orthographic projections of the second conductive connection portion N22 and the first scan signal line GN on the substrate 310 do not overlap, the voltage variation of the first scan signal line GN can have a minimal impact on the brightness of the light-emitting device 212. In addition, when the voltage change value of the first scanning signal line GN is small, the first scanning signal line GN has little effect on the voltage of the first conductive connection part N11 in the pixel driving circuit 211 adjacent to the above-mentioned pixel driving circuit 211 in the row direction X. Therefore, the brightness of the light-emitting device 212 driven by the adjacent pixel driving circuit 211 is less affected, thereby improving the problem of lateral crosstalk. When the above-mentioned array substrate 300 is applied to the display panel 200, the display effect of the display panel 200 can be improved.

[0200] The second scanning signal line GP is electrically connected to the control electrode g4 of the data writing transistor T4, and the light control signal line Em is electrically connected to the control electrode g5 of the first emission control transistor T5. Therefore, the position of the second scanning signal line GP can determine the position of the control electrode g4 of the data writing transistor T4, and the position of the light control signal line Em can determine the position of the control electrode g5 of the first emission control transistor T5.

[0201] In some of the above embodiments, within a row of pixel regions 301 (as shown in FIG12 ), the orthogonal projection of the first scan signal line GN on the substrate 310 is located on a side of the orthogonal projection of the second scan signal line GP on the substrate 310 that is away from the orthogonal projection of the emission control signal line Em on the substrate 310, and the drive transistor T3 is located between the second scan signal line GP and the emission control signal line Em. This arrangement allows the drive transistor T3, the data write transistor T4, and the first emission control transistor T5 to be located on the same side of the first scan signal line GN.

[0202] Among them, the second conductive connection part N22 is electrically connected to the second electrode d4 of the data writing transistor T4, the second electrode d5 of the first light-emitting control transistor T5 and the control electrode g3 of the driving transistor T3. Therefore, the second conductive connection part N22 can be located on the same side of the first scanning signal GN as the data writing transistor T4, the first light-emitting control transistor T5 and the driving transistor T3, so that the second conductive connection part N22 and the first scanning signal GN do not overlap, thereby reducing the capacitance value of the capacitor formed between the second conductive connection part N22 and the first scanning signal line GN.

[0203] In some embodiments, the data writing transistor T4 and the first light emission control transistor T5 are sequentially arranged along the column direction Y, and the first light emission control transistor T5 is located on a side of the data writing transistor T4 away from the first scan signal line GN.

[0204] In some embodiments, the pixel driving circuit 211 further includes a third reset transistor T8 , wherein a second electrode d8 of the third reset transistor T8 is electrically connected to the second conductive connection portion N22 .

[0205] The array substrate 300 also includes: multiple second reset signal lines Rst-H, which are located on the side of the multiple pixel driving circuits 211 away from the substrate 310, and the multiple second reset signal lines Rst-H extend along the row direction X and are arranged in sequence along the column direction Y.

[0206] A second reset signal line Rst-H is electrically connected to the control electrode g8 of the third reset transistor T8 of a row of pixel driving circuits 211 , and thus a second reset signal line Rst-H can provide a second reset signal RST-H to the control electrode g8 of the third reset transistor T8 of a row of pixel driving circuits 211 .

[0207] The second reset signal line Rst-H to which a row of pixel driving circuits 211 is electrically connected is located in a row of pixel region 301 (as shown in FIG. 12 ) where the row of pixel driving circuits 211 is located.

[0208] In one row of pixel regions (as shown in FIG12 ), the second reset signal line Rst-H is located on a side of the light emitting control signal line Em away from the first scanning signal line GN.

[0209] By positioning the second reset signal line Rst-H on a side of the light-emission control signal line Em away from the first scan signal line GN, the third reset transistor T8 and the first light-emission control transistor T5 can be positioned on the same side of the first scan signal line GN. As can be seen from some of the aforementioned embodiments, the data-writing transistor T4, the driving transistor T3, and the first light-emission control transistor T5 can be positioned on the same side of the first scan signal line GN. The second conductive connection portion N22 can be electrically connected to the second electrode d8 of the third reset transistor T8, the second electrode d4 of the data-writing transistor T4, the first electrode s3 of the driving transistor T3, and the second electrode d5 of the first light-emission control transistor T5. Since the third reset transistor T8, the data-writing transistor T4, the driving transistor T3, and the first light-emission control transistor T5 are all positioned on the same side of the first scan signal line GN, the second conductive connection portion N22 can be prevented from overlapping the first scan signal line GN, thereby reducing the capacitance between the second conductive connection portion N22 and the first scan signal line GN.

[0210] In some embodiments, the array substrate 300 further includes a plurality of third initialization signal lines Vt3 located on one side of the substrate 310 . For example, the plurality of third initialization signal lines Vt3 may be located on a side of the plurality of pixel driving circuits 211 facing away from the substrate 310 .

[0211] The plurality of third initialization signal lines Vt3 extend along the row direction X and are sequentially arranged along the column direction Y. One third initialization signal line Vt3 is electrically connected to the first electrode s3 of the third reset transistor T8 of a row of pixel driving circuits 211 .

[0212] The third initialization signal line Vt3 electrically connected to a row of pixel driving circuits 211 is located in a row of pixel region 301 (as shown in FIG. 12 ) where the row of pixel driving circuits 211 is located.

[0213] In one row of pixel regions 301 (as shown in FIG12 ), the orthographic projection of the third initialization signal line Vt3 on the substrate 310 at least partially overlaps with the orthographic projection of the emission control signal line Em on the substrate 310. At this point, the orthographic projection of the third initialization signal line Vt3 on the substrate 310 is located between the orthographic projection of the second reset signal line Rst-H on the substrate 310 and the orthographic projection of the second scan signal line GP on the substrate 310.

[0214] The orthographic projection of the third initialization signal line Vt3 on the substrate 310 at least partially overlaps with the orthographic projection of the light emitting control signal line Em on the substrate 310 , thereby reducing the size of the pixel driving circuit 211 in the column direction Y.

[0215] 14A and FIG13 , in a row of pixel regions 301 (as shown in FIG12 ): the third reset transistor T8 passes through the second reset signal line Rst-H and is located on a side of the third initialization signal line Vt3 away from the light emitting control signal line Em.

[0216] The first electrode s8 and the second electrode d8 of the third reset transistor T8 are respectively located on both sides of the second reset signal line Rst-H in the column direction Y. For example, the orthographic projection of the first electrode s8 of the third reset transistor T8 on the substrate 310 is located between the orthographic projection of the third initialization signal line Vt3 on the substrate 310 and the orthographic projection of the second reset signal line Rst-H on the substrate 310. Therefore, the first electrode s8 of the third reset transistor T8 and the third initialization signal line Vt3 are adjacent to each other in the column direction Y.

[0217] The orthographic projection of the second electrode d8 of the third reset transistor T8 on the substrate 310 is located on a side of the orthographic projection of the second reset signal line Rst-H on the substrate 310 away from the orthographic projection of the third initialization signal line Vt3 on the substrate 310 .

[0218] Among them, the first electrode s8 of the third reset transistor T8 is electrically connected to the third initialization signal line Vt3, and the first electrode s8 of the third reset transistor T8 and the third initialization signal line Vt3 are adjacent to each other in the column direction Y, so that the first electrode s8 of the third reset transistor T8 and the third initialization signal line Vt3 can be electrically connected.

[0219] In some examples, the array substrate 300 may further include a second transition portion 392, wherein the second transition portion 392 may be electrically connected to the third initialization signal line Vt3 and the first electrode s8 of the third reset transistor T8, respectively. For example, the two ends of the orthographic projection of the second transition portion 392 on the substrate 310 may overlap with the orthographic projection of the third initialization signal line Vt3 on the substrate 310 and the orthographic projection of the first electrode s8 of the third reset transistor T8 on the substrate 310, respectively.

[0220] The second conductive connection portion N22 crosses the third initialization signal line Vt3 , the light emission control signal line Em, and the second reset signal line Rst-H, and is electrically connected to the second electrode d8 of the third reset transistor T8 .

[0221] Among them, the second conductive connection part N22 crosses the third initialization signal line Vt3, the light-emitting control signal line Em and the second reset signal line Rst-H. It can be understood that the positive projection of the second conductive connection part N22 on the substrate 310 can partially overlap with the positive projection of the third initialization signal line Vt3, the light-emitting control signal line Em and the second reset signal line Rst-H on the substrate 310.

[0222] For example, the second conductive connection portion N22 may extend along the column direction Y.

[0223] In some embodiments, the orthographic projection of the second conductive connection portion N22 on the substrate 310 overlaps with the orthographic projections of the second electrode d8, the control electrode g8, and a portion of the first electrode s8 of the third reset transistor T8 on the substrate 310. The second electrode d8, the control electrode g8, and the first electrode s8 of the third reset transistor T8 may be sequentially arranged along the column direction Y. By ensuring that the orthographic projection of the second conductive connection portion N22 on the substrate 310 overlaps with the orthographic projections of the second electrode d8, the control electrode g8, and a portion of the first electrode s8 of the third reset transistor T8 on the substrate 310, the width of the pixel driving circuit 211 in the row direction X can be reduced.

[0224] In some examples, the positive projection of the third reset transistor T8 on the substrate 310 and the positive projection of the first light-emitting control transistor T5 perpendicular to the substrate 310 are arranged opposite to each other in the row direction X, thereby reducing the width of the pixel driving circuit 211 in the row direction X.

[0225] In some embodiments, the driving transistor T3, the data writing transistor T4, the first light-emitting control transistor T5 and the third reset transistor T8 are all located on the side of the first scanning signal line GN where the second scanning signal line GP is provided. At this time, the driving transistor T3, the data writing transistor T4, the first light-emitting control transistor T5 and the third reset transistor T8 have no overlap with the first scanning signal line GN. Therefore, the first electrode s3 of the driving transistor T3, the second electrode d4 of the data writing transistor T4, the second electrode d5 of the first light-emitting control transistor T5 and the second electrode d8 of the third reset transistor T8 electrically connected by the second conductive connection portion N22 have no overlap with the first scanning signal line GN.

[0226] The voltages of the first electrode s3 of the driving transistor T3, the second electrode d4 of the data writing transistor T4, the second electrode d5 of the first emission control transistor T5, and the second electrode d8 of the third reset transistor T8 can vary with the second conductive connection portion N22. Therefore, changes in the voltages of these four elements can also cause voltage fluctuations on the first scanning signal line GN. By ensuring that the first electrode s3 of the driving transistor T3, the second electrode d4 of the data writing transistor T4, the second electrode d5 of the first emission control transistor T5, and the second electrode d8 of the third reset transistor T8, to which the second conductive connection portion N22 is electrically connected, do not overlap with the first scanning signal line GN, the capacitance between these four elements and the first scanning signal line GN can be reduced. Therefore, when the voltage of the second conductive connection portion N22 changes, voltage fluctuations on the first scanning signal line GN can be reduced, thereby reducing the impact of the first scanning signal line GN on the voltage of the first conductive connection portion N11, thereby improving the display quality of the display panel.

[0227] Please continue to refer to FIG. 14A and combine it with FIG. 13 . In some embodiments, the pixel driving circuit 211 further includes a second light emitting control transistor T6 and a second reset transistor T7 .

[0228] A first electrode s6 of the second light emitting control transistor T6 is electrically connected to the second electrode d3 of the driving transistor T3 and the first electrode s2 of the compensation transistor T2 . A second electrode d6 of the second light emitting control transistor T6 is electrically connected to the light emitting device 212 and the second electrode d7 of the second reset transistor T7 .

[0229] Among them, the control electrode g6 of the second light-emitting control transistor T6 of a row of pixel driving circuits 211 is electrically connected to a light-emitting control signal line Em, and then the light-emitting control signal line Em can provide a light-emitting control signal EM for the control electrode g6 of the second light-emitting control transistor T6 of a row of pixel driving circuits 211.

[0230] The control electrode g7 of the second reset transistor T7 of a row of pixel driving circuits 211 is electrically connected to a second reset signal line Rst-H, and the second reset signal line Rst-H can provide a second reset signal RST-H to the control electrode g7 of the second reset transistor T7 of a row of pixel driving circuits 211.

[0231] The array substrate 300 further includes: a plurality of second initialization signal lines Vt2, which are located on a side of the plurality of pixel driving circuits 211 away from the substrate 310, and extend along the row direction X and are sequentially arranged along the column direction Y.

[0232] A second initialization signal line Vt2 is electrically connected to the first electrode s7 of the second reset transistor T7 of a row of pixel driving circuits 211 , and the second initialization signal provided by the second initialization signal line Vt2 can reset the first electrode s7 of the second reset transistor T7 of a row of pixel driving circuits 211 .

[0233] The second reset signal line Rst-H and the second initialization signal line Vt2 electrically connected to a row of pixel driving circuits 211 are both located in the row pixel region 301 where the row of pixel driving circuits 211 is located (as shown in FIG. 12 ).

[0234] In which, in a row pixel area 301 (as shown in Figure 12): the positive projection of the second initialization signal line Vt2 on the substrate 310 is located on the side of the positive projection of the second reset signal line Rst-H on the substrate 310 away from the positive projection of the first scanning signal line GN on the substrate 310.

[0235] The first electrode s7 and the second electrode d7 of the second reset transistor T7 may be respectively located on either side of the second reset signal line Rst-H in the column direction Y. For example, the orthographic projection of the first electrode s7 of the second reset transistor T7 on the substrate 310 may be located between the orthographic projection of the second reset signal line Rst-H on the substrate 310 and the orthographic projection of the second initialization signal line Vt2 on the substrate 310. This arrangement allows the first electrode s7 of the second reset transistor T7 and the second initialization signal line Vt2 to be adjacent to each other in the column direction Y, thereby facilitating electrical connection between the first electrode s7 of the second reset transistor T7 and the second initialization signal line Vt2.

[0236] In some examples, the array substrate 300 may further include a fifth transition portion 395. The fifth transition portion 395 may be electrically connected to the first electrode s7 of the second reset transistor T7 and the second initialization signal line Vt2. Furthermore, the second initialization signal line Vt2 may be electrically connected to the first electrode s7 of the second reset transistor T7 through the fifth transition portion 395. The orthographic projection of the fifth transition portion 395 on the substrate 310 may overlap with the orthographic projection of the first electrode s7 of the second reset transistor T7 and the orthographic projection of the second initialization signal line Vt2 on the substrate 310, respectively.

[0237] In some examples, the orthogonal projection of the second reset transistor T7 on the substrate 310 and the orthogonal projection of the third reset transistor T8 on the substrate 310 are arranged opposite to each other in the row direction X. This arrangement can reduce the size of the pixel driving circuit 211 in the column direction Y.

[0238] Continuing to refer to FIG. 14A and in conjunction with FIG. 13 , in some embodiments, the pixel driving circuit 211 further includes: a first reset transistor T1 and a third conductive connection portion N33 . The third conductive connection portion N33 is electrically connected to the second electrode d1 of the first reset transistor T1 , the second electrode d3 of the driving transistor T3 , the first electrode s2 of the compensation transistor T2 , and the first electrode s6 of the second light-emitting control transistor T6 .

[0239] The array substrate 300 further includes a plurality of first reset signal lines Rst-P. The plurality of first reset signal lines Rst-P are located on a side of the plurality of pixel driving circuits 211 away from the substrate 310. The plurality of first reset signal lines Rst-P extend along the row direction X and are sequentially arranged along the column direction Y. Each first reset signal line Rst-P is electrically connected to the control electrode g1 of the first reset transistor T1 of a row of pixel driving circuits 211. Consequently, each first reset signal line Rst-P can provide a first reset signal RST-P to the control electrode g1 of the first reset transistor T1 of a row of pixel driving circuits 211.

[0240] The first reset signal line Rst-P to which a row of pixel driving circuits 211 is electrically connected is located in a row of pixel region 301 (as shown in FIG. 12 ) where the row of pixel driving circuits 211 is located.

[0241] In which, in the row pixel area 301 (as shown in Figure 12), the positive projection of the first reset signal line Rst-P on the substrate 310 is located on the side of the positive projection of the light-emitting control signal line Em on the substrate 310 away from the positive projection of the first scanning signal line GN on the substrate 310.

[0242] For example, in the row pixel area 301 (as shown in Figure 12), the positive projection of the first reset signal line Rst-P on the substrate 310 is located on the side of the positive projection of the second reset signal line Rst-H on the substrate 310 away from the positive projection of the first light-emitting control signal line EM on the substrate 310.

[0243] Among them, the position of the first reset signal line Rst-P determines the position of the first reset transistor T1 in the pixel driving circuit 211. By making the first reset signal line Rst-P located on the side of the light-emitting control signal line Em away from the first scanning signal line Em, the first reset transistor T1 and the compensation transistor T2 can be respectively located on both sides of the first scanning signal line Em.

[0244] The orthographic projection of the first electrode s2 of the compensation transistor T2 on the substrate 310 is located on a side of the orthographic projection of the first scan signal line GN on the substrate 310 that is away from the orthographic projection of the emission control signal line EM on the substrate 310. The third conductive connection portion N33 can be electrically connected to the first electrode s2 of the compensation transistor T2 and the second electrode d2 of the first reset transistor T1. Therefore, the third conductive connection portion N33 can extend from one side of the first scan signal line GN in the column direction Y to the other side of the first scan signal line GN in the column direction Y. In this case, the third conductive connection portion N33 overlaps with the first scan signal line GN in a direction perpendicular to the substrate 310.

[0245] In addition, since the third conductive connection portion N33 is also electrically connected to the second electrode d3 of the driving transistor T3 and the first electrode s6 of the second light-emitting control transistor T6, the voltage of the second electrode d3 of the driving transistor T3, the voltage of the first electrode s1 of the second light-emitting control transistor T6 and the voltage of the third conductive connection portion N33 are equal.

[0246] As can be seen from some of the aforementioned embodiments, the orthographic projection of the driving transistor T3 on the substrate 310 and the orthographic projection of the second emission control transistor T6 on the substrate 310 are both located on the side where the orthographic projection of the first scan signal line GN on the substrate 310 is close to the orthographic projection of the emission control signal line Em on the substrate 310. Therefore, the orthographic projection of the second electrode d3 of the driving transistor T3 on the substrate 310 and the orthographic projection of the first electrode s6 of the second emission control transistor T6 on the substrate 310 are located on the side where the orthographic projection of the first scan signal line GN on the substrate 310 is close to the orthographic projection of the emission control signal line Em on the substrate 310. This arrangement ensures that the second electrode d3 of the driving transistor T3 and the first electrode s6 of the second emission control transistor T6 do not overlap with the first scan signal line GN. Therefore, when the voltage of the third conductive connection portion N33 suddenly changes, the impact on the voltage of the first scan signal line GN can be reduced.

[0247] In summary, among the third conductive connection portion N33, the second electrode d1 of the first reset transistor T1, the second electrode d3 of the driving transistor T3, the first electrode s2 of the compensation transistor T2 and the first electrode s6 of the second light-emitting control transistor T6, the third conductive connection portion N33 overlaps with the first scanning signal line GN, while the second electrode d1 of the first reset transistor T1, the second electrode d3 of the driving transistor T3, the first electrode s2 of the compensation transistor T2 and the first electrode s1 of the second light-emitting control transistor T6 do not overlap with the first scanning signal line GN. Therefore, when the voltage of the third conductive connection portion N33 suddenly changes, the impact on the voltage of the first scanning signal line GN can be reduced.

[0248] In some examples, the third conductive connection portion N33 may sequentially pass through the first electrode s2 of the compensation transistor T2, the second electrode d3 of the driving transistor T3, the connection point of the first electrode s6 of the second light emitting control transistor T6, and the second electrode d1 of the first reset transistor T1 along the column direction Y.

[0249] In some examples, the orthographic projection of the second initialization signal line Vt2 on the substrate 310 overlaps with the orthographic projection of the first reset signal line Rst-P on the substrate 310. In this case, the orthographic projection of the second initialization signal line Vt2 on the substrate 310 and the orthographic projection of the first reset signal line Rst-P on the substrate 310 may partially overlap or completely overlap. This configuration reduces the size of the pixel driving circuit 211 in the column direction Y.

[0250] Continuing with reference to FIG. 13 and FIG. 14A , in some embodiments, the array substrate 300 further includes a plurality of first initialization signal lines Vt1 . The plurality of first initialization signal lines Vt1 may be located on a side of the plurality of pixel driving circuits 211 facing away from the substrate 310 . The plurality of first initialization signal lines Vt1 extend along the row direction X and are sequentially arranged along the column direction Y. One first initialization signal line Vt1 is electrically connected to the first electrode s1 of the first reset transistor T1 of a row of pixel driving circuits 211. Therefore, one first initialization signal line Vt1 may provide a first initialization signal to the first electrode s1 of the first reset transistor T1 of a row of pixel driving circuits 211.

[0251] The first initialization signal line Vt1 electrically connected to a row of pixel driving circuits 211 is located in a row of pixel region 301 (as shown in FIG. 12 ) where the row of pixel driving circuits 211 is located.

[0252] In the row pixel region 301 (as shown in FIG12 ), the first initialization signal line Vt1 is located on a side of the first reset signal line Rst-P away from the first scanning signal line GN.

[0253] In some embodiments, the first reset transistor T1 passes through the first reset signal line Rst-P. At this time, the orthographic projection of the first reset transistor T1 on the substrate 310 overlaps with the orthographic projection of the first reset signal line Rst-P on the substrate 310.

[0254] The first electrode s1 and the second electrode d1 of the first reset transistor T1 are respectively located on both sides of the first reset signal line Rst-P in the column direction Y.

[0255] The orthographic projection of the first electrode s1 of the first reset transistor T1 on the substrate 310 is located between the orthographic projection of the first reset signal line Rst-P on the substrate 310 and the orthographic projection of the first initialization signal line Vt1 on the substrate 310. With this arrangement, the first electrode s1 of the first reset transistor T1 can be disposed adjacent to the first initialization signal line Vt1, thereby facilitating electrical connection between the first electrode s1 of the first reset transistor T1 and the first initialization signal line Vt1.

[0256] In some examples, the array substrate 300 may further include a first transition portion 391, wherein the first transition portion 391 may be electrically connected to the first electrode s1 of the first reset transistor T1 and the first initialization signal line Vt1, and further, the first initialization signal line Vt1 may be electrically connected to the first electrode s1 of the first reset transistor T1 through the first transition portion 391. The orthographic projection of the first transition portion 391 on the substrate 310 may overlap with the orthographic projection of the first electrode s1 of the first reset transistor T1 and the orthographic projection of the first initialization signal line Vt1 on the substrate 310, respectively.

[0257] The orthographic projection of the second electrode d1 of the first reset transistor T1 on the substrate 310 is located between the orthographic projections of the first reset signal line Rst-P and the second reset signal line Rst-H on the substrate 310. The third conductive connection portion N33 can be electrically connected to the second electrode d1 of the first reset transistor T1, thereby reducing the length of the third conductive connection portion N33.

[0258] In some examples, the orthogonal projection of the first reset transistor T1 on the substrate 310 and the orthogonal projection of the second reset transistor T7 on the substrate 310 are arranged opposite to each other in the row direction Y. This arrangement can reduce the size of the pixel driving circuit 211 in the column direction Y.

[0259] FIG. 15 is another schematic structural diagram of an array substrate 300 according to some embodiments.

[0260] 15 , the array substrate 300 further includes a plurality of auxiliary signal lines Vt40 . The plurality of auxiliary signal lines Vt40 are located on one side of the substrate 310 . For example, the plurality of auxiliary signal lines Vt40 may be located on a side of the pixel driving circuit 211 facing away from the substrate 310 .

[0261] The plurality of auxiliary signal lines Vt40 extend along the column direction Y and are sequentially arranged along the row direction X.

[0262] One auxiliary signal line Vt40 is electrically connected to any one of the first initialization signal line Vt1 , the second initialization signal line Vt2 and the third initialization signal line Vt3 .

[0263] For example, among the plurality of auxiliary signal lines Vt40 , the auxiliary signal line Vt40 that may be electrically connected to the first initialization signal line Vt1 is the first auxiliary signal line Vt41 .

[0264] Among the plurality of auxiliary signal lines Vt40 , the auxiliary signal line Vt40 that may be electrically connected to the second initialization signal line Vt2 is the second auxiliary signal line Vt42 .

[0265] Among the plurality of auxiliary signal lines Vt40 , the auxiliary signal line Vt40 that may be electrically connected to the third initialization signal line Vt3 is the third auxiliary signal line Vt43 .

[0266] In some embodiments, the plurality of auxiliary signal lines Vt40 may include any one or more of a first auxiliary signal line Vt41 , a second auxiliary signal line Vt42 , and a third auxiliary signal line Vt43 .

[0267] By providing the first auxiliary signal line Vt41 electrically connected to the first initialization signal line Vt1 , the first initialization signal line Vt1 and the first auxiliary signal line Vt41 can be interwoven into a mesh, thereby reducing the impedance of the first initialization signal line Vt1 .

[0268] By providing a second auxiliary signal line Vt42 electrically connected to the second initialization signal line Vt2 , the second initialization signal line Vt2 and the second auxiliary signal line Vt42 can be interwoven into a mesh, thereby reducing the impedance of the second initialization signal line Vt2 .

[0269] By providing a third auxiliary signal line Vt43 electrically connected to the third initialization signal line Vt3 , the third initialization signal line Vt3 and the third auxiliary signal line Vt43 can be interwoven into a mesh, thereby reducing the impedance of the third initialization signal line Vt3 .

[0270] In some embodiments, the first auxiliary signal line Vt41, the second auxiliary signal line Vt42, and the third auxiliary signal line Vt43 may be cyclically arranged along the row direction X. For example, along the row direction X, the first auxiliary signal line Vt41, the second auxiliary signal line Vt42, the third auxiliary signal line Vt43, the first auxiliary signal line Vt41, the second auxiliary signal line Vt42, and the third auxiliary signal line Vt43 are sequentially arranged. . . the first auxiliary signal line Vt41, the second auxiliary signal line Vt42, and the third auxiliary signal line Vt43.

[0271] Among them, by allowing the first auxiliary signal line Vt41, the second auxiliary signal line Vt42 and the third auxiliary signal line Vt43 to be arranged cyclically along the row direction X, the first auxiliary signal line Vt41, the second auxiliary signal line Vt42 and the third auxiliary signal line Vt43 can be designed more regularly, thereby facilitating the production of the array substrate 300.

[0272] Continuing to refer to FIG. 15 , in some embodiments, a row of pixel driving circuits 211 is divided into a plurality of repeating units 201 sequentially arranged along the row direction X, and each repeating unit 201 includes at least one pixel driving circuit 211 .

[0273] The auxiliary signal line Vt40 is located between two adjacent repeating units 201 in the row direction X.

[0274] A row of repeating units 201 are all located in 301 (as shown in FIG. 12 ).

[0275] One or more pixel driving circuits 211 may be provided in a repeating unit 201. For example, the repeating unit 201 includes two pixel driving circuits 211. In this case, the two pixel driving circuits 211 in the repeating unit 201 are symmetrically arranged in the row direction X.

[0276] FIG. 16 is a structural diagram of an array substrate 300 according to some embodiments.

[0277] Please refer to Figure 16. In some embodiments, the array substrate 300 may further include a light-shielding layer 320. The light-shielding layer 320 is located between the substrate 310 and the pixel driving circuit 211. The orthographic projection of the light-shielding layer 320 on the substrate 310 may cover the orthographic projection of the driving transistor T3 (as shown in Figure 14A) on the substrate 310.

[0278] For example, the orthographic projection of the light shielding layer 320 on the substrate 310 can completely cover the orthographic projection of the driving transistor T3 on the substrate 310 . In this case, the orthographic projection of the driving transistor T3 on the substrate 310 can be located in the area covered by the orthographic projection of the light shielding layer 320 on the substrate 310 .

[0279] In some embodiments, the light shielding layer 320 includes a plurality of light shielding portions 321 and a plurality of connecting portions 322 , and the orthographic projections of the light shielding portions 321 on the substrate 310 cover the orthographic projections of the driving transistor T3 on the substrate 310 .

[0280] Two adjacent light shielding portions 321 in the row direction X are connected via a connecting portion 322 ; and / or two adjacent light shielding portions 321 in the column direction Y are connected via a connecting portion 322 .

[0281] The light shielding layer 320 is configured to receive a first voltage signal.

[0282] The light shielding layer 320 receives the first voltage signal, thereby reducing static electricity accumulation in the light shielding layer 320. The connection between two adjacent light shielding portions 321 via the connection portion 322 can reduce the impedance of the light shielding layer 320.

[0283] Next, each film layer of the array substrate 300 is introduced.

[0284] FIG. 17 is a structural diagram of the first active film layer 330 of the array substrate 300 according to some embodiments.

[0285] 17 , the array substrate 300 includes a first active film layer 330. The first active film layer 330 may be used to form active layers of multiple transistors in the pixel driving circuit 211, wherein the active layer of a transistor may include a channel region of the transistor and a first electrode and a second electrode located on both sides of the channel region.

[0286] In some examples, the first active film layer 330 may be made of polysilicon material.

[0287] For example, the first active film layer 330 includes an active layer of the first reset transistor T1, an active layer of the driving transistor T3, an active layer of the data writing transistor T4, an active layer of the first light emission control transistor T5, an active layer of the second light emission control transistor T6, an active layer of the second reset transistor T7 and an active layer of the third reset transistor T8.

[0288] The active layer of the driving transistor T3 may be in a "X" shape. One end of the active layer of the driving transistor T3 is connected to the active layer of the second emission control transistor T6, and the other end is connected to the active layer of the data writing transistor T4 and the active layer of the first emission control transistor T5.

[0289] A portion of the active layer of the data write transistor T4 may extend along the column direction Y, and a portion of the active layer of the first light emission control transistor T5 may extend along the column direction Y.

[0290] One end of the active layer of the second light emitting control transistor T6 away from the active layer of the driving transistor T3 is connected to the active layer of the second reset transistor T7 .

[0291] The active layer of the third reset transistor T8 may be located between the active layer of the second reset transistor T7 and the active layer of the first emission control transistor T5. The X-shaped opening formed by the active layer of the driving transistor T3 may be away from the active layer of the third reset transistor T8.

[0292] An end of the active layer of the second reset transistor T7 away from the active layer of the second light emission control transistor T6 may be located between the active layers of the first reset transistor T1 and the third reset transistor T8 .

[0293] In some examples, the first active film layer 330 may further include an active connection portion 331 , wherein the active connection portion 331 is connected to the active layer of the data writing transistor T4 , the active layer of the first light emission control transistor T5 , and the active layer of the driving transistor T3 .

[0294] FIG18A is a structural diagram of the first active film layer 330 of the array substrate 300 according to some embodiments. In FIG18A , only a partial structure of the repeating unit 201 on the left is shown.

[0295] Referring to FIG. 18A , in some other embodiments, the two first reset transistors T1 in a repeating unit 201 are respectively located at the two ends of the repeating unit 201 in the row direction X. That is, in a repeating unit 201, the first reset transistor T1 in one pixel driving circuit 211 is located in the pixel driving circuit 211 away from the other pixel driving circuit 211. In this case, the first reset transistors T1 in two adjacent repeating units 201 in the row direction X are adjacently arranged.

[0296] The first electrodes s1 of two adjacent first reset transistors T1 in the row direction X can be electrically connected. In this case, the two adjacent first reset transistors T1 in the row direction X share the first electrode s1. This configuration can reduce the width of the pixel driving circuit 211 in the row direction X, which is conducive to high PPI (Pixels Per Inch) design of the display panel.

[0297] The first electrodes s5 of two adjacent first light emission control transistors T5 in the row direction X may be electrically connected.

[0298] Fig. 18B is a diagram showing the stacking of film layers of the array substrate 300 based on the first active film layer 330 in Fig. 18A. It should be noted that in Fig. 18B, only a partial structure of the repeating unit 201 on the left is shown.

[0299] 18B , the first electrode s1 of the first reset transistor T1 is electrically connected to the first initialization signal line Vt1. The array substrate 300 may further include a seventh connecting portion 397. The seventh connecting portion 397 is electrically connected to the first electrodes s1 of the two first reset transistors T1 through vias.

[0300] In some of the above embodiments, the first electrodes s1 of two adjacent first reset transistors T1 in the row direction X may be electrically connected. In this configuration, the first initialization signal line Vt1 may be electrically connected to the first electrodes s1 of the two first reset transistors T1 through a seventh connecting portion 397 .

[0301] FIG. 19 is a structural diagram of a first gate metal layer of an array substrate 300 according to some embodiments.

[0302] Referring to FIG. 19 , the array substrate 300 further includes a first gate metal layer 340 . The first gate metal layer 340 may be located on a side of the first active film layer 330 facing away from the substrate 310 .

[0303] For example, the first gate metal layer 340 may include the second scan signal line GP, the light emission control signal line Em, the first reset signal line Rst-P, the second reset signal line Rst-H, and the first electrode of the capacitor Cst.

[0304] For example, the second scanning signal line GP, the light emitting control signal line Em, the first reset signal line Rst-P, and the second reset signal line Rst-H can be arranged in sequence along the column direction Y, and the first electrode of the capacitor Cst can be located between the second scanning signal line GP and the light emitting control signal line Em.

[0305] FIG. 20 is a structural diagram of a stacked arrangement of a first active film layer 330 and a first gate metal layer 340 according to some embodiments.

[0306] Referring to FIG. 20 , the overlapping portion of the first gate metal layer 340 and the first active film layer 330 may serve as a control electrode of the transistor.

[0307] For example, a portion where the second scan signal line GP overlaps with the channel region of the data writing transistor T4 can be reused as the control electrode g4 of the data writing transistor T4.

[0308] The first electrode of the capacitor Cst is arranged to overlap with the channel region of the driving transistor T3 , so the first electrode of the capacitor Cst can be reused as the control electrode g3 of the driving transistor T3 .

[0309] The part where the light-emitting control signal line Em overlaps with the channel region of the first light-emitting control transistor T5 can be reused as the control electrode g5 of the first light-emitting control transistor T5, and the part where the light-emitting control signal line Em overlaps with the channel region of the second light-emitting control transistor T6 can be reused as the control electrode g6 of the second light-emitting control transistor T6.

[0310] The overlapping portion of the second reset signal line Rst-H and the channel region of the second reset transistor T7 can be reused as the control electrode g7 of the second reset transistor T7, and the overlapping portion of the second reset signal line Rst-H and the channel region of the third reset transistor T8 can be reused as the control electrode g8 of the third reset transistor T8.

[0311] FIG. 21 is a structural diagram of a second gate metal layer of an array substrate 300 according to some embodiments.

[0312] 21 , the second gate metal layer 350 is located on a side of the first gate metal layer 340 facing away from the substrate 310 . The first gate metal layer 340 may include the first scan signal line GN, the second electrode of the capacitor Cst, and the first initialization signal line Vt1 .

[0313] FIG. 22 is a structural diagram showing a stacked arrangement of a first active film layer 330 , a first gate metal layer 340 , and a second gate metal layer 350 according to some embodiments.

[0314] 22 , the second electrode of the capacitor Cst may be overlapped with the first electrode of the capacitor Cst, and a via is provided on the second electrode of the capacitor Cst.

[0315] In some examples, the second gate metal layer 350 may further include an electrode connection portion 351 , and the second electrodes of the capacitors Cst in two adjacent pixel driving circuits 211 in the row direction X may be electrically connected via the electrode connection portion 351 , thereby reducing the impedance of the second electrodes of the capacitors Cst.

[0316] FIG. 23 is a structural diagram of the second active film layer of the array substrate 300 according to some embodiments.

[0317] 23 , the second active film layer 360 may be located on a side of the second gate metal layer 350 facing away from the substrate 310. The second active film layer 330 may include an active layer of the compensation transistor T2. The active layer of the compensation transistor T2 may include a first electrode, a channel region, and a second electrode of the compensation transistor T2.

[0318] For example, the second active film layer 360 may be made of oxide. For example, the second active film layer 330 may be made of IGZO (Indium Gallium Zinc Oxide).

[0319] FIG. 24 is a structural diagram showing a stacked arrangement of a first active film layer 330 , a first gate metal layer 340 , a second gate metal layer 350 , and a second active film layer 360 according to some embodiments.

[0320] 24 , the channel region of the compensation transistor T2 may be overlapped with the second scan signal line GP, wherein the overlapping portion of the second scan signal line GP and the channel region of the compensation transistor T2 may be reused as the control electrode g2 of the compensation transistor T2 .

[0321] FIG. 25 is a structural diagram of a third gate metal layer of the array substrate 300 according to some embodiments.

[0322] 25 , the third gate metal layer 370 is disposed on a side of the second active film layer 360 facing away from the substrate 310 , wherein the third gate metal layer 370 may include a first scan signal line GN, a second initialization signal line Vt2 , and a third initialization signal line Vt3 .

[0323] 26 is a structural diagram of a stacked arrangement of a first active film layer 330 , a first gate metal layer 340 , a second gate metal layer 350 , a second active film layer 360 , and a third gate metal layer 370 according to some embodiments.

[0324] 26 , the overlapping portion of the first scan signal line GN in the third gate metal layer 370 and the active layer of the compensation transistor T2 can serve as the control electrode of the compensation transistor T2 . In this case, the compensation transistor T2 can be a dual-gate transistor.

[0325] The first scan signal line GN in the third gate metal layer 370 may be overlapped with the first scan signal line GN in the first gate metal layer 340 .

[0326] The second initialization signal line Vt2 may be disposed to overlap with the second reset signal line Rst-H, and the third initialization signal line Vt3 may be disposed to overlap with the light emission control signal line Em.

[0327] Figure 27 is a structural diagram of an insulating layer of an array substrate 300 according to some embodiments. Figure 28 is a structural diagram of a stacked arrangement of a first active film layer 330, a first gate metal layer 340, a second gate metal layer 350, a second active film layer 360, a third gate metal layer 370, and an insulating layer 380 according to some embodiments.

[0328] 27 and 28 , the insulating layer 380 is disposed on a side of the third gate metal layer 370 facing away from the substrate 310 . A plurality of via holes 381 are disposed in the insulating layer 380 .

[0329] FIG. 29 is a structural diagram of a first source-drain metal layer of an array substrate 300 according to some embodiments.

[0330] 29 , the first source-drain metal layer 390 is located on a side of the insulating layer 380 facing away from the substrate 310. The first source-drain metal layer 390 includes a first conductive connection portion N11, a second conductive connection portion N22, and a third conductive connection portion N33.

[0331] 30 is a structural diagram of a stacked arrangement of a first active film layer 330 , a first gate metal layer 340 , a second gate metal layer 350 , a second active film layer 360 , a third gate metal layer 370 , an insulating layer 380 and a first source / drain metal layer 390 according to some embodiments.

[0332] 30 , the first conductive connection portion N11 may be electrically connected to the control electrode g3 of the driving transistor T3 (as shown in FIG13 ) and the second electrode d2 of the compensation transistor T2 (as shown in FIG13 ) through a via hole 381 in the insulating layer 380 .

[0333] The second conductive connection portion N22 can be electrically connected to the second electrode d5 of the first light-emitting control transistor T5 and the second electrode d8 of the third reset transistor T8 through the via 381 in the insulating layer 380, and the second electrode d5 of the first light-emitting control transistor T5 can be electrically connected to the second electrode d4 of the data writing transistor T4 and the first electrode s3 of the driving transistor T3 through the active connection portion 331, so that the second conductive connection portion N22 can be electrically connected to the second electrode d4 of the data writing transistor T4 and the second electrode d5 of the first light-emitting control transistor T5, the first electrode s3 of the driving transistor T3 and the second electrode d8 of the third reset transistor T8.

[0334] The third conductive connection portion N33 can be electrically connected to the second electrode d1 of the first reset transistor T1, the second electrode d3 of the driving transistor T3, the first electrode s2 of the compensation transistor T2 and the first electrode s6 of the second light emission control transistor T6 through the via hole 381 in the insulating layer 380.

[0335] In addition, the first source-drain metal layer 390 may include a first transfer portion 391 , a second transfer portion 392 , a third transfer portion 393 , a data transfer portion 394 , a fifth transfer portion 395 and a sixth transfer portion 396 .

[0336] The first transfer portion 391 may be electrically connected to the first initialization signal line Vt1 and the first electrode s1 of the first reset transistor T1 through a via.

[0337] The second transfer portion 392 can be electrically connected to the first electrode s8 of the third reset transistor T8 and the third initialization signal line Vt3 through a via hole, so that the third initialization signal line Vt3 can be electrically connected to the first electrode s8 of the third reset transistor T8.

[0338] The third transition portion 393 can be electrically connected to the second gate metal layer 350 through a via and can also include an electrode connection portion 351 and the first electrode s5 of the first light-emitting control transistor T5. Since the electrode connection portion 351 is electrically connected to the second electrode of the capacitor Cst, the third transition portion 393 can be coupled to the second electrode of the capacitor Cst.

[0339] In some examples, the third transition portion 393 may include a first sub-connection portion 3931 and a second sub-connection portion 3932. The first sub-connection portion 3931 may extend substantially along a first designated direction, wherein the first designated direction is parallel to the substrate 310 and intersects the row direction X and the column direction Y. The second sub-connection portion 3932 is connected to one end of the first sub-connection portion 3931. The orthographic projection of the first sub-connection portion 3931 on the substrate 310 is closer to the orthographic projection of the first scan signal line GN on the substrate 310 than the orthographic projection of the second sub-connection portion 3932 on the substrate 310. The orthographic projection of the first sub-connection portion 3931 on the substrate 310 is closer to the orthographic projection of the third conductive connection portion N33 on the substrate 310 than the orthographic projection of the second sub-connection portion 3932 on the substrate 310.

[0340] For example, the second sub-connection portion 3932 is away from the first sub-connection portion 3931 and can be connected to the first electrode s5 of the first light emission control transistor T5 through a via hole.

[0341] Referring back to FIG. 16 , in some examples, within a repeating unit, the data writing transistors T4 in two pixel driving circuits 211 are adjacent in the row direction X, and the first emission control transistors T5 in the two pixel driving circuits 211 are adjacent in the row direction X. The third adapter portion 393 electrically connected to the first electrodes s5 of the first emission control transistors T5 in the two pixel driving circuits 211 share a second sub-connection portion 3932. In this case, the first sub-connection portion 3931 electrically connected to the first electrodes s5 of the first emission control transistors T5 in the two pixel driving circuits 211 is electrically connected to the same second sub-connection portion 3932. One second sub-connection portion 3932 can be electrically connected to the first electrodes s5 of the first emission control transistors T5 in the two pixel driving circuits 211 within a repeating unit.

[0342] Continuing to refer to FIG. 30 , the data transfer portion 394 may be electrically connected to the first electrode s4 of the data writing transistor T4 through a via.

[0343] The fifth transfer portion 395 can be electrically connected to the first electrode s7 of the second reset transistor T7 and the second initialization signal line Vt2 through a via hole, so that the second initialization signal line Vt2 can be electrically connected to the first electrode s7 of the second reset transistor T7.

[0344] The sixth adapter 396 can be electrically connected to the second electrode d6 of the second light-emitting control transistor T6 and the second electrode d7 of the second reset transistor T7 through a via hole. The sixth adapter 396 can also be electrically connected to the light-emitting device 212. Thus, the light-emitting device 212 can be electrically connected to the second electrode d6 of the second light-emitting control transistor T6 and the second electrode d7 of the second reset transistor T7 through the sixth adapter 396.

[0345] Please refer to Figure 15 again. In some embodiments, the first source-drain metal layer 390 may further include multiple auxiliary signal lines Vt40. For example, the multiple auxiliary signal lines Vt40 may include any one or more of the first auxiliary signal line Vt41, the second auxiliary signal line Vt42 and the third auxiliary signal line Vt43.

[0346] Figure 31 is a structural diagram of a second source-drain metal layer of an array substrate 300 according to some embodiments. Figure 32 is a structural diagram of a stacked arrangement of a first active film layer 330, a first gate metal layer 340, a second gate metal layer 350, a second active film layer 360, a third gate metal layer 370, an insulating layer 380, a first source-drain metal layer 390, and a second source-drain metal layer according to some embodiments.

[0347] Referring to FIG. 31 , the second source / drain metal layer 410 is located on a side of the first source / drain metal layer 390 facing away from the substrate 310. The second source / drain metal layer 410 may include a first power signal line VDD and a data line DT. The first power signal line VDD may be electrically connected to a third transfer portion 393, which in turn is electrically connected to the first electrode s5 of the first emission control transistor T5 and the second electrode of the capacitor Cst. Consequently, the first power signal line VDD may provide a first power signal to the second electrode of the capacitor Cst and the first electrode s5 of the first emission control transistor T5 via the third transfer portion 393.

[0348] For example, the first power signal line VDD may be connected to an end of the first sub-connection portion 3931 away from the second sub-connection portion 3932 through a via hole.

[0349] The data line DT may be electrically connected to the data transfer portion 394 , so that the data line DT may provide a data signal to the first electrode s4 of the data writing transistor T4 through the data transfer portion 394 .

[0350] In the present disclosure, a display panel using the array substrate 300 shown in FIG31 was tested. The test showed that the capacitance between the second conductive connection portion N22 and the first scan signal line GN was 0, while the capacitance between the third conductive connection portion N33 and the first scan signal line was 2.859 fF.

[0351] In the related art, the capacitance between the second conductive connection portion N22 and the first scan signal line GN is 1.829 fF, and the capacitance between the third conductive connection portion N33 and the first scan signal line is 3.340 fF.

[0352] By comparison, it can be seen that compared with the related art, the present disclosure can effectively reduce the capacitance between the second conductive connection portion N22 and the first scan signal line GN, and the capacitance between the third conductive connection portion N33 and the first scan signal line.

[0353] In some of the above embodiments, the film layer structure of the “8T1C” pixel driving circuit is introduced. In other embodiments, the “8T1C” pixel driving circuit may also have different film layer structures, which are not introduced one by one here.

[0354] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that a person skilled in the art can conceive within the technical scope disclosed in the present disclosure should be included within the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. An array substrate, comprising: substrate; A plurality of pixel driving circuits are located on one side of the substrate and arranged in multiple rows and columns; A pixel driving circuit comprises a compensation transistor, a driving transistor and a first conductive connection portion, wherein a control electrode of the driving transistor and a second electrode of the compensation transistor are both electrically connected to the first conductive connection portion; A plurality of first scanning signal lines are located on one side of the substrate, the plurality of first scanning signal lines are extended along a row direction and are arranged in sequence along a column direction, the row direction and the column direction are parallel to the substrate and are arranged crosswise; one first scanning signal line is electrically connected to a control electrode of the compensation transistor of a row of pixel driving circuits; The first conductive connection portion and the first scanning signal line do not overlap in a direction perpendicular to the substrate.

2. The array substrate according to claim 1, wherein: The pixel driving circuit further includes: a data writing transistor and a first light emission control transistor, wherein the second electrode of the data writing transistor is electrically connected to the first electrode of the driving transistor and the second electrode of the first light emission control transistor; The array substrate further comprises: a plurality of second scanning signal lines and a plurality of light emitting control signal lines, which are located on one side of the substrate; the plurality of second scanning signal lines all extend along the row direction and are sequentially arranged along the column direction, and one second scanning signal line is electrically connected to a control electrode of a data writing transistor of a row of pixel driving circuits; the plurality of light emitting control signal lines all extend along the row direction and are sequentially arranged along the column direction, and one light emitting control signal line is electrically connected to a control electrode of the first light emitting control transistor of a row of pixel driving circuits; The array substrate further comprises: a plurality of row pixel regions, the plurality of row pixel regions extending along the row direction and arranged in sequence along the column direction; a row pixel driving circuit is arranged in one row pixel region, and the first scanning signal line, the second scanning signal line and the light emitting control signal line electrically connected to the row pixel driving circuit are located in the row pixel region where the row pixel driving circuit is located; Among them, in one of the row pixel areas: the orthographic projection of the first scanning signal on the substrate is located on a side of the orthographic projection of the second scanning signal line on the substrate away from the orthographic projection of the light emitting control signal line on the substrate, and the orthographic projection of the driving transistor on the substrate is located between the orthographic projection of the second scanning signal line on the substrate and the orthographic projection of the light emitting control signal line on the substrate.

3. The array substrate according to claim 2, wherein: In one of the row pixel areas, the compensation transistor and the first conductive connection portion are arranged in sequence along the column direction; wherein the compensation transistor passes through the first scanning signal line, and the orthographic projection of the second electrode of the compensation transistor on the substrate is located on a side where the orthographic projection of the first scanning signal line on the substrate is close to the orthographic projection of the light-emitting control signal line on the substrate, and the first conductive connection portion is located on a side of the first scanning signal line close to the light-emitting control signal line.

4. The array substrate according to claim 3, wherein: In one of the row pixel areas, a portion of the orthographic projection of the data write transistor on the substrate is arranged opposite to the orthographic projection of the compensation transistor on the substrate in the row direction, and another portion of the orthographic projection of the data write transistor on the substrate is arranged opposite to the orthographic projection of the first conductive connection portion on the substrate in the row direction.

5. The array substrate according to claim 4, wherein: The data writing transistor passes through the second scanning signal line, and the data writing transistor is located on a side of the first scanning signal line close to the light emitting control signal line; The array substrate further includes: A plurality of data transfer parts, wherein the plurality of data transfer parts are located at a side of the plurality of pixel driving circuits away from the substrate; a plurality of data lines, the plurality of data lines being located on a side of the plurality of data transfer portions away from the substrate, the plurality of data lines extending along the column direction and arranged in sequence along the row direction, one data line being electrically connected to a first electrode of a data writing transistor of a row of pixel driving circuits through one data transfer portion; Among them, in one of the row pixel regions, the orthographic projection of the data transfer portion on the substrate is located between the orthographic projection of the first scanning signal line on the substrate and the orthographic projection of the second scanning signal line on the substrate.

6. The array substrate according to any one of claims 3 to 5, wherein: In one of the row pixel regions, a portion of the orthographic projection of the first conductive connection portion on the substrate overlaps with a portion of the orthographic projection of the compensation transistor on the substrate, and another portion of the orthographic projection of the first conductive connection portion on the substrate overlaps with a portion of the orthographic projection of the driving transistor on the substrate.

7. The array substrate according to any one of claims 2 to 6, wherein: The pixel driving circuit further includes a second conductive connection portion, the second conductive connection portion being electrically connected to a first electrode of the driving transistor, a second electrode of the first light emitting control transistor, and a second electrode of the data writing transistor; An orthographic projection of the second conductive connection portion on the substrate does not overlap with an orthographic projection of the first scan signal line on the substrate.

8. The array substrate according to claim 7, wherein: The pixel driving circuit further includes: a third reset transistor, a second electrode of the third reset transistor being electrically connected to the second conductive connection portion; The array substrate further comprises: a plurality of second reset signal lines, the plurality of second reset signal lines are located at a side of the plurality of pixel driving circuits away from the substrate, the plurality of second reset signal lines all extend along the row direction, and are sequentially arranged along the column direction; one of the second reset signal lines is electrically connected to a control electrode of a third reset transistor of a row of pixel driving circuits; the second reset signal line electrically connected to a row of pixel driving circuits is located in a row pixel region where the row of pixel driving circuits is located; Wherein, in one of the row pixel regions: the second reset signal line is located at a side of the light emitting control signal line away from the first scanning signal line.

9. The array substrate according to claim 8, wherein: Also includes: A plurality of third initialization signal lines are located on one side of the substrate; the plurality of third initialization signal lines extend along the row direction and are sequentially arranged along the column direction, and one third initialization signal line is electrically connected to a first electrode of a third reset transistor of a row of pixel driving circuits; In one of the row pixel regions: an orthographic projection of the third initialization signal line on the substrate at least partially overlaps with an orthographic projection of the light emitting control signal line on the substrate.

10. The array substrate according to claim 9, wherein: In one of the row pixel regions: the third reset transistor passes through the second reset signal line and is located on a side of the third initialization signal line away from the light emitting control signal line; wherein the orthographic projection of the first electrode of the third reset transistor on the substrate is located between the orthographic projection of the third initialization signal line on the substrate and the orthographic projection of the second reset signal line on the substrate, and the orthographic projection of the second electrode of the third reset transistor on the substrate is located on a side of the orthographic projection of the second reset signal line on the substrate away from the orthographic projection of the third initialization signal line on the substrate; The second conductive connection portion crosses the third initialization signal line, the light emission control signal line, and the second reset signal line, and is electrically connected to a second electrode of the third reset transistor.

11. The array substrate according to claim 10, wherein: The orthographic projection of the second conductive connection portion on the substrate overlaps with the orthographic projections of the second electrode, the control electrode, and part of the first electrode of the third reset transistor on the substrate.

12. The array substrate according to any one of claims 9 to 11, wherein: The pixel driving circuit further includes a second light-emitting control transistor and a second reset transistor; a first electrode of the second light-emitting control transistor is electrically connected to the second electrode of the driving transistor and the first electrode of the compensation transistor, and a second electrode of the second light-emitting control transistor is electrically connected to the light-emitting device and the second electrode of the second reset transistor; wherein the control electrode of the second light-emitting control transistor of a row of pixel driving circuits is electrically connected to one of the light-emitting control signal lines, and the control electrode of the second reset transistor of a row of pixel driving circuits is electrically connected to one of the second reset signal lines; The array substrate further comprises: a plurality of second initialization signal lines, the plurality of second initialization signal lines are located on a side of the plurality of pixel driving circuits away from the substrate, the plurality of second initialization signal lines extend along the row direction, and are sequentially arranged along the column direction; one second initialization signal line is electrically connected to a first electrode of a second reset transistor of a row of pixel driving circuits; Wherein, in one of the row pixel regions: the orthographic projection of the second initialization signal line on the substrate is located on a side where the orthographic projection of the second reset signal line on the substrate is away from the orthographic projection of the first scanning signal line on the substrate.

13. The array substrate according to claim 12, wherein: The pixel driving circuit further includes: a first reset transistor and a third conductive connection portion, wherein the third conductive connection portion is electrically connected to the second electrode of the first reset transistor, the second electrode of the driving transistor and the first electrode of the compensation transistor; The array substrate further comprises: a plurality of first reset signal lines, the plurality of first reset signal lines being located on a side of the plurality of pixel driving circuits away from the substrate; the plurality of first reset signal lines all extend along the row direction and are sequentially arranged along the column direction, and one first reset signal line is electrically connected to a control electrode of a first reset transistor of a row of pixel driving circuits; Wherein, in the row pixel area, the orthographic projection of the first reset signal line on the substrate is located on a side where the orthographic projection of the light emitting control signal line on the substrate is away from the orthographic projection of the first scanning signal line on the substrate.

14. The array substrate according to claim 13, wherein: Also includes: a plurality of first initialization signal lines, located at a side of the plurality of pixel driving circuits away from the substrate, the plurality of first initialization signal lines all extending along the row direction and arranged in sequence along the column direction, one first initialization signal line being electrically connected to a first electrode of a first reset transistor of a row of pixel driving circuits; Wherein, in the row pixel area, the first initialization signal line is located on a side of the first reset signal line away from the first scanning signal line.

15. The array substrate according to claim 14, wherein: The first reset transistor passes through the first reset signal line, the orthographic projection of the first electrode of the first reset transistor on the substrate is located between the orthographic projection of the first reset signal line on the substrate and the orthographic projection of the first initialization signal line on the substrate, and the orthographic projection of the second electrode of the first reset transistor on the substrate is located between the orthographic projection of the first reset signal line on the substrate and the orthographic projection of the second reset signal line on the substrate.

16. The array substrate according to claim 14 or 15, wherein: An orthographic projection of the first reset signal line on the substrate overlaps with an orthographic projection of the second initialization signal line on the substrate.

17. The array substrate according to any one of claims 14 to 16, wherein: Also includes: A plurality of auxiliary signal lines are located on one side of the substrate, the plurality of auxiliary signal lines all extend along the column direction and are sequentially arranged along the row direction; Wherein, an auxiliary signal line is electrically connected to any one of the first initialization signal line, the second initialization signal line and the third initialization signal line.

18. The array substrate according to claim 17, wherein: A row of pixel driving circuits is divided into a plurality of repeating units arranged in sequence along the row direction, and one of the repeating units includes at least one of the pixel driving circuits; The auxiliary signal line is located between two adjacent repeating units in the row direction.

19. The array substrate according to claim 18, wherein: The repeating unit includes two pixel driving circuits, and the two pixel driving circuits in one repeating unit are symmetrically arranged in the row direction.

20. The array substrate according to any one of claims 17 to 19, wherein: The plurality of auxiliary signal lines include a first auxiliary signal line, a second auxiliary signal line and a third auxiliary signal line, the first auxiliary signal line is electrically connected to the first initialization signal line, the second auxiliary signal line is electrically connected to the second initialization signal line, and the third auxiliary signal line is electrically connected to the third initialization signal line.

21. A display panel, comprising: The array substrate according to any one of claims 1 to 20; A light emitting device layer, located on a side of the array substrate away from the substrate; The encapsulation layer is located on a side of the light emitting device layer away from the array substrate.

22. A display device, comprising: The display panel as claimed in claim 21; The driving chip is electrically connected to the display panel.

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