Display substrate and manufacturing method therefor, and display device

Abstract

A display substrate and a manufacturing method therefor, and a display device. The display substrate comprises a driving structure layer and a light-emitting structure layer which are arranged on a substrate; the driving structure layer comprises a plurality of circuit units, and each circuit unit comprises a pixel driving circuit; the light-emitting structure layer comprises a plurality of light-emitting units, each light-emitting unit comprises an anode and a pixel definition layer, the anode is connected to the pixel driving circuit of the corresponding circuit unit, and the pixel definition layer is provided with a pixel opening exposing the anode; the driving structure layer further comprises at least two signal lines extending in a first direction, the orthographic projection of the pixel opening on the substrate at least partially overlaps the orthographic projection of the at least two signal lines on the substrate, the at least two signal lines are respectively located on two sides of the geometric center of the pixel opening in a second direction, and the first direction intersects with the second direction.

Description

Display substrate and manufacturing method thereof, and display device

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on June 21, 2023, with application number 202310745478.6 and invention name “Display substrate, preparation method thereof, and display device”, the contents of which should be understood as incorporated into this application by reference. Technical Field

[0002] This article relates to but is not limited to the field of display technology, and specifically to a display substrate and a preparation method thereof, and a display device. Background Art

[0003] Organic Light Emitting Diodes (OLEDs) and Quantum-dot Light Emitting Diodes (QLEDs) are active light-emitting display devices with advantages such as self-luminescence, wide viewing angles, high contrast, low power consumption, extremely fast response times, thinness, flexibility, and low cost. With the continuous advancement of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and thin-film transistors (TFTs) for signal control have become mainstream products in the display field.

[0004] Summary of the Invention

[0005] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0006] On the one hand, the present disclosure provides a display substrate, comprising a driving structure layer arranged on a substrate and a light-emitting structure layer arranged on a side of the driving structure layer away from the substrate; the driving structure layer comprises a plurality of circuit units, at least one circuit unit comprising a pixel driving circuit; the light-emitting structure layer comprises a plurality of light-emitting units, at least one light-emitting unit comprising an anode and a pixel definition layer arranged on a side of the anode away from the substrate, the anode being connected to the pixel driving circuit of the corresponding circuit unit, and the pixel definition layer being provided with a pixel opening exposing the anode; the driving structure layer further comprises at least two signal lines extending along a first direction, in at least one pixel opening, the positive projection of the pixel opening on the substrate at least partially overlaps with the positive projection of at least two signal lines on the substrate, and at least two signal lines are respectively located on both sides of the geometric center of the pixel opening in a second direction, and the first direction and the second direction intersect.

[0007] In an exemplary embodiment, at least two signal lines include a first connection line and a power connection line, the power connection line is connected to the data signal line extending along the second direction, the power connection line is connected to the first power line extending along the second direction, and the data signal line and the first power line are connected to the pixel driving circuit; in at least one pixel opening, the first connection line and the power connection line are symmetrically arranged with respect to a center line, and the center line is a straight line extending along the first direction and passing through the geometric center of the pixel opening.

[0008] In an exemplary embodiment, in at least one pixel opening, the pixel opening includes a first end portion located on a side of the power connection line away from the center line and a second end portion located on a side of the first connection line away from the center line, the power connection line includes a first edge on a side away from the center line, the first connection line includes a second edge on a side away from the center line, a first distance is between the first end portion and the first edge, a second distance is between the second end portion and the second edge, and a ratio of the first distance to the second distance is 0.9 to 1.1.

[0009] In an exemplary embodiment, the driving structure layer further includes a second connecting line extending along the second direction, the second connecting line being connected to the first connecting line, and in at least one pixel opening, the orthographic projection of the second connecting line on the substrate at least partially overlaps with the orthographic projection of the geometric center of the pixel opening on the substrate.

[0010] In an exemplary embodiment, an orthographic projection of the pixel opening on the substrate at least partially overlaps with an orthographic projection of two data signal lines on the substrate, the second connection line is disposed between the two data signal lines, and the two data signal lines are symmetrically disposed relative to the second connection line.

[0011] In an exemplary embodiment, an orthographic projection of the pixel opening on the substrate at least partially overlaps with an orthographic projection of two first power lines on the substrate, the second connecting line and the two data signal lines are arranged between the two first power lines, and the two first power lines are symmetrically arranged with respect to the second connecting line.

[0012] In an exemplary embodiment, the driving structure layer further includes a plurality of power connection lines extending along the first direction and a plurality of first power lines extending along the second direction, wherein the power connection lines and the first power lines are connected to form a grid connection structure for transmitting the first power signal.

[0013] In an exemplary embodiment, on a plane perpendicular to the display substrate, the driving structure layer includes a plurality of conductive layers sequentially disposed on the base, and the power connection line and the first power line are disposed in different conductive layers.

[0014] In an exemplary embodiment, the at least two signal lines include a first connection line and the power connection line, and the power connection line and the first connection line are provided in the same conductive layer.

[0015] In an exemplary embodiment, the driving structure layer further includes a second connection line connected to the first connection line, the first connection line is connected to a data signal line, and the data signal line, the first power line and the second connection line are arranged in the same conductive layer.

[0016] In an exemplary embodiment, the plurality of light-emitting units include a red light-emitting unit that emits red light, a blue light-emitting unit that emits blue light, a first green light-emitting unit that emits green light, and a second green light-emitting unit that emits green light, the red light-emitting unit includes at least a first anode and a first pixel opening exposing the first anode, the blue light-emitting unit includes at least a second anode and a second pixel opening exposing the second anode, the first green light-emitting unit includes at least a third anode and a third pixel opening exposing the third anode, and the second green light-emitting unit includes at least a fourth anode and a fourth pixel opening exposing the fourth anode; at least one of the first pixel opening and the second pixel opening, and the at least two signal lines are respectively located on both sides of the second direction of the geometric center of the pixel opening.

[0017] In an exemplary embodiment, the driving structure layer further includes a plurality of anode spacers, and at least one of the third pixel opening and the fourth pixel opening has an orthographic projection on the substrate at least partially overlapping with an orthographic projection of the anode spacer on the substrate.

[0018] In an exemplary embodiment, at least one of the third pixel opening and the fourth pixel opening has an orthographic projection on the substrate located within a range of an orthographic projection of the anode spacer on the substrate.

[0019] In an exemplary embodiment, the driving structure layer further includes a first power line, and the anode spacer is connected to the first power line.

[0020] On the other hand, the present disclosure further provides a display device comprising the aforementioned display substrate.

[0021] In another aspect, the present disclosure further provides a method for preparing a display substrate, comprising:

[0022] forming a driving structure layer on a substrate, wherein the driving structure layer includes a plurality of circuit units and at least two signal lines extending along a first direction, and at least one circuit unit includes a pixel driving circuit;

[0023] forming a light-emitting structure layer on the driving structure layer, the light-emitting structure layer including a plurality of light-emitting units, at least one of which includes an anode and a pixel definition layer disposed on a side of the anode away from the substrate, the anode being connected to a pixel driving circuit of a corresponding circuit unit, and the pixel definition layer being provided with a pixel opening exposing the anode;

[0024] The driving structure layer also includes at least two signal lines extending along a first direction. In at least one pixel opening, the positive projection of the pixel opening on the substrate at least partially overlaps with the positive projection of at least two signal lines on the substrate. The at least two signal lines are respectively located on both sides of the geometric center of the pixel opening in a second direction, and the first direction and the second direction intersect.

[0025] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The accompanying drawings are used to provide an understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation to the technical solution of the present disclosure.

[0027] FIG1 is a schematic structural diagram of a display device;

[0028] FIG2 is a schematic structural diagram of a display substrate;

[0029] FIG3 is a schematic diagram of a planar structure of a display area in a display substrate;

[0030] FIG4 is a schematic diagram of a cross-sectional structure of a display area in a display substrate;

[0031] FIG5 is a schematic diagram of an equivalent circuit of a pixel driving circuit;

[0032] FIG6 is a schematic diagram of a planar structure of a display substrate according to an exemplary embodiment of the present disclosure;

[0033] FIG7 is a schematic diagram of an embodiment of the present disclosure after forming a shielding layer pattern;

[0034] 8A and 8B are schematic diagrams of an embodiment of the present disclosure after forming a first semiconductor layer pattern;

[0035] 9A and 9B are schematic diagrams of an embodiment of the present disclosure after forming a first conductive layer pattern;

[0036] 10A and 10B are schematic diagrams of an embodiment of the present disclosure after forming a second conductive layer pattern;

[0037] 11A and 11B are schematic diagrams of an embodiment of the present disclosure after forming a second semiconductor layer pattern;

[0038] 12A and 12B are schematic diagrams of an embodiment of the present disclosure after forming a third conductive layer pattern;

[0039] FIG13 is a schematic diagram of an embodiment of the present disclosure after forming a sixth insulating layer pattern;

[0040] 14A and 14B are schematic diagrams of an embodiment of the present disclosure after forming a fourth conductive layer pattern;

[0041] FIG15 is a schematic diagram of an embodiment of the present disclosure after forming a first planar layer pattern;

[0042] 16A and 16B are schematic diagrams of an embodiment of the present disclosure after forming a fifth conductive layer pattern;

[0043] FIG17 is a schematic diagram of an embodiment of the present disclosure after forming a second planar layer pattern;

[0044] 18A and 18B are schematic diagrams of an embodiment of the present disclosure after forming a sixth conductive layer pattern;

[0045] FIG19 is a schematic diagram of an embodiment of the present disclosure after forming a third planar layer pattern;

[0046] FIG20 is a schematic diagram of an embodiment of the present disclosure after forming an anode conductive layer pattern;

[0047] FIG21 is a schematic diagram of an embodiment of the present disclosure after forming a pixel definition layer pattern;

[0048] FIG. 22 is a schematic diagram showing the positional relationship between pixel openings and signal lines of the present disclosure.

[0049] Explanation of Reference Numerals: 11—first active layer; 12—second active layer; 13—third active layer; 14—fourth active layer; 15—fifth active layer; 16—sixth active layer; 17—seventh active layer; 18—eighth active layer; 21—first scanning signal line; 22—second scanning signal line; 23—third scanning signal line; 24—light-emitting signal line; 25—first electrode plate; 31—shielding line; 32—second electrode plate; 33—opening; 34—first connecting bar; 35—second connecting bar; 41—first initial signal line; 42—second initial signal line; 43—third initial signal line; 44—fourth scanning signal line; 51—first connecting electrode; 52—second connecting electrode; 53—third connecting electrode; 54—fourth connecting electrode; 55—fifth connecting electrode; 56—sixth connecting electrode; 57—seventh connecting electrode; 58—eighth connecting electrode; 59—ninth connecting electrode; 61—eleventh connecting electrode; 62—twelfth connecting electrode; 63—power connection line; 64—first shielding electrode; 65—second shielding electrode; 71—first power line; 72—data signal line; 73—anode connection electrode; 81—first connection line; 82—second connection line; 90A—first anode; 90B—second anode; 90C—third anode; 90D—fourth anode; 91—first shielding connection line; 92—second shielding connection line; 93—third shielding connection line; 94—shielding electrode; 100—display area; 100A—first pixel opening; 100B—second pixel opening; 100C—third pixel opening; 100D—fourth pixel opening; 101—substrate; 102—driving circuit layer;103—light-emitting structure layer; 104—encapsulation structure layer; 200—binding area; 210—data lead line; 300—frame area. DETAILED DESCRIPTION

[0050] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Note that the embodiments can be implemented in a variety of different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other.

[0051] The scales of the figures in this disclosure can be used as a reference for actual processes, but are not limited to such. For example, the width-to-length ratio of the channel, the thickness and spacing of the various film layers, and the width and spacing of the various signal lines can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The figures described in this disclosure are merely schematic structural diagrams, and one embodiment of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0052] In this specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0053] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced according to the circumstances.

[0054] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure.

[0055] In this specification, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0056] In this specification, the first electrode can be a drain electrode and the second electrode can be a source electrode, or vice versa. The functions of "source electrode" and "drain electrode" may be interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, "source electrode" and "drain electrode" can be interchanged, and "source terminal" and "drain terminal" can be interchanged.

[0057] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0058] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0059] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0060] The triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0061] The term "about" in the present disclosure refers to a numerical value that is not strictly defined and allows for process and measurement errors.

[0062] FIG1 is a schematic diagram of the structure of a display device. As shown in FIG1 , the display device may include a timing controller, a data driver, a scan driver, a light-emitting driver, and a pixel array. The timing controller is respectively connected to the data driver, the scan driver, and the light-emitting driver. The data driver is respectively connected to a plurality of data signal lines (D1 to Dn). The scan driver is respectively connected to a plurality of scan signal lines (S1 to Sm). The light-emitting driver is respectively connected to a plurality of light-emitting signal lines (E1 to Eo). The pixel array may include a plurality of sub-pixels Pxij, where i and j may be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light-emitting unit. The circuit unit may include at least a pixel driving circuit, which is respectively connected to the scan signal lines, the light-emitting signal lines, and the data signal lines. The light-emitting unit may include a light-emitting device, which is connected to the pixel driving circuit of the circuit unit. In an exemplary embodiment, the timing controller may provide grayscale values ​​and control signals suitable for the specifications of the data driver to the data driver, may provide clock signals, scan start signals, etc. suitable for the specifications of the scan driver to the scan driver, and may provide clock signals, emission stop signals, etc. suitable for the specifications of the light-emitting driver to the light-emitting driver. The data driver can generate data voltages to be supplied to the data signal lines DATA1, D2, D3, ..., and Dn using grayscale values ​​and control signals received from the timing controller. For example, the data driver can sample grayscale values ​​using a clock signal and apply data voltages corresponding to the grayscale values ​​to the data signal lines DATA1 to Dn on a pixel row basis, where n can be a natural number. The scan driver can generate scan signals to be supplied to the scan signal lines S1, S2, S3, ..., and Sm by receiving clock signals, scan start signals, and the like from the timing controller. For example, the scan driver can sequentially supply scan signals having on-level pulses to the scan signal lines S1 to Sm. For example, the scan driver can be configured as a shift register and can sequentially transmit the scan start signals provided in the form of on-level pulses to the next stage circuit under the control of a clock signal, where m can be a natural number. The emission driver can generate emission signals to be supplied to the emission signal lines EM1, E2, E3, ..., and Eo by receiving clock signals, emission stop signals, and the like from the timing controller. For example, the light emitting driver may sequentially provide emission signals having off-level pulses to the light emitting signal lines EM1 to Eo. For example, the light emitting driver may be configured as a shift register and may generate emission signals by sequentially transmitting emission stop signals provided in the form of off-level pulses to the next stage circuit under the control of a clock signal. o may be a natural number. In an exemplary embodiment, the pixel array may be provided on a display substrate.

[0063] Figure 2 is a schematic diagram of the structure of a display substrate. As shown in Figure 2, the display substrate may include a display area 100, a binding area 200 located on one side of the display area 100, and a border area 300 located on the other side of the display area 100. In an exemplary embodiment, the display area 100 may be a flat area including a plurality of sub-pixels forming a pixel array. The plurality of sub-pixels are configured to display dynamic or still images. The display area 100 may be referred to as an active area (AA). In an exemplary embodiment, the display substrate may be a flexible substrate, and thus the display substrate may be deformable, such as being curled, bent, folded, or rolled.

[0064] In an exemplary embodiment, the binding area 200 may include a fan-out area, a bending area, a driver chip area, and a binding pin area arranged in sequence along a direction away from the display area 100. The fan-out area is connected to the display area 100 and may include at least a plurality of data lead-out lines parallel to each other. The bending area is connected to the fan-out area and may include a composite insulating layer provided with a groove, which is configured to bend the binding area to the back of the display area. The driver chip area may include at least an integrated circuit (IC) configured to be connected to a plurality of data fan-out lines. The binding pin area may include at least a plurality of bonding pads configured to be bound and connected to an external flexible printed circuit (FPC).

[0065] In an exemplary embodiment, the frame area 300 may include a circuit area, a power line area, a crack dam area, and a cutting area, which are sequentially arranged in a direction away from the display area 100. The circuit area is connected to the display area 100 and may include at least a gate drive circuit, which is connected to the scanning signal line and the light-emitting signal line of the pixel drive circuit in the display area 100. The power line area is connected to the circuit area and may include at least a frame power lead, which extends in a direction parallel to the edge of the display area and is connected to the cathode in the display area 100. The crack dam area is connected to the power line area and may include at least a plurality of cracks provided on the composite insulating layer. The cutting area is connected to the crack dam area and may include at least a cutting groove provided on the composite insulating layer. The cutting groove is configured so that after all film layers of the display substrate are prepared, the cutting equipment can cut along the cutting groove respectively.

[0066] In an exemplary embodiment, the fan-out area in the binding area 200 and the power line area in the border area 300 may be provided with at least one isolation dam, and the isolation dam may extend in a direction parallel to the edge of the display area to form a ring structure surrounding the display area 100. The edge of the display area is the edge of the display area close to the binding area or the border area.

[0067] In an exemplary embodiment, the display area 100 further includes a plurality of data signal lines 72 extending along the second direction Y, a plurality of first connection lines 81 extending along the first direction X, and a plurality of second connection lines 82 extending along the second direction Y. The data signal lines 72 are respectively connected to the plurality of pixel driving circuits in a pixel column, and the data signal lines 72 are configured to provide data signals to the connected pixel driving circuits. The first ends of the plurality of first connection lines 81 are connected to the plurality of data signal lines 72, the second ends of the plurality of first connection lines 81 are connected to the first ends of the plurality of second connection lines 82, and the second ends of the plurality of second connection lines 82 are connected to the first ends of the plurality of data lead lines 210 in the binding area 200. The second ends of the plurality of data lead lines 210 extend along the second direction Y, cross the bend area, and are connected to the driver chip in the driver chip area. The driver chip applies the data signal provided by the driver chip to the data signal lines 72 via the data lead lines 210, the first connection lines 81, and the second connection lines 82. In an exemplary embodiment, the first connection line 81 and the second connection line 82 can constitute a data connection line, forming a data connection line located in the display area (Fanout in AA, abbreviated as FIAA) structure. Since the data connection line is set in the display area, the width of the bottom frame can be reduced, and the screen ratio can be increased.

[0068] FIG3 is a schematic diagram of a planar structure of a display area in a display substrate. As shown in FIG2 , the display substrate may include a plurality of pixel units P arranged in a matrix, and at least one pixel unit P may include a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, a third sub-pixel P3 emitting a third color light, and a fourth sub-pixel P4 emitting a third color light. Each sub-pixel may include a circuit unit and a light-emitting unit. The circuit unit may include at least a pixel driving circuit. The pixel driving circuit is respectively connected to a scan signal line, a data signal line, and a light-emitting signal line. The pixel driving circuit is configured to receive a data voltage transmitted by the data signal line under the control of the scan signal line and the light-emitting signal line, and output a corresponding current to the light-emitting unit. The light-emitting unit in each sub-pixel is respectively connected to the pixel driving circuit of the sub-pixel in which it is located. The light-emitting unit is configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel in which it is located.

[0069] In an exemplary embodiment, the first sub-pixel P1 may be a red sub-pixel (R) that emits red light, the second sub-pixel P2 may be a blue sub-pixel (B) that emits blue light, and the third sub-pixel P3 and the fourth sub-pixel P4 may be green sub-pixels (G) that emit green light. In an exemplary embodiment, the sub-pixels may be rectangular, rhombus, pentagonal, or hexagonal, and the four sub-pixels may be arranged in a diamond shape to form an RGBG pixel arrangement. In other exemplary embodiments, the four sub-pixels may be arranged horizontally, vertically, or in a square, etc., which is not limited in this disclosure.

[0070] In an exemplary embodiment, a pixel unit may include three sub-pixels, and the three sub-pixels may be arranged in a horizontal parallel arrangement, a vertical parallel arrangement, or a triangular arrangement, which is not limited in the present disclosure.

[0071] Figure 4 is a schematic cross-sectional view of the display region of a display substrate, illustrating the structure of four sub-pixels in the display region. As shown in Figure 3, in a plane perpendicular to the display substrate, the display substrate may include a drive circuit layer 102 disposed on a substrate 101, a light-emitting structure layer 103 disposed on a side of the drive circuit layer 102 away from the substrate 101, and an encapsulation structure layer 104 disposed on a side of the light-emitting structure layer 103 away from the substrate 101. In some possible implementations, the display substrate may include other film layers, such as a touch structure layer, etc., which are not limited in this disclosure.

[0072] In an exemplary embodiment, the substrate 101 may be a flexible substrate or a rigid substrate. The driving circuit layer 102 may include a plurality of circuit units, each of which may include at least a pixel driving circuit composed of a plurality of transistors and a storage capacitor. The light-emitting structure layer 103 may include a plurality of light-emitting units, each of which may include at least an anode, a pixel definition layer, an organic light-emitting layer and a cathode, the anode being connected to the pixel driving circuit, the organic light-emitting layer being connected to the anode, and the cathode being connected to the organic light-emitting layer, and the organic light-emitting layer emitting light of corresponding colors under the drive of the anode and the cathode. The encapsulation structure layer 104 may include a first encapsulation layer, a second encapsulation layer and a third encapsulation layer stacked together, the first encapsulation layer and the third encapsulation layer may be made of inorganic materials, the second encapsulation layer may be made of organic materials, and the second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer to form an inorganic material / organic material / inorganic material laminated structure, which can ensure that external water vapor cannot enter the light-emitting structure layer 103.

[0073] FIG5 is a schematic diagram of an equivalent circuit of a pixel driving circuit. In an exemplary embodiment, the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. As shown in FIG5 , the pixel driving circuit may include 8 transistors (a first transistor T1 to an eighth transistor T8) and a storage capacitor C. The pixel driving circuit is respectively connected to 10 signal lines (a first scan signal line S1, a second scan signal line S2, a third scan signal line S3, a fourth scan signal line S4, an emission signal line EM, a first initial signal line INIT1, a second initial signal line INIT2, a third initial signal line INIT3, a data signal line DATA, and a first power line VDD).

[0074] In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, a third node N3, and a fourth node N4. The first node N1 is connected to the first electrode of the second transistor T2, the gate electrode of the third transistor T3, and the first end of the storage capacitor C, respectively; the second node N2 is connected to the first electrode of the third transistor T3, the second electrode of the fourth transistor T4, the second electrode of the fifth transistor T5, and the second electrode of the eighth transistor T8, respectively; the third node N3 is connected to the second electrode of the first transistor T1, the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the first electrode of the sixth transistor T6, respectively; the fourth node N4 is connected to the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7, respectively; and the fourth node N4 is further connected to the anode of the light emitting device EL.

[0075] In an exemplary embodiment, a first end of the storage capacitor C is connected to the first node N1 , and a second end of the storage capacitor C is connected to the first power line VDD.

[0076] In an exemplary embodiment, the first transistor T1 may be referred to as a first initialization transistor. A gate electrode of the first transistor T1 is connected to the third scan signal line S3, a first electrode of the first transistor T1 is connected to the first initial signal line INIT1, and a second electrode of the first transistor T1 is connected to the third node N3. The second transistor T2 may be referred to as a compensation transistor. A gate electrode of the second transistor T2 is connected to the fourth scan signal line S4, a first electrode of the second transistor T2 is connected to the first node N1, and a second electrode of the second transistor T2 is connected to the third node N3. The third transistor T3 may be referred to as a driving transistor. A gate electrode of the third transistor T3 is connected to the first node N1, that is, the gate electrode of the third transistor T3 is connected to the first end of the storage capacitor C, a first electrode of the third transistor T3 is connected to the second node N2, and a second electrode of the third transistor T3 is connected to the third node N3. The fourth transistor T4 may be referred to as a data write transistor. A gate electrode of the fourth transistor T4 is connected to the first scan signal line S1, a first electrode of the fourth transistor T4 is connected to the data signal line DATA, and a second electrode of the fourth transistor T4 is connected to the second node N2. The fifth transistor T5 can be referred to as a first emission control transistor. A gate electrode of the fifth transistor T5 is connected to the emission signal line EM, a first electrode of the fifth transistor T5 is connected to the first power line VDD, and a second electrode of the fifth transistor T5 is connected to the second node N2. The sixth transistor T6 can be referred to as a second emission control transistor. A gate electrode of the sixth transistor T6 is connected to the emission signal line EM, a first electrode of the sixth transistor T6 is connected to the third node N3, and a second electrode of the sixth transistor T6 is connected to the fourth node N4. The seventh transistor T7 can be referred to as a second initialization transistor. A gate electrode of the seventh transistor T7 is connected to the second scan signal line S2, a first electrode of the seventh transistor T7 is connected to the second initialization signal line INIT2, and a second electrode of the seventh transistor T7 is connected to the fourth node N4. The eighth transistor T8 can be referred to as a third initialization transistor. A gate electrode of the eighth transistor T8 is connected to the second scan signal line S2, a first electrode of the eighth transistor T8 is connected to the third initialization signal line INIT3, and a second electrode of the eighth transistor T8 is connected to the second node N2.

[0077] In an exemplary embodiment, the light-emitting device EL can be an OLED, including a stacked anode (first pole), an organic light-emitting layer and a cathode (second pole), or can be a QLED, including a stacked anode (first pole), a quantum dot light-emitting layer and a cathode (second pole).

[0078] In an exemplary embodiment, the first electrode of the light emitting device EL is connected to the fourth node N4, the second electrode of the light emitting device EL is connected to the second power line VSS, the signal of the second power line VSS is a continuously provided low level signal, and the signal of the first power line VDD is a continuously provided high level signal.

[0079] In an exemplary embodiment, the first transistor T1 to the eighth transistor T8 may be a P-type transistor or an N-type transistor. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the manufacturing difficulty of the display panel, and improve the product yield. In some possible implementations, the first transistor T1 to the eighth transistor T8 may include P-type transistors and N-type transistors.

[0080] In an exemplary embodiment, the first transistor T1 to the eighth transistor T8 may be low-temperature polysilicon transistors, or oxide transistors, or both low-temperature polysilicon transistors and metal oxide transistors. The active layer of the low-temperature polysilicon transistor is made of low-temperature polysilicon (LTPS), and the active layer of the metal oxide transistor is made of metal oxide semiconductor (Oxide). Low-temperature polysilicon transistors have advantages such as high mobility and fast charging, while oxide transistors have advantages such as low leakage current. Integrating low-temperature polysilicon transistors and metal oxide transistors on a display substrate to form a low-temperature polycrystalline oxide (LTPO) display substrate can leverage the advantages of both, enabling low-frequency driving, reducing power consumption, and improving display quality.

[0081] In an exemplary embodiment, the second transistor T2 may be a metal oxide transistor, and the first transistor T1 and the third transistor T3 to the eighth transistor T8 may be low temperature polysilicon transistors.

[0082] An exemplary embodiment of the present disclosure provides a display substrate. In an exemplary embodiment, on a plane perpendicular to the display substrate, the display substrate may include a driving structure layer arranged on a base and a light-emitting structure layer arranged on a side of the driving structure layer away from the base. On a plane parallel to the display substrate, the display substrate may include at least a display area, a binding area located on one side of the display area, and a frame area located on the other side of the display area. In an exemplary embodiment, the driving structure layer of the display area may include a plurality of circuit units constituting a plurality of unit rows and a plurality of unit columns, at least one circuit unit may include a pixel driving circuit, and the pixel driving circuit is configured to output a corresponding current to the connected light-emitting device. The light-emitting structure layer of the display area may include a plurality of light-emitting units, at least one light-emitting unit may include a light-emitting device, the light-emitting device is connected to the pixel driving circuit of the corresponding circuit unit, and the light-emitting device is configured to emit light of corresponding brightness in response to the current output by the connected pixel driving circuit.

[0083] In exemplary embodiments, the circuit unit referred to in this disclosure refers to a region divided according to the pixel driving circuit, and the light-emitting unit referred to in this disclosure refers to a region divided according to the light-emitting device. In exemplary embodiments, the position and shape of the orthographic projection of the light-emitting unit on the substrate may correspond to the position and shape of the orthographic projection of the circuit unit on the substrate, or the position and shape of the orthographic projection of the light-emitting unit on the substrate may not correspond to the position and shape of the orthographic projection of the circuit unit on the substrate.

[0084] In an exemplary embodiment, the driving structure layer further includes at least two signal lines extending along a first direction, and the at least one light-emitting device may include an anode disposed on a side of the driving structure layer distal from the substrate, and a pixel definition layer disposed on a side of the anode distal from the substrate, the pixel definition layer being provided with a pixel opening exposing a surface of the anode. In at least one pixel opening, an orthographic projection of the pixel opening on the substrate at least partially overlaps with an orthographic projection of the at least two signal lines extending along the first direction on the substrate. The at least two signal lines extending along the first direction may be located on either side of a geometric center of the pixel opening in a second direction, with the first direction and the second direction intersecting.

[0085] In an exemplary embodiment, at least two signal lines include a first connection line and a power connection line, the power connection line is connected to the data signal line extending along the second direction, the power connection line is connected to the first power line extending along the second direction, and the data signal line and the first power line are connected to the pixel driving circuit; in at least one pixel opening, the first connection line and the power connection line are symmetrically arranged with respect to a center line, and the center line is a straight line extending along the first direction and passing through the geometric center of the pixel opening.

[0086] In an exemplary embodiment, in at least one pixel opening, the pixel opening includes a first end portion located on a side of the power connection line away from the center line and a second end portion located on a side of the first connection line away from the center line, the power connection line includes a first edge on a side away from the center line, the first connection line includes a second edge on a side away from the center line, a first distance is between the first end portion and the first edge, a second distance is between the second end portion and the second edge, and a ratio of the first distance to the second distance is 0.9 to 1.1.

[0087] In an exemplary embodiment, the driving structure layer further includes a second connecting line extending along the second direction, the second connecting line being connected to the first connecting line. In at least one pixel opening, an orthographic projection of the second connecting line on the substrate at least partially overlaps an orthographic projection of a geometric center of the pixel opening on the substrate.

[0088] In an exemplary embodiment, an orthographic projection of the pixel opening on the substrate at least partially overlaps with an orthographic projection of two data signal lines on the substrate, the second connection line is disposed between the two data signal lines, and the two data signal lines are symmetrically disposed relative to the second connection line.

[0089] In an exemplary embodiment, an orthographic projection of the pixel opening on the substrate at least partially overlaps with an orthographic projection of two first power lines on the substrate, the second connecting line and the two data signal lines are arranged between the two first power lines, and the two first power lines are symmetrically arranged with respect to the second connecting line.

[0090] In an exemplary embodiment, the driving structure layer further includes a plurality of power connection lines extending along the first direction and a plurality of first power lines extending along the second direction, wherein the power connection lines and the first power lines are connected to form a grid connection structure for transmitting the first power signal.

[0091] Figure 6 is a schematic diagram of a planar structure of a display substrate according to an exemplary embodiment of the present disclosure. In this exemplary embodiment, the display substrate may include at least a drive structure layer disposed on a base and a light-emitting structure layer disposed on a side of the drive structure layer away from the base. In a plane parallel to the display substrate, the drive structure layer may include multiple circuit units, and the light-emitting structure layer may include multiple light-emitting units.

[0092] In an exemplary embodiment, the plurality of circuit units may form a plurality of unit rows and a plurality of unit columns, with the plurality of circuit units in each unit row being sequentially arranged along a first direction X, and the plurality of unit rows being sequentially arranged along a second direction Y, forming an array of circuit units arranged in an array. The circuit units may include at least a pixel driver circuit. The plurality of light-emitting units may form a plurality of light-emitting rows and a plurality of light-emitting columns, with the plurality of light-emitting units in each light-emitting row being sequentially arranged along a first direction X, and the plurality of light-emitting rows being sequentially arranged along a second direction Y, forming an array of light-emitting units arranged in an array. The light-emitting units may include at least an anode and a pixel definition layer covering the anode. The anode is connected to the pixel driver circuit of the corresponding circuit unit, and the pixel definition layer is provided with a pixel opening exposing the anode. In an exemplary embodiment, the first direction X intersects the second direction Y.

[0093] As shown in Figure 6, the driving structure layer may further include a power connection line 63 and a first connection line 81, the main part of which extends along the first direction X, and a first power line 71, a data signal line 72, and a second connection line 82, the main part of which extends along the second direction Y. In this disclosure, A extending along the B direction means that A can include a main part and a secondary part connected to the main part, the main part is a line, a line segment, or a strip-shaped body, the main part extends along the B direction, and the length of the main part extending along the B direction is greater than the length of the secondary part extending along other directions. In the following description, "A extends along the B direction" means "the main part of A extends along the B direction."

[0094] In an exemplary embodiment, the second connection line 82 is connected to the first connection line 81, the first connection line 81 is connected to the data signal line 72, the data signal line 72 is connected to multiple pixel driving circuits of a unit column, the first connection line 81 and the second connection line 82 are configured to provide data signals to the connected data signal line 72, forming an FIAA structure, and the data signal line 72 is configured to provide data signals to the connected pixel driving circuit.

[0095] In an exemplary embodiment, first power lines 71 are connected to multiple pixel driving circuits in a unit column. First power lines 71 are configured to provide a first power signal to the connected pixel driving circuits. Multiple power connection lines 63 and multiple first power lines 71 form a grid-connected structure on the display substrate that transmits the first power signal.

[0096] As shown in FIG6 , the light emitting structure layer includes a plurality of light emitting units, including a red light emitting unit that emits red light, a blue light emitting unit that emits blue light, a first green light emitting unit that emits green light, and a second green light emitting unit that emits green light. In an exemplary embodiment, the red light emitting unit may include at least a first anode and a first pixel opening 100A exposing the first anode, the blue light emitting unit may include at least a second anode and a second pixel opening 100B exposing the second anode, the first green light emitting unit may include at least a third anode and a third pixel opening 100C exposing the third anode, and the second green light emitting unit may include at least a fourth anode and a fourth pixel opening 100D exposing the fourth anode.

[0097] In an exemplary embodiment, the power connection line 63 and the first connection line 81 extending along the first direction X may be respectively located on both sides of the second direction Y of the geometric center of the first pixel opening 100A, and / or, the power connection line 63 and the first connection line 81 extending along the first direction X may be respectively located on both sides of the second direction Y of the geometric center of the second pixel opening 100B.

[0098] In an exemplary embodiment, the power connection line 63 and the first connection line 81 may be symmetrically arranged relative to the center line of the pixel opening. For example, the power connection line 63 and the first connection line 81 may be symmetrically arranged relative to the center line of the first pixel opening 100A, where the center line of the first pixel opening 100A is a straight line extending along the first direction X and passing through the geometric center of the first pixel opening 100A. For another example, the power connection line 63 and the first connection line 81 may be symmetrically arranged relative to the center line of the second pixel opening 100B, where the center line of the second pixel opening 100B is a straight line extending along the first direction X and passing through the geometric center of the second pixel opening 100B.

[0099] In an exemplary embodiment, in at least one of the first pixel opening 100A and the second pixel opening 100B, a distance between the power connection line 63 and one end of the pixel opening and a distance between the first connection line 81 and the other end of the pixel opening may be substantially the same.

[0100] In an exemplary embodiment, taking the second pixel opening 100B as an example, the second pixel opening 100B has a center line O, a first end portion A1 located on the side of the power connection line 63 away from the center line O, and a second end portion A2 located on the side of the first connection line 81 away from the center line O. The power connection line 63 has a first edge B1 on the side away from the center line O, and the first connection line 81 has a second edge B2 on the side away from the center line O. A first distance L1 is between the first end portion A1 and the first edge B1, and a second distance L2 is between the second end portion A2 and the second edge B2. The ratio of the first distance L1 to the second distance L2 can be approximately 0.9 to 1.1.

[0101] In an exemplary embodiment, a ratio of the first distance L1 to the second distance L2 may be approximately 1.0.

[0102] In an exemplary embodiment, the orthographic projections of the first power line 71, the data signal line 72, and the second connection line 82 extending along the second direction Y on the substrate at least partially overlap with the orthographic projection of the first pixel opening 100A on the substrate, and / or the orthographic projections of the first power line 71, the data signal line 72, and the second connection line 82 extending along the second direction Y on the substrate at least partially overlap with the orthographic projection of the second pixel opening 100B on the substrate.

[0103] In an exemplary embodiment, the orthographic projection of the second connection line 82 on the substrate at least partially overlaps with the orthographic projection of the geometric center of the first pixel opening 100A on the substrate, and / or the orthographic projection of the second connection line 82 on the substrate at least partially overlaps with the orthographic projection of the geometric center of the second pixel opening 100B on the substrate.

[0104] In an exemplary embodiment, an orthographic projection of the first pixel opening 100A on the substrate at least partially overlaps with an orthographic projection of the two data signal lines 72 on the substrate, and / or an orthographic projection of the second pixel opening 100B on the substrate at least partially overlaps with an orthographic projection of the two data signal lines 72 on the substrate. The second connection line 82 may be disposed between the two data signal lines 72, and the two data signal lines 72 may be symmetrically disposed with respect to the second connection line 82.

[0105] In an exemplary embodiment, an orthographic projection of the first pixel opening 100A on the substrate at least partially overlaps an orthographic projection of the two first power lines 71 on the substrate, and / or an orthographic projection of the second pixel opening 100B on the substrate at least partially overlaps an orthographic projection of the two first power lines 71 on the substrate. The second connection line 82 and the two data signal lines 72 may be disposed between the two first power lines 71, and the two first power lines 71 may be symmetrically disposed with respect to the second connection line 82.

[0106] In an exemplary embodiment, the driving structure layer may further include a plurality of anode spacers 74 , and the anode spacers 74 are connected to the first power lines 71 .

[0107] In an exemplary embodiment, in one unit row, the anode spacers 74 in some two adjacent circuit units may be interconnected and integrally formed.

[0108] In an exemplary embodiment, the orthographic projection of the third pixel opening 100C on the substrate at least partially overlaps with the orthographic projection of the anode spacer 74 on the substrate, and / or the orthographic projection of the fourth pixel opening 100D on the substrate at least partially overlaps with the orthographic projection of the anode spacer 74 on the substrate.

[0109] In an exemplary embodiment, the orthographic projection of the third pixel opening 100C on the substrate may be located within the range of the orthographic projection of the anode spacer 74 on the substrate, and / or the orthographic projection of the fourth pixel opening 100D on the substrate may be located within the range of the orthographic projection of the anode spacer 74 on the substrate.

[0110] In an exemplary embodiment, on a plane perpendicular to the display substrate, the driving structure layer includes a plurality of conductive layers sequentially arranged on the base, the first connecting line 81 and the second connecting line 82 can be arranged in different conductive layers, the power connecting line 63 and the first power connecting line 71 can be arranged in different conductive layers, the power connecting line 63 and the first connecting line 81 can be arranged in the same conductive layer, the first power connecting line 71, the data signal line 72 and the second connecting line 82 can be arranged in the same conductive layer, the second connecting line 82 can be connected to the first connecting line 81 through a via, the first connecting line 81 can be connected to the data signal line 72 through a via, and the first power line 71 can be connected to the power connecting line 63 through a via.

[0111] In an exemplary embodiment, the multiple conductive layers may include at least a first source-drain metal layer, a second source-drain metal layer, and a third source-drain metal layer arranged in sequence along a direction away from the substrate, the power connection line 63 and the first power line 71 may be arranged in the second source-drain metal layer, and the first power line 71, the data signal line 72 and the second connection line 82 may be arranged in the third source-drain metal layer.

[0112] In an exemplary embodiment, the anode spacer 74 and the first power line 71 may be provided in the same conductive layer and be an integral structure connected to each other.

[0113] In an exemplary embodiment, the pixel driving circuit includes at least a storage capacitor and a plurality of transistors, the plurality of transistors may include a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor and an eighth transistor, the second transistor is an oxide transistor, and the first transistor, the third transistor to the eighth transistor are low-temperature polysilicon transistors.

[0114] The following is an illustrative explanation of the preparation process of the display substrate. The "patterning process" mentioned in the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials, or transparent conductive materials, and includes processes such as coating organic materials, mask exposure, and development for organic materials. Deposition can be carried out by any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be carried out by any one or more of spraying, spin coating, and inkjet printing, and etching can be carried out by any one or more of dry etching and wet etching, and the present disclosure does not limit this. "Thin film" refers to a thin film made by deposition, coating, or other processes on a substrate of a certain material. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". As used in this disclosure, "A and B are disposed in the same layer" means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer refers to the dimension of the film layer in a direction perpendicular to the display substrate. In exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or that the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0115] In an exemplary embodiment, taking eight circuit units (two unit rows and four unit columns) as an example, the preparation process of the driving circuit layer may include the following operations.

[0116] (1) Forming a blocking layer pattern. In an exemplary embodiment, forming a blocking layer pattern may include: depositing a blocking film on a substrate, patterning the blocking film through a patterning process, and forming a blocking layer pattern on the substrate, as shown in FIG. 7 .

[0117] In an exemplary embodiment, the shielding layer pattern of each circuit unit may include at least a first shielding connection line 91 , a second shielding connection line 92 , a third shielding connection line 93 , and a shielding electrode 94 .

[0118] In an exemplary embodiment, the shielding electrode 94 may be rectangular in shape, and the corners of the rectangle may be chamfered. The first shielding connection line 91 may be a straight line extending along the first direction X. The first shielding connection line 91 may be arranged on one side of the shielding electrode 94 in the first direction X and connected to the shielding electrode 94. The second shielding connection line 92 may be shaped like a zigzag extending along the second direction Y. The second shielding connection line 92 may be arranged on one side of the shielding electrode 94 in the second direction Y and connected to the shielding electrode 94. The third shielding connection line 93 may be shaped like a zigzag extending along the second direction Y. The third shielding connection line 93 may be arranged on the side of the shielding electrode 94 opposite to the second direction Y and connected to the shielding electrode 94.

[0119] In an exemplary embodiment, the first shielding connection line 91 of each circuit unit is connected to the shielding electrode 94 of the adjacent circuit unit in the first direction X, so that the shielding layers in one unit row are connected as a whole to form an interconnected integrated structure.

[0120] In an exemplary embodiment, the second shielding connection line 92 of each circuit unit is connected to the third shielding connection line 93 of the adjacent circuit unit in the second direction Y, so that the second shielding connection line 92, the third shielding connection line 93 and the shielding electrode 94 in a unit column are connected into one, forming an interconnected integrated structure.

[0121] In an exemplary embodiment, the shielding layers in the unit rows and unit columns are connected as one, which can ensure that the shielding layers in the display substrate have the same potential, which is beneficial to improving the uniformity of the panel, avoiding poor display of the display substrate, and ensuring the display effect of the display substrate.

[0122] In an exemplary embodiment, the shielding layers of adjacent cell columns may be mirror-symmetrical with respect to a column boundary, which may be a straight line located between adjacent cell columns and extending along the second direction Y. For example, the shielding layer of the Nth column and the shielding layer of the N+1th column may be mirror-symmetrical with respect to the column boundary, the shielding layer of the N+1th column and the shielding layer of the N+2th column may be mirror-symmetrical with respect to the column boundary, and the shielding layer of the N+2th column and the shielding layer of the N+3th column may be mirror-symmetrical with respect to the column boundary. In an exemplary embodiment, the shapes of the shielding layers in multiple cell rows may be substantially the same.

[0123] (2) Forming a first semiconductor layer pattern. In an exemplary embodiment, forming the first semiconductor layer pattern may include: sequentially depositing a first insulating film and a first semiconductor film on a substrate, patterning the first semiconductor film through a patterning process to form a first insulating layer covering the shielding layer, and a first semiconductor layer pattern disposed on the first insulating layer, as shown in FIG8A and FIG8B , where FIG8B is a plan view schematic diagram of the first semiconductor layer in FIG8A .

[0124] In an exemplary embodiment, the first semiconductor layer pattern of each circuit unit may include at least the first active layer 11 of the first transistor T1, the third active layer 13 of the third transistor T3 to the eighth active layer 18 of the eighth transistor T8, and the third active layer 13 to the seventh active layer 17 are an integrated structure connected to each other, and the first active layer 11 and the eighth active layer 18 are separately provided.

[0125] In an exemplary embodiment, an orthographic projection of the third active layer 13 on the substrate at least partially overlaps with an orthographic projection of the shielding electrode 94 on the substrate.

[0126] In the first direction X, the first active layer 11 and the sixth active layer 16 may be located on one side of the third active layer 13 in the present circuit unit in the first direction X, and the fourth active layer 14 and the fifth active layer 15 may be located on a side of the third active layer 13 in the present circuit unit in the opposite direction of the first direction X. In the second direction Y, the fourth active layer 14 may be located on a side of the third active layer 13 in the present circuit unit in the opposite direction of the second direction Y, and the first active layer 11, the fifth active layer 15, the sixth active layer 16, the seventh active layer 17, and the eighth active layer 18 may be located on one side of the third active layer 13 in the present circuit unit in the second direction Y.

[0127] In an exemplary embodiment, the third active layer 13 may have an inverted "Ω" shape, the first active layer 11, the fourth active layer 14, the fifth active layer 15, and the sixth active layer 16 may have an "I" shape, and the seventh active layer 17 and the eighth active layer 18 may have an "L" shape.

[0128] In an exemplary embodiment, the first active layer 11 and the third active layers 13 to 18 may each include a first region, a second region, and a channel region located between the first and second regions. In an exemplary embodiment, the first region 13-1 of the third active layer may simultaneously serve as the second region 14-2 of the fourth active layer and the second region 15-2 of the fifth active layer, the second region 13-2 of the third active layer may serve as the first region 16-1 of the sixth active layer, and the second region 16-2 of the sixth active layer may serve as the second region 17-2 of the seventh active layer. The first region 11-1 of the first active layer, the second region 11-2 of the first active layer, the first region 14-1 of the fourth active layer, the first region 15-1 of the fifth active layer, the first region 17-1 of the seventh active layer, the first region 18-1 of the eighth active layer, and the second region 18-2 of the eighth active layer may be provided separately.

[0129] In an exemplary embodiment, the fifth active layers of some two adjacent circuit cells in a cell row may be interconnected as a single unit. For example, the first region 15-1 of the fifth active layer in the N-1th column is interconnected with the first region 15-1 of the fifth active layer in the Nth column, the first region 15-1 of the fifth active layer in the N+1th column is interconnected with the first region 15-1 of the fifth active layer in the N+2th column, and the first region 15-1 of the fifth active layer in the N+3th column is interconnected with the first region 15-1 of the fifth active layer in the N+4th column. Because the first region of the fifth active layer in each circuit cell is configured to connect to a subsequently formed first power line, by forming the first regions of the fifth active layers of adjacent circuit cells into a single unit, the first electrodes of the fifth transistors T5 of adjacent circuit cells can be ensured to have the same potential, which helps improve the uniformity of the panel, avoid display defects on the display substrate, and ensure the display quality of the display substrate.

[0130] In an exemplary embodiment, the eighth active layers of some two adjacent circuit cells in a cell row may be interconnected as a single unit. For example, the first region 18-1 of the eighth active layer in the N-1th column is interconnected with the first region 18-1 of the eighth active layer in the Nth column, the first region 18-1 of the eighth active layer in the N+1th column is interconnected with the first region 18-1 of the eighth active layer in the N+2th column, and the first region 18-1 of the eighth active layer in the N+3th column is interconnected with the first region 18-1 of the eighth active layer in the N+4th column. Because the first region 18-1 of the eighth active layer in each circuit cell is configured to connect to a subsequently formed third initial signal line, by forming the first regions 18-1 of the eighth active layers of adjacent circuit cells into a single unitary structure, the first electrodes of the eighth transistors in the adjacent circuit cells can be ensured to have the same potential, which is beneficial for improving the uniformity of the panel, avoiding display defects on the display substrate, and ensuring the display quality of the display substrate.

[0131] In an exemplary embodiment, the first active layer 11 may be disposed between two adjacent cell columns, the first region 11-1 of the first active layer may be located in the circuit cell of the Mth row, and the second region 11-2 of the first active layer may be located in the circuit cell of the M+1th row, where M may be a positive integer greater than or equal to 1.

[0132] In an exemplary embodiment, the first semiconductor layers of adjacent cell columns may be mirror-symmetrical with respect to a column boundary. For example, the first semiconductor layer of the Nth column and the first semiconductor layer of the N+1th column may be mirror-symmetrical with respect to the column boundary, the first semiconductor layer of the N+1th column and the first semiconductor layer of the N+2th column may be mirror-symmetrical with respect to the column boundary, and the first semiconductor layer of the N+2th column and the first semiconductor layer of the N+3th column may be mirror-symmetrical with respect to the column boundary. In an exemplary embodiment, the shapes of the first semiconductor layers in multiple cell rows may be substantially the same.

[0133] In an exemplary embodiment, the first semiconductor layer may be made of polycrystalline silicon (p-Si), meaning the third to seventh transistors are LTPS transistors. In an exemplary embodiment, patterning the first semiconductor film through a patterning process may include: first forming an amorphous silicon (a-Si) film on the first insulating film, performing a dehydrogenation treatment on the amorphous silicon film, and then crystallizing the dehydrogenated amorphous silicon film to form a polycrystalline silicon film. Subsequently, patterning the polycrystalline silicon film to form a first semiconductor layer pattern.

[0134] (3) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include: sequentially depositing a second insulating film and a first conductive film on the substrate having the aforementioned pattern formed thereon, patterning the first conductive film through a patterning process to form a second insulating layer covering the first semiconductor layer pattern, and a first conductive layer pattern disposed on the second insulating layer, as shown in FIG9A and FIG9B , FIG9B being a planar schematic diagram of the first conductive layer in FIG9A . In an exemplary embodiment, the first conductive layer may be referred to as a first gate metal (GATE1) layer.

[0135] In an exemplary embodiment, the first conductive layer pattern of each circuit unit includes at least a first scan signal line 21 , a second scan signal line 22 , a third scan signal line 23 , a light emitting signal line 24 and a first plate 25 of a storage capacitor.

[0136] In an exemplary embodiment, the first electrode plate 25 may be rectangular, with chamfered corners. The orthographic projection of the first electrode plate 25 on the substrate at least partially overlaps the orthographic projection of the third active layer of the third transistor T3 on the substrate. In an exemplary embodiment, the first electrode plate 25 may serve as both a plate of the storage capacitor and a gate electrode of the third transistor T3.

[0137] In an exemplary embodiment, the shape of the first scanning signal line 21 can be a zigzag shape with the main portion extending along the first direction X. The first scanning signal line 21 can be located on the side of the first electrode 25 in the opposite direction of the second direction Y. The area where the first scanning signal line 21 overlaps with the fourth active layer can serve as the gate electrode of the fourth transistor T4.

[0138] In an exemplary embodiment, the shape of the second scanning signal line 22 can be a zigzag shape with the main portion extending along the first direction X. The second scanning signal line 22 can be located on one side of the first electrode 25 in the second direction Y. The area where the second scanning signal line 22 overlaps with the seventh active layer can serve as the gate electrode of the seventh transistor T7, and the area where the second scanning signal line 22 overlaps with the eighth active layer can serve as the gate electrode of the eighth transistor T8.

[0139] In an exemplary embodiment, the shape of the third scan signal line 23 can be a zigzag shape with the main portion extending along the first direction X. The third scan signal line 23 can be located on a side of the second scan signal line 22 away from the first electrode 25. The area where the third scan signal line 23 overlaps with the first active layer can serve as the gate electrode of the first transistor T1.

[0140] In an exemplary embodiment, the shape of the light-emitting signal line 24 can be a broken line with the main portion extending along the first direction X. The light-emitting signal line 24 can be located on the side of the second scanning signal line 22 close to the first electrode 25. The area where the light-emitting signal line 24 overlaps with the fifth active layer can serve as the gate electrode of the fifth transistor T5, and the area where the light-emitting signal line 24 overlaps with the sixth active layer can serve as the gate electrode of the sixth transistor T6.

[0141] In an exemplary embodiment, the first scanning signal line 21, the second scanning signal line 22, the third scanning signal line 23 and the light-emitting signal line 24 can be designed with non-equal widths, and the width is the dimension in the second direction Y, which not only facilitates the layout of the pixel structure, but also reduces the parasitic capacitance between the signal lines. The present disclosure does not limit this.

[0142] In an exemplary embodiment, the first scan signal line 21, the second scan signal line 22, the third scan signal line 23 and the light emitting signal line 24 may include an area overlapping with the first semiconductor layer and an area not overlapping with the first semiconductor layer, and the width of the signal line in the area overlapping with the first semiconductor layer may be greater than the width of the signal line in the area not overlapping with the first semiconductor layer.

[0143] In an exemplary embodiment, the first conductive layers of adjacent cell columns may be mirror-symmetric with respect to a column boundary. For example, the first conductive layer of the Nth column and the first conductive layer of the N+1th column may be mirror-symmetric with respect to the column boundary, the first conductive layer of the N+1th column and the first conductive layer of the N+2th column may be mirror-symmetric with respect to the column boundary, and the first conductive layer of the N+2th column and the first conductive layer of the N+3th column may be mirror-symmetric with respect to the column boundary. In an exemplary embodiment, the shapes of the first conductive layers in multiple cell rows may be substantially the same.

[0144] In an exemplary embodiment, after forming the first conductive layer pattern, the first conductive layer can be used as a shield to perform conductorization on the first semiconductor layer. The first semiconductor layer in the area shielded by the first conductive layer forms the channel region of the first transistor T1 and the third transistor T3 to the eighth transistor T8, and the first semiconductor layer in the area not shielded by the first conductive layer is conductorized, that is, the first area and the second area of ​​the first transistor T1 and the third transistor T3 to the eighth transistor T8 are all conductorized.

[0145] (4) Forming a second conductive layer pattern. In an exemplary embodiment, forming the second conductive layer pattern may include: sequentially depositing a third insulating film and a second conductive film on the substrate having the aforementioned pattern formed thereon, patterning the second conductive film using a patterning process to form a third insulating layer covering the first conductive layer, and a second conductive layer pattern disposed on the third insulating layer, as shown in FIG10A and FIG10B , where FIG10B is a plan view schematic diagram of the second conductive layer in FIG10A . In an exemplary embodiment, the second conductive layer may be referred to as a second gate metal (GATE2) layer.

[0146] In an exemplary embodiment, the second conductive layer pattern of each circuit unit includes at least a shielding line 31 and a second electrode 32 of a storage capacitor.

[0147] In an exemplary embodiment, the shape of the shielding line 31 can be a line shape in which the main part extends along the first direction X. The shielding line 31 can be located between the first scanning signal line 21 and the first electrode 25. The shielding line 31 is configured as a shielding layer of the second transistor T2, shielding the channel region of the second transistor T2, ensuring the electrical performance of the oxide second transistor T2, and at the same time being configured as the bottom gate electrode of the second transistor T2.

[0148] In an exemplary embodiment, the shielding lines 31 may be designed with unequal widths, which not only facilitates the layout of the pixel structure but also reduces the parasitic capacitance between the signal lines.

[0149] In an exemplary embodiment, the outline of the second electrode plate 32 can be rectangular, and the corners of the rectangle can be chamfered. The orthographic projection of the second electrode plate 32 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate 25 on the substrate. The second electrode plate 32 can serve as another electrode plate of the storage capacitor, and the first electrode plate 25 and the second electrode plate 32 constitute the storage capacitor of the pixel driving circuit.

[0150] In an exemplary embodiment, an opening 33 is provided on the second electrode plate 32. Opening 33 can be rectangular and located in the middle of the second electrode plate 32, forming an annular structure. Opening 33 exposes the third insulating layer covering the first electrode plate 25, and the orthographic projection of the first electrode plate 25 on the substrate includes the orthographic projection of opening 33 on the substrate. In an exemplary embodiment, opening 33 is configured to accommodate a thirteenth via hole to be formed later. The thirteenth via hole is located within opening 33 and exposes the first electrode plate 25, allowing a first connecting electrode to be formed later to connect to the first electrode plate 25.

[0151] In an exemplary embodiment, the second plates 32 in two adjacent circuit units in a unit row can be interconnected integral structures. The second plate 32 in the Nth column and the second plate 32 in the N+1th column are interconnected via a first connecting bar 34. For another example, the second plate 32 in the N+1th column and the second plate 32 in the N+2th column can be interconnected via a second connecting bar 35. Since the second plate 32 in each circuit unit is connected to a first power line formed subsequently, by forming the second plates 32 of adjacent circuit units into an integral structure that is interconnected, the second plates of the integral structure can be reused as power signal lines, ensuring that multiple second plates in a unit row have the same potential, which is beneficial to improving the uniformity of the panel, avoiding poor display of the display substrate, and ensuring the display effect of the display substrate.

[0152] In an exemplary embodiment, the lengths and widths of the first and second connecting bars 34 and 35 may be different, and the first and second connecting bars 34 and 35 may be staggered in the second direction.

[0153] In an exemplary embodiment, the second conductive layers of adjacent cell columns may be mirror-symmetric with respect to a column boundary. For example, the second conductive layer of the Nth column and the second conductive layer of the N+1th column may be mirror-symmetric with respect to the column boundary, the second conductive layer of the N+1th column and the second conductive layer of the N+2th column may be mirror-symmetric with respect to the column boundary, and the second conductive layer of the N+2th column and the second conductive layer of the N+3th column may be mirror-symmetric with respect to the column boundary. In an exemplary embodiment, the shapes of the second conductive layers in multiple cell rows may be substantially the same.

[0154] (5) Forming a second semiconductor layer pattern. In an exemplary embodiment, forming the second semiconductor layer pattern may include: sequentially depositing a fourth insulating film and a second semiconductor film on the substrate having the aforementioned pattern formed thereon, patterning the second semiconductor film through a patterning process to form a fourth insulating layer covering the substrate, and a second semiconductor layer pattern disposed on the fourth insulating layer, as shown in FIG11A and FIG11B , where FIG11B is a plan view schematic diagram of the second semiconductor layer in FIG11A .

[0155] In an exemplary embodiment, the second semiconductor layer pattern of each circuit unit includes at least a second active layer 12 of a second transistor T2 .

[0156] In an exemplary embodiment, the second active layer 12 may be in an “L” shape, and an orthographic projection of the second active layer 12 on the substrate at least partially overlaps an orthographic projection of the shielding line 31 on the substrate.

[0157] In an exemplary embodiment, the first region 12 - 1 of the second active layer may be located on a side of the shielding line 31 away from the second electrode plate 32 , and the second region 12 - 2 of the second active layer may be located on a side of the shielding line 31 close to the second electrode plate 32 .

[0158] In an exemplary embodiment, the second semiconductor layers of adjacent cell columns may be mirror-symmetrical with respect to a column boundary. For example, the second semiconductor layer of the Nth column and the second semiconductor layer of the N+1th column may be mirror-symmetrical with respect to the column boundary, the second semiconductor layer of the N+1th column and the second semiconductor layer of the N+2th column may be mirror-symmetrical with respect to the column boundary, and the second semiconductor layer of the N+2th column and the second semiconductor layer of the N+3th column may be mirror-symmetrical with respect to the column boundary. In an exemplary embodiment, the shapes of the second semiconductor layers in multiple cell rows may be substantially the same.

[0159] In an exemplary embodiment, the second semiconductor layer may be made of oxide, that is, the eighth transistor T8 is an oxide transistor. In an exemplary embodiment, the second semiconductor thin film may be made of indium gallium zinc oxide (IGZO), which has higher electron mobility than amorphous silicon.

[0160] (6) Forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer pattern may include: sequentially depositing a fifth insulating film and a third conductive film on the substrate having the aforementioned pattern formed thereon, patterning the third conductive film using a patterning process to form a fifth insulating layer covering the second semiconductor layer, and a third conductive layer pattern disposed on the fifth insulating layer, as shown in FIG12A and FIG12B , where FIG12B is a plan view schematic diagram of the third conductive layer in FIG12A . In an exemplary embodiment, the second conductive layer may be referred to as a third gate metal (GATE3) layer.

[0161] In an exemplary embodiment, the third conductive layer pattern of each circuit unit includes at least a first preliminary signal line 41 , a second preliminary signal line 42 , a third preliminary signal line 43 and a fourth scan signal line 44 .

[0162] In an exemplary embodiment, the shape of the first initial signal line 41 can be a zigzag shape with the main portion extending along the first direction X. The first initial signal line 41 can be located between the third scanning signal line 23 and the light-emitting signal line 24. A first initial connection block 41-1 is provided on the first initial signal line 41 of each circuit unit. The first initial connection block 41-1 is configured to be connected to the first region of the first active layer through a seventh connection electrode formed subsequently.

[0163] In an exemplary embodiment, the shape of the second initial signal line 42 can be a broken line with the main portion extending along the first direction X. The second initial signal line 42 can be located on the side of the first initial signal line 41 away from the second electrode plate 32. A second initial connection block 42-1 is provided on the second initial signal line 42 of each circuit unit, and the second initial connection block 42-1 is configured to be connected to the first area of ​​the seventh active layer through the subsequently formed eighth connection electrode.

[0164] In an exemplary embodiment, the shape of the third initial signal line 43 can be a broken line with the main portion extending along the first direction X. The third initial signal line 43 can be located on the side of the first initial signal line 41 close to the second electrode plate 32. A third initial connection block 43-1 is provided on the third initial signal line 43 of each circuit unit. The third initial connection block 43-1 is configured to be connected to the first area of ​​the eighth active layer through a ninth connection electrode formed subsequently.

[0165] In an exemplary embodiment, the shape of the fourth scan signal line 44 can be a line shape whose main portion extends along the first direction X. The fourth scan signal line 44 can be located between the first scan signal line 21 and the first electrode 25. The orthographic projection of the fourth scan signal line 44 on the substrate at least partially overlaps with the orthographic projection of the shielding line 31 on the substrate. The area where the fourth scan signal line 44 overlaps with the second active layer can serve as the gate electrode of the second transistor T2.

[0166] In an exemplary embodiment, the fourth scanning signal line 44 and the shielding line 31 can be connected to the same signal source, so that the shielding line 31 can serve as the bottom gate electrode of the second transistor T2, and the fourth scanning signal line 44 can serve as the top gate electrode of the second transistor T2, forming a second transistor T2 with a top-gate and bottom-gate structure.

[0167] In an exemplary embodiment, the third conductive layers of adjacent cell columns may be mirror-symmetric with respect to a column boundary. For example, the third conductive layer of the Nth column and the third conductive layer of the N+1th column may be mirror-symmetric with respect to the column boundary, the third conductive layer of the N+1th column and the third conductive layer of the N+2th column may be mirror-symmetric with respect to the column boundary, and the third conductive layer of the N+2th column and the third conductive layer of the N+3th column may be mirror-symmetric with respect to the column boundary. In an exemplary embodiment, the shapes of the third conductive layers in multiple cell rows may be substantially the same.

[0168] (7) Forming a sixth insulating layer pattern. In an exemplary embodiment, forming the sixth insulating layer pattern may include: depositing a sixth insulating film on the substrate having the aforementioned pattern formed thereon, patterning the fifth insulating film using a patterning process to form a sixth insulating layer covering the third conductive layer, wherein the sixth insulating layer is provided with a plurality of vias, as shown in FIG. 13 .

[0169] In an exemplary embodiment, the multiple vias of each circuit unit include at least: a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, a ninth via V9, a tenth via V10, an eleventh via V11, a twelfth via V12, a thirteenth via V13, a fourteenth via V14, a fifteenth via V15, a sixteenth via V16 and a seventeenth via V17.

[0170] In an exemplary embodiment, the orthographic projection of the first via hole V1 on the substrate is located within the range of the orthographic projection of the first region of the first active layer on the substrate, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer within the first via hole V1 are etched away to expose the surface of the first region of the first active layer, and the first via hole V1 is configured to connect a subsequently formed seventh connecting electrode to the first region of the first active layer through the via hole.

[0171] In an exemplary embodiment, the orthographic projection of the second via hole V2 on the substrate is located within the range of the orthographic projection of the second region of the first active layer on the substrate, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the second via hole V2 are etched away to expose the surface of the second region of the first active layer, and the second via hole V2 is configured to connect a subsequently formed second connecting electrode to the second region of the first active layer through the via hole.

[0172] In an exemplary embodiment, the orthographic projection of the third via hole V3 on the substrate is located within the range of the orthographic projection of the first region of the second active layer on the substrate, the sixth insulating layer and the fifth insulating layer in the third via hole V3 are etched away to expose the surface of the first region of the second active layer, and the third via hole V3 is configured to connect a subsequently formed first connecting electrode to the first region of the second active layer through the via hole.

[0173] In an exemplary embodiment, the orthographic projection of the fourth via hole V4 on the substrate is located within the range of the orthographic projection of the second region of the second active layer on the substrate, the sixth insulating layer and the fifth insulating layer in the fourth via hole V4 are etched away to expose the surface of the second region of the second active layer, and the fourth via hole V4 is configured to connect a subsequently formed second connecting electrode to the second region of the second active layer through the via hole.

[0174] In an exemplary embodiment, the orthographic projection of the fifth via hole V5 on the substrate is located within the range of the orthographic projection of the second area of ​​the third active layer (also the first area of ​​the sixth active layer) on the substrate, and the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the fifth via hole V5 are etched away to expose the surface of the second area of ​​the third active layer (also the first area of ​​the sixth active layer), and the fifth via hole V5 is configured to connect the subsequently formed second connecting electrode to the second area of ​​the third active layer (also the first area of ​​the sixth active layer) through the via hole.

[0175] In an exemplary embodiment, the orthographic projection of the sixth via hole V6 on the substrate is located within the range of the orthographic projection of the first area of ​​the fourth active layer on the substrate, and the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the sixth via hole V6 are etched away to expose the surface of the first area of ​​the fourth active layer. The sixth via hole V6 is configured to connect a subsequently formed third connecting electrode to the first area of ​​the fourth active layer through the via hole.

[0176] In an exemplary embodiment, the orthographic projection of the seventh via V7 on the substrate is located within the orthographic projection of the first region of the fifth active layer on the substrate. The sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer, and the second insulating layer within the seventh via V7 are etched away, exposing the surface of the first region of the fifth active layer. The seventh via V7 is configured to connect a subsequently formed fourth connection electrode to the first region of the fifth active layer through the via. In an exemplary embodiment, because the first regions of the fifth active layers of some adjacent circuit cells in a cell row are interconnected, some of the adjacent circuit cells can share one seventh via V7.

[0177] In an exemplary embodiment, the orthographic projection of the eighth via V8 on the substrate is located within the range of the orthographic projection of the second region of the fifth active layer on the substrate, and the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer within the eighth via V8 are etched away to expose the surface of the second region of the fifth active layer. The eighth via V8 is configured to connect the subsequently formed fifth connecting electrode to the second region of the fifth active layer (which is also the first region of the third active layer and the second region of the fourth active layer) through the via.

[0178] In an exemplary embodiment, the orthographic projection of the ninth via hole V9 on the substrate is located within the range of the orthographic projection of the second area of ​​the sixth active layer (also the second area of ​​the seventh active layer) on the substrate, and the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the ninth via hole V9 are etched away to expose the surface of the second area of ​​the sixth active layer (also the second area of ​​the seventh active layer), and the ninth via hole V9 is configured to connect the subsequently formed sixth connecting electrode to the second area of ​​the sixth active layer (also the second area of ​​the seventh active layer) through the via hole.

[0179] In an exemplary embodiment, the orthographic projection of the tenth via hole V10 on the substrate is located within the range of the orthographic projection of the first region of the seventh active layer on the substrate, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer within the tenth via hole V10 are etched away to expose the surface of the first region of the seventh active layer, and the tenth via hole V10 is configured to connect the subsequently formed eighth connecting electrode to the first region of the seventh active layer through the via hole.

[0180] In an exemplary embodiment, the orthographic projection of the eleventh via hole V11 on the substrate is located within the orthographic projection of the first region of the eighth active layer on the substrate. The sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer, and the second insulating layer within the eleventh via hole V11 are etched away, exposing the surface of the first region of the eighth active layer. The eleventh via hole V11 is configured to connect a subsequently formed ninth connecting electrode to the first region of the eighth active layer through the via hole. In an exemplary embodiment, since the first regions of the eighth active layer of some adjacent circuit cells in a cell row are interconnected, some of the adjacent circuit cells can share the same eleventh via hole V11.

[0181] In an exemplary embodiment, the orthographic projection of the twelfth via hole V12 on the substrate is located within the range of the orthographic projection of the second region of the eighth active layer on the substrate, and the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the twelfth via hole V12 are etched away to expose the surface of the second region of the eighth active layer. The twelfth via hole V12 is configured to connect the subsequently formed fifth connecting electrode to the second region of the eighth active layer through the via hole.

[0182] In an exemplary embodiment, the orthographic projection of the thirteenth via hole V13 on the substrate is located within the range of the orthographic projection of the opening 33 on the substrate, and the sixth insulating layer, the fifth insulating layer, the fourth insulating layer and the third insulating layer in the thirteenth via hole V13 are etched away to expose the surface of the first electrode 25. The thirteenth via hole V13 is configured to connect the subsequently formed first connecting electrode to the first electrode 25 through the via hole.

[0183] In the exemplary embodiment, the orthographic projection of the fourteenth via hole V14 on the substrate is located within the range of the orthographic projection of the second electrode plate 32 on the substrate. The sixth insulating layer, the fifth insulating layer, and the fourth insulating layer within the fourteenth via hole V14 are etched away, exposing the surface of the second electrode plate 32. The fourteenth via hole V14 is configured to connect a subsequently formed fourth connection electrode to the second electrode plate 32 through the via hole. In the exemplary embodiment, since the second electrodes 32 of adjacent circuit cells in a cell row are connected to each other, some adjacent circuit cells in a cell row can share a fourteenth via hole V14.

[0184] In an exemplary embodiment, the orthographic projection of the fifteenth via V15 on the substrate is located within the range of the orthographic projection of the first initial connection block 41-1 of the first initial signal line 41 on the substrate, the sixth insulating layer in the fifteenth via V15 is etched away, exposing the surface of the first initial connection block 41-1, and the fifteenth via V15 is configured to connect the subsequently formed seventh connection electrode to the first initial connection block 41-1 through the via.

[0185] In an exemplary embodiment, the orthographic projection of the sixteenth via V16 on the substrate is located within the range of the orthographic projection of the second initial connection block 42-1 of the second initial signal line 42 on the substrate, the sixth insulating layer in the sixteenth via V16 is etched away, exposing the surface of the second initial connection block 42-1, and the sixteenth via V16 is configured to connect the subsequently formed eighth connection electrode to the second initial connection block 42-1 through the via.

[0186] In an exemplary embodiment, the orthographic projection of the seventeenth via V17 on the substrate is located within the range of the orthographic projection of the third initial connection block 43-1 of the third initial signal line 43 on the substrate, the sixth insulating layer in the seventeenth via V17 is etched away, exposing the surface of the third initial connection block 43-1, and the seventeenth via V17 is configured to connect the subsequently formed ninth connection electrode to the third initial connection block 43-1 through the via.

[0187] In an exemplary embodiment, the plurality of via holes in adjacent cell columns may be mirror-symmetrical with respect to a column boundary line, and the shapes of the plurality of via holes in the plurality of cell rows may be substantially the same.

[0188] (8) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming the fourth conductive layer may include: depositing a fourth conductive film on the substrate having the aforementioned pattern formed thereon, and patterning the fourth conductive film using a patterning process to form a fourth conductive layer disposed on the sixth insulating layer, as shown in FIG. 14A and FIG. 14B , where FIG. 14B is a plan view schematic diagram of the fourth conductive layer in FIG. 14A . In an exemplary embodiment, the fourth conductive layer may be referred to as a first source / drain metal (SD1) layer.

[0189] In an exemplary embodiment, the fourth conductive layer of each circuit unit includes at least: a first connection electrode 51, a second connection electrode 52, a third connection electrode 53, a fourth connection electrode 54, a fifth connection electrode 55, a sixth connection electrode 56, a seventh connection electrode 57, an eighth connection electrode 58 and a ninth connection electrode 59.

[0190] In an exemplary embodiment, the first connection electrode 51 may be shaped like a zigzag line with a main portion extending along the second direction Y. A first end of the first connection electrode 51 is connected to the first region of the second active layer via a third via hole V3. A second end of the first connection electrode 51 extends along the second direction Y and is connected to the first electrode plate 25 via a thirteenth via hole V13. In an exemplary embodiment, because the first electrode plate 25 also serves as the gate electrode of the third transistor T3, the first connection electrode 51 causes the first electrode of the second transistor T2, the gate electrode of the third transistor T3, and the first electrode plate 25 to have the same potential, forming a first node N1 of the pixel driving circuit.

[0191] In an exemplary embodiment, the second connection electrode 52 may be in the shape of a strip with a main portion extending along the second direction Y. The first end of the second connection electrode 52 is connected to the second region of the first active layer via a second via hole V2. The second end of the second connection electrode 52, after extending along the second direction Y, is connected to the second region of the third active layer (also the first region of the sixth active layer) via a fifth via hole V5. The portion between the first and second ends of the second connection electrode 52 is connected to the second region of the second active layer via a fourth via hole V4. In an exemplary embodiment, the second connection electrode 52 causes the second electrodes of the first transistor T1, the second electrodes of the second transistor T2, the second electrodes of the third transistor T3, and the first electrode of the sixth transistor T6 to have the same potential, forming a third node N3 of the pixel driving circuit.

[0192] In an exemplary embodiment, the third connection electrode 53 may be in a block shape (e.g., a rectangular shape) and is connected to the first region of the fourth active layer through a sixth via hole V6. In an exemplary embodiment, the third connection electrode 53 may serve as a first electrode of the fourth transistor T4 and is configured to be connected to an eleventh connection electrode to be formed subsequently.

[0193] In an exemplary embodiment, the shape of the fourth connection electrode 54 can be a broken line with the main portion extending along the second direction Y. The first end of the fourth connection electrode 54 is connected to the first area of ​​the fifth active layer through the seventh via V7. The second end of the fourth connection electrode 54 extends in the opposite direction of the second direction Y and is connected to the second electrode plate 32 through the fourteenth via V14, thereby achieving the same potential for the first electrode of the fifth transistor T5 in the circuit unit and the second electrode plate 32 of the storage capacitor.

[0194] In an exemplary embodiment, the fourth connection electrode 54 may serve as a first electrode of the fifth transistor T5. A power connection block 54-1 is provided on the fourth connection electrode 54. The power connection block 54-1 is provided on a side of the second end of the fourth connection electrode 54 away from the first end. The power connection block 54-1 is configured to be connected to a power connection line formed subsequently.

[0195] In an exemplary embodiment, within a cell row, the fourth connection electrodes 54 of some two adjacent circuit cells may be interconnected and integrally formed. This ensures that the first electrodes of the fifth transistors T5 and the second plates 32 of the storage capacitors in the adjacent circuit cells have the same potential, thereby improving panel uniformity, preventing display defects on the display substrate, and ensuring the display quality of the display substrate. For example, the fourth connection electrode 54 in the N-1th column is interconnected with the fourth connection electrode 54 in the Nth column, the fourth connection electrode 54 in the N+1th column is interconnected with the fourth connection electrode 54 in the N+2th column, and the fourth connection electrode 54 in the N+3th column is interconnected with the fourth connection electrode 54 in the N+4th column.

[0196] In an exemplary embodiment, the fifth connection electrode 55 may be shaped like a zigzag line with a main portion extending along the second direction Y. A first end of the fifth connection electrode 55 is connected to the second region of the fifth active layer via an eighth via hole V8. A second end of the fifth connection electrode 55 extends along the second direction Y and is connected to the second region of the eighth active layer via a twelfth via hole V12. In an exemplary embodiment, because the second region of the fifth active layer serves as both the first region of the third active layer and the second region of the fourth active layer, the fifth connection electrode 55 causes the first electrode of the third transistor T3, the second electrode of the fourth transistor T4, the second electrode of the fifth transistor T5, and the second electrode of the eighth transistor T8 to have the same potential, thereby forming a second node N2 of the pixel driving circuit.

[0197] In an exemplary embodiment, the sixth connection electrode 56 may be in a block shape (e.g., a rectangle) and is connected to the second region of the sixth active layer (also the second region of the seventh active layer) via a ninth via hole V9. In an exemplary embodiment, the sixth connection electrode 56 may simultaneously serve as the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7. The sixth connection electrode 56 is configured to be connected to a subsequently formed twelfth connection electrode.

[0198] In an exemplary embodiment, the seventh connection electrode 57 may be in the shape of a strip with a main portion extending along the second direction Y. A first end of the seventh connection electrode 57 is connected to the first region of the first active layer via a first via hole V1, and a second end of the seventh connection electrode 57 is connected to the first initial connection block 41-1 via a fifteenth via hole V15. In an exemplary embodiment, the seventh connection electrode 57 may serve as the first electrode of the first transistor T1. Because the first initial connection block 41-1 is connected to the first initial signal line 41, the seventh connection electrode 57 allows the first initial signal transmitted by the first initial signal line 41 to be written into the first electrode of the first transistor T1.

[0199] In an exemplary embodiment, the eighth connection electrode 58 may be in the shape of a strip with a main portion extending along the second direction Y. A first end of the eighth connection electrode 58 is connected to the first region of the seventh active layer via a tenth via hole V10, and a second end of the eighth connection electrode 58 is connected to the second initial connection block 42-1 via a sixteenth via hole V16. In an exemplary embodiment, the eighth connection electrode 58 may serve as the first electrode of the seventh transistor T7. Since the second initial connection block 42-1 is connected to the second initial signal line 42, the eighth connection electrode 58 causes the second initial signal transmitted by the second initial signal line 42 to be written into the first electrode of the seventh transistor T7.

[0200] In an exemplary embodiment, the ninth connection electrode 59 may be shaped like a zigzag line with a main portion extending along the second direction Y. The first end of the eighth connection electrode 58 is connected to the first region of the eighth active layer via an eleventh via hole V11, and the second end of the eighth connection electrode 58 is connected to the third initial connection block 43-1 via a seventeenth via hole V17. In an exemplary embodiment, the ninth connection electrode 59 may serve as the first electrode of the eighth transistor T8. Since the third initial connection block 43-1 is connected to the third initial signal line 43, the ninth connection electrode 59 enables the third initial signal transmitted by the third initial signal line 43 to be written into the first electrode of the eighth transistor T8.

[0201] In an exemplary embodiment, within a unit row, the ninth connecting electrodes 59 in some adjacent circuit units may be interconnected and integrally formed. This ensures that the first electrodes of the eighth transistors T8 in the adjacent circuit units have the same potential, thereby improving panel uniformity, preventing display defects on the display substrate, and ensuring the display quality of the display substrate. For example, the ninth connecting electrode 59 in the N-1th column is interconnected with the ninth connecting electrode 59 in the Nth column, the ninth connecting electrode 59 in the N+1th column is interconnected with the ninth connecting electrode 59 in the N+2th column, and the ninth connecting electrode 59 in the N+3th column is interconnected with the ninth connecting electrode 59 in the N+4th column.

[0202] In an exemplary embodiment, the fourth conductive layers of adjacent cell columns may be mirror-symmetric with respect to the column boundary. For example, the fourth conductive layer of the Nth column and the fourth conductive layer of the N+1th column may be mirror-symmetric with respect to the column boundary, the fourth conductive layer of the N+1th column and the fourth conductive layer of the N+2th column may be mirror-symmetric with respect to the column boundary, and the fourth conductive layer of the N+2th column and the fourth conductive layer of the N+3th column may be mirror-symmetric with respect to the column boundary. In an exemplary embodiment, the shapes of the fourth conductive layers in multiple cell rows may be substantially the same.

[0203] (9) Forming a first planar layer pattern. In an exemplary embodiment, forming the first planar layer pattern may include: coating a first planar film on the substrate on which the aforementioned pattern is formed, patterning the first planar film using a patterning process to form a first planar layer covering the fourth conductive layer pattern, wherein a plurality of vias are provided on the first planar layer, as shown in FIG. 15 .

[0204] In an exemplary embodiment, the plurality of vias in each circuit unit includes at least a twenty-first via V21 , a twenty-second via V22 , and a twenty-third via V23 .

[0205] In an exemplary embodiment, the orthographic projection of the twenty-first via hole V21 on the substrate is located within the range of the orthographic projection of the third connecting electrode 53 on the substrate, the first flat layer in the twenty-first via hole V21 is etched away to expose the surface of the third connecting electrode 53, and the twenty-first via hole V21 is configured to connect the subsequently formed eleventh connecting electrode to the third connecting electrode 53 through the via hole.

[0206] In an exemplary embodiment, the orthographic projection of the twenty-second via V22 on the substrate is located within the range of the orthographic projection of the power connection block 54-1 of the fourth connection electrode 54 on the substrate, the first flat layer in the twenty-second via V22 is etched away to expose the surface of the power connection block 54-1, and the twenty-second via V22 is configured to connect a subsequently formed power connection line to the power connection block 54-1 through the via.

[0207] In an exemplary embodiment, the orthographic projection of the twenty-third via hole V23 on the substrate is located within the range of the orthographic projection of the sixth connecting electrode 56 on the substrate, the first flat layer in the twenty-third via hole V23 is etched away to expose the surface of the sixth connecting electrode 56, and the twenty-third via hole V23 is configured to connect the subsequently formed twelfth connecting electrode to the sixth connecting electrode 56 through the via hole.

[0208] In an exemplary embodiment, the plurality of via holes on the first planar layer of adjacent cell columns may be mirror-symmetrical with respect to a column boundary line, and the plurality of via holes on the first planar layer in the plurality of cell rows may have substantially the same shape.

[0209] (10) Forming a fifth conductive layer pattern. In an exemplary embodiment, forming the fifth conductive layer may include: depositing a fifth conductive film on the substrate having the aforementioned pattern formed thereon, and patterning the fifth conductive film using a patterning process to form a fifth conductive layer disposed on the first flat layer, as shown in FIG16A and FIG16B , where FIG16B is a planar schematic diagram of the fifth conductive layer in FIG16A . In an exemplary embodiment, the fifth conductive layer may be referred to as a second source / drain metal (SD2) layer.

[0210] In an exemplary embodiment, the fifth conductive layer of each circuit unit includes at least an eleventh connecting electrode 61 , a twelfth connecting electrode 62 , a power connection line 63 , a first shielding electrode 64 , and a second shielding electrode 65 .

[0211] In an exemplary embodiment, the eleventh connection electrode 61 may be in the shape of a strip with a main portion extending along the second direction Y. The eleventh connection electrode 61 is connected to the third connection electrode 53 through the twenty-first via hole V21. The eleventh connection electrode 61 is configured to be connected to a subsequently formed data signal line.

[0212] In an exemplary embodiment, the shape of the twelfth connecting electrode 62 can be a strip shape with the main portion extending along the second direction Y. The twelfth connecting electrode 62 is connected to the sixth connecting electrode 56 through the twenty-third via hole V23. The twelfth connecting electrode 62 is configured to be connected to the subsequently formed anode connecting electrode.

[0213] In an exemplary embodiment, the power connection line 63 may be in the shape of a line with a main portion extending along the first direction X. The power connection line 63 is connected to the power connection block 54-1 of each circuit unit through the twenty-second via V22. Since the power connection line 63 is configured to connect to the first power line formed later, it can be reused as a horizontal power signal line. The power connection line 63 is connected to the fourth connection electrode 54 of each circuit unit. The fourth connection electrode 54 is respectively connected to the first region of the fifth active layer and the second plate 32 of the storage capacitor. The power connection line 63 can write the first power signal to all fifth transistors T5 and the second plates 32 of the storage capacitors in a cell row, ensuring that the second plates of multiple storage capacitors in a cell row have the same potential, which is beneficial for improving the uniformity of the panel, avoiding display defects on the display substrate, and ensuring the display quality of the display substrate.

[0214] In an exemplary embodiment, the first shielding electrode 64 and the second shielding electrode 65 may be block-shaped (e.g., rectangular) and connected to the power connection line 63. In an exemplary embodiment, the first shielding electrode 64 may be located on one side of the power connection line 63 in the second direction Y, and the second shielding electrode 65 may be located on the side of the power connection line 63 opposite to the second direction Y. The orthographic projections of the power connection line 63, the first shielding electrode 64, and the second shielding electrode 65 on the substrate at least partially overlap with the orthographic projection of the first connection electrode 51 on the substrate. Because the power connection line 63 is connected to the first power line formed later, the power connection line 63, the first shielding electrode 64, and the second shielding electrode 65, which have a constant potential, can effectively shield the first node N1 in the pixel driving circuit from the effects of data voltage jumps and other signals, thereby preventing the data voltage jumps and other signals from affecting the potential of the first node N1 and improving the driving performance of the pixel driving circuit.

[0215] In an exemplary embodiment, the orthographic projections of the power connection line 63 and the second shielding electrode 65 on the substrate at least partially overlap with the orthographic projection of the second active layer on the substrate, so that the power connection line 63 and the second shielding electrode 65 can block the second active layer, thereby blocking the light emitted by the light-emitting device and the light reflected by the film layer from irradiating the second transistor T2 of the oxide, preventing the characteristics of the oxide transistor from drifting due to light, and improving the electrical characteristics of the oxide transistor.

[0216] In an exemplary embodiment, in a unit row, the second shielding electrodes 65 in some two adjacent circuit units may be an integrated structure connected to each other, which can improve the shielding effect of shielding the second transistor T2.

[0217] In an exemplary embodiment, the fifth conductive layer may further include a first connection line 81. The first connection line 81 may be in the shape of a line with a main portion extending along the first direction X. The first connection line 81 is configured as a transverse trace among the data connection lines.

[0218] In an exemplary embodiment, the orthographic projection of the first connecting line 81 on the substrate at least partially overlaps with the orthographic projection of the first initial signal line 41 on the substrate, so that the first initial signal line 41 with a constant potential can effectively shield the influence of the voltage jump in the first connecting line 81 on the pixel driving circuit.

[0219] In an exemplary embodiment, the fifth conductive layers of adjacent cell columns may be mirror-symmetric with respect to the column boundary. For example, the fifth conductive layer of the Nth column and the fifth conductive layer of the N+1th column may be mirror-symmetric with respect to the column boundary, the fifth conductive layer of the N+1th column and the fifth conductive layer of the N+2th column may be mirror-symmetric with respect to the column boundary, and the fifth conductive layer of the N+2th column and the fifth conductive layer of the N+3th column may be mirror-symmetric with respect to the column boundary. In an exemplary embodiment, the shapes of the fifth conductive layers in multiple cell rows may be substantially the same.

[0220] (11) Forming a second planar layer pattern. In an exemplary embodiment, forming the second planar layer pattern may include: coating a second planar film on the substrate having the aforementioned pattern formed thereon, patterning the second planar film using a patterning process to form a second planar layer covering the fifth conductive layer pattern, wherein a plurality of vias are provided on the second planar layer, as shown in FIG. 17 .

[0221] In an exemplary embodiment, the plurality of vias in each circuit unit includes at least a thirty-first via V31 , a thirty-second via V32 , and a thirty-third via V33 .

[0222] In an exemplary embodiment, the orthographic projection of the thirty-first via hole V31 on the substrate is located within the range of the orthographic projection of the eleventh connecting electrode 61 on the substrate, the second flat layer in the thirty-first via hole V31 is etched away to expose the surface of the eleventh connecting electrode 61, and the thirty-first via hole V31 is configured to connect a subsequently formed data signal line to the eleventh connecting electrode 61 through the via hole.

[0223] In an exemplary embodiment, the orthographic projection of the thirty-second via V32 on the substrate is located within the range of the orthographic projection of the power connection line 63 on the substrate, the second flat layer within the thirty-second via V32 is etched away to expose the surface of the power connection line 63, and the thirty-second via V32 is configured to connect the subsequently formed first power line to the power connection line 63 through the via.

[0224] In an exemplary embodiment, the orthographic projection of the thirty-third via V33 on the substrate is located within the range of the orthographic projection of the twelfth connecting electrode 62 on the substrate, the second flat layer within the thirty-third via V33 is etched away to expose the surface of the twelfth connecting electrode 62, and the thirty-third via V33 is configured to connect the subsequently formed anode connecting electrode to the twelfth connecting electrode 62 through the via.

[0225] In an exemplary embodiment, the plurality of via holes on the second planar layer of adjacent cell columns may be mirror-symmetrical with respect to a column boundary line, and the plurality of via holes on the second planar layer in the plurality of cell rows may have substantially the same shape.

[0226] (12) Forming a sixth conductive layer pattern. In an exemplary embodiment, forming the sixth conductive layer may include: depositing a sixth conductive film on the substrate having the aforementioned pattern formed thereon, and patterning the sixth conductive film using a patterning process to form a sixth conductive layer disposed on the second flat layer, as shown in FIG18A and FIG18B , where FIG18A is a plan view schematic diagram of the sixth conductive layer in FIG18B . In an exemplary embodiment, the sixth conductive layer may be referred to as a third source / drain metal (SD3) layer.

[0227] In an exemplary embodiment, the sixth conductive layer of each circuit unit includes at least a first power line 71 , a data signal line 72 , and an anode connection electrode 73 .

[0228] In an exemplary embodiment, the first power line 71 may be shaped like a zigzag line with a main portion extending along the second direction Y. The first power line 71 is connected to the power connection line 63 through the thirty-second via hole V32. Since the power connection line 63 is connected to the fourth connection electrode 54, and the fourth connection electrode 54 is respectively connected to the first region of the fifth active layer and the second plate 32 of the storage capacitor, the first power line 71 can write the first power signal to the fifth transistor T5 and the second plate 32 of the storage capacitor.

[0229] In an exemplary embodiment, the first power line 71 may be a zigzag line with unequal width, which not only facilitates the layout of the pixel structure but also reduces the parasitic capacitance between the first power line and the data signal line.

[0230] In an exemplary embodiment, the first power line 71 may be connected to an anode spacer 74, which may be disposed on one side of the first direction X of the first power line 71 or on the side opposite to the first direction X. The orthographic projection of the anode spacer 74 on the substrate at least partially overlaps with the orthographic projection of the second shielding electrode 65 on the substrate, and the anode spacer 74 is configured to improve the flatness of the anode layer.

[0231] In an exemplary embodiment, the spacers 74 in some adjacent circuit cells within a cell row may be interconnected as a single unit. For example, the spacers 74 in the Nth column and the spacers 74 in the N+1th column are interconnected, thereby interconnecting the first power lines 71 in the two circuit cells. For another example, the spacers 74 in the N+2th column and the spacers 74 in the N+3th column are interconnected, thereby interconnecting the first power lines 71 in the two circuit cells.

[0232] In an exemplary embodiment, the first power line 71 is connected to the power connection line 63, thereby realizing the mutual connection between the power connection line 63 extending in the first direction X of the main body and the first power line 71 extending in the second direction Y of the main body. The first power line 71 and the power connection line 63 form a grid connection structure for transmitting the first power signal on the display substrate. This can not only effectively reduce the first power line and reduce the voltage drop of the first power signal, but also effectively improve the uniformity of the first power signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display quality.

[0233] In an exemplary embodiment, the data signal line 72 may be in the shape of a line having a main portion extending along the second direction Y. The data signal line 72 is connected to the eleventh connection electrode 61 through the thirty-first via hole V31. Since the eleventh connection electrode 61 is connected to the third connection electrode 53 through the via hole, and the third connection electrode 53 is connected to the first region of the fourth active layer through the via hole, the data signal line 72 is connected to the first electrode of the fourth transistor T4. The data signal line 72 can write a data signal to the first electrode of the fourth transistor T4.

[0234] In an exemplary embodiment, since the data signal line is arranged in the third source-drain metal (SD3) layer and is separated from the corresponding signal line by the thicker first and second planar layers, the distance between the data signal line and the corresponding signal line is increased, and the parasitic capacitance between the data signal line and the corresponding signal line is reduced, thereby effectively reducing the capacitive load of the data signal line.

[0235] In an exemplary embodiment, the anode connection electrode 73 may be in a block shape (e.g., a rectangular shape). The anode connection electrode 73 is connected to the twelfth connection electrode 62 via a thirty-third via hole V33. The anode connection electrode 73 is configured to be connected to a subsequently formed anode. Since the twelfth connection electrode 62 is connected to the sixth connection electrode 56 via the via hole, and the sixth connection electrode 56 is connected to the second region of the sixth active layer and the second region of the seventh active layer via the via hole, the subsequently formed anode can be connected to the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7, and the pixel driving circuit can drive the light-emitting device to emit light.

[0236] In an exemplary embodiment, the sixth conductive layer may further include a second connection line 82. The second connection line 82 may be in the shape of a line with a main portion extending along the second direction Y, and may be located in the gap between the pixel driving circuits of some adjacent unit columns. For example, the second connection line 82 may be located between the pixel driving circuit of the N-1 column and the pixel driving circuit of the N column. For another example, the second connection line 82 may be located between the pixel driving circuit of the N+1 column and the pixel driving circuit of the N+2 column. For another example, the second connection line 82 may be located between the pixel driving circuit of the N+3 column and the pixel driving circuit of the N+4 column.

[0237] In an exemplary embodiment, at least one second connection line 82 may be disposed between two data signal lines 72 of adjacent cell columns, and two data signal lines 72 located on both sides of the second connection line 82 may be mirror-symmetrical with respect to the second connection line 82 .

[0238] In an exemplary embodiment, one second connection line 82 and two data signal lines 72 may be disposed between two first power lines 71 of adjacent cell columns, and the two first power lines 71 may be mirror-symmetrical with respect to the second connection line 82 .

[0239] In an exemplary embodiment, in at least one circuit unit, the second connection line 82 can be connected to the first connection line 81 through a via, and in at least another circuit unit, the data signal line 72 can be connected to the first connection line 81 through a via, thereby realizing the sequential connection of the second connection line 82, the first connection line 81 and the data signal line 72, and the data signal of the binding area can be transmitted to the data signal line 72 through the second connection line 82 and the first connection line 81.

[0240] In an exemplary embodiment, since the second connecting line is arranged in the third source-drain metal (SD3) layer and is separated from the corresponding signal line by the thicker first flat layer and the second flat layer, the distance between the second connecting line and the corresponding signal line is increased, and the parasitic capacitance between the second connecting line and the corresponding signal line is reduced, thereby effectively reducing the capacitive load of the second connecting line.

[0241] In an exemplary embodiment, since the first connecting line is arranged in the second source-drain metal (SD2) layer and the second connecting line is arranged in the third source-drain metal (SD3) layer, the first connecting line and the second connecting line only need one flat layer via to be connected, thereby minimizing the occupied space and facilitating the realization of high-resolution display.

[0242] In an exemplary embodiment, the first power lines 71 and data signal lines 72 of adjacent cell columns may be mirror-symmetric with respect to the column boundary. For example, the first power lines 71 and data signal lines 72 of the Nth and N+1th columns may be mirror-symmetric with respect to the column boundary, and the first power lines 71 and data signal lines 72 of the N+1 and N+2 columns may be mirror-symmetric with respect to the column boundary. The first power lines 71 and data signal lines 72 of the N+2 and N+3 columns may be mirror-symmetric with respect to the column boundary. In an exemplary embodiment, the shapes of the first power lines 71 and data signal lines 72 in multiple cell rows may be substantially the same.

[0243] In an exemplary embodiment, the position and shape of the anode connecting electrode 73 in the Mth row and Nth column may be substantially the same as the position and shape of the anode connecting electrode 73 in the M+1th row and N+2 column, the position and shape of the anode connecting electrode 73 in the M+1th row and N+3 column may be substantially the same as the position and shape of the anode connecting electrode 73 in the M+1th row and N+2 column, the position and shape of the anode connecting electrode 73 in the M+1th row and N column may be substantially the same as the position and shape of the anode connecting electrode 73 in the M+1th row and N+3 column, and the position and shape of the anode connecting electrode 73 in the M+1th row and N+1 column may be substantially the same as the position and shape of the anode connecting electrode 73 in the M+1th row and N+1 column.

[0244] (13) Forming a third planar layer pattern. In an exemplary embodiment, forming the third planar layer pattern may include: coating a third planar film on the substrate having the aforementioned pattern formed thereon, patterning the third planar film using a patterning process to form a third planar layer covering the sixth conductive layer pattern, wherein a plurality of anode vias V40 are provided on the third planar layer, as shown in FIG. 19 .

[0245] In an exemplary embodiment, the orthographic projection of the anode via V40 of each circuit unit on the substrate is located within the range of the orthographic projection of the anode connecting electrode 73 on the substrate, the third flat layer in the anode via V40 is removed to expose the surface of the anode connecting electrode 73, and the anode via V40 is configured to connect a subsequently formed anode to the anode connecting electrode 73 through the via.

[0246] At this point, the driving circuit layer is prepared on the substrate. In a plane parallel to the display substrate, the driving circuit layer may include a plurality of circuit units, each circuit unit may include a pixel driving circuit, and a first scanning signal line, a second scanning signal line, a third scanning signal line, a fourth scanning signal line, a light-emitting signal line, a data signal line, a first power line, a first initial signal line, a second initial signal line, and a third initial signal line connected to the pixel driving circuit. In a plane perpendicular to the display substrate, the driving circuit layer may include a shielding layer, a first insulating layer, a first semiconductor layer, a second insulating layer, a first conductive layer, a third insulating layer, a second conductive layer, a fourth insulating layer, a second semiconductor layer, a fifth insulating layer, a third conductive layer, a sixth insulating layer, a fourth conductive layer, a first flat layer, a fifth conductive layer, a second flat layer, a sixth conductive layer, and a third flat layer sequentially arranged on the substrate. The blocking layer may include at least a blocking electrode, the first semiconductor layer may include at least the active layers of the first transistor, the third transistor to the seventh transistor, the first conductive layer may include at least the first scanning signal line, the second scanning signal line, the third scanning signal line, the light-emitting signal line and the first plate of the storage capacitor, the second conductive layer may include at least the blocking line and the second plate of the storage capacitor, the second semiconductor layer may include at least the active layer of the second transistor, the third conductive layer may include at least the first initial signal line, the second initial signal line, the third initial signal line and the fourth scanning signal line, the fourth conductive layer may include at least a plurality of connecting electrodes, the fifth conductive layer may include at least the power connection line and the first connection line, and the sixth conductive layer may include at least the first power line, the data signal line, the anode connection electrode and the second connection line.

[0247] In an exemplary embodiment, the substrate may be a flexible substrate or a rigid substrate. The rigid substrate may include, but is not limited to, one or more of glass and quartz, and the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers. In an exemplary embodiment, the flexible substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked. The materials of the first and second flexible material layers may be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film, and the materials of the first and second inorganic material layers may be silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the substrate's resistance to water and oxygen. The first and second inorganic material layers are also referred to as barrier layers, and the material of the semiconductor layer may be amorphous silicon (a-Si).

[0248] In an exemplary embodiment, the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer, the fifth conductive layer, and the sixth conductive layer can be made of a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and can be a single layer structure or a multi-layer composite structure, such as Mo / Cu / Mo. The first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, the fifth insulating layer, and the sixth insulating layer can be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and can be a single layer, a multi-layer, or a composite layer. The first planarizing layer, the second planarizing layer, and the third planarizing layer can be made of an organic material, such as a resin.

[0249] In an exemplary embodiment, the pixel driving circuits in two adjacent circuit units in a unit row may be substantially mirror-symmetrical with respect to a column boundary, where the column boundary is a straight line located between the two adjacent circuit units and extending along the second direction Y. For example, the pixel driving circuit in the Nth column and the pixel driving circuit in the N+1th column may be mirror-symmetrical with respect to the column boundary. For another example, the pixel driving circuit in the N+1th column and the pixel driving circuit in the N+2th column may be mirror-symmetrical with respect to the column boundary.

[0250] In an exemplary embodiment, the pixel driving circuits in two adjacent circuit units may be substantially mirror-symmetrical with respect to the column dividing line and may include any one or more of the following: the first semiconductor layer in two adjacent circuit units in a unit row may be mirror-symmetrical with respect to the column dividing line, the first conductive layer in two adjacent circuit units in a unit row may be mirror-symmetrical with respect to the column dividing line, the second conductive layer in two adjacent circuit units in a unit row may be mirror-symmetrical with respect to the column dividing line, the second semiconductor layer in two adjacent circuit units in a unit row may be mirror-symmetrical with respect to the column dividing line, the third conductive layer in two adjacent circuit units in a unit row may be mirror-symmetrical with respect to the column dividing line, the fourth conductive layer in two adjacent circuit units in a unit row may be mirror-symmetrical with respect to the column dividing line, the fifth conductive layer in two adjacent circuit units in a unit row may be mirror-symmetrical with respect to the column dividing line, and the sixth conductive layer (excluding the anode connecting electrode) in two adjacent circuit units in a unit row may be mirror-symmetrical with respect to the column dividing line.

[0251] In an exemplary embodiment, after the driving circuit layer is prepared, a light emitting structure layer is prepared on the driving circuit layer. The preparation process of the light emitting structure layer may include the following operations.

[0252] (14) Forming an anode conductive layer pattern. In an exemplary embodiment, forming the anode conductive layer pattern may include: depositing an anode conductive film on the substrate on which the aforementioned pattern is formed, and patterning the anode conductive film using a patterning process to form an anode conductive layer disposed on the third flat layer, wherein the anode conductive layer includes at least a plurality of anode patterns, as shown in FIG. 20 .

[0253] In an exemplary embodiment, the anode conductive layer may have a single-layer structure, such as indium tin oxide (ITO) or indium zinc oxide (IZO), or may have a multi-layer composite structure, such as ITO / Ag / ITO.

[0254] In an exemplary embodiment, the plurality of anode patterns may include a first anode 90A located at a red light emitting unit emitting red light, a second anode 90B located at a blue light emitting unit emitting blue light, a third anode 90C located at a first green light emitting unit emitting green light, and a fourth anode 90D located at a second green light emitting unit emitting green light.

[0255] In an exemplary embodiment, the first anode 90A, the second anode 90B, the third anode 90C, and the fourth anode 90D may be connected to the anode connection electrode 73 of the circuit unit through the anode via V40 , respectively.

[0256] In an exemplary embodiment, at least one of the first anode 90A, the second anode 90B, the third anode 90C and the fourth anode 90D may include an anode main body and an anode connecting portion that are connected to each other, the shape of the anode main body may be a diamond shape, the rectangular corners may be provided with arc-shaped chamfers, the shape of the anode connecting portion may be a strip shape, the first end of the anode connecting portion is connected to the anode main body, and the second end of the anode connecting portion extends in a direction away from the anode main body and is connected to the anode connecting electrode 73 through the anode via V40.

[0257] In an exemplary embodiment, orthographic projections of the first and second anodes 90A and 90B on the substrate at least partially overlap with orthographic projections of the power connection line 63 , the first connection line 81 , the first power line 71 , the data signal line 72 , and the second connection line 82 on the substrate.

[0258] In an exemplary embodiment, the orthographic projections of the third anode 90C and the fourth anode 90D on the substrate at least partially overlap with the orthographic projection of the anode spacer 74 on the substrate.

[0259] (15) Forming a pixel definition layer pattern. In an exemplary embodiment, forming the pixel definition layer pattern may include: coating a pixel definition film on the substrate on which the aforementioned pattern is formed, patterning the pixel definition film using a patterning process to form a pixel definition layer pattern covering the anode conductive layer pattern, wherein a plurality of pixel openings are provided on the pixel definition layer, as shown in FIG. 21 .

[0260] In an exemplary embodiment, the plurality of pixel openings may include a first pixel opening 100A located in a red light emitting unit emitting red light, a second pixel opening 100B located in a blue light emitting unit emitting blue light, a third pixel opening 100C located in a first green light emitting unit emitting green light, and a fourth pixel opening 100D located in a second green light emitting unit emitting green light, and the pixel definition films within the first pixel opening 100A, the second pixel opening 100B, the third pixel opening 100C, and the fourth pixel opening 100D are removed to expose the surfaces of the first anode 90A, the second anode 90B, the third anode 90C, and the fourth anode 90D, respectively.

[0261] FIG22 is a schematic diagram illustrating the positional relationship between pixel openings and signal lines of the present disclosure. As shown in FIG22 , in an exemplary embodiment, the orthographic projections of the first pixel opening 100A, the second pixel opening 100B, the third pixel opening 100C, and the fourth pixel opening 100D on the substrate at least partially overlap with the orthographic projection of at least one signal line on the substrate.

[0262] In an exemplary embodiment, orthographic projections of the first pixel opening 100A and the second pixel opening 100B on the substrate at least partially overlap with orthographic projections of the plurality of signal lines extending along the second direction Y on the substrate. In an exemplary embodiment, the plurality of signal lines may include two first power lines 71, two data signal lines 72, and one second connection line 82. The two data signal lines 72 may be located on either side of the second connection line 82 in the first direction X, and the two first power lines 71 may be located on either side of the two data signal lines 72 in the first direction X, respectively.

[0263] In an exemplary embodiment, the orthographic projection of the second connection line 82 on the substrate at least partially overlaps with the orthographic projection of the geometric center of the first pixel opening 100A and the geometric center of the second pixel opening 100B on the substrate. Because the two data signal lines 72 on either side of the second connection line 82 are mirror-symmetrical with respect to the second connection line 82, and the two first power lines 71 on the side of the data signal line 72 away from the second connection line 82 are mirror-symmetrical with respect to the second connection line 82, in the first direction X, the first anode 90A exposed by the first pixel opening 100A and the second anode 90B exposed by the second pixel opening 100B are ensured to have both good flatness and good flatness symmetry, effectively improving color shift and enhancing display quality.

[0264] In an exemplary embodiment, the orthographic projections of the first pixel opening 100A and the second pixel opening 100B on the substrate at least partially overlap with the orthographic projections of at least two signal lines extending along the first direction X. In an exemplary embodiment, the at least two signal lines may include a power connection line 63 and a first connection line 81. For the first pixel opening 100A, the power connection line 63 and the first connection line 81 may be located on either side of the geometric center of the first pixel opening 100A in the second direction Y. For the second pixel opening 100B, the power connection line 63 and the first connection line 81 may be located on either side of the geometric center of the second pixel opening 100B in the second direction Y.

[0265] In an exemplary embodiment, the power connection line 63 and the first connection line 81 may be symmetrically arranged relative to the center line of the pixel opening. For example, for the first pixel opening 100A, the power connection line 63 and the first connection line 81 may be symmetrically arranged relative to the center line of the first pixel opening 100A, where the center line of the first pixel opening 100A is a straight line extending along the first direction X and passing through the geometric center of the first pixel opening 100A. For another example, for the second pixel opening 100B, the power connection line 63 and the first connection line 81 may be symmetrically arranged relative to the center line of the second pixel opening 100B, where the center line of the second pixel opening 100B is a straight line extending along the first direction X and passing through the geometric center of the second pixel opening 100B.

[0266] In an exemplary embodiment, in at least one of the first pixel opening 100A and the second pixel opening 100B, a distance between the power connection line 63 and one end of the pixel opening and a distance between the first connection line 81 and the other end of the pixel opening may be substantially the same.

[0267] In an exemplary embodiment, taking the second pixel opening 100B as an example, the second pixel opening 100B has a center line O, a first end portion A1 located on the side of the power connection line 63 away from the center line O, and a second end portion A2 located on the side of the first connection line 81 away from the center line O. The power connection line 63 has a first edge B1 on the side away from the center line O, and the first connection line 81 has a second edge B2 on the side away from the center line O. A first distance L1 is between the first end portion A1 and the first edge B1, and a second distance L2 is between the second end portion A2 and the second edge B2. The ratio of the first distance L1 to the second distance L2 can be approximately 0.9 to 1.1.

[0268] In an exemplary embodiment, the ratio of the first distance L1 to the second distance L2 can be approximately 1.0, thereby ensuring that in the second direction Y, the first anode 90A exposed by the first pixel opening 100A and the second anode 90B exposed by the second pixel opening 100B not only have good flatness but also have good flatness symmetry, which can effectively improve color deviation and enhance display quality.

[0269] In an exemplary embodiment, the orthographic projections of the third pixel opening 100C and the fourth pixel opening 100D on the substrate at least partially overlap with the orthographic projection of the anode spacer 74 on the substrate, the orthographic projections of the third pixel opening 100C and the fourth pixel opening 100D on the substrate do not overlap with the orthographic projections of the power connection line 63 and the first connection line 81 extending along the first direction X on the substrate, and the orthographic projections of the third pixel opening 100C and the fourth pixel opening 100D on the substrate do not overlap with the orthographic projections of the first power line 71, the data signal line 72, and the second connection line 82 extending along the second direction Y on the substrate.

[0270] In an exemplary embodiment, the orthographic projections of the third pixel opening 100C and the fourth pixel opening 100D on the substrate can each be located within the orthographic projection of the anode spacer 74 in the corresponding circuit unit on the substrate. Because the anode spacer 74 is disposed on the side of the second planar layer away from the substrate and exhibits excellent planarity, the third anode 90C exposed by the third pixel opening 100C and the fourth anode 90D exposed by the fourth pixel opening 100D both exhibit excellent planarity, effectively reducing color shift and improving display quality.

[0271] In an exemplary embodiment, the subsequent preparation process may include: first forming an organic light-emitting layer by an evaporation or inkjet printing process, then forming a cathode on the organic light-emitting layer, and then forming an encapsulation structure layer. The encapsulation structure layer may include a stacked first encapsulation layer, a second encapsulation layer, and a third encapsulation layer. The first encapsulation layer and the third encapsulation layer may be made of inorganic materials, and the second encapsulation layer may be made of organic materials. The second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer to ensure that external water vapor cannot enter the light-emitting structure layer.

[0272] Research has found that the main cause of color shift and other problems in existing display devices is poor anode flatness. The display substrate provided by the exemplary embodiments of the present disclosure, by disposing first connecting lines and power supply connecting lines extending along a first (transverse) direction on the second source / drain metal layer, and disposing second connecting lines, data signal lines, and first power supply lines extending along a second (vertical) direction on the third source / drain metal layer, ensures that the multiple transverse and longitudinal metal lines below the anode are substantially mirror-symmetrical relative to the center line. As a result, the anode exposed by the pixel opening has not only good flatness but also good flatness symmetry, effectively improving color shift and enhancing display quality.

[0273] Comparative tests show that for a conventional structure where the first and second pixel openings overlap a horizontal signal line, the flatness of the anode exposed by the first pixel opening is approximately 0.12, and the flatness of the anode exposed by the second pixel opening is approximately 0.36. For the disclosed structure where the first and second pixel openings overlap the power connection line and the first power line, the flatness of the anode exposed by the first pixel opening is approximately 0.05, and the flatness of the anode exposed by the second pixel opening is approximately 0.10. Therefore, the disclosed display substrate structure achieves excellent anode flatness, effectively improving color shift.

[0274] The present disclosure provides a power connection line extending along the first direction in the second source-drain metal layer, and provides a first power line extending along the second direction in the third source-drain metal layer, and the first power line is connected to the power connection line, so that the first power line and the power connection line form a mesh structure for transmitting the first power signal on the display substrate. This can not only effectively reduce the resistance of the power line and the voltage drop of the first power signal, and reduce the voltage drop of the first power signal by about 22% when the brightness is 500 nits, but also effectively improve the uniformity of the first power signal in the display substrate, effectively improve the display uniformity, and improve the display uniformity by about 3%, thereby improving the display quality and display quality.

[0275] The present disclosure arranges the first connecting line in the second source-drain metal layer and the second connecting line in the third source-drain metal layer. Thus, the first and second connecting lines only require a single flat layer via to connect, minimizing space usage and facilitating high-resolution display. While achieving a narrow bezel, the LTPO display substrate's PPI can be effectively improved. The present disclosure arranges the data signal line and the second connecting line in the third source-drain metal layer, increasing the distance between the data signal line and the second connecting line and the corresponding signal line, reducing the parasitic capacitance between the data signal line and the second connecting line and the corresponding signal line, thereby effectively reducing the capacitive load of the data signal line and the second connecting line. The present disclosure arranges a shielding electrode in the second source-drain metal layer. The shielding electrode can, on the one hand, block the light emitted by the light-emitting device and the light reflected by the film layer from reaching the oxide transistor, thereby preventing the oxide transistor from drifting due to light and improving its electrical characteristics. On the other hand, the shielding electrode can effectively shield the data voltage jump and other signals from affecting the first node in the pixel driver circuit, preventing the data voltage jump and other signals from affecting the potential of the first node and effectively preventing crosstalk from worsening. The preparation process disclosed in the present invention is well compatible with existing preparation processes, is simple to implement, easy to implement, has high production efficiency, low production cost, and high yield rate.

[0276] The structure and preparation process shown above in the present disclosure are merely exemplary. In exemplary embodiments, the corresponding structure can be changed and the patterning process can be increased or decreased according to actual needs, and the present disclosure does not limit this.

[0277] In an exemplary embodiment, the display substrate of the present disclosure may be applied to other display devices having a pixel driving circuit, such as a quantum dot display, etc., which is not limited in the present disclosure.

[0278] The present disclosure also provides a method for preparing a display substrate to produce the display substrate provided in the above embodiment. In an exemplary embodiment, the preparation method may include:

[0279] forming a driving structure layer on a substrate, wherein the driving structure layer includes a plurality of circuit units and at least two signal lines extending along a first direction, and at least one circuit unit includes a pixel driving circuit;

[0280] forming a light-emitting structure layer on the driving structure layer, the light-emitting structure layer including a plurality of light-emitting units, at least one of which includes an anode and a pixel definition layer disposed on a side of the anode away from the substrate, the anode being connected to a pixel driving circuit of a corresponding circuit unit, and the pixel definition layer being provided with a pixel opening exposing the anode;

[0281] The driving structure layer also includes at least two signal lines extending along a first direction. In at least one pixel opening, the positive projection of the pixel opening on the substrate at least partially overlaps with the positive projection of at least two signal lines on the substrate. The at least two signal lines are respectively located on both sides of the geometric center of the pixel opening in a second direction, and the first direction and the second direction intersect.

[0282] While the embodiments disclosed herein are as described above, it should be noted that the above embodiments are merely illustrative and not restrictive. Therefore, the present disclosure is not limited to what is specifically shown and described herein. Various modifications, substitutions, or omissions may be made to the forms and details of the embodiments without departing from the scope of the present disclosure.

Claims

1. A display substrate, comprising a driving structure layer arranged on a substrate and a light-emitting structure layer arranged on a side of the driving structure layer away from the substrate; the driving structure layer comprises a plurality of circuit units, at least one of which comprises a pixel driving circuit; the light-emitting structure layer comprises a plurality of light-emitting units, at least one of which comprises an anode and a pixel definition layer arranged on a side of the anode away from the substrate, the anode being connected to the pixel driving circuit of the corresponding circuit unit, and the pixel definition layer being provided with a pixel opening exposing the anode; the driving structure layer further comprises at least two signal lines extending along a first direction, in at least one pixel opening, the orthographic projection of the pixel opening on the substrate at least partially overlaps with the orthographic projection of at least two signal lines on the substrate, and at least two signal lines are respectively located on both sides of a second direction of a geometric center of the pixel opening, and the first direction intersects with the second direction.

2. The display substrate according to claim 1, wherein: The at least two signal lines include a first connection line and a power connection line, the power connection line is connected to the data signal line extending along the second direction, the power connection line is connected to the first power line extending along the second direction, and the data signal line and the first power line are connected to the pixel driving circuit; In at least one pixel opening, the first connection line and the power connection line are symmetrically arranged relative to a center line, and the center line is a straight line extending along the first direction and passing through the geometric center of the pixel opening.

3. The display substrate according to claim 2, wherein: In at least one pixel opening, the pixel opening includes a first end located on a side of the power connection line away from the center line and a second end located on a side of the first connection line away from the center line, the power connection line includes a first edge away from the center line, the first connection line includes a second edge away from the center line, the first end has a first distance from the first edge, the second end has a second distance from the second edge, and the ratio of the first distance to the second distance is 0.9 to 1.

1.

4. The display substrate according to claim 2, wherein: The driving structure layer also includes a second connecting line extending along the second direction, the second connecting line is connected to the first connecting line, and in at least one pixel opening, the orthographic projection of the second connecting line on the substrate at least partially overlaps with the orthographic projection of the geometric center of the pixel opening on the substrate.

5. The display substrate according to claim 4, wherein: The orthographic projection of the pixel opening on the substrate at least partially overlaps with the orthographic projections of two data signal lines on the substrate, the second connecting line is arranged between the two data signal lines, and the two data signal lines are symmetrically arranged relative to the second connecting line.

6. The display substrate according to claim 5, wherein: The orthographic projection of the pixel opening on the substrate at least partially overlaps with the orthographic projection of two first power lines on the substrate, the second connecting line and the two data signal lines are arranged between the two first power lines, and the two first power lines are symmetrically arranged relative to the second connecting line.

7. The display substrate according to any one of claims 1 to 6, wherein: The driving structure layer further includes a plurality of power connection lines extending along the first direction and a plurality of first power lines extending along the second direction. The power connection lines are connected to the first power lines to form a grid connection structure for transmitting a first power signal.

8. The display substrate according to claim 7, wherein: On a plane perpendicular to the display substrate, the driving structure layer includes a plurality of conductive layers sequentially arranged on the base, and the power connection line and the first power line are arranged in different conductive layers.

9. The display substrate according to claim 8, wherein: The at least two signal lines include a first connection line and the power connection line, and the power connection line and the first connection line are arranged in the same conductive layer.

10. The display substrate according to claim 9, wherein: The driving structure layer further includes a second connection line, the second connection line is connected to the first connection line, the first connection line is connected to a data signal line, and the data signal line, the first power line and the second connection line are arranged in the same conductive layer.

11. The display substrate according to any one of claims 1 to 6, wherein: The plurality of light-emitting units include a red light-emitting unit emitting red light, a blue light-emitting unit emitting blue light, a first green light-emitting unit emitting green light, and a second green light-emitting unit emitting green light, the red light-emitting unit at least includes a first anode and a first pixel opening exposing the first anode, the blue light-emitting unit at least includes a second anode and a second pixel opening exposing the second anode, the first green light-emitting unit at least includes a third anode and a third pixel opening exposing the third anode, and the second green light-emitting unit at least includes a fourth anode and a fourth pixel opening exposing the fourth anode; For at least one of the first pixel opening and the second pixel opening, the at least two signal lines are respectively located on both sides of the geometric center of the pixel opening in the second direction.

12. The display substrate according to claim 11, wherein: The driving structure layer further includes a plurality of anode spacers, and at least one of the third pixel opening and the fourth pixel opening, wherein an orthographic projection of the pixel opening on the substrate at least partially overlaps with an orthographic projection of the anode spacer on the substrate.

13. The display substrate according to claim 12, wherein: At least one of the third pixel opening and the fourth pixel opening has an orthographic projection on the substrate located within a range of an orthographic projection of the anode spacer on the substrate.

14. The display substrate according to claim 12, wherein: The driving structure layer further includes a first power line, and the anode pad is connected to the first power line.

15. The display substrate according to claim 14, wherein: On a plane perpendicular to the display substrate, the driving structure layer includes a plurality of conductive layers sequentially arranged on a base, and the anode pad and the first power line are arranged in the same conductive layer.

16. A display device comprising the display substrate according to any one of claims 1 to 15.

17. A method for preparing a display substrate, comprising: forming a driving structure layer on a substrate, wherein the driving structure layer comprises a plurality of circuit units and at least two signal lines extending along a first direction, and at least one circuit unit comprises a pixel driving circuit; forming a light-emitting structure layer on the driving structure layer, wherein the light-emitting structure layer comprises a plurality of light-emitting units, at least one of the light-emitting units comprises an anode and a pixel definition layer arranged on a side of the anode away from the substrate, the anode is connected to a pixel driving circuit of a corresponding circuit unit, and the pixel definition layer is provided with a pixel opening exposing the anode; The driving structure layer also includes at least two signal lines extending along a first direction. In at least one pixel opening, the orthographic projection of the pixel opening on the substrate at least partially overlaps with the orthographic projection of at least two signal lines on the substrate. At least two signal lines are respectively located on both sides of the second direction of the geometric center of the pixel opening, and the first direction and the second direction intersect.

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